clk-tegra114.c revision fd428ad87b1f4a12820de07ecb3a155c51c802c7
1/* 2 * Copyright (c) 2012, 2013, NVIDIA CORPORATION. All rights reserved. 3 * 4 * This program is free software; you can redistribute it and/or modify it 5 * under the terms and conditions of the GNU General Public License, 6 * version 2, as published by the Free Software Foundation. 7 * 8 * This program is distributed in the hope it will be useful, but WITHOUT 9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 11 * more details. 12 * 13 * You should have received a copy of the GNU General Public License 14 * along with this program. If not, see <http://www.gnu.org/licenses/>. 15 */ 16 17#include <linux/io.h> 18#include <linux/clk.h> 19#include <linux/clk-provider.h> 20#include <linux/clkdev.h> 21#include <linux/of.h> 22#include <linux/of_address.h> 23#include <linux/delay.h> 24#include <linux/clk/tegra.h> 25 26#include "clk.h" 27 28#define RST_DEVICES_L 0x004 29#define RST_DEVICES_H 0x008 30#define RST_DEVICES_U 0x00C 31#define RST_DEVICES_V 0x358 32#define RST_DEVICES_W 0x35C 33#define RST_DEVICES_X 0x28C 34#define RST_DEVICES_SET_L 0x300 35#define RST_DEVICES_CLR_L 0x304 36#define RST_DEVICES_SET_H 0x308 37#define RST_DEVICES_CLR_H 0x30c 38#define RST_DEVICES_SET_U 0x310 39#define RST_DEVICES_CLR_U 0x314 40#define RST_DEVICES_SET_V 0x430 41#define RST_DEVICES_CLR_V 0x434 42#define RST_DEVICES_SET_W 0x438 43#define RST_DEVICES_CLR_W 0x43c 44#define RST_DEVICES_NUM 5 45 46#define CLK_OUT_ENB_L 0x010 47#define CLK_OUT_ENB_H 0x014 48#define CLK_OUT_ENB_U 0x018 49#define CLK_OUT_ENB_V 0x360 50#define CLK_OUT_ENB_W 0x364 51#define CLK_OUT_ENB_X 0x280 52#define CLK_OUT_ENB_SET_L 0x320 53#define CLK_OUT_ENB_CLR_L 0x324 54#define CLK_OUT_ENB_SET_H 0x328 55#define CLK_OUT_ENB_CLR_H 0x32c 56#define CLK_OUT_ENB_SET_U 0x330 57#define CLK_OUT_ENB_CLR_U 0x334 58#define CLK_OUT_ENB_SET_V 0x440 59#define CLK_OUT_ENB_CLR_V 0x444 60#define CLK_OUT_ENB_SET_W 0x448 61#define CLK_OUT_ENB_CLR_W 0x44c 62#define CLK_OUT_ENB_SET_X 0x284 63#define CLK_OUT_ENB_CLR_X 0x288 64#define CLK_OUT_ENB_NUM 6 65 66#define PLLC_BASE 0x80 67#define PLLC_MISC2 0x88 68#define PLLC_MISC 0x8c 69#define PLLC2_BASE 0x4e8 70#define PLLC2_MISC 0x4ec 71#define PLLC3_BASE 0x4fc 72#define PLLC3_MISC 0x500 73#define PLLM_BASE 0x90 74#define PLLM_MISC 0x9c 75#define PLLP_BASE 0xa0 76#define PLLP_MISC 0xac 77#define PLLX_BASE 0xe0 78#define PLLX_MISC 0xe4 79#define PLLX_MISC2 0x514 80#define PLLX_MISC3 0x518 81#define PLLD_BASE 0xd0 82#define PLLD_MISC 0xdc 83#define PLLD2_BASE 0x4b8 84#define PLLD2_MISC 0x4bc 85#define PLLE_BASE 0xe8 86#define PLLE_MISC 0xec 87#define PLLA_BASE 0xb0 88#define PLLA_MISC 0xbc 89#define PLLU_BASE 0xc0 90#define PLLU_MISC 0xcc 91#define PLLRE_BASE 0x4c4 92#define PLLRE_MISC 0x4c8 93 94#define PLL_MISC_LOCK_ENABLE 18 95#define PLLC_MISC_LOCK_ENABLE 24 96#define PLLDU_MISC_LOCK_ENABLE 22 97#define PLLE_MISC_LOCK_ENABLE 9 98#define PLLRE_MISC_LOCK_ENABLE 30 99 100#define PLLC_IDDQ_BIT 26 101#define PLLX_IDDQ_BIT 3 102#define PLLRE_IDDQ_BIT 16 103 104#define PLL_BASE_LOCK BIT(27) 105#define PLLE_MISC_LOCK BIT(11) 106#define PLLRE_MISC_LOCK BIT(24) 107#define PLLCX_BASE_LOCK (BIT(26)|BIT(27)) 108 109#define PLLE_AUX 0x48c 110#define PLLC_OUT 0x84 111#define PLLM_OUT 0x94 112#define PLLP_OUTA 0xa4 113#define PLLP_OUTB 0xa8 114#define PLLA_OUT 0xb4 115 116#define AUDIO_SYNC_CLK_I2S0 0x4a0 117#define AUDIO_SYNC_CLK_I2S1 0x4a4 118#define AUDIO_SYNC_CLK_I2S2 0x4a8 119#define AUDIO_SYNC_CLK_I2S3 0x4ac 120#define AUDIO_SYNC_CLK_I2S4 0x4b0 121#define AUDIO_SYNC_CLK_SPDIF 0x4b4 122 123#define AUDIO_SYNC_DOUBLER 0x49c 124 125#define PMC_CLK_OUT_CNTRL 0x1a8 126#define PMC_DPD_PADS_ORIDE 0x1c 127#define PMC_DPD_PADS_ORIDE_BLINK_ENB 20 128#define PMC_CTRL 0 129#define PMC_CTRL_BLINK_ENB 7 130#define PMC_BLINK_TIMER 0x40 131 132#define OSC_CTRL 0x50 133#define OSC_CTRL_OSC_FREQ_SHIFT 28 134#define OSC_CTRL_PLL_REF_DIV_SHIFT 26 135 136#define PLLXC_SW_MAX_P 6 137 138#define CCLKG_BURST_POLICY 0x368 139#define CCLKLP_BURST_POLICY 0x370 140#define SCLK_BURST_POLICY 0x028 141#define SYSTEM_CLK_RATE 0x030 142 143#define UTMIP_PLL_CFG2 0x488 144#define UTMIP_PLL_CFG2_STABLE_COUNT(x) (((x) & 0xffff) << 6) 145#define UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(x) (((x) & 0x3f) << 18) 146#define UTMIP_PLL_CFG2_FORCE_PD_SAMP_A_POWERDOWN BIT(0) 147#define UTMIP_PLL_CFG2_FORCE_PD_SAMP_B_POWERDOWN BIT(2) 148#define UTMIP_PLL_CFG2_FORCE_PD_SAMP_C_POWERDOWN BIT(4) 149 150#define UTMIP_PLL_CFG1 0x484 151#define UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(x) (((x) & 0x1f) << 6) 152#define UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(x) (((x) & 0xfff) << 0) 153#define UTMIP_PLL_CFG1_FORCE_PLLU_POWERUP BIT(17) 154#define UTMIP_PLL_CFG1_FORCE_PLLU_POWERDOWN BIT(16) 155#define UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERUP BIT(15) 156#define UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN BIT(14) 157#define UTMIP_PLL_CFG1_FORCE_PLL_ACTIVE_POWERDOWN BIT(12) 158 159#define UTMIPLL_HW_PWRDN_CFG0 0x52c 160#define UTMIPLL_HW_PWRDN_CFG0_SEQ_START_STATE BIT(25) 161#define UTMIPLL_HW_PWRDN_CFG0_SEQ_ENABLE BIT(24) 162#define UTMIPLL_HW_PWRDN_CFG0_USE_LOCKDET BIT(6) 163#define UTMIPLL_HW_PWRDN_CFG0_SEQ_RESET_INPUT_VALUE BIT(5) 164#define UTMIPLL_HW_PWRDN_CFG0_SEQ_IN_SWCTL BIT(4) 165#define UTMIPLL_HW_PWRDN_CFG0_CLK_ENABLE_SWCTL BIT(2) 166#define UTMIPLL_HW_PWRDN_CFG0_IDDQ_OVERRIDE BIT(1) 167#define UTMIPLL_HW_PWRDN_CFG0_IDDQ_SWCTL BIT(0) 168 169#define CLK_SOURCE_I2S0 0x1d8 170#define CLK_SOURCE_I2S1 0x100 171#define CLK_SOURCE_I2S2 0x104 172#define CLK_SOURCE_NDFLASH 0x160 173#define CLK_SOURCE_I2S3 0x3bc 174#define CLK_SOURCE_I2S4 0x3c0 175#define CLK_SOURCE_SPDIF_OUT 0x108 176#define CLK_SOURCE_SPDIF_IN 0x10c 177#define CLK_SOURCE_PWM 0x110 178#define CLK_SOURCE_ADX 0x638 179#define CLK_SOURCE_AMX 0x63c 180#define CLK_SOURCE_HDA 0x428 181#define CLK_SOURCE_HDA2CODEC_2X 0x3e4 182#define CLK_SOURCE_SBC1 0x134 183#define CLK_SOURCE_SBC2 0x118 184#define CLK_SOURCE_SBC3 0x11c 185#define CLK_SOURCE_SBC4 0x1b4 186#define CLK_SOURCE_SBC5 0x3c8 187#define CLK_SOURCE_SBC6 0x3cc 188#define CLK_SOURCE_SATA_OOB 0x420 189#define CLK_SOURCE_SATA 0x424 190#define CLK_SOURCE_NDSPEED 0x3f8 191#define CLK_SOURCE_VFIR 0x168 192#define CLK_SOURCE_SDMMC1 0x150 193#define CLK_SOURCE_SDMMC2 0x154 194#define CLK_SOURCE_SDMMC3 0x1bc 195#define CLK_SOURCE_SDMMC4 0x164 196#define CLK_SOURCE_VDE 0x1c8 197#define CLK_SOURCE_CSITE 0x1d4 198#define CLK_SOURCE_LA 0x1f8 199#define CLK_SOURCE_TRACE 0x634 200#define CLK_SOURCE_OWR 0x1cc 201#define CLK_SOURCE_NOR 0x1d0 202#define CLK_SOURCE_MIPI 0x174 203#define CLK_SOURCE_I2C1 0x124 204#define CLK_SOURCE_I2C2 0x198 205#define CLK_SOURCE_I2C3 0x1b8 206#define CLK_SOURCE_I2C4 0x3c4 207#define CLK_SOURCE_I2C5 0x128 208#define CLK_SOURCE_UARTA 0x178 209#define CLK_SOURCE_UARTB 0x17c 210#define CLK_SOURCE_UARTC 0x1a0 211#define CLK_SOURCE_UARTD 0x1c0 212#define CLK_SOURCE_UARTE 0x1c4 213#define CLK_SOURCE_UARTA_DBG 0x178 214#define CLK_SOURCE_UARTB_DBG 0x17c 215#define CLK_SOURCE_UARTC_DBG 0x1a0 216#define CLK_SOURCE_UARTD_DBG 0x1c0 217#define CLK_SOURCE_UARTE_DBG 0x1c4 218#define CLK_SOURCE_3D 0x158 219#define CLK_SOURCE_2D 0x15c 220#define CLK_SOURCE_VI_SENSOR 0x1a8 221#define CLK_SOURCE_VI 0x148 222#define CLK_SOURCE_EPP 0x16c 223#define CLK_SOURCE_MSENC 0x1f0 224#define CLK_SOURCE_TSEC 0x1f4 225#define CLK_SOURCE_HOST1X 0x180 226#define CLK_SOURCE_HDMI 0x18c 227#define CLK_SOURCE_DISP1 0x138 228#define CLK_SOURCE_DISP2 0x13c 229#define CLK_SOURCE_CILAB 0x614 230#define CLK_SOURCE_CILCD 0x618 231#define CLK_SOURCE_CILE 0x61c 232#define CLK_SOURCE_DSIALP 0x620 233#define CLK_SOURCE_DSIBLP 0x624 234#define CLK_SOURCE_TSENSOR 0x3b8 235#define CLK_SOURCE_D_AUDIO 0x3d0 236#define CLK_SOURCE_DAM0 0x3d8 237#define CLK_SOURCE_DAM1 0x3dc 238#define CLK_SOURCE_DAM2 0x3e0 239#define CLK_SOURCE_ACTMON 0x3e8 240#define CLK_SOURCE_EXTERN1 0x3ec 241#define CLK_SOURCE_EXTERN2 0x3f0 242#define CLK_SOURCE_EXTERN3 0x3f4 243#define CLK_SOURCE_I2CSLOW 0x3fc 244#define CLK_SOURCE_SE 0x42c 245#define CLK_SOURCE_MSELECT 0x3b4 246#define CLK_SOURCE_SOC_THERM 0x644 247#define CLK_SOURCE_XUSB_HOST_SRC 0x600 248#define CLK_SOURCE_XUSB_FALCON_SRC 0x604 249#define CLK_SOURCE_XUSB_FS_SRC 0x608 250#define CLK_SOURCE_XUSB_SS_SRC 0x610 251#define CLK_SOURCE_XUSB_DEV_SRC 0x60c 252#define CLK_SOURCE_EMC 0x19c 253 254static int periph_clk_enb_refcnt[CLK_OUT_ENB_NUM * 32]; 255 256static void __iomem *clk_base; 257static void __iomem *pmc_base; 258 259static DEFINE_SPINLOCK(pll_d_lock); 260static DEFINE_SPINLOCK(pll_d2_lock); 261static DEFINE_SPINLOCK(pll_u_lock); 262static DEFINE_SPINLOCK(pll_div_lock); 263static DEFINE_SPINLOCK(pll_re_lock); 264static DEFINE_SPINLOCK(clk_doubler_lock); 265static DEFINE_SPINLOCK(clk_out_lock); 266static DEFINE_SPINLOCK(sysrate_lock); 267 268static struct div_nmp pllxc_nmp = { 269 .divm_shift = 0, 270 .divm_width = 8, 271 .divn_shift = 8, 272 .divn_width = 8, 273 .divp_shift = 20, 274 .divp_width = 4, 275}; 276 277static struct pdiv_map pllxc_p[] = { 278 { .pdiv = 1, .hw_val = 0 }, 279 { .pdiv = 2, .hw_val = 1 }, 280 { .pdiv = 3, .hw_val = 2 }, 281 { .pdiv = 4, .hw_val = 3 }, 282 { .pdiv = 5, .hw_val = 4 }, 283 { .pdiv = 6, .hw_val = 5 }, 284 { .pdiv = 8, .hw_val = 6 }, 285 { .pdiv = 10, .hw_val = 7 }, 286 { .pdiv = 12, .hw_val = 8 }, 287 { .pdiv = 16, .hw_val = 9 }, 288 { .pdiv = 12, .hw_val = 10 }, 289 { .pdiv = 16, .hw_val = 11 }, 290 { .pdiv = 20, .hw_val = 12 }, 291 { .pdiv = 24, .hw_val = 13 }, 292 { .pdiv = 32, .hw_val = 14 }, 293 { .pdiv = 0, .hw_val = 0 }, 294}; 295 296static struct tegra_clk_pll_freq_table pll_c_freq_table[] = { 297 { 12000000, 624000000, 104, 0, 2}, 298 { 12000000, 600000000, 100, 0, 2}, 299 { 13000000, 600000000, 92, 0, 2}, /* actual: 598.0 MHz */ 300 { 16800000, 600000000, 71, 0, 2}, /* actual: 596.4 MHz */ 301 { 19200000, 600000000, 62, 0, 2}, /* actual: 595.2 MHz */ 302 { 26000000, 600000000, 92, 1, 2}, /* actual: 598.0 MHz */ 303 { 0, 0, 0, 0, 0, 0 }, 304}; 305 306static struct tegra_clk_pll_params pll_c_params = { 307 .input_min = 12000000, 308 .input_max = 800000000, 309 .cf_min = 12000000, 310 .cf_max = 19200000, /* s/w policy, h/w capability 50 MHz */ 311 .vco_min = 600000000, 312 .vco_max = 1400000000, 313 .base_reg = PLLC_BASE, 314 .misc_reg = PLLC_MISC, 315 .lock_mask = PLL_BASE_LOCK, 316 .lock_enable_bit_idx = PLLC_MISC_LOCK_ENABLE, 317 .lock_delay = 300, 318 .iddq_reg = PLLC_MISC, 319 .iddq_bit_idx = PLLC_IDDQ_BIT, 320 .max_p = PLLXC_SW_MAX_P, 321 .dyn_ramp_reg = PLLC_MISC2, 322 .stepa_shift = 17, 323 .stepb_shift = 9, 324 .pdiv_tohw = pllxc_p, 325 .div_nmp = &pllxc_nmp, 326}; 327 328static struct div_nmp pllcx_nmp = { 329 .divm_shift = 0, 330 .divm_width = 2, 331 .divn_shift = 8, 332 .divn_width = 8, 333 .divp_shift = 20, 334 .divp_width = 3, 335}; 336 337static struct pdiv_map pllc_p[] = { 338 { .pdiv = 1, .hw_val = 0 }, 339 { .pdiv = 2, .hw_val = 1 }, 340 { .pdiv = 4, .hw_val = 3 }, 341 { .pdiv = 8, .hw_val = 5 }, 342 { .pdiv = 16, .hw_val = 7 }, 343 { .pdiv = 0, .hw_val = 0 }, 344}; 345 346static struct tegra_clk_pll_freq_table pll_cx_freq_table[] = { 347 {12000000, 600000000, 100, 0, 2}, 348 {13000000, 600000000, 92, 0, 2}, /* actual: 598.0 MHz */ 349 {16800000, 600000000, 71, 0, 2}, /* actual: 596.4 MHz */ 350 {19200000, 600000000, 62, 0, 2}, /* actual: 595.2 MHz */ 351 {26000000, 600000000, 92, 1, 2}, /* actual: 598.0 MHz */ 352 {0, 0, 0, 0, 0, 0}, 353}; 354 355static struct tegra_clk_pll_params pll_c2_params = { 356 .input_min = 12000000, 357 .input_max = 48000000, 358 .cf_min = 12000000, 359 .cf_max = 19200000, 360 .vco_min = 600000000, 361 .vco_max = 1200000000, 362 .base_reg = PLLC2_BASE, 363 .misc_reg = PLLC2_MISC, 364 .lock_mask = PLL_BASE_LOCK, 365 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE, 366 .lock_delay = 300, 367 .pdiv_tohw = pllc_p, 368 .div_nmp = &pllcx_nmp, 369 .max_p = 7, 370 .ext_misc_reg[0] = 0x4f0, 371 .ext_misc_reg[1] = 0x4f4, 372 .ext_misc_reg[2] = 0x4f8, 373}; 374 375static struct tegra_clk_pll_params pll_c3_params = { 376 .input_min = 12000000, 377 .input_max = 48000000, 378 .cf_min = 12000000, 379 .cf_max = 19200000, 380 .vco_min = 600000000, 381 .vco_max = 1200000000, 382 .base_reg = PLLC3_BASE, 383 .misc_reg = PLLC3_MISC, 384 .lock_mask = PLL_BASE_LOCK, 385 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE, 386 .lock_delay = 300, 387 .pdiv_tohw = pllc_p, 388 .div_nmp = &pllcx_nmp, 389 .max_p = 7, 390 .ext_misc_reg[0] = 0x504, 391 .ext_misc_reg[1] = 0x508, 392 .ext_misc_reg[2] = 0x50c, 393}; 394 395static struct div_nmp pllm_nmp = { 396 .divm_shift = 0, 397 .divm_width = 8, 398 .divn_shift = 8, 399 .divn_width = 8, 400 .divp_shift = 20, 401 .divp_width = 1, 402}; 403 404static struct pdiv_map pllm_p[] = { 405 { .pdiv = 1, .hw_val = 0 }, 406 { .pdiv = 2, .hw_val = 1 }, 407 { .pdiv = 0, .hw_val = 0 }, 408}; 409 410static struct tegra_clk_pll_freq_table pll_m_freq_table[] = { 411 {12000000, 800000000, 66, 0, 1}, /* actual: 792.0 MHz */ 412 {13000000, 800000000, 61, 0, 1}, /* actual: 793.0 MHz */ 413 {16800000, 800000000, 47, 0, 1}, /* actual: 789.6 MHz */ 414 {19200000, 800000000, 41, 0, 1}, /* actual: 787.2 MHz */ 415 {26000000, 800000000, 61, 1, 1}, /* actual: 793.0 MHz */ 416 {0, 0, 0, 0, 0, 0}, 417}; 418 419static struct tegra_clk_pll_params pll_m_params = { 420 .input_min = 12000000, 421 .input_max = 500000000, 422 .cf_min = 12000000, 423 .cf_max = 19200000, /* s/w policy, h/w capability 50 MHz */ 424 .vco_min = 400000000, 425 .vco_max = 1066000000, 426 .base_reg = PLLM_BASE, 427 .misc_reg = PLLM_MISC, 428 .lock_mask = PLL_BASE_LOCK, 429 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE, 430 .lock_delay = 300, 431 .max_p = 2, 432 .pdiv_tohw = pllm_p, 433 .div_nmp = &pllm_nmp, 434}; 435 436static struct div_nmp pllp_nmp = { 437 .divm_shift = 0, 438 .divm_width = 5, 439 .divn_shift = 8, 440 .divn_width = 10, 441 .divp_shift = 20, 442 .divp_width = 3, 443}; 444 445static struct tegra_clk_pll_freq_table pll_p_freq_table[] = { 446 {12000000, 216000000, 432, 12, 1, 8}, 447 {13000000, 216000000, 432, 13, 1, 8}, 448 {16800000, 216000000, 360, 14, 1, 8}, 449 {19200000, 216000000, 360, 16, 1, 8}, 450 {26000000, 216000000, 432, 26, 1, 8}, 451 {0, 0, 0, 0, 0, 0}, 452}; 453 454static struct tegra_clk_pll_params pll_p_params = { 455 .input_min = 2000000, 456 .input_max = 31000000, 457 .cf_min = 1000000, 458 .cf_max = 6000000, 459 .vco_min = 200000000, 460 .vco_max = 700000000, 461 .base_reg = PLLP_BASE, 462 .misc_reg = PLLP_MISC, 463 .lock_mask = PLL_BASE_LOCK, 464 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE, 465 .lock_delay = 300, 466 .div_nmp = &pllp_nmp, 467}; 468 469static struct tegra_clk_pll_freq_table pll_a_freq_table[] = { 470 {9600000, 282240000, 147, 5, 0, 4}, 471 {9600000, 368640000, 192, 5, 0, 4}, 472 {9600000, 240000000, 200, 8, 0, 8}, 473 474 {28800000, 282240000, 245, 25, 0, 8}, 475 {28800000, 368640000, 320, 25, 0, 8}, 476 {28800000, 240000000, 200, 24, 0, 8}, 477 {0, 0, 0, 0, 0, 0}, 478}; 479 480 481static struct tegra_clk_pll_params pll_a_params = { 482 .input_min = 2000000, 483 .input_max = 31000000, 484 .cf_min = 1000000, 485 .cf_max = 6000000, 486 .vco_min = 200000000, 487 .vco_max = 700000000, 488 .base_reg = PLLA_BASE, 489 .misc_reg = PLLA_MISC, 490 .lock_mask = PLL_BASE_LOCK, 491 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE, 492 .lock_delay = 300, 493 .div_nmp = &pllp_nmp, 494}; 495 496static struct tegra_clk_pll_freq_table pll_d_freq_table[] = { 497 {12000000, 216000000, 864, 12, 2, 12}, 498 {13000000, 216000000, 864, 13, 2, 12}, 499 {16800000, 216000000, 720, 14, 2, 12}, 500 {19200000, 216000000, 720, 16, 2, 12}, 501 {26000000, 216000000, 864, 26, 2, 12}, 502 503 {12000000, 594000000, 594, 12, 0, 12}, 504 {13000000, 594000000, 594, 13, 0, 12}, 505 {16800000, 594000000, 495, 14, 0, 12}, 506 {19200000, 594000000, 495, 16, 0, 12}, 507 {26000000, 594000000, 594, 26, 0, 12}, 508 509 {12000000, 1000000000, 1000, 12, 0, 12}, 510 {13000000, 1000000000, 1000, 13, 0, 12}, 511 {19200000, 1000000000, 625, 12, 0, 12}, 512 {26000000, 1000000000, 1000, 26, 0, 12}, 513 514 {0, 0, 0, 0, 0, 0}, 515}; 516 517static struct tegra_clk_pll_params pll_d_params = { 518 .input_min = 2000000, 519 .input_max = 40000000, 520 .cf_min = 1000000, 521 .cf_max = 6000000, 522 .vco_min = 500000000, 523 .vco_max = 1000000000, 524 .base_reg = PLLD_BASE, 525 .misc_reg = PLLD_MISC, 526 .lock_mask = PLL_BASE_LOCK, 527 .lock_enable_bit_idx = PLLDU_MISC_LOCK_ENABLE, 528 .lock_delay = 1000, 529 .div_nmp = &pllp_nmp, 530}; 531 532static struct tegra_clk_pll_params pll_d2_params = { 533 .input_min = 2000000, 534 .input_max = 40000000, 535 .cf_min = 1000000, 536 .cf_max = 6000000, 537 .vco_min = 500000000, 538 .vco_max = 1000000000, 539 .base_reg = PLLD2_BASE, 540 .misc_reg = PLLD2_MISC, 541 .lock_mask = PLL_BASE_LOCK, 542 .lock_enable_bit_idx = PLLDU_MISC_LOCK_ENABLE, 543 .lock_delay = 1000, 544 .div_nmp = &pllp_nmp, 545}; 546 547static struct pdiv_map pllu_p[] = { 548 { .pdiv = 1, .hw_val = 1 }, 549 { .pdiv = 2, .hw_val = 0 }, 550 { .pdiv = 0, .hw_val = 0 }, 551}; 552 553static struct div_nmp pllu_nmp = { 554 .divm_shift = 0, 555 .divm_width = 5, 556 .divn_shift = 8, 557 .divn_width = 10, 558 .divp_shift = 20, 559 .divp_width = 1, 560}; 561 562static struct tegra_clk_pll_freq_table pll_u_freq_table[] = { 563 {12000000, 480000000, 960, 12, 0, 12}, 564 {13000000, 480000000, 960, 13, 0, 12}, 565 {16800000, 480000000, 400, 7, 0, 5}, 566 {19200000, 480000000, 200, 4, 0, 3}, 567 {26000000, 480000000, 960, 26, 0, 12}, 568 {0, 0, 0, 0, 0, 0}, 569}; 570 571static struct tegra_clk_pll_params pll_u_params = { 572 .input_min = 2000000, 573 .input_max = 40000000, 574 .cf_min = 1000000, 575 .cf_max = 6000000, 576 .vco_min = 480000000, 577 .vco_max = 960000000, 578 .base_reg = PLLU_BASE, 579 .misc_reg = PLLU_MISC, 580 .lock_mask = PLL_BASE_LOCK, 581 .lock_enable_bit_idx = PLLDU_MISC_LOCK_ENABLE, 582 .lock_delay = 1000, 583 .pdiv_tohw = pllu_p, 584 .div_nmp = &pllu_nmp, 585}; 586 587static struct tegra_clk_pll_freq_table pll_x_freq_table[] = { 588 /* 1 GHz */ 589 {12000000, 1000000000, 83, 0, 1}, /* actual: 996.0 MHz */ 590 {13000000, 1000000000, 76, 0, 1}, /* actual: 988.0 MHz */ 591 {16800000, 1000000000, 59, 0, 1}, /* actual: 991.2 MHz */ 592 {19200000, 1000000000, 52, 0, 1}, /* actual: 998.4 MHz */ 593 {26000000, 1000000000, 76, 1, 1}, /* actual: 988.0 MHz */ 594 595 {0, 0, 0, 0, 0, 0}, 596}; 597 598static struct tegra_clk_pll_params pll_x_params = { 599 .input_min = 12000000, 600 .input_max = 800000000, 601 .cf_min = 12000000, 602 .cf_max = 19200000, /* s/w policy, h/w capability 50 MHz */ 603 .vco_min = 700000000, 604 .vco_max = 2400000000U, 605 .base_reg = PLLX_BASE, 606 .misc_reg = PLLX_MISC, 607 .lock_mask = PLL_BASE_LOCK, 608 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE, 609 .lock_delay = 300, 610 .iddq_reg = PLLX_MISC3, 611 .iddq_bit_idx = PLLX_IDDQ_BIT, 612 .max_p = PLLXC_SW_MAX_P, 613 .dyn_ramp_reg = PLLX_MISC2, 614 .stepa_shift = 16, 615 .stepb_shift = 24, 616 .pdiv_tohw = pllxc_p, 617 .div_nmp = &pllxc_nmp, 618}; 619 620static struct tegra_clk_pll_freq_table pll_e_freq_table[] = { 621 /* PLLE special case: use cpcon field to store cml divider value */ 622 {336000000, 100000000, 100, 21, 16, 11}, 623 {312000000, 100000000, 200, 26, 24, 13}, 624 {0, 0, 0, 0, 0, 0}, 625}; 626 627static struct div_nmp plle_nmp = { 628 .divm_shift = 0, 629 .divm_width = 8, 630 .divn_shift = 8, 631 .divn_width = 8, 632 .divp_shift = 24, 633 .divp_width = 4, 634}; 635 636static struct tegra_clk_pll_params pll_e_params = { 637 .input_min = 12000000, 638 .input_max = 1000000000, 639 .cf_min = 12000000, 640 .cf_max = 75000000, 641 .vco_min = 1600000000, 642 .vco_max = 2400000000U, 643 .base_reg = PLLE_BASE, 644 .misc_reg = PLLE_MISC, 645 .aux_reg = PLLE_AUX, 646 .lock_mask = PLLE_MISC_LOCK, 647 .lock_enable_bit_idx = PLLE_MISC_LOCK_ENABLE, 648 .lock_delay = 300, 649 .div_nmp = &plle_nmp, 650}; 651 652static struct div_nmp pllre_nmp = { 653 .divm_shift = 0, 654 .divm_width = 8, 655 .divn_shift = 8, 656 .divn_width = 8, 657 .divp_shift = 16, 658 .divp_width = 4, 659}; 660 661static struct tegra_clk_pll_params pll_re_vco_params = { 662 .input_min = 12000000, 663 .input_max = 1000000000, 664 .cf_min = 12000000, 665 .cf_max = 19200000, /* s/w policy, h/w capability 38 MHz */ 666 .vco_min = 300000000, 667 .vco_max = 600000000, 668 .base_reg = PLLRE_BASE, 669 .misc_reg = PLLRE_MISC, 670 .lock_mask = PLLRE_MISC_LOCK, 671 .lock_enable_bit_idx = PLLRE_MISC_LOCK_ENABLE, 672 .lock_delay = 300, 673 .iddq_reg = PLLRE_MISC, 674 .iddq_bit_idx = PLLRE_IDDQ_BIT, 675 .div_nmp = &pllre_nmp, 676}; 677 678/* Peripheral clock registers */ 679 680static struct tegra_clk_periph_regs periph_l_regs = { 681 .enb_reg = CLK_OUT_ENB_L, 682 .enb_set_reg = CLK_OUT_ENB_SET_L, 683 .enb_clr_reg = CLK_OUT_ENB_CLR_L, 684 .rst_reg = RST_DEVICES_L, 685 .rst_set_reg = RST_DEVICES_SET_L, 686 .rst_clr_reg = RST_DEVICES_CLR_L, 687}; 688 689static struct tegra_clk_periph_regs periph_h_regs = { 690 .enb_reg = CLK_OUT_ENB_H, 691 .enb_set_reg = CLK_OUT_ENB_SET_H, 692 .enb_clr_reg = CLK_OUT_ENB_CLR_H, 693 .rst_reg = RST_DEVICES_H, 694 .rst_set_reg = RST_DEVICES_SET_H, 695 .rst_clr_reg = RST_DEVICES_CLR_H, 696}; 697 698static struct tegra_clk_periph_regs periph_u_regs = { 699 .enb_reg = CLK_OUT_ENB_U, 700 .enb_set_reg = CLK_OUT_ENB_SET_U, 701 .enb_clr_reg = CLK_OUT_ENB_CLR_U, 702 .rst_reg = RST_DEVICES_U, 703 .rst_set_reg = RST_DEVICES_SET_U, 704 .rst_clr_reg = RST_DEVICES_CLR_U, 705}; 706 707static struct tegra_clk_periph_regs periph_v_regs = { 708 .enb_reg = CLK_OUT_ENB_V, 709 .enb_set_reg = CLK_OUT_ENB_SET_V, 710 .enb_clr_reg = CLK_OUT_ENB_CLR_V, 711 .rst_reg = RST_DEVICES_V, 712 .rst_set_reg = RST_DEVICES_SET_V, 713 .rst_clr_reg = RST_DEVICES_CLR_V, 714}; 715 716static struct tegra_clk_periph_regs periph_w_regs = { 717 .enb_reg = CLK_OUT_ENB_W, 718 .enb_set_reg = CLK_OUT_ENB_SET_W, 719 .enb_clr_reg = CLK_OUT_ENB_CLR_W, 720 .rst_reg = RST_DEVICES_W, 721 .rst_set_reg = RST_DEVICES_SET_W, 722 .rst_clr_reg = RST_DEVICES_CLR_W, 723}; 724 725/* possible OSC frequencies in Hz */ 726static unsigned long tegra114_input_freq[] = { 727 [0] = 13000000, 728 [1] = 16800000, 729 [4] = 19200000, 730 [5] = 38400000, 731 [8] = 12000000, 732 [9] = 48000000, 733 [12] = 260000000, 734}; 735 736#define MASK(x) (BIT(x) - 1) 737 738#define TEGRA_INIT_DATA_MUX(_name, _con_id, _dev_id, _parents, _offset, \ 739 _clk_num, _regs, _gate_flags, _clk_id) \ 740 TEGRA_INIT_DATA_TABLE(_name, _con_id, _dev_id, _parents, _offset,\ 741 30, MASK(2), 0, 0, 8, 1, 0, _regs, _clk_num, \ 742 periph_clk_enb_refcnt, _gate_flags, _clk_id, \ 743 _parents##_idx, 0) 744 745#define TEGRA_INIT_DATA_MUX_FLAGS(_name, _con_id, _dev_id, _parents, _offset,\ 746 _clk_num, _regs, _gate_flags, _clk_id, flags)\ 747 TEGRA_INIT_DATA_TABLE(_name, _con_id, _dev_id, _parents, _offset,\ 748 30, MASK(2), 0, 0, 8, 1, 0, _regs, _clk_num, \ 749 periph_clk_enb_refcnt, _gate_flags, _clk_id, \ 750 _parents##_idx, flags) 751 752#define TEGRA_INIT_DATA_MUX8(_name, _con_id, _dev_id, _parents, _offset, \ 753 _clk_num, _regs, _gate_flags, _clk_id) \ 754 TEGRA_INIT_DATA_TABLE(_name, _con_id, _dev_id, _parents, _offset,\ 755 29, MASK(3), 0, 0, 8, 1, 0, _regs, _clk_num, \ 756 periph_clk_enb_refcnt, _gate_flags, _clk_id, \ 757 _parents##_idx, 0) 758 759#define TEGRA_INIT_DATA_INT(_name, _con_id, _dev_id, _parents, _offset, \ 760 _clk_num, _regs, _gate_flags, _clk_id) \ 761 TEGRA_INIT_DATA_TABLE(_name, _con_id, _dev_id, _parents, _offset,\ 762 30, MASK(2), 0, 0, 8, 1, TEGRA_DIVIDER_INT, _regs,\ 763 _clk_num, periph_clk_enb_refcnt, _gate_flags, \ 764 _clk_id, _parents##_idx, 0) 765 766#define TEGRA_INIT_DATA_INT_FLAGS(_name, _con_id, _dev_id, _parents, _offset,\ 767 _clk_num, _regs, _gate_flags, _clk_id, flags)\ 768 TEGRA_INIT_DATA_TABLE(_name, _con_id, _dev_id, _parents, _offset,\ 769 30, MASK(2), 0, 0, 8, 1, TEGRA_DIVIDER_INT, _regs,\ 770 _clk_num, periph_clk_enb_refcnt, _gate_flags, \ 771 _clk_id, _parents##_idx, flags) 772 773#define TEGRA_INIT_DATA_INT8(_name, _con_id, _dev_id, _parents, _offset,\ 774 _clk_num, _regs, _gate_flags, _clk_id) \ 775 TEGRA_INIT_DATA_TABLE(_name, _con_id, _dev_id, _parents, _offset,\ 776 29, MASK(3), 0, 0, 8, 1, TEGRA_DIVIDER_INT, _regs,\ 777 _clk_num, periph_clk_enb_refcnt, _gate_flags, \ 778 _clk_id, _parents##_idx, 0) 779 780#define TEGRA_INIT_DATA_UART(_name, _con_id, _dev_id, _parents, _offset,\ 781 _clk_num, _regs, _clk_id) \ 782 TEGRA_INIT_DATA_TABLE(_name, _con_id, _dev_id, _parents, _offset,\ 783 30, MASK(2), 0, 0, 16, 1, TEGRA_DIVIDER_UART, _regs,\ 784 _clk_num, periph_clk_enb_refcnt, 0, _clk_id, \ 785 _parents##_idx, 0) 786 787#define TEGRA_INIT_DATA_I2C(_name, _con_id, _dev_id, _parents, _offset,\ 788 _clk_num, _regs, _clk_id) \ 789 TEGRA_INIT_DATA_TABLE(_name, _con_id, _dev_id, _parents, _offset,\ 790 30, MASK(2), 0, 0, 16, 0, 0, _regs, _clk_num, \ 791 periph_clk_enb_refcnt, 0, _clk_id, _parents##_idx, 0) 792 793#define TEGRA_INIT_DATA_NODIV(_name, _con_id, _dev_id, _parents, _offset, \ 794 _mux_shift, _mux_mask, _clk_num, _regs, \ 795 _gate_flags, _clk_id) \ 796 TEGRA_INIT_DATA_TABLE(_name, _con_id, _dev_id, _parents, _offset,\ 797 _mux_shift, _mux_mask, 0, 0, 0, 0, 0, _regs, \ 798 _clk_num, periph_clk_enb_refcnt, _gate_flags, \ 799 _clk_id, _parents##_idx, 0) 800 801#define TEGRA_INIT_DATA_XUSB(_name, _con_id, _dev_id, _parents, _offset, \ 802 _clk_num, _regs, _gate_flags, _clk_id) \ 803 TEGRA_INIT_DATA_TABLE(_name, _con_id, _dev_id, _parents, _offset, \ 804 29, MASK(3), 0, 0, 8, 1, TEGRA_DIVIDER_INT, _regs, \ 805 _clk_num, periph_clk_enb_refcnt, _gate_flags, \ 806 _clk_id, _parents##_idx, 0) 807 808#define TEGRA_INIT_DATA_AUDIO(_name, _con_id, _dev_id, _offset, _clk_num,\ 809 _regs, _gate_flags, _clk_id) \ 810 TEGRA_INIT_DATA_TABLE(_name, _con_id, _dev_id, mux_d_audio_clk, \ 811 _offset, 16, 0xE01F, 0, 0, 8, 1, 0, _regs, _clk_num, \ 812 periph_clk_enb_refcnt, _gate_flags , _clk_id, \ 813 mux_d_audio_clk_idx, 0) 814 815enum tegra114_clk { 816 rtc = 4, timer = 5, uarta = 6, sdmmc2 = 9, i2s1 = 11, i2c1 = 12, 817 ndflash = 13, sdmmc1 = 14, sdmmc4 = 15, pwm = 17, i2s2 = 18, epp = 19, 818 gr_2d = 21, usbd = 22, isp = 23, gr_3d = 24, disp2 = 26, disp1 = 27, 819 host1x = 28, vcp = 29, i2s0 = 30, apbdma = 34, kbc = 36, kfuse = 40, 820 sbc1 = 41, nor = 42, sbc2 = 44, sbc3 = 46, i2c5 = 47, dsia = 48, 821 mipi = 50, hdmi = 51, csi = 52, i2c2 = 54, uartc = 55, mipi_cal = 56, 822 emc, usb2, usb3, vde = 61, bsea = 62, bsev = 63, uartd = 65, 823 i2c3 = 67, sbc4 = 68, sdmmc3 = 69, owr = 71, csite = 73, 824 la = 76, trace = 77, soc_therm = 78, dtv = 79, ndspeed = 80, 825 i2cslow = 81, dsib = 82, tsec = 83, xusb_host = 89, msenc = 91, 826 csus = 92, mselect = 99, tsensor = 100, i2s3 = 101, i2s4 = 102, 827 i2c4 = 103, sbc5 = 104, sbc6 = 105, d_audio, apbif = 107, dam0, dam1, 828 dam2, hda2codec_2x = 111, audio0_2x = 113, audio1_2x, audio2_2x, 829 audio3_2x, audio4_2x, spdif_2x, actmon = 119, extern1 = 120, 830 extern2 = 121, extern3 = 122, hda = 125, se = 127, hda2hdmi = 128, 831 cilab = 144, cilcd = 145, cile = 146, dsialp = 147, dsiblp = 148, 832 dds = 150, dp2 = 152, amx = 153, adx = 154, xusb_ss = 156, uartb = 192, 833 vfir, spdif_in, spdif_out, vi, vi_sensor, fuse, fuse_burn, clk_32k, 834 clk_m, clk_m_div2, clk_m_div4, pll_ref, pll_c, pll_c_out1, pll_c2, 835 pll_c3, pll_m, pll_m_out1, pll_p, pll_p_out1, pll_p_out2, pll_p_out3, 836 pll_p_out4, pll_a, pll_a_out0, pll_d, pll_d_out0, pll_d2, pll_d2_out0, 837 pll_u, pll_u_480M, pll_u_60M, pll_u_48M, pll_u_12M, pll_x, pll_x_out0, 838 pll_re_vco, pll_re_out, pll_e_out0, spdif_in_sync, i2s0_sync, 839 i2s1_sync, i2s2_sync, i2s3_sync, i2s4_sync, vimclk_sync, audio0, 840 audio1, audio2, audio3, audio4, spdif, clk_out_1, clk_out_2, clk_out_3, 841 blink, xusb_host_src = 252, xusb_falcon_src, xusb_fs_src, xusb_ss_src, 842 xusb_dev_src, xusb_dev, xusb_hs_src, sclk, hclk, pclk, cclk_g, cclk_lp, 843 844 /* Mux clocks */ 845 846 audio0_mux = 300, audio1_mux, audio2_mux, audio3_mux, audio4_mux, 847 spdif_mux, clk_out_1_mux, clk_out_2_mux, clk_out_3_mux, dsia_mux, 848 dsib_mux, clk_max, 849}; 850 851struct utmi_clk_param { 852 /* Oscillator Frequency in KHz */ 853 u32 osc_frequency; 854 /* UTMIP PLL Enable Delay Count */ 855 u8 enable_delay_count; 856 /* UTMIP PLL Stable count */ 857 u8 stable_count; 858 /* UTMIP PLL Active delay count */ 859 u8 active_delay_count; 860 /* UTMIP PLL Xtal frequency count */ 861 u8 xtal_freq_count; 862}; 863 864static const struct utmi_clk_param utmi_parameters[] = { 865 {.osc_frequency = 13000000, .enable_delay_count = 0x02, 866 .stable_count = 0x33, .active_delay_count = 0x05, 867 .xtal_freq_count = 0x7F}, 868 {.osc_frequency = 19200000, .enable_delay_count = 0x03, 869 .stable_count = 0x4B, .active_delay_count = 0x06, 870 .xtal_freq_count = 0xBB}, 871 {.osc_frequency = 12000000, .enable_delay_count = 0x02, 872 .stable_count = 0x2F, .active_delay_count = 0x04, 873 .xtal_freq_count = 0x76}, 874 {.osc_frequency = 26000000, .enable_delay_count = 0x04, 875 .stable_count = 0x66, .active_delay_count = 0x09, 876 .xtal_freq_count = 0xFE}, 877 {.osc_frequency = 16800000, .enable_delay_count = 0x03, 878 .stable_count = 0x41, .active_delay_count = 0x0A, 879 .xtal_freq_count = 0xA4}, 880}; 881 882/* peripheral mux definitions */ 883 884#define MUX_I2S_SPDIF(_id) \ 885static const char *mux_pllaout0_##_id##_2x_pllp_clkm[] = { "pll_a_out0", \ 886 #_id, "pll_p",\ 887 "clk_m"}; 888MUX_I2S_SPDIF(audio0) 889MUX_I2S_SPDIF(audio1) 890MUX_I2S_SPDIF(audio2) 891MUX_I2S_SPDIF(audio3) 892MUX_I2S_SPDIF(audio4) 893MUX_I2S_SPDIF(audio) 894 895#define mux_pllaout0_audio0_2x_pllp_clkm_idx NULL 896#define mux_pllaout0_audio1_2x_pllp_clkm_idx NULL 897#define mux_pllaout0_audio2_2x_pllp_clkm_idx NULL 898#define mux_pllaout0_audio3_2x_pllp_clkm_idx NULL 899#define mux_pllaout0_audio4_2x_pllp_clkm_idx NULL 900#define mux_pllaout0_audio_2x_pllp_clkm_idx NULL 901 902static const char *mux_pllp_pllc_pllm_clkm[] = { 903 "pll_p", "pll_c", "pll_m", "clk_m" 904}; 905#define mux_pllp_pllc_pllm_clkm_idx NULL 906 907static const char *mux_pllp_pllc_pllm[] = { "pll_p", "pll_c", "pll_m" }; 908#define mux_pllp_pllc_pllm_idx NULL 909 910static const char *mux_pllp_pllc_clk32_clkm[] = { 911 "pll_p", "pll_c", "clk_32k", "clk_m" 912}; 913#define mux_pllp_pllc_clk32_clkm_idx NULL 914 915static const char *mux_plla_pllc_pllp_clkm[] = { 916 "pll_a_out0", "pll_c", "pll_p", "clk_m" 917}; 918#define mux_plla_pllc_pllp_clkm_idx mux_pllp_pllc_pllm_clkm_idx 919 920static const char *mux_pllp_pllc2_c_c3_pllm_clkm[] = { 921 "pll_p", "pll_c2", "pll_c", "pll_c3", "pll_m", "clk_m" 922}; 923static u32 mux_pllp_pllc2_c_c3_pllm_clkm_idx[] = { 924 [0] = 0, [1] = 1, [2] = 2, [3] = 3, [4] = 4, [5] = 6, 925}; 926 927static const char *mux_pllp_clkm[] = { 928 "pll_p", "clk_m" 929}; 930static u32 mux_pllp_clkm_idx[] = { 931 [0] = 0, [1] = 3, 932}; 933 934static const char *mux_pllm_pllc2_c_c3_pllp_plla[] = { 935 "pll_m", "pll_c2", "pll_c", "pll_c3", "pll_p", "pll_a_out0" 936}; 937#define mux_pllm_pllc2_c_c3_pllp_plla_idx mux_pllp_pllc2_c_c3_pllm_clkm_idx 938 939static const char *mux_pllp_pllm_plld_plla_pllc_plld2_clkm[] = { 940 "pll_p", "pll_m", "pll_d_out0", "pll_a_out0", "pll_c", 941 "pll_d2_out0", "clk_m" 942}; 943#define mux_pllp_pllm_plld_plla_pllc_plld2_clkm_idx NULL 944 945static const char *mux_pllm_pllc_pllp_plla[] = { 946 "pll_m", "pll_c", "pll_p", "pll_a_out0" 947}; 948#define mux_pllm_pllc_pllp_plla_idx mux_pllp_pllc_pllm_clkm_idx 949 950static const char *mux_pllp_pllc_clkm[] = { 951 "pll_p", "pll_c", "pll_m" 952}; 953static u32 mux_pllp_pllc_clkm_idx[] = { 954 [0] = 0, [1] = 1, [2] = 3, 955}; 956 957static const char *mux_pllp_pllc_clkm_clk32[] = { 958 "pll_p", "pll_c", "clk_m", "clk_32k" 959}; 960#define mux_pllp_pllc_clkm_clk32_idx NULL 961 962static const char *mux_plla_clk32_pllp_clkm_plle[] = { 963 "pll_a_out0", "clk_32k", "pll_p", "clk_m", "pll_e_out0" 964}; 965#define mux_plla_clk32_pllp_clkm_plle_idx NULL 966 967static const char *mux_clkm_pllp_pllc_pllre[] = { 968 "clk_m", "pll_p", "pll_c", "pll_re_out" 969}; 970static u32 mux_clkm_pllp_pllc_pllre_idx[] = { 971 [0] = 0, [1] = 1, [2] = 3, [3] = 5, 972}; 973 974static const char *mux_clkm_48M_pllp_480M[] = { 975 "clk_m", "pll_u_48M", "pll_p", "pll_u_480M" 976}; 977#define mux_clkm_48M_pllp_480M_idx NULL 978 979static const char *mux_clkm_pllre_clk32_480M_pllc_ref[] = { 980 "clk_m", "pll_re_out", "clk_32k", "pll_u_480M", "pll_c", "pll_ref" 981}; 982static u32 mux_clkm_pllre_clk32_480M_pllc_ref_idx[] = { 983 [0] = 0, [1] = 1, [2] = 3, [3] = 3, [4] = 4, [5] = 7, 984}; 985 986static const char *mux_plld_out0_plld2_out0[] = { 987 "pll_d_out0", "pll_d2_out0", 988}; 989#define mux_plld_out0_plld2_out0_idx NULL 990 991static const char *mux_d_audio_clk[] = { 992 "pll_a_out0", "pll_p", "clk_m", "spdif_in_sync", "i2s0_sync", 993 "i2s1_sync", "i2s2_sync", "i2s3_sync", "i2s4_sync", "vimclk_sync", 994}; 995static u32 mux_d_audio_clk_idx[] = { 996 [0] = 0, [1] = 0x8000, [2] = 0xc000, [3] = 0xE000, [4] = 0xE001, 997 [5] = 0xE002, [6] = 0xE003, [7] = 0xE004, [8] = 0xE005, [9] = 0xE007, 998}; 999 1000static const char *mux_pllmcp_clkm[] = { 1001 "pll_m_out0", "pll_c_out0", "pll_p_out0", "clk_m", "pll_m_ud", 1002}; 1003 1004static const struct clk_div_table pll_re_div_table[] = { 1005 { .val = 0, .div = 1 }, 1006 { .val = 1, .div = 2 }, 1007 { .val = 2, .div = 3 }, 1008 { .val = 3, .div = 4 }, 1009 { .val = 4, .div = 5 }, 1010 { .val = 5, .div = 6 }, 1011 { .val = 0, .div = 0 }, 1012}; 1013 1014static struct clk *clks[clk_max]; 1015static struct clk_onecell_data clk_data; 1016 1017static unsigned long osc_freq; 1018static unsigned long pll_ref_freq; 1019 1020static int __init tegra114_osc_clk_init(void __iomem *clk_base) 1021{ 1022 struct clk *clk; 1023 u32 val, pll_ref_div; 1024 1025 val = readl_relaxed(clk_base + OSC_CTRL); 1026 1027 osc_freq = tegra114_input_freq[val >> OSC_CTRL_OSC_FREQ_SHIFT]; 1028 if (!osc_freq) { 1029 WARN_ON(1); 1030 return -EINVAL; 1031 } 1032 1033 /* clk_m */ 1034 clk = clk_register_fixed_rate(NULL, "clk_m", NULL, CLK_IS_ROOT, 1035 osc_freq); 1036 clk_register_clkdev(clk, "clk_m", NULL); 1037 clks[clk_m] = clk; 1038 1039 /* pll_ref */ 1040 val = (val >> OSC_CTRL_PLL_REF_DIV_SHIFT) & 3; 1041 pll_ref_div = 1 << val; 1042 clk = clk_register_fixed_factor(NULL, "pll_ref", "clk_m", 1043 CLK_SET_RATE_PARENT, 1, pll_ref_div); 1044 clk_register_clkdev(clk, "pll_ref", NULL); 1045 clks[pll_ref] = clk; 1046 1047 pll_ref_freq = osc_freq / pll_ref_div; 1048 1049 return 0; 1050} 1051 1052static void __init tegra114_fixed_clk_init(void __iomem *clk_base) 1053{ 1054 struct clk *clk; 1055 1056 /* clk_32k */ 1057 clk = clk_register_fixed_rate(NULL, "clk_32k", NULL, CLK_IS_ROOT, 1058 32768); 1059 clk_register_clkdev(clk, "clk_32k", NULL); 1060 clks[clk_32k] = clk; 1061 1062 /* clk_m_div2 */ 1063 clk = clk_register_fixed_factor(NULL, "clk_m_div2", "clk_m", 1064 CLK_SET_RATE_PARENT, 1, 2); 1065 clk_register_clkdev(clk, "clk_m_div2", NULL); 1066 clks[clk_m_div2] = clk; 1067 1068 /* clk_m_div4 */ 1069 clk = clk_register_fixed_factor(NULL, "clk_m_div4", "clk_m", 1070 CLK_SET_RATE_PARENT, 1, 4); 1071 clk_register_clkdev(clk, "clk_m_div4", NULL); 1072 clks[clk_m_div4] = clk; 1073 1074} 1075 1076static __init void tegra114_utmi_param_configure(void __iomem *clk_base) 1077{ 1078 u32 reg; 1079 int i; 1080 1081 for (i = 0; i < ARRAY_SIZE(utmi_parameters); i++) { 1082 if (osc_freq == utmi_parameters[i].osc_frequency) 1083 break; 1084 } 1085 1086 if (i >= ARRAY_SIZE(utmi_parameters)) { 1087 pr_err("%s: Unexpected oscillator freq %lu\n", __func__, 1088 osc_freq); 1089 return; 1090 } 1091 1092 reg = readl_relaxed(clk_base + UTMIP_PLL_CFG2); 1093 1094 /* Program UTMIP PLL stable and active counts */ 1095 /* [FIXME] arclk_rst.h says WRONG! This should be 1ms -> 0x50 Check! */ 1096 reg &= ~UTMIP_PLL_CFG2_STABLE_COUNT(~0); 1097 reg |= UTMIP_PLL_CFG2_STABLE_COUNT(utmi_parameters[i].stable_count); 1098 1099 reg &= ~UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(~0); 1100 1101 reg |= UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(utmi_parameters[i]. 1102 active_delay_count); 1103 1104 /* Remove power downs from UTMIP PLL control bits */ 1105 reg &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_A_POWERDOWN; 1106 reg &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_B_POWERDOWN; 1107 reg &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_C_POWERDOWN; 1108 1109 writel_relaxed(reg, clk_base + UTMIP_PLL_CFG2); 1110 1111 /* Program UTMIP PLL delay and oscillator frequency counts */ 1112 reg = readl_relaxed(clk_base + UTMIP_PLL_CFG1); 1113 reg &= ~UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(~0); 1114 1115 reg |= UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(utmi_parameters[i]. 1116 enable_delay_count); 1117 1118 reg &= ~UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(~0); 1119 reg |= UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(utmi_parameters[i]. 1120 xtal_freq_count); 1121 1122 /* Remove power downs from UTMIP PLL control bits */ 1123 reg &= ~UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN; 1124 reg &= ~UTMIP_PLL_CFG1_FORCE_PLL_ACTIVE_POWERDOWN; 1125 reg &= ~UTMIP_PLL_CFG1_FORCE_PLLU_POWERUP; 1126 reg &= ~UTMIP_PLL_CFG1_FORCE_PLLU_POWERDOWN; 1127 writel_relaxed(reg, clk_base + UTMIP_PLL_CFG1); 1128 1129 /* Setup HW control of UTMIPLL */ 1130 reg = readl_relaxed(clk_base + UTMIPLL_HW_PWRDN_CFG0); 1131 reg |= UTMIPLL_HW_PWRDN_CFG0_USE_LOCKDET; 1132 reg &= ~UTMIPLL_HW_PWRDN_CFG0_CLK_ENABLE_SWCTL; 1133 reg |= UTMIPLL_HW_PWRDN_CFG0_SEQ_START_STATE; 1134 writel_relaxed(reg, clk_base + UTMIPLL_HW_PWRDN_CFG0); 1135 1136 reg = readl_relaxed(clk_base + UTMIP_PLL_CFG1); 1137 reg &= ~UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERUP; 1138 reg &= ~UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN; 1139 writel_relaxed(reg, clk_base + UTMIP_PLL_CFG1); 1140 1141 udelay(1); 1142 1143 /* Setup SW override of UTMIPLL assuming USB2.0 1144 ports are assigned to USB2 */ 1145 reg = readl_relaxed(clk_base + UTMIPLL_HW_PWRDN_CFG0); 1146 reg |= UTMIPLL_HW_PWRDN_CFG0_IDDQ_SWCTL; 1147 reg &= ~UTMIPLL_HW_PWRDN_CFG0_IDDQ_OVERRIDE; 1148 writel_relaxed(reg, clk_base + UTMIPLL_HW_PWRDN_CFG0); 1149 1150 udelay(1); 1151 1152 /* Enable HW control UTMIPLL */ 1153 reg = readl_relaxed(clk_base + UTMIPLL_HW_PWRDN_CFG0); 1154 reg |= UTMIPLL_HW_PWRDN_CFG0_SEQ_ENABLE; 1155 writel_relaxed(reg, clk_base + UTMIPLL_HW_PWRDN_CFG0); 1156} 1157 1158static void __init _clip_vco_min(struct tegra_clk_pll_params *pll_params) 1159{ 1160 pll_params->vco_min = 1161 DIV_ROUND_UP(pll_params->vco_min, pll_ref_freq) * pll_ref_freq; 1162} 1163 1164static int __init _setup_dynamic_ramp(struct tegra_clk_pll_params *pll_params, 1165 void __iomem *clk_base) 1166{ 1167 u32 val; 1168 u32 step_a, step_b; 1169 1170 switch (pll_ref_freq) { 1171 case 12000000: 1172 case 13000000: 1173 case 26000000: 1174 step_a = 0x2B; 1175 step_b = 0x0B; 1176 break; 1177 case 16800000: 1178 step_a = 0x1A; 1179 step_b = 0x09; 1180 break; 1181 case 19200000: 1182 step_a = 0x12; 1183 step_b = 0x08; 1184 break; 1185 default: 1186 pr_err("%s: Unexpected reference rate %lu\n", 1187 __func__, pll_ref_freq); 1188 WARN_ON(1); 1189 return -EINVAL; 1190 } 1191 1192 val = step_a << pll_params->stepa_shift; 1193 val |= step_b << pll_params->stepb_shift; 1194 writel_relaxed(val, clk_base + pll_params->dyn_ramp_reg); 1195 1196 return 0; 1197} 1198 1199static void __init _init_iddq(struct tegra_clk_pll_params *pll_params, 1200 void __iomem *clk_base) 1201{ 1202 u32 val, val_iddq; 1203 1204 val = readl_relaxed(clk_base + pll_params->base_reg); 1205 val_iddq = readl_relaxed(clk_base + pll_params->iddq_reg); 1206 1207 if (val & BIT(30)) 1208 WARN_ON(val_iddq & BIT(pll_params->iddq_bit_idx)); 1209 else { 1210 val_iddq |= BIT(pll_params->iddq_bit_idx); 1211 writel_relaxed(val_iddq, clk_base + pll_params->iddq_reg); 1212 } 1213} 1214 1215static void __init tegra114_pll_init(void __iomem *clk_base, 1216 void __iomem *pmc) 1217{ 1218 u32 val; 1219 struct clk *clk; 1220 1221 /* PLLC */ 1222 _clip_vco_min(&pll_c_params); 1223 if (_setup_dynamic_ramp(&pll_c_params, clk_base) >= 0) { 1224 _init_iddq(&pll_c_params, clk_base); 1225 clk = tegra_clk_register_pllxc("pll_c", "pll_ref", clk_base, 1226 pmc, 0, 0, &pll_c_params, TEGRA_PLL_USE_LOCK, 1227 pll_c_freq_table, NULL); 1228 clk_register_clkdev(clk, "pll_c", NULL); 1229 clks[pll_c] = clk; 1230 1231 /* PLLC_OUT1 */ 1232 clk = tegra_clk_register_divider("pll_c_out1_div", "pll_c", 1233 clk_base + PLLC_OUT, 0, TEGRA_DIVIDER_ROUND_UP, 1234 8, 8, 1, NULL); 1235 clk = tegra_clk_register_pll_out("pll_c_out1", "pll_c_out1_div", 1236 clk_base + PLLC_OUT, 1, 0, 1237 CLK_SET_RATE_PARENT, 0, NULL); 1238 clk_register_clkdev(clk, "pll_c_out1", NULL); 1239 clks[pll_c_out1] = clk; 1240 } 1241 1242 /* PLLC2 */ 1243 _clip_vco_min(&pll_c2_params); 1244 clk = tegra_clk_register_pllc("pll_c2", "pll_ref", clk_base, pmc, 0, 0, 1245 &pll_c2_params, TEGRA_PLL_USE_LOCK, 1246 pll_cx_freq_table, NULL); 1247 clk_register_clkdev(clk, "pll_c2", NULL); 1248 clks[pll_c2] = clk; 1249 1250 /* PLLC3 */ 1251 _clip_vco_min(&pll_c3_params); 1252 clk = tegra_clk_register_pllc("pll_c3", "pll_ref", clk_base, pmc, 0, 0, 1253 &pll_c3_params, TEGRA_PLL_USE_LOCK, 1254 pll_cx_freq_table, NULL); 1255 clk_register_clkdev(clk, "pll_c3", NULL); 1256 clks[pll_c3] = clk; 1257 1258 /* PLLP */ 1259 clk = tegra_clk_register_pll("pll_p", "pll_ref", clk_base, pmc, 0, 1260 408000000, &pll_p_params, 1261 TEGRA_PLL_FIXED | TEGRA_PLL_USE_LOCK, 1262 pll_p_freq_table, NULL); 1263 clk_register_clkdev(clk, "pll_p", NULL); 1264 clks[pll_p] = clk; 1265 1266 /* PLLP_OUT1 */ 1267 clk = tegra_clk_register_divider("pll_p_out1_div", "pll_p", 1268 clk_base + PLLP_OUTA, 0, TEGRA_DIVIDER_FIXED | 1269 TEGRA_DIVIDER_ROUND_UP, 8, 8, 1, &pll_div_lock); 1270 clk = tegra_clk_register_pll_out("pll_p_out1", "pll_p_out1_div", 1271 clk_base + PLLP_OUTA, 1, 0, 1272 CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0, 1273 &pll_div_lock); 1274 clk_register_clkdev(clk, "pll_p_out1", NULL); 1275 clks[pll_p_out1] = clk; 1276 1277 /* PLLP_OUT2 */ 1278 clk = tegra_clk_register_divider("pll_p_out2_div", "pll_p", 1279 clk_base + PLLP_OUTA, 0, TEGRA_DIVIDER_FIXED | 1280 TEGRA_DIVIDER_ROUND_UP | TEGRA_DIVIDER_INT, 24, 1281 8, 1, &pll_div_lock); 1282 clk = tegra_clk_register_pll_out("pll_p_out2", "pll_p_out2_div", 1283 clk_base + PLLP_OUTA, 17, 16, 1284 CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0, 1285 &pll_div_lock); 1286 clk_register_clkdev(clk, "pll_p_out2", NULL); 1287 clks[pll_p_out2] = clk; 1288 1289 /* PLLP_OUT3 */ 1290 clk = tegra_clk_register_divider("pll_p_out3_div", "pll_p", 1291 clk_base + PLLP_OUTB, 0, TEGRA_DIVIDER_FIXED | 1292 TEGRA_DIVIDER_ROUND_UP, 8, 8, 1, &pll_div_lock); 1293 clk = tegra_clk_register_pll_out("pll_p_out3", "pll_p_out3_div", 1294 clk_base + PLLP_OUTB, 1, 0, 1295 CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0, 1296 &pll_div_lock); 1297 clk_register_clkdev(clk, "pll_p_out3", NULL); 1298 clks[pll_p_out3] = clk; 1299 1300 /* PLLP_OUT4 */ 1301 clk = tegra_clk_register_divider("pll_p_out4_div", "pll_p", 1302 clk_base + PLLP_OUTB, 0, TEGRA_DIVIDER_FIXED | 1303 TEGRA_DIVIDER_ROUND_UP, 24, 8, 1, 1304 &pll_div_lock); 1305 clk = tegra_clk_register_pll_out("pll_p_out4", "pll_p_out4_div", 1306 clk_base + PLLP_OUTB, 17, 16, 1307 CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0, 1308 &pll_div_lock); 1309 clk_register_clkdev(clk, "pll_p_out4", NULL); 1310 clks[pll_p_out4] = clk; 1311 1312 /* PLLM */ 1313 _clip_vco_min(&pll_m_params); 1314 clk = tegra_clk_register_pllm("pll_m", "pll_ref", clk_base, pmc, 1315 CLK_IGNORE_UNUSED | CLK_SET_RATE_GATE, 0, 1316 &pll_m_params, TEGRA_PLL_USE_LOCK, 1317 pll_m_freq_table, NULL); 1318 clk_register_clkdev(clk, "pll_m", NULL); 1319 clks[pll_m] = clk; 1320 1321 /* PLLM_OUT1 */ 1322 clk = tegra_clk_register_divider("pll_m_out1_div", "pll_m", 1323 clk_base + PLLM_OUT, 0, TEGRA_DIVIDER_ROUND_UP, 1324 8, 8, 1, NULL); 1325 clk = tegra_clk_register_pll_out("pll_m_out1", "pll_m_out1_div", 1326 clk_base + PLLM_OUT, 1, 0, CLK_IGNORE_UNUSED | 1327 CLK_SET_RATE_PARENT, 0, NULL); 1328 clk_register_clkdev(clk, "pll_m_out1", NULL); 1329 clks[pll_m_out1] = clk; 1330 1331 /* PLLM_UD */ 1332 clk = clk_register_fixed_factor(NULL, "pll_m_ud", "pll_m", 1333 CLK_SET_RATE_PARENT, 1, 1); 1334 1335 /* PLLX */ 1336 _clip_vco_min(&pll_x_params); 1337 if (_setup_dynamic_ramp(&pll_x_params, clk_base) >= 0) { 1338 _init_iddq(&pll_x_params, clk_base); 1339 clk = tegra_clk_register_pllxc("pll_x", "pll_ref", clk_base, 1340 pmc, CLK_IGNORE_UNUSED, 0, &pll_x_params, 1341 TEGRA_PLL_USE_LOCK, pll_x_freq_table, NULL); 1342 clk_register_clkdev(clk, "pll_x", NULL); 1343 clks[pll_x] = clk; 1344 } 1345 1346 /* PLLX_OUT0 */ 1347 clk = clk_register_fixed_factor(NULL, "pll_x_out0", "pll_x", 1348 CLK_SET_RATE_PARENT, 1, 2); 1349 clk_register_clkdev(clk, "pll_x_out0", NULL); 1350 clks[pll_x_out0] = clk; 1351 1352 /* PLLU */ 1353 val = readl(clk_base + pll_u_params.base_reg); 1354 val &= ~BIT(24); /* disable PLLU_OVERRIDE */ 1355 writel(val, clk_base + pll_u_params.base_reg); 1356 1357 clk = tegra_clk_register_pll("pll_u", "pll_ref", clk_base, pmc, 0, 1358 0, &pll_u_params, TEGRA_PLLU | 1359 TEGRA_PLL_HAS_CPCON | TEGRA_PLL_SET_LFCON | 1360 TEGRA_PLL_USE_LOCK, pll_u_freq_table, &pll_u_lock); 1361 clk_register_clkdev(clk, "pll_u", NULL); 1362 clks[pll_u] = clk; 1363 1364 tegra114_utmi_param_configure(clk_base); 1365 1366 /* PLLU_480M */ 1367 clk = clk_register_gate(NULL, "pll_u_480M", "pll_u", 1368 CLK_SET_RATE_PARENT, clk_base + PLLU_BASE, 1369 22, 0, &pll_u_lock); 1370 clk_register_clkdev(clk, "pll_u_480M", NULL); 1371 clks[pll_u_480M] = clk; 1372 1373 /* PLLU_60M */ 1374 clk = clk_register_fixed_factor(NULL, "pll_u_60M", "pll_u", 1375 CLK_SET_RATE_PARENT, 1, 8); 1376 clk_register_clkdev(clk, "pll_u_60M", NULL); 1377 clks[pll_u_60M] = clk; 1378 1379 /* PLLU_48M */ 1380 clk = clk_register_fixed_factor(NULL, "pll_u_48M", "pll_u", 1381 CLK_SET_RATE_PARENT, 1, 10); 1382 clk_register_clkdev(clk, "pll_u_48M", NULL); 1383 clks[pll_u_48M] = clk; 1384 1385 /* PLLU_12M */ 1386 clk = clk_register_fixed_factor(NULL, "pll_u_12M", "pll_u", 1387 CLK_SET_RATE_PARENT, 1, 40); 1388 clk_register_clkdev(clk, "pll_u_12M", NULL); 1389 clks[pll_u_12M] = clk; 1390 1391 /* PLLD */ 1392 clk = tegra_clk_register_pll("pll_d", "pll_ref", clk_base, pmc, 0, 1393 0, &pll_d_params, 1394 TEGRA_PLL_HAS_CPCON | TEGRA_PLL_SET_LFCON | 1395 TEGRA_PLL_USE_LOCK, pll_d_freq_table, &pll_d_lock); 1396 clk_register_clkdev(clk, "pll_d", NULL); 1397 clks[pll_d] = clk; 1398 1399 /* PLLD_OUT0 */ 1400 clk = clk_register_fixed_factor(NULL, "pll_d_out0", "pll_d", 1401 CLK_SET_RATE_PARENT, 1, 2); 1402 clk_register_clkdev(clk, "pll_d_out0", NULL); 1403 clks[pll_d_out0] = clk; 1404 1405 /* PLLD2 */ 1406 clk = tegra_clk_register_pll("pll_d2", "pll_ref", clk_base, pmc, 0, 1407 0, &pll_d2_params, 1408 TEGRA_PLL_HAS_CPCON | TEGRA_PLL_SET_LFCON | 1409 TEGRA_PLL_USE_LOCK, pll_d_freq_table, &pll_d2_lock); 1410 clk_register_clkdev(clk, "pll_d2", NULL); 1411 clks[pll_d2] = clk; 1412 1413 /* PLLD2_OUT0 */ 1414 clk = clk_register_fixed_factor(NULL, "pll_d2_out0", "pll_d2", 1415 CLK_SET_RATE_PARENT, 1, 2); 1416 clk_register_clkdev(clk, "pll_d2_out0", NULL); 1417 clks[pll_d2_out0] = clk; 1418 1419 /* PLLA */ 1420 clk = tegra_clk_register_pll("pll_a", "pll_p_out1", clk_base, pmc, 0, 1421 0, &pll_a_params, TEGRA_PLL_HAS_CPCON | 1422 TEGRA_PLL_USE_LOCK, pll_a_freq_table, NULL); 1423 clk_register_clkdev(clk, "pll_a", NULL); 1424 clks[pll_a] = clk; 1425 1426 /* PLLA_OUT0 */ 1427 clk = tegra_clk_register_divider("pll_a_out0_div", "pll_a", 1428 clk_base + PLLA_OUT, 0, TEGRA_DIVIDER_ROUND_UP, 1429 8, 8, 1, NULL); 1430 clk = tegra_clk_register_pll_out("pll_a_out0", "pll_a_out0_div", 1431 clk_base + PLLA_OUT, 1, 0, CLK_IGNORE_UNUSED | 1432 CLK_SET_RATE_PARENT, 0, NULL); 1433 clk_register_clkdev(clk, "pll_a_out0", NULL); 1434 clks[pll_a_out0] = clk; 1435 1436 /* PLLRE */ 1437 _clip_vco_min(&pll_re_vco_params); 1438 clk = tegra_clk_register_pllre("pll_re_vco", "pll_ref", clk_base, pmc, 1439 0, 0, &pll_re_vco_params, TEGRA_PLL_USE_LOCK, 1440 NULL, &pll_re_lock, pll_ref_freq); 1441 clk_register_clkdev(clk, "pll_re_vco", NULL); 1442 clks[pll_re_vco] = clk; 1443 1444 clk = clk_register_divider_table(NULL, "pll_re_out", "pll_re_vco", 0, 1445 clk_base + PLLRE_BASE, 16, 4, 0, 1446 pll_re_div_table, &pll_re_lock); 1447 clk_register_clkdev(clk, "pll_re_out", NULL); 1448 clks[pll_re_out] = clk; 1449 1450 /* PLLE */ 1451 clk = tegra_clk_register_plle_tegra114("pll_e_out0", "pll_re_vco", 1452 clk_base, 0, 100000000, &pll_e_params, 1453 pll_e_freq_table, NULL); 1454 clk_register_clkdev(clk, "pll_e_out0", NULL); 1455 clks[pll_e_out0] = clk; 1456} 1457 1458static const char *mux_audio_sync_clk[] = { "spdif_in_sync", "i2s0_sync", 1459 "i2s1_sync", "i2s2_sync", "i2s3_sync", "i2s4_sync", "vimclk_sync", 1460}; 1461 1462static const char *clk_out1_parents[] = { "clk_m", "clk_m_div2", 1463 "clk_m_div4", "extern1", 1464}; 1465 1466static const char *clk_out2_parents[] = { "clk_m", "clk_m_div2", 1467 "clk_m_div4", "extern2", 1468}; 1469 1470static const char *clk_out3_parents[] = { "clk_m", "clk_m_div2", 1471 "clk_m_div4", "extern3", 1472}; 1473 1474static void __init tegra114_audio_clk_init(void __iomem *clk_base) 1475{ 1476 struct clk *clk; 1477 1478 /* spdif_in_sync */ 1479 clk = tegra_clk_register_sync_source("spdif_in_sync", 24000000, 1480 24000000); 1481 clk_register_clkdev(clk, "spdif_in_sync", NULL); 1482 clks[spdif_in_sync] = clk; 1483 1484 /* i2s0_sync */ 1485 clk = tegra_clk_register_sync_source("i2s0_sync", 24000000, 24000000); 1486 clk_register_clkdev(clk, "i2s0_sync", NULL); 1487 clks[i2s0_sync] = clk; 1488 1489 /* i2s1_sync */ 1490 clk = tegra_clk_register_sync_source("i2s1_sync", 24000000, 24000000); 1491 clk_register_clkdev(clk, "i2s1_sync", NULL); 1492 clks[i2s1_sync] = clk; 1493 1494 /* i2s2_sync */ 1495 clk = tegra_clk_register_sync_source("i2s2_sync", 24000000, 24000000); 1496 clk_register_clkdev(clk, "i2s2_sync", NULL); 1497 clks[i2s2_sync] = clk; 1498 1499 /* i2s3_sync */ 1500 clk = tegra_clk_register_sync_source("i2s3_sync", 24000000, 24000000); 1501 clk_register_clkdev(clk, "i2s3_sync", NULL); 1502 clks[i2s3_sync] = clk; 1503 1504 /* i2s4_sync */ 1505 clk = tegra_clk_register_sync_source("i2s4_sync", 24000000, 24000000); 1506 clk_register_clkdev(clk, "i2s4_sync", NULL); 1507 clks[i2s4_sync] = clk; 1508 1509 /* vimclk_sync */ 1510 clk = tegra_clk_register_sync_source("vimclk_sync", 24000000, 24000000); 1511 clk_register_clkdev(clk, "vimclk_sync", NULL); 1512 clks[vimclk_sync] = clk; 1513 1514 /* audio0 */ 1515 clk = clk_register_mux(NULL, "audio0_mux", mux_audio_sync_clk, 1516 ARRAY_SIZE(mux_audio_sync_clk), 0, 1517 clk_base + AUDIO_SYNC_CLK_I2S0, 0, 3, 0, 1518 NULL); 1519 clks[audio0_mux] = clk; 1520 clk = clk_register_gate(NULL, "audio0", "audio0_mux", 0, 1521 clk_base + AUDIO_SYNC_CLK_I2S0, 4, 1522 CLK_GATE_SET_TO_DISABLE, NULL); 1523 clk_register_clkdev(clk, "audio0", NULL); 1524 clks[audio0] = clk; 1525 1526 /* audio1 */ 1527 clk = clk_register_mux(NULL, "audio1_mux", mux_audio_sync_clk, 1528 ARRAY_SIZE(mux_audio_sync_clk), 0, 1529 clk_base + AUDIO_SYNC_CLK_I2S1, 0, 3, 0, 1530 NULL); 1531 clks[audio1_mux] = clk; 1532 clk = clk_register_gate(NULL, "audio1", "audio1_mux", 0, 1533 clk_base + AUDIO_SYNC_CLK_I2S1, 4, 1534 CLK_GATE_SET_TO_DISABLE, NULL); 1535 clk_register_clkdev(clk, "audio1", NULL); 1536 clks[audio1] = clk; 1537 1538 /* audio2 */ 1539 clk = clk_register_mux(NULL, "audio2_mux", mux_audio_sync_clk, 1540 ARRAY_SIZE(mux_audio_sync_clk), 0, 1541 clk_base + AUDIO_SYNC_CLK_I2S2, 0, 3, 0, 1542 NULL); 1543 clks[audio2_mux] = clk; 1544 clk = clk_register_gate(NULL, "audio2", "audio2_mux", 0, 1545 clk_base + AUDIO_SYNC_CLK_I2S2, 4, 1546 CLK_GATE_SET_TO_DISABLE, NULL); 1547 clk_register_clkdev(clk, "audio2", NULL); 1548 clks[audio2] = clk; 1549 1550 /* audio3 */ 1551 clk = clk_register_mux(NULL, "audio3_mux", mux_audio_sync_clk, 1552 ARRAY_SIZE(mux_audio_sync_clk), 0, 1553 clk_base + AUDIO_SYNC_CLK_I2S3, 0, 3, 0, 1554 NULL); 1555 clks[audio3_mux] = clk; 1556 clk = clk_register_gate(NULL, "audio3", "audio3_mux", 0, 1557 clk_base + AUDIO_SYNC_CLK_I2S3, 4, 1558 CLK_GATE_SET_TO_DISABLE, NULL); 1559 clk_register_clkdev(clk, "audio3", NULL); 1560 clks[audio3] = clk; 1561 1562 /* audio4 */ 1563 clk = clk_register_mux(NULL, "audio4_mux", mux_audio_sync_clk, 1564 ARRAY_SIZE(mux_audio_sync_clk), 0, 1565 clk_base + AUDIO_SYNC_CLK_I2S4, 0, 3, 0, 1566 NULL); 1567 clks[audio4_mux] = clk; 1568 clk = clk_register_gate(NULL, "audio4", "audio4_mux", 0, 1569 clk_base + AUDIO_SYNC_CLK_I2S4, 4, 1570 CLK_GATE_SET_TO_DISABLE, NULL); 1571 clk_register_clkdev(clk, "audio4", NULL); 1572 clks[audio4] = clk; 1573 1574 /* spdif */ 1575 clk = clk_register_mux(NULL, "spdif_mux", mux_audio_sync_clk, 1576 ARRAY_SIZE(mux_audio_sync_clk), 0, 1577 clk_base + AUDIO_SYNC_CLK_SPDIF, 0, 3, 0, 1578 NULL); 1579 clks[spdif_mux] = clk; 1580 clk = clk_register_gate(NULL, "spdif", "spdif_mux", 0, 1581 clk_base + AUDIO_SYNC_CLK_SPDIF, 4, 1582 CLK_GATE_SET_TO_DISABLE, NULL); 1583 clk_register_clkdev(clk, "spdif", NULL); 1584 clks[spdif] = clk; 1585 1586 /* audio0_2x */ 1587 clk = clk_register_fixed_factor(NULL, "audio0_doubler", "audio0", 1588 CLK_SET_RATE_PARENT, 2, 1); 1589 clk = tegra_clk_register_divider("audio0_div", "audio0_doubler", 1590 clk_base + AUDIO_SYNC_DOUBLER, 0, 0, 24, 1, 1591 0, &clk_doubler_lock); 1592 clk = tegra_clk_register_periph_gate("audio0_2x", "audio0_div", 1593 TEGRA_PERIPH_NO_RESET, clk_base, 1594 CLK_SET_RATE_PARENT, 113, &periph_v_regs, 1595 periph_clk_enb_refcnt); 1596 clk_register_clkdev(clk, "audio0_2x", NULL); 1597 clks[audio0_2x] = clk; 1598 1599 /* audio1_2x */ 1600 clk = clk_register_fixed_factor(NULL, "audio1_doubler", "audio1", 1601 CLK_SET_RATE_PARENT, 2, 1); 1602 clk = tegra_clk_register_divider("audio1_div", "audio1_doubler", 1603 clk_base + AUDIO_SYNC_DOUBLER, 0, 0, 25, 1, 1604 0, &clk_doubler_lock); 1605 clk = tegra_clk_register_periph_gate("audio1_2x", "audio1_div", 1606 TEGRA_PERIPH_NO_RESET, clk_base, 1607 CLK_SET_RATE_PARENT, 114, &periph_v_regs, 1608 periph_clk_enb_refcnt); 1609 clk_register_clkdev(clk, "audio1_2x", NULL); 1610 clks[audio1_2x] = clk; 1611 1612 /* audio2_2x */ 1613 clk = clk_register_fixed_factor(NULL, "audio2_doubler", "audio2", 1614 CLK_SET_RATE_PARENT, 2, 1); 1615 clk = tegra_clk_register_divider("audio2_div", "audio2_doubler", 1616 clk_base + AUDIO_SYNC_DOUBLER, 0, 0, 26, 1, 1617 0, &clk_doubler_lock); 1618 clk = tegra_clk_register_periph_gate("audio2_2x", "audio2_div", 1619 TEGRA_PERIPH_NO_RESET, clk_base, 1620 CLK_SET_RATE_PARENT, 115, &periph_v_regs, 1621 periph_clk_enb_refcnt); 1622 clk_register_clkdev(clk, "audio2_2x", NULL); 1623 clks[audio2_2x] = clk; 1624 1625 /* audio3_2x */ 1626 clk = clk_register_fixed_factor(NULL, "audio3_doubler", "audio3", 1627 CLK_SET_RATE_PARENT, 2, 1); 1628 clk = tegra_clk_register_divider("audio3_div", "audio3_doubler", 1629 clk_base + AUDIO_SYNC_DOUBLER, 0, 0, 27, 1, 1630 0, &clk_doubler_lock); 1631 clk = tegra_clk_register_periph_gate("audio3_2x", "audio3_div", 1632 TEGRA_PERIPH_NO_RESET, clk_base, 1633 CLK_SET_RATE_PARENT, 116, &periph_v_regs, 1634 periph_clk_enb_refcnt); 1635 clk_register_clkdev(clk, "audio3_2x", NULL); 1636 clks[audio3_2x] = clk; 1637 1638 /* audio4_2x */ 1639 clk = clk_register_fixed_factor(NULL, "audio4_doubler", "audio4", 1640 CLK_SET_RATE_PARENT, 2, 1); 1641 clk = tegra_clk_register_divider("audio4_div", "audio4_doubler", 1642 clk_base + AUDIO_SYNC_DOUBLER, 0, 0, 28, 1, 1643 0, &clk_doubler_lock); 1644 clk = tegra_clk_register_periph_gate("audio4_2x", "audio4_div", 1645 TEGRA_PERIPH_NO_RESET, clk_base, 1646 CLK_SET_RATE_PARENT, 117, &periph_v_regs, 1647 periph_clk_enb_refcnt); 1648 clk_register_clkdev(clk, "audio4_2x", NULL); 1649 clks[audio4_2x] = clk; 1650 1651 /* spdif_2x */ 1652 clk = clk_register_fixed_factor(NULL, "spdif_doubler", "spdif", 1653 CLK_SET_RATE_PARENT, 2, 1); 1654 clk = tegra_clk_register_divider("spdif_div", "spdif_doubler", 1655 clk_base + AUDIO_SYNC_DOUBLER, 0, 0, 29, 1, 1656 0, &clk_doubler_lock); 1657 clk = tegra_clk_register_periph_gate("spdif_2x", "spdif_div", 1658 TEGRA_PERIPH_NO_RESET, clk_base, 1659 CLK_SET_RATE_PARENT, 118, 1660 &periph_v_regs, periph_clk_enb_refcnt); 1661 clk_register_clkdev(clk, "spdif_2x", NULL); 1662 clks[spdif_2x] = clk; 1663} 1664 1665static void __init tegra114_pmc_clk_init(void __iomem *pmc_base) 1666{ 1667 struct clk *clk; 1668 1669 /* clk_out_1 */ 1670 clk = clk_register_mux(NULL, "clk_out_1_mux", clk_out1_parents, 1671 ARRAY_SIZE(clk_out1_parents), 0, 1672 pmc_base + PMC_CLK_OUT_CNTRL, 6, 3, 0, 1673 &clk_out_lock); 1674 clks[clk_out_1_mux] = clk; 1675 clk = clk_register_gate(NULL, "clk_out_1", "clk_out_1_mux", 0, 1676 pmc_base + PMC_CLK_OUT_CNTRL, 2, 0, 1677 &clk_out_lock); 1678 clk_register_clkdev(clk, "extern1", "clk_out_1"); 1679 clks[clk_out_1] = clk; 1680 1681 /* clk_out_2 */ 1682 clk = clk_register_mux(NULL, "clk_out_2_mux", clk_out2_parents, 1683 ARRAY_SIZE(clk_out2_parents), 0, 1684 pmc_base + PMC_CLK_OUT_CNTRL, 14, 3, 0, 1685 &clk_out_lock); 1686 clks[clk_out_2_mux] = clk; 1687 clk = clk_register_gate(NULL, "clk_out_2", "clk_out_2_mux", 0, 1688 pmc_base + PMC_CLK_OUT_CNTRL, 10, 0, 1689 &clk_out_lock); 1690 clk_register_clkdev(clk, "extern2", "clk_out_2"); 1691 clks[clk_out_2] = clk; 1692 1693 /* clk_out_3 */ 1694 clk = clk_register_mux(NULL, "clk_out_3_mux", clk_out3_parents, 1695 ARRAY_SIZE(clk_out3_parents), 0, 1696 pmc_base + PMC_CLK_OUT_CNTRL, 22, 3, 0, 1697 &clk_out_lock); 1698 clks[clk_out_3_mux] = clk; 1699 clk = clk_register_gate(NULL, "clk_out_3", "clk_out_3_mux", 0, 1700 pmc_base + PMC_CLK_OUT_CNTRL, 18, 0, 1701 &clk_out_lock); 1702 clk_register_clkdev(clk, "extern3", "clk_out_3"); 1703 clks[clk_out_3] = clk; 1704 1705 /* blink */ 1706 /* clear the blink timer register to directly output clk_32k */ 1707 writel_relaxed(0, pmc_base + PMC_BLINK_TIMER); 1708 clk = clk_register_gate(NULL, "blink_override", "clk_32k", 0, 1709 pmc_base + PMC_DPD_PADS_ORIDE, 1710 PMC_DPD_PADS_ORIDE_BLINK_ENB, 0, NULL); 1711 clk = clk_register_gate(NULL, "blink", "blink_override", 0, 1712 pmc_base + PMC_CTRL, 1713 PMC_CTRL_BLINK_ENB, 0, NULL); 1714 clk_register_clkdev(clk, "blink", NULL); 1715 clks[blink] = clk; 1716 1717} 1718 1719static const char *sclk_parents[] = { "clk_m", "pll_c_out1", "pll_p_out4", 1720 "pll_p_out3", "pll_p_out2", "unused", 1721 "clk_32k", "pll_m_out1" }; 1722 1723static const char *cclk_g_parents[] = { "clk_m", "pll_c", "clk_32k", "pll_m", 1724 "pll_p", "pll_p_out4", "unused", 1725 "unused", "pll_x" }; 1726 1727static const char *cclk_lp_parents[] = { "clk_m", "pll_c", "clk_32k", "pll_m", 1728 "pll_p", "pll_p_out4", "unused", 1729 "unused", "pll_x", "pll_x_out0" }; 1730 1731static void __init tegra114_super_clk_init(void __iomem *clk_base) 1732{ 1733 struct clk *clk; 1734 1735 /* CCLKG */ 1736 clk = tegra_clk_register_super_mux("cclk_g", cclk_g_parents, 1737 ARRAY_SIZE(cclk_g_parents), 1738 CLK_SET_RATE_PARENT, 1739 clk_base + CCLKG_BURST_POLICY, 1740 0, 4, 0, 0, NULL); 1741 clk_register_clkdev(clk, "cclk_g", NULL); 1742 clks[cclk_g] = clk; 1743 1744 /* CCLKLP */ 1745 clk = tegra_clk_register_super_mux("cclk_lp", cclk_lp_parents, 1746 ARRAY_SIZE(cclk_lp_parents), 1747 CLK_SET_RATE_PARENT, 1748 clk_base + CCLKLP_BURST_POLICY, 1749 0, 4, 8, 9, NULL); 1750 clk_register_clkdev(clk, "cclk_lp", NULL); 1751 clks[cclk_lp] = clk; 1752 1753 /* SCLK */ 1754 clk = tegra_clk_register_super_mux("sclk", sclk_parents, 1755 ARRAY_SIZE(sclk_parents), 1756 CLK_SET_RATE_PARENT, 1757 clk_base + SCLK_BURST_POLICY, 1758 0, 4, 0, 0, NULL); 1759 clk_register_clkdev(clk, "sclk", NULL); 1760 clks[sclk] = clk; 1761 1762 /* HCLK */ 1763 clk = clk_register_divider(NULL, "hclk_div", "sclk", 0, 1764 clk_base + SYSTEM_CLK_RATE, 4, 2, 0, 1765 &sysrate_lock); 1766 clk = clk_register_gate(NULL, "hclk", "hclk_div", CLK_SET_RATE_PARENT | 1767 CLK_IGNORE_UNUSED, clk_base + SYSTEM_CLK_RATE, 1768 7, CLK_GATE_SET_TO_DISABLE, &sysrate_lock); 1769 clk_register_clkdev(clk, "hclk", NULL); 1770 clks[hclk] = clk; 1771 1772 /* PCLK */ 1773 clk = clk_register_divider(NULL, "pclk_div", "hclk", 0, 1774 clk_base + SYSTEM_CLK_RATE, 0, 2, 0, 1775 &sysrate_lock); 1776 clk = clk_register_gate(NULL, "pclk", "pclk_div", CLK_SET_RATE_PARENT | 1777 CLK_IGNORE_UNUSED, clk_base + SYSTEM_CLK_RATE, 1778 3, CLK_GATE_SET_TO_DISABLE, &sysrate_lock); 1779 clk_register_clkdev(clk, "pclk", NULL); 1780 clks[pclk] = clk; 1781} 1782 1783static struct tegra_periph_init_data tegra_periph_clk_list[] = { 1784 TEGRA_INIT_DATA_MUX("i2s0", NULL, "tegra30-i2s.0", mux_pllaout0_audio0_2x_pllp_clkm, CLK_SOURCE_I2S0, 30, &periph_l_regs, TEGRA_PERIPH_ON_APB, i2s0), 1785 TEGRA_INIT_DATA_MUX("i2s1", NULL, "tegra30-i2s.1", mux_pllaout0_audio1_2x_pllp_clkm, CLK_SOURCE_I2S1, 11, &periph_l_regs, TEGRA_PERIPH_ON_APB, i2s1), 1786 TEGRA_INIT_DATA_MUX("i2s2", NULL, "tegra30-i2s.2", mux_pllaout0_audio2_2x_pllp_clkm, CLK_SOURCE_I2S2, 18, &periph_l_regs, TEGRA_PERIPH_ON_APB, i2s2), 1787 TEGRA_INIT_DATA_MUX("i2s3", NULL, "tegra30-i2s.3", mux_pllaout0_audio3_2x_pllp_clkm, CLK_SOURCE_I2S3, 101, &periph_v_regs, TEGRA_PERIPH_ON_APB, i2s3), 1788 TEGRA_INIT_DATA_MUX("i2s4", NULL, "tegra30-i2s.4", mux_pllaout0_audio4_2x_pllp_clkm, CLK_SOURCE_I2S4, 102, &periph_v_regs, TEGRA_PERIPH_ON_APB, i2s4), 1789 TEGRA_INIT_DATA_MUX("spdif_out", "spdif_out", "tegra30-spdif", mux_pllaout0_audio_2x_pllp_clkm, CLK_SOURCE_SPDIF_OUT, 10, &periph_l_regs, TEGRA_PERIPH_ON_APB, spdif_out), 1790 TEGRA_INIT_DATA_MUX("spdif_in", "spdif_in", "tegra30-spdif", mux_pllp_pllc_pllm, CLK_SOURCE_SPDIF_IN, 10, &periph_l_regs, TEGRA_PERIPH_ON_APB, spdif_in), 1791 TEGRA_INIT_DATA_MUX("pwm", NULL, "pwm", mux_pllp_pllc_clk32_clkm, CLK_SOURCE_PWM, 17, &periph_l_regs, TEGRA_PERIPH_ON_APB, pwm), 1792 TEGRA_INIT_DATA_MUX("adx", NULL, "adx", mux_plla_pllc_pllp_clkm, CLK_SOURCE_ADX, 154, &periph_w_regs, TEGRA_PERIPH_ON_APB, adx), 1793 TEGRA_INIT_DATA_MUX("amx", NULL, "amx", mux_plla_pllc_pllp_clkm, CLK_SOURCE_AMX, 153, &periph_w_regs, TEGRA_PERIPH_ON_APB, amx), 1794 TEGRA_INIT_DATA_MUX("hda", "hda", "tegra30-hda", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_HDA, 125, &periph_v_regs, TEGRA_PERIPH_ON_APB, hda), 1795 TEGRA_INIT_DATA_MUX("hda2codec_2x", "hda2codec", "tegra30-hda", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_HDA2CODEC_2X, 111, &periph_v_regs, TEGRA_PERIPH_ON_APB, hda2codec_2x), 1796 TEGRA_INIT_DATA_MUX("sbc1", NULL, "tegra11-spi.0", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SBC1, 41, &periph_h_regs, TEGRA_PERIPH_ON_APB, sbc1), 1797 TEGRA_INIT_DATA_MUX("sbc2", NULL, "tegra11-spi.1", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SBC2, 44, &periph_h_regs, TEGRA_PERIPH_ON_APB, sbc2), 1798 TEGRA_INIT_DATA_MUX("sbc3", NULL, "tegra11-spi.2", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SBC3, 46, &periph_h_regs, TEGRA_PERIPH_ON_APB, sbc3), 1799 TEGRA_INIT_DATA_MUX("sbc4", NULL, "tegra11-spi.3", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SBC4, 68, &periph_u_regs, TEGRA_PERIPH_ON_APB, sbc4), 1800 TEGRA_INIT_DATA_MUX("sbc5", NULL, "tegra11-spi.4", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SBC5, 104, &periph_v_regs, TEGRA_PERIPH_ON_APB, sbc5), 1801 TEGRA_INIT_DATA_MUX("sbc6", NULL, "tegra11-spi.5", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SBC6, 105, &periph_v_regs, TEGRA_PERIPH_ON_APB, sbc6), 1802 TEGRA_INIT_DATA_MUX8("ndflash", NULL, "tegra_nand", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_NDFLASH, 13, &periph_u_regs, TEGRA_PERIPH_ON_APB, ndspeed), 1803 TEGRA_INIT_DATA_MUX8("ndspeed", NULL, "tegra_nand_speed", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_NDSPEED, 80, &periph_u_regs, TEGRA_PERIPH_ON_APB, ndspeed), 1804 TEGRA_INIT_DATA_MUX("vfir", NULL, "vfir", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_VFIR, 7, &periph_l_regs, TEGRA_PERIPH_ON_APB, vfir), 1805 TEGRA_INIT_DATA_MUX("sdmmc1", NULL, "sdhci-tegra.0", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SDMMC1, 14, &periph_l_regs, 0, sdmmc1), 1806 TEGRA_INIT_DATA_MUX("sdmmc2", NULL, "sdhci-tegra.1", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SDMMC2, 9, &periph_l_regs, 0, sdmmc2), 1807 TEGRA_INIT_DATA_MUX("sdmmc3", NULL, "sdhci-tegra.2", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SDMMC3, 69, &periph_u_regs, 0, sdmmc3), 1808 TEGRA_INIT_DATA_MUX("sdmmc4", NULL, "sdhci-tegra.3", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SDMMC4, 15, &periph_l_regs, 0, sdmmc4), 1809 TEGRA_INIT_DATA_INT("vde", NULL, "vde", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_VDE, 61, &periph_h_regs, 0, vde), 1810 TEGRA_INIT_DATA_MUX_FLAGS("csite", NULL, "csite", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_CSITE, 73, &periph_u_regs, TEGRA_PERIPH_ON_APB, csite, CLK_IGNORE_UNUSED), 1811 TEGRA_INIT_DATA_MUX("la", NULL, "la", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_LA, 76, &periph_u_regs, TEGRA_PERIPH_ON_APB, la), 1812 TEGRA_INIT_DATA_MUX("trace", NULL, "trace", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_TRACE, 77, &periph_u_regs, TEGRA_PERIPH_ON_APB, trace), 1813 TEGRA_INIT_DATA_MUX("owr", NULL, "tegra_w1", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_OWR, 71, &periph_u_regs, TEGRA_PERIPH_ON_APB, owr), 1814 TEGRA_INIT_DATA_MUX("nor", NULL, "tegra-nor", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_NOR, 42, &periph_h_regs, 0, nor), 1815 TEGRA_INIT_DATA_MUX("mipi", NULL, "mipi", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_MIPI, 50, &periph_h_regs, TEGRA_PERIPH_ON_APB, mipi), 1816 TEGRA_INIT_DATA_I2C("i2c1", "div-clk", "tegra11-i2c.0", mux_pllp_clkm, CLK_SOURCE_I2C1, 12, &periph_l_regs, i2c1), 1817 TEGRA_INIT_DATA_I2C("i2c2", "div-clk", "tegra11-i2c.1", mux_pllp_clkm, CLK_SOURCE_I2C2, 54, &periph_h_regs, i2c2), 1818 TEGRA_INIT_DATA_I2C("i2c3", "div-clk", "tegra11-i2c.2", mux_pllp_clkm, CLK_SOURCE_I2C3, 67, &periph_u_regs, i2c3), 1819 TEGRA_INIT_DATA_I2C("i2c4", "div-clk", "tegra11-i2c.3", mux_pllp_clkm, CLK_SOURCE_I2C4, 103, &periph_v_regs, i2c4), 1820 TEGRA_INIT_DATA_I2C("i2c5", "div-clk", "tegra11-i2c.4", mux_pllp_clkm, CLK_SOURCE_I2C5, 47, &periph_h_regs, i2c5), 1821 TEGRA_INIT_DATA_UART("uarta", NULL, "tegra_uart.0", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_UARTA, 6, &periph_l_regs, uarta), 1822 TEGRA_INIT_DATA_UART("uartb", NULL, "tegra_uart.1", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_UARTB, 7, &periph_l_regs, uartb), 1823 TEGRA_INIT_DATA_UART("uartc", NULL, "tegra_uart.2", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_UARTC, 55, &periph_h_regs, uartc), 1824 TEGRA_INIT_DATA_UART("uartd", NULL, "tegra_uart.3", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_UARTD, 65, &periph_u_regs, uartd), 1825 TEGRA_INIT_DATA_INT("3d", NULL, "3d", mux_pllm_pllc2_c_c3_pllp_plla, CLK_SOURCE_3D, 24, &periph_l_regs, 0, gr_3d), 1826 TEGRA_INIT_DATA_INT("2d", NULL, "2d", mux_pllm_pllc2_c_c3_pllp_plla, CLK_SOURCE_2D, 21, &periph_l_regs, 0, gr_2d), 1827 TEGRA_INIT_DATA_MUX("vi_sensor", "vi_sensor", "tegra_camera", mux_pllm_pllc2_c_c3_pllp_plla, CLK_SOURCE_VI_SENSOR, 20, &periph_l_regs, TEGRA_PERIPH_NO_RESET, vi_sensor), 1828 TEGRA_INIT_DATA_INT8("vi", "vi", "tegra_camera", mux_pllm_pllc2_c_c3_pllp_plla, CLK_SOURCE_VI, 20, &periph_l_regs, 0, vi), 1829 TEGRA_INIT_DATA_INT8("epp", NULL, "epp", mux_pllm_pllc2_c_c3_pllp_plla, CLK_SOURCE_EPP, 19, &periph_l_regs, 0, epp), 1830 TEGRA_INIT_DATA_INT8("msenc", NULL, "msenc", mux_pllm_pllc2_c_c3_pllp_plla, CLK_SOURCE_MSENC, 91, &periph_u_regs, TEGRA_PERIPH_WAR_1005168, msenc), 1831 TEGRA_INIT_DATA_INT8("tsec", NULL, "tsec", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_TSEC, 83, &periph_u_regs, 0, tsec), 1832 TEGRA_INIT_DATA_INT8("host1x", NULL, "host1x", mux_pllm_pllc2_c_c3_pllp_plla, CLK_SOURCE_HOST1X, 28, &periph_l_regs, 0, host1x), 1833 TEGRA_INIT_DATA_MUX8("hdmi", NULL, "hdmi", mux_pllp_pllm_plld_plla_pllc_plld2_clkm, CLK_SOURCE_HDMI, 51, &periph_h_regs, 0, hdmi), 1834 TEGRA_INIT_DATA_MUX("cilab", "cilab", "tegra_camera", mux_pllp_pllc_clkm, CLK_SOURCE_CILAB, 144, &periph_w_regs, 0, cilab), 1835 TEGRA_INIT_DATA_MUX("cilcd", "cilcd", "tegra_camera", mux_pllp_pllc_clkm, CLK_SOURCE_CILCD, 145, &periph_w_regs, 0, cilcd), 1836 TEGRA_INIT_DATA_MUX("cile", "cile", "tegra_camera", mux_pllp_pllc_clkm, CLK_SOURCE_CILE, 146, &periph_w_regs, 0, cile), 1837 TEGRA_INIT_DATA_MUX("dsialp", "dsialp", "tegradc.0", mux_pllp_pllc_clkm, CLK_SOURCE_DSIALP, 147, &periph_w_regs, 0, dsialp), 1838 TEGRA_INIT_DATA_MUX("dsiblp", "dsiblp", "tegradc.1", mux_pllp_pllc_clkm, CLK_SOURCE_DSIBLP, 148, &periph_w_regs, 0, dsiblp), 1839 TEGRA_INIT_DATA_MUX("tsensor", NULL, "tegra-tsensor", mux_pllp_pllc_clkm_clk32, CLK_SOURCE_TSENSOR, 100, &periph_v_regs, TEGRA_PERIPH_ON_APB, tsensor), 1840 TEGRA_INIT_DATA_MUX("actmon", NULL, "actmon", mux_pllp_pllc_clk32_clkm, CLK_SOURCE_ACTMON, 119, &periph_v_regs, 0, actmon), 1841 TEGRA_INIT_DATA_MUX8("extern1", NULL, "extern1", mux_plla_clk32_pllp_clkm_plle, CLK_SOURCE_EXTERN1, 120, &periph_v_regs, 0, extern1), 1842 TEGRA_INIT_DATA_MUX8("extern2", NULL, "extern2", mux_plla_clk32_pllp_clkm_plle, CLK_SOURCE_EXTERN2, 121, &periph_v_regs, 0, extern2), 1843 TEGRA_INIT_DATA_MUX8("extern3", NULL, "extern3", mux_plla_clk32_pllp_clkm_plle, CLK_SOURCE_EXTERN3, 122, &periph_v_regs, 0, extern3), 1844 TEGRA_INIT_DATA_MUX("i2cslow", NULL, "i2cslow", mux_pllp_pllc_clk32_clkm, CLK_SOURCE_I2CSLOW, 81, &periph_u_regs, TEGRA_PERIPH_ON_APB, i2cslow), 1845 TEGRA_INIT_DATA_INT8("se", NULL, "se", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_SE, 127, &periph_v_regs, TEGRA_PERIPH_ON_APB, se), 1846 TEGRA_INIT_DATA_INT_FLAGS("mselect", NULL, "mselect", mux_pllp_clkm, CLK_SOURCE_MSELECT, 99, &periph_v_regs, 0, mselect, CLK_IGNORE_UNUSED), 1847 TEGRA_INIT_DATA_MUX8("soc_therm", NULL, "soc_therm", mux_pllm_pllc_pllp_plla, CLK_SOURCE_SOC_THERM, 78, &periph_u_regs, TEGRA_PERIPH_ON_APB, soc_therm), 1848 TEGRA_INIT_DATA_XUSB("xusb_host_src", "host_src", "tegra_xhci", mux_clkm_pllp_pllc_pllre, CLK_SOURCE_XUSB_HOST_SRC, 143, &periph_w_regs, TEGRA_PERIPH_ON_APB | TEGRA_PERIPH_NO_RESET, xusb_host_src), 1849 TEGRA_INIT_DATA_XUSB("xusb_falcon_src", "falcon_src", "tegra_xhci", mux_clkm_pllp_pllc_pllre, CLK_SOURCE_XUSB_FALCON_SRC, 143, &periph_w_regs, TEGRA_PERIPH_NO_RESET, xusb_falcon_src), 1850 TEGRA_INIT_DATA_XUSB("xusb_fs_src", "fs_src", "tegra_xhci", mux_clkm_48M_pllp_480M, CLK_SOURCE_XUSB_FS_SRC, 143, &periph_w_regs, TEGRA_PERIPH_NO_RESET, xusb_fs_src), 1851 TEGRA_INIT_DATA_XUSB("xusb_ss_src", "ss_src", "tegra_xhci", mux_clkm_pllre_clk32_480M_pllc_ref, CLK_SOURCE_XUSB_SS_SRC, 143, &periph_w_regs, TEGRA_PERIPH_NO_RESET, xusb_ss_src), 1852 TEGRA_INIT_DATA_XUSB("xusb_dev_src", "dev_src", "tegra_xhci", mux_clkm_pllp_pllc_pllre, CLK_SOURCE_XUSB_DEV_SRC, 95, &periph_u_regs, TEGRA_PERIPH_ON_APB | TEGRA_PERIPH_NO_RESET, xusb_dev_src), 1853 TEGRA_INIT_DATA_AUDIO("d_audio", "d_audio", "tegra30-ahub", CLK_SOURCE_D_AUDIO, 106, &periph_v_regs, TEGRA_PERIPH_ON_APB, d_audio), 1854 TEGRA_INIT_DATA_AUDIO("dam0", NULL, "tegra30-dam.0", CLK_SOURCE_DAM0, 108, &periph_v_regs, TEGRA_PERIPH_ON_APB, dam0), 1855 TEGRA_INIT_DATA_AUDIO("dam1", NULL, "tegra30-dam.1", CLK_SOURCE_DAM1, 109, &periph_v_regs, TEGRA_PERIPH_ON_APB, dam1), 1856 TEGRA_INIT_DATA_AUDIO("dam2", NULL, "tegra30-dam.2", CLK_SOURCE_DAM2, 110, &periph_v_regs, TEGRA_PERIPH_ON_APB, dam2), 1857}; 1858 1859static struct tegra_periph_init_data tegra_periph_nodiv_clk_list[] = { 1860 TEGRA_INIT_DATA_NODIV("disp1", NULL, "tegradc.0", mux_pllp_pllm_plld_plla_pllc_plld2_clkm, CLK_SOURCE_DISP1, 29, 7, 27, &periph_l_regs, 0, disp1), 1861 TEGRA_INIT_DATA_NODIV("disp2", NULL, "tegradc.1", mux_pllp_pllm_plld_plla_pllc_plld2_clkm, CLK_SOURCE_DISP2, 29, 7, 26, &periph_l_regs, 0, disp2), 1862}; 1863 1864static __init void tegra114_periph_clk_init(void __iomem *clk_base) 1865{ 1866 struct tegra_periph_init_data *data; 1867 struct clk *clk; 1868 int i; 1869 u32 val; 1870 1871 /* apbdma */ 1872 clk = tegra_clk_register_periph_gate("apbdma", "clk_m", 0, clk_base, 1873 0, 34, &periph_h_regs, 1874 periph_clk_enb_refcnt); 1875 clks[apbdma] = clk; 1876 1877 /* rtc */ 1878 clk = tegra_clk_register_periph_gate("rtc", "clk_32k", 1879 TEGRA_PERIPH_ON_APB | 1880 TEGRA_PERIPH_NO_RESET, clk_base, 1881 0, 4, &periph_l_regs, 1882 periph_clk_enb_refcnt); 1883 clk_register_clkdev(clk, NULL, "rtc-tegra"); 1884 clks[rtc] = clk; 1885 1886 /* kbc */ 1887 clk = tegra_clk_register_periph_gate("kbc", "clk_32k", 1888 TEGRA_PERIPH_ON_APB | 1889 TEGRA_PERIPH_NO_RESET, clk_base, 1890 0, 36, &periph_h_regs, 1891 periph_clk_enb_refcnt); 1892 clks[kbc] = clk; 1893 1894 /* timer */ 1895 clk = tegra_clk_register_periph_gate("timer", "clk_m", 0, clk_base, 1896 0, 5, &periph_l_regs, 1897 periph_clk_enb_refcnt); 1898 clk_register_clkdev(clk, NULL, "timer"); 1899 clks[timer] = clk; 1900 1901 /* kfuse */ 1902 clk = tegra_clk_register_periph_gate("kfuse", "clk_m", 1903 TEGRA_PERIPH_ON_APB, clk_base, 0, 40, 1904 &periph_h_regs, periph_clk_enb_refcnt); 1905 clks[kfuse] = clk; 1906 1907 /* fuse */ 1908 clk = tegra_clk_register_periph_gate("fuse", "clk_m", 1909 TEGRA_PERIPH_ON_APB, clk_base, 0, 39, 1910 &periph_h_regs, periph_clk_enb_refcnt); 1911 clks[fuse] = clk; 1912 1913 /* fuse_burn */ 1914 clk = tegra_clk_register_periph_gate("fuse_burn", "clk_m", 1915 TEGRA_PERIPH_ON_APB, clk_base, 0, 39, 1916 &periph_h_regs, periph_clk_enb_refcnt); 1917 clks[fuse_burn] = clk; 1918 1919 /* apbif */ 1920 clk = tegra_clk_register_periph_gate("apbif", "clk_m", 1921 TEGRA_PERIPH_ON_APB, clk_base, 0, 107, 1922 &periph_v_regs, periph_clk_enb_refcnt); 1923 clks[apbif] = clk; 1924 1925 /* hda2hdmi */ 1926 clk = tegra_clk_register_periph_gate("hda2hdmi", "clk_m", 1927 TEGRA_PERIPH_ON_APB, clk_base, 0, 128, 1928 &periph_w_regs, periph_clk_enb_refcnt); 1929 clks[hda2hdmi] = clk; 1930 1931 /* vcp */ 1932 clk = tegra_clk_register_periph_gate("vcp", "clk_m", 0, clk_base, 0, 1933 29, &periph_l_regs, 1934 periph_clk_enb_refcnt); 1935 clks[vcp] = clk; 1936 1937 /* bsea */ 1938 clk = tegra_clk_register_periph_gate("bsea", "clk_m", 0, clk_base, 1939 0, 62, &periph_h_regs, 1940 periph_clk_enb_refcnt); 1941 clks[bsea] = clk; 1942 1943 /* bsev */ 1944 clk = tegra_clk_register_periph_gate("bsev", "clk_m", 0, clk_base, 1945 0, 63, &periph_h_regs, 1946 periph_clk_enb_refcnt); 1947 clks[bsev] = clk; 1948 1949 /* mipi-cal */ 1950 clk = tegra_clk_register_periph_gate("mipi-cal", "clk_m", 0, clk_base, 1951 0, 56, &periph_h_regs, 1952 periph_clk_enb_refcnt); 1953 clks[mipi_cal] = clk; 1954 1955 /* usbd */ 1956 clk = tegra_clk_register_periph_gate("usbd", "clk_m", 0, clk_base, 1957 0, 22, &periph_l_regs, 1958 periph_clk_enb_refcnt); 1959 clks[usbd] = clk; 1960 1961 /* usb2 */ 1962 clk = tegra_clk_register_periph_gate("usb2", "clk_m", 0, clk_base, 1963 0, 58, &periph_h_regs, 1964 periph_clk_enb_refcnt); 1965 clks[usb2] = clk; 1966 1967 /* usb3 */ 1968 clk = tegra_clk_register_periph_gate("usb3", "clk_m", 0, clk_base, 1969 0, 59, &periph_h_regs, 1970 periph_clk_enb_refcnt); 1971 clks[usb3] = clk; 1972 1973 /* csi */ 1974 clk = tegra_clk_register_periph_gate("csi", "pll_p_out3", 0, clk_base, 1975 0, 52, &periph_h_regs, 1976 periph_clk_enb_refcnt); 1977 clks[csi] = clk; 1978 1979 /* isp */ 1980 clk = tegra_clk_register_periph_gate("isp", "clk_m", 0, clk_base, 0, 1981 23, &periph_l_regs, 1982 periph_clk_enb_refcnt); 1983 clks[isp] = clk; 1984 1985 /* csus */ 1986 clk = tegra_clk_register_periph_gate("csus", "clk_m", 1987 TEGRA_PERIPH_NO_RESET, clk_base, 0, 92, 1988 &periph_u_regs, periph_clk_enb_refcnt); 1989 clks[csus] = clk; 1990 1991 /* dds */ 1992 clk = tegra_clk_register_periph_gate("dds", "clk_m", 1993 TEGRA_PERIPH_ON_APB, clk_base, 0, 150, 1994 &periph_w_regs, periph_clk_enb_refcnt); 1995 clks[dds] = clk; 1996 1997 /* dp2 */ 1998 clk = tegra_clk_register_periph_gate("dp2", "clk_m", 1999 TEGRA_PERIPH_ON_APB, clk_base, 0, 152, 2000 &periph_w_regs, periph_clk_enb_refcnt); 2001 clks[dp2] = clk; 2002 2003 /* dtv */ 2004 clk = tegra_clk_register_periph_gate("dtv", "clk_m", 2005 TEGRA_PERIPH_ON_APB, clk_base, 0, 79, 2006 &periph_u_regs, periph_clk_enb_refcnt); 2007 clks[dtv] = clk; 2008 2009 /* dsia */ 2010 clk = clk_register_mux(NULL, "dsia_mux", mux_plld_out0_plld2_out0, 2011 ARRAY_SIZE(mux_plld_out0_plld2_out0), 0, 2012 clk_base + PLLD_BASE, 25, 1, 0, &pll_d_lock); 2013 clks[dsia_mux] = clk; 2014 clk = tegra_clk_register_periph_gate("dsia", "dsia_mux", 0, clk_base, 2015 0, 48, &periph_h_regs, 2016 periph_clk_enb_refcnt); 2017 clks[dsia] = clk; 2018 2019 /* dsib */ 2020 clk = clk_register_mux(NULL, "dsib_mux", mux_plld_out0_plld2_out0, 2021 ARRAY_SIZE(mux_plld_out0_plld2_out0), 0, 2022 clk_base + PLLD2_BASE, 25, 1, 0, &pll_d2_lock); 2023 clks[dsib_mux] = clk; 2024 clk = tegra_clk_register_periph_gate("dsib", "dsib_mux", 0, clk_base, 2025 0, 82, &periph_u_regs, 2026 periph_clk_enb_refcnt); 2027 clks[dsib] = clk; 2028 2029 /* xusb_hs_src */ 2030 val = readl(clk_base + CLK_SOURCE_XUSB_SS_SRC); 2031 val |= BIT(25); /* always select PLLU_60M */ 2032 writel(val, clk_base + CLK_SOURCE_XUSB_SS_SRC); 2033 2034 clk = clk_register_fixed_factor(NULL, "xusb_hs_src", "pll_u_60M", 0, 2035 1, 1); 2036 clks[xusb_hs_src] = clk; 2037 2038 /* xusb_host */ 2039 clk = tegra_clk_register_periph_gate("xusb_host", "xusb_host_src", 0, 2040 clk_base, 0, 89, &periph_u_regs, 2041 periph_clk_enb_refcnt); 2042 clks[xusb_host] = clk; 2043 2044 /* xusb_ss */ 2045 clk = tegra_clk_register_periph_gate("xusb_ss", "xusb_ss_src", 0, 2046 clk_base, 0, 156, &periph_w_regs, 2047 periph_clk_enb_refcnt); 2048 clks[xusb_host] = clk; 2049 2050 /* xusb_dev */ 2051 clk = tegra_clk_register_periph_gate("xusb_dev", "xusb_dev_src", 0, 2052 clk_base, 0, 95, &periph_u_regs, 2053 periph_clk_enb_refcnt); 2054 clks[xusb_dev] = clk; 2055 2056 /* emc */ 2057 clk = clk_register_mux(NULL, "emc_mux", mux_pllmcp_clkm, 2058 ARRAY_SIZE(mux_pllmcp_clkm), 0, 2059 clk_base + CLK_SOURCE_EMC, 2060 29, 3, 0, NULL); 2061 clk = tegra_clk_register_periph_gate("emc", "emc_mux", 0, clk_base, 2062 CLK_IGNORE_UNUSED, 57, &periph_h_regs, 2063 periph_clk_enb_refcnt); 2064 clks[emc] = clk; 2065 2066 for (i = 0; i < ARRAY_SIZE(tegra_periph_clk_list); i++) { 2067 data = &tegra_periph_clk_list[i]; 2068 clk = tegra_clk_register_periph(data->name, data->parent_names, 2069 data->num_parents, &data->periph, 2070 clk_base, data->offset, data->flags); 2071 clks[data->clk_id] = clk; 2072 } 2073 2074 for (i = 0; i < ARRAY_SIZE(tegra_periph_nodiv_clk_list); i++) { 2075 data = &tegra_periph_nodiv_clk_list[i]; 2076 clk = tegra_clk_register_periph_nodiv(data->name, 2077 data->parent_names, data->num_parents, 2078 &data->periph, clk_base, data->offset); 2079 clks[data->clk_id] = clk; 2080 } 2081} 2082 2083static struct tegra_cpu_car_ops tegra114_cpu_car_ops; 2084 2085static const struct of_device_id pmc_match[] __initconst = { 2086 { .compatible = "nvidia,tegra114-pmc" }, 2087 {}, 2088}; 2089 2090static __initdata struct tegra_clk_init_table init_table[] = { 2091 {uarta, pll_p, 408000000, 0}, 2092 {uartb, pll_p, 408000000, 0}, 2093 {uartc, pll_p, 408000000, 0}, 2094 {uartd, pll_p, 408000000, 0}, 2095 {pll_a, clk_max, 564480000, 1}, 2096 {pll_a_out0, clk_max, 11289600, 1}, 2097 {extern1, pll_a_out0, 0, 1}, 2098 {clk_out_1_mux, extern1, 0, 1}, 2099 {clk_out_1, clk_max, 0, 1}, 2100 {i2s0, pll_a_out0, 11289600, 0}, 2101 {i2s1, pll_a_out0, 11289600, 0}, 2102 {i2s2, pll_a_out0, 11289600, 0}, 2103 {i2s3, pll_a_out0, 11289600, 0}, 2104 {i2s4, pll_a_out0, 11289600, 0}, 2105 {clk_max, clk_max, 0, 0}, /* This MUST be the last entry. */ 2106}; 2107 2108static void __init tegra114_clock_apply_init_table(void) 2109{ 2110 tegra_init_from_table(init_table, clks, clk_max); 2111} 2112 2113static void __init tegra114_clock_init(struct device_node *np) 2114{ 2115 struct device_node *node; 2116 int i; 2117 2118 clk_base = of_iomap(np, 0); 2119 if (!clk_base) { 2120 pr_err("ioremap tegra114 CAR failed\n"); 2121 return; 2122 } 2123 2124 node = of_find_matching_node(NULL, pmc_match); 2125 if (!node) { 2126 pr_err("Failed to find pmc node\n"); 2127 WARN_ON(1); 2128 return; 2129 } 2130 2131 pmc_base = of_iomap(node, 0); 2132 if (!pmc_base) { 2133 pr_err("Can't map pmc registers\n"); 2134 WARN_ON(1); 2135 return; 2136 } 2137 2138 if (tegra114_osc_clk_init(clk_base) < 0) 2139 return; 2140 2141 tegra114_fixed_clk_init(clk_base); 2142 tegra114_pll_init(clk_base, pmc_base); 2143 tegra114_periph_clk_init(clk_base); 2144 tegra114_audio_clk_init(clk_base); 2145 tegra114_pmc_clk_init(pmc_base); 2146 tegra114_super_clk_init(clk_base); 2147 2148 for (i = 0; i < ARRAY_SIZE(clks); i++) { 2149 if (IS_ERR(clks[i])) { 2150 pr_err 2151 ("Tegra114 clk %d: register failed with %ld\n", 2152 i, PTR_ERR(clks[i])); 2153 } 2154 if (!clks[i]) 2155 clks[i] = ERR_PTR(-EINVAL); 2156 } 2157 2158 clk_data.clks = clks; 2159 clk_data.clk_num = ARRAY_SIZE(clks); 2160 of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data); 2161 2162 tegra_clk_apply_init_table = tegra114_clock_apply_init_table; 2163 2164 tegra_cpu_car_ops = &tegra114_cpu_car_ops; 2165} 2166CLK_OF_DECLARE(tegra114, "nvidia,tegra114-car", tegra114_clock_init); 2167