clk-tegra124.c revision 5c992afcf8e4f91fac05d39b86c7f7922a50145c
1/* 2 * Copyright (c) 2012, 2013, NVIDIA CORPORATION. All rights reserved. 3 * 4 * This program is free software; you can redistribute it and/or modify it 5 * under the terms and conditions of the GNU General Public License, 6 * version 2, as published by the Free Software Foundation. 7 * 8 * This program is distributed in the hope it will be useful, but WITHOUT 9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 11 * more details. 12 * 13 * You should have received a copy of the GNU General Public License 14 * along with this program. If not, see <http://www.gnu.org/licenses/>. 15 */ 16 17#include <linux/io.h> 18#include <linux/clk.h> 19#include <linux/clk-provider.h> 20#include <linux/clkdev.h> 21#include <linux/of.h> 22#include <linux/of_address.h> 23#include <linux/delay.h> 24#include <linux/export.h> 25#include <linux/clk/tegra.h> 26#include <dt-bindings/clock/tegra124-car.h> 27 28#include "clk.h" 29#include "clk-id.h" 30 31#define CLK_SOURCE_CSITE 0x1d4 32#define CLK_SOURCE_EMC 0x19c 33 34#define PLLC_BASE 0x80 35#define PLLC_OUT 0x84 36#define PLLC_MISC2 0x88 37#define PLLC_MISC 0x8c 38#define PLLC2_BASE 0x4e8 39#define PLLC2_MISC 0x4ec 40#define PLLC3_BASE 0x4fc 41#define PLLC3_MISC 0x500 42#define PLLM_BASE 0x90 43#define PLLM_OUT 0x94 44#define PLLM_MISC 0x9c 45#define PLLP_BASE 0xa0 46#define PLLP_MISC 0xac 47#define PLLA_BASE 0xb0 48#define PLLA_MISC 0xbc 49#define PLLD_BASE 0xd0 50#define PLLD_MISC 0xdc 51#define PLLU_BASE 0xc0 52#define PLLU_MISC 0xcc 53#define PLLX_BASE 0xe0 54#define PLLX_MISC 0xe4 55#define PLLX_MISC2 0x514 56#define PLLX_MISC3 0x518 57#define PLLE_BASE 0xe8 58#define PLLE_MISC 0xec 59#define PLLD2_BASE 0x4b8 60#define PLLD2_MISC 0x4bc 61#define PLLE_AUX 0x48c 62#define PLLRE_BASE 0x4c4 63#define PLLRE_MISC 0x4c8 64#define PLLDP_BASE 0x590 65#define PLLDP_MISC 0x594 66#define PLLC4_BASE 0x5a4 67#define PLLC4_MISC 0x5a8 68 69#define PLLC_IDDQ_BIT 26 70#define PLLRE_IDDQ_BIT 16 71#define PLLSS_IDDQ_BIT 19 72 73#define PLL_BASE_LOCK BIT(27) 74#define PLLE_MISC_LOCK BIT(11) 75#define PLLRE_MISC_LOCK BIT(24) 76 77#define PLL_MISC_LOCK_ENABLE 18 78#define PLLC_MISC_LOCK_ENABLE 24 79#define PLLDU_MISC_LOCK_ENABLE 22 80#define PLLE_MISC_LOCK_ENABLE 9 81#define PLLRE_MISC_LOCK_ENABLE 30 82#define PLLSS_MISC_LOCK_ENABLE 30 83 84#define PLLXC_SW_MAX_P 6 85 86#define PMC_PLLM_WB0_OVERRIDE 0x1dc 87#define PMC_PLLM_WB0_OVERRIDE_2 0x2b0 88 89#define UTMIP_PLL_CFG2 0x488 90#define UTMIP_PLL_CFG2_STABLE_COUNT(x) (((x) & 0xffff) << 6) 91#define UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(x) (((x) & 0x3f) << 18) 92#define UTMIP_PLL_CFG2_FORCE_PD_SAMP_A_POWERDOWN BIT(0) 93#define UTMIP_PLL_CFG2_FORCE_PD_SAMP_B_POWERDOWN BIT(2) 94#define UTMIP_PLL_CFG2_FORCE_PD_SAMP_C_POWERDOWN BIT(4) 95 96#define UTMIP_PLL_CFG1 0x484 97#define UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(x) (((x) & 0x1f) << 6) 98#define UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(x) (((x) & 0xfff) << 0) 99#define UTMIP_PLL_CFG1_FORCE_PLLU_POWERUP BIT(17) 100#define UTMIP_PLL_CFG1_FORCE_PLLU_POWERDOWN BIT(16) 101#define UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERUP BIT(15) 102#define UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN BIT(14) 103#define UTMIP_PLL_CFG1_FORCE_PLL_ACTIVE_POWERDOWN BIT(12) 104 105#define UTMIPLL_HW_PWRDN_CFG0 0x52c 106#define UTMIPLL_HW_PWRDN_CFG0_SEQ_START_STATE BIT(25) 107#define UTMIPLL_HW_PWRDN_CFG0_SEQ_ENABLE BIT(24) 108#define UTMIPLL_HW_PWRDN_CFG0_USE_LOCKDET BIT(6) 109#define UTMIPLL_HW_PWRDN_CFG0_SEQ_RESET_INPUT_VALUE BIT(5) 110#define UTMIPLL_HW_PWRDN_CFG0_SEQ_IN_SWCTL BIT(4) 111#define UTMIPLL_HW_PWRDN_CFG0_CLK_ENABLE_SWCTL BIT(2) 112#define UTMIPLL_HW_PWRDN_CFG0_IDDQ_OVERRIDE BIT(1) 113#define UTMIPLL_HW_PWRDN_CFG0_IDDQ_SWCTL BIT(0) 114 115/* Tegra CPU clock and reset control regs */ 116#define CLK_RST_CONTROLLER_CPU_CMPLX_STATUS 0x470 117 118#ifdef CONFIG_PM_SLEEP 119static struct cpu_clk_suspend_context { 120 u32 clk_csite_src; 121} tegra124_cpu_clk_sctx; 122#endif 123 124static void __iomem *clk_base; 125static void __iomem *pmc_base; 126 127static unsigned long osc_freq; 128static unsigned long pll_ref_freq; 129 130static DEFINE_SPINLOCK(pll_d_lock); 131static DEFINE_SPINLOCK(pll_d2_lock); 132static DEFINE_SPINLOCK(pll_e_lock); 133static DEFINE_SPINLOCK(pll_re_lock); 134static DEFINE_SPINLOCK(pll_u_lock); 135 136/* possible OSC frequencies in Hz */ 137static unsigned long tegra124_input_freq[] = { 138 [0] = 13000000, 139 [1] = 16800000, 140 [4] = 19200000, 141 [5] = 38400000, 142 [8] = 12000000, 143 [9] = 48000000, 144 [12] = 260000000, 145}; 146 147static const char *mux_plld_out0_plld2_out0[] = { 148 "pll_d_out0", "pll_d2_out0", 149}; 150#define mux_plld_out0_plld2_out0_idx NULL 151 152static const char *mux_pllmcp_clkm[] = { 153 "pll_m", "pll_c", "pll_p", "clk_m", "pll_m_ud", "pll_c2", "pll_c3", 154}; 155#define mux_pllmcp_clkm_idx NULL 156 157static struct div_nmp pllxc_nmp = { 158 .divm_shift = 0, 159 .divm_width = 8, 160 .divn_shift = 8, 161 .divn_width = 8, 162 .divp_shift = 20, 163 .divp_width = 4, 164}; 165 166static struct pdiv_map pllxc_p[] = { 167 { .pdiv = 1, .hw_val = 0 }, 168 { .pdiv = 2, .hw_val = 1 }, 169 { .pdiv = 3, .hw_val = 2 }, 170 { .pdiv = 4, .hw_val = 3 }, 171 { .pdiv = 5, .hw_val = 4 }, 172 { .pdiv = 6, .hw_val = 5 }, 173 { .pdiv = 8, .hw_val = 6 }, 174 { .pdiv = 10, .hw_val = 7 }, 175 { .pdiv = 12, .hw_val = 8 }, 176 { .pdiv = 16, .hw_val = 9 }, 177 { .pdiv = 12, .hw_val = 10 }, 178 { .pdiv = 16, .hw_val = 11 }, 179 { .pdiv = 20, .hw_val = 12 }, 180 { .pdiv = 24, .hw_val = 13 }, 181 { .pdiv = 32, .hw_val = 14 }, 182 { .pdiv = 0, .hw_val = 0 }, 183}; 184 185static struct tegra_clk_pll_freq_table pll_x_freq_table[] = { 186 /* 1 GHz */ 187 {12000000, 1000000000, 83, 0, 1}, /* actual: 996.0 MHz */ 188 {13000000, 1000000000, 76, 0, 1}, /* actual: 988.0 MHz */ 189 {16800000, 1000000000, 59, 0, 1}, /* actual: 991.2 MHz */ 190 {19200000, 1000000000, 52, 0, 1}, /* actual: 998.4 MHz */ 191 {26000000, 1000000000, 76, 1, 1}, /* actual: 988.0 MHz */ 192 {0, 0, 0, 0, 0, 0}, 193}; 194 195static struct tegra_clk_pll_params pll_x_params = { 196 .input_min = 12000000, 197 .input_max = 800000000, 198 .cf_min = 12000000, 199 .cf_max = 19200000, /* s/w policy, h/w capability 50 MHz */ 200 .vco_min = 700000000, 201 .vco_max = 3000000000UL, 202 .base_reg = PLLX_BASE, 203 .misc_reg = PLLX_MISC, 204 .lock_mask = PLL_BASE_LOCK, 205 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE, 206 .lock_delay = 300, 207 .iddq_reg = PLLX_MISC3, 208 .iddq_bit_idx = 3, 209 .max_p = 6, 210 .dyn_ramp_reg = PLLX_MISC2, 211 .stepa_shift = 16, 212 .stepb_shift = 24, 213 .pdiv_tohw = pllxc_p, 214 .div_nmp = &pllxc_nmp, 215 .freq_table = pll_x_freq_table, 216 .flags = TEGRA_PLL_USE_LOCK, 217}; 218 219static struct tegra_clk_pll_freq_table pll_c_freq_table[] = { 220 { 12000000, 624000000, 104, 1, 2}, 221 { 12000000, 600000000, 100, 1, 2}, 222 { 13000000, 600000000, 92, 1, 2}, /* actual: 598.0 MHz */ 223 { 16800000, 600000000, 71, 1, 2}, /* actual: 596.4 MHz */ 224 { 19200000, 600000000, 62, 1, 2}, /* actual: 595.2 MHz */ 225 { 26000000, 600000000, 92, 2, 2}, /* actual: 598.0 MHz */ 226 { 0, 0, 0, 0, 0, 0 }, 227}; 228 229static struct tegra_clk_pll_params pll_c_params = { 230 .input_min = 12000000, 231 .input_max = 800000000, 232 .cf_min = 12000000, 233 .cf_max = 19200000, /* s/w policy, h/w capability 50 MHz */ 234 .vco_min = 600000000, 235 .vco_max = 1400000000, 236 .base_reg = PLLC_BASE, 237 .misc_reg = PLLC_MISC, 238 .lock_mask = PLL_BASE_LOCK, 239 .lock_enable_bit_idx = PLLC_MISC_LOCK_ENABLE, 240 .lock_delay = 300, 241 .iddq_reg = PLLC_MISC, 242 .iddq_bit_idx = PLLC_IDDQ_BIT, 243 .max_p = PLLXC_SW_MAX_P, 244 .dyn_ramp_reg = PLLC_MISC2, 245 .stepa_shift = 17, 246 .stepb_shift = 9, 247 .pdiv_tohw = pllxc_p, 248 .div_nmp = &pllxc_nmp, 249 .freq_table = pll_c_freq_table, 250 .flags = TEGRA_PLL_USE_LOCK, 251}; 252 253static struct div_nmp pllcx_nmp = { 254 .divm_shift = 0, 255 .divm_width = 2, 256 .divn_shift = 8, 257 .divn_width = 8, 258 .divp_shift = 20, 259 .divp_width = 3, 260}; 261 262static struct pdiv_map pllc_p[] = { 263 { .pdiv = 1, .hw_val = 0 }, 264 { .pdiv = 2, .hw_val = 1 }, 265 { .pdiv = 3, .hw_val = 2 }, 266 { .pdiv = 4, .hw_val = 3 }, 267 { .pdiv = 6, .hw_val = 4 }, 268 { .pdiv = 8, .hw_val = 5 }, 269 { .pdiv = 12, .hw_val = 6 }, 270 { .pdiv = 16, .hw_val = 7 }, 271 { .pdiv = 0, .hw_val = 0 }, 272}; 273 274static struct tegra_clk_pll_freq_table pll_cx_freq_table[] = { 275 {12000000, 600000000, 100, 1, 2}, 276 {13000000, 600000000, 92, 1, 2}, /* actual: 598.0 MHz */ 277 {16800000, 600000000, 71, 1, 2}, /* actual: 596.4 MHz */ 278 {19200000, 600000000, 62, 1, 2}, /* actual: 595.2 MHz */ 279 {26000000, 600000000, 92, 2, 2}, /* actual: 598.0 MHz */ 280 {0, 0, 0, 0, 0, 0}, 281}; 282 283static struct tegra_clk_pll_params pll_c2_params = { 284 .input_min = 12000000, 285 .input_max = 48000000, 286 .cf_min = 12000000, 287 .cf_max = 19200000, 288 .vco_min = 600000000, 289 .vco_max = 1200000000, 290 .base_reg = PLLC2_BASE, 291 .misc_reg = PLLC2_MISC, 292 .lock_mask = PLL_BASE_LOCK, 293 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE, 294 .lock_delay = 300, 295 .pdiv_tohw = pllc_p, 296 .div_nmp = &pllcx_nmp, 297 .max_p = 7, 298 .ext_misc_reg[0] = 0x4f0, 299 .ext_misc_reg[1] = 0x4f4, 300 .ext_misc_reg[2] = 0x4f8, 301 .freq_table = pll_cx_freq_table, 302 .flags = TEGRA_PLL_USE_LOCK, 303}; 304 305static struct tegra_clk_pll_params pll_c3_params = { 306 .input_min = 12000000, 307 .input_max = 48000000, 308 .cf_min = 12000000, 309 .cf_max = 19200000, 310 .vco_min = 600000000, 311 .vco_max = 1200000000, 312 .base_reg = PLLC3_BASE, 313 .misc_reg = PLLC3_MISC, 314 .lock_mask = PLL_BASE_LOCK, 315 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE, 316 .lock_delay = 300, 317 .pdiv_tohw = pllc_p, 318 .div_nmp = &pllcx_nmp, 319 .max_p = 7, 320 .ext_misc_reg[0] = 0x504, 321 .ext_misc_reg[1] = 0x508, 322 .ext_misc_reg[2] = 0x50c, 323 .freq_table = pll_cx_freq_table, 324 .flags = TEGRA_PLL_USE_LOCK, 325}; 326 327static struct div_nmp pllss_nmp = { 328 .divm_shift = 0, 329 .divm_width = 8, 330 .divn_shift = 8, 331 .divn_width = 8, 332 .divp_shift = 20, 333 .divp_width = 4, 334}; 335 336static struct pdiv_map pll12g_ssd_esd_p[] = { 337 { .pdiv = 1, .hw_val = 0 }, 338 { .pdiv = 2, .hw_val = 1 }, 339 { .pdiv = 3, .hw_val = 2 }, 340 { .pdiv = 4, .hw_val = 3 }, 341 { .pdiv = 5, .hw_val = 4 }, 342 { .pdiv = 6, .hw_val = 5 }, 343 { .pdiv = 8, .hw_val = 6 }, 344 { .pdiv = 10, .hw_val = 7 }, 345 { .pdiv = 12, .hw_val = 8 }, 346 { .pdiv = 16, .hw_val = 9 }, 347 { .pdiv = 12, .hw_val = 10 }, 348 { .pdiv = 16, .hw_val = 11 }, 349 { .pdiv = 20, .hw_val = 12 }, 350 { .pdiv = 24, .hw_val = 13 }, 351 { .pdiv = 32, .hw_val = 14 }, 352 { .pdiv = 0, .hw_val = 0 }, 353}; 354 355static struct tegra_clk_pll_freq_table pll_c4_freq_table[] = { 356 { 12000000, 600000000, 100, 1, 1}, 357 { 13000000, 600000000, 92, 1, 1}, /* actual: 598.0 MHz */ 358 { 16800000, 600000000, 71, 1, 1}, /* actual: 596.4 MHz */ 359 { 19200000, 600000000, 62, 1, 1}, /* actual: 595.2 MHz */ 360 { 26000000, 600000000, 92, 2, 1}, /* actual: 598.0 MHz */ 361 { 0, 0, 0, 0, 0, 0 }, 362}; 363 364static struct tegra_clk_pll_params pll_c4_params = { 365 .input_min = 12000000, 366 .input_max = 1000000000, 367 .cf_min = 12000000, 368 .cf_max = 19200000, /* s/w policy, h/w capability 38 MHz */ 369 .vco_min = 600000000, 370 .vco_max = 1200000000, 371 .base_reg = PLLC4_BASE, 372 .misc_reg = PLLC4_MISC, 373 .lock_mask = PLL_BASE_LOCK, 374 .lock_enable_bit_idx = PLLSS_MISC_LOCK_ENABLE, 375 .lock_delay = 300, 376 .iddq_reg = PLLC4_BASE, 377 .iddq_bit_idx = PLLSS_IDDQ_BIT, 378 .pdiv_tohw = pll12g_ssd_esd_p, 379 .div_nmp = &pllss_nmp, 380 .ext_misc_reg[0] = 0x5ac, 381 .ext_misc_reg[1] = 0x5b0, 382 .ext_misc_reg[2] = 0x5b4, 383 .freq_table = pll_c4_freq_table, 384}; 385 386static struct pdiv_map pllm_p[] = { 387 { .pdiv = 1, .hw_val = 0 }, 388 { .pdiv = 2, .hw_val = 1 }, 389 { .pdiv = 0, .hw_val = 0 }, 390}; 391 392static struct tegra_clk_pll_freq_table pll_m_freq_table[] = { 393 {12000000, 800000000, 66, 1, 1}, /* actual: 792.0 MHz */ 394 {13000000, 800000000, 61, 1, 1}, /* actual: 793.0 MHz */ 395 {16800000, 800000000, 47, 1, 1}, /* actual: 789.6 MHz */ 396 {19200000, 800000000, 41, 1, 1}, /* actual: 787.2 MHz */ 397 {26000000, 800000000, 61, 2, 1}, /* actual: 793.0 MHz */ 398 {0, 0, 0, 0, 0, 0}, 399}; 400 401static struct div_nmp pllm_nmp = { 402 .divm_shift = 0, 403 .divm_width = 8, 404 .override_divm_shift = 0, 405 .divn_shift = 8, 406 .divn_width = 8, 407 .override_divn_shift = 8, 408 .divp_shift = 20, 409 .divp_width = 1, 410 .override_divp_shift = 27, 411}; 412 413static struct tegra_clk_pll_params pll_m_params = { 414 .input_min = 12000000, 415 .input_max = 500000000, 416 .cf_min = 12000000, 417 .cf_max = 19200000, /* s/w policy, h/w capability 50 MHz */ 418 .vco_min = 400000000, 419 .vco_max = 1066000000, 420 .base_reg = PLLM_BASE, 421 .misc_reg = PLLM_MISC, 422 .lock_mask = PLL_BASE_LOCK, 423 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE, 424 .lock_delay = 300, 425 .max_p = 2, 426 .pdiv_tohw = pllm_p, 427 .div_nmp = &pllm_nmp, 428 .pmc_divnm_reg = PMC_PLLM_WB0_OVERRIDE, 429 .pmc_divp_reg = PMC_PLLM_WB0_OVERRIDE_2, 430 .freq_table = pll_m_freq_table, 431 .flags = TEGRA_PLL_USE_LOCK, 432}; 433 434static struct tegra_clk_pll_freq_table pll_e_freq_table[] = { 435 /* PLLE special case: use cpcon field to store cml divider value */ 436 {336000000, 100000000, 100, 21, 16, 11}, 437 {312000000, 100000000, 200, 26, 24, 13}, 438 {13000000, 100000000, 200, 1, 26, 13}, 439 {12000000, 100000000, 200, 1, 24, 13}, 440 {0, 0, 0, 0, 0, 0}, 441}; 442 443static struct div_nmp plle_nmp = { 444 .divm_shift = 0, 445 .divm_width = 8, 446 .divn_shift = 8, 447 .divn_width = 8, 448 .divp_shift = 24, 449 .divp_width = 4, 450}; 451 452static struct tegra_clk_pll_params pll_e_params = { 453 .input_min = 12000000, 454 .input_max = 1000000000, 455 .cf_min = 12000000, 456 .cf_max = 75000000, 457 .vco_min = 1600000000, 458 .vco_max = 2400000000U, 459 .base_reg = PLLE_BASE, 460 .misc_reg = PLLE_MISC, 461 .aux_reg = PLLE_AUX, 462 .lock_mask = PLLE_MISC_LOCK, 463 .lock_enable_bit_idx = PLLE_MISC_LOCK_ENABLE, 464 .lock_delay = 300, 465 .div_nmp = &plle_nmp, 466 .freq_table = pll_e_freq_table, 467 .flags = TEGRA_PLL_FIXED, 468 .fixed_rate = 100000000, 469}; 470 471static const struct clk_div_table pll_re_div_table[] = { 472 { .val = 0, .div = 1 }, 473 { .val = 1, .div = 2 }, 474 { .val = 2, .div = 3 }, 475 { .val = 3, .div = 4 }, 476 { .val = 4, .div = 5 }, 477 { .val = 5, .div = 6 }, 478 { .val = 0, .div = 0 }, 479}; 480 481static struct div_nmp pllre_nmp = { 482 .divm_shift = 0, 483 .divm_width = 8, 484 .divn_shift = 8, 485 .divn_width = 8, 486 .divp_shift = 16, 487 .divp_width = 4, 488}; 489 490static struct tegra_clk_pll_params pll_re_vco_params = { 491 .input_min = 12000000, 492 .input_max = 1000000000, 493 .cf_min = 12000000, 494 .cf_max = 19200000, /* s/w policy, h/w capability 38 MHz */ 495 .vco_min = 300000000, 496 .vco_max = 600000000, 497 .base_reg = PLLRE_BASE, 498 .misc_reg = PLLRE_MISC, 499 .lock_mask = PLLRE_MISC_LOCK, 500 .lock_enable_bit_idx = PLLRE_MISC_LOCK_ENABLE, 501 .lock_delay = 300, 502 .iddq_reg = PLLRE_MISC, 503 .iddq_bit_idx = PLLRE_IDDQ_BIT, 504 .div_nmp = &pllre_nmp, 505 .flags = TEGRA_PLL_USE_LOCK, 506}; 507 508static struct div_nmp pllp_nmp = { 509 .divm_shift = 0, 510 .divm_width = 5, 511 .divn_shift = 8, 512 .divn_width = 10, 513 .divp_shift = 20, 514 .divp_width = 3, 515}; 516 517static struct tegra_clk_pll_freq_table pll_p_freq_table[] = { 518 {12000000, 408000000, 408, 12, 0, 8}, 519 {13000000, 408000000, 408, 13, 0, 8}, 520 {16800000, 408000000, 340, 14, 0, 8}, 521 {19200000, 408000000, 340, 16, 0, 8}, 522 {26000000, 408000000, 408, 26, 0, 8}, 523 {0, 0, 0, 0, 0, 0}, 524}; 525 526static struct tegra_clk_pll_params pll_p_params = { 527 .input_min = 2000000, 528 .input_max = 31000000, 529 .cf_min = 1000000, 530 .cf_max = 6000000, 531 .vco_min = 200000000, 532 .vco_max = 700000000, 533 .base_reg = PLLP_BASE, 534 .misc_reg = PLLP_MISC, 535 .lock_mask = PLL_BASE_LOCK, 536 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE, 537 .lock_delay = 300, 538 .div_nmp = &pllp_nmp, 539 .freq_table = pll_p_freq_table, 540 .fixed_rate = 408000000, 541 .flags = TEGRA_PLL_FIXED | TEGRA_PLL_USE_LOCK, 542}; 543 544static struct tegra_clk_pll_freq_table pll_a_freq_table[] = { 545 {9600000, 282240000, 147, 5, 0, 4}, 546 {9600000, 368640000, 192, 5, 0, 4}, 547 {9600000, 240000000, 200, 8, 0, 8}, 548 549 {28800000, 282240000, 245, 25, 0, 8}, 550 {28800000, 368640000, 320, 25, 0, 8}, 551 {28800000, 240000000, 200, 24, 0, 8}, 552 {0, 0, 0, 0, 0, 0}, 553}; 554 555static struct tegra_clk_pll_params pll_a_params = { 556 .input_min = 2000000, 557 .input_max = 31000000, 558 .cf_min = 1000000, 559 .cf_max = 6000000, 560 .vco_min = 200000000, 561 .vco_max = 700000000, 562 .base_reg = PLLA_BASE, 563 .misc_reg = PLLA_MISC, 564 .lock_mask = PLL_BASE_LOCK, 565 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE, 566 .lock_delay = 300, 567 .div_nmp = &pllp_nmp, 568 .freq_table = pll_a_freq_table, 569 .flags = TEGRA_PLL_HAS_CPCON | TEGRA_PLL_USE_LOCK, 570}; 571 572static struct div_nmp plld_nmp = { 573 .divm_shift = 0, 574 .divm_width = 5, 575 .divn_shift = 8, 576 .divn_width = 11, 577 .divp_shift = 20, 578 .divp_width = 3, 579}; 580 581static struct tegra_clk_pll_freq_table pll_d_freq_table[] = { 582 {12000000, 216000000, 864, 12, 4, 12}, 583 {13000000, 216000000, 864, 13, 4, 12}, 584 {16800000, 216000000, 720, 14, 4, 12}, 585 {19200000, 216000000, 720, 16, 4, 12}, 586 {26000000, 216000000, 864, 26, 4, 12}, 587 588 {12000000, 594000000, 594, 12, 1, 12}, 589 {13000000, 594000000, 594, 13, 1, 12}, 590 {16800000, 594000000, 495, 14, 1, 12}, 591 {19200000, 594000000, 495, 16, 1, 12}, 592 {26000000, 594000000, 594, 26, 1, 12}, 593 594 {12000000, 1000000000, 1000, 12, 1, 12}, 595 {13000000, 1000000000, 1000, 13, 1, 12}, 596 {19200000, 1000000000, 625, 12, 1, 12}, 597 {26000000, 1000000000, 1000, 26, 1, 12}, 598 599 {0, 0, 0, 0, 0, 0}, 600}; 601 602static struct tegra_clk_pll_params pll_d_params = { 603 .input_min = 2000000, 604 .input_max = 40000000, 605 .cf_min = 1000000, 606 .cf_max = 6000000, 607 .vco_min = 500000000, 608 .vco_max = 1000000000, 609 .base_reg = PLLD_BASE, 610 .misc_reg = PLLD_MISC, 611 .lock_mask = PLL_BASE_LOCK, 612 .lock_enable_bit_idx = PLLDU_MISC_LOCK_ENABLE, 613 .lock_delay = 1000, 614 .div_nmp = &plld_nmp, 615 .freq_table = pll_d_freq_table, 616 .flags = TEGRA_PLL_HAS_CPCON | TEGRA_PLL_SET_LFCON | 617 TEGRA_PLL_USE_LOCK, 618}; 619 620static struct tegra_clk_pll_freq_table tegra124_pll_d2_freq_table[] = { 621 { 12000000, 594000000, 99, 1, 2}, 622 { 13000000, 594000000, 91, 1, 2}, /* actual: 591.5 MHz */ 623 { 16800000, 594000000, 71, 1, 2}, /* actual: 596.4 MHz */ 624 { 19200000, 594000000, 62, 1, 2}, /* actual: 595.2 MHz */ 625 { 26000000, 594000000, 91, 2, 2}, /* actual: 591.5 MHz */ 626 { 0, 0, 0, 0, 0, 0 }, 627}; 628 629static struct tegra_clk_pll_params tegra124_pll_d2_params = { 630 .input_min = 12000000, 631 .input_max = 1000000000, 632 .cf_min = 12000000, 633 .cf_max = 19200000, /* s/w policy, h/w capability 38 MHz */ 634 .vco_min = 600000000, 635 .vco_max = 1200000000, 636 .base_reg = PLLD2_BASE, 637 .misc_reg = PLLD2_MISC, 638 .lock_mask = PLL_BASE_LOCK, 639 .lock_enable_bit_idx = PLLSS_MISC_LOCK_ENABLE, 640 .lock_delay = 300, 641 .iddq_reg = PLLD2_BASE, 642 .iddq_bit_idx = PLLSS_IDDQ_BIT, 643 .pdiv_tohw = pll12g_ssd_esd_p, 644 .div_nmp = &pllss_nmp, 645 .ext_misc_reg[0] = 0x570, 646 .ext_misc_reg[1] = 0x574, 647 .ext_misc_reg[2] = 0x578, 648 .max_p = 15, 649 .freq_table = tegra124_pll_d2_freq_table, 650}; 651 652static struct tegra_clk_pll_freq_table pll_dp_freq_table[] = { 653 { 12000000, 600000000, 100, 1, 1}, 654 { 13000000, 600000000, 92, 1, 1}, /* actual: 598.0 MHz */ 655 { 16800000, 600000000, 71, 1, 1}, /* actual: 596.4 MHz */ 656 { 19200000, 600000000, 62, 1, 1}, /* actual: 595.2 MHz */ 657 { 26000000, 600000000, 92, 2, 1}, /* actual: 598.0 MHz */ 658 { 0, 0, 0, 0, 0, 0 }, 659}; 660 661static struct tegra_clk_pll_params pll_dp_params = { 662 .input_min = 12000000, 663 .input_max = 1000000000, 664 .cf_min = 12000000, 665 .cf_max = 19200000, /* s/w policy, h/w capability 38 MHz */ 666 .vco_min = 600000000, 667 .vco_max = 1200000000, 668 .base_reg = PLLDP_BASE, 669 .misc_reg = PLLDP_MISC, 670 .lock_mask = PLL_BASE_LOCK, 671 .lock_enable_bit_idx = PLLSS_MISC_LOCK_ENABLE, 672 .lock_delay = 300, 673 .iddq_reg = PLLDP_BASE, 674 .iddq_bit_idx = PLLSS_IDDQ_BIT, 675 .pdiv_tohw = pll12g_ssd_esd_p, 676 .div_nmp = &pllss_nmp, 677 .ext_misc_reg[0] = 0x598, 678 .ext_misc_reg[1] = 0x59c, 679 .ext_misc_reg[2] = 0x5a0, 680 .max_p = 5, 681 .freq_table = pll_dp_freq_table, 682}; 683 684static struct pdiv_map pllu_p[] = { 685 { .pdiv = 1, .hw_val = 1 }, 686 { .pdiv = 2, .hw_val = 0 }, 687 { .pdiv = 0, .hw_val = 0 }, 688}; 689 690static struct div_nmp pllu_nmp = { 691 .divm_shift = 0, 692 .divm_width = 5, 693 .divn_shift = 8, 694 .divn_width = 10, 695 .divp_shift = 20, 696 .divp_width = 1, 697}; 698 699static struct tegra_clk_pll_freq_table pll_u_freq_table[] = { 700 {12000000, 480000000, 960, 12, 2, 12}, 701 {13000000, 480000000, 960, 13, 2, 12}, 702 {16800000, 480000000, 400, 7, 2, 5}, 703 {19200000, 480000000, 200, 4, 2, 3}, 704 {26000000, 480000000, 960, 26, 2, 12}, 705 {0, 0, 0, 0, 0, 0}, 706}; 707 708static struct tegra_clk_pll_params pll_u_params = { 709 .input_min = 2000000, 710 .input_max = 40000000, 711 .cf_min = 1000000, 712 .cf_max = 6000000, 713 .vco_min = 480000000, 714 .vco_max = 960000000, 715 .base_reg = PLLU_BASE, 716 .misc_reg = PLLU_MISC, 717 .lock_mask = PLL_BASE_LOCK, 718 .lock_enable_bit_idx = PLLDU_MISC_LOCK_ENABLE, 719 .lock_delay = 1000, 720 .pdiv_tohw = pllu_p, 721 .div_nmp = &pllu_nmp, 722 .freq_table = pll_u_freq_table, 723 .flags = TEGRA_PLLU | TEGRA_PLL_HAS_CPCON | TEGRA_PLL_SET_LFCON | 724 TEGRA_PLL_USE_LOCK, 725}; 726 727struct utmi_clk_param { 728 /* Oscillator Frequency in KHz */ 729 u32 osc_frequency; 730 /* UTMIP PLL Enable Delay Count */ 731 u8 enable_delay_count; 732 /* UTMIP PLL Stable count */ 733 u8 stable_count; 734 /* UTMIP PLL Active delay count */ 735 u8 active_delay_count; 736 /* UTMIP PLL Xtal frequency count */ 737 u8 xtal_freq_count; 738}; 739 740static const struct utmi_clk_param utmi_parameters[] = { 741 {.osc_frequency = 13000000, .enable_delay_count = 0x02, 742 .stable_count = 0x33, .active_delay_count = 0x05, 743 .xtal_freq_count = 0x7F}, 744 {.osc_frequency = 19200000, .enable_delay_count = 0x03, 745 .stable_count = 0x4B, .active_delay_count = 0x06, 746 .xtal_freq_count = 0xBB}, 747 {.osc_frequency = 12000000, .enable_delay_count = 0x02, 748 .stable_count = 0x2F, .active_delay_count = 0x04, 749 .xtal_freq_count = 0x76}, 750 {.osc_frequency = 26000000, .enable_delay_count = 0x04, 751 .stable_count = 0x66, .active_delay_count = 0x09, 752 .xtal_freq_count = 0xFE}, 753 {.osc_frequency = 16800000, .enable_delay_count = 0x03, 754 .stable_count = 0x41, .active_delay_count = 0x0A, 755 .xtal_freq_count = 0xA4}, 756}; 757 758static struct tegra_clk tegra124_clks[tegra_clk_max] __initdata = { 759 [tegra_clk_ispb] = { .dt_id = TEGRA124_CLK_ISPB, .present = true }, 760 [tegra_clk_rtc] = { .dt_id = TEGRA124_CLK_RTC, .present = true }, 761 [tegra_clk_timer] = { .dt_id = TEGRA124_CLK_TIMER, .present = true }, 762 [tegra_clk_uarta] = { .dt_id = TEGRA124_CLK_UARTA, .present = true }, 763 [tegra_clk_sdmmc2_8] = { .dt_id = TEGRA124_CLK_SDMMC2, .present = true }, 764 [tegra_clk_i2s1] = { .dt_id = TEGRA124_CLK_I2S1, .present = true }, 765 [tegra_clk_i2c1] = { .dt_id = TEGRA124_CLK_I2C1, .present = true }, 766 [tegra_clk_sdmmc1_8] = { .dt_id = TEGRA124_CLK_SDMMC1, .present = true }, 767 [tegra_clk_sdmmc4_8] = { .dt_id = TEGRA124_CLK_SDMMC4, .present = true }, 768 [tegra_clk_pwm] = { .dt_id = TEGRA124_CLK_PWM, .present = true }, 769 [tegra_clk_i2s2] = { .dt_id = TEGRA124_CLK_I2S2, .present = true }, 770 [tegra_clk_usbd] = { .dt_id = TEGRA124_CLK_USBD, .present = true }, 771 [tegra_clk_isp_8] = { .dt_id = TEGRA124_CLK_ISP, .present = true }, 772 [tegra_clk_disp2] = { .dt_id = TEGRA124_CLK_DISP2, .present = true }, 773 [tegra_clk_disp1] = { .dt_id = TEGRA124_CLK_DISP1, .present = true }, 774 [tegra_clk_host1x_8] = { .dt_id = TEGRA124_CLK_HOST1X, .present = true }, 775 [tegra_clk_vcp] = { .dt_id = TEGRA124_CLK_VCP, .present = true }, 776 [tegra_clk_i2s0] = { .dt_id = TEGRA124_CLK_I2S0, .present = true }, 777 [tegra_clk_apbdma] = { .dt_id = TEGRA124_CLK_APBDMA, .present = true }, 778 [tegra_clk_kbc] = { .dt_id = TEGRA124_CLK_KBC, .present = true }, 779 [tegra_clk_kfuse] = { .dt_id = TEGRA124_CLK_KFUSE, .present = true }, 780 [tegra_clk_sbc1] = { .dt_id = TEGRA124_CLK_SBC1, .present = true }, 781 [tegra_clk_nor] = { .dt_id = TEGRA124_CLK_NOR, .present = true }, 782 [tegra_clk_sbc2] = { .dt_id = TEGRA124_CLK_SBC2, .present = true }, 783 [tegra_clk_sbc3] = { .dt_id = TEGRA124_CLK_SBC3, .present = true }, 784 [tegra_clk_i2c5] = { .dt_id = TEGRA124_CLK_I2C5, .present = true }, 785 [tegra_clk_dsia] = { .dt_id = TEGRA124_CLK_DSIA, .present = true }, 786 [tegra_clk_mipi] = { .dt_id = TEGRA124_CLK_MIPI, .present = true }, 787 [tegra_clk_hdmi] = { .dt_id = TEGRA124_CLK_HDMI, .present = true }, 788 [tegra_clk_csi] = { .dt_id = TEGRA124_CLK_CSI, .present = true }, 789 [tegra_clk_i2c2] = { .dt_id = TEGRA124_CLK_I2C2, .present = true }, 790 [tegra_clk_uartc] = { .dt_id = TEGRA124_CLK_UARTC, .present = true }, 791 [tegra_clk_mipi_cal] = { .dt_id = TEGRA124_CLK_MIPI_CAL, .present = true }, 792 [tegra_clk_emc] = { .dt_id = TEGRA124_CLK_EMC, .present = true }, 793 [tegra_clk_usb2] = { .dt_id = TEGRA124_CLK_USB2, .present = true }, 794 [tegra_clk_usb3] = { .dt_id = TEGRA124_CLK_USB3, .present = true }, 795 [tegra_clk_vde_8] = { .dt_id = TEGRA124_CLK_VDE, .present = true }, 796 [tegra_clk_bsea] = { .dt_id = TEGRA124_CLK_BSEA, .present = true }, 797 [tegra_clk_bsev] = { .dt_id = TEGRA124_CLK_BSEV, .present = true }, 798 [tegra_clk_uartd] = { .dt_id = TEGRA124_CLK_UARTD, .present = true }, 799 [tegra_clk_i2c3] = { .dt_id = TEGRA124_CLK_I2C3, .present = true }, 800 [tegra_clk_sbc4] = { .dt_id = TEGRA124_CLK_SBC4, .present = true }, 801 [tegra_clk_sdmmc3_8] = { .dt_id = TEGRA124_CLK_SDMMC3, .present = true }, 802 [tegra_clk_pcie] = { .dt_id = TEGRA124_CLK_PCIE, .present = true }, 803 [tegra_clk_owr] = { .dt_id = TEGRA124_CLK_OWR, .present = true }, 804 [tegra_clk_afi] = { .dt_id = TEGRA124_CLK_AFI, .present = true }, 805 [tegra_clk_csite] = { .dt_id = TEGRA124_CLK_CSITE, .present = true }, 806 [tegra_clk_la] = { .dt_id = TEGRA124_CLK_LA, .present = true }, 807 [tegra_clk_trace] = { .dt_id = TEGRA124_CLK_TRACE, .present = true }, 808 [tegra_clk_soc_therm] = { .dt_id = TEGRA124_CLK_SOC_THERM, .present = true }, 809 [tegra_clk_dtv] = { .dt_id = TEGRA124_CLK_DTV, .present = true }, 810 [tegra_clk_i2cslow] = { .dt_id = TEGRA124_CLK_I2CSLOW, .present = true }, 811 [tegra_clk_dsib] = { .dt_id = TEGRA124_CLK_DSIB, .present = true }, 812 [tegra_clk_tsec] = { .dt_id = TEGRA124_CLK_TSEC, .present = true }, 813 [tegra_clk_xusb_host] = { .dt_id = TEGRA124_CLK_XUSB_HOST, .present = true }, 814 [tegra_clk_msenc] = { .dt_id = TEGRA124_CLK_MSENC, .present = true }, 815 [tegra_clk_csus] = { .dt_id = TEGRA124_CLK_CSUS, .present = true }, 816 [tegra_clk_mselect] = { .dt_id = TEGRA124_CLK_MSELECT, .present = true }, 817 [tegra_clk_tsensor] = { .dt_id = TEGRA124_CLK_TSENSOR, .present = true }, 818 [tegra_clk_i2s3] = { .dt_id = TEGRA124_CLK_I2S3, .present = true }, 819 [tegra_clk_i2s4] = { .dt_id = TEGRA124_CLK_I2S4, .present = true }, 820 [tegra_clk_i2c4] = { .dt_id = TEGRA124_CLK_I2C4, .present = true }, 821 [tegra_clk_sbc5] = { .dt_id = TEGRA124_CLK_SBC5, .present = true }, 822 [tegra_clk_sbc6] = { .dt_id = TEGRA124_CLK_SBC6, .present = true }, 823 [tegra_clk_d_audio] = { .dt_id = TEGRA124_CLK_D_AUDIO, .present = true }, 824 [tegra_clk_apbif] = { .dt_id = TEGRA124_CLK_APBIF, .present = true }, 825 [tegra_clk_dam0] = { .dt_id = TEGRA124_CLK_DAM0, .present = true }, 826 [tegra_clk_dam1] = { .dt_id = TEGRA124_CLK_DAM1, .present = true }, 827 [tegra_clk_dam2] = { .dt_id = TEGRA124_CLK_DAM2, .present = true }, 828 [tegra_clk_hda2codec_2x] = { .dt_id = TEGRA124_CLK_HDA2CODEC_2X, .present = true }, 829 [tegra_clk_audio0_2x] = { .dt_id = TEGRA124_CLK_AUDIO0_2X, .present = true }, 830 [tegra_clk_audio1_2x] = { .dt_id = TEGRA124_CLK_AUDIO1_2X, .present = true }, 831 [tegra_clk_audio2_2x] = { .dt_id = TEGRA124_CLK_AUDIO2_2X, .present = true }, 832 [tegra_clk_audio3_2x] = { .dt_id = TEGRA124_CLK_AUDIO3_2X, .present = true }, 833 [tegra_clk_audio4_2x] = { .dt_id = TEGRA124_CLK_AUDIO4_2X, .present = true }, 834 [tegra_clk_spdif_2x] = { .dt_id = TEGRA124_CLK_SPDIF_2X, .present = true }, 835 [tegra_clk_actmon] = { .dt_id = TEGRA124_CLK_ACTMON, .present = true }, 836 [tegra_clk_extern1] = { .dt_id = TEGRA124_CLK_EXTERN1, .present = true }, 837 [tegra_clk_extern2] = { .dt_id = TEGRA124_CLK_EXTERN2, .present = true }, 838 [tegra_clk_extern3] = { .dt_id = TEGRA124_CLK_EXTERN3, .present = true }, 839 [tegra_clk_sata_oob] = { .dt_id = TEGRA124_CLK_SATA_OOB, .present = true }, 840 [tegra_clk_sata] = { .dt_id = TEGRA124_CLK_SATA, .present = true }, 841 [tegra_clk_hda] = { .dt_id = TEGRA124_CLK_HDA, .present = true }, 842 [tegra_clk_se] = { .dt_id = TEGRA124_CLK_SE, .present = true }, 843 [tegra_clk_hda2hdmi] = { .dt_id = TEGRA124_CLK_HDA2HDMI, .present = true }, 844 [tegra_clk_sata_cold] = { .dt_id = TEGRA124_CLK_SATA_COLD, .present = true }, 845 [tegra_clk_cilab] = { .dt_id = TEGRA124_CLK_CILAB, .present = true }, 846 [tegra_clk_cilcd] = { .dt_id = TEGRA124_CLK_CILCD, .present = true }, 847 [tegra_clk_cile] = { .dt_id = TEGRA124_CLK_CILE, .present = true }, 848 [tegra_clk_dsialp] = { .dt_id = TEGRA124_CLK_DSIALP, .present = true }, 849 [tegra_clk_dsiblp] = { .dt_id = TEGRA124_CLK_DSIBLP, .present = true }, 850 [tegra_clk_entropy] = { .dt_id = TEGRA124_CLK_ENTROPY, .present = true }, 851 [tegra_clk_dds] = { .dt_id = TEGRA124_CLK_DDS, .present = true }, 852 [tegra_clk_dp2] = { .dt_id = TEGRA124_CLK_DP2, .present = true }, 853 [tegra_clk_amx] = { .dt_id = TEGRA124_CLK_AMX, .present = true }, 854 [tegra_clk_adx] = { .dt_id = TEGRA124_CLK_ADX, .present = true }, 855 [tegra_clk_xusb_ss] = { .dt_id = TEGRA124_CLK_XUSB_SS, .present = true }, 856 [tegra_clk_i2c6] = { .dt_id = TEGRA124_CLK_I2C6, .present = true }, 857 [tegra_clk_vim2_clk] = { .dt_id = TEGRA124_CLK_VIM2_CLK, .present = true }, 858 [tegra_clk_hdmi_audio] = { .dt_id = TEGRA124_CLK_HDMI_AUDIO, .present = true }, 859 [tegra_clk_clk72Mhz] = { .dt_id = TEGRA124_CLK_CLK72MHZ, .present = true }, 860 [tegra_clk_vic03] = { .dt_id = TEGRA124_CLK_VIC03, .present = true }, 861 [tegra_clk_adx1] = { .dt_id = TEGRA124_CLK_ADX1, .present = true }, 862 [tegra_clk_dpaux] = { .dt_id = TEGRA124_CLK_DPAUX, .present = true }, 863 [tegra_clk_sor0] = { .dt_id = TEGRA124_CLK_SOR0, .present = true }, 864 [tegra_clk_sor0_lvds] = { .dt_id = TEGRA124_CLK_SOR0_LVDS, .present = true }, 865 [tegra_clk_gpu] = { .dt_id = TEGRA124_CLK_GPU, .present = true }, 866 [tegra_clk_amx1] = { .dt_id = TEGRA124_CLK_AMX1, .present = true }, 867 [tegra_clk_uartb] = { .dt_id = TEGRA124_CLK_UARTB, .present = true }, 868 [tegra_clk_vfir] = { .dt_id = TEGRA124_CLK_VFIR, .present = true }, 869 [tegra_clk_spdif_in] = { .dt_id = TEGRA124_CLK_SPDIF_IN, .present = true }, 870 [tegra_clk_spdif_out] = { .dt_id = TEGRA124_CLK_SPDIF_OUT, .present = true }, 871 [tegra_clk_vi_9] = { .dt_id = TEGRA124_CLK_VI, .present = true }, 872 [tegra_clk_vi_sensor] = { .dt_id = TEGRA124_CLK_VI_SENSOR, .present = true }, 873 [tegra_clk_fuse] = { .dt_id = TEGRA124_CLK_FUSE, .present = true }, 874 [tegra_clk_fuse_burn] = { .dt_id = TEGRA124_CLK_FUSE_BURN, .present = true }, 875 [tegra_clk_clk_32k] = { .dt_id = TEGRA124_CLK_CLK_32K, .present = true }, 876 [tegra_clk_clk_m] = { .dt_id = TEGRA124_CLK_CLK_M, .present = true }, 877 [tegra_clk_clk_m_div2] = { .dt_id = TEGRA124_CLK_CLK_M_DIV2, .present = true }, 878 [tegra_clk_clk_m_div4] = { .dt_id = TEGRA124_CLK_CLK_M_DIV4, .present = true }, 879 [tegra_clk_pll_ref] = { .dt_id = TEGRA124_CLK_PLL_REF, .present = true }, 880 [tegra_clk_pll_c] = { .dt_id = TEGRA124_CLK_PLL_C, .present = true }, 881 [tegra_clk_pll_c_out1] = { .dt_id = TEGRA124_CLK_PLL_C_OUT1, .present = true }, 882 [tegra_clk_pll_c2] = { .dt_id = TEGRA124_CLK_PLL_C2, .present = true }, 883 [tegra_clk_pll_c3] = { .dt_id = TEGRA124_CLK_PLL_C3, .present = true }, 884 [tegra_clk_pll_m] = { .dt_id = TEGRA124_CLK_PLL_M, .present = true }, 885 [tegra_clk_pll_m_out1] = { .dt_id = TEGRA124_CLK_PLL_M_OUT1, .present = true }, 886 [tegra_clk_pll_p] = { .dt_id = TEGRA124_CLK_PLL_P, .present = true }, 887 [tegra_clk_pll_p_out1] = { .dt_id = TEGRA124_CLK_PLL_P_OUT1, .present = true }, 888 [tegra_clk_pll_p_out2] = { .dt_id = TEGRA124_CLK_PLL_P_OUT2, .present = true }, 889 [tegra_clk_pll_p_out3] = { .dt_id = TEGRA124_CLK_PLL_P_OUT3, .present = true }, 890 [tegra_clk_pll_p_out4] = { .dt_id = TEGRA124_CLK_PLL_P_OUT4, .present = true }, 891 [tegra_clk_pll_a] = { .dt_id = TEGRA124_CLK_PLL_A, .present = true }, 892 [tegra_clk_pll_a_out0] = { .dt_id = TEGRA124_CLK_PLL_A_OUT0, .present = true }, 893 [tegra_clk_pll_d] = { .dt_id = TEGRA124_CLK_PLL_D, .present = true }, 894 [tegra_clk_pll_d_out0] = { .dt_id = TEGRA124_CLK_PLL_D_OUT0, .present = true }, 895 [tegra_clk_pll_d2] = { .dt_id = TEGRA124_CLK_PLL_D2, .present = true }, 896 [tegra_clk_pll_d2_out0] = { .dt_id = TEGRA124_CLK_PLL_D2_OUT0, .present = true }, 897 [tegra_clk_pll_u] = { .dt_id = TEGRA124_CLK_PLL_U, .present = true }, 898 [tegra_clk_pll_u_480m] = { .dt_id = TEGRA124_CLK_PLL_U_480M, .present = true }, 899 [tegra_clk_pll_u_60m] = { .dt_id = TEGRA124_CLK_PLL_U_60M, .present = true }, 900 [tegra_clk_pll_u_48m] = { .dt_id = TEGRA124_CLK_PLL_U_48M, .present = true }, 901 [tegra_clk_pll_u_12m] = { .dt_id = TEGRA124_CLK_PLL_U_12M, .present = true }, 902 [tegra_clk_pll_x] = { .dt_id = TEGRA124_CLK_PLL_X, .present = true }, 903 [tegra_clk_pll_x_out0] = { .dt_id = TEGRA124_CLK_PLL_X_OUT0, .present = true }, 904 [tegra_clk_pll_re_vco] = { .dt_id = TEGRA124_CLK_PLL_RE_VCO, .present = true }, 905 [tegra_clk_pll_re_out] = { .dt_id = TEGRA124_CLK_PLL_RE_OUT, .present = true }, 906 [tegra_clk_spdif_in_sync] = { .dt_id = TEGRA124_CLK_SPDIF_IN_SYNC, .present = true }, 907 [tegra_clk_i2s0_sync] = { .dt_id = TEGRA124_CLK_I2S0_SYNC, .present = true }, 908 [tegra_clk_i2s1_sync] = { .dt_id = TEGRA124_CLK_I2S1_SYNC, .present = true }, 909 [tegra_clk_i2s2_sync] = { .dt_id = TEGRA124_CLK_I2S2_SYNC, .present = true }, 910 [tegra_clk_i2s3_sync] = { .dt_id = TEGRA124_CLK_I2S3_SYNC, .present = true }, 911 [tegra_clk_i2s4_sync] = { .dt_id = TEGRA124_CLK_I2S4_SYNC, .present = true }, 912 [tegra_clk_vimclk_sync] = { .dt_id = TEGRA124_CLK_VIMCLK_SYNC, .present = true }, 913 [tegra_clk_audio0] = { .dt_id = TEGRA124_CLK_AUDIO0, .present = true }, 914 [tegra_clk_audio1] = { .dt_id = TEGRA124_CLK_AUDIO1, .present = true }, 915 [tegra_clk_audio2] = { .dt_id = TEGRA124_CLK_AUDIO2, .present = true }, 916 [tegra_clk_audio3] = { .dt_id = TEGRA124_CLK_AUDIO3, .present = true }, 917 [tegra_clk_audio4] = { .dt_id = TEGRA124_CLK_AUDIO4, .present = true }, 918 [tegra_clk_spdif] = { .dt_id = TEGRA124_CLK_SPDIF, .present = true }, 919 [tegra_clk_clk_out_1] = { .dt_id = TEGRA124_CLK_CLK_OUT_1, .present = true }, 920 [tegra_clk_clk_out_2] = { .dt_id = TEGRA124_CLK_CLK_OUT_2, .present = true }, 921 [tegra_clk_clk_out_3] = { .dt_id = TEGRA124_CLK_CLK_OUT_3, .present = true }, 922 [tegra_clk_blink] = { .dt_id = TEGRA124_CLK_BLINK, .present = true }, 923 [tegra_clk_xusb_host_src] = { .dt_id = TEGRA124_CLK_XUSB_HOST_SRC, .present = true }, 924 [tegra_clk_xusb_falcon_src] = { .dt_id = TEGRA124_CLK_XUSB_FALCON_SRC, .present = true }, 925 [tegra_clk_xusb_fs_src] = { .dt_id = TEGRA124_CLK_XUSB_FS_SRC, .present = true }, 926 [tegra_clk_xusb_ss_src] = { .dt_id = TEGRA124_CLK_XUSB_SS_SRC, .present = true }, 927 [tegra_clk_xusb_ss_div2] = { .dt_id = TEGRA124_CLK_XUSB_SS_DIV2, .present = true }, 928 [tegra_clk_xusb_dev_src] = { .dt_id = TEGRA124_CLK_XUSB_DEV_SRC, .present = true }, 929 [tegra_clk_xusb_dev] = { .dt_id = TEGRA124_CLK_XUSB_DEV, .present = true }, 930 [tegra_clk_xusb_hs_src] = { .dt_id = TEGRA124_CLK_XUSB_HS_SRC, .present = true }, 931 [tegra_clk_sclk] = { .dt_id = TEGRA124_CLK_SCLK, .present = true }, 932 [tegra_clk_hclk] = { .dt_id = TEGRA124_CLK_HCLK, .present = true }, 933 [tegra_clk_pclk] = { .dt_id = TEGRA124_CLK_PCLK, .present = true }, 934 [tegra_clk_cclk_g] = { .dt_id = TEGRA124_CLK_CCLK_G, .present = true }, 935 [tegra_clk_cclk_lp] = { .dt_id = TEGRA124_CLK_CCLK_LP, .present = true }, 936 [tegra_clk_dfll_ref] = { .dt_id = TEGRA124_CLK_DFLL_REF, .present = true }, 937 [tegra_clk_dfll_soc] = { .dt_id = TEGRA124_CLK_DFLL_SOC, .present = true }, 938 [tegra_clk_vi_sensor2] = { .dt_id = TEGRA124_CLK_VI_SENSOR2, .present = true }, 939 [tegra_clk_pll_p_out5] = { .dt_id = TEGRA124_CLK_PLL_P_OUT5, .present = true }, 940 [tegra_clk_pll_c4] = { .dt_id = TEGRA124_CLK_PLL_C4, .present = true }, 941 [tegra_clk_pll_dp] = { .dt_id = TEGRA124_CLK_PLL_DP, .present = true }, 942 [tegra_clk_audio0_mux] = { .dt_id = TEGRA124_CLK_AUDIO0_MUX, .present = true }, 943 [tegra_clk_audio1_mux] = { .dt_id = TEGRA124_CLK_AUDIO1_MUX, .present = true }, 944 [tegra_clk_audio2_mux] = { .dt_id = TEGRA124_CLK_AUDIO2_MUX, .present = true }, 945 [tegra_clk_audio3_mux] = { .dt_id = TEGRA124_CLK_AUDIO3_MUX, .present = true }, 946 [tegra_clk_audio4_mux] = { .dt_id = TEGRA124_CLK_AUDIO4_MUX, .present = true }, 947 [tegra_clk_spdif_mux] = { .dt_id = TEGRA124_CLK_SPDIF_MUX, .present = true }, 948 [tegra_clk_clk_out_1_mux] = { .dt_id = TEGRA124_CLK_CLK_OUT_1_MUX, .present = true }, 949 [tegra_clk_clk_out_2_mux] = { .dt_id = TEGRA124_CLK_CLK_OUT_2_MUX, .present = true }, 950 [tegra_clk_clk_out_3_mux] = { .dt_id = TEGRA124_CLK_CLK_OUT_3_MUX, .present = true }, 951 [tegra_clk_dsia_mux] = { .dt_id = TEGRA124_CLK_DSIA_MUX, .present = true }, 952 [tegra_clk_dsib_mux] = { .dt_id = TEGRA124_CLK_DSIB_MUX, .present = true }, 953}; 954 955static struct tegra_devclk devclks[] __initdata = { 956 { .con_id = "clk_m", .dt_id = TEGRA124_CLK_CLK_M }, 957 { .con_id = "pll_ref", .dt_id = TEGRA124_CLK_PLL_REF }, 958 { .con_id = "clk_32k", .dt_id = TEGRA124_CLK_CLK_32K }, 959 { .con_id = "clk_m_div2", .dt_id = TEGRA124_CLK_CLK_M_DIV2 }, 960 { .con_id = "clk_m_div4", .dt_id = TEGRA124_CLK_CLK_M_DIV4 }, 961 { .con_id = "pll_c", .dt_id = TEGRA124_CLK_PLL_C }, 962 { .con_id = "pll_c_out1", .dt_id = TEGRA124_CLK_PLL_C_OUT1 }, 963 { .con_id = "pll_c2", .dt_id = TEGRA124_CLK_PLL_C2 }, 964 { .con_id = "pll_c3", .dt_id = TEGRA124_CLK_PLL_C3 }, 965 { .con_id = "pll_p", .dt_id = TEGRA124_CLK_PLL_P }, 966 { .con_id = "pll_p_out1", .dt_id = TEGRA124_CLK_PLL_P_OUT1 }, 967 { .con_id = "pll_p_out2", .dt_id = TEGRA124_CLK_PLL_P_OUT2 }, 968 { .con_id = "pll_p_out3", .dt_id = TEGRA124_CLK_PLL_P_OUT3 }, 969 { .con_id = "pll_p_out4", .dt_id = TEGRA124_CLK_PLL_P_OUT4 }, 970 { .con_id = "pll_m", .dt_id = TEGRA124_CLK_PLL_M }, 971 { .con_id = "pll_m_out1", .dt_id = TEGRA124_CLK_PLL_M_OUT1 }, 972 { .con_id = "pll_x", .dt_id = TEGRA124_CLK_PLL_X }, 973 { .con_id = "pll_x_out0", .dt_id = TEGRA124_CLK_PLL_X_OUT0 }, 974 { .con_id = "pll_u", .dt_id = TEGRA124_CLK_PLL_U }, 975 { .con_id = "pll_u_480M", .dt_id = TEGRA124_CLK_PLL_U_480M }, 976 { .con_id = "pll_u_60M", .dt_id = TEGRA124_CLK_PLL_U_60M }, 977 { .con_id = "pll_u_48M", .dt_id = TEGRA124_CLK_PLL_U_48M }, 978 { .con_id = "pll_u_12M", .dt_id = TEGRA124_CLK_PLL_U_12M }, 979 { .con_id = "pll_d", .dt_id = TEGRA124_CLK_PLL_D }, 980 { .con_id = "pll_d_out0", .dt_id = TEGRA124_CLK_PLL_D_OUT0 }, 981 { .con_id = "pll_d2", .dt_id = TEGRA124_CLK_PLL_D2 }, 982 { .con_id = "pll_d2_out0", .dt_id = TEGRA124_CLK_PLL_D2_OUT0 }, 983 { .con_id = "pll_a", .dt_id = TEGRA124_CLK_PLL_A }, 984 { .con_id = "pll_a_out0", .dt_id = TEGRA124_CLK_PLL_A_OUT0 }, 985 { .con_id = "pll_re_vco", .dt_id = TEGRA124_CLK_PLL_RE_VCO }, 986 { .con_id = "pll_re_out", .dt_id = TEGRA124_CLK_PLL_RE_OUT }, 987 { .con_id = "spdif_in_sync", .dt_id = TEGRA124_CLK_SPDIF_IN_SYNC }, 988 { .con_id = "i2s0_sync", .dt_id = TEGRA124_CLK_I2S0_SYNC }, 989 { .con_id = "i2s1_sync", .dt_id = TEGRA124_CLK_I2S1_SYNC }, 990 { .con_id = "i2s2_sync", .dt_id = TEGRA124_CLK_I2S2_SYNC }, 991 { .con_id = "i2s3_sync", .dt_id = TEGRA124_CLK_I2S3_SYNC }, 992 { .con_id = "i2s4_sync", .dt_id = TEGRA124_CLK_I2S4_SYNC }, 993 { .con_id = "vimclk_sync", .dt_id = TEGRA124_CLK_VIMCLK_SYNC }, 994 { .con_id = "audio0", .dt_id = TEGRA124_CLK_AUDIO0 }, 995 { .con_id = "audio1", .dt_id = TEGRA124_CLK_AUDIO1 }, 996 { .con_id = "audio2", .dt_id = TEGRA124_CLK_AUDIO2 }, 997 { .con_id = "audio3", .dt_id = TEGRA124_CLK_AUDIO3 }, 998 { .con_id = "audio4", .dt_id = TEGRA124_CLK_AUDIO4 }, 999 { .con_id = "spdif", .dt_id = TEGRA124_CLK_SPDIF }, 1000 { .con_id = "audio0_2x", .dt_id = TEGRA124_CLK_AUDIO0_2X }, 1001 { .con_id = "audio1_2x", .dt_id = TEGRA124_CLK_AUDIO1_2X }, 1002 { .con_id = "audio2_2x", .dt_id = TEGRA124_CLK_AUDIO2_2X }, 1003 { .con_id = "audio3_2x", .dt_id = TEGRA124_CLK_AUDIO3_2X }, 1004 { .con_id = "audio4_2x", .dt_id = TEGRA124_CLK_AUDIO4_2X }, 1005 { .con_id = "spdif_2x", .dt_id = TEGRA124_CLK_SPDIF_2X }, 1006 { .con_id = "extern1", .dev_id = "clk_out_1", .dt_id = TEGRA124_CLK_EXTERN1 }, 1007 { .con_id = "extern2", .dev_id = "clk_out_2", .dt_id = TEGRA124_CLK_EXTERN2 }, 1008 { .con_id = "extern3", .dev_id = "clk_out_3", .dt_id = TEGRA124_CLK_EXTERN3 }, 1009 { .con_id = "blink", .dt_id = TEGRA124_CLK_BLINK }, 1010 { .con_id = "cclk_g", .dt_id = TEGRA124_CLK_CCLK_G }, 1011 { .con_id = "cclk_lp", .dt_id = TEGRA124_CLK_CCLK_LP }, 1012 { .con_id = "sclk", .dt_id = TEGRA124_CLK_SCLK }, 1013 { .con_id = "hclk", .dt_id = TEGRA124_CLK_HCLK }, 1014 { .con_id = "pclk", .dt_id = TEGRA124_CLK_PCLK }, 1015 { .con_id = "fuse", .dt_id = TEGRA124_CLK_FUSE }, 1016 { .dev_id = "rtc-tegra", .dt_id = TEGRA124_CLK_RTC }, 1017 { .dev_id = "timer", .dt_id = TEGRA124_CLK_TIMER }, 1018}; 1019 1020static struct clk **clks; 1021 1022static void tegra124_utmi_param_configure(void __iomem *clk_base) 1023{ 1024 u32 reg; 1025 int i; 1026 1027 for (i = 0; i < ARRAY_SIZE(utmi_parameters); i++) { 1028 if (osc_freq == utmi_parameters[i].osc_frequency) 1029 break; 1030 } 1031 1032 if (i >= ARRAY_SIZE(utmi_parameters)) { 1033 pr_err("%s: Unexpected oscillator freq %lu\n", __func__, 1034 osc_freq); 1035 return; 1036 } 1037 1038 reg = readl_relaxed(clk_base + UTMIP_PLL_CFG2); 1039 1040 /* Program UTMIP PLL stable and active counts */ 1041 /* [FIXME] arclk_rst.h says WRONG! This should be 1ms -> 0x50 Check! */ 1042 reg &= ~UTMIP_PLL_CFG2_STABLE_COUNT(~0); 1043 reg |= UTMIP_PLL_CFG2_STABLE_COUNT(utmi_parameters[i].stable_count); 1044 1045 reg &= ~UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(~0); 1046 1047 reg |= UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(utmi_parameters[i]. 1048 active_delay_count); 1049 1050 /* Remove power downs from UTMIP PLL control bits */ 1051 reg &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_A_POWERDOWN; 1052 reg &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_B_POWERDOWN; 1053 reg &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_C_POWERDOWN; 1054 1055 writel_relaxed(reg, clk_base + UTMIP_PLL_CFG2); 1056 1057 /* Program UTMIP PLL delay and oscillator frequency counts */ 1058 reg = readl_relaxed(clk_base + UTMIP_PLL_CFG1); 1059 reg &= ~UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(~0); 1060 1061 reg |= UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(utmi_parameters[i]. 1062 enable_delay_count); 1063 1064 reg &= ~UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(~0); 1065 reg |= UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(utmi_parameters[i]. 1066 xtal_freq_count); 1067 1068 /* Remove power downs from UTMIP PLL control bits */ 1069 reg &= ~UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN; 1070 reg &= ~UTMIP_PLL_CFG1_FORCE_PLL_ACTIVE_POWERDOWN; 1071 reg &= ~UTMIP_PLL_CFG1_FORCE_PLLU_POWERUP; 1072 reg &= ~UTMIP_PLL_CFG1_FORCE_PLLU_POWERDOWN; 1073 writel_relaxed(reg, clk_base + UTMIP_PLL_CFG1); 1074 1075 /* Setup HW control of UTMIPLL */ 1076 reg = readl_relaxed(clk_base + UTMIPLL_HW_PWRDN_CFG0); 1077 reg |= UTMIPLL_HW_PWRDN_CFG0_USE_LOCKDET; 1078 reg &= ~UTMIPLL_HW_PWRDN_CFG0_CLK_ENABLE_SWCTL; 1079 reg |= UTMIPLL_HW_PWRDN_CFG0_SEQ_START_STATE; 1080 writel_relaxed(reg, clk_base + UTMIPLL_HW_PWRDN_CFG0); 1081 1082 reg = readl_relaxed(clk_base + UTMIP_PLL_CFG1); 1083 reg &= ~UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERUP; 1084 reg &= ~UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN; 1085 writel_relaxed(reg, clk_base + UTMIP_PLL_CFG1); 1086 1087 udelay(1); 1088 1089 /* Setup SW override of UTMIPLL assuming USB2.0 1090 ports are assigned to USB2 */ 1091 reg = readl_relaxed(clk_base + UTMIPLL_HW_PWRDN_CFG0); 1092 reg |= UTMIPLL_HW_PWRDN_CFG0_IDDQ_SWCTL; 1093 reg &= ~UTMIPLL_HW_PWRDN_CFG0_IDDQ_OVERRIDE; 1094 writel_relaxed(reg, clk_base + UTMIPLL_HW_PWRDN_CFG0); 1095 1096 udelay(1); 1097 1098 /* Enable HW control UTMIPLL */ 1099 reg = readl_relaxed(clk_base + UTMIPLL_HW_PWRDN_CFG0); 1100 reg |= UTMIPLL_HW_PWRDN_CFG0_SEQ_ENABLE; 1101 writel_relaxed(reg, clk_base + UTMIPLL_HW_PWRDN_CFG0); 1102} 1103 1104static __init void tegra124_periph_clk_init(void __iomem *clk_base, 1105 void __iomem *pmc_base) 1106{ 1107 struct clk *clk; 1108 1109 /* xusb_ss_div2 */ 1110 clk = clk_register_fixed_factor(NULL, "xusb_ss_div2", "xusb_ss_src", 0, 1111 1, 2); 1112 clks[TEGRA124_CLK_XUSB_SS_DIV2] = clk; 1113 1114 /* dsia mux */ 1115 clk = clk_register_mux(NULL, "dsia_mux", mux_plld_out0_plld2_out0, 1116 ARRAY_SIZE(mux_plld_out0_plld2_out0), 0, 1117 clk_base + PLLD_BASE, 25, 1, 0, &pll_d_lock); 1118 clks[TEGRA124_CLK_DSIA_MUX] = clk; 1119 1120 /* dsib mux */ 1121 clk = clk_register_mux(NULL, "dsib_mux", mux_plld_out0_plld2_out0, 1122 ARRAY_SIZE(mux_plld_out0_plld2_out0), 0, 1123 clk_base + PLLD2_BASE, 25, 1, 0, &pll_d2_lock); 1124 clks[TEGRA124_CLK_DSIB_MUX] = clk; 1125 1126 /* emc mux */ 1127 clk = clk_register_mux(NULL, "emc_mux", mux_pllmcp_clkm, 1128 ARRAY_SIZE(mux_pllmcp_clkm), 0, 1129 clk_base + CLK_SOURCE_EMC, 1130 29, 3, 0, NULL); 1131 1132 /* cml0 */ 1133 clk = clk_register_gate(NULL, "cml0", "pll_e", 0, clk_base + PLLE_AUX, 1134 0, 0, &pll_e_lock); 1135 clk_register_clkdev(clk, "cml0", NULL); 1136 clks[TEGRA124_CLK_CML0] = clk; 1137 1138 /* cml1 */ 1139 clk = clk_register_gate(NULL, "cml1", "pll_e", 0, clk_base + PLLE_AUX, 1140 1, 0, &pll_e_lock); 1141 clk_register_clkdev(clk, "cml1", NULL); 1142 clks[TEGRA124_CLK_CML1] = clk; 1143 1144 tegra_periph_clk_init(clk_base, pmc_base, tegra124_clks, &pll_p_params); 1145} 1146 1147static void __init tegra124_pll_init(void __iomem *clk_base, 1148 void __iomem *pmc) 1149{ 1150 u32 val; 1151 struct clk *clk; 1152 1153 /* PLLC */ 1154 clk = tegra_clk_register_pllxc("pll_c", "pll_ref", clk_base, 1155 pmc, 0, &pll_c_params, NULL); 1156 clk_register_clkdev(clk, "pll_c", NULL); 1157 clks[TEGRA124_CLK_PLL_C] = clk; 1158 1159 /* PLLC_OUT1 */ 1160 clk = tegra_clk_register_divider("pll_c_out1_div", "pll_c", 1161 clk_base + PLLC_OUT, 0, TEGRA_DIVIDER_ROUND_UP, 1162 8, 8, 1, NULL); 1163 clk = tegra_clk_register_pll_out("pll_c_out1", "pll_c_out1_div", 1164 clk_base + PLLC_OUT, 1, 0, 1165 CLK_SET_RATE_PARENT, 0, NULL); 1166 clk_register_clkdev(clk, "pll_c_out1", NULL); 1167 clks[TEGRA124_CLK_PLL_C_OUT1] = clk; 1168 1169 /* PLLC2 */ 1170 clk = tegra_clk_register_pllc("pll_c2", "pll_ref", clk_base, pmc, 0, 1171 &pll_c2_params, NULL); 1172 clk_register_clkdev(clk, "pll_c2", NULL); 1173 clks[TEGRA124_CLK_PLL_C2] = clk; 1174 1175 /* PLLC3 */ 1176 clk = tegra_clk_register_pllc("pll_c3", "pll_ref", clk_base, pmc, 0, 1177 &pll_c3_params, NULL); 1178 clk_register_clkdev(clk, "pll_c3", NULL); 1179 clks[TEGRA124_CLK_PLL_C3] = clk; 1180 1181 /* PLLM */ 1182 clk = tegra_clk_register_pllm("pll_m", "pll_ref", clk_base, pmc, 1183 CLK_IGNORE_UNUSED | CLK_SET_RATE_GATE, 1184 &pll_m_params, NULL); 1185 clk_register_clkdev(clk, "pll_m", NULL); 1186 clks[TEGRA124_CLK_PLL_M] = clk; 1187 1188 /* PLLM_OUT1 */ 1189 clk = tegra_clk_register_divider("pll_m_out1_div", "pll_m", 1190 clk_base + PLLM_OUT, 0, TEGRA_DIVIDER_ROUND_UP, 1191 8, 8, 1, NULL); 1192 clk = tegra_clk_register_pll_out("pll_m_out1", "pll_m_out1_div", 1193 clk_base + PLLM_OUT, 1, 0, CLK_IGNORE_UNUSED | 1194 CLK_SET_RATE_PARENT, 0, NULL); 1195 clk_register_clkdev(clk, "pll_m_out1", NULL); 1196 clks[TEGRA124_CLK_PLL_M_OUT1] = clk; 1197 1198 /* PLLM_UD */ 1199 clk = clk_register_fixed_factor(NULL, "pll_m_ud", "pll_m", 1200 CLK_SET_RATE_PARENT, 1, 1); 1201 1202 /* PLLU */ 1203 val = readl(clk_base + pll_u_params.base_reg); 1204 val &= ~BIT(24); /* disable PLLU_OVERRIDE */ 1205 writel(val, clk_base + pll_u_params.base_reg); 1206 1207 clk = tegra_clk_register_pll("pll_u", "pll_ref", clk_base, pmc, 0, 1208 &pll_u_params, &pll_u_lock); 1209 clk_register_clkdev(clk, "pll_u", NULL); 1210 clks[TEGRA124_CLK_PLL_U] = clk; 1211 1212 tegra124_utmi_param_configure(clk_base); 1213 1214 /* PLLU_480M */ 1215 clk = clk_register_gate(NULL, "pll_u_480M", "pll_u", 1216 CLK_SET_RATE_PARENT, clk_base + PLLU_BASE, 1217 22, 0, &pll_u_lock); 1218 clk_register_clkdev(clk, "pll_u_480M", NULL); 1219 clks[TEGRA124_CLK_PLL_U_480M] = clk; 1220 1221 /* PLLU_60M */ 1222 clk = clk_register_fixed_factor(NULL, "pll_u_60M", "pll_u", 1223 CLK_SET_RATE_PARENT, 1, 8); 1224 clk_register_clkdev(clk, "pll_u_60M", NULL); 1225 clks[TEGRA124_CLK_PLL_U_60M] = clk; 1226 1227 /* PLLU_48M */ 1228 clk = clk_register_fixed_factor(NULL, "pll_u_48M", "pll_u", 1229 CLK_SET_RATE_PARENT, 1, 10); 1230 clk_register_clkdev(clk, "pll_u_48M", NULL); 1231 clks[TEGRA124_CLK_PLL_U_48M] = clk; 1232 1233 /* PLLU_12M */ 1234 clk = clk_register_fixed_factor(NULL, "pll_u_12M", "pll_u", 1235 CLK_SET_RATE_PARENT, 1, 40); 1236 clk_register_clkdev(clk, "pll_u_12M", NULL); 1237 clks[TEGRA124_CLK_PLL_U_12M] = clk; 1238 1239 /* PLLD */ 1240 clk = tegra_clk_register_pll("pll_d", "pll_ref", clk_base, pmc, 0, 1241 &pll_d_params, &pll_d_lock); 1242 clk_register_clkdev(clk, "pll_d", NULL); 1243 clks[TEGRA124_CLK_PLL_D] = clk; 1244 1245 /* PLLD_OUT0 */ 1246 clk = clk_register_fixed_factor(NULL, "pll_d_out0", "pll_d", 1247 CLK_SET_RATE_PARENT, 1, 2); 1248 clk_register_clkdev(clk, "pll_d_out0", NULL); 1249 clks[TEGRA124_CLK_PLL_D_OUT0] = clk; 1250 1251 /* PLLRE */ 1252 clk = tegra_clk_register_pllre("pll_re_vco", "pll_ref", clk_base, pmc, 1253 0, &pll_re_vco_params, &pll_re_lock, pll_ref_freq); 1254 clk_register_clkdev(clk, "pll_re_vco", NULL); 1255 clks[TEGRA124_CLK_PLL_RE_VCO] = clk; 1256 1257 clk = clk_register_divider_table(NULL, "pll_re_out", "pll_re_vco", 0, 1258 clk_base + PLLRE_BASE, 16, 4, 0, 1259 pll_re_div_table, &pll_re_lock); 1260 clk_register_clkdev(clk, "pll_re_out", NULL); 1261 clks[TEGRA124_CLK_PLL_RE_OUT] = clk; 1262 1263 /* PLLE */ 1264 clk = tegra_clk_register_plle_tegra114("pll_e", "pll_ref", 1265 clk_base, 0, &pll_e_params, NULL); 1266 clk_register_clkdev(clk, "pll_e", NULL); 1267 clks[TEGRA124_CLK_PLL_E] = clk; 1268 1269 /* PLLC4 */ 1270 clk = tegra_clk_register_pllss("pll_c4", "pll_ref", clk_base, 0, 1271 &pll_c4_params, NULL); 1272 clk_register_clkdev(clk, "pll_c4", NULL); 1273 clks[TEGRA124_CLK_PLL_C4] = clk; 1274 1275 /* PLLDP */ 1276 clk = tegra_clk_register_pllss("pll_dp", "pll_ref", clk_base, 0, 1277 &pll_dp_params, NULL); 1278 clk_register_clkdev(clk, "pll_dp", NULL); 1279 clks[TEGRA124_CLK_PLL_DP] = clk; 1280 1281 /* PLLD2 */ 1282 clk = tegra_clk_register_pllss("pll_d2", "pll_ref", clk_base, 0, 1283 &tegra124_pll_d2_params, NULL); 1284 clk_register_clkdev(clk, "pll_d2", NULL); 1285 clks[TEGRA124_CLK_PLL_D2] = clk; 1286 1287 /* PLLD2_OUT0 */ 1288 clk = clk_register_fixed_factor(NULL, "pll_d2_out0", "pll_d2", 1289 CLK_SET_RATE_PARENT, 1, 1); 1290 clk_register_clkdev(clk, "pll_d2_out0", NULL); 1291 clks[TEGRA124_CLK_PLL_D2_OUT0] = clk; 1292 1293} 1294 1295/* Tegra124 CPU clock and reset control functions */ 1296static void tegra124_wait_cpu_in_reset(u32 cpu) 1297{ 1298 unsigned int reg; 1299 1300 do { 1301 reg = readl(clk_base + CLK_RST_CONTROLLER_CPU_CMPLX_STATUS); 1302 cpu_relax(); 1303 } while (!(reg & (1 << cpu))); /* check CPU been reset or not */ 1304} 1305 1306static void tegra124_disable_cpu_clock(u32 cpu) 1307{ 1308 /* flow controller would take care in the power sequence. */ 1309} 1310 1311#ifdef CONFIG_PM_SLEEP 1312static void tegra124_cpu_clock_suspend(void) 1313{ 1314 /* switch coresite to clk_m, save off original source */ 1315 tegra124_cpu_clk_sctx.clk_csite_src = 1316 readl(clk_base + CLK_SOURCE_CSITE); 1317 writel(3 << 30, clk_base + CLK_SOURCE_CSITE); 1318} 1319 1320static void tegra124_cpu_clock_resume(void) 1321{ 1322 writel(tegra124_cpu_clk_sctx.clk_csite_src, 1323 clk_base + CLK_SOURCE_CSITE); 1324} 1325#endif 1326 1327static struct tegra_cpu_car_ops tegra124_cpu_car_ops = { 1328 .wait_for_reset = tegra124_wait_cpu_in_reset, 1329 .disable_clock = tegra124_disable_cpu_clock, 1330#ifdef CONFIG_PM_SLEEP 1331 .suspend = tegra124_cpu_clock_suspend, 1332 .resume = tegra124_cpu_clock_resume, 1333#endif 1334}; 1335 1336static const struct of_device_id pmc_match[] __initconst = { 1337 { .compatible = "nvidia,tegra124-pmc" }, 1338 {}, 1339}; 1340 1341static struct tegra_clk_init_table init_table[] __initdata = { 1342 {TEGRA124_CLK_UARTA, TEGRA124_CLK_PLL_P, 408000000, 0}, 1343 {TEGRA124_CLK_UARTB, TEGRA124_CLK_PLL_P, 408000000, 0}, 1344 {TEGRA124_CLK_UARTC, TEGRA124_CLK_PLL_P, 408000000, 0}, 1345 {TEGRA124_CLK_UARTD, TEGRA124_CLK_PLL_P, 408000000, 0}, 1346 {TEGRA124_CLK_PLL_A, TEGRA124_CLK_CLK_MAX, 564480000, 1}, 1347 {TEGRA124_CLK_PLL_A_OUT0, TEGRA124_CLK_CLK_MAX, 11289600, 1}, 1348 {TEGRA124_CLK_EXTERN1, TEGRA124_CLK_PLL_A_OUT0, 0, 1}, 1349 {TEGRA124_CLK_CLK_OUT_1_MUX, TEGRA124_CLK_EXTERN1, 0, 1}, 1350 {TEGRA124_CLK_CLK_OUT_1, TEGRA124_CLK_CLK_MAX, 0, 1}, 1351 {TEGRA124_CLK_I2S0, TEGRA124_CLK_PLL_A_OUT0, 11289600, 0}, 1352 {TEGRA124_CLK_I2S1, TEGRA124_CLK_PLL_A_OUT0, 11289600, 0}, 1353 {TEGRA124_CLK_I2S2, TEGRA124_CLK_PLL_A_OUT0, 11289600, 0}, 1354 {TEGRA124_CLK_I2S3, TEGRA124_CLK_PLL_A_OUT0, 11289600, 0}, 1355 {TEGRA124_CLK_I2S4, TEGRA124_CLK_PLL_A_OUT0, 11289600, 0}, 1356 {TEGRA124_CLK_VDE, TEGRA124_CLK_PLL_P, 0, 0}, 1357 {TEGRA124_CLK_HOST1X, TEGRA124_CLK_PLL_P, 136000000, 1}, 1358 {TEGRA124_CLK_SCLK, TEGRA124_CLK_PLL_P_OUT2, 102000000, 1}, 1359 {TEGRA124_CLK_DFLL_SOC, TEGRA124_CLK_PLL_P, 51000000, 1}, 1360 {TEGRA124_CLK_DFLL_REF, TEGRA124_CLK_PLL_P, 51000000, 1}, 1361 {TEGRA124_CLK_PLL_C, TEGRA124_CLK_CLK_MAX, 768000000, 0}, 1362 {TEGRA124_CLK_PLL_C_OUT1, TEGRA124_CLK_CLK_MAX, 100000000, 0}, 1363 {TEGRA124_CLK_SBC4, TEGRA124_CLK_PLL_P, 12000000, 1}, 1364 {TEGRA124_CLK_TSEC, TEGRA124_CLK_PLL_C3, 0, 0}, 1365 {TEGRA124_CLK_MSENC, TEGRA124_CLK_PLL_C3, 0, 0}, 1366 /* This MUST be the last entry. */ 1367 {TEGRA124_CLK_CLK_MAX, TEGRA124_CLK_CLK_MAX, 0, 0}, 1368}; 1369 1370static void __init tegra124_clock_apply_init_table(void) 1371{ 1372 tegra_init_from_table(init_table, clks, TEGRA124_CLK_CLK_MAX); 1373} 1374 1375static void __init tegra124_clock_init(struct device_node *np) 1376{ 1377 struct device_node *node; 1378 1379 clk_base = of_iomap(np, 0); 1380 if (!clk_base) { 1381 pr_err("ioremap tegra124 CAR failed\n"); 1382 return; 1383 } 1384 1385 node = of_find_matching_node(NULL, pmc_match); 1386 if (!node) { 1387 pr_err("Failed to find pmc node\n"); 1388 WARN_ON(1); 1389 return; 1390 } 1391 1392 pmc_base = of_iomap(node, 0); 1393 if (!pmc_base) { 1394 pr_err("Can't map pmc registers\n"); 1395 WARN_ON(1); 1396 return; 1397 } 1398 1399 clks = tegra_clk_init(clk_base, TEGRA124_CLK_CLK_MAX, 6); 1400 if (!clks) 1401 return; 1402 1403 if (tegra_osc_clk_init(clk_base, tegra124_clks, tegra124_input_freq, 1404 ARRAY_SIZE(tegra124_input_freq), &osc_freq, &pll_ref_freq) < 0) 1405 return; 1406 1407 tegra_fixed_clk_init(tegra124_clks); 1408 tegra124_pll_init(clk_base, pmc_base); 1409 tegra124_periph_clk_init(clk_base, pmc_base); 1410 tegra_audio_clk_init(clk_base, pmc_base, tegra124_clks, &pll_a_params); 1411 tegra_pmc_clk_init(pmc_base, tegra124_clks); 1412 1413 tegra_super_clk_gen4_init(clk_base, pmc_base, tegra124_clks, 1414 &pll_x_params); 1415 tegra_add_of_provider(np); 1416 tegra_register_devclks(devclks, ARRAY_SIZE(devclks)); 1417 1418 tegra_clk_apply_init_table = tegra124_clock_apply_init_table; 1419 1420 tegra_cpu_car_ops = &tegra124_cpu_car_ops; 1421} 1422CLK_OF_DECLARE(tegra124, "nvidia,tegra124-car", tegra124_clock_init); 1423