clk-tegra30.c revision 0b6525acd13f2d33cd3be86d0dbd2ddd1ffeda8f
1/* 2 * Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved. 3 * 4 * This program is free software; you can redistribute it and/or modify it 5 * under the terms and conditions of the GNU General Public License, 6 * version 2, as published by the Free Software Foundation. 7 * 8 * This program is distributed in the hope it will be useful, but WITHOUT 9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 11 * more details. 12 * 13 * You should have received a copy of the GNU General Public License 14 * along with this program. If not, see <http://www.gnu.org/licenses/>. 15 */ 16 17#include <linux/io.h> 18#include <linux/delay.h> 19#include <linux/clk.h> 20#include <linux/clk-provider.h> 21#include <linux/clkdev.h> 22#include <linux/of.h> 23#include <linux/of_address.h> 24#include <linux/clk/tegra.h> 25 26#include <mach/powergate.h> 27 28#include "clk.h" 29 30#define RST_DEVICES_L 0x004 31#define RST_DEVICES_H 0x008 32#define RST_DEVICES_U 0x00c 33#define RST_DEVICES_V 0x358 34#define RST_DEVICES_W 0x35c 35#define RST_DEVICES_SET_L 0x300 36#define RST_DEVICES_CLR_L 0x304 37#define RST_DEVICES_SET_H 0x308 38#define RST_DEVICES_CLR_H 0x30c 39#define RST_DEVICES_SET_U 0x310 40#define RST_DEVICES_CLR_U 0x314 41#define RST_DEVICES_SET_V 0x430 42#define RST_DEVICES_CLR_V 0x434 43#define RST_DEVICES_SET_W 0x438 44#define RST_DEVICES_CLR_W 0x43c 45#define RST_DEVICES_NUM 5 46 47#define CLK_OUT_ENB_L 0x010 48#define CLK_OUT_ENB_H 0x014 49#define CLK_OUT_ENB_U 0x018 50#define CLK_OUT_ENB_V 0x360 51#define CLK_OUT_ENB_W 0x364 52#define CLK_OUT_ENB_SET_L 0x320 53#define CLK_OUT_ENB_CLR_L 0x324 54#define CLK_OUT_ENB_SET_H 0x328 55#define CLK_OUT_ENB_CLR_H 0x32c 56#define CLK_OUT_ENB_SET_U 0x330 57#define CLK_OUT_ENB_CLR_U 0x334 58#define CLK_OUT_ENB_SET_V 0x440 59#define CLK_OUT_ENB_CLR_V 0x444 60#define CLK_OUT_ENB_SET_W 0x448 61#define CLK_OUT_ENB_CLR_W 0x44c 62#define CLK_OUT_ENB_NUM 5 63 64#define OSC_CTRL 0x50 65#define OSC_CTRL_OSC_FREQ_MASK (0xF<<28) 66#define OSC_CTRL_OSC_FREQ_13MHZ (0X0<<28) 67#define OSC_CTRL_OSC_FREQ_19_2MHZ (0X4<<28) 68#define OSC_CTRL_OSC_FREQ_12MHZ (0X8<<28) 69#define OSC_CTRL_OSC_FREQ_26MHZ (0XC<<28) 70#define OSC_CTRL_OSC_FREQ_16_8MHZ (0X1<<28) 71#define OSC_CTRL_OSC_FREQ_38_4MHZ (0X5<<28) 72#define OSC_CTRL_OSC_FREQ_48MHZ (0X9<<28) 73#define OSC_CTRL_MASK (0x3f2 | OSC_CTRL_OSC_FREQ_MASK) 74 75#define OSC_CTRL_PLL_REF_DIV_MASK (3<<26) 76#define OSC_CTRL_PLL_REF_DIV_1 (0<<26) 77#define OSC_CTRL_PLL_REF_DIV_2 (1<<26) 78#define OSC_CTRL_PLL_REF_DIV_4 (2<<26) 79 80#define OSC_FREQ_DET 0x58 81#define OSC_FREQ_DET_TRIG BIT(31) 82 83#define OSC_FREQ_DET_STATUS 0x5c 84#define OSC_FREQ_DET_BUSY BIT(31) 85#define OSC_FREQ_DET_CNT_MASK 0xffff 86 87#define CCLKG_BURST_POLICY 0x368 88#define SUPER_CCLKG_DIVIDER 0x36c 89#define CCLKLP_BURST_POLICY 0x370 90#define SUPER_CCLKLP_DIVIDER 0x374 91#define SCLK_BURST_POLICY 0x028 92#define SUPER_SCLK_DIVIDER 0x02c 93 94#define SYSTEM_CLK_RATE 0x030 95 96#define PLLC_BASE 0x80 97#define PLLC_MISC 0x8c 98#define PLLM_BASE 0x90 99#define PLLM_MISC 0x9c 100#define PLLP_BASE 0xa0 101#define PLLP_MISC 0xac 102#define PLLX_BASE 0xe0 103#define PLLX_MISC 0xe4 104#define PLLD_BASE 0xd0 105#define PLLD_MISC 0xdc 106#define PLLD2_BASE 0x4b8 107#define PLLD2_MISC 0x4bc 108#define PLLE_BASE 0xe8 109#define PLLE_MISC 0xec 110#define PLLA_BASE 0xb0 111#define PLLA_MISC 0xbc 112#define PLLU_BASE 0xc0 113#define PLLU_MISC 0xcc 114 115#define PLL_MISC_LOCK_ENABLE 18 116#define PLLDU_MISC_LOCK_ENABLE 22 117#define PLLE_MISC_LOCK_ENABLE 9 118 119#define PLL_BASE_LOCK 27 120#define PLLE_MISC_LOCK 11 121 122#define PLLE_AUX 0x48c 123#define PLLC_OUT 0x84 124#define PLLM_OUT 0x94 125#define PLLP_OUTA 0xa4 126#define PLLP_OUTB 0xa8 127#define PLLA_OUT 0xb4 128 129#define AUDIO_SYNC_CLK_I2S0 0x4a0 130#define AUDIO_SYNC_CLK_I2S1 0x4a4 131#define AUDIO_SYNC_CLK_I2S2 0x4a8 132#define AUDIO_SYNC_CLK_I2S3 0x4ac 133#define AUDIO_SYNC_CLK_I2S4 0x4b0 134#define AUDIO_SYNC_CLK_SPDIF 0x4b4 135 136#define PMC_CLK_OUT_CNTRL 0x1a8 137 138#define CLK_SOURCE_I2S0 0x1d8 139#define CLK_SOURCE_I2S1 0x100 140#define CLK_SOURCE_I2S2 0x104 141#define CLK_SOURCE_I2S3 0x3bc 142#define CLK_SOURCE_I2S4 0x3c0 143#define CLK_SOURCE_SPDIF_OUT 0x108 144#define CLK_SOURCE_SPDIF_IN 0x10c 145#define CLK_SOURCE_PWM 0x110 146#define CLK_SOURCE_D_AUDIO 0x3d0 147#define CLK_SOURCE_DAM0 0x3d8 148#define CLK_SOURCE_DAM1 0x3dc 149#define CLK_SOURCE_DAM2 0x3e0 150#define CLK_SOURCE_HDA 0x428 151#define CLK_SOURCE_HDA2CODEC_2X 0x3e4 152#define CLK_SOURCE_SBC1 0x134 153#define CLK_SOURCE_SBC2 0x118 154#define CLK_SOURCE_SBC3 0x11c 155#define CLK_SOURCE_SBC4 0x1b4 156#define CLK_SOURCE_SBC5 0x3c8 157#define CLK_SOURCE_SBC6 0x3cc 158#define CLK_SOURCE_SATA_OOB 0x420 159#define CLK_SOURCE_SATA 0x424 160#define CLK_SOURCE_NDFLASH 0x160 161#define CLK_SOURCE_NDSPEED 0x3f8 162#define CLK_SOURCE_VFIR 0x168 163#define CLK_SOURCE_SDMMC1 0x150 164#define CLK_SOURCE_SDMMC2 0x154 165#define CLK_SOURCE_SDMMC3 0x1bc 166#define CLK_SOURCE_SDMMC4 0x164 167#define CLK_SOURCE_VDE 0x1c8 168#define CLK_SOURCE_CSITE 0x1d4 169#define CLK_SOURCE_LA 0x1f8 170#define CLK_SOURCE_OWR 0x1cc 171#define CLK_SOURCE_NOR 0x1d0 172#define CLK_SOURCE_MIPI 0x174 173#define CLK_SOURCE_I2C1 0x124 174#define CLK_SOURCE_I2C2 0x198 175#define CLK_SOURCE_I2C3 0x1b8 176#define CLK_SOURCE_I2C4 0x3c4 177#define CLK_SOURCE_I2C5 0x128 178#define CLK_SOURCE_UARTA 0x178 179#define CLK_SOURCE_UARTB 0x17c 180#define CLK_SOURCE_UARTC 0x1a0 181#define CLK_SOURCE_UARTD 0x1c0 182#define CLK_SOURCE_UARTE 0x1c4 183#define CLK_SOURCE_VI 0x148 184#define CLK_SOURCE_VI_SENSOR 0x1a8 185#define CLK_SOURCE_3D 0x158 186#define CLK_SOURCE_3D2 0x3b0 187#define CLK_SOURCE_2D 0x15c 188#define CLK_SOURCE_EPP 0x16c 189#define CLK_SOURCE_MPE 0x170 190#define CLK_SOURCE_HOST1X 0x180 191#define CLK_SOURCE_CVE 0x140 192#define CLK_SOURCE_TVO 0x188 193#define CLK_SOURCE_DTV 0x1dc 194#define CLK_SOURCE_HDMI 0x18c 195#define CLK_SOURCE_TVDAC 0x194 196#define CLK_SOURCE_DISP1 0x138 197#define CLK_SOURCE_DISP2 0x13c 198#define CLK_SOURCE_DSIB 0xd0 199#define CLK_SOURCE_TSENSOR 0x3b8 200#define CLK_SOURCE_ACTMON 0x3e8 201#define CLK_SOURCE_EXTERN1 0x3ec 202#define CLK_SOURCE_EXTERN2 0x3f0 203#define CLK_SOURCE_EXTERN3 0x3f4 204#define CLK_SOURCE_I2CSLOW 0x3fc 205#define CLK_SOURCE_SE 0x42c 206#define CLK_SOURCE_MSELECT 0x3b4 207#define CLK_SOURCE_EMC 0x19c 208 209#define AUDIO_SYNC_DOUBLER 0x49c 210 211#define PMC_CTRL 0 212#define PMC_CTRL_BLINK_ENB 7 213 214#define PMC_DPD_PADS_ORIDE 0x1c 215#define PMC_DPD_PADS_ORIDE_BLINK_ENB 20 216#define PMC_BLINK_TIMER 0x40 217 218#define UTMIP_PLL_CFG2 0x488 219#define UTMIP_PLL_CFG2_STABLE_COUNT(x) (((x) & 0xffff) << 6) 220#define UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(x) (((x) & 0x3f) << 18) 221#define UTMIP_PLL_CFG2_FORCE_PD_SAMP_A_POWERDOWN BIT(0) 222#define UTMIP_PLL_CFG2_FORCE_PD_SAMP_B_POWERDOWN BIT(2) 223#define UTMIP_PLL_CFG2_FORCE_PD_SAMP_C_POWERDOWN BIT(4) 224 225#define UTMIP_PLL_CFG1 0x484 226#define UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(x) (((x) & 0x1f) << 6) 227#define UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(x) (((x) & 0xfff) << 0) 228#define UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN BIT(14) 229#define UTMIP_PLL_CFG1_FORCE_PLL_ACTIVE_POWERDOWN BIT(12) 230#define UTMIP_PLL_CFG1_FORCE_PLLU_POWERDOWN BIT(16) 231 232/* Tegra CPU clock and reset control regs */ 233#define TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX 0x4c 234#define TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET 0x340 235#define TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR 0x344 236#define TEGRA30_CLK_RST_CONTROLLER_CLK_CPU_CMPLX_CLR 0x34c 237#define TEGRA30_CLK_RST_CONTROLLER_CPU_CMPLX_STATUS 0x470 238 239#define CPU_CLOCK(cpu) (0x1 << (8 + cpu)) 240#define CPU_RESET(cpu) (0x1111ul << (cpu)) 241 242#define CLK_RESET_CCLK_BURST 0x20 243#define CLK_RESET_CCLK_DIVIDER 0x24 244#define CLK_RESET_PLLX_BASE 0xe0 245#define CLK_RESET_PLLX_MISC 0xe4 246 247#define CLK_RESET_SOURCE_CSITE 0x1d4 248 249#define CLK_RESET_CCLK_BURST_POLICY_SHIFT 28 250#define CLK_RESET_CCLK_RUN_POLICY_SHIFT 4 251#define CLK_RESET_CCLK_IDLE_POLICY_SHIFT 0 252#define CLK_RESET_CCLK_IDLE_POLICY 1 253#define CLK_RESET_CCLK_RUN_POLICY 2 254#define CLK_RESET_CCLK_BURST_POLICY_PLLX 8 255 256#ifdef CONFIG_PM_SLEEP 257static struct cpu_clk_suspend_context { 258 u32 pllx_misc; 259 u32 pllx_base; 260 261 u32 cpu_burst; 262 u32 clk_csite_src; 263 u32 cclk_divider; 264} tegra30_cpu_clk_sctx; 265#endif 266 267static int periph_clk_enb_refcnt[CLK_OUT_ENB_NUM * 32]; 268 269static void __iomem *clk_base; 270static void __iomem *pmc_base; 271static unsigned long input_freq; 272 273static DEFINE_SPINLOCK(clk_doubler_lock); 274static DEFINE_SPINLOCK(clk_out_lock); 275static DEFINE_SPINLOCK(pll_div_lock); 276static DEFINE_SPINLOCK(cml_lock); 277static DEFINE_SPINLOCK(pll_d_lock); 278static DEFINE_SPINLOCK(sysrate_lock); 279 280#define TEGRA_INIT_DATA_MUX(_name, _con_id, _dev_id, _parents, _offset, \ 281 _clk_num, _regs, _gate_flags, _clk_id) \ 282 TEGRA_INIT_DATA(_name, _con_id, _dev_id, _parents, _offset, \ 283 30, 2, 0, 0, 8, 1, 0, _regs, _clk_num, \ 284 periph_clk_enb_refcnt, _gate_flags, _clk_id) 285 286#define TEGRA_INIT_DATA_DIV16(_name, _con_id, _dev_id, _parents, _offset, \ 287 _clk_num, _regs, _gate_flags, _clk_id) \ 288 TEGRA_INIT_DATA(_name, _con_id, _dev_id, _parents, _offset, \ 289 30, 2, 0, 0, 16, 0, TEGRA_DIVIDER_ROUND_UP, \ 290 _regs, _clk_num, periph_clk_enb_refcnt, \ 291 _gate_flags, _clk_id) 292 293#define TEGRA_INIT_DATA_MUX8(_name, _con_id, _dev_id, _parents, _offset, \ 294 _clk_num, _regs, _gate_flags, _clk_id) \ 295 TEGRA_INIT_DATA(_name, _con_id, _dev_id, _parents, _offset, \ 296 29, 3, 0, 0, 8, 1, 0, _regs, _clk_num, \ 297 periph_clk_enb_refcnt, _gate_flags, _clk_id) 298 299#define TEGRA_INIT_DATA_INT(_name, _con_id, _dev_id, _parents, _offset, \ 300 _clk_num, _regs, _gate_flags, _clk_id) \ 301 TEGRA_INIT_DATA(_name, _con_id, _dev_id, _parents, _offset, \ 302 30, 2, 0, 0, 8, 1, TEGRA_DIVIDER_INT, _regs, \ 303 _clk_num, periph_clk_enb_refcnt, _gate_flags, \ 304 _clk_id) 305 306#define TEGRA_INIT_DATA_UART(_name, _con_id, _dev_id, _parents, _offset,\ 307 _clk_num, _regs, _clk_id) \ 308 TEGRA_INIT_DATA(_name, _con_id, _dev_id, _parents, _offset, \ 309 30, 2, 0, 0, 16, 1, TEGRA_DIVIDER_UART, _regs, \ 310 _clk_num, periph_clk_enb_refcnt, 0, _clk_id) 311 312#define TEGRA_INIT_DATA_NODIV(_name, _con_id, _dev_id, _parents, _offset, \ 313 _mux_shift, _mux_width, _clk_num, _regs, \ 314 _gate_flags, _clk_id) \ 315 TEGRA_INIT_DATA(_name, _con_id, _dev_id, _parents, _offset, \ 316 _mux_shift, _mux_width, 0, 0, 0, 0, 0, _regs, \ 317 _clk_num, periph_clk_enb_refcnt, _gate_flags, \ 318 _clk_id) 319 320/* 321 * IDs assigned here must be in sync with DT bindings definition 322 * for Tegra30 clocks. 323 */ 324enum tegra30_clk { 325 cpu, rtc = 4, timer, uarta, gpio = 8, sdmmc2, i2s1 = 11, i2c1, ndflash, 326 sdmmc1, sdmmc4, pwm = 17, i2s2, epp, gr2d = 21, usbd, isp, gr3d, 327 disp2 = 26, disp1, host1x, vcp, i2s0, cop_cache, mc, ahbdma, apbdma, 328 kbc = 36, statmon, pmc, kfuse = 40, sbc1, nor, sbc2 = 44, sbc3 = 46, 329 i2c5, dsia, mipi = 50, hdmi, csi, tvdac, i2c2, uartc, emc = 57, usb2, 330 usb3, mpe, vde, bsea, bsev, speedo, uartd, uarte, i2c3, sbc4, sdmmc3, 331 pcie, owr, afi, csite, pciex, avpucq, la, dtv = 79, ndspeed, i2cslow, 332 dsib, irama = 84, iramb, iramc, iramd, cram2, audio_2x = 90, csus = 92, 333 cdev2, cdev1, cpu_g = 96, cpu_lp, gr3d2, mselect, tsensor, i2s3, i2s4, 334 i2c4, sbc5, sbc6, d_audio, apbif, dam0, dam1, dam2, hda2codec_2x, 335 atomics, audio0_2x, audio1_2x, audio2_2x, audio3_2x, audio4_2x, 336 spdif_2x, actmon, extern1, extern2, extern3, sata_oob, sata, hda, 337 se = 127, hda2hdmi, sata_cold, uartb = 160, vfir, spdif_in, spdif_out, 338 vi, vi_sensor, fuse, fuse_burn, cve, tvo, clk_32k, clk_m, clk_m_div2, 339 clk_m_div4, pll_ref, pll_c, pll_c_out1, pll_m, pll_m_out1, pll_p, 340 pll_p_out1, pll_p_out2, pll_p_out3, pll_p_out4, pll_a, pll_a_out0, 341 pll_d, pll_d_out0, pll_d2, pll_d2_out0, pll_u, pll_x, pll_x_out0, pll_e, 342 spdif_in_sync, i2s0_sync, i2s1_sync, i2s2_sync, i2s3_sync, i2s4_sync, 343 vimclk_sync, audio0, audio1, audio2, audio3, audio4, spdif, clk_out_1, 344 clk_out_2, clk_out_3, sclk, blink, cclk_g, cclk_lp, twd, cml0, cml1, 345 hclk, pclk, clk_out_1_mux = 300, clk_max 346}; 347 348static struct clk *clks[clk_max]; 349static struct clk_onecell_data clk_data; 350 351/* 352 * Structure defining the fields for USB UTMI clocks Parameters. 353 */ 354struct utmi_clk_param { 355 /* Oscillator Frequency in KHz */ 356 u32 osc_frequency; 357 /* UTMIP PLL Enable Delay Count */ 358 u8 enable_delay_count; 359 /* UTMIP PLL Stable count */ 360 u8 stable_count; 361 /* UTMIP PLL Active delay count */ 362 u8 active_delay_count; 363 /* UTMIP PLL Xtal frequency count */ 364 u8 xtal_freq_count; 365}; 366 367static const struct utmi_clk_param utmi_parameters[] = { 368/* OSC_FREQUENCY, ENABLE_DLY, STABLE_CNT, ACTIVE_DLY, XTAL_FREQ_CNT */ 369 {13000000, 0x02, 0x33, 0x05, 0x7F}, 370 {19200000, 0x03, 0x4B, 0x06, 0xBB}, 371 {12000000, 0x02, 0x2F, 0x04, 0x76}, 372 {26000000, 0x04, 0x66, 0x09, 0xFE}, 373 {16800000, 0x03, 0x41, 0x0A, 0xA4}, 374}; 375 376static struct tegra_clk_pll_freq_table pll_c_freq_table[] = { 377 { 12000000, 1040000000, 520, 6, 0, 8}, 378 { 13000000, 1040000000, 480, 6, 0, 8}, 379 { 16800000, 1040000000, 495, 8, 0, 8}, /* actual: 1039.5 MHz */ 380 { 19200000, 1040000000, 325, 6, 0, 6}, 381 { 26000000, 1040000000, 520, 13, 0, 8}, 382 383 { 12000000, 832000000, 416, 6, 0, 8}, 384 { 13000000, 832000000, 832, 13, 0, 8}, 385 { 16800000, 832000000, 396, 8, 0, 8}, /* actual: 831.6 MHz */ 386 { 19200000, 832000000, 260, 6, 0, 8}, 387 { 26000000, 832000000, 416, 13, 0, 8}, 388 389 { 12000000, 624000000, 624, 12, 0, 8}, 390 { 13000000, 624000000, 624, 13, 0, 8}, 391 { 16800000, 600000000, 520, 14, 0, 8}, 392 { 19200000, 624000000, 520, 16, 0, 8}, 393 { 26000000, 624000000, 624, 26, 0, 8}, 394 395 { 12000000, 600000000, 600, 12, 0, 8}, 396 { 13000000, 600000000, 600, 13, 0, 8}, 397 { 16800000, 600000000, 500, 14, 0, 8}, 398 { 19200000, 600000000, 375, 12, 0, 6}, 399 { 26000000, 600000000, 600, 26, 0, 8}, 400 401 { 12000000, 520000000, 520, 12, 0, 8}, 402 { 13000000, 520000000, 520, 13, 0, 8}, 403 { 16800000, 520000000, 495, 16, 0, 8}, /* actual: 519.75 MHz */ 404 { 19200000, 520000000, 325, 12, 0, 6}, 405 { 26000000, 520000000, 520, 26, 0, 8}, 406 407 { 12000000, 416000000, 416, 12, 0, 8}, 408 { 13000000, 416000000, 416, 13, 0, 8}, 409 { 16800000, 416000000, 396, 16, 0, 8}, /* actual: 415.8 MHz */ 410 { 19200000, 416000000, 260, 12, 0, 6}, 411 { 26000000, 416000000, 416, 26, 0, 8}, 412 { 0, 0, 0, 0, 0, 0 }, 413}; 414 415static struct tegra_clk_pll_freq_table pll_m_freq_table[] = { 416 { 12000000, 666000000, 666, 12, 0, 8}, 417 { 13000000, 666000000, 666, 13, 0, 8}, 418 { 16800000, 666000000, 555, 14, 0, 8}, 419 { 19200000, 666000000, 555, 16, 0, 8}, 420 { 26000000, 666000000, 666, 26, 0, 8}, 421 { 12000000, 600000000, 600, 12, 0, 8}, 422 { 13000000, 600000000, 600, 13, 0, 8}, 423 { 16800000, 600000000, 500, 14, 0, 8}, 424 { 19200000, 600000000, 375, 12, 0, 6}, 425 { 26000000, 600000000, 600, 26, 0, 8}, 426 { 0, 0, 0, 0, 0, 0 }, 427}; 428 429static struct tegra_clk_pll_freq_table pll_p_freq_table[] = { 430 { 12000000, 216000000, 432, 12, 1, 8}, 431 { 13000000, 216000000, 432, 13, 1, 8}, 432 { 16800000, 216000000, 360, 14, 1, 8}, 433 { 19200000, 216000000, 360, 16, 1, 8}, 434 { 26000000, 216000000, 432, 26, 1, 8}, 435 { 0, 0, 0, 0, 0, 0 }, 436}; 437 438static struct tegra_clk_pll_freq_table pll_a_freq_table[] = { 439 { 9600000, 564480000, 294, 5, 0, 4}, 440 { 9600000, 552960000, 288, 5, 0, 4}, 441 { 9600000, 24000000, 5, 2, 0, 1}, 442 443 { 28800000, 56448000, 49, 25, 0, 1}, 444 { 28800000, 73728000, 64, 25, 0, 1}, 445 { 28800000, 24000000, 5, 6, 0, 1}, 446 { 0, 0, 0, 0, 0, 0 }, 447}; 448 449static struct tegra_clk_pll_freq_table pll_d_freq_table[] = { 450 { 12000000, 216000000, 216, 12, 0, 4}, 451 { 13000000, 216000000, 216, 13, 0, 4}, 452 { 16800000, 216000000, 180, 14, 0, 4}, 453 { 19200000, 216000000, 180, 16, 0, 4}, 454 { 26000000, 216000000, 216, 26, 0, 4}, 455 456 { 12000000, 594000000, 594, 12, 0, 8}, 457 { 13000000, 594000000, 594, 13, 0, 8}, 458 { 16800000, 594000000, 495, 14, 0, 8}, 459 { 19200000, 594000000, 495, 16, 0, 8}, 460 { 26000000, 594000000, 594, 26, 0, 8}, 461 462 { 12000000, 1000000000, 1000, 12, 0, 12}, 463 { 13000000, 1000000000, 1000, 13, 0, 12}, 464 { 19200000, 1000000000, 625, 12, 0, 8}, 465 { 26000000, 1000000000, 1000, 26, 0, 12}, 466 467 { 0, 0, 0, 0, 0, 0 }, 468}; 469 470static struct pdiv_map pllu_p[] = { 471 { .pdiv = 1, .hw_val = 1 }, 472 { .pdiv = 2, .hw_val = 0 }, 473 { .pdiv = 0, .hw_val = 0 }, 474}; 475 476static struct tegra_clk_pll_freq_table pll_u_freq_table[] = { 477 { 12000000, 480000000, 960, 12, 0, 12}, 478 { 13000000, 480000000, 960, 13, 0, 12}, 479 { 16800000, 480000000, 400, 7, 0, 5}, 480 { 19200000, 480000000, 200, 4, 0, 3}, 481 { 26000000, 480000000, 960, 26, 0, 12}, 482 { 0, 0, 0, 0, 0, 0 }, 483}; 484 485static struct tegra_clk_pll_freq_table pll_x_freq_table[] = { 486 /* 1.7 GHz */ 487 { 12000000, 1700000000, 850, 6, 0, 8}, 488 { 13000000, 1700000000, 915, 7, 0, 8}, /* actual: 1699.2 MHz */ 489 { 16800000, 1700000000, 708, 7, 0, 8}, /* actual: 1699.2 MHz */ 490 { 19200000, 1700000000, 885, 10, 0, 8}, /* actual: 1699.2 MHz */ 491 { 26000000, 1700000000, 850, 13, 0, 8}, 492 493 /* 1.6 GHz */ 494 { 12000000, 1600000000, 800, 6, 0, 8}, 495 { 13000000, 1600000000, 738, 6, 0, 8}, /* actual: 1599.0 MHz */ 496 { 16800000, 1600000000, 857, 9, 0, 8}, /* actual: 1599.7 MHz */ 497 { 19200000, 1600000000, 500, 6, 0, 8}, 498 { 26000000, 1600000000, 800, 13, 0, 8}, 499 500 /* 1.5 GHz */ 501 { 12000000, 1500000000, 750, 6, 0, 8}, 502 { 13000000, 1500000000, 923, 8, 0, 8}, /* actual: 1499.8 MHz */ 503 { 16800000, 1500000000, 625, 7, 0, 8}, 504 { 19200000, 1500000000, 625, 8, 0, 8}, 505 { 26000000, 1500000000, 750, 13, 0, 8}, 506 507 /* 1.4 GHz */ 508 { 12000000, 1400000000, 700, 6, 0, 8}, 509 { 13000000, 1400000000, 969, 9, 0, 8}, /* actual: 1399.7 MHz */ 510 { 16800000, 1400000000, 1000, 12, 0, 8}, 511 { 19200000, 1400000000, 875, 12, 0, 8}, 512 { 26000000, 1400000000, 700, 13, 0, 8}, 513 514 /* 1.3 GHz */ 515 { 12000000, 1300000000, 975, 9, 0, 8}, 516 { 13000000, 1300000000, 1000, 10, 0, 8}, 517 { 16800000, 1300000000, 928, 12, 0, 8}, /* actual: 1299.2 MHz */ 518 { 19200000, 1300000000, 812, 12, 0, 8}, /* actual: 1299.2 MHz */ 519 { 26000000, 1300000000, 650, 13, 0, 8}, 520 521 /* 1.2 GHz */ 522 { 12000000, 1200000000, 1000, 10, 0, 8}, 523 { 13000000, 1200000000, 923, 10, 0, 8}, /* actual: 1199.9 MHz */ 524 { 16800000, 1200000000, 1000, 14, 0, 8}, 525 { 19200000, 1200000000, 1000, 16, 0, 8}, 526 { 26000000, 1200000000, 600, 13, 0, 8}, 527 528 /* 1.1 GHz */ 529 { 12000000, 1100000000, 825, 9, 0, 8}, 530 { 13000000, 1100000000, 846, 10, 0, 8}, /* actual: 1099.8 MHz */ 531 { 16800000, 1100000000, 982, 15, 0, 8}, /* actual: 1099.8 MHz */ 532 { 19200000, 1100000000, 859, 15, 0, 8}, /* actual: 1099.5 MHz */ 533 { 26000000, 1100000000, 550, 13, 0, 8}, 534 535 /* 1 GHz */ 536 { 12000000, 1000000000, 1000, 12, 0, 8}, 537 { 13000000, 1000000000, 1000, 13, 0, 8}, 538 { 16800000, 1000000000, 833, 14, 0, 8}, /* actual: 999.6 MHz */ 539 { 19200000, 1000000000, 625, 12, 0, 8}, 540 { 26000000, 1000000000, 1000, 26, 0, 8}, 541 542 { 0, 0, 0, 0, 0, 0 }, 543}; 544 545static struct tegra_clk_pll_freq_table pll_e_freq_table[] = { 546 /* PLLE special case: use cpcon field to store cml divider value */ 547 { 12000000, 100000000, 150, 1, 18, 11}, 548 { 216000000, 100000000, 200, 18, 24, 13}, 549 { 0, 0, 0, 0, 0, 0 }, 550}; 551 552/* PLL parameters */ 553static struct tegra_clk_pll_params pll_c_params = { 554 .input_min = 2000000, 555 .input_max = 31000000, 556 .cf_min = 1000000, 557 .cf_max = 6000000, 558 .vco_min = 20000000, 559 .vco_max = 1400000000, 560 .base_reg = PLLC_BASE, 561 .misc_reg = PLLC_MISC, 562 .lock_bit_idx = PLL_BASE_LOCK, 563 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE, 564 .lock_delay = 300, 565}; 566 567static struct tegra_clk_pll_params pll_m_params = { 568 .input_min = 2000000, 569 .input_max = 31000000, 570 .cf_min = 1000000, 571 .cf_max = 6000000, 572 .vco_min = 20000000, 573 .vco_max = 1200000000, 574 .base_reg = PLLM_BASE, 575 .misc_reg = PLLM_MISC, 576 .lock_bit_idx = PLL_BASE_LOCK, 577 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE, 578 .lock_delay = 300, 579}; 580 581static struct tegra_clk_pll_params pll_p_params = { 582 .input_min = 2000000, 583 .input_max = 31000000, 584 .cf_min = 1000000, 585 .cf_max = 6000000, 586 .vco_min = 20000000, 587 .vco_max = 1400000000, 588 .base_reg = PLLP_BASE, 589 .misc_reg = PLLP_MISC, 590 .lock_bit_idx = PLL_BASE_LOCK, 591 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE, 592 .lock_delay = 300, 593}; 594 595static struct tegra_clk_pll_params pll_a_params = { 596 .input_min = 2000000, 597 .input_max = 31000000, 598 .cf_min = 1000000, 599 .cf_max = 6000000, 600 .vco_min = 20000000, 601 .vco_max = 1400000000, 602 .base_reg = PLLA_BASE, 603 .misc_reg = PLLA_MISC, 604 .lock_bit_idx = PLL_BASE_LOCK, 605 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE, 606 .lock_delay = 300, 607}; 608 609static struct tegra_clk_pll_params pll_d_params = { 610 .input_min = 2000000, 611 .input_max = 40000000, 612 .cf_min = 1000000, 613 .cf_max = 6000000, 614 .vco_min = 40000000, 615 .vco_max = 1000000000, 616 .base_reg = PLLD_BASE, 617 .misc_reg = PLLD_MISC, 618 .lock_bit_idx = PLL_BASE_LOCK, 619 .lock_enable_bit_idx = PLLDU_MISC_LOCK_ENABLE, 620 .lock_delay = 1000, 621}; 622 623static struct tegra_clk_pll_params pll_d2_params = { 624 .input_min = 2000000, 625 .input_max = 40000000, 626 .cf_min = 1000000, 627 .cf_max = 6000000, 628 .vco_min = 40000000, 629 .vco_max = 1000000000, 630 .base_reg = PLLD2_BASE, 631 .misc_reg = PLLD2_MISC, 632 .lock_bit_idx = PLL_BASE_LOCK, 633 .lock_enable_bit_idx = PLLDU_MISC_LOCK_ENABLE, 634 .lock_delay = 1000, 635}; 636 637static struct tegra_clk_pll_params pll_u_params = { 638 .input_min = 2000000, 639 .input_max = 40000000, 640 .cf_min = 1000000, 641 .cf_max = 6000000, 642 .vco_min = 48000000, 643 .vco_max = 960000000, 644 .base_reg = PLLU_BASE, 645 .misc_reg = PLLU_MISC, 646 .lock_bit_idx = PLL_BASE_LOCK, 647 .lock_enable_bit_idx = PLLDU_MISC_LOCK_ENABLE, 648 .lock_delay = 1000, 649 .pdiv_tohw = pllu_p, 650}; 651 652static struct tegra_clk_pll_params pll_x_params = { 653 .input_min = 2000000, 654 .input_max = 31000000, 655 .cf_min = 1000000, 656 .cf_max = 6000000, 657 .vco_min = 20000000, 658 .vco_max = 1700000000, 659 .base_reg = PLLX_BASE, 660 .misc_reg = PLLX_MISC, 661 .lock_bit_idx = PLL_BASE_LOCK, 662 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE, 663 .lock_delay = 300, 664}; 665 666static struct tegra_clk_pll_params pll_e_params = { 667 .input_min = 12000000, 668 .input_max = 216000000, 669 .cf_min = 12000000, 670 .cf_max = 12000000, 671 .vco_min = 1200000000, 672 .vco_max = 2400000000U, 673 .base_reg = PLLE_BASE, 674 .misc_reg = PLLE_MISC, 675 .lock_bit_idx = PLLE_MISC_LOCK, 676 .lock_enable_bit_idx = PLLE_MISC_LOCK_ENABLE, 677 .lock_delay = 300, 678}; 679 680/* Peripheral clock registers */ 681static struct tegra_clk_periph_regs periph_l_regs = { 682 .enb_reg = CLK_OUT_ENB_L, 683 .enb_set_reg = CLK_OUT_ENB_SET_L, 684 .enb_clr_reg = CLK_OUT_ENB_CLR_L, 685 .rst_reg = RST_DEVICES_L, 686 .rst_set_reg = RST_DEVICES_SET_L, 687 .rst_clr_reg = RST_DEVICES_CLR_L, 688}; 689 690static struct tegra_clk_periph_regs periph_h_regs = { 691 .enb_reg = CLK_OUT_ENB_H, 692 .enb_set_reg = CLK_OUT_ENB_SET_H, 693 .enb_clr_reg = CLK_OUT_ENB_CLR_H, 694 .rst_reg = RST_DEVICES_H, 695 .rst_set_reg = RST_DEVICES_SET_H, 696 .rst_clr_reg = RST_DEVICES_CLR_H, 697}; 698 699static struct tegra_clk_periph_regs periph_u_regs = { 700 .enb_reg = CLK_OUT_ENB_U, 701 .enb_set_reg = CLK_OUT_ENB_SET_U, 702 .enb_clr_reg = CLK_OUT_ENB_CLR_U, 703 .rst_reg = RST_DEVICES_U, 704 .rst_set_reg = RST_DEVICES_SET_U, 705 .rst_clr_reg = RST_DEVICES_CLR_U, 706}; 707 708static struct tegra_clk_periph_regs periph_v_regs = { 709 .enb_reg = CLK_OUT_ENB_V, 710 .enb_set_reg = CLK_OUT_ENB_SET_V, 711 .enb_clr_reg = CLK_OUT_ENB_CLR_V, 712 .rst_reg = RST_DEVICES_V, 713 .rst_set_reg = RST_DEVICES_SET_V, 714 .rst_clr_reg = RST_DEVICES_CLR_V, 715}; 716 717static struct tegra_clk_periph_regs periph_w_regs = { 718 .enb_reg = CLK_OUT_ENB_W, 719 .enb_set_reg = CLK_OUT_ENB_SET_W, 720 .enb_clr_reg = CLK_OUT_ENB_CLR_W, 721 .rst_reg = RST_DEVICES_W, 722 .rst_set_reg = RST_DEVICES_SET_W, 723 .rst_clr_reg = RST_DEVICES_CLR_W, 724}; 725 726static void tegra30_clk_measure_input_freq(void) 727{ 728 u32 osc_ctrl = readl_relaxed(clk_base + OSC_CTRL); 729 u32 auto_clk_control = osc_ctrl & OSC_CTRL_OSC_FREQ_MASK; 730 u32 pll_ref_div = osc_ctrl & OSC_CTRL_PLL_REF_DIV_MASK; 731 732 switch (auto_clk_control) { 733 case OSC_CTRL_OSC_FREQ_12MHZ: 734 BUG_ON(pll_ref_div != OSC_CTRL_PLL_REF_DIV_1); 735 input_freq = 12000000; 736 break; 737 case OSC_CTRL_OSC_FREQ_13MHZ: 738 BUG_ON(pll_ref_div != OSC_CTRL_PLL_REF_DIV_1); 739 input_freq = 13000000; 740 break; 741 case OSC_CTRL_OSC_FREQ_19_2MHZ: 742 BUG_ON(pll_ref_div != OSC_CTRL_PLL_REF_DIV_1); 743 input_freq = 19200000; 744 break; 745 case OSC_CTRL_OSC_FREQ_26MHZ: 746 BUG_ON(pll_ref_div != OSC_CTRL_PLL_REF_DIV_1); 747 input_freq = 26000000; 748 break; 749 case OSC_CTRL_OSC_FREQ_16_8MHZ: 750 BUG_ON(pll_ref_div != OSC_CTRL_PLL_REF_DIV_1); 751 input_freq = 16800000; 752 break; 753 case OSC_CTRL_OSC_FREQ_38_4MHZ: 754 BUG_ON(pll_ref_div != OSC_CTRL_PLL_REF_DIV_2); 755 input_freq = 38400000; 756 break; 757 case OSC_CTRL_OSC_FREQ_48MHZ: 758 BUG_ON(pll_ref_div != OSC_CTRL_PLL_REF_DIV_4); 759 input_freq = 48000000; 760 break; 761 default: 762 pr_err("Unexpected auto clock control value %d", 763 auto_clk_control); 764 BUG(); 765 return; 766 } 767} 768 769static unsigned int tegra30_get_pll_ref_div(void) 770{ 771 u32 pll_ref_div = readl_relaxed(clk_base + OSC_CTRL) & 772 OSC_CTRL_PLL_REF_DIV_MASK; 773 774 switch (pll_ref_div) { 775 case OSC_CTRL_PLL_REF_DIV_1: 776 return 1; 777 case OSC_CTRL_PLL_REF_DIV_2: 778 return 2; 779 case OSC_CTRL_PLL_REF_DIV_4: 780 return 4; 781 default: 782 pr_err("Invalid pll ref divider %d", pll_ref_div); 783 BUG(); 784 } 785 return 0; 786} 787 788static void tegra30_utmi_param_configure(void) 789{ 790 u32 reg; 791 int i; 792 793 for (i = 0; i < ARRAY_SIZE(utmi_parameters); i++) { 794 if (input_freq == utmi_parameters[i].osc_frequency) 795 break; 796 } 797 798 if (i >= ARRAY_SIZE(utmi_parameters)) { 799 pr_err("%s: Unexpected input rate %lu\n", __func__, input_freq); 800 return; 801 } 802 803 reg = readl_relaxed(clk_base + UTMIP_PLL_CFG2); 804 805 /* Program UTMIP PLL stable and active counts */ 806 reg &= ~UTMIP_PLL_CFG2_STABLE_COUNT(~0); 807 reg |= UTMIP_PLL_CFG2_STABLE_COUNT( 808 utmi_parameters[i].stable_count); 809 810 reg &= ~UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(~0); 811 812 reg |= UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT( 813 utmi_parameters[i].active_delay_count); 814 815 /* Remove power downs from UTMIP PLL control bits */ 816 reg &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_A_POWERDOWN; 817 reg &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_B_POWERDOWN; 818 reg &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_C_POWERDOWN; 819 820 writel_relaxed(reg, clk_base + UTMIP_PLL_CFG2); 821 822 /* Program UTMIP PLL delay and oscillator frequency counts */ 823 reg = readl_relaxed(clk_base + UTMIP_PLL_CFG1); 824 reg &= ~UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(~0); 825 826 reg |= UTMIP_PLL_CFG1_ENABLE_DLY_COUNT( 827 utmi_parameters[i].enable_delay_count); 828 829 reg &= ~UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(~0); 830 reg |= UTMIP_PLL_CFG1_XTAL_FREQ_COUNT( 831 utmi_parameters[i].xtal_freq_count); 832 833 /* Remove power downs from UTMIP PLL control bits */ 834 reg &= ~UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN; 835 reg &= ~UTMIP_PLL_CFG1_FORCE_PLL_ACTIVE_POWERDOWN; 836 reg &= ~UTMIP_PLL_CFG1_FORCE_PLLU_POWERDOWN; 837 838 writel_relaxed(reg, clk_base + UTMIP_PLL_CFG1); 839} 840 841static const char *pll_e_parents[] = {"pll_ref", "pll_p"}; 842 843static void __init tegra30_pll_init(void) 844{ 845 struct clk *clk; 846 847 /* PLLC */ 848 clk = tegra_clk_register_pll("pll_c", "pll_ref", clk_base, pmc_base, 0, 849 0, &pll_c_params, 850 TEGRA_PLL_HAS_CPCON | TEGRA_PLL_USE_LOCK, 851 pll_c_freq_table, NULL); 852 clk_register_clkdev(clk, "pll_c", NULL); 853 clks[pll_c] = clk; 854 855 /* PLLC_OUT1 */ 856 clk = tegra_clk_register_divider("pll_c_out1_div", "pll_c", 857 clk_base + PLLC_OUT, 0, TEGRA_DIVIDER_ROUND_UP, 858 8, 8, 1, NULL); 859 clk = tegra_clk_register_pll_out("pll_c_out1", "pll_c_out1_div", 860 clk_base + PLLC_OUT, 1, 0, CLK_SET_RATE_PARENT, 861 0, NULL); 862 clk_register_clkdev(clk, "pll_c_out1", NULL); 863 clks[pll_c_out1] = clk; 864 865 /* PLLP */ 866 clk = tegra_clk_register_pll("pll_p", "pll_ref", clk_base, pmc_base, 0, 867 408000000, &pll_p_params, 868 TEGRA_PLL_FIXED | TEGRA_PLL_HAS_CPCON | 869 TEGRA_PLL_USE_LOCK, pll_p_freq_table, NULL); 870 clk_register_clkdev(clk, "pll_p", NULL); 871 clks[pll_p] = clk; 872 873 /* PLLP_OUT1 */ 874 clk = tegra_clk_register_divider("pll_p_out1_div", "pll_p", 875 clk_base + PLLP_OUTA, 0, TEGRA_DIVIDER_FIXED | 876 TEGRA_DIVIDER_ROUND_UP, 8, 8, 1, 877 &pll_div_lock); 878 clk = tegra_clk_register_pll_out("pll_p_out1", "pll_p_out1_div", 879 clk_base + PLLP_OUTA, 1, 0, 880 CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0, 881 &pll_div_lock); 882 clk_register_clkdev(clk, "pll_p_out1", NULL); 883 clks[pll_p_out1] = clk; 884 885 /* PLLP_OUT2 */ 886 clk = tegra_clk_register_divider("pll_p_out2_div", "pll_p", 887 clk_base + PLLP_OUTA, 0, TEGRA_DIVIDER_FIXED | 888 TEGRA_DIVIDER_ROUND_UP, 24, 8, 1, 889 &pll_div_lock); 890 clk = tegra_clk_register_pll_out("pll_p_out2", "pll_p_out2_div", 891 clk_base + PLLP_OUTA, 17, 16, 892 CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0, 893 &pll_div_lock); 894 clk_register_clkdev(clk, "pll_p_out2", NULL); 895 clks[pll_p_out2] = clk; 896 897 /* PLLP_OUT3 */ 898 clk = tegra_clk_register_divider("pll_p_out3_div", "pll_p", 899 clk_base + PLLP_OUTB, 0, TEGRA_DIVIDER_FIXED | 900 TEGRA_DIVIDER_ROUND_UP, 8, 8, 1, 901 &pll_div_lock); 902 clk = tegra_clk_register_pll_out("pll_p_out3", "pll_p_out3_div", 903 clk_base + PLLP_OUTB, 1, 0, 904 CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0, 905 &pll_div_lock); 906 clk_register_clkdev(clk, "pll_p_out3", NULL); 907 clks[pll_p_out3] = clk; 908 909 /* PLLP_OUT4 */ 910 clk = tegra_clk_register_divider("pll_p_out4_div", "pll_p", 911 clk_base + PLLP_OUTB, 0, TEGRA_DIVIDER_FIXED | 912 TEGRA_DIVIDER_ROUND_UP, 24, 8, 1, 913 &pll_div_lock); 914 clk = tegra_clk_register_pll_out("pll_p_out4", "pll_p_out4_div", 915 clk_base + PLLP_OUTB, 17, 16, 916 CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0, 917 &pll_div_lock); 918 clk_register_clkdev(clk, "pll_p_out4", NULL); 919 clks[pll_p_out4] = clk; 920 921 /* PLLM */ 922 clk = tegra_clk_register_pll("pll_m", "pll_ref", clk_base, pmc_base, 923 CLK_IGNORE_UNUSED | CLK_SET_RATE_GATE, 0, 924 &pll_m_params, TEGRA_PLLM | TEGRA_PLL_HAS_CPCON | 925 TEGRA_PLL_SET_DCCON | TEGRA_PLL_USE_LOCK, 926 pll_m_freq_table, NULL); 927 clk_register_clkdev(clk, "pll_m", NULL); 928 clks[pll_m] = clk; 929 930 /* PLLM_OUT1 */ 931 clk = tegra_clk_register_divider("pll_m_out1_div", "pll_m", 932 clk_base + PLLM_OUT, 0, TEGRA_DIVIDER_ROUND_UP, 933 8, 8, 1, NULL); 934 clk = tegra_clk_register_pll_out("pll_m_out1", "pll_m_out1_div", 935 clk_base + PLLM_OUT, 1, 0, CLK_IGNORE_UNUSED | 936 CLK_SET_RATE_PARENT, 0, NULL); 937 clk_register_clkdev(clk, "pll_m_out1", NULL); 938 clks[pll_m_out1] = clk; 939 940 /* PLLX */ 941 clk = tegra_clk_register_pll("pll_x", "pll_ref", clk_base, pmc_base, 0, 942 0, &pll_x_params, TEGRA_PLL_HAS_CPCON | 943 TEGRA_PLL_SET_DCCON | TEGRA_PLL_USE_LOCK, 944 pll_x_freq_table, NULL); 945 clk_register_clkdev(clk, "pll_x", NULL); 946 clks[pll_x] = clk; 947 948 /* PLLX_OUT0 */ 949 clk = clk_register_fixed_factor(NULL, "pll_x_out0", "pll_x", 950 CLK_SET_RATE_PARENT, 1, 2); 951 clk_register_clkdev(clk, "pll_x_out0", NULL); 952 clks[pll_x_out0] = clk; 953 954 /* PLLU */ 955 clk = tegra_clk_register_pll("pll_u", "pll_ref", clk_base, pmc_base, 0, 956 0, &pll_u_params, TEGRA_PLLU | TEGRA_PLL_HAS_CPCON | 957 TEGRA_PLL_SET_LFCON | TEGRA_PLL_USE_LOCK, 958 pll_u_freq_table, 959 NULL); 960 clk_register_clkdev(clk, "pll_u", NULL); 961 clks[pll_u] = clk; 962 963 tegra30_utmi_param_configure(); 964 965 /* PLLD */ 966 clk = tegra_clk_register_pll("pll_d", "pll_ref", clk_base, pmc_base, 0, 967 0, &pll_d_params, TEGRA_PLL_HAS_CPCON | 968 TEGRA_PLL_SET_LFCON | TEGRA_PLL_USE_LOCK, 969 pll_d_freq_table, &pll_d_lock); 970 clk_register_clkdev(clk, "pll_d", NULL); 971 clks[pll_d] = clk; 972 973 /* PLLD_OUT0 */ 974 clk = clk_register_fixed_factor(NULL, "pll_d_out0", "pll_d", 975 CLK_SET_RATE_PARENT, 1, 2); 976 clk_register_clkdev(clk, "pll_d_out0", NULL); 977 clks[pll_d_out0] = clk; 978 979 /* PLLD2 */ 980 clk = tegra_clk_register_pll("pll_d2", "pll_ref", clk_base, pmc_base, 0, 981 0, &pll_d2_params, TEGRA_PLL_HAS_CPCON | 982 TEGRA_PLL_SET_LFCON | TEGRA_PLL_USE_LOCK, 983 pll_d_freq_table, NULL); 984 clk_register_clkdev(clk, "pll_d2", NULL); 985 clks[pll_d2] = clk; 986 987 /* PLLD2_OUT0 */ 988 clk = clk_register_fixed_factor(NULL, "pll_d2_out0", "pll_d2", 989 CLK_SET_RATE_PARENT, 1, 2); 990 clk_register_clkdev(clk, "pll_d2_out0", NULL); 991 clks[pll_d2_out0] = clk; 992 993 /* PLLA */ 994 clk = tegra_clk_register_pll("pll_a", "pll_p_out1", clk_base, pmc_base, 995 0, 0, &pll_a_params, TEGRA_PLL_HAS_CPCON | 996 TEGRA_PLL_USE_LOCK, pll_a_freq_table, NULL); 997 clk_register_clkdev(clk, "pll_a", NULL); 998 clks[pll_a] = clk; 999 1000 /* PLLA_OUT0 */ 1001 clk = tegra_clk_register_divider("pll_a_out0_div", "pll_a", 1002 clk_base + PLLA_OUT, 0, TEGRA_DIVIDER_ROUND_UP, 1003 8, 8, 1, NULL); 1004 clk = tegra_clk_register_pll_out("pll_a_out0", "pll_a_out0_div", 1005 clk_base + PLLA_OUT, 1, 0, CLK_IGNORE_UNUSED | 1006 CLK_SET_RATE_PARENT, 0, NULL); 1007 clk_register_clkdev(clk, "pll_a_out0", NULL); 1008 clks[pll_a_out0] = clk; 1009 1010 /* PLLE */ 1011 clk = clk_register_mux(NULL, "pll_e_mux", pll_e_parents, 1012 ARRAY_SIZE(pll_e_parents), 0, 1013 clk_base + PLLE_AUX, 2, 1, 0, NULL); 1014 clk = tegra_clk_register_plle("pll_e", "pll_e_mux", clk_base, pmc_base, 1015 CLK_GET_RATE_NOCACHE, 100000000, &pll_e_params, 1016 TEGRA_PLLE_CONFIGURE, pll_e_freq_table, NULL); 1017 clk_register_clkdev(clk, "pll_e", NULL); 1018 clks[pll_e] = clk; 1019} 1020 1021static const char *mux_audio_sync_clk[] = { "spdif_in_sync", "i2s0_sync", 1022 "i2s1_sync", "i2s2_sync", "i2s3_sync", "i2s4_sync", "vimclk_sync",}; 1023static const char *clk_out1_parents[] = { "clk_m", "clk_m_div2", 1024 "clk_m_div4", "extern1", }; 1025static const char *clk_out2_parents[] = { "clk_m", "clk_m_div2", 1026 "clk_m_div4", "extern2", }; 1027static const char *clk_out3_parents[] = { "clk_m", "clk_m_div2", 1028 "clk_m_div4", "extern3", }; 1029 1030static void __init tegra30_audio_clk_init(void) 1031{ 1032 struct clk *clk; 1033 1034 /* spdif_in_sync */ 1035 clk = tegra_clk_register_sync_source("spdif_in_sync", 24000000, 1036 24000000); 1037 clk_register_clkdev(clk, "spdif_in_sync", NULL); 1038 clks[spdif_in_sync] = clk; 1039 1040 /* i2s0_sync */ 1041 clk = tegra_clk_register_sync_source("i2s0_sync", 24000000, 24000000); 1042 clk_register_clkdev(clk, "i2s0_sync", NULL); 1043 clks[i2s0_sync] = clk; 1044 1045 /* i2s1_sync */ 1046 clk = tegra_clk_register_sync_source("i2s1_sync", 24000000, 24000000); 1047 clk_register_clkdev(clk, "i2s1_sync", NULL); 1048 clks[i2s1_sync] = clk; 1049 1050 /* i2s2_sync */ 1051 clk = tegra_clk_register_sync_source("i2s2_sync", 24000000, 24000000); 1052 clk_register_clkdev(clk, "i2s2_sync", NULL); 1053 clks[i2s2_sync] = clk; 1054 1055 /* i2s3_sync */ 1056 clk = tegra_clk_register_sync_source("i2s3_sync", 24000000, 24000000); 1057 clk_register_clkdev(clk, "i2s3_sync", NULL); 1058 clks[i2s3_sync] = clk; 1059 1060 /* i2s4_sync */ 1061 clk = tegra_clk_register_sync_source("i2s4_sync", 24000000, 24000000); 1062 clk_register_clkdev(clk, "i2s4_sync", NULL); 1063 clks[i2s4_sync] = clk; 1064 1065 /* vimclk_sync */ 1066 clk = tegra_clk_register_sync_source("vimclk_sync", 24000000, 24000000); 1067 clk_register_clkdev(clk, "vimclk_sync", NULL); 1068 clks[vimclk_sync] = clk; 1069 1070 /* audio0 */ 1071 clk = clk_register_mux(NULL, "audio0_mux", mux_audio_sync_clk, 1072 ARRAY_SIZE(mux_audio_sync_clk), 0, 1073 clk_base + AUDIO_SYNC_CLK_I2S0, 0, 3, 0, NULL); 1074 clk = clk_register_gate(NULL, "audio0", "audio0_mux", 0, 1075 clk_base + AUDIO_SYNC_CLK_I2S0, 4, 1076 CLK_GATE_SET_TO_DISABLE, NULL); 1077 clk_register_clkdev(clk, "audio0", NULL); 1078 clks[audio0] = clk; 1079 1080 /* audio1 */ 1081 clk = clk_register_mux(NULL, "audio1_mux", mux_audio_sync_clk, 1082 ARRAY_SIZE(mux_audio_sync_clk), 0, 1083 clk_base + AUDIO_SYNC_CLK_I2S1, 0, 3, 0, NULL); 1084 clk = clk_register_gate(NULL, "audio1", "audio1_mux", 0, 1085 clk_base + AUDIO_SYNC_CLK_I2S1, 4, 1086 CLK_GATE_SET_TO_DISABLE, NULL); 1087 clk_register_clkdev(clk, "audio1", NULL); 1088 clks[audio1] = clk; 1089 1090 /* audio2 */ 1091 clk = clk_register_mux(NULL, "audio2_mux", mux_audio_sync_clk, 1092 ARRAY_SIZE(mux_audio_sync_clk), 0, 1093 clk_base + AUDIO_SYNC_CLK_I2S2, 0, 3, 0, NULL); 1094 clk = clk_register_gate(NULL, "audio2", "audio2_mux", 0, 1095 clk_base + AUDIO_SYNC_CLK_I2S2, 4, 1096 CLK_GATE_SET_TO_DISABLE, NULL); 1097 clk_register_clkdev(clk, "audio2", NULL); 1098 clks[audio2] = clk; 1099 1100 /* audio3 */ 1101 clk = clk_register_mux(NULL, "audio3_mux", mux_audio_sync_clk, 1102 ARRAY_SIZE(mux_audio_sync_clk), 0, 1103 clk_base + AUDIO_SYNC_CLK_I2S3, 0, 3, 0, NULL); 1104 clk = clk_register_gate(NULL, "audio3", "audio3_mux", 0, 1105 clk_base + AUDIO_SYNC_CLK_I2S3, 4, 1106 CLK_GATE_SET_TO_DISABLE, NULL); 1107 clk_register_clkdev(clk, "audio3", NULL); 1108 clks[audio3] = clk; 1109 1110 /* audio4 */ 1111 clk = clk_register_mux(NULL, "audio4_mux", mux_audio_sync_clk, 1112 ARRAY_SIZE(mux_audio_sync_clk), 0, 1113 clk_base + AUDIO_SYNC_CLK_I2S4, 0, 3, 0, NULL); 1114 clk = clk_register_gate(NULL, "audio4", "audio4_mux", 0, 1115 clk_base + AUDIO_SYNC_CLK_I2S4, 4, 1116 CLK_GATE_SET_TO_DISABLE, NULL); 1117 clk_register_clkdev(clk, "audio4", NULL); 1118 clks[audio4] = clk; 1119 1120 /* spdif */ 1121 clk = clk_register_mux(NULL, "spdif_mux", mux_audio_sync_clk, 1122 ARRAY_SIZE(mux_audio_sync_clk), 0, 1123 clk_base + AUDIO_SYNC_CLK_SPDIF, 0, 3, 0, NULL); 1124 clk = clk_register_gate(NULL, "spdif", "spdif_mux", 0, 1125 clk_base + AUDIO_SYNC_CLK_SPDIF, 4, 1126 CLK_GATE_SET_TO_DISABLE, NULL); 1127 clk_register_clkdev(clk, "spdif", NULL); 1128 clks[spdif] = clk; 1129 1130 /* audio0_2x */ 1131 clk = clk_register_fixed_factor(NULL, "audio0_doubler", "audio0", 1132 CLK_SET_RATE_PARENT, 2, 1); 1133 clk = tegra_clk_register_divider("audio0_div", "audio0_doubler", 1134 clk_base + AUDIO_SYNC_DOUBLER, 0, 0, 24, 1, 0, 1135 &clk_doubler_lock); 1136 clk = tegra_clk_register_periph_gate("audio0_2x", "audio0_div", 1137 TEGRA_PERIPH_NO_RESET, clk_base, 1138 CLK_SET_RATE_PARENT, 113, &periph_v_regs, 1139 periph_clk_enb_refcnt); 1140 clk_register_clkdev(clk, "audio0_2x", NULL); 1141 clks[audio0_2x] = clk; 1142 1143 /* audio1_2x */ 1144 clk = clk_register_fixed_factor(NULL, "audio1_doubler", "audio1", 1145 CLK_SET_RATE_PARENT, 2, 1); 1146 clk = tegra_clk_register_divider("audio1_div", "audio1_doubler", 1147 clk_base + AUDIO_SYNC_DOUBLER, 0, 0, 25, 1, 0, 1148 &clk_doubler_lock); 1149 clk = tegra_clk_register_periph_gate("audio1_2x", "audio1_div", 1150 TEGRA_PERIPH_NO_RESET, clk_base, 1151 CLK_SET_RATE_PARENT, 114, &periph_v_regs, 1152 periph_clk_enb_refcnt); 1153 clk_register_clkdev(clk, "audio1_2x", NULL); 1154 clks[audio1_2x] = clk; 1155 1156 /* audio2_2x */ 1157 clk = clk_register_fixed_factor(NULL, "audio2_doubler", "audio2", 1158 CLK_SET_RATE_PARENT, 2, 1); 1159 clk = tegra_clk_register_divider("audio2_div", "audio2_doubler", 1160 clk_base + AUDIO_SYNC_DOUBLER, 0, 0, 26, 1, 0, 1161 &clk_doubler_lock); 1162 clk = tegra_clk_register_periph_gate("audio2_2x", "audio2_div", 1163 TEGRA_PERIPH_NO_RESET, clk_base, 1164 CLK_SET_RATE_PARENT, 115, &periph_v_regs, 1165 periph_clk_enb_refcnt); 1166 clk_register_clkdev(clk, "audio2_2x", NULL); 1167 clks[audio2_2x] = clk; 1168 1169 /* audio3_2x */ 1170 clk = clk_register_fixed_factor(NULL, "audio3_doubler", "audio3", 1171 CLK_SET_RATE_PARENT, 2, 1); 1172 clk = tegra_clk_register_divider("audio3_div", "audio3_doubler", 1173 clk_base + AUDIO_SYNC_DOUBLER, 0, 0, 27, 1, 0, 1174 &clk_doubler_lock); 1175 clk = tegra_clk_register_periph_gate("audio3_2x", "audio3_div", 1176 TEGRA_PERIPH_NO_RESET, clk_base, 1177 CLK_SET_RATE_PARENT, 116, &periph_v_regs, 1178 periph_clk_enb_refcnt); 1179 clk_register_clkdev(clk, "audio3_2x", NULL); 1180 clks[audio3_2x] = clk; 1181 1182 /* audio4_2x */ 1183 clk = clk_register_fixed_factor(NULL, "audio4_doubler", "audio4", 1184 CLK_SET_RATE_PARENT, 2, 1); 1185 clk = tegra_clk_register_divider("audio4_div", "audio4_doubler", 1186 clk_base + AUDIO_SYNC_DOUBLER, 0, 0, 28, 1, 0, 1187 &clk_doubler_lock); 1188 clk = tegra_clk_register_periph_gate("audio4_2x", "audio4_div", 1189 TEGRA_PERIPH_NO_RESET, clk_base, 1190 CLK_SET_RATE_PARENT, 117, &periph_v_regs, 1191 periph_clk_enb_refcnt); 1192 clk_register_clkdev(clk, "audio4_2x", NULL); 1193 clks[audio4_2x] = clk; 1194 1195 /* spdif_2x */ 1196 clk = clk_register_fixed_factor(NULL, "spdif_doubler", "spdif", 1197 CLK_SET_RATE_PARENT, 2, 1); 1198 clk = tegra_clk_register_divider("spdif_div", "spdif_doubler", 1199 clk_base + AUDIO_SYNC_DOUBLER, 0, 0, 29, 1, 0, 1200 &clk_doubler_lock); 1201 clk = tegra_clk_register_periph_gate("spdif_2x", "spdif_div", 1202 TEGRA_PERIPH_NO_RESET, clk_base, 1203 CLK_SET_RATE_PARENT, 118, &periph_v_regs, 1204 periph_clk_enb_refcnt); 1205 clk_register_clkdev(clk, "spdif_2x", NULL); 1206 clks[spdif_2x] = clk; 1207} 1208 1209static void __init tegra30_pmc_clk_init(void) 1210{ 1211 struct clk *clk; 1212 1213 /* clk_out_1 */ 1214 clk = clk_register_mux(NULL, "clk_out_1_mux", clk_out1_parents, 1215 ARRAY_SIZE(clk_out1_parents), 0, 1216 pmc_base + PMC_CLK_OUT_CNTRL, 6, 3, 0, 1217 &clk_out_lock); 1218 clks[clk_out_1_mux] = clk; 1219 clk = clk_register_gate(NULL, "clk_out_1", "clk_out_1_mux", 0, 1220 pmc_base + PMC_CLK_OUT_CNTRL, 2, 0, 1221 &clk_out_lock); 1222 clk_register_clkdev(clk, "extern1", "clk_out_1"); 1223 clks[clk_out_1] = clk; 1224 1225 /* clk_out_2 */ 1226 clk = clk_register_mux(NULL, "clk_out_2_mux", clk_out2_parents, 1227 ARRAY_SIZE(clk_out1_parents), 0, 1228 pmc_base + PMC_CLK_OUT_CNTRL, 14, 3, 0, 1229 &clk_out_lock); 1230 clk = clk_register_gate(NULL, "clk_out_2", "clk_out_2_mux", 0, 1231 pmc_base + PMC_CLK_OUT_CNTRL, 10, 0, 1232 &clk_out_lock); 1233 clk_register_clkdev(clk, "extern2", "clk_out_2"); 1234 clks[clk_out_2] = clk; 1235 1236 /* clk_out_3 */ 1237 clk = clk_register_mux(NULL, "clk_out_3_mux", clk_out3_parents, 1238 ARRAY_SIZE(clk_out1_parents), 0, 1239 pmc_base + PMC_CLK_OUT_CNTRL, 22, 3, 0, 1240 &clk_out_lock); 1241 clk = clk_register_gate(NULL, "clk_out_3", "clk_out_3_mux", 0, 1242 pmc_base + PMC_CLK_OUT_CNTRL, 18, 0, 1243 &clk_out_lock); 1244 clk_register_clkdev(clk, "extern3", "clk_out_3"); 1245 clks[clk_out_3] = clk; 1246 1247 /* blink */ 1248 writel_relaxed(0, pmc_base + PMC_BLINK_TIMER); 1249 clk = clk_register_gate(NULL, "blink_override", "clk_32k", 0, 1250 pmc_base + PMC_DPD_PADS_ORIDE, 1251 PMC_DPD_PADS_ORIDE_BLINK_ENB, 0, NULL); 1252 clk = clk_register_gate(NULL, "blink", "blink_override", 0, 1253 pmc_base + PMC_CTRL, 1254 PMC_CTRL_BLINK_ENB, 0, NULL); 1255 clk_register_clkdev(clk, "blink", NULL); 1256 clks[blink] = clk; 1257 1258} 1259 1260static const char *cclk_g_parents[] = { "clk_m", "pll_c", "clk_32k", "pll_m", 1261 "pll_p_cclkg", "pll_p_out4_cclkg", 1262 "pll_p_out3_cclkg", "unused", "pll_x" }; 1263static const char *cclk_lp_parents[] = { "clk_m", "pll_c", "clk_32k", "pll_m", 1264 "pll_p_cclklp", "pll_p_out4_cclklp", 1265 "pll_p_out3_cclklp", "unused", "pll_x", 1266 "pll_x_out0" }; 1267static const char *sclk_parents[] = { "clk_m", "pll_c_out1", "pll_p_out4", 1268 "pll_p_out3", "pll_p_out2", "unused", 1269 "clk_32k", "pll_m_out1" }; 1270 1271static void __init tegra30_super_clk_init(void) 1272{ 1273 struct clk *clk; 1274 1275 /* 1276 * Clock input to cclk_g divided from pll_p using 1277 * U71 divider of cclk_g. 1278 */ 1279 clk = tegra_clk_register_divider("pll_p_cclkg", "pll_p", 1280 clk_base + SUPER_CCLKG_DIVIDER, 0, 1281 TEGRA_DIVIDER_INT, 16, 8, 1, NULL); 1282 clk_register_clkdev(clk, "pll_p_cclkg", NULL); 1283 1284 /* 1285 * Clock input to cclk_g divided from pll_p_out3 using 1286 * U71 divider of cclk_g. 1287 */ 1288 clk = tegra_clk_register_divider("pll_p_out3_cclkg", "pll_p_out3", 1289 clk_base + SUPER_CCLKG_DIVIDER, 0, 1290 TEGRA_DIVIDER_INT, 16, 8, 1, NULL); 1291 clk_register_clkdev(clk, "pll_p_out3_cclkg", NULL); 1292 1293 /* 1294 * Clock input to cclk_g divided from pll_p_out4 using 1295 * U71 divider of cclk_g. 1296 */ 1297 clk = tegra_clk_register_divider("pll_p_out4_cclkg", "pll_p_out4", 1298 clk_base + SUPER_CCLKG_DIVIDER, 0, 1299 TEGRA_DIVIDER_INT, 16, 8, 1, NULL); 1300 clk_register_clkdev(clk, "pll_p_out4_cclkg", NULL); 1301 1302 /* CCLKG */ 1303 clk = tegra_clk_register_super_mux("cclk_g", cclk_g_parents, 1304 ARRAY_SIZE(cclk_g_parents), 1305 CLK_SET_RATE_PARENT, 1306 clk_base + CCLKG_BURST_POLICY, 1307 0, 4, 0, 0, NULL); 1308 clk_register_clkdev(clk, "cclk_g", NULL); 1309 clks[cclk_g] = clk; 1310 1311 /* 1312 * Clock input to cclk_lp divided from pll_p using 1313 * U71 divider of cclk_lp. 1314 */ 1315 clk = tegra_clk_register_divider("pll_p_cclklp", "pll_p", 1316 clk_base + SUPER_CCLKLP_DIVIDER, 0, 1317 TEGRA_DIVIDER_INT, 16, 8, 1, NULL); 1318 clk_register_clkdev(clk, "pll_p_cclklp", NULL); 1319 1320 /* 1321 * Clock input to cclk_lp divided from pll_p_out3 using 1322 * U71 divider of cclk_lp. 1323 */ 1324 clk = tegra_clk_register_divider("pll_p_out3_cclklp", "pll_p_out3", 1325 clk_base + SUPER_CCLKG_DIVIDER, 0, 1326 TEGRA_DIVIDER_INT, 16, 8, 1, NULL); 1327 clk_register_clkdev(clk, "pll_p_out3_cclklp", NULL); 1328 1329 /* 1330 * Clock input to cclk_lp divided from pll_p_out4 using 1331 * U71 divider of cclk_lp. 1332 */ 1333 clk = tegra_clk_register_divider("pll_p_out4_cclklp", "pll_p_out4", 1334 clk_base + SUPER_CCLKLP_DIVIDER, 0, 1335 TEGRA_DIVIDER_INT, 16, 8, 1, NULL); 1336 clk_register_clkdev(clk, "pll_p_out4_cclklp", NULL); 1337 1338 /* CCLKLP */ 1339 clk = tegra_clk_register_super_mux("cclk_lp", cclk_lp_parents, 1340 ARRAY_SIZE(cclk_lp_parents), 1341 CLK_SET_RATE_PARENT, 1342 clk_base + CCLKLP_BURST_POLICY, 1343 TEGRA_DIVIDER_2, 4, 8, 9, 1344 NULL); 1345 clk_register_clkdev(clk, "cclk_lp", NULL); 1346 clks[cclk_lp] = clk; 1347 1348 /* SCLK */ 1349 clk = tegra_clk_register_super_mux("sclk", sclk_parents, 1350 ARRAY_SIZE(sclk_parents), 1351 CLK_SET_RATE_PARENT, 1352 clk_base + SCLK_BURST_POLICY, 1353 0, 4, 0, 0, NULL); 1354 clk_register_clkdev(clk, "sclk", NULL); 1355 clks[sclk] = clk; 1356 1357 /* HCLK */ 1358 clk = clk_register_divider(NULL, "hclk_div", "sclk", 0, 1359 clk_base + SYSTEM_CLK_RATE, 4, 2, 0, 1360 &sysrate_lock); 1361 clk = clk_register_gate(NULL, "hclk", "hclk_div", CLK_SET_RATE_PARENT, 1362 clk_base + SYSTEM_CLK_RATE, 7, 1363 CLK_GATE_SET_TO_DISABLE, &sysrate_lock); 1364 clk_register_clkdev(clk, "hclk", NULL); 1365 clks[hclk] = clk; 1366 1367 /* PCLK */ 1368 clk = clk_register_divider(NULL, "pclk_div", "hclk", 0, 1369 clk_base + SYSTEM_CLK_RATE, 0, 2, 0, 1370 &sysrate_lock); 1371 clk = clk_register_gate(NULL, "pclk", "pclk_div", CLK_SET_RATE_PARENT, 1372 clk_base + SYSTEM_CLK_RATE, 3, 1373 CLK_GATE_SET_TO_DISABLE, &sysrate_lock); 1374 clk_register_clkdev(clk, "pclk", NULL); 1375 clks[pclk] = clk; 1376 1377 /* twd */ 1378 clk = clk_register_fixed_factor(NULL, "twd", "cclk_g", 1379 CLK_SET_RATE_PARENT, 1, 2); 1380 clk_register_clkdev(clk, "twd", NULL); 1381 clks[twd] = clk; 1382} 1383 1384static const char *mux_pllacp_clkm[] = { "pll_a_out0", "unused", "pll_p", 1385 "clk_m" }; 1386static const char *mux_pllpcm_clkm[] = { "pll_p", "pll_c", "pll_m", "clk_m" }; 1387static const char *mux_pllmcp_clkm[] = { "pll_m", "pll_c", "pll_p", "clk_m" }; 1388static const char *i2s0_parents[] = { "pll_a_out0", "audio0_2x", "pll_p", 1389 "clk_m" }; 1390static const char *i2s1_parents[] = { "pll_a_out0", "audio1_2x", "pll_p", 1391 "clk_m" }; 1392static const char *i2s2_parents[] = { "pll_a_out0", "audio2_2x", "pll_p", 1393 "clk_m" }; 1394static const char *i2s3_parents[] = { "pll_a_out0", "audio3_2x", "pll_p", 1395 "clk_m" }; 1396static const char *i2s4_parents[] = { "pll_a_out0", "audio4_2x", "pll_p", 1397 "clk_m" }; 1398static const char *spdif_out_parents[] = { "pll_a_out0", "spdif_2x", "pll_p", 1399 "clk_m" }; 1400static const char *spdif_in_parents[] = { "pll_p", "pll_c", "pll_m" }; 1401static const char *mux_pllpc_clk32k_clkm[] = { "pll_p", "pll_c", "clk_32k", 1402 "clk_m" }; 1403static const char *mux_pllpc_clkm_clk32k[] = { "pll_p", "pll_c", "clk_m", 1404 "clk_32k" }; 1405static const char *mux_pllmcpa[] = { "pll_m", "pll_c", "pll_p", "pll_a_out0" }; 1406static const char *mux_pllpdc_clkm[] = { "pll_p", "pll_d_out0", "pll_c", 1407 "clk_m" }; 1408static const char *mux_pllp_clkm[] = { "pll_p", "unused", "unused", "clk_m" }; 1409static const char *mux_pllpmdacd2_clkm[] = { "pll_p", "pll_m", "pll_d_out0", 1410 "pll_a_out0", "pll_c", 1411 "pll_d2_out0", "clk_m" }; 1412static const char *mux_plla_clk32k_pllp_clkm_plle[] = { "pll_a_out0", 1413 "clk_32k", "pll_p", 1414 "clk_m", "pll_e" }; 1415static const char *mux_plld_out0_plld2_out0[] = { "pll_d_out0", 1416 "pll_d2_out0" }; 1417 1418static struct tegra_periph_init_data tegra_periph_clk_list[] = { 1419 TEGRA_INIT_DATA_MUX("i2s0", NULL, "tegra30-i2s.0", i2s0_parents, CLK_SOURCE_I2S0, 30, &periph_l_regs, TEGRA_PERIPH_ON_APB, i2s0), 1420 TEGRA_INIT_DATA_MUX("i2s1", NULL, "tegra30-i2s.1", i2s1_parents, CLK_SOURCE_I2S1, 11, &periph_l_regs, TEGRA_PERIPH_ON_APB, i2s1), 1421 TEGRA_INIT_DATA_MUX("i2s2", NULL, "tegra30-i2s.2", i2s2_parents, CLK_SOURCE_I2S2, 18, &periph_l_regs, TEGRA_PERIPH_ON_APB, i2s2), 1422 TEGRA_INIT_DATA_MUX("i2s3", NULL, "tegra30-i2s.3", i2s3_parents, CLK_SOURCE_I2S3, 101, &periph_v_regs, TEGRA_PERIPH_ON_APB, i2s3), 1423 TEGRA_INIT_DATA_MUX("i2s4", NULL, "tegra30-i2s.4", i2s4_parents, CLK_SOURCE_I2S4, 102, &periph_v_regs, TEGRA_PERIPH_ON_APB, i2s4), 1424 TEGRA_INIT_DATA_MUX("spdif_out", "spdif_out", "tegra30-spdif", spdif_out_parents, CLK_SOURCE_SPDIF_OUT, 10, &periph_l_regs, TEGRA_PERIPH_ON_APB, spdif_out), 1425 TEGRA_INIT_DATA_MUX("spdif_in", "spdif_in", "tegra30-spdif", spdif_in_parents, CLK_SOURCE_SPDIF_IN, 10, &periph_l_regs, TEGRA_PERIPH_ON_APB, spdif_in), 1426 TEGRA_INIT_DATA_MUX("d_audio", "d_audio", "tegra30-ahub", mux_pllacp_clkm, CLK_SOURCE_D_AUDIO, 106, &periph_v_regs, 0, d_audio), 1427 TEGRA_INIT_DATA_MUX("dam0", NULL, "tegra30-dam.0", mux_pllacp_clkm, CLK_SOURCE_DAM0, 108, &periph_v_regs, 0, dam0), 1428 TEGRA_INIT_DATA_MUX("dam1", NULL, "tegra30-dam.1", mux_pllacp_clkm, CLK_SOURCE_DAM1, 109, &periph_v_regs, 0, dam1), 1429 TEGRA_INIT_DATA_MUX("dam2", NULL, "tegra30-dam.2", mux_pllacp_clkm, CLK_SOURCE_DAM2, 110, &periph_v_regs, 0, dam2), 1430 TEGRA_INIT_DATA_MUX("hda", "hda", "tegra30-hda", mux_pllpcm_clkm, CLK_SOURCE_HDA, 125, &periph_v_regs, 0, hda), 1431 TEGRA_INIT_DATA_MUX("hda2codec_2x", "hda2codec", "tegra30-hda", mux_pllpcm_clkm, CLK_SOURCE_HDA2CODEC_2X, 111, &periph_v_regs, 0, hda2codec_2x), 1432 TEGRA_INIT_DATA_MUX("sbc1", NULL, "spi_tegra.0", mux_pllpcm_clkm, CLK_SOURCE_SBC1, 41, &periph_h_regs, TEGRA_PERIPH_ON_APB, sbc1), 1433 TEGRA_INIT_DATA_MUX("sbc2", NULL, "spi_tegra.1", mux_pllpcm_clkm, CLK_SOURCE_SBC2, 44, &periph_h_regs, TEGRA_PERIPH_ON_APB, sbc2), 1434 TEGRA_INIT_DATA_MUX("sbc3", NULL, "spi_tegra.2", mux_pllpcm_clkm, CLK_SOURCE_SBC3, 46, &periph_h_regs, TEGRA_PERIPH_ON_APB, sbc3), 1435 TEGRA_INIT_DATA_MUX("sbc4", NULL, "spi_tegra.3", mux_pllpcm_clkm, CLK_SOURCE_SBC4, 68, &periph_u_regs, TEGRA_PERIPH_ON_APB, sbc4), 1436 TEGRA_INIT_DATA_MUX("sbc5", NULL, "spi_tegra.4", mux_pllpcm_clkm, CLK_SOURCE_SBC5, 104, &periph_v_regs, TEGRA_PERIPH_ON_APB, sbc5), 1437 TEGRA_INIT_DATA_MUX("sbc6", NULL, "spi_tegra.5", mux_pllpcm_clkm, CLK_SOURCE_SBC6, 105, &periph_v_regs, TEGRA_PERIPH_ON_APB, sbc6), 1438 TEGRA_INIT_DATA_MUX("sata_oob", NULL, "tegra_sata_oob", mux_pllpcm_clkm, CLK_SOURCE_SATA_OOB, 123, &periph_v_regs, TEGRA_PERIPH_ON_APB, sata_oob), 1439 TEGRA_INIT_DATA_MUX("sata", NULL, "tegra_sata", mux_pllpcm_clkm, CLK_SOURCE_SATA, 124, &periph_v_regs, TEGRA_PERIPH_ON_APB, sata), 1440 TEGRA_INIT_DATA_MUX("ndflash", NULL, "tegra_nand", mux_pllpcm_clkm, CLK_SOURCE_NDFLASH, 13, &periph_l_regs, TEGRA_PERIPH_ON_APB, ndflash), 1441 TEGRA_INIT_DATA_MUX("ndspeed", NULL, "tegra_nand_speed", mux_pllpcm_clkm, CLK_SOURCE_NDSPEED, 80, &periph_u_regs, TEGRA_PERIPH_ON_APB, ndspeed), 1442 TEGRA_INIT_DATA_MUX("vfir", NULL, "vfir", mux_pllpcm_clkm, CLK_SOURCE_VFIR, 7, &periph_l_regs, TEGRA_PERIPH_ON_APB, vfir), 1443 TEGRA_INIT_DATA_MUX("csite", NULL, "csite", mux_pllpcm_clkm, CLK_SOURCE_CSITE, 73, &periph_u_regs, TEGRA_PERIPH_ON_APB, csite), 1444 TEGRA_INIT_DATA_MUX("la", NULL, "la", mux_pllpcm_clkm, CLK_SOURCE_LA, 76, &periph_u_regs, TEGRA_PERIPH_ON_APB, la), 1445 TEGRA_INIT_DATA_MUX("owr", NULL, "tegra_w1", mux_pllpcm_clkm, CLK_SOURCE_OWR, 71, &periph_u_regs, TEGRA_PERIPH_ON_APB, owr), 1446 TEGRA_INIT_DATA_MUX("mipi", NULL, "mipi", mux_pllpcm_clkm, CLK_SOURCE_MIPI, 50, &periph_h_regs, TEGRA_PERIPH_ON_APB, mipi), 1447 TEGRA_INIT_DATA_MUX("tsensor", NULL, "tegra-tsensor", mux_pllpc_clkm_clk32k, CLK_SOURCE_TSENSOR, 100, &periph_v_regs, TEGRA_PERIPH_ON_APB, tsensor), 1448 TEGRA_INIT_DATA_MUX("i2cslow", NULL, "i2cslow", mux_pllpc_clk32k_clkm, CLK_SOURCE_I2CSLOW, 81, &periph_u_regs, TEGRA_PERIPH_ON_APB, i2cslow), 1449 TEGRA_INIT_DATA_INT("vde", NULL, "vde", mux_pllpcm_clkm, CLK_SOURCE_VDE, 61, &periph_h_regs, 0, vde), 1450 TEGRA_INIT_DATA_INT("vi", "vi", "tegra_camera", mux_pllmcpa, CLK_SOURCE_VI, 20, &periph_l_regs, 0, vi), 1451 TEGRA_INIT_DATA_INT("epp", NULL, "epp", mux_pllmcpa, CLK_SOURCE_EPP, 19, &periph_l_regs, 0, epp), 1452 TEGRA_INIT_DATA_INT("mpe", NULL, "mpe", mux_pllmcpa, CLK_SOURCE_MPE, 60, &periph_h_regs, 0, mpe), 1453 TEGRA_INIT_DATA_INT("host1x", NULL, "host1x", mux_pllmcpa, CLK_SOURCE_HOST1X, 28, &periph_l_regs, 0, host1x), 1454 TEGRA_INIT_DATA_INT("3d", NULL, "3d", mux_pllmcpa, CLK_SOURCE_3D, 24, &periph_l_regs, TEGRA_PERIPH_MANUAL_RESET, gr3d), 1455 TEGRA_INIT_DATA_INT("3d2", NULL, "3d2", mux_pllmcpa, CLK_SOURCE_3D2, 98, &periph_v_regs, TEGRA_PERIPH_MANUAL_RESET, gr3d2), 1456 TEGRA_INIT_DATA_INT("2d", NULL, "2d", mux_pllmcpa, CLK_SOURCE_2D, 21, &periph_l_regs, 0, gr2d), 1457 TEGRA_INIT_DATA_INT("se", NULL, "se", mux_pllpcm_clkm, CLK_SOURCE_SE, 127, &periph_v_regs, 0, se), 1458 TEGRA_INIT_DATA_MUX("mselect", NULL, "mselect", mux_pllp_clkm, CLK_SOURCE_MSELECT, 99, &periph_v_regs, 0, mselect), 1459 TEGRA_INIT_DATA_MUX("nor", NULL, "tegra-nor", mux_pllpcm_clkm, CLK_SOURCE_NOR, 42, &periph_h_regs, 0, nor), 1460 TEGRA_INIT_DATA_MUX("sdmmc1", NULL, "sdhci-tegra.0", mux_pllpcm_clkm, CLK_SOURCE_SDMMC1, 14, &periph_l_regs, 0, sdmmc1), 1461 TEGRA_INIT_DATA_MUX("sdmmc2", NULL, "sdhci-tegra.1", mux_pllpcm_clkm, CLK_SOURCE_SDMMC2, 9, &periph_l_regs, 0, sdmmc2), 1462 TEGRA_INIT_DATA_MUX("sdmmc3", NULL, "sdhci-tegra.2", mux_pllpcm_clkm, CLK_SOURCE_SDMMC3, 69, &periph_u_regs, 0, sdmmc3), 1463 TEGRA_INIT_DATA_MUX("sdmmc4", NULL, "sdhci-tegra.3", mux_pllpcm_clkm, CLK_SOURCE_SDMMC4, 15, &periph_l_regs, 0, sdmmc4), 1464 TEGRA_INIT_DATA_MUX("cve", NULL, "cve", mux_pllpdc_clkm, CLK_SOURCE_CVE, 49, &periph_h_regs, 0, cve), 1465 TEGRA_INIT_DATA_MUX("tvo", NULL, "tvo", mux_pllpdc_clkm, CLK_SOURCE_TVO, 49, &periph_h_regs, 0, tvo), 1466 TEGRA_INIT_DATA_MUX("tvdac", NULL, "tvdac", mux_pllpdc_clkm, CLK_SOURCE_TVDAC, 53, &periph_h_regs, 0, tvdac), 1467 TEGRA_INIT_DATA_MUX("actmon", NULL, "actmon", mux_pllpc_clk32k_clkm, CLK_SOURCE_ACTMON, 119, &periph_v_regs, 0, actmon), 1468 TEGRA_INIT_DATA_MUX("vi_sensor", "vi_sensor", "tegra_camera", mux_pllmcpa, CLK_SOURCE_VI_SENSOR, 20, &periph_l_regs, TEGRA_PERIPH_NO_RESET, vi_sensor), 1469 TEGRA_INIT_DATA_DIV16("i2c1", "div-clk", "tegra-i2c.0", mux_pllp_clkm, CLK_SOURCE_I2C1, 12, &periph_l_regs, TEGRA_PERIPH_ON_APB, i2c1), 1470 TEGRA_INIT_DATA_DIV16("i2c2", "div-clk", "tegra-i2c.1", mux_pllp_clkm, CLK_SOURCE_I2C2, 54, &periph_h_regs, TEGRA_PERIPH_ON_APB, i2c2), 1471 TEGRA_INIT_DATA_DIV16("i2c3", "div-clk", "tegra-i2c.2", mux_pllp_clkm, CLK_SOURCE_I2C3, 67, &periph_u_regs, TEGRA_PERIPH_ON_APB, i2c3), 1472 TEGRA_INIT_DATA_DIV16("i2c4", "div-clk", "tegra-i2c.3", mux_pllp_clkm, CLK_SOURCE_I2C4, 103, &periph_v_regs, TEGRA_PERIPH_ON_APB, i2c4), 1473 TEGRA_INIT_DATA_DIV16("i2c5", "div-clk", "tegra-i2c.4", mux_pllp_clkm, CLK_SOURCE_I2C5, 47, &periph_h_regs, TEGRA_PERIPH_ON_APB, i2c5), 1474 TEGRA_INIT_DATA_UART("uarta", NULL, "tegra_uart.0", mux_pllpcm_clkm, CLK_SOURCE_UARTA, 6, &periph_l_regs, uarta), 1475 TEGRA_INIT_DATA_UART("uartb", NULL, "tegra_uart.1", mux_pllpcm_clkm, CLK_SOURCE_UARTB, 7, &periph_l_regs, uartb), 1476 TEGRA_INIT_DATA_UART("uartc", NULL, "tegra_uart.2", mux_pllpcm_clkm, CLK_SOURCE_UARTC, 55, &periph_h_regs, uartc), 1477 TEGRA_INIT_DATA_UART("uartd", NULL, "tegra_uart.3", mux_pllpcm_clkm, CLK_SOURCE_UARTD, 65, &periph_u_regs, uartd), 1478 TEGRA_INIT_DATA_UART("uarte", NULL, "tegra_uart.4", mux_pllpcm_clkm, CLK_SOURCE_UARTE, 66, &periph_u_regs, uarte), 1479 TEGRA_INIT_DATA_MUX8("hdmi", NULL, "hdmi", mux_pllpmdacd2_clkm, CLK_SOURCE_HDMI, 51, &periph_h_regs, 0, hdmi), 1480 TEGRA_INIT_DATA_MUX8("extern1", NULL, "extern1", mux_plla_clk32k_pllp_clkm_plle, CLK_SOURCE_EXTERN1, 120, &periph_v_regs, 0, extern1), 1481 TEGRA_INIT_DATA_MUX8("extern2", NULL, "extern2", mux_plla_clk32k_pllp_clkm_plle, CLK_SOURCE_EXTERN2, 121, &periph_v_regs, 0, extern2), 1482 TEGRA_INIT_DATA_MUX8("extern3", NULL, "extern3", mux_plla_clk32k_pllp_clkm_plle, CLK_SOURCE_EXTERN3, 122, &periph_v_regs, 0, extern3), 1483 TEGRA_INIT_DATA("pwm", NULL, "pwm", mux_pllpc_clk32k_clkm, CLK_SOURCE_PWM, 28, 2, 0, 0, 8, 1, 0, &periph_l_regs, 17, periph_clk_enb_refcnt, 0, pwm), 1484}; 1485 1486static struct tegra_periph_init_data tegra_periph_nodiv_clk_list[] = { 1487 TEGRA_INIT_DATA_NODIV("disp1", NULL, "tegradc.0", mux_pllpmdacd2_clkm, CLK_SOURCE_DISP1, 29, 3, 27, &periph_l_regs, 0, disp1), 1488 TEGRA_INIT_DATA_NODIV("disp2", NULL, "tegradc.1", mux_pllpmdacd2_clkm, CLK_SOURCE_DISP2, 29, 3, 26, &periph_l_regs, 0, disp2), 1489 TEGRA_INIT_DATA_NODIV("dsib", NULL, "tegradc.1", mux_plld_out0_plld2_out0, CLK_SOURCE_DSIB, 25, 1, 82, &periph_u_regs, 0, dsib), 1490}; 1491 1492static void __init tegra30_periph_clk_init(void) 1493{ 1494 struct tegra_periph_init_data *data; 1495 struct clk *clk; 1496 int i; 1497 1498 /* apbdma */ 1499 clk = tegra_clk_register_periph_gate("apbdma", "clk_m", 0, clk_base, 0, 34, 1500 &periph_h_regs, periph_clk_enb_refcnt); 1501 clk_register_clkdev(clk, NULL, "tegra-apbdma"); 1502 clks[apbdma] = clk; 1503 1504 /* rtc */ 1505 clk = tegra_clk_register_periph_gate("rtc", "clk_32k", 1506 TEGRA_PERIPH_NO_RESET | TEGRA_PERIPH_ON_APB, 1507 clk_base, 0, 4, &periph_l_regs, 1508 periph_clk_enb_refcnt); 1509 clk_register_clkdev(clk, NULL, "rtc-tegra"); 1510 clks[rtc] = clk; 1511 1512 /* timer */ 1513 clk = tegra_clk_register_periph_gate("timer", "clk_m", 0, clk_base, 0, 1514 5, &periph_l_regs, periph_clk_enb_refcnt); 1515 clk_register_clkdev(clk, NULL, "timer"); 1516 clks[timer] = clk; 1517 1518 /* kbc */ 1519 clk = tegra_clk_register_periph_gate("kbc", "clk_32k", 1520 TEGRA_PERIPH_NO_RESET | TEGRA_PERIPH_ON_APB, 1521 clk_base, 0, 36, &periph_h_regs, 1522 periph_clk_enb_refcnt); 1523 clk_register_clkdev(clk, NULL, "tegra-kbc"); 1524 clks[kbc] = clk; 1525 1526 /* csus */ 1527 clk = tegra_clk_register_periph_gate("csus", "clk_m", 1528 TEGRA_PERIPH_NO_RESET | TEGRA_PERIPH_ON_APB, 1529 clk_base, 0, 92, &periph_u_regs, 1530 periph_clk_enb_refcnt); 1531 clk_register_clkdev(clk, "csus", "tengra_camera"); 1532 clks[csus] = clk; 1533 1534 /* vcp */ 1535 clk = tegra_clk_register_periph_gate("vcp", "clk_m", 0, clk_base, 0, 29, 1536 &periph_l_regs, periph_clk_enb_refcnt); 1537 clk_register_clkdev(clk, "vcp", "tegra-avp"); 1538 clks[vcp] = clk; 1539 1540 /* bsea */ 1541 clk = tegra_clk_register_periph_gate("bsea", "clk_m", 0, clk_base, 0, 1542 62, &periph_h_regs, periph_clk_enb_refcnt); 1543 clk_register_clkdev(clk, "bsea", "tegra-avp"); 1544 clks[bsea] = clk; 1545 1546 /* bsev */ 1547 clk = tegra_clk_register_periph_gate("bsev", "clk_m", 0, clk_base, 0, 1548 63, &periph_h_regs, periph_clk_enb_refcnt); 1549 clk_register_clkdev(clk, "bsev", "tegra-aes"); 1550 clks[bsev] = clk; 1551 1552 /* usbd */ 1553 clk = tegra_clk_register_periph_gate("usbd", "clk_m", 0, clk_base, 0, 1554 22, &periph_l_regs, periph_clk_enb_refcnt); 1555 clk_register_clkdev(clk, NULL, "fsl-tegra-udc"); 1556 clks[usbd] = clk; 1557 1558 /* usb2 */ 1559 clk = tegra_clk_register_periph_gate("usb2", "clk_m", 0, clk_base, 0, 1560 58, &periph_h_regs, periph_clk_enb_refcnt); 1561 clk_register_clkdev(clk, NULL, "tegra-ehci.1"); 1562 clks[usb2] = clk; 1563 1564 /* usb3 */ 1565 clk = tegra_clk_register_periph_gate("usb3", "clk_m", 0, clk_base, 0, 1566 59, &periph_h_regs, periph_clk_enb_refcnt); 1567 clk_register_clkdev(clk, NULL, "tegra-ehci.2"); 1568 clks[usb3] = clk; 1569 1570 /* dsia */ 1571 clk = tegra_clk_register_periph_gate("dsia", "pll_d_out0", 0, clk_base, 1572 0, 48, &periph_h_regs, 1573 periph_clk_enb_refcnt); 1574 clk_register_clkdev(clk, "dsia", "tegradc.0"); 1575 clks[dsia] = clk; 1576 1577 /* csi */ 1578 clk = tegra_clk_register_periph_gate("csi", "pll_p_out3", 0, clk_base, 1579 0, 52, &periph_h_regs, 1580 periph_clk_enb_refcnt); 1581 clk_register_clkdev(clk, "csi", "tegra_camera"); 1582 clks[csi] = clk; 1583 1584 /* isp */ 1585 clk = tegra_clk_register_periph_gate("isp", "clk_m", 0, clk_base, 0, 23, 1586 &periph_l_regs, periph_clk_enb_refcnt); 1587 clk_register_clkdev(clk, "isp", "tegra_camera"); 1588 clks[isp] = clk; 1589 1590 /* pcie */ 1591 clk = tegra_clk_register_periph_gate("pcie", "clk_m", 0, clk_base, 0, 1592 70, &periph_u_regs, periph_clk_enb_refcnt); 1593 clk_register_clkdev(clk, "pcie", "tegra-pcie"); 1594 clks[pcie] = clk; 1595 1596 /* afi */ 1597 clk = tegra_clk_register_periph_gate("afi", "clk_m", 0, clk_base, 0, 72, 1598 &periph_u_regs, periph_clk_enb_refcnt); 1599 clk_register_clkdev(clk, "afi", "tegra-pcie"); 1600 clks[afi] = clk; 1601 1602 /* kfuse */ 1603 clk = tegra_clk_register_periph_gate("kfuse", "clk_m", 1604 TEGRA_PERIPH_ON_APB, 1605 clk_base, 0, 40, &periph_h_regs, 1606 periph_clk_enb_refcnt); 1607 clk_register_clkdev(clk, NULL, "kfuse-tegra"); 1608 clks[kfuse] = clk; 1609 1610 /* fuse */ 1611 clk = tegra_clk_register_periph_gate("fuse", "clk_m", 1612 TEGRA_PERIPH_ON_APB, 1613 clk_base, 0, 39, &periph_h_regs, 1614 periph_clk_enb_refcnt); 1615 clk_register_clkdev(clk, "fuse", "fuse-tegra"); 1616 clks[fuse] = clk; 1617 1618 /* fuse_burn */ 1619 clk = tegra_clk_register_periph_gate("fuse_burn", "clk_m", 1620 TEGRA_PERIPH_ON_APB, 1621 clk_base, 0, 39, &periph_h_regs, 1622 periph_clk_enb_refcnt); 1623 clk_register_clkdev(clk, "fuse_burn", "fuse-tegra"); 1624 clks[fuse_burn] = clk; 1625 1626 /* apbif */ 1627 clk = tegra_clk_register_periph_gate("apbif", "clk_m", 0, 1628 clk_base, 0, 107, &periph_v_regs, 1629 periph_clk_enb_refcnt); 1630 clk_register_clkdev(clk, "apbif", "tegra30-ahub"); 1631 clks[apbif] = clk; 1632 1633 /* hda2hdmi */ 1634 clk = tegra_clk_register_periph_gate("hda2hdmi", "clk_m", 1635 TEGRA_PERIPH_ON_APB, 1636 clk_base, 0, 128, &periph_w_regs, 1637 periph_clk_enb_refcnt); 1638 clk_register_clkdev(clk, "hda2hdmi", "tegra30-hda"); 1639 clks[hda2hdmi] = clk; 1640 1641 /* sata_cold */ 1642 clk = tegra_clk_register_periph_gate("sata_cold", "clk_m", 1643 TEGRA_PERIPH_ON_APB, 1644 clk_base, 0, 129, &periph_w_regs, 1645 periph_clk_enb_refcnt); 1646 clk_register_clkdev(clk, NULL, "tegra_sata_cold"); 1647 clks[sata_cold] = clk; 1648 1649 /* dtv */ 1650 clk = tegra_clk_register_periph_gate("dtv", "clk_m", 1651 TEGRA_PERIPH_ON_APB, 1652 clk_base, 0, 79, &periph_u_regs, 1653 periph_clk_enb_refcnt); 1654 clk_register_clkdev(clk, NULL, "dtv"); 1655 clks[dtv] = clk; 1656 1657 /* emc */ 1658 clk = clk_register_mux(NULL, "emc_mux", mux_pllmcp_clkm, 1659 ARRAY_SIZE(mux_pllmcp_clkm), 0, 1660 clk_base + CLK_SOURCE_EMC, 1661 30, 2, 0, NULL); 1662 clk = tegra_clk_register_periph_gate("emc", "emc_mux", 0, clk_base, 0, 1663 57, &periph_h_regs, periph_clk_enb_refcnt); 1664 clk_register_clkdev(clk, "emc", NULL); 1665 clks[emc] = clk; 1666 1667 for (i = 0; i < ARRAY_SIZE(tegra_periph_clk_list); i++) { 1668 data = &tegra_periph_clk_list[i]; 1669 clk = tegra_clk_register_periph(data->name, data->parent_names, 1670 data->num_parents, &data->periph, 1671 clk_base, data->offset); 1672 clk_register_clkdev(clk, data->con_id, data->dev_id); 1673 clks[data->clk_id] = clk; 1674 } 1675 1676 for (i = 0; i < ARRAY_SIZE(tegra_periph_nodiv_clk_list); i++) { 1677 data = &tegra_periph_nodiv_clk_list[i]; 1678 clk = tegra_clk_register_periph_nodiv(data->name, 1679 data->parent_names, 1680 data->num_parents, &data->periph, 1681 clk_base, data->offset); 1682 clk_register_clkdev(clk, data->con_id, data->dev_id); 1683 clks[data->clk_id] = clk; 1684 } 1685} 1686 1687static void __init tegra30_fixed_clk_init(void) 1688{ 1689 struct clk *clk; 1690 1691 /* clk_32k */ 1692 clk = clk_register_fixed_rate(NULL, "clk_32k", NULL, CLK_IS_ROOT, 1693 32768); 1694 clk_register_clkdev(clk, "clk_32k", NULL); 1695 clks[clk_32k] = clk; 1696 1697 /* clk_m_div2 */ 1698 clk = clk_register_fixed_factor(NULL, "clk_m_div2", "clk_m", 1699 CLK_SET_RATE_PARENT, 1, 2); 1700 clk_register_clkdev(clk, "clk_m_div2", NULL); 1701 clks[clk_m_div2] = clk; 1702 1703 /* clk_m_div4 */ 1704 clk = clk_register_fixed_factor(NULL, "clk_m_div4", "clk_m", 1705 CLK_SET_RATE_PARENT, 1, 4); 1706 clk_register_clkdev(clk, "clk_m_div4", NULL); 1707 clks[clk_m_div4] = clk; 1708 1709 /* cml0 */ 1710 clk = clk_register_gate(NULL, "cml0", "pll_e", 0, clk_base + PLLE_AUX, 1711 0, 0, &cml_lock); 1712 clk_register_clkdev(clk, "cml0", NULL); 1713 clks[cml0] = clk; 1714 1715 /* cml1 */ 1716 clk = clk_register_gate(NULL, "cml1", "pll_e", 0, clk_base + PLLE_AUX, 1717 1, 0, &cml_lock); 1718 clk_register_clkdev(clk, "cml1", NULL); 1719 clks[cml1] = clk; 1720 1721 /* pciex */ 1722 clk = clk_register_fixed_rate(NULL, "pciex", "pll_e", 0, 100000000); 1723 clk_register_clkdev(clk, "pciex", NULL); 1724 clks[pciex] = clk; 1725} 1726 1727static void __init tegra30_osc_clk_init(void) 1728{ 1729 struct clk *clk; 1730 unsigned int pll_ref_div; 1731 1732 tegra30_clk_measure_input_freq(); 1733 1734 /* clk_m */ 1735 clk = clk_register_fixed_rate(NULL, "clk_m", NULL, CLK_IS_ROOT, 1736 input_freq); 1737 clk_register_clkdev(clk, "clk_m", NULL); 1738 clks[clk_m] = clk; 1739 1740 /* pll_ref */ 1741 pll_ref_div = tegra30_get_pll_ref_div(); 1742 clk = clk_register_fixed_factor(NULL, "pll_ref", "clk_m", 1743 CLK_SET_RATE_PARENT, 1, pll_ref_div); 1744 clk_register_clkdev(clk, "pll_ref", NULL); 1745 clks[pll_ref] = clk; 1746} 1747 1748/* Tegra30 CPU clock and reset control functions */ 1749static void tegra30_wait_cpu_in_reset(u32 cpu) 1750{ 1751 unsigned int reg; 1752 1753 do { 1754 reg = readl(clk_base + 1755 TEGRA30_CLK_RST_CONTROLLER_CPU_CMPLX_STATUS); 1756 cpu_relax(); 1757 } while (!(reg & (1 << cpu))); /* check CPU been reset or not */ 1758 1759 return; 1760} 1761 1762static void tegra30_put_cpu_in_reset(u32 cpu) 1763{ 1764 writel(CPU_RESET(cpu), 1765 clk_base + TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET); 1766 dmb(); 1767} 1768 1769static void tegra30_cpu_out_of_reset(u32 cpu) 1770{ 1771 writel(CPU_RESET(cpu), 1772 clk_base + TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR); 1773 wmb(); 1774} 1775 1776 1777static void tegra30_enable_cpu_clock(u32 cpu) 1778{ 1779 unsigned int reg; 1780 1781 writel(CPU_CLOCK(cpu), 1782 clk_base + TEGRA30_CLK_RST_CONTROLLER_CLK_CPU_CMPLX_CLR); 1783 reg = readl(clk_base + 1784 TEGRA30_CLK_RST_CONTROLLER_CLK_CPU_CMPLX_CLR); 1785} 1786 1787static void tegra30_disable_cpu_clock(u32 cpu) 1788{ 1789 1790 unsigned int reg; 1791 1792 reg = readl(clk_base + TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX); 1793 writel(reg | CPU_CLOCK(cpu), 1794 clk_base + TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX); 1795} 1796 1797#ifdef CONFIG_PM_SLEEP 1798static bool tegra30_cpu_rail_off_ready(void) 1799{ 1800 unsigned int cpu_rst_status; 1801 int cpu_pwr_status; 1802 1803 cpu_rst_status = readl(clk_base + 1804 TEGRA30_CLK_RST_CONTROLLER_CPU_CMPLX_STATUS); 1805 cpu_pwr_status = tegra_powergate_is_powered(TEGRA_POWERGATE_CPU1) || 1806 tegra_powergate_is_powered(TEGRA_POWERGATE_CPU2) || 1807 tegra_powergate_is_powered(TEGRA_POWERGATE_CPU3); 1808 1809 if (((cpu_rst_status & 0xE) != 0xE) || cpu_pwr_status) 1810 return false; 1811 1812 return true; 1813} 1814 1815static void tegra30_cpu_clock_suspend(void) 1816{ 1817 /* switch coresite to clk_m, save off original source */ 1818 tegra30_cpu_clk_sctx.clk_csite_src = 1819 readl(clk_base + CLK_RESET_SOURCE_CSITE); 1820 writel(3<<30, clk_base + CLK_RESET_SOURCE_CSITE); 1821 1822 tegra30_cpu_clk_sctx.cpu_burst = 1823 readl(clk_base + CLK_RESET_CCLK_BURST); 1824 tegra30_cpu_clk_sctx.pllx_base = 1825 readl(clk_base + CLK_RESET_PLLX_BASE); 1826 tegra30_cpu_clk_sctx.pllx_misc = 1827 readl(clk_base + CLK_RESET_PLLX_MISC); 1828 tegra30_cpu_clk_sctx.cclk_divider = 1829 readl(clk_base + CLK_RESET_CCLK_DIVIDER); 1830} 1831 1832static void tegra30_cpu_clock_resume(void) 1833{ 1834 unsigned int reg, policy; 1835 1836 /* Is CPU complex already running on PLLX? */ 1837 reg = readl(clk_base + CLK_RESET_CCLK_BURST); 1838 policy = (reg >> CLK_RESET_CCLK_BURST_POLICY_SHIFT) & 0xF; 1839 1840 if (policy == CLK_RESET_CCLK_IDLE_POLICY) 1841 reg = (reg >> CLK_RESET_CCLK_IDLE_POLICY_SHIFT) & 0xF; 1842 else if (policy == CLK_RESET_CCLK_RUN_POLICY) 1843 reg = (reg >> CLK_RESET_CCLK_RUN_POLICY_SHIFT) & 0xF; 1844 else 1845 BUG(); 1846 1847 if (reg != CLK_RESET_CCLK_BURST_POLICY_PLLX) { 1848 /* restore PLLX settings if CPU is on different PLL */ 1849 writel(tegra30_cpu_clk_sctx.pllx_misc, 1850 clk_base + CLK_RESET_PLLX_MISC); 1851 writel(tegra30_cpu_clk_sctx.pllx_base, 1852 clk_base + CLK_RESET_PLLX_BASE); 1853 1854 /* wait for PLL stabilization if PLLX was enabled */ 1855 if (tegra30_cpu_clk_sctx.pllx_base & (1 << 30)) 1856 udelay(300); 1857 } 1858 1859 /* 1860 * Restore original burst policy setting for calls resulting from CPU 1861 * LP2 in idle or system suspend. 1862 */ 1863 writel(tegra30_cpu_clk_sctx.cclk_divider, 1864 clk_base + CLK_RESET_CCLK_DIVIDER); 1865 writel(tegra30_cpu_clk_sctx.cpu_burst, 1866 clk_base + CLK_RESET_CCLK_BURST); 1867 1868 writel(tegra30_cpu_clk_sctx.clk_csite_src, 1869 clk_base + CLK_RESET_SOURCE_CSITE); 1870} 1871#endif 1872 1873static struct tegra_cpu_car_ops tegra30_cpu_car_ops = { 1874 .wait_for_reset = tegra30_wait_cpu_in_reset, 1875 .put_in_reset = tegra30_put_cpu_in_reset, 1876 .out_of_reset = tegra30_cpu_out_of_reset, 1877 .enable_clock = tegra30_enable_cpu_clock, 1878 .disable_clock = tegra30_disable_cpu_clock, 1879#ifdef CONFIG_PM_SLEEP 1880 .rail_off_ready = tegra30_cpu_rail_off_ready, 1881 .suspend = tegra30_cpu_clock_suspend, 1882 .resume = tegra30_cpu_clock_resume, 1883#endif 1884}; 1885 1886static __initdata struct tegra_clk_init_table init_table[] = { 1887 {uarta, pll_p, 408000000, 0}, 1888 {uartb, pll_p, 408000000, 0}, 1889 {uartc, pll_p, 408000000, 0}, 1890 {uartd, pll_p, 408000000, 0}, 1891 {uarte, pll_p, 408000000, 0}, 1892 {pll_a, clk_max, 564480000, 1}, 1893 {pll_a_out0, clk_max, 11289600, 1}, 1894 {extern1, pll_a_out0, 0, 1}, 1895 {clk_out_1_mux, extern1, 0, 0}, 1896 {clk_out_1, clk_max, 0, 1}, 1897 {blink, clk_max, 0, 1}, 1898 {i2s0, pll_a_out0, 11289600, 0}, 1899 {i2s1, pll_a_out0, 11289600, 0}, 1900 {i2s2, pll_a_out0, 11289600, 0}, 1901 {i2s3, pll_a_out0, 11289600, 0}, 1902 {i2s4, pll_a_out0, 11289600, 0}, 1903 {sdmmc1, pll_p, 48000000, 0}, 1904 {sdmmc2, pll_p, 48000000, 0}, 1905 {sdmmc3, pll_p, 48000000, 0}, 1906 {pll_m, clk_max, 0, 1}, 1907 {pclk, clk_max, 0, 1}, 1908 {csite, clk_max, 0, 1}, 1909 {emc, clk_max, 0, 1}, 1910 {mselect, clk_max, 0, 1}, 1911 {sbc1, pll_p, 100000000, 0}, 1912 {sbc2, pll_p, 100000000, 0}, 1913 {sbc3, pll_p, 100000000, 0}, 1914 {sbc4, pll_p, 100000000, 0}, 1915 {sbc5, pll_p, 100000000, 0}, 1916 {sbc6, pll_p, 100000000, 0}, 1917 {host1x, pll_c, 150000000, 0}, 1918 {disp1, pll_p, 600000000, 0}, 1919 {disp2, pll_p, 600000000, 0}, 1920 {twd, clk_max, 0, 1}, 1921 {gr2d, pll_c, 300000000, 0}, 1922 {gr3d, pll_c, 300000000, 0}, 1923 {clk_max, clk_max, 0, 0}, /* This MUST be the last entry. */ 1924}; 1925 1926static void __init tegra30_clock_apply_init_table(void) 1927{ 1928 tegra_init_from_table(init_table, clks, clk_max); 1929} 1930 1931/* 1932 * Some clocks may be used by different drivers depending on the board 1933 * configuration. List those here to register them twice in the clock lookup 1934 * table under two names. 1935 */ 1936static struct tegra_clk_duplicate tegra_clk_duplicates[] = { 1937 TEGRA_CLK_DUPLICATE(usbd, "utmip-pad", NULL), 1938 TEGRA_CLK_DUPLICATE(usbd, "tegra-ehci.0", NULL), 1939 TEGRA_CLK_DUPLICATE(usbd, "tegra-otg", NULL), 1940 TEGRA_CLK_DUPLICATE(bsev, "tegra-avp", "bsev"), 1941 TEGRA_CLK_DUPLICATE(bsev, "nvavp", "bsev"), 1942 TEGRA_CLK_DUPLICATE(vde, "tegra-aes", "vde"), 1943 TEGRA_CLK_DUPLICATE(bsea, "tegra-aes", "bsea"), 1944 TEGRA_CLK_DUPLICATE(bsea, "nvavp", "bsea"), 1945 TEGRA_CLK_DUPLICATE(cml1, "tegra_sata_cml", NULL), 1946 TEGRA_CLK_DUPLICATE(cml0, "tegra_pcie", "cml"), 1947 TEGRA_CLK_DUPLICATE(pciex, "tegra_pcie", "pciex"), 1948 TEGRA_CLK_DUPLICATE(vcp, "nvavp", "vcp"), 1949 TEGRA_CLK_DUPLICATE(clk_max, NULL, NULL), /* MUST be the last entry */ 1950}; 1951 1952static const struct of_device_id pmc_match[] __initconst = { 1953 { .compatible = "nvidia,tegra30-pmc" }, 1954 {}, 1955}; 1956 1957void __init tegra30_clock_init(struct device_node *np) 1958{ 1959 struct device_node *node; 1960 int i; 1961 1962 clk_base = of_iomap(np, 0); 1963 if (!clk_base) { 1964 pr_err("ioremap tegra30 CAR failed\n"); 1965 return; 1966 } 1967 1968 node = of_find_matching_node(NULL, pmc_match); 1969 if (!node) { 1970 pr_err("Failed to find pmc node\n"); 1971 BUG(); 1972 } 1973 1974 pmc_base = of_iomap(node, 0); 1975 if (!pmc_base) { 1976 pr_err("Can't map pmc registers\n"); 1977 BUG(); 1978 } 1979 1980 tegra30_osc_clk_init(); 1981 tegra30_fixed_clk_init(); 1982 tegra30_pll_init(); 1983 tegra30_super_clk_init(); 1984 tegra30_periph_clk_init(); 1985 tegra30_audio_clk_init(); 1986 tegra30_pmc_clk_init(); 1987 1988 for (i = 0; i < ARRAY_SIZE(clks); i++) { 1989 if (IS_ERR(clks[i])) { 1990 pr_err("Tegra30 clk %d: register failed with %ld\n", 1991 i, PTR_ERR(clks[i])); 1992 BUG(); 1993 } 1994 if (!clks[i]) 1995 clks[i] = ERR_PTR(-EINVAL); 1996 } 1997 1998 tegra_init_dup_clks(tegra_clk_duplicates, clks, clk_max); 1999 2000 clk_data.clks = clks; 2001 clk_data.clk_num = ARRAY_SIZE(clks); 2002 of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data); 2003 2004 tegra_clk_apply_init_table = tegra30_clock_apply_init_table; 2005 2006 tegra_cpu_car_ops = &tegra30_cpu_car_ops; 2007} 2008