clk-tegra30.c revision 252d0d2bb07119296e215de7dc9afa8d12746b80
1/* 2 * Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved. 3 * 4 * This program is free software; you can redistribute it and/or modify it 5 * under the terms and conditions of the GNU General Public License, 6 * version 2, as published by the Free Software Foundation. 7 * 8 * This program is distributed in the hope it will be useful, but WITHOUT 9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 11 * more details. 12 * 13 * You should have received a copy of the GNU General Public License 14 * along with this program. If not, see <http://www.gnu.org/licenses/>. 15 */ 16 17#include <linux/io.h> 18#include <linux/delay.h> 19#include <linux/clk.h> 20#include <linux/clk-provider.h> 21#include <linux/clkdev.h> 22#include <linux/of.h> 23#include <linux/of_address.h> 24#include <linux/clk/tegra.h> 25#include <linux/tegra-powergate.h> 26 27#include "clk.h" 28 29#define RST_DEVICES_L 0x004 30#define RST_DEVICES_H 0x008 31#define RST_DEVICES_U 0x00c 32#define RST_DEVICES_V 0x358 33#define RST_DEVICES_W 0x35c 34#define RST_DEVICES_SET_L 0x300 35#define RST_DEVICES_CLR_L 0x304 36#define RST_DEVICES_SET_H 0x308 37#define RST_DEVICES_CLR_H 0x30c 38#define RST_DEVICES_SET_U 0x310 39#define RST_DEVICES_CLR_U 0x314 40#define RST_DEVICES_SET_V 0x430 41#define RST_DEVICES_CLR_V 0x434 42#define RST_DEVICES_SET_W 0x438 43#define RST_DEVICES_CLR_W 0x43c 44#define RST_DEVICES_NUM 5 45 46#define CLK_OUT_ENB_L 0x010 47#define CLK_OUT_ENB_H 0x014 48#define CLK_OUT_ENB_U 0x018 49#define CLK_OUT_ENB_V 0x360 50#define CLK_OUT_ENB_W 0x364 51#define CLK_OUT_ENB_SET_L 0x320 52#define CLK_OUT_ENB_CLR_L 0x324 53#define CLK_OUT_ENB_SET_H 0x328 54#define CLK_OUT_ENB_CLR_H 0x32c 55#define CLK_OUT_ENB_SET_U 0x330 56#define CLK_OUT_ENB_CLR_U 0x334 57#define CLK_OUT_ENB_SET_V 0x440 58#define CLK_OUT_ENB_CLR_V 0x444 59#define CLK_OUT_ENB_SET_W 0x448 60#define CLK_OUT_ENB_CLR_W 0x44c 61#define CLK_OUT_ENB_NUM 5 62 63#define OSC_CTRL 0x50 64#define OSC_CTRL_OSC_FREQ_MASK (0xF<<28) 65#define OSC_CTRL_OSC_FREQ_13MHZ (0X0<<28) 66#define OSC_CTRL_OSC_FREQ_19_2MHZ (0X4<<28) 67#define OSC_CTRL_OSC_FREQ_12MHZ (0X8<<28) 68#define OSC_CTRL_OSC_FREQ_26MHZ (0XC<<28) 69#define OSC_CTRL_OSC_FREQ_16_8MHZ (0X1<<28) 70#define OSC_CTRL_OSC_FREQ_38_4MHZ (0X5<<28) 71#define OSC_CTRL_OSC_FREQ_48MHZ (0X9<<28) 72#define OSC_CTRL_MASK (0x3f2 | OSC_CTRL_OSC_FREQ_MASK) 73 74#define OSC_CTRL_PLL_REF_DIV_MASK (3<<26) 75#define OSC_CTRL_PLL_REF_DIV_1 (0<<26) 76#define OSC_CTRL_PLL_REF_DIV_2 (1<<26) 77#define OSC_CTRL_PLL_REF_DIV_4 (2<<26) 78 79#define OSC_FREQ_DET 0x58 80#define OSC_FREQ_DET_TRIG BIT(31) 81 82#define OSC_FREQ_DET_STATUS 0x5c 83#define OSC_FREQ_DET_BUSY BIT(31) 84#define OSC_FREQ_DET_CNT_MASK 0xffff 85 86#define CCLKG_BURST_POLICY 0x368 87#define SUPER_CCLKG_DIVIDER 0x36c 88#define CCLKLP_BURST_POLICY 0x370 89#define SUPER_CCLKLP_DIVIDER 0x374 90#define SCLK_BURST_POLICY 0x028 91#define SUPER_SCLK_DIVIDER 0x02c 92 93#define SYSTEM_CLK_RATE 0x030 94 95#define PLLC_BASE 0x80 96#define PLLC_MISC 0x8c 97#define PLLM_BASE 0x90 98#define PLLM_MISC 0x9c 99#define PLLP_BASE 0xa0 100#define PLLP_MISC 0xac 101#define PLLX_BASE 0xe0 102#define PLLX_MISC 0xe4 103#define PLLD_BASE 0xd0 104#define PLLD_MISC 0xdc 105#define PLLD2_BASE 0x4b8 106#define PLLD2_MISC 0x4bc 107#define PLLE_BASE 0xe8 108#define PLLE_MISC 0xec 109#define PLLA_BASE 0xb0 110#define PLLA_MISC 0xbc 111#define PLLU_BASE 0xc0 112#define PLLU_MISC 0xcc 113 114#define PLL_MISC_LOCK_ENABLE 18 115#define PLLDU_MISC_LOCK_ENABLE 22 116#define PLLE_MISC_LOCK_ENABLE 9 117 118#define PLL_BASE_LOCK BIT(27) 119#define PLLE_MISC_LOCK BIT(11) 120 121#define PLLE_AUX 0x48c 122#define PLLC_OUT 0x84 123#define PLLM_OUT 0x94 124#define PLLP_OUTA 0xa4 125#define PLLP_OUTB 0xa8 126#define PLLA_OUT 0xb4 127 128#define AUDIO_SYNC_CLK_I2S0 0x4a0 129#define AUDIO_SYNC_CLK_I2S1 0x4a4 130#define AUDIO_SYNC_CLK_I2S2 0x4a8 131#define AUDIO_SYNC_CLK_I2S3 0x4ac 132#define AUDIO_SYNC_CLK_I2S4 0x4b0 133#define AUDIO_SYNC_CLK_SPDIF 0x4b4 134 135#define PMC_CLK_OUT_CNTRL 0x1a8 136 137#define CLK_SOURCE_I2S0 0x1d8 138#define CLK_SOURCE_I2S1 0x100 139#define CLK_SOURCE_I2S2 0x104 140#define CLK_SOURCE_I2S3 0x3bc 141#define CLK_SOURCE_I2S4 0x3c0 142#define CLK_SOURCE_SPDIF_OUT 0x108 143#define CLK_SOURCE_SPDIF_IN 0x10c 144#define CLK_SOURCE_PWM 0x110 145#define CLK_SOURCE_D_AUDIO 0x3d0 146#define CLK_SOURCE_DAM0 0x3d8 147#define CLK_SOURCE_DAM1 0x3dc 148#define CLK_SOURCE_DAM2 0x3e0 149#define CLK_SOURCE_HDA 0x428 150#define CLK_SOURCE_HDA2CODEC_2X 0x3e4 151#define CLK_SOURCE_SBC1 0x134 152#define CLK_SOURCE_SBC2 0x118 153#define CLK_SOURCE_SBC3 0x11c 154#define CLK_SOURCE_SBC4 0x1b4 155#define CLK_SOURCE_SBC5 0x3c8 156#define CLK_SOURCE_SBC6 0x3cc 157#define CLK_SOURCE_SATA_OOB 0x420 158#define CLK_SOURCE_SATA 0x424 159#define CLK_SOURCE_NDFLASH 0x160 160#define CLK_SOURCE_NDSPEED 0x3f8 161#define CLK_SOURCE_VFIR 0x168 162#define CLK_SOURCE_SDMMC1 0x150 163#define CLK_SOURCE_SDMMC2 0x154 164#define CLK_SOURCE_SDMMC3 0x1bc 165#define CLK_SOURCE_SDMMC4 0x164 166#define CLK_SOURCE_VDE 0x1c8 167#define CLK_SOURCE_CSITE 0x1d4 168#define CLK_SOURCE_LA 0x1f8 169#define CLK_SOURCE_OWR 0x1cc 170#define CLK_SOURCE_NOR 0x1d0 171#define CLK_SOURCE_MIPI 0x174 172#define CLK_SOURCE_I2C1 0x124 173#define CLK_SOURCE_I2C2 0x198 174#define CLK_SOURCE_I2C3 0x1b8 175#define CLK_SOURCE_I2C4 0x3c4 176#define CLK_SOURCE_I2C5 0x128 177#define CLK_SOURCE_UARTA 0x178 178#define CLK_SOURCE_UARTB 0x17c 179#define CLK_SOURCE_UARTC 0x1a0 180#define CLK_SOURCE_UARTD 0x1c0 181#define CLK_SOURCE_UARTE 0x1c4 182#define CLK_SOURCE_VI 0x148 183#define CLK_SOURCE_VI_SENSOR 0x1a8 184#define CLK_SOURCE_3D 0x158 185#define CLK_SOURCE_3D2 0x3b0 186#define CLK_SOURCE_2D 0x15c 187#define CLK_SOURCE_EPP 0x16c 188#define CLK_SOURCE_MPE 0x170 189#define CLK_SOURCE_HOST1X 0x180 190#define CLK_SOURCE_CVE 0x140 191#define CLK_SOURCE_TVO 0x188 192#define CLK_SOURCE_DTV 0x1dc 193#define CLK_SOURCE_HDMI 0x18c 194#define CLK_SOURCE_TVDAC 0x194 195#define CLK_SOURCE_DISP1 0x138 196#define CLK_SOURCE_DISP2 0x13c 197#define CLK_SOURCE_DSIB 0xd0 198#define CLK_SOURCE_TSENSOR 0x3b8 199#define CLK_SOURCE_ACTMON 0x3e8 200#define CLK_SOURCE_EXTERN1 0x3ec 201#define CLK_SOURCE_EXTERN2 0x3f0 202#define CLK_SOURCE_EXTERN3 0x3f4 203#define CLK_SOURCE_I2CSLOW 0x3fc 204#define CLK_SOURCE_SE 0x42c 205#define CLK_SOURCE_MSELECT 0x3b4 206#define CLK_SOURCE_EMC 0x19c 207 208#define AUDIO_SYNC_DOUBLER 0x49c 209 210#define PMC_CTRL 0 211#define PMC_CTRL_BLINK_ENB 7 212 213#define PMC_DPD_PADS_ORIDE 0x1c 214#define PMC_DPD_PADS_ORIDE_BLINK_ENB 20 215#define PMC_BLINK_TIMER 0x40 216 217#define UTMIP_PLL_CFG2 0x488 218#define UTMIP_PLL_CFG2_STABLE_COUNT(x) (((x) & 0xffff) << 6) 219#define UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(x) (((x) & 0x3f) << 18) 220#define UTMIP_PLL_CFG2_FORCE_PD_SAMP_A_POWERDOWN BIT(0) 221#define UTMIP_PLL_CFG2_FORCE_PD_SAMP_B_POWERDOWN BIT(2) 222#define UTMIP_PLL_CFG2_FORCE_PD_SAMP_C_POWERDOWN BIT(4) 223 224#define UTMIP_PLL_CFG1 0x484 225#define UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(x) (((x) & 0x1f) << 6) 226#define UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(x) (((x) & 0xfff) << 0) 227#define UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN BIT(14) 228#define UTMIP_PLL_CFG1_FORCE_PLL_ACTIVE_POWERDOWN BIT(12) 229#define UTMIP_PLL_CFG1_FORCE_PLLU_POWERDOWN BIT(16) 230 231/* Tegra CPU clock and reset control regs */ 232#define TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX 0x4c 233#define TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET 0x340 234#define TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR 0x344 235#define TEGRA30_CLK_RST_CONTROLLER_CLK_CPU_CMPLX_CLR 0x34c 236#define TEGRA30_CLK_RST_CONTROLLER_CPU_CMPLX_STATUS 0x470 237 238#define CPU_CLOCK(cpu) (0x1 << (8 + cpu)) 239#define CPU_RESET(cpu) (0x1111ul << (cpu)) 240 241#define CLK_RESET_CCLK_BURST 0x20 242#define CLK_RESET_CCLK_DIVIDER 0x24 243#define CLK_RESET_PLLX_BASE 0xe0 244#define CLK_RESET_PLLX_MISC 0xe4 245 246#define CLK_RESET_SOURCE_CSITE 0x1d4 247 248#define CLK_RESET_CCLK_BURST_POLICY_SHIFT 28 249#define CLK_RESET_CCLK_RUN_POLICY_SHIFT 4 250#define CLK_RESET_CCLK_IDLE_POLICY_SHIFT 0 251#define CLK_RESET_CCLK_IDLE_POLICY 1 252#define CLK_RESET_CCLK_RUN_POLICY 2 253#define CLK_RESET_CCLK_BURST_POLICY_PLLX 8 254 255/* PLLM override registers */ 256#define PMC_PLLM_WB0_OVERRIDE 0x1dc 257 258#ifdef CONFIG_PM_SLEEP 259static struct cpu_clk_suspend_context { 260 u32 pllx_misc; 261 u32 pllx_base; 262 263 u32 cpu_burst; 264 u32 clk_csite_src; 265 u32 cclk_divider; 266} tegra30_cpu_clk_sctx; 267#endif 268 269static int periph_clk_enb_refcnt[CLK_OUT_ENB_NUM * 32]; 270 271static void __iomem *clk_base; 272static void __iomem *pmc_base; 273static unsigned long input_freq; 274 275static DEFINE_SPINLOCK(clk_doubler_lock); 276static DEFINE_SPINLOCK(clk_out_lock); 277static DEFINE_SPINLOCK(pll_div_lock); 278static DEFINE_SPINLOCK(cml_lock); 279static DEFINE_SPINLOCK(pll_d_lock); 280static DEFINE_SPINLOCK(sysrate_lock); 281 282#define TEGRA_INIT_DATA_MUX(_name, _con_id, _dev_id, _parents, _offset, \ 283 _clk_num, _regs, _gate_flags, _clk_id) \ 284 TEGRA_INIT_DATA(_name, _con_id, _dev_id, _parents, _offset, \ 285 30, 2, 0, 0, 8, 1, TEGRA_DIVIDER_ROUND_UP, _regs, \ 286 _clk_num, periph_clk_enb_refcnt, _gate_flags, _clk_id) 287 288#define TEGRA_INIT_DATA_DIV16(_name, _con_id, _dev_id, _parents, _offset, \ 289 _clk_num, _regs, _gate_flags, _clk_id) \ 290 TEGRA_INIT_DATA(_name, _con_id, _dev_id, _parents, _offset, \ 291 30, 2, 0, 0, 16, 0, TEGRA_DIVIDER_ROUND_UP, \ 292 _regs, _clk_num, periph_clk_enb_refcnt, \ 293 _gate_flags, _clk_id) 294 295#define TEGRA_INIT_DATA_MUX8(_name, _con_id, _dev_id, _parents, _offset, \ 296 _clk_num, _regs, _gate_flags, _clk_id) \ 297 TEGRA_INIT_DATA(_name, _con_id, _dev_id, _parents, _offset, \ 298 29, 3, 0, 0, 8, 1, TEGRA_DIVIDER_ROUND_UP, _regs,\ 299 _clk_num, periph_clk_enb_refcnt, _gate_flags, _clk_id) 300 301#define TEGRA_INIT_DATA_INT(_name, _con_id, _dev_id, _parents, _offset, \ 302 _clk_num, _regs, _gate_flags, _clk_id) \ 303 TEGRA_INIT_DATA(_name, _con_id, _dev_id, _parents, _offset, \ 304 30, 2, 0, 0, 8, 1, TEGRA_DIVIDER_INT | \ 305 TEGRA_DIVIDER_ROUND_UP, _regs, _clk_num, \ 306 periph_clk_enb_refcnt, _gate_flags, _clk_id) 307 308#define TEGRA_INIT_DATA_UART(_name, _con_id, _dev_id, _parents, _offset,\ 309 _clk_num, _regs, _clk_id) \ 310 TEGRA_INIT_DATA(_name, _con_id, _dev_id, _parents, _offset, \ 311 30, 2, 0, 0, 16, 1, TEGRA_DIVIDER_UART | \ 312 TEGRA_DIVIDER_ROUND_UP, _regs, _clk_num, \ 313 periph_clk_enb_refcnt, 0, _clk_id) 314 315#define TEGRA_INIT_DATA_NODIV(_name, _con_id, _dev_id, _parents, _offset, \ 316 _mux_shift, _mux_width, _clk_num, _regs, \ 317 _gate_flags, _clk_id) \ 318 TEGRA_INIT_DATA(_name, _con_id, _dev_id, _parents, _offset, \ 319 _mux_shift, _mux_width, 0, 0, 0, 0, 0, _regs, \ 320 _clk_num, periph_clk_enb_refcnt, _gate_flags, \ 321 _clk_id) 322 323/* 324 * IDs assigned here must be in sync with DT bindings definition 325 * for Tegra30 clocks. 326 */ 327enum tegra30_clk { 328 cpu, rtc = 4, timer, uarta, gpio = 8, sdmmc2, i2s1 = 11, i2c1, ndflash, 329 sdmmc1, sdmmc4, pwm = 17, i2s2, epp, gr2d = 21, usbd, isp, gr3d, 330 disp2 = 26, disp1, host1x, vcp, i2s0, cop_cache, mc, ahbdma, apbdma, 331 kbc = 36, statmon, pmc, kfuse = 40, sbc1, nor, sbc2 = 44, sbc3 = 46, 332 i2c5, dsia, mipi = 50, hdmi, csi, tvdac, i2c2, uartc, emc = 57, usb2, 333 usb3, mpe, vde, bsea, bsev, speedo, uartd, uarte, i2c3, sbc4, sdmmc3, 334 pcie, owr, afi, csite, pciex, avpucq, la, dtv = 79, ndspeed, i2cslow, 335 dsib, irama = 84, iramb, iramc, iramd, cram2, audio_2x = 90, csus = 92, 336 cdev2, cdev1, cpu_g = 96, cpu_lp, gr3d2, mselect, tsensor, i2s3, i2s4, 337 i2c4, sbc5, sbc6, d_audio, apbif, dam0, dam1, dam2, hda2codec_2x, 338 atomics, audio0_2x, audio1_2x, audio2_2x, audio3_2x, audio4_2x, 339 spdif_2x, actmon, extern1, extern2, extern3, sata_oob, sata, hda, 340 se = 127, hda2hdmi, sata_cold, uartb = 160, vfir, spdif_in, spdif_out, 341 vi, vi_sensor, fuse, fuse_burn, cve, tvo, clk_32k, clk_m, clk_m_div2, 342 clk_m_div4, pll_ref, pll_c, pll_c_out1, pll_m, pll_m_out1, pll_p, 343 pll_p_out1, pll_p_out2, pll_p_out3, pll_p_out4, pll_a, pll_a_out0, 344 pll_d, pll_d_out0, pll_d2, pll_d2_out0, pll_u, pll_x, pll_x_out0, pll_e, 345 spdif_in_sync, i2s0_sync, i2s1_sync, i2s2_sync, i2s3_sync, i2s4_sync, 346 vimclk_sync, audio0, audio1, audio2, audio3, audio4, spdif, clk_out_1, 347 clk_out_2, clk_out_3, sclk, blink, cclk_g, cclk_lp, twd, cml0, cml1, 348 hclk, pclk, clk_out_1_mux = 300, clk_max 349}; 350 351static struct clk *clks[clk_max]; 352static struct clk_onecell_data clk_data; 353 354/* 355 * Structure defining the fields for USB UTMI clocks Parameters. 356 */ 357struct utmi_clk_param { 358 /* Oscillator Frequency in KHz */ 359 u32 osc_frequency; 360 /* UTMIP PLL Enable Delay Count */ 361 u8 enable_delay_count; 362 /* UTMIP PLL Stable count */ 363 u8 stable_count; 364 /* UTMIP PLL Active delay count */ 365 u8 active_delay_count; 366 /* UTMIP PLL Xtal frequency count */ 367 u8 xtal_freq_count; 368}; 369 370static const struct utmi_clk_param utmi_parameters[] = { 371/* OSC_FREQUENCY, ENABLE_DLY, STABLE_CNT, ACTIVE_DLY, XTAL_FREQ_CNT */ 372 {13000000, 0x02, 0x33, 0x05, 0x7F}, 373 {19200000, 0x03, 0x4B, 0x06, 0xBB}, 374 {12000000, 0x02, 0x2F, 0x04, 0x76}, 375 {26000000, 0x04, 0x66, 0x09, 0xFE}, 376 {16800000, 0x03, 0x41, 0x0A, 0xA4}, 377}; 378 379static struct tegra_clk_pll_freq_table pll_c_freq_table[] = { 380 { 12000000, 1040000000, 520, 6, 0, 8}, 381 { 13000000, 1040000000, 480, 6, 0, 8}, 382 { 16800000, 1040000000, 495, 8, 0, 8}, /* actual: 1039.5 MHz */ 383 { 19200000, 1040000000, 325, 6, 0, 6}, 384 { 26000000, 1040000000, 520, 13, 0, 8}, 385 386 { 12000000, 832000000, 416, 6, 0, 8}, 387 { 13000000, 832000000, 832, 13, 0, 8}, 388 { 16800000, 832000000, 396, 8, 0, 8}, /* actual: 831.6 MHz */ 389 { 19200000, 832000000, 260, 6, 0, 8}, 390 { 26000000, 832000000, 416, 13, 0, 8}, 391 392 { 12000000, 624000000, 624, 12, 0, 8}, 393 { 13000000, 624000000, 624, 13, 0, 8}, 394 { 16800000, 600000000, 520, 14, 0, 8}, 395 { 19200000, 624000000, 520, 16, 0, 8}, 396 { 26000000, 624000000, 624, 26, 0, 8}, 397 398 { 12000000, 600000000, 600, 12, 0, 8}, 399 { 13000000, 600000000, 600, 13, 0, 8}, 400 { 16800000, 600000000, 500, 14, 0, 8}, 401 { 19200000, 600000000, 375, 12, 0, 6}, 402 { 26000000, 600000000, 600, 26, 0, 8}, 403 404 { 12000000, 520000000, 520, 12, 0, 8}, 405 { 13000000, 520000000, 520, 13, 0, 8}, 406 { 16800000, 520000000, 495, 16, 0, 8}, /* actual: 519.75 MHz */ 407 { 19200000, 520000000, 325, 12, 0, 6}, 408 { 26000000, 520000000, 520, 26, 0, 8}, 409 410 { 12000000, 416000000, 416, 12, 0, 8}, 411 { 13000000, 416000000, 416, 13, 0, 8}, 412 { 16800000, 416000000, 396, 16, 0, 8}, /* actual: 415.8 MHz */ 413 { 19200000, 416000000, 260, 12, 0, 6}, 414 { 26000000, 416000000, 416, 26, 0, 8}, 415 { 0, 0, 0, 0, 0, 0 }, 416}; 417 418static struct tegra_clk_pll_freq_table pll_m_freq_table[] = { 419 { 12000000, 666000000, 666, 12, 0, 8}, 420 { 13000000, 666000000, 666, 13, 0, 8}, 421 { 16800000, 666000000, 555, 14, 0, 8}, 422 { 19200000, 666000000, 555, 16, 0, 8}, 423 { 26000000, 666000000, 666, 26, 0, 8}, 424 { 12000000, 600000000, 600, 12, 0, 8}, 425 { 13000000, 600000000, 600, 13, 0, 8}, 426 { 16800000, 600000000, 500, 14, 0, 8}, 427 { 19200000, 600000000, 375, 12, 0, 6}, 428 { 26000000, 600000000, 600, 26, 0, 8}, 429 { 0, 0, 0, 0, 0, 0 }, 430}; 431 432static struct tegra_clk_pll_freq_table pll_p_freq_table[] = { 433 { 12000000, 216000000, 432, 12, 1, 8}, 434 { 13000000, 216000000, 432, 13, 1, 8}, 435 { 16800000, 216000000, 360, 14, 1, 8}, 436 { 19200000, 216000000, 360, 16, 1, 8}, 437 { 26000000, 216000000, 432, 26, 1, 8}, 438 { 0, 0, 0, 0, 0, 0 }, 439}; 440 441static struct tegra_clk_pll_freq_table pll_a_freq_table[] = { 442 { 9600000, 564480000, 294, 5, 0, 4}, 443 { 9600000, 552960000, 288, 5, 0, 4}, 444 { 9600000, 24000000, 5, 2, 0, 1}, 445 446 { 28800000, 56448000, 49, 25, 0, 1}, 447 { 28800000, 73728000, 64, 25, 0, 1}, 448 { 28800000, 24000000, 5, 6, 0, 1}, 449 { 0, 0, 0, 0, 0, 0 }, 450}; 451 452static struct tegra_clk_pll_freq_table pll_d_freq_table[] = { 453 { 12000000, 216000000, 216, 12, 0, 4}, 454 { 13000000, 216000000, 216, 13, 0, 4}, 455 { 16800000, 216000000, 180, 14, 0, 4}, 456 { 19200000, 216000000, 180, 16, 0, 4}, 457 { 26000000, 216000000, 216, 26, 0, 4}, 458 459 { 12000000, 594000000, 594, 12, 0, 8}, 460 { 13000000, 594000000, 594, 13, 0, 8}, 461 { 16800000, 594000000, 495, 14, 0, 8}, 462 { 19200000, 594000000, 495, 16, 0, 8}, 463 { 26000000, 594000000, 594, 26, 0, 8}, 464 465 { 12000000, 1000000000, 1000, 12, 0, 12}, 466 { 13000000, 1000000000, 1000, 13, 0, 12}, 467 { 19200000, 1000000000, 625, 12, 0, 8}, 468 { 26000000, 1000000000, 1000, 26, 0, 12}, 469 470 { 0, 0, 0, 0, 0, 0 }, 471}; 472 473static struct pdiv_map pllu_p[] = { 474 { .pdiv = 1, .hw_val = 1 }, 475 { .pdiv = 2, .hw_val = 0 }, 476 { .pdiv = 0, .hw_val = 0 }, 477}; 478 479static struct tegra_clk_pll_freq_table pll_u_freq_table[] = { 480 { 12000000, 480000000, 960, 12, 0, 12}, 481 { 13000000, 480000000, 960, 13, 0, 12}, 482 { 16800000, 480000000, 400, 7, 0, 5}, 483 { 19200000, 480000000, 200, 4, 0, 3}, 484 { 26000000, 480000000, 960, 26, 0, 12}, 485 { 0, 0, 0, 0, 0, 0 }, 486}; 487 488static struct tegra_clk_pll_freq_table pll_x_freq_table[] = { 489 /* 1.7 GHz */ 490 { 12000000, 1700000000, 850, 6, 0, 8}, 491 { 13000000, 1700000000, 915, 7, 0, 8}, /* actual: 1699.2 MHz */ 492 { 16800000, 1700000000, 708, 7, 0, 8}, /* actual: 1699.2 MHz */ 493 { 19200000, 1700000000, 885, 10, 0, 8}, /* actual: 1699.2 MHz */ 494 { 26000000, 1700000000, 850, 13, 0, 8}, 495 496 /* 1.6 GHz */ 497 { 12000000, 1600000000, 800, 6, 0, 8}, 498 { 13000000, 1600000000, 738, 6, 0, 8}, /* actual: 1599.0 MHz */ 499 { 16800000, 1600000000, 857, 9, 0, 8}, /* actual: 1599.7 MHz */ 500 { 19200000, 1600000000, 500, 6, 0, 8}, 501 { 26000000, 1600000000, 800, 13, 0, 8}, 502 503 /* 1.5 GHz */ 504 { 12000000, 1500000000, 750, 6, 0, 8}, 505 { 13000000, 1500000000, 923, 8, 0, 8}, /* actual: 1499.8 MHz */ 506 { 16800000, 1500000000, 625, 7, 0, 8}, 507 { 19200000, 1500000000, 625, 8, 0, 8}, 508 { 26000000, 1500000000, 750, 13, 0, 8}, 509 510 /* 1.4 GHz */ 511 { 12000000, 1400000000, 700, 6, 0, 8}, 512 { 13000000, 1400000000, 969, 9, 0, 8}, /* actual: 1399.7 MHz */ 513 { 16800000, 1400000000, 1000, 12, 0, 8}, 514 { 19200000, 1400000000, 875, 12, 0, 8}, 515 { 26000000, 1400000000, 700, 13, 0, 8}, 516 517 /* 1.3 GHz */ 518 { 12000000, 1300000000, 975, 9, 0, 8}, 519 { 13000000, 1300000000, 1000, 10, 0, 8}, 520 { 16800000, 1300000000, 928, 12, 0, 8}, /* actual: 1299.2 MHz */ 521 { 19200000, 1300000000, 812, 12, 0, 8}, /* actual: 1299.2 MHz */ 522 { 26000000, 1300000000, 650, 13, 0, 8}, 523 524 /* 1.2 GHz */ 525 { 12000000, 1200000000, 1000, 10, 0, 8}, 526 { 13000000, 1200000000, 923, 10, 0, 8}, /* actual: 1199.9 MHz */ 527 { 16800000, 1200000000, 1000, 14, 0, 8}, 528 { 19200000, 1200000000, 1000, 16, 0, 8}, 529 { 26000000, 1200000000, 600, 13, 0, 8}, 530 531 /* 1.1 GHz */ 532 { 12000000, 1100000000, 825, 9, 0, 8}, 533 { 13000000, 1100000000, 846, 10, 0, 8}, /* actual: 1099.8 MHz */ 534 { 16800000, 1100000000, 982, 15, 0, 8}, /* actual: 1099.8 MHz */ 535 { 19200000, 1100000000, 859, 15, 0, 8}, /* actual: 1099.5 MHz */ 536 { 26000000, 1100000000, 550, 13, 0, 8}, 537 538 /* 1 GHz */ 539 { 12000000, 1000000000, 1000, 12, 0, 8}, 540 { 13000000, 1000000000, 1000, 13, 0, 8}, 541 { 16800000, 1000000000, 833, 14, 0, 8}, /* actual: 999.6 MHz */ 542 { 19200000, 1000000000, 625, 12, 0, 8}, 543 { 26000000, 1000000000, 1000, 26, 0, 8}, 544 545 { 0, 0, 0, 0, 0, 0 }, 546}; 547 548static struct tegra_clk_pll_freq_table pll_e_freq_table[] = { 549 /* PLLE special case: use cpcon field to store cml divider value */ 550 { 12000000, 100000000, 150, 1, 18, 11}, 551 { 216000000, 100000000, 200, 18, 24, 13}, 552 { 0, 0, 0, 0, 0, 0 }, 553}; 554 555/* PLL parameters */ 556static struct tegra_clk_pll_params pll_c_params = { 557 .input_min = 2000000, 558 .input_max = 31000000, 559 .cf_min = 1000000, 560 .cf_max = 6000000, 561 .vco_min = 20000000, 562 .vco_max = 1400000000, 563 .base_reg = PLLC_BASE, 564 .misc_reg = PLLC_MISC, 565 .lock_mask = PLL_BASE_LOCK, 566 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE, 567 .lock_delay = 300, 568}; 569 570static struct div_nmp pllm_nmp = { 571 .divn_shift = 8, 572 .divn_width = 10, 573 .override_divn_shift = 5, 574 .divm_shift = 0, 575 .divm_width = 5, 576 .override_divm_shift = 0, 577 .divp_shift = 20, 578 .divp_width = 3, 579 .override_divp_shift = 15, 580}; 581 582static struct tegra_clk_pll_params pll_m_params = { 583 .input_min = 2000000, 584 .input_max = 31000000, 585 .cf_min = 1000000, 586 .cf_max = 6000000, 587 .vco_min = 20000000, 588 .vco_max = 1200000000, 589 .base_reg = PLLM_BASE, 590 .misc_reg = PLLM_MISC, 591 .lock_mask = PLL_BASE_LOCK, 592 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE, 593 .lock_delay = 300, 594 .div_nmp = &pllm_nmp, 595 .pmc_divnm_reg = PMC_PLLM_WB0_OVERRIDE, 596 .pmc_divp_reg = PMC_PLLM_WB0_OVERRIDE, 597}; 598 599static struct tegra_clk_pll_params pll_p_params = { 600 .input_min = 2000000, 601 .input_max = 31000000, 602 .cf_min = 1000000, 603 .cf_max = 6000000, 604 .vco_min = 20000000, 605 .vco_max = 1400000000, 606 .base_reg = PLLP_BASE, 607 .misc_reg = PLLP_MISC, 608 .lock_mask = PLL_BASE_LOCK, 609 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE, 610 .lock_delay = 300, 611}; 612 613static struct tegra_clk_pll_params pll_a_params = { 614 .input_min = 2000000, 615 .input_max = 31000000, 616 .cf_min = 1000000, 617 .cf_max = 6000000, 618 .vco_min = 20000000, 619 .vco_max = 1400000000, 620 .base_reg = PLLA_BASE, 621 .misc_reg = PLLA_MISC, 622 .lock_mask = PLL_BASE_LOCK, 623 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE, 624 .lock_delay = 300, 625}; 626 627static struct tegra_clk_pll_params pll_d_params = { 628 .input_min = 2000000, 629 .input_max = 40000000, 630 .cf_min = 1000000, 631 .cf_max = 6000000, 632 .vco_min = 40000000, 633 .vco_max = 1000000000, 634 .base_reg = PLLD_BASE, 635 .misc_reg = PLLD_MISC, 636 .lock_mask = PLL_BASE_LOCK, 637 .lock_enable_bit_idx = PLLDU_MISC_LOCK_ENABLE, 638 .lock_delay = 1000, 639}; 640 641static struct tegra_clk_pll_params pll_d2_params = { 642 .input_min = 2000000, 643 .input_max = 40000000, 644 .cf_min = 1000000, 645 .cf_max = 6000000, 646 .vco_min = 40000000, 647 .vco_max = 1000000000, 648 .base_reg = PLLD2_BASE, 649 .misc_reg = PLLD2_MISC, 650 .lock_mask = PLL_BASE_LOCK, 651 .lock_enable_bit_idx = PLLDU_MISC_LOCK_ENABLE, 652 .lock_delay = 1000, 653}; 654 655static struct tegra_clk_pll_params pll_u_params = { 656 .input_min = 2000000, 657 .input_max = 40000000, 658 .cf_min = 1000000, 659 .cf_max = 6000000, 660 .vco_min = 48000000, 661 .vco_max = 960000000, 662 .base_reg = PLLU_BASE, 663 .misc_reg = PLLU_MISC, 664 .lock_mask = PLL_BASE_LOCK, 665 .lock_enable_bit_idx = PLLDU_MISC_LOCK_ENABLE, 666 .lock_delay = 1000, 667 .pdiv_tohw = pllu_p, 668}; 669 670static struct tegra_clk_pll_params pll_x_params = { 671 .input_min = 2000000, 672 .input_max = 31000000, 673 .cf_min = 1000000, 674 .cf_max = 6000000, 675 .vco_min = 20000000, 676 .vco_max = 1700000000, 677 .base_reg = PLLX_BASE, 678 .misc_reg = PLLX_MISC, 679 .lock_mask = PLL_BASE_LOCK, 680 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE, 681 .lock_delay = 300, 682}; 683 684static struct tegra_clk_pll_params pll_e_params = { 685 .input_min = 12000000, 686 .input_max = 216000000, 687 .cf_min = 12000000, 688 .cf_max = 12000000, 689 .vco_min = 1200000000, 690 .vco_max = 2400000000U, 691 .base_reg = PLLE_BASE, 692 .misc_reg = PLLE_MISC, 693 .lock_mask = PLLE_MISC_LOCK, 694 .lock_enable_bit_idx = PLLE_MISC_LOCK_ENABLE, 695 .lock_delay = 300, 696}; 697 698/* Peripheral clock registers */ 699static struct tegra_clk_periph_regs periph_l_regs = { 700 .enb_reg = CLK_OUT_ENB_L, 701 .enb_set_reg = CLK_OUT_ENB_SET_L, 702 .enb_clr_reg = CLK_OUT_ENB_CLR_L, 703 .rst_reg = RST_DEVICES_L, 704 .rst_set_reg = RST_DEVICES_SET_L, 705 .rst_clr_reg = RST_DEVICES_CLR_L, 706}; 707 708static struct tegra_clk_periph_regs periph_h_regs = { 709 .enb_reg = CLK_OUT_ENB_H, 710 .enb_set_reg = CLK_OUT_ENB_SET_H, 711 .enb_clr_reg = CLK_OUT_ENB_CLR_H, 712 .rst_reg = RST_DEVICES_H, 713 .rst_set_reg = RST_DEVICES_SET_H, 714 .rst_clr_reg = RST_DEVICES_CLR_H, 715}; 716 717static struct tegra_clk_periph_regs periph_u_regs = { 718 .enb_reg = CLK_OUT_ENB_U, 719 .enb_set_reg = CLK_OUT_ENB_SET_U, 720 .enb_clr_reg = CLK_OUT_ENB_CLR_U, 721 .rst_reg = RST_DEVICES_U, 722 .rst_set_reg = RST_DEVICES_SET_U, 723 .rst_clr_reg = RST_DEVICES_CLR_U, 724}; 725 726static struct tegra_clk_periph_regs periph_v_regs = { 727 .enb_reg = CLK_OUT_ENB_V, 728 .enb_set_reg = CLK_OUT_ENB_SET_V, 729 .enb_clr_reg = CLK_OUT_ENB_CLR_V, 730 .rst_reg = RST_DEVICES_V, 731 .rst_set_reg = RST_DEVICES_SET_V, 732 .rst_clr_reg = RST_DEVICES_CLR_V, 733}; 734 735static struct tegra_clk_periph_regs periph_w_regs = { 736 .enb_reg = CLK_OUT_ENB_W, 737 .enb_set_reg = CLK_OUT_ENB_SET_W, 738 .enb_clr_reg = CLK_OUT_ENB_CLR_W, 739 .rst_reg = RST_DEVICES_W, 740 .rst_set_reg = RST_DEVICES_SET_W, 741 .rst_clr_reg = RST_DEVICES_CLR_W, 742}; 743 744static void tegra30_clk_measure_input_freq(void) 745{ 746 u32 osc_ctrl = readl_relaxed(clk_base + OSC_CTRL); 747 u32 auto_clk_control = osc_ctrl & OSC_CTRL_OSC_FREQ_MASK; 748 u32 pll_ref_div = osc_ctrl & OSC_CTRL_PLL_REF_DIV_MASK; 749 750 switch (auto_clk_control) { 751 case OSC_CTRL_OSC_FREQ_12MHZ: 752 BUG_ON(pll_ref_div != OSC_CTRL_PLL_REF_DIV_1); 753 input_freq = 12000000; 754 break; 755 case OSC_CTRL_OSC_FREQ_13MHZ: 756 BUG_ON(pll_ref_div != OSC_CTRL_PLL_REF_DIV_1); 757 input_freq = 13000000; 758 break; 759 case OSC_CTRL_OSC_FREQ_19_2MHZ: 760 BUG_ON(pll_ref_div != OSC_CTRL_PLL_REF_DIV_1); 761 input_freq = 19200000; 762 break; 763 case OSC_CTRL_OSC_FREQ_26MHZ: 764 BUG_ON(pll_ref_div != OSC_CTRL_PLL_REF_DIV_1); 765 input_freq = 26000000; 766 break; 767 case OSC_CTRL_OSC_FREQ_16_8MHZ: 768 BUG_ON(pll_ref_div != OSC_CTRL_PLL_REF_DIV_1); 769 input_freq = 16800000; 770 break; 771 case OSC_CTRL_OSC_FREQ_38_4MHZ: 772 BUG_ON(pll_ref_div != OSC_CTRL_PLL_REF_DIV_2); 773 input_freq = 38400000; 774 break; 775 case OSC_CTRL_OSC_FREQ_48MHZ: 776 BUG_ON(pll_ref_div != OSC_CTRL_PLL_REF_DIV_4); 777 input_freq = 48000000; 778 break; 779 default: 780 pr_err("Unexpected auto clock control value %d", 781 auto_clk_control); 782 BUG(); 783 return; 784 } 785} 786 787static unsigned int tegra30_get_pll_ref_div(void) 788{ 789 u32 pll_ref_div = readl_relaxed(clk_base + OSC_CTRL) & 790 OSC_CTRL_PLL_REF_DIV_MASK; 791 792 switch (pll_ref_div) { 793 case OSC_CTRL_PLL_REF_DIV_1: 794 return 1; 795 case OSC_CTRL_PLL_REF_DIV_2: 796 return 2; 797 case OSC_CTRL_PLL_REF_DIV_4: 798 return 4; 799 default: 800 pr_err("Invalid pll ref divider %d", pll_ref_div); 801 BUG(); 802 } 803 return 0; 804} 805 806static void tegra30_utmi_param_configure(void) 807{ 808 u32 reg; 809 int i; 810 811 for (i = 0; i < ARRAY_SIZE(utmi_parameters); i++) { 812 if (input_freq == utmi_parameters[i].osc_frequency) 813 break; 814 } 815 816 if (i >= ARRAY_SIZE(utmi_parameters)) { 817 pr_err("%s: Unexpected input rate %lu\n", __func__, input_freq); 818 return; 819 } 820 821 reg = readl_relaxed(clk_base + UTMIP_PLL_CFG2); 822 823 /* Program UTMIP PLL stable and active counts */ 824 reg &= ~UTMIP_PLL_CFG2_STABLE_COUNT(~0); 825 reg |= UTMIP_PLL_CFG2_STABLE_COUNT( 826 utmi_parameters[i].stable_count); 827 828 reg &= ~UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(~0); 829 830 reg |= UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT( 831 utmi_parameters[i].active_delay_count); 832 833 /* Remove power downs from UTMIP PLL control bits */ 834 reg &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_A_POWERDOWN; 835 reg &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_B_POWERDOWN; 836 reg &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_C_POWERDOWN; 837 838 writel_relaxed(reg, clk_base + UTMIP_PLL_CFG2); 839 840 /* Program UTMIP PLL delay and oscillator frequency counts */ 841 reg = readl_relaxed(clk_base + UTMIP_PLL_CFG1); 842 reg &= ~UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(~0); 843 844 reg |= UTMIP_PLL_CFG1_ENABLE_DLY_COUNT( 845 utmi_parameters[i].enable_delay_count); 846 847 reg &= ~UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(~0); 848 reg |= UTMIP_PLL_CFG1_XTAL_FREQ_COUNT( 849 utmi_parameters[i].xtal_freq_count); 850 851 /* Remove power downs from UTMIP PLL control bits */ 852 reg &= ~UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN; 853 reg &= ~UTMIP_PLL_CFG1_FORCE_PLL_ACTIVE_POWERDOWN; 854 reg &= ~UTMIP_PLL_CFG1_FORCE_PLLU_POWERDOWN; 855 856 writel_relaxed(reg, clk_base + UTMIP_PLL_CFG1); 857} 858 859static const char *pll_e_parents[] = {"pll_ref", "pll_p"}; 860 861static void __init tegra30_pll_init(void) 862{ 863 struct clk *clk; 864 865 /* PLLC */ 866 clk = tegra_clk_register_pll("pll_c", "pll_ref", clk_base, pmc_base, 0, 867 0, &pll_c_params, 868 TEGRA_PLL_HAS_CPCON | TEGRA_PLL_USE_LOCK, 869 pll_c_freq_table, NULL); 870 clk_register_clkdev(clk, "pll_c", NULL); 871 clks[pll_c] = clk; 872 873 /* PLLC_OUT1 */ 874 clk = tegra_clk_register_divider("pll_c_out1_div", "pll_c", 875 clk_base + PLLC_OUT, 0, TEGRA_DIVIDER_ROUND_UP, 876 8, 8, 1, NULL); 877 clk = tegra_clk_register_pll_out("pll_c_out1", "pll_c_out1_div", 878 clk_base + PLLC_OUT, 1, 0, CLK_SET_RATE_PARENT, 879 0, NULL); 880 clk_register_clkdev(clk, "pll_c_out1", NULL); 881 clks[pll_c_out1] = clk; 882 883 /* PLLP */ 884 clk = tegra_clk_register_pll("pll_p", "pll_ref", clk_base, pmc_base, 0, 885 408000000, &pll_p_params, 886 TEGRA_PLL_FIXED | TEGRA_PLL_HAS_CPCON | 887 TEGRA_PLL_USE_LOCK, pll_p_freq_table, NULL); 888 clk_register_clkdev(clk, "pll_p", NULL); 889 clks[pll_p] = clk; 890 891 /* PLLP_OUT1 */ 892 clk = tegra_clk_register_divider("pll_p_out1_div", "pll_p", 893 clk_base + PLLP_OUTA, 0, TEGRA_DIVIDER_FIXED | 894 TEGRA_DIVIDER_ROUND_UP, 8, 8, 1, 895 &pll_div_lock); 896 clk = tegra_clk_register_pll_out("pll_p_out1", "pll_p_out1_div", 897 clk_base + PLLP_OUTA, 1, 0, 898 CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0, 899 &pll_div_lock); 900 clk_register_clkdev(clk, "pll_p_out1", NULL); 901 clks[pll_p_out1] = clk; 902 903 /* PLLP_OUT2 */ 904 clk = tegra_clk_register_divider("pll_p_out2_div", "pll_p", 905 clk_base + PLLP_OUTA, 0, TEGRA_DIVIDER_FIXED | 906 TEGRA_DIVIDER_ROUND_UP, 24, 8, 1, 907 &pll_div_lock); 908 clk = tegra_clk_register_pll_out("pll_p_out2", "pll_p_out2_div", 909 clk_base + PLLP_OUTA, 17, 16, 910 CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0, 911 &pll_div_lock); 912 clk_register_clkdev(clk, "pll_p_out2", NULL); 913 clks[pll_p_out2] = clk; 914 915 /* PLLP_OUT3 */ 916 clk = tegra_clk_register_divider("pll_p_out3_div", "pll_p", 917 clk_base + PLLP_OUTB, 0, TEGRA_DIVIDER_FIXED | 918 TEGRA_DIVIDER_ROUND_UP, 8, 8, 1, 919 &pll_div_lock); 920 clk = tegra_clk_register_pll_out("pll_p_out3", "pll_p_out3_div", 921 clk_base + PLLP_OUTB, 1, 0, 922 CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0, 923 &pll_div_lock); 924 clk_register_clkdev(clk, "pll_p_out3", NULL); 925 clks[pll_p_out3] = clk; 926 927 /* PLLP_OUT4 */ 928 clk = tegra_clk_register_divider("pll_p_out4_div", "pll_p", 929 clk_base + PLLP_OUTB, 0, TEGRA_DIVIDER_FIXED | 930 TEGRA_DIVIDER_ROUND_UP, 24, 8, 1, 931 &pll_div_lock); 932 clk = tegra_clk_register_pll_out("pll_p_out4", "pll_p_out4_div", 933 clk_base + PLLP_OUTB, 17, 16, 934 CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0, 935 &pll_div_lock); 936 clk_register_clkdev(clk, "pll_p_out4", NULL); 937 clks[pll_p_out4] = clk; 938 939 /* PLLM */ 940 clk = tegra_clk_register_pll("pll_m", "pll_ref", clk_base, pmc_base, 941 CLK_IGNORE_UNUSED | CLK_SET_RATE_GATE, 0, 942 &pll_m_params, TEGRA_PLLM | TEGRA_PLL_HAS_CPCON | 943 TEGRA_PLL_SET_DCCON | TEGRA_PLL_USE_LOCK, 944 pll_m_freq_table, NULL); 945 clk_register_clkdev(clk, "pll_m", NULL); 946 clks[pll_m] = clk; 947 948 /* PLLM_OUT1 */ 949 clk = tegra_clk_register_divider("pll_m_out1_div", "pll_m", 950 clk_base + PLLM_OUT, 0, TEGRA_DIVIDER_ROUND_UP, 951 8, 8, 1, NULL); 952 clk = tegra_clk_register_pll_out("pll_m_out1", "pll_m_out1_div", 953 clk_base + PLLM_OUT, 1, 0, CLK_IGNORE_UNUSED | 954 CLK_SET_RATE_PARENT, 0, NULL); 955 clk_register_clkdev(clk, "pll_m_out1", NULL); 956 clks[pll_m_out1] = clk; 957 958 /* PLLX */ 959 clk = tegra_clk_register_pll("pll_x", "pll_ref", clk_base, pmc_base, 0, 960 0, &pll_x_params, TEGRA_PLL_HAS_CPCON | 961 TEGRA_PLL_SET_DCCON | TEGRA_PLL_USE_LOCK, 962 pll_x_freq_table, NULL); 963 clk_register_clkdev(clk, "pll_x", NULL); 964 clks[pll_x] = clk; 965 966 /* PLLX_OUT0 */ 967 clk = clk_register_fixed_factor(NULL, "pll_x_out0", "pll_x", 968 CLK_SET_RATE_PARENT, 1, 2); 969 clk_register_clkdev(clk, "pll_x_out0", NULL); 970 clks[pll_x_out0] = clk; 971 972 /* PLLU */ 973 clk = tegra_clk_register_pll("pll_u", "pll_ref", clk_base, pmc_base, 0, 974 0, &pll_u_params, TEGRA_PLLU | TEGRA_PLL_HAS_CPCON | 975 TEGRA_PLL_SET_LFCON, 976 pll_u_freq_table, 977 NULL); 978 clk_register_clkdev(clk, "pll_u", NULL); 979 clks[pll_u] = clk; 980 981 tegra30_utmi_param_configure(); 982 983 /* PLLD */ 984 clk = tegra_clk_register_pll("pll_d", "pll_ref", clk_base, pmc_base, 0, 985 0, &pll_d_params, TEGRA_PLL_HAS_CPCON | 986 TEGRA_PLL_SET_LFCON | TEGRA_PLL_USE_LOCK, 987 pll_d_freq_table, &pll_d_lock); 988 clk_register_clkdev(clk, "pll_d", NULL); 989 clks[pll_d] = clk; 990 991 /* PLLD_OUT0 */ 992 clk = clk_register_fixed_factor(NULL, "pll_d_out0", "pll_d", 993 CLK_SET_RATE_PARENT, 1, 2); 994 clk_register_clkdev(clk, "pll_d_out0", NULL); 995 clks[pll_d_out0] = clk; 996 997 /* PLLD2 */ 998 clk = tegra_clk_register_pll("pll_d2", "pll_ref", clk_base, pmc_base, 0, 999 0, &pll_d2_params, TEGRA_PLL_HAS_CPCON | 1000 TEGRA_PLL_SET_LFCON | TEGRA_PLL_USE_LOCK, 1001 pll_d_freq_table, NULL); 1002 clk_register_clkdev(clk, "pll_d2", NULL); 1003 clks[pll_d2] = clk; 1004 1005 /* PLLD2_OUT0 */ 1006 clk = clk_register_fixed_factor(NULL, "pll_d2_out0", "pll_d2", 1007 CLK_SET_RATE_PARENT, 1, 2); 1008 clk_register_clkdev(clk, "pll_d2_out0", NULL); 1009 clks[pll_d2_out0] = clk; 1010 1011 /* PLLA */ 1012 clk = tegra_clk_register_pll("pll_a", "pll_p_out1", clk_base, pmc_base, 1013 0, 0, &pll_a_params, TEGRA_PLL_HAS_CPCON | 1014 TEGRA_PLL_USE_LOCK, pll_a_freq_table, NULL); 1015 clk_register_clkdev(clk, "pll_a", NULL); 1016 clks[pll_a] = clk; 1017 1018 /* PLLA_OUT0 */ 1019 clk = tegra_clk_register_divider("pll_a_out0_div", "pll_a", 1020 clk_base + PLLA_OUT, 0, TEGRA_DIVIDER_ROUND_UP, 1021 8, 8, 1, NULL); 1022 clk = tegra_clk_register_pll_out("pll_a_out0", "pll_a_out0_div", 1023 clk_base + PLLA_OUT, 1, 0, CLK_IGNORE_UNUSED | 1024 CLK_SET_RATE_PARENT, 0, NULL); 1025 clk_register_clkdev(clk, "pll_a_out0", NULL); 1026 clks[pll_a_out0] = clk; 1027 1028 /* PLLE */ 1029 clk = clk_register_mux(NULL, "pll_e_mux", pll_e_parents, 1030 ARRAY_SIZE(pll_e_parents), 1031 CLK_SET_RATE_NO_REPARENT, 1032 clk_base + PLLE_AUX, 2, 1, 0, NULL); 1033 clk = tegra_clk_register_plle("pll_e", "pll_e_mux", clk_base, pmc_base, 1034 CLK_GET_RATE_NOCACHE, 100000000, &pll_e_params, 1035 TEGRA_PLLE_CONFIGURE, pll_e_freq_table, NULL); 1036 clk_register_clkdev(clk, "pll_e", NULL); 1037 clks[pll_e] = clk; 1038} 1039 1040static const char *mux_audio_sync_clk[] = { "spdif_in_sync", "i2s0_sync", 1041 "i2s1_sync", "i2s2_sync", "i2s3_sync", "i2s4_sync", "vimclk_sync",}; 1042static const char *clk_out1_parents[] = { "clk_m", "clk_m_div2", 1043 "clk_m_div4", "extern1", }; 1044static const char *clk_out2_parents[] = { "clk_m", "clk_m_div2", 1045 "clk_m_div4", "extern2", }; 1046static const char *clk_out3_parents[] = { "clk_m", "clk_m_div2", 1047 "clk_m_div4", "extern3", }; 1048 1049static void __init tegra30_audio_clk_init(void) 1050{ 1051 struct clk *clk; 1052 1053 /* spdif_in_sync */ 1054 clk = tegra_clk_register_sync_source("spdif_in_sync", 24000000, 1055 24000000); 1056 clk_register_clkdev(clk, "spdif_in_sync", NULL); 1057 clks[spdif_in_sync] = clk; 1058 1059 /* i2s0_sync */ 1060 clk = tegra_clk_register_sync_source("i2s0_sync", 24000000, 24000000); 1061 clk_register_clkdev(clk, "i2s0_sync", NULL); 1062 clks[i2s0_sync] = clk; 1063 1064 /* i2s1_sync */ 1065 clk = tegra_clk_register_sync_source("i2s1_sync", 24000000, 24000000); 1066 clk_register_clkdev(clk, "i2s1_sync", NULL); 1067 clks[i2s1_sync] = clk; 1068 1069 /* i2s2_sync */ 1070 clk = tegra_clk_register_sync_source("i2s2_sync", 24000000, 24000000); 1071 clk_register_clkdev(clk, "i2s2_sync", NULL); 1072 clks[i2s2_sync] = clk; 1073 1074 /* i2s3_sync */ 1075 clk = tegra_clk_register_sync_source("i2s3_sync", 24000000, 24000000); 1076 clk_register_clkdev(clk, "i2s3_sync", NULL); 1077 clks[i2s3_sync] = clk; 1078 1079 /* i2s4_sync */ 1080 clk = tegra_clk_register_sync_source("i2s4_sync", 24000000, 24000000); 1081 clk_register_clkdev(clk, "i2s4_sync", NULL); 1082 clks[i2s4_sync] = clk; 1083 1084 /* vimclk_sync */ 1085 clk = tegra_clk_register_sync_source("vimclk_sync", 24000000, 24000000); 1086 clk_register_clkdev(clk, "vimclk_sync", NULL); 1087 clks[vimclk_sync] = clk; 1088 1089 /* audio0 */ 1090 clk = clk_register_mux(NULL, "audio0_mux", mux_audio_sync_clk, 1091 ARRAY_SIZE(mux_audio_sync_clk), 1092 CLK_SET_RATE_NO_REPARENT, 1093 clk_base + AUDIO_SYNC_CLK_I2S0, 0, 3, 0, NULL); 1094 clk = clk_register_gate(NULL, "audio0", "audio0_mux", 0, 1095 clk_base + AUDIO_SYNC_CLK_I2S0, 4, 1096 CLK_GATE_SET_TO_DISABLE, NULL); 1097 clk_register_clkdev(clk, "audio0", NULL); 1098 clks[audio0] = clk; 1099 1100 /* audio1 */ 1101 clk = clk_register_mux(NULL, "audio1_mux", mux_audio_sync_clk, 1102 ARRAY_SIZE(mux_audio_sync_clk), 1103 CLK_SET_RATE_NO_REPARENT, 1104 clk_base + AUDIO_SYNC_CLK_I2S1, 0, 3, 0, NULL); 1105 clk = clk_register_gate(NULL, "audio1", "audio1_mux", 0, 1106 clk_base + AUDIO_SYNC_CLK_I2S1, 4, 1107 CLK_GATE_SET_TO_DISABLE, NULL); 1108 clk_register_clkdev(clk, "audio1", NULL); 1109 clks[audio1] = clk; 1110 1111 /* audio2 */ 1112 clk = clk_register_mux(NULL, "audio2_mux", mux_audio_sync_clk, 1113 ARRAY_SIZE(mux_audio_sync_clk), 1114 CLK_SET_RATE_NO_REPARENT, 1115 clk_base + AUDIO_SYNC_CLK_I2S2, 0, 3, 0, NULL); 1116 clk = clk_register_gate(NULL, "audio2", "audio2_mux", 0, 1117 clk_base + AUDIO_SYNC_CLK_I2S2, 4, 1118 CLK_GATE_SET_TO_DISABLE, NULL); 1119 clk_register_clkdev(clk, "audio2", NULL); 1120 clks[audio2] = clk; 1121 1122 /* audio3 */ 1123 clk = clk_register_mux(NULL, "audio3_mux", mux_audio_sync_clk, 1124 ARRAY_SIZE(mux_audio_sync_clk), 1125 CLK_SET_RATE_NO_REPARENT, 1126 clk_base + AUDIO_SYNC_CLK_I2S3, 0, 3, 0, NULL); 1127 clk = clk_register_gate(NULL, "audio3", "audio3_mux", 0, 1128 clk_base + AUDIO_SYNC_CLK_I2S3, 4, 1129 CLK_GATE_SET_TO_DISABLE, NULL); 1130 clk_register_clkdev(clk, "audio3", NULL); 1131 clks[audio3] = clk; 1132 1133 /* audio4 */ 1134 clk = clk_register_mux(NULL, "audio4_mux", mux_audio_sync_clk, 1135 ARRAY_SIZE(mux_audio_sync_clk), 1136 CLK_SET_RATE_NO_REPARENT, 1137 clk_base + AUDIO_SYNC_CLK_I2S4, 0, 3, 0, NULL); 1138 clk = clk_register_gate(NULL, "audio4", "audio4_mux", 0, 1139 clk_base + AUDIO_SYNC_CLK_I2S4, 4, 1140 CLK_GATE_SET_TO_DISABLE, NULL); 1141 clk_register_clkdev(clk, "audio4", NULL); 1142 clks[audio4] = clk; 1143 1144 /* spdif */ 1145 clk = clk_register_mux(NULL, "spdif_mux", mux_audio_sync_clk, 1146 ARRAY_SIZE(mux_audio_sync_clk), 1147 CLK_SET_RATE_NO_REPARENT, 1148 clk_base + AUDIO_SYNC_CLK_SPDIF, 0, 3, 0, NULL); 1149 clk = clk_register_gate(NULL, "spdif", "spdif_mux", 0, 1150 clk_base + AUDIO_SYNC_CLK_SPDIF, 4, 1151 CLK_GATE_SET_TO_DISABLE, NULL); 1152 clk_register_clkdev(clk, "spdif", NULL); 1153 clks[spdif] = clk; 1154 1155 /* audio0_2x */ 1156 clk = clk_register_fixed_factor(NULL, "audio0_doubler", "audio0", 1157 CLK_SET_RATE_PARENT, 2, 1); 1158 clk = tegra_clk_register_divider("audio0_div", "audio0_doubler", 1159 clk_base + AUDIO_SYNC_DOUBLER, 0, 0, 24, 1, 0, 1160 &clk_doubler_lock); 1161 clk = tegra_clk_register_periph_gate("audio0_2x", "audio0_div", 1162 TEGRA_PERIPH_NO_RESET, clk_base, 1163 CLK_SET_RATE_PARENT, 113, &periph_v_regs, 1164 periph_clk_enb_refcnt); 1165 clk_register_clkdev(clk, "audio0_2x", NULL); 1166 clks[audio0_2x] = clk; 1167 1168 /* audio1_2x */ 1169 clk = clk_register_fixed_factor(NULL, "audio1_doubler", "audio1", 1170 CLK_SET_RATE_PARENT, 2, 1); 1171 clk = tegra_clk_register_divider("audio1_div", "audio1_doubler", 1172 clk_base + AUDIO_SYNC_DOUBLER, 0, 0, 25, 1, 0, 1173 &clk_doubler_lock); 1174 clk = tegra_clk_register_periph_gate("audio1_2x", "audio1_div", 1175 TEGRA_PERIPH_NO_RESET, clk_base, 1176 CLK_SET_RATE_PARENT, 114, &periph_v_regs, 1177 periph_clk_enb_refcnt); 1178 clk_register_clkdev(clk, "audio1_2x", NULL); 1179 clks[audio1_2x] = clk; 1180 1181 /* audio2_2x */ 1182 clk = clk_register_fixed_factor(NULL, "audio2_doubler", "audio2", 1183 CLK_SET_RATE_PARENT, 2, 1); 1184 clk = tegra_clk_register_divider("audio2_div", "audio2_doubler", 1185 clk_base + AUDIO_SYNC_DOUBLER, 0, 0, 26, 1, 0, 1186 &clk_doubler_lock); 1187 clk = tegra_clk_register_periph_gate("audio2_2x", "audio2_div", 1188 TEGRA_PERIPH_NO_RESET, clk_base, 1189 CLK_SET_RATE_PARENT, 115, &periph_v_regs, 1190 periph_clk_enb_refcnt); 1191 clk_register_clkdev(clk, "audio2_2x", NULL); 1192 clks[audio2_2x] = clk; 1193 1194 /* audio3_2x */ 1195 clk = clk_register_fixed_factor(NULL, "audio3_doubler", "audio3", 1196 CLK_SET_RATE_PARENT, 2, 1); 1197 clk = tegra_clk_register_divider("audio3_div", "audio3_doubler", 1198 clk_base + AUDIO_SYNC_DOUBLER, 0, 0, 27, 1, 0, 1199 &clk_doubler_lock); 1200 clk = tegra_clk_register_periph_gate("audio3_2x", "audio3_div", 1201 TEGRA_PERIPH_NO_RESET, clk_base, 1202 CLK_SET_RATE_PARENT, 116, &periph_v_regs, 1203 periph_clk_enb_refcnt); 1204 clk_register_clkdev(clk, "audio3_2x", NULL); 1205 clks[audio3_2x] = clk; 1206 1207 /* audio4_2x */ 1208 clk = clk_register_fixed_factor(NULL, "audio4_doubler", "audio4", 1209 CLK_SET_RATE_PARENT, 2, 1); 1210 clk = tegra_clk_register_divider("audio4_div", "audio4_doubler", 1211 clk_base + AUDIO_SYNC_DOUBLER, 0, 0, 28, 1, 0, 1212 &clk_doubler_lock); 1213 clk = tegra_clk_register_periph_gate("audio4_2x", "audio4_div", 1214 TEGRA_PERIPH_NO_RESET, clk_base, 1215 CLK_SET_RATE_PARENT, 117, &periph_v_regs, 1216 periph_clk_enb_refcnt); 1217 clk_register_clkdev(clk, "audio4_2x", NULL); 1218 clks[audio4_2x] = clk; 1219 1220 /* spdif_2x */ 1221 clk = clk_register_fixed_factor(NULL, "spdif_doubler", "spdif", 1222 CLK_SET_RATE_PARENT, 2, 1); 1223 clk = tegra_clk_register_divider("spdif_div", "spdif_doubler", 1224 clk_base + AUDIO_SYNC_DOUBLER, 0, 0, 29, 1, 0, 1225 &clk_doubler_lock); 1226 clk = tegra_clk_register_periph_gate("spdif_2x", "spdif_div", 1227 TEGRA_PERIPH_NO_RESET, clk_base, 1228 CLK_SET_RATE_PARENT, 118, &periph_v_regs, 1229 periph_clk_enb_refcnt); 1230 clk_register_clkdev(clk, "spdif_2x", NULL); 1231 clks[spdif_2x] = clk; 1232} 1233 1234static void __init tegra30_pmc_clk_init(void) 1235{ 1236 struct clk *clk; 1237 1238 /* clk_out_1 */ 1239 clk = clk_register_mux(NULL, "clk_out_1_mux", clk_out1_parents, 1240 ARRAY_SIZE(clk_out1_parents), 1241 CLK_SET_RATE_NO_REPARENT, 1242 pmc_base + PMC_CLK_OUT_CNTRL, 6, 3, 0, 1243 &clk_out_lock); 1244 clks[clk_out_1_mux] = clk; 1245 clk = clk_register_gate(NULL, "clk_out_1", "clk_out_1_mux", 0, 1246 pmc_base + PMC_CLK_OUT_CNTRL, 2, 0, 1247 &clk_out_lock); 1248 clk_register_clkdev(clk, "extern1", "clk_out_1"); 1249 clks[clk_out_1] = clk; 1250 1251 /* clk_out_2 */ 1252 clk = clk_register_mux(NULL, "clk_out_2_mux", clk_out2_parents, 1253 ARRAY_SIZE(clk_out2_parents), 1254 CLK_SET_RATE_NO_REPARENT, 1255 pmc_base + PMC_CLK_OUT_CNTRL, 14, 3, 0, 1256 &clk_out_lock); 1257 clk = clk_register_gate(NULL, "clk_out_2", "clk_out_2_mux", 0, 1258 pmc_base + PMC_CLK_OUT_CNTRL, 10, 0, 1259 &clk_out_lock); 1260 clk_register_clkdev(clk, "extern2", "clk_out_2"); 1261 clks[clk_out_2] = clk; 1262 1263 /* clk_out_3 */ 1264 clk = clk_register_mux(NULL, "clk_out_3_mux", clk_out3_parents, 1265 ARRAY_SIZE(clk_out3_parents), 1266 CLK_SET_RATE_NO_REPARENT, 1267 pmc_base + PMC_CLK_OUT_CNTRL, 22, 3, 0, 1268 &clk_out_lock); 1269 clk = clk_register_gate(NULL, "clk_out_3", "clk_out_3_mux", 0, 1270 pmc_base + PMC_CLK_OUT_CNTRL, 18, 0, 1271 &clk_out_lock); 1272 clk_register_clkdev(clk, "extern3", "clk_out_3"); 1273 clks[clk_out_3] = clk; 1274 1275 /* blink */ 1276 writel_relaxed(0, pmc_base + PMC_BLINK_TIMER); 1277 clk = clk_register_gate(NULL, "blink_override", "clk_32k", 0, 1278 pmc_base + PMC_DPD_PADS_ORIDE, 1279 PMC_DPD_PADS_ORIDE_BLINK_ENB, 0, NULL); 1280 clk = clk_register_gate(NULL, "blink", "blink_override", 0, 1281 pmc_base + PMC_CTRL, 1282 PMC_CTRL_BLINK_ENB, 0, NULL); 1283 clk_register_clkdev(clk, "blink", NULL); 1284 clks[blink] = clk; 1285 1286} 1287 1288static const char *cclk_g_parents[] = { "clk_m", "pll_c", "clk_32k", "pll_m", 1289 "pll_p_cclkg", "pll_p_out4_cclkg", 1290 "pll_p_out3_cclkg", "unused", "pll_x" }; 1291static const char *cclk_lp_parents[] = { "clk_m", "pll_c", "clk_32k", "pll_m", 1292 "pll_p_cclklp", "pll_p_out4_cclklp", 1293 "pll_p_out3_cclklp", "unused", "pll_x", 1294 "pll_x_out0" }; 1295static const char *sclk_parents[] = { "clk_m", "pll_c_out1", "pll_p_out4", 1296 "pll_p_out3", "pll_p_out2", "unused", 1297 "clk_32k", "pll_m_out1" }; 1298 1299static void __init tegra30_super_clk_init(void) 1300{ 1301 struct clk *clk; 1302 1303 /* 1304 * Clock input to cclk_g divided from pll_p using 1305 * U71 divider of cclk_g. 1306 */ 1307 clk = tegra_clk_register_divider("pll_p_cclkg", "pll_p", 1308 clk_base + SUPER_CCLKG_DIVIDER, 0, 1309 TEGRA_DIVIDER_INT, 16, 8, 1, NULL); 1310 clk_register_clkdev(clk, "pll_p_cclkg", NULL); 1311 1312 /* 1313 * Clock input to cclk_g divided from pll_p_out3 using 1314 * U71 divider of cclk_g. 1315 */ 1316 clk = tegra_clk_register_divider("pll_p_out3_cclkg", "pll_p_out3", 1317 clk_base + SUPER_CCLKG_DIVIDER, 0, 1318 TEGRA_DIVIDER_INT, 16, 8, 1, NULL); 1319 clk_register_clkdev(clk, "pll_p_out3_cclkg", NULL); 1320 1321 /* 1322 * Clock input to cclk_g divided from pll_p_out4 using 1323 * U71 divider of cclk_g. 1324 */ 1325 clk = tegra_clk_register_divider("pll_p_out4_cclkg", "pll_p_out4", 1326 clk_base + SUPER_CCLKG_DIVIDER, 0, 1327 TEGRA_DIVIDER_INT, 16, 8, 1, NULL); 1328 clk_register_clkdev(clk, "pll_p_out4_cclkg", NULL); 1329 1330 /* CCLKG */ 1331 clk = tegra_clk_register_super_mux("cclk_g", cclk_g_parents, 1332 ARRAY_SIZE(cclk_g_parents), 1333 CLK_SET_RATE_PARENT, 1334 clk_base + CCLKG_BURST_POLICY, 1335 0, 4, 0, 0, NULL); 1336 clk_register_clkdev(clk, "cclk_g", NULL); 1337 clks[cclk_g] = clk; 1338 1339 /* 1340 * Clock input to cclk_lp divided from pll_p using 1341 * U71 divider of cclk_lp. 1342 */ 1343 clk = tegra_clk_register_divider("pll_p_cclklp", "pll_p", 1344 clk_base + SUPER_CCLKLP_DIVIDER, 0, 1345 TEGRA_DIVIDER_INT, 16, 8, 1, NULL); 1346 clk_register_clkdev(clk, "pll_p_cclklp", NULL); 1347 1348 /* 1349 * Clock input to cclk_lp divided from pll_p_out3 using 1350 * U71 divider of cclk_lp. 1351 */ 1352 clk = tegra_clk_register_divider("pll_p_out3_cclklp", "pll_p_out3", 1353 clk_base + SUPER_CCLKG_DIVIDER, 0, 1354 TEGRA_DIVIDER_INT, 16, 8, 1, NULL); 1355 clk_register_clkdev(clk, "pll_p_out3_cclklp", NULL); 1356 1357 /* 1358 * Clock input to cclk_lp divided from pll_p_out4 using 1359 * U71 divider of cclk_lp. 1360 */ 1361 clk = tegra_clk_register_divider("pll_p_out4_cclklp", "pll_p_out4", 1362 clk_base + SUPER_CCLKLP_DIVIDER, 0, 1363 TEGRA_DIVIDER_INT, 16, 8, 1, NULL); 1364 clk_register_clkdev(clk, "pll_p_out4_cclklp", NULL); 1365 1366 /* CCLKLP */ 1367 clk = tegra_clk_register_super_mux("cclk_lp", cclk_lp_parents, 1368 ARRAY_SIZE(cclk_lp_parents), 1369 CLK_SET_RATE_PARENT, 1370 clk_base + CCLKLP_BURST_POLICY, 1371 TEGRA_DIVIDER_2, 4, 8, 9, 1372 NULL); 1373 clk_register_clkdev(clk, "cclk_lp", NULL); 1374 clks[cclk_lp] = clk; 1375 1376 /* SCLK */ 1377 clk = tegra_clk_register_super_mux("sclk", sclk_parents, 1378 ARRAY_SIZE(sclk_parents), 1379 CLK_SET_RATE_PARENT, 1380 clk_base + SCLK_BURST_POLICY, 1381 0, 4, 0, 0, NULL); 1382 clk_register_clkdev(clk, "sclk", NULL); 1383 clks[sclk] = clk; 1384 1385 /* HCLK */ 1386 clk = clk_register_divider(NULL, "hclk_div", "sclk", 0, 1387 clk_base + SYSTEM_CLK_RATE, 4, 2, 0, 1388 &sysrate_lock); 1389 clk = clk_register_gate(NULL, "hclk", "hclk_div", CLK_SET_RATE_PARENT, 1390 clk_base + SYSTEM_CLK_RATE, 7, 1391 CLK_GATE_SET_TO_DISABLE, &sysrate_lock); 1392 clk_register_clkdev(clk, "hclk", NULL); 1393 clks[hclk] = clk; 1394 1395 /* PCLK */ 1396 clk = clk_register_divider(NULL, "pclk_div", "hclk", 0, 1397 clk_base + SYSTEM_CLK_RATE, 0, 2, 0, 1398 &sysrate_lock); 1399 clk = clk_register_gate(NULL, "pclk", "pclk_div", CLK_SET_RATE_PARENT, 1400 clk_base + SYSTEM_CLK_RATE, 3, 1401 CLK_GATE_SET_TO_DISABLE, &sysrate_lock); 1402 clk_register_clkdev(clk, "pclk", NULL); 1403 clks[pclk] = clk; 1404 1405 /* twd */ 1406 clk = clk_register_fixed_factor(NULL, "twd", "cclk_g", 1407 CLK_SET_RATE_PARENT, 1, 2); 1408 clk_register_clkdev(clk, "twd", NULL); 1409 clks[twd] = clk; 1410} 1411 1412static const char *mux_pllacp_clkm[] = { "pll_a_out0", "unused", "pll_p", 1413 "clk_m" }; 1414static const char *mux_pllpcm_clkm[] = { "pll_p", "pll_c", "pll_m", "clk_m" }; 1415static const char *mux_pllmcp_clkm[] = { "pll_m", "pll_c", "pll_p", "clk_m" }; 1416static const char *i2s0_parents[] = { "pll_a_out0", "audio0_2x", "pll_p", 1417 "clk_m" }; 1418static const char *i2s1_parents[] = { "pll_a_out0", "audio1_2x", "pll_p", 1419 "clk_m" }; 1420static const char *i2s2_parents[] = { "pll_a_out0", "audio2_2x", "pll_p", 1421 "clk_m" }; 1422static const char *i2s3_parents[] = { "pll_a_out0", "audio3_2x", "pll_p", 1423 "clk_m" }; 1424static const char *i2s4_parents[] = { "pll_a_out0", "audio4_2x", "pll_p", 1425 "clk_m" }; 1426static const char *spdif_out_parents[] = { "pll_a_out0", "spdif_2x", "pll_p", 1427 "clk_m" }; 1428static const char *spdif_in_parents[] = { "pll_p", "pll_c", "pll_m" }; 1429static const char *mux_pllpc_clk32k_clkm[] = { "pll_p", "pll_c", "clk_32k", 1430 "clk_m" }; 1431static const char *mux_pllpc_clkm_clk32k[] = { "pll_p", "pll_c", "clk_m", 1432 "clk_32k" }; 1433static const char *mux_pllmcpa[] = { "pll_m", "pll_c", "pll_p", "pll_a_out0" }; 1434static const char *mux_pllpdc_clkm[] = { "pll_p", "pll_d_out0", "pll_c", 1435 "clk_m" }; 1436static const char *mux_pllp_clkm[] = { "pll_p", "unused", "unused", "clk_m" }; 1437static const char *mux_pllpmdacd2_clkm[] = { "pll_p", "pll_m", "pll_d_out0", 1438 "pll_a_out0", "pll_c", 1439 "pll_d2_out0", "clk_m" }; 1440static const char *mux_plla_clk32k_pllp_clkm_plle[] = { "pll_a_out0", 1441 "clk_32k", "pll_p", 1442 "clk_m", "pll_e" }; 1443static const char *mux_plld_out0_plld2_out0[] = { "pll_d_out0", 1444 "pll_d2_out0" }; 1445 1446static struct tegra_periph_init_data tegra_periph_clk_list[] = { 1447 TEGRA_INIT_DATA_MUX("i2s0", NULL, "tegra30-i2s.0", i2s0_parents, CLK_SOURCE_I2S0, 30, &periph_l_regs, TEGRA_PERIPH_ON_APB, i2s0), 1448 TEGRA_INIT_DATA_MUX("i2s1", NULL, "tegra30-i2s.1", i2s1_parents, CLK_SOURCE_I2S1, 11, &periph_l_regs, TEGRA_PERIPH_ON_APB, i2s1), 1449 TEGRA_INIT_DATA_MUX("i2s2", NULL, "tegra30-i2s.2", i2s2_parents, CLK_SOURCE_I2S2, 18, &periph_l_regs, TEGRA_PERIPH_ON_APB, i2s2), 1450 TEGRA_INIT_DATA_MUX("i2s3", NULL, "tegra30-i2s.3", i2s3_parents, CLK_SOURCE_I2S3, 101, &periph_v_regs, TEGRA_PERIPH_ON_APB, i2s3), 1451 TEGRA_INIT_DATA_MUX("i2s4", NULL, "tegra30-i2s.4", i2s4_parents, CLK_SOURCE_I2S4, 102, &periph_v_regs, TEGRA_PERIPH_ON_APB, i2s4), 1452 TEGRA_INIT_DATA_MUX("spdif_out", "spdif_out", "tegra30-spdif", spdif_out_parents, CLK_SOURCE_SPDIF_OUT, 10, &periph_l_regs, TEGRA_PERIPH_ON_APB, spdif_out), 1453 TEGRA_INIT_DATA_MUX("spdif_in", "spdif_in", "tegra30-spdif", spdif_in_parents, CLK_SOURCE_SPDIF_IN, 10, &periph_l_regs, TEGRA_PERIPH_ON_APB, spdif_in), 1454 TEGRA_INIT_DATA_MUX("d_audio", "d_audio", "tegra30-ahub", mux_pllacp_clkm, CLK_SOURCE_D_AUDIO, 106, &periph_v_regs, 0, d_audio), 1455 TEGRA_INIT_DATA_MUX("dam0", NULL, "tegra30-dam.0", mux_pllacp_clkm, CLK_SOURCE_DAM0, 108, &periph_v_regs, 0, dam0), 1456 TEGRA_INIT_DATA_MUX("dam1", NULL, "tegra30-dam.1", mux_pllacp_clkm, CLK_SOURCE_DAM1, 109, &periph_v_regs, 0, dam1), 1457 TEGRA_INIT_DATA_MUX("dam2", NULL, "tegra30-dam.2", mux_pllacp_clkm, CLK_SOURCE_DAM2, 110, &periph_v_regs, 0, dam2), 1458 TEGRA_INIT_DATA_MUX("hda", "hda", "tegra30-hda", mux_pllpcm_clkm, CLK_SOURCE_HDA, 125, &periph_v_regs, 0, hda), 1459 TEGRA_INIT_DATA_MUX("hda2codec_2x", "hda2codec", "tegra30-hda", mux_pllpcm_clkm, CLK_SOURCE_HDA2CODEC_2X, 111, &periph_v_regs, 0, hda2codec_2x), 1460 TEGRA_INIT_DATA_MUX("sbc1", NULL, "spi_tegra.0", mux_pllpcm_clkm, CLK_SOURCE_SBC1, 41, &periph_h_regs, TEGRA_PERIPH_ON_APB, sbc1), 1461 TEGRA_INIT_DATA_MUX("sbc2", NULL, "spi_tegra.1", mux_pllpcm_clkm, CLK_SOURCE_SBC2, 44, &periph_h_regs, TEGRA_PERIPH_ON_APB, sbc2), 1462 TEGRA_INIT_DATA_MUX("sbc3", NULL, "spi_tegra.2", mux_pllpcm_clkm, CLK_SOURCE_SBC3, 46, &periph_h_regs, TEGRA_PERIPH_ON_APB, sbc3), 1463 TEGRA_INIT_DATA_MUX("sbc4", NULL, "spi_tegra.3", mux_pllpcm_clkm, CLK_SOURCE_SBC4, 68, &periph_u_regs, TEGRA_PERIPH_ON_APB, sbc4), 1464 TEGRA_INIT_DATA_MUX("sbc5", NULL, "spi_tegra.4", mux_pllpcm_clkm, CLK_SOURCE_SBC5, 104, &periph_v_regs, TEGRA_PERIPH_ON_APB, sbc5), 1465 TEGRA_INIT_DATA_MUX("sbc6", NULL, "spi_tegra.5", mux_pllpcm_clkm, CLK_SOURCE_SBC6, 105, &periph_v_regs, TEGRA_PERIPH_ON_APB, sbc6), 1466 TEGRA_INIT_DATA_MUX("sata_oob", NULL, "tegra_sata_oob", mux_pllpcm_clkm, CLK_SOURCE_SATA_OOB, 123, &periph_v_regs, TEGRA_PERIPH_ON_APB, sata_oob), 1467 TEGRA_INIT_DATA_MUX("sata", NULL, "tegra_sata", mux_pllpcm_clkm, CLK_SOURCE_SATA, 124, &periph_v_regs, TEGRA_PERIPH_ON_APB, sata), 1468 TEGRA_INIT_DATA_MUX("ndflash", NULL, "tegra_nand", mux_pllpcm_clkm, CLK_SOURCE_NDFLASH, 13, &periph_l_regs, TEGRA_PERIPH_ON_APB, ndflash), 1469 TEGRA_INIT_DATA_MUX("ndspeed", NULL, "tegra_nand_speed", mux_pllpcm_clkm, CLK_SOURCE_NDSPEED, 80, &periph_u_regs, TEGRA_PERIPH_ON_APB, ndspeed), 1470 TEGRA_INIT_DATA_MUX("vfir", NULL, "vfir", mux_pllpcm_clkm, CLK_SOURCE_VFIR, 7, &periph_l_regs, TEGRA_PERIPH_ON_APB, vfir), 1471 TEGRA_INIT_DATA_MUX("csite", NULL, "csite", mux_pllpcm_clkm, CLK_SOURCE_CSITE, 73, &periph_u_regs, TEGRA_PERIPH_ON_APB, csite), 1472 TEGRA_INIT_DATA_MUX("la", NULL, "la", mux_pllpcm_clkm, CLK_SOURCE_LA, 76, &periph_u_regs, TEGRA_PERIPH_ON_APB, la), 1473 TEGRA_INIT_DATA_MUX("owr", NULL, "tegra_w1", mux_pllpcm_clkm, CLK_SOURCE_OWR, 71, &periph_u_regs, TEGRA_PERIPH_ON_APB, owr), 1474 TEGRA_INIT_DATA_MUX("mipi", NULL, "mipi", mux_pllpcm_clkm, CLK_SOURCE_MIPI, 50, &periph_h_regs, TEGRA_PERIPH_ON_APB, mipi), 1475 TEGRA_INIT_DATA_MUX("tsensor", NULL, "tegra-tsensor", mux_pllpc_clkm_clk32k, CLK_SOURCE_TSENSOR, 100, &periph_v_regs, TEGRA_PERIPH_ON_APB, tsensor), 1476 TEGRA_INIT_DATA_MUX("i2cslow", NULL, "i2cslow", mux_pllpc_clk32k_clkm, CLK_SOURCE_I2CSLOW, 81, &periph_u_regs, TEGRA_PERIPH_ON_APB, i2cslow), 1477 TEGRA_INIT_DATA_INT("vde", NULL, "vde", mux_pllpcm_clkm, CLK_SOURCE_VDE, 61, &periph_h_regs, 0, vde), 1478 TEGRA_INIT_DATA_INT("vi", "vi", "tegra_camera", mux_pllmcpa, CLK_SOURCE_VI, 20, &periph_l_regs, 0, vi), 1479 TEGRA_INIT_DATA_INT("epp", NULL, "epp", mux_pllmcpa, CLK_SOURCE_EPP, 19, &periph_l_regs, 0, epp), 1480 TEGRA_INIT_DATA_INT("mpe", NULL, "mpe", mux_pllmcpa, CLK_SOURCE_MPE, 60, &periph_h_regs, 0, mpe), 1481 TEGRA_INIT_DATA_INT("host1x", NULL, "host1x", mux_pllmcpa, CLK_SOURCE_HOST1X, 28, &periph_l_regs, 0, host1x), 1482 TEGRA_INIT_DATA_INT("3d", NULL, "3d", mux_pllmcpa, CLK_SOURCE_3D, 24, &periph_l_regs, TEGRA_PERIPH_MANUAL_RESET, gr3d), 1483 TEGRA_INIT_DATA_INT("3d2", NULL, "3d2", mux_pllmcpa, CLK_SOURCE_3D2, 98, &periph_v_regs, TEGRA_PERIPH_MANUAL_RESET, gr3d2), 1484 TEGRA_INIT_DATA_INT("2d", NULL, "2d", mux_pllmcpa, CLK_SOURCE_2D, 21, &periph_l_regs, 0, gr2d), 1485 TEGRA_INIT_DATA_INT("se", NULL, "se", mux_pllpcm_clkm, CLK_SOURCE_SE, 127, &periph_v_regs, 0, se), 1486 TEGRA_INIT_DATA_MUX("mselect", NULL, "mselect", mux_pllp_clkm, CLK_SOURCE_MSELECT, 99, &periph_v_regs, 0, mselect), 1487 TEGRA_INIT_DATA_MUX("nor", NULL, "tegra-nor", mux_pllpcm_clkm, CLK_SOURCE_NOR, 42, &periph_h_regs, 0, nor), 1488 TEGRA_INIT_DATA_MUX("sdmmc1", NULL, "sdhci-tegra.0", mux_pllpcm_clkm, CLK_SOURCE_SDMMC1, 14, &periph_l_regs, 0, sdmmc1), 1489 TEGRA_INIT_DATA_MUX("sdmmc2", NULL, "sdhci-tegra.1", mux_pllpcm_clkm, CLK_SOURCE_SDMMC2, 9, &periph_l_regs, 0, sdmmc2), 1490 TEGRA_INIT_DATA_MUX("sdmmc3", NULL, "sdhci-tegra.2", mux_pllpcm_clkm, CLK_SOURCE_SDMMC3, 69, &periph_u_regs, 0, sdmmc3), 1491 TEGRA_INIT_DATA_MUX("sdmmc4", NULL, "sdhci-tegra.3", mux_pllpcm_clkm, CLK_SOURCE_SDMMC4, 15, &periph_l_regs, 0, sdmmc4), 1492 TEGRA_INIT_DATA_MUX("cve", NULL, "cve", mux_pllpdc_clkm, CLK_SOURCE_CVE, 49, &periph_h_regs, 0, cve), 1493 TEGRA_INIT_DATA_MUX("tvo", NULL, "tvo", mux_pllpdc_clkm, CLK_SOURCE_TVO, 49, &periph_h_regs, 0, tvo), 1494 TEGRA_INIT_DATA_MUX("tvdac", NULL, "tvdac", mux_pllpdc_clkm, CLK_SOURCE_TVDAC, 53, &periph_h_regs, 0, tvdac), 1495 TEGRA_INIT_DATA_MUX("actmon", NULL, "actmon", mux_pllpc_clk32k_clkm, CLK_SOURCE_ACTMON, 119, &periph_v_regs, 0, actmon), 1496 TEGRA_INIT_DATA_MUX("vi_sensor", "vi_sensor", "tegra_camera", mux_pllmcpa, CLK_SOURCE_VI_SENSOR, 20, &periph_l_regs, TEGRA_PERIPH_NO_RESET, vi_sensor), 1497 TEGRA_INIT_DATA_DIV16("i2c1", "div-clk", "tegra-i2c.0", mux_pllp_clkm, CLK_SOURCE_I2C1, 12, &periph_l_regs, TEGRA_PERIPH_ON_APB, i2c1), 1498 TEGRA_INIT_DATA_DIV16("i2c2", "div-clk", "tegra-i2c.1", mux_pllp_clkm, CLK_SOURCE_I2C2, 54, &periph_h_regs, TEGRA_PERIPH_ON_APB, i2c2), 1499 TEGRA_INIT_DATA_DIV16("i2c3", "div-clk", "tegra-i2c.2", mux_pllp_clkm, CLK_SOURCE_I2C3, 67, &periph_u_regs, TEGRA_PERIPH_ON_APB, i2c3), 1500 TEGRA_INIT_DATA_DIV16("i2c4", "div-clk", "tegra-i2c.3", mux_pllp_clkm, CLK_SOURCE_I2C4, 103, &periph_v_regs, TEGRA_PERIPH_ON_APB, i2c4), 1501 TEGRA_INIT_DATA_DIV16("i2c5", "div-clk", "tegra-i2c.4", mux_pllp_clkm, CLK_SOURCE_I2C5, 47, &periph_h_regs, TEGRA_PERIPH_ON_APB, i2c5), 1502 TEGRA_INIT_DATA_UART("uarta", NULL, "tegra_uart.0", mux_pllpcm_clkm, CLK_SOURCE_UARTA, 6, &periph_l_regs, uarta), 1503 TEGRA_INIT_DATA_UART("uartb", NULL, "tegra_uart.1", mux_pllpcm_clkm, CLK_SOURCE_UARTB, 7, &periph_l_regs, uartb), 1504 TEGRA_INIT_DATA_UART("uartc", NULL, "tegra_uart.2", mux_pllpcm_clkm, CLK_SOURCE_UARTC, 55, &periph_h_regs, uartc), 1505 TEGRA_INIT_DATA_UART("uartd", NULL, "tegra_uart.3", mux_pllpcm_clkm, CLK_SOURCE_UARTD, 65, &periph_u_regs, uartd), 1506 TEGRA_INIT_DATA_UART("uarte", NULL, "tegra_uart.4", mux_pllpcm_clkm, CLK_SOURCE_UARTE, 66, &periph_u_regs, uarte), 1507 TEGRA_INIT_DATA_MUX8("hdmi", NULL, "hdmi", mux_pllpmdacd2_clkm, CLK_SOURCE_HDMI, 51, &periph_h_regs, 0, hdmi), 1508 TEGRA_INIT_DATA_MUX8("extern1", NULL, "extern1", mux_plla_clk32k_pllp_clkm_plle, CLK_SOURCE_EXTERN1, 120, &periph_v_regs, 0, extern1), 1509 TEGRA_INIT_DATA_MUX8("extern2", NULL, "extern2", mux_plla_clk32k_pllp_clkm_plle, CLK_SOURCE_EXTERN2, 121, &periph_v_regs, 0, extern2), 1510 TEGRA_INIT_DATA_MUX8("extern3", NULL, "extern3", mux_plla_clk32k_pllp_clkm_plle, CLK_SOURCE_EXTERN3, 122, &periph_v_regs, 0, extern3), 1511 TEGRA_INIT_DATA("pwm", NULL, "pwm", mux_pllpc_clk32k_clkm, CLK_SOURCE_PWM, 28, 2, 0, 0, 8, 1, 0, &periph_l_regs, 17, periph_clk_enb_refcnt, 0, pwm), 1512}; 1513 1514static struct tegra_periph_init_data tegra_periph_nodiv_clk_list[] = { 1515 TEGRA_INIT_DATA_NODIV("disp1", NULL, "tegradc.0", mux_pllpmdacd2_clkm, CLK_SOURCE_DISP1, 29, 3, 27, &periph_l_regs, 0, disp1), 1516 TEGRA_INIT_DATA_NODIV("disp2", NULL, "tegradc.1", mux_pllpmdacd2_clkm, CLK_SOURCE_DISP2, 29, 3, 26, &periph_l_regs, 0, disp2), 1517 TEGRA_INIT_DATA_NODIV("dsib", NULL, "tegradc.1", mux_plld_out0_plld2_out0, CLK_SOURCE_DSIB, 25, 1, 82, &periph_u_regs, 0, dsib), 1518}; 1519 1520static void __init tegra30_periph_clk_init(void) 1521{ 1522 struct tegra_periph_init_data *data; 1523 struct clk *clk; 1524 int i; 1525 1526 /* apbdma */ 1527 clk = tegra_clk_register_periph_gate("apbdma", "clk_m", 0, clk_base, 0, 34, 1528 &periph_h_regs, periph_clk_enb_refcnt); 1529 clk_register_clkdev(clk, NULL, "tegra-apbdma"); 1530 clks[apbdma] = clk; 1531 1532 /* rtc */ 1533 clk = tegra_clk_register_periph_gate("rtc", "clk_32k", 1534 TEGRA_PERIPH_NO_RESET | TEGRA_PERIPH_ON_APB, 1535 clk_base, 0, 4, &periph_l_regs, 1536 periph_clk_enb_refcnt); 1537 clk_register_clkdev(clk, NULL, "rtc-tegra"); 1538 clks[rtc] = clk; 1539 1540 /* timer */ 1541 clk = tegra_clk_register_periph_gate("timer", "clk_m", 0, clk_base, 0, 1542 5, &periph_l_regs, periph_clk_enb_refcnt); 1543 clk_register_clkdev(clk, NULL, "timer"); 1544 clks[timer] = clk; 1545 1546 /* kbc */ 1547 clk = tegra_clk_register_periph_gate("kbc", "clk_32k", 1548 TEGRA_PERIPH_NO_RESET | TEGRA_PERIPH_ON_APB, 1549 clk_base, 0, 36, &periph_h_regs, 1550 periph_clk_enb_refcnt); 1551 clk_register_clkdev(clk, NULL, "tegra-kbc"); 1552 clks[kbc] = clk; 1553 1554 /* csus */ 1555 clk = tegra_clk_register_periph_gate("csus", "clk_m", 1556 TEGRA_PERIPH_NO_RESET | TEGRA_PERIPH_ON_APB, 1557 clk_base, 0, 92, &periph_u_regs, 1558 periph_clk_enb_refcnt); 1559 clk_register_clkdev(clk, "csus", "tengra_camera"); 1560 clks[csus] = clk; 1561 1562 /* vcp */ 1563 clk = tegra_clk_register_periph_gate("vcp", "clk_m", 0, clk_base, 0, 29, 1564 &periph_l_regs, periph_clk_enb_refcnt); 1565 clk_register_clkdev(clk, "vcp", "tegra-avp"); 1566 clks[vcp] = clk; 1567 1568 /* bsea */ 1569 clk = tegra_clk_register_periph_gate("bsea", "clk_m", 0, clk_base, 0, 1570 62, &periph_h_regs, periph_clk_enb_refcnt); 1571 clk_register_clkdev(clk, "bsea", "tegra-avp"); 1572 clks[bsea] = clk; 1573 1574 /* bsev */ 1575 clk = tegra_clk_register_periph_gate("bsev", "clk_m", 0, clk_base, 0, 1576 63, &periph_h_regs, periph_clk_enb_refcnt); 1577 clk_register_clkdev(clk, "bsev", "tegra-aes"); 1578 clks[bsev] = clk; 1579 1580 /* usbd */ 1581 clk = tegra_clk_register_periph_gate("usbd", "clk_m", 0, clk_base, 0, 1582 22, &periph_l_regs, periph_clk_enb_refcnt); 1583 clk_register_clkdev(clk, NULL, "fsl-tegra-udc"); 1584 clks[usbd] = clk; 1585 1586 /* usb2 */ 1587 clk = tegra_clk_register_periph_gate("usb2", "clk_m", 0, clk_base, 0, 1588 58, &periph_h_regs, periph_clk_enb_refcnt); 1589 clk_register_clkdev(clk, NULL, "tegra-ehci.1"); 1590 clks[usb2] = clk; 1591 1592 /* usb3 */ 1593 clk = tegra_clk_register_periph_gate("usb3", "clk_m", 0, clk_base, 0, 1594 59, &periph_h_regs, periph_clk_enb_refcnt); 1595 clk_register_clkdev(clk, NULL, "tegra-ehci.2"); 1596 clks[usb3] = clk; 1597 1598 /* dsia */ 1599 clk = tegra_clk_register_periph_gate("dsia", "pll_d_out0", 0, clk_base, 1600 0, 48, &periph_h_regs, 1601 periph_clk_enb_refcnt); 1602 clk_register_clkdev(clk, "dsia", "tegradc.0"); 1603 clks[dsia] = clk; 1604 1605 /* csi */ 1606 clk = tegra_clk_register_periph_gate("csi", "pll_p_out3", 0, clk_base, 1607 0, 52, &periph_h_regs, 1608 periph_clk_enb_refcnt); 1609 clk_register_clkdev(clk, "csi", "tegra_camera"); 1610 clks[csi] = clk; 1611 1612 /* isp */ 1613 clk = tegra_clk_register_periph_gate("isp", "clk_m", 0, clk_base, 0, 23, 1614 &periph_l_regs, periph_clk_enb_refcnt); 1615 clk_register_clkdev(clk, "isp", "tegra_camera"); 1616 clks[isp] = clk; 1617 1618 /* pcie */ 1619 clk = tegra_clk_register_periph_gate("pcie", "clk_m", 0, clk_base, 0, 1620 70, &periph_u_regs, periph_clk_enb_refcnt); 1621 clk_register_clkdev(clk, "pcie", "tegra-pcie"); 1622 clks[pcie] = clk; 1623 1624 /* afi */ 1625 clk = tegra_clk_register_periph_gate("afi", "clk_m", 0, clk_base, 0, 72, 1626 &periph_u_regs, periph_clk_enb_refcnt); 1627 clk_register_clkdev(clk, "afi", "tegra-pcie"); 1628 clks[afi] = clk; 1629 1630 /* pciex */ 1631 clk = tegra_clk_register_periph_gate("pciex", "pll_e", 0, clk_base, 0, 1632 74, &periph_u_regs, periph_clk_enb_refcnt); 1633 clk_register_clkdev(clk, "pciex", "tegra-pcie"); 1634 clks[pciex] = clk; 1635 1636 /* kfuse */ 1637 clk = tegra_clk_register_periph_gate("kfuse", "clk_m", 1638 TEGRA_PERIPH_ON_APB, 1639 clk_base, 0, 40, &periph_h_regs, 1640 periph_clk_enb_refcnt); 1641 clk_register_clkdev(clk, NULL, "kfuse-tegra"); 1642 clks[kfuse] = clk; 1643 1644 /* fuse */ 1645 clk = tegra_clk_register_periph_gate("fuse", "clk_m", 1646 TEGRA_PERIPH_ON_APB, 1647 clk_base, 0, 39, &periph_h_regs, 1648 periph_clk_enb_refcnt); 1649 clk_register_clkdev(clk, "fuse", "fuse-tegra"); 1650 clks[fuse] = clk; 1651 1652 /* fuse_burn */ 1653 clk = tegra_clk_register_periph_gate("fuse_burn", "clk_m", 1654 TEGRA_PERIPH_ON_APB, 1655 clk_base, 0, 39, &periph_h_regs, 1656 periph_clk_enb_refcnt); 1657 clk_register_clkdev(clk, "fuse_burn", "fuse-tegra"); 1658 clks[fuse_burn] = clk; 1659 1660 /* apbif */ 1661 clk = tegra_clk_register_periph_gate("apbif", "clk_m", 0, 1662 clk_base, 0, 107, &periph_v_regs, 1663 periph_clk_enb_refcnt); 1664 clk_register_clkdev(clk, "apbif", "tegra30-ahub"); 1665 clks[apbif] = clk; 1666 1667 /* hda2hdmi */ 1668 clk = tegra_clk_register_periph_gate("hda2hdmi", "clk_m", 1669 TEGRA_PERIPH_ON_APB, 1670 clk_base, 0, 128, &periph_w_regs, 1671 periph_clk_enb_refcnt); 1672 clk_register_clkdev(clk, "hda2hdmi", "tegra30-hda"); 1673 clks[hda2hdmi] = clk; 1674 1675 /* sata_cold */ 1676 clk = tegra_clk_register_periph_gate("sata_cold", "clk_m", 1677 TEGRA_PERIPH_ON_APB, 1678 clk_base, 0, 129, &periph_w_regs, 1679 periph_clk_enb_refcnt); 1680 clk_register_clkdev(clk, NULL, "tegra_sata_cold"); 1681 clks[sata_cold] = clk; 1682 1683 /* dtv */ 1684 clk = tegra_clk_register_periph_gate("dtv", "clk_m", 1685 TEGRA_PERIPH_ON_APB, 1686 clk_base, 0, 79, &periph_u_regs, 1687 periph_clk_enb_refcnt); 1688 clk_register_clkdev(clk, NULL, "dtv"); 1689 clks[dtv] = clk; 1690 1691 /* emc */ 1692 clk = clk_register_mux(NULL, "emc_mux", mux_pllmcp_clkm, 1693 ARRAY_SIZE(mux_pllmcp_clkm), 1694 CLK_SET_RATE_NO_REPARENT, 1695 clk_base + CLK_SOURCE_EMC, 1696 30, 2, 0, NULL); 1697 clk = tegra_clk_register_periph_gate("emc", "emc_mux", 0, clk_base, 0, 1698 57, &periph_h_regs, periph_clk_enb_refcnt); 1699 clk_register_clkdev(clk, "emc", NULL); 1700 clks[emc] = clk; 1701 1702 for (i = 0; i < ARRAY_SIZE(tegra_periph_clk_list); i++) { 1703 data = &tegra_periph_clk_list[i]; 1704 clk = tegra_clk_register_periph(data->name, data->parent_names, 1705 data->num_parents, &data->periph, 1706 clk_base, data->offset, data->flags); 1707 clk_register_clkdev(clk, data->con_id, data->dev_id); 1708 clks[data->clk_id] = clk; 1709 } 1710 1711 for (i = 0; i < ARRAY_SIZE(tegra_periph_nodiv_clk_list); i++) { 1712 data = &tegra_periph_nodiv_clk_list[i]; 1713 clk = tegra_clk_register_periph_nodiv(data->name, 1714 data->parent_names, 1715 data->num_parents, &data->periph, 1716 clk_base, data->offset); 1717 clk_register_clkdev(clk, data->con_id, data->dev_id); 1718 clks[data->clk_id] = clk; 1719 } 1720} 1721 1722static void __init tegra30_fixed_clk_init(void) 1723{ 1724 struct clk *clk; 1725 1726 /* clk_32k */ 1727 clk = clk_register_fixed_rate(NULL, "clk_32k", NULL, CLK_IS_ROOT, 1728 32768); 1729 clk_register_clkdev(clk, "clk_32k", NULL); 1730 clks[clk_32k] = clk; 1731 1732 /* clk_m_div2 */ 1733 clk = clk_register_fixed_factor(NULL, "clk_m_div2", "clk_m", 1734 CLK_SET_RATE_PARENT, 1, 2); 1735 clk_register_clkdev(clk, "clk_m_div2", NULL); 1736 clks[clk_m_div2] = clk; 1737 1738 /* clk_m_div4 */ 1739 clk = clk_register_fixed_factor(NULL, "clk_m_div4", "clk_m", 1740 CLK_SET_RATE_PARENT, 1, 4); 1741 clk_register_clkdev(clk, "clk_m_div4", NULL); 1742 clks[clk_m_div4] = clk; 1743 1744 /* cml0 */ 1745 clk = clk_register_gate(NULL, "cml0", "pll_e", 0, clk_base + PLLE_AUX, 1746 0, 0, &cml_lock); 1747 clk_register_clkdev(clk, "cml0", NULL); 1748 clks[cml0] = clk; 1749 1750 /* cml1 */ 1751 clk = clk_register_gate(NULL, "cml1", "pll_e", 0, clk_base + PLLE_AUX, 1752 1, 0, &cml_lock); 1753 clk_register_clkdev(clk, "cml1", NULL); 1754 clks[cml1] = clk; 1755} 1756 1757static void __init tegra30_osc_clk_init(void) 1758{ 1759 struct clk *clk; 1760 unsigned int pll_ref_div; 1761 1762 tegra30_clk_measure_input_freq(); 1763 1764 /* clk_m */ 1765 clk = clk_register_fixed_rate(NULL, "clk_m", NULL, CLK_IS_ROOT, 1766 input_freq); 1767 clk_register_clkdev(clk, "clk_m", NULL); 1768 clks[clk_m] = clk; 1769 1770 /* pll_ref */ 1771 pll_ref_div = tegra30_get_pll_ref_div(); 1772 clk = clk_register_fixed_factor(NULL, "pll_ref", "clk_m", 1773 CLK_SET_RATE_PARENT, 1, pll_ref_div); 1774 clk_register_clkdev(clk, "pll_ref", NULL); 1775 clks[pll_ref] = clk; 1776} 1777 1778/* Tegra30 CPU clock and reset control functions */ 1779static void tegra30_wait_cpu_in_reset(u32 cpu) 1780{ 1781 unsigned int reg; 1782 1783 do { 1784 reg = readl(clk_base + 1785 TEGRA30_CLK_RST_CONTROLLER_CPU_CMPLX_STATUS); 1786 cpu_relax(); 1787 } while (!(reg & (1 << cpu))); /* check CPU been reset or not */ 1788 1789 return; 1790} 1791 1792static void tegra30_put_cpu_in_reset(u32 cpu) 1793{ 1794 writel(CPU_RESET(cpu), 1795 clk_base + TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET); 1796 dmb(); 1797} 1798 1799static void tegra30_cpu_out_of_reset(u32 cpu) 1800{ 1801 writel(CPU_RESET(cpu), 1802 clk_base + TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR); 1803 wmb(); 1804} 1805 1806 1807static void tegra30_enable_cpu_clock(u32 cpu) 1808{ 1809 unsigned int reg; 1810 1811 writel(CPU_CLOCK(cpu), 1812 clk_base + TEGRA30_CLK_RST_CONTROLLER_CLK_CPU_CMPLX_CLR); 1813 reg = readl(clk_base + 1814 TEGRA30_CLK_RST_CONTROLLER_CLK_CPU_CMPLX_CLR); 1815} 1816 1817static void tegra30_disable_cpu_clock(u32 cpu) 1818{ 1819 1820 unsigned int reg; 1821 1822 reg = readl(clk_base + TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX); 1823 writel(reg | CPU_CLOCK(cpu), 1824 clk_base + TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX); 1825} 1826 1827#ifdef CONFIG_PM_SLEEP 1828static bool tegra30_cpu_rail_off_ready(void) 1829{ 1830 unsigned int cpu_rst_status; 1831 int cpu_pwr_status; 1832 1833 cpu_rst_status = readl(clk_base + 1834 TEGRA30_CLK_RST_CONTROLLER_CPU_CMPLX_STATUS); 1835 cpu_pwr_status = tegra_powergate_is_powered(TEGRA_POWERGATE_CPU1) || 1836 tegra_powergate_is_powered(TEGRA_POWERGATE_CPU2) || 1837 tegra_powergate_is_powered(TEGRA_POWERGATE_CPU3); 1838 1839 if (((cpu_rst_status & 0xE) != 0xE) || cpu_pwr_status) 1840 return false; 1841 1842 return true; 1843} 1844 1845static void tegra30_cpu_clock_suspend(void) 1846{ 1847 /* switch coresite to clk_m, save off original source */ 1848 tegra30_cpu_clk_sctx.clk_csite_src = 1849 readl(clk_base + CLK_RESET_SOURCE_CSITE); 1850 writel(3<<30, clk_base + CLK_RESET_SOURCE_CSITE); 1851 1852 tegra30_cpu_clk_sctx.cpu_burst = 1853 readl(clk_base + CLK_RESET_CCLK_BURST); 1854 tegra30_cpu_clk_sctx.pllx_base = 1855 readl(clk_base + CLK_RESET_PLLX_BASE); 1856 tegra30_cpu_clk_sctx.pllx_misc = 1857 readl(clk_base + CLK_RESET_PLLX_MISC); 1858 tegra30_cpu_clk_sctx.cclk_divider = 1859 readl(clk_base + CLK_RESET_CCLK_DIVIDER); 1860} 1861 1862static void tegra30_cpu_clock_resume(void) 1863{ 1864 unsigned int reg, policy; 1865 1866 /* Is CPU complex already running on PLLX? */ 1867 reg = readl(clk_base + CLK_RESET_CCLK_BURST); 1868 policy = (reg >> CLK_RESET_CCLK_BURST_POLICY_SHIFT) & 0xF; 1869 1870 if (policy == CLK_RESET_CCLK_IDLE_POLICY) 1871 reg = (reg >> CLK_RESET_CCLK_IDLE_POLICY_SHIFT) & 0xF; 1872 else if (policy == CLK_RESET_CCLK_RUN_POLICY) 1873 reg = (reg >> CLK_RESET_CCLK_RUN_POLICY_SHIFT) & 0xF; 1874 else 1875 BUG(); 1876 1877 if (reg != CLK_RESET_CCLK_BURST_POLICY_PLLX) { 1878 /* restore PLLX settings if CPU is on different PLL */ 1879 writel(tegra30_cpu_clk_sctx.pllx_misc, 1880 clk_base + CLK_RESET_PLLX_MISC); 1881 writel(tegra30_cpu_clk_sctx.pllx_base, 1882 clk_base + CLK_RESET_PLLX_BASE); 1883 1884 /* wait for PLL stabilization if PLLX was enabled */ 1885 if (tegra30_cpu_clk_sctx.pllx_base & (1 << 30)) 1886 udelay(300); 1887 } 1888 1889 /* 1890 * Restore original burst policy setting for calls resulting from CPU 1891 * LP2 in idle or system suspend. 1892 */ 1893 writel(tegra30_cpu_clk_sctx.cclk_divider, 1894 clk_base + CLK_RESET_CCLK_DIVIDER); 1895 writel(tegra30_cpu_clk_sctx.cpu_burst, 1896 clk_base + CLK_RESET_CCLK_BURST); 1897 1898 writel(tegra30_cpu_clk_sctx.clk_csite_src, 1899 clk_base + CLK_RESET_SOURCE_CSITE); 1900} 1901#endif 1902 1903static struct tegra_cpu_car_ops tegra30_cpu_car_ops = { 1904 .wait_for_reset = tegra30_wait_cpu_in_reset, 1905 .put_in_reset = tegra30_put_cpu_in_reset, 1906 .out_of_reset = tegra30_cpu_out_of_reset, 1907 .enable_clock = tegra30_enable_cpu_clock, 1908 .disable_clock = tegra30_disable_cpu_clock, 1909#ifdef CONFIG_PM_SLEEP 1910 .rail_off_ready = tegra30_cpu_rail_off_ready, 1911 .suspend = tegra30_cpu_clock_suspend, 1912 .resume = tegra30_cpu_clock_resume, 1913#endif 1914}; 1915 1916static struct tegra_clk_init_table init_table[] __initdata = { 1917 {uarta, pll_p, 408000000, 0}, 1918 {uartb, pll_p, 408000000, 0}, 1919 {uartc, pll_p, 408000000, 0}, 1920 {uartd, pll_p, 408000000, 0}, 1921 {uarte, pll_p, 408000000, 0}, 1922 {pll_a, clk_max, 564480000, 1}, 1923 {pll_a_out0, clk_max, 11289600, 1}, 1924 {extern1, pll_a_out0, 0, 1}, 1925 {clk_out_1_mux, extern1, 0, 0}, 1926 {clk_out_1, clk_max, 0, 1}, 1927 {blink, clk_max, 0, 1}, 1928 {i2s0, pll_a_out0, 11289600, 0}, 1929 {i2s1, pll_a_out0, 11289600, 0}, 1930 {i2s2, pll_a_out0, 11289600, 0}, 1931 {i2s3, pll_a_out0, 11289600, 0}, 1932 {i2s4, pll_a_out0, 11289600, 0}, 1933 {sdmmc1, pll_p, 48000000, 0}, 1934 {sdmmc2, pll_p, 48000000, 0}, 1935 {sdmmc3, pll_p, 48000000, 0}, 1936 {pll_m, clk_max, 0, 1}, 1937 {pclk, clk_max, 0, 1}, 1938 {csite, clk_max, 0, 1}, 1939 {emc, clk_max, 0, 1}, 1940 {mselect, clk_max, 0, 1}, 1941 {sbc1, pll_p, 100000000, 0}, 1942 {sbc2, pll_p, 100000000, 0}, 1943 {sbc3, pll_p, 100000000, 0}, 1944 {sbc4, pll_p, 100000000, 0}, 1945 {sbc5, pll_p, 100000000, 0}, 1946 {sbc6, pll_p, 100000000, 0}, 1947 {host1x, pll_c, 150000000, 0}, 1948 {disp1, pll_p, 600000000, 0}, 1949 {disp2, pll_p, 600000000, 0}, 1950 {twd, clk_max, 0, 1}, 1951 {gr2d, pll_c, 300000000, 0}, 1952 {gr3d, pll_c, 300000000, 0}, 1953 {clk_max, clk_max, 0, 0}, /* This MUST be the last entry. */ 1954}; 1955 1956static void __init tegra30_clock_apply_init_table(void) 1957{ 1958 tegra_init_from_table(init_table, clks, clk_max); 1959} 1960 1961/* 1962 * Some clocks may be used by different drivers depending on the board 1963 * configuration. List those here to register them twice in the clock lookup 1964 * table under two names. 1965 */ 1966static struct tegra_clk_duplicate tegra_clk_duplicates[] = { 1967 TEGRA_CLK_DUPLICATE(usbd, "utmip-pad", NULL), 1968 TEGRA_CLK_DUPLICATE(usbd, "tegra-ehci.0", NULL), 1969 TEGRA_CLK_DUPLICATE(usbd, "tegra-otg", NULL), 1970 TEGRA_CLK_DUPLICATE(bsev, "tegra-avp", "bsev"), 1971 TEGRA_CLK_DUPLICATE(bsev, "nvavp", "bsev"), 1972 TEGRA_CLK_DUPLICATE(vde, "tegra-aes", "vde"), 1973 TEGRA_CLK_DUPLICATE(bsea, "tegra-aes", "bsea"), 1974 TEGRA_CLK_DUPLICATE(bsea, "nvavp", "bsea"), 1975 TEGRA_CLK_DUPLICATE(cml1, "tegra_sata_cml", NULL), 1976 TEGRA_CLK_DUPLICATE(cml0, "tegra_pcie", "cml"), 1977 TEGRA_CLK_DUPLICATE(pciex, "tegra_pcie", "pciex"), 1978 TEGRA_CLK_DUPLICATE(vcp, "nvavp", "vcp"), 1979 TEGRA_CLK_DUPLICATE(clk_max, NULL, NULL), /* MUST be the last entry */ 1980}; 1981 1982static const struct of_device_id pmc_match[] __initconst = { 1983 { .compatible = "nvidia,tegra30-pmc" }, 1984 {}, 1985}; 1986 1987static void __init tegra30_clock_init(struct device_node *np) 1988{ 1989 struct device_node *node; 1990 int i; 1991 1992 clk_base = of_iomap(np, 0); 1993 if (!clk_base) { 1994 pr_err("ioremap tegra30 CAR failed\n"); 1995 return; 1996 } 1997 1998 node = of_find_matching_node(NULL, pmc_match); 1999 if (!node) { 2000 pr_err("Failed to find pmc node\n"); 2001 BUG(); 2002 } 2003 2004 pmc_base = of_iomap(node, 0); 2005 if (!pmc_base) { 2006 pr_err("Can't map pmc registers\n"); 2007 BUG(); 2008 } 2009 2010 tegra30_osc_clk_init(); 2011 tegra30_fixed_clk_init(); 2012 tegra30_pll_init(); 2013 tegra30_super_clk_init(); 2014 tegra30_periph_clk_init(); 2015 tegra30_audio_clk_init(); 2016 tegra30_pmc_clk_init(); 2017 2018 for (i = 0; i < ARRAY_SIZE(clks); i++) { 2019 if (IS_ERR(clks[i])) { 2020 pr_err("Tegra30 clk %d: register failed with %ld\n", 2021 i, PTR_ERR(clks[i])); 2022 BUG(); 2023 } 2024 if (!clks[i]) 2025 clks[i] = ERR_PTR(-EINVAL); 2026 } 2027 2028 tegra_init_dup_clks(tegra_clk_duplicates, clks, clk_max); 2029 2030 clk_data.clks = clks; 2031 clk_data.clk_num = ARRAY_SIZE(clks); 2032 of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data); 2033 2034 tegra_clk_apply_init_table = tegra30_clock_apply_init_table; 2035 2036 tegra_cpu_car_ops = &tegra30_cpu_car_ops; 2037} 2038CLK_OF_DECLARE(tegra30, "nvidia,tegra30-car", tegra30_clock_init); 2039