clk-tegra30.c revision 76ebc134d45d7e6e1dc29fdcef4e539c5bc76eb8
1/* 2 * Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved. 3 * 4 * This program is free software; you can redistribute it and/or modify it 5 * under the terms and conditions of the GNU General Public License, 6 * version 2, as published by the Free Software Foundation. 7 * 8 * This program is distributed in the hope it will be useful, but WITHOUT 9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 11 * more details. 12 * 13 * You should have received a copy of the GNU General Public License 14 * along with this program. If not, see <http://www.gnu.org/licenses/>. 15 */ 16 17#include <linux/io.h> 18#include <linux/delay.h> 19#include <linux/clk.h> 20#include <linux/clk-provider.h> 21#include <linux/clkdev.h> 22#include <linux/of.h> 23#include <linux/of_address.h> 24#include <linux/clk/tegra.h> 25#include <linux/tegra-powergate.h> 26 27#include "clk.h" 28 29#define OSC_CTRL 0x50 30#define OSC_CTRL_OSC_FREQ_MASK (0xF<<28) 31#define OSC_CTRL_OSC_FREQ_13MHZ (0X0<<28) 32#define OSC_CTRL_OSC_FREQ_19_2MHZ (0X4<<28) 33#define OSC_CTRL_OSC_FREQ_12MHZ (0X8<<28) 34#define OSC_CTRL_OSC_FREQ_26MHZ (0XC<<28) 35#define OSC_CTRL_OSC_FREQ_16_8MHZ (0X1<<28) 36#define OSC_CTRL_OSC_FREQ_38_4MHZ (0X5<<28) 37#define OSC_CTRL_OSC_FREQ_48MHZ (0X9<<28) 38#define OSC_CTRL_MASK (0x3f2 | OSC_CTRL_OSC_FREQ_MASK) 39 40#define OSC_CTRL_PLL_REF_DIV_MASK (3<<26) 41#define OSC_CTRL_PLL_REF_DIV_1 (0<<26) 42#define OSC_CTRL_PLL_REF_DIV_2 (1<<26) 43#define OSC_CTRL_PLL_REF_DIV_4 (2<<26) 44 45#define OSC_FREQ_DET 0x58 46#define OSC_FREQ_DET_TRIG BIT(31) 47 48#define OSC_FREQ_DET_STATUS 0x5c 49#define OSC_FREQ_DET_BUSY BIT(31) 50#define OSC_FREQ_DET_CNT_MASK 0xffff 51 52#define CCLKG_BURST_POLICY 0x368 53#define SUPER_CCLKG_DIVIDER 0x36c 54#define CCLKLP_BURST_POLICY 0x370 55#define SUPER_CCLKLP_DIVIDER 0x374 56#define SCLK_BURST_POLICY 0x028 57#define SUPER_SCLK_DIVIDER 0x02c 58 59#define SYSTEM_CLK_RATE 0x030 60 61#define TEGRA30_CLK_PERIPH_BANKS 5 62 63#define PLLC_BASE 0x80 64#define PLLC_MISC 0x8c 65#define PLLM_BASE 0x90 66#define PLLM_MISC 0x9c 67#define PLLP_BASE 0xa0 68#define PLLP_MISC 0xac 69#define PLLX_BASE 0xe0 70#define PLLX_MISC 0xe4 71#define PLLD_BASE 0xd0 72#define PLLD_MISC 0xdc 73#define PLLD2_BASE 0x4b8 74#define PLLD2_MISC 0x4bc 75#define PLLE_BASE 0xe8 76#define PLLE_MISC 0xec 77#define PLLA_BASE 0xb0 78#define PLLA_MISC 0xbc 79#define PLLU_BASE 0xc0 80#define PLLU_MISC 0xcc 81 82#define PLL_MISC_LOCK_ENABLE 18 83#define PLLDU_MISC_LOCK_ENABLE 22 84#define PLLE_MISC_LOCK_ENABLE 9 85 86#define PLL_BASE_LOCK BIT(27) 87#define PLLE_MISC_LOCK BIT(11) 88 89#define PLLE_AUX 0x48c 90#define PLLC_OUT 0x84 91#define PLLM_OUT 0x94 92#define PLLP_OUTA 0xa4 93#define PLLP_OUTB 0xa8 94#define PLLA_OUT 0xb4 95 96#define AUDIO_SYNC_CLK_I2S0 0x4a0 97#define AUDIO_SYNC_CLK_I2S1 0x4a4 98#define AUDIO_SYNC_CLK_I2S2 0x4a8 99#define AUDIO_SYNC_CLK_I2S3 0x4ac 100#define AUDIO_SYNC_CLK_I2S4 0x4b0 101#define AUDIO_SYNC_CLK_SPDIF 0x4b4 102 103#define PMC_CLK_OUT_CNTRL 0x1a8 104 105#define CLK_SOURCE_I2S0 0x1d8 106#define CLK_SOURCE_I2S1 0x100 107#define CLK_SOURCE_I2S2 0x104 108#define CLK_SOURCE_I2S3 0x3bc 109#define CLK_SOURCE_I2S4 0x3c0 110#define CLK_SOURCE_SPDIF_OUT 0x108 111#define CLK_SOURCE_SPDIF_IN 0x10c 112#define CLK_SOURCE_PWM 0x110 113#define CLK_SOURCE_D_AUDIO 0x3d0 114#define CLK_SOURCE_DAM0 0x3d8 115#define CLK_SOURCE_DAM1 0x3dc 116#define CLK_SOURCE_DAM2 0x3e0 117#define CLK_SOURCE_HDA 0x428 118#define CLK_SOURCE_HDA2CODEC_2X 0x3e4 119#define CLK_SOURCE_SBC1 0x134 120#define CLK_SOURCE_SBC2 0x118 121#define CLK_SOURCE_SBC3 0x11c 122#define CLK_SOURCE_SBC4 0x1b4 123#define CLK_SOURCE_SBC5 0x3c8 124#define CLK_SOURCE_SBC6 0x3cc 125#define CLK_SOURCE_SATA_OOB 0x420 126#define CLK_SOURCE_SATA 0x424 127#define CLK_SOURCE_NDFLASH 0x160 128#define CLK_SOURCE_NDSPEED 0x3f8 129#define CLK_SOURCE_VFIR 0x168 130#define CLK_SOURCE_SDMMC1 0x150 131#define CLK_SOURCE_SDMMC2 0x154 132#define CLK_SOURCE_SDMMC3 0x1bc 133#define CLK_SOURCE_SDMMC4 0x164 134#define CLK_SOURCE_VDE 0x1c8 135#define CLK_SOURCE_CSITE 0x1d4 136#define CLK_SOURCE_LA 0x1f8 137#define CLK_SOURCE_OWR 0x1cc 138#define CLK_SOURCE_NOR 0x1d0 139#define CLK_SOURCE_MIPI 0x174 140#define CLK_SOURCE_I2C1 0x124 141#define CLK_SOURCE_I2C2 0x198 142#define CLK_SOURCE_I2C3 0x1b8 143#define CLK_SOURCE_I2C4 0x3c4 144#define CLK_SOURCE_I2C5 0x128 145#define CLK_SOURCE_UARTA 0x178 146#define CLK_SOURCE_UARTB 0x17c 147#define CLK_SOURCE_UARTC 0x1a0 148#define CLK_SOURCE_UARTD 0x1c0 149#define CLK_SOURCE_UARTE 0x1c4 150#define CLK_SOURCE_VI 0x148 151#define CLK_SOURCE_VI_SENSOR 0x1a8 152#define CLK_SOURCE_3D 0x158 153#define CLK_SOURCE_3D2 0x3b0 154#define CLK_SOURCE_2D 0x15c 155#define CLK_SOURCE_EPP 0x16c 156#define CLK_SOURCE_MPE 0x170 157#define CLK_SOURCE_HOST1X 0x180 158#define CLK_SOURCE_CVE 0x140 159#define CLK_SOURCE_TVO 0x188 160#define CLK_SOURCE_DTV 0x1dc 161#define CLK_SOURCE_HDMI 0x18c 162#define CLK_SOURCE_TVDAC 0x194 163#define CLK_SOURCE_DISP1 0x138 164#define CLK_SOURCE_DISP2 0x13c 165#define CLK_SOURCE_DSIB 0xd0 166#define CLK_SOURCE_TSENSOR 0x3b8 167#define CLK_SOURCE_ACTMON 0x3e8 168#define CLK_SOURCE_EXTERN1 0x3ec 169#define CLK_SOURCE_EXTERN2 0x3f0 170#define CLK_SOURCE_EXTERN3 0x3f4 171#define CLK_SOURCE_I2CSLOW 0x3fc 172#define CLK_SOURCE_SE 0x42c 173#define CLK_SOURCE_MSELECT 0x3b4 174#define CLK_SOURCE_EMC 0x19c 175 176#define AUDIO_SYNC_DOUBLER 0x49c 177 178#define PMC_CTRL 0 179#define PMC_CTRL_BLINK_ENB 7 180 181#define PMC_DPD_PADS_ORIDE 0x1c 182#define PMC_DPD_PADS_ORIDE_BLINK_ENB 20 183#define PMC_BLINK_TIMER 0x40 184 185#define UTMIP_PLL_CFG2 0x488 186#define UTMIP_PLL_CFG2_STABLE_COUNT(x) (((x) & 0xffff) << 6) 187#define UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(x) (((x) & 0x3f) << 18) 188#define UTMIP_PLL_CFG2_FORCE_PD_SAMP_A_POWERDOWN BIT(0) 189#define UTMIP_PLL_CFG2_FORCE_PD_SAMP_B_POWERDOWN BIT(2) 190#define UTMIP_PLL_CFG2_FORCE_PD_SAMP_C_POWERDOWN BIT(4) 191 192#define UTMIP_PLL_CFG1 0x484 193#define UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(x) (((x) & 0x1f) << 6) 194#define UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(x) (((x) & 0xfff) << 0) 195#define UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN BIT(14) 196#define UTMIP_PLL_CFG1_FORCE_PLL_ACTIVE_POWERDOWN BIT(12) 197#define UTMIP_PLL_CFG1_FORCE_PLLU_POWERDOWN BIT(16) 198 199/* Tegra CPU clock and reset control regs */ 200#define TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX 0x4c 201#define TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET 0x340 202#define TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR 0x344 203#define TEGRA30_CLK_RST_CONTROLLER_CLK_CPU_CMPLX_CLR 0x34c 204#define TEGRA30_CLK_RST_CONTROLLER_CPU_CMPLX_STATUS 0x470 205 206#define CPU_CLOCK(cpu) (0x1 << (8 + cpu)) 207#define CPU_RESET(cpu) (0x1111ul << (cpu)) 208 209#define CLK_RESET_CCLK_BURST 0x20 210#define CLK_RESET_CCLK_DIVIDER 0x24 211#define CLK_RESET_PLLX_BASE 0xe0 212#define CLK_RESET_PLLX_MISC 0xe4 213 214#define CLK_RESET_SOURCE_CSITE 0x1d4 215 216#define CLK_RESET_CCLK_BURST_POLICY_SHIFT 28 217#define CLK_RESET_CCLK_RUN_POLICY_SHIFT 4 218#define CLK_RESET_CCLK_IDLE_POLICY_SHIFT 0 219#define CLK_RESET_CCLK_IDLE_POLICY 1 220#define CLK_RESET_CCLK_RUN_POLICY 2 221#define CLK_RESET_CCLK_BURST_POLICY_PLLX 8 222 223/* PLLM override registers */ 224#define PMC_PLLM_WB0_OVERRIDE 0x1dc 225 226#ifdef CONFIG_PM_SLEEP 227static struct cpu_clk_suspend_context { 228 u32 pllx_misc; 229 u32 pllx_base; 230 231 u32 cpu_burst; 232 u32 clk_csite_src; 233 u32 cclk_divider; 234} tegra30_cpu_clk_sctx; 235#endif 236 237static void __iomem *clk_base; 238static void __iomem *pmc_base; 239static unsigned long input_freq; 240 241static DEFINE_SPINLOCK(clk_doubler_lock); 242static DEFINE_SPINLOCK(clk_out_lock); 243static DEFINE_SPINLOCK(pll_div_lock); 244static DEFINE_SPINLOCK(cml_lock); 245static DEFINE_SPINLOCK(pll_d_lock); 246static DEFINE_SPINLOCK(sysrate_lock); 247 248#define TEGRA_INIT_DATA_MUX(_name, _con_id, _dev_id, _parents, _offset, \ 249 _clk_num, _gate_flags, _clk_id) \ 250 TEGRA_INIT_DATA(_name, _con_id, _dev_id, _parents, _offset, \ 251 30, 2, 0, 0, 8, 1, TEGRA_DIVIDER_ROUND_UP, \ 252 _clk_num, _gate_flags, _clk_id) 253 254#define TEGRA_INIT_DATA_DIV16(_name, _con_id, _dev_id, _parents, _offset, \ 255 _clk_num, _gate_flags, _clk_id) \ 256 TEGRA_INIT_DATA(_name, _con_id, _dev_id, _parents, _offset, \ 257 30, 2, 0, 0, 16, 0, TEGRA_DIVIDER_ROUND_UP, \ 258 _clk_num, \ 259 _gate_flags, _clk_id) 260 261#define TEGRA_INIT_DATA_MUX8(_name, _con_id, _dev_id, _parents, _offset, \ 262 _clk_num, _gate_flags, _clk_id) \ 263 TEGRA_INIT_DATA(_name, _con_id, _dev_id, _parents, _offset, \ 264 29, 3, 0, 0, 8, 1, TEGRA_DIVIDER_ROUND_UP, \ 265 _clk_num, _gate_flags, _clk_id) 266 267#define TEGRA_INIT_DATA_INT(_name, _con_id, _dev_id, _parents, _offset, \ 268 _clk_num, _gate_flags, _clk_id) \ 269 TEGRA_INIT_DATA(_name, _con_id, _dev_id, _parents, _offset, \ 270 30, 2, 0, 0, 8, 1, TEGRA_DIVIDER_INT | \ 271 TEGRA_DIVIDER_ROUND_UP, _clk_num, \ 272 _gate_flags, _clk_id) 273 274#define TEGRA_INIT_DATA_UART(_name, _con_id, _dev_id, _parents, _offset,\ 275 _clk_num, _clk_id) \ 276 TEGRA_INIT_DATA(_name, _con_id, _dev_id, _parents, _offset, \ 277 30, 2, 0, 0, 16, 1, TEGRA_DIVIDER_UART | \ 278 TEGRA_DIVIDER_ROUND_UP, _clk_num, \ 279 0, _clk_id) 280 281#define TEGRA_INIT_DATA_NODIV(_name, _con_id, _dev_id, _parents, _offset, \ 282 _mux_shift, _mux_width, _clk_num, \ 283 _gate_flags, _clk_id) \ 284 TEGRA_INIT_DATA(_name, _con_id, _dev_id, _parents, _offset, \ 285 _mux_shift, _mux_width, 0, 0, 0, 0, 0,\ 286 _clk_num, _gate_flags, \ 287 _clk_id) 288 289/* 290 * IDs assigned here must be in sync with DT bindings definition 291 * for Tegra30 clocks. 292 */ 293enum tegra30_clk { 294 cpu, rtc = 4, timer, uarta, gpio = 8, sdmmc2, i2s1 = 11, i2c1, ndflash, 295 sdmmc1, sdmmc4, pwm = 17, i2s2, epp, gr2d = 21, usbd, isp, gr3d, 296 disp2 = 26, disp1, host1x, vcp, i2s0, cop_cache, mc, ahbdma, apbdma, 297 kbc = 36, statmon, pmc, kfuse = 40, sbc1, nor, sbc2 = 44, sbc3 = 46, 298 i2c5, dsia, mipi = 50, hdmi, csi, tvdac, i2c2, uartc, emc = 57, usb2, 299 usb3, mpe, vde, bsea, bsev, speedo, uartd, uarte, i2c3, sbc4, sdmmc3, 300 pcie, owr, afi, csite, pciex, avpucq, la, dtv = 79, ndspeed, i2cslow, 301 dsib, irama = 84, iramb, iramc, iramd, cram2, audio_2x = 90, csus = 92, 302 cdev2, cdev1, cpu_g = 96, cpu_lp, gr3d2, mselect, tsensor, i2s3, i2s4, 303 i2c4, sbc5, sbc6, d_audio, apbif, dam0, dam1, dam2, hda2codec_2x, 304 atomics, audio0_2x, audio1_2x, audio2_2x, audio3_2x, audio4_2x, 305 spdif_2x, actmon, extern1, extern2, extern3, sata_oob, sata, hda, 306 se = 127, hda2hdmi, sata_cold, uartb = 160, vfir, spdif_in, spdif_out, 307 vi, vi_sensor, fuse, fuse_burn, cve, tvo, clk_32k, clk_m, clk_m_div2, 308 clk_m_div4, pll_ref, pll_c, pll_c_out1, pll_m, pll_m_out1, pll_p, 309 pll_p_out1, pll_p_out2, pll_p_out3, pll_p_out4, pll_a, pll_a_out0, 310 pll_d, pll_d_out0, pll_d2, pll_d2_out0, pll_u, pll_x, pll_x_out0, pll_e, 311 spdif_in_sync, i2s0_sync, i2s1_sync, i2s2_sync, i2s3_sync, i2s4_sync, 312 vimclk_sync, audio0, audio1, audio2, audio3, audio4, spdif, clk_out_1, 313 clk_out_2, clk_out_3, sclk, blink, cclk_g, cclk_lp, twd, cml0, cml1, 314 hclk, pclk, clk_out_1_mux = 300, clk_max 315}; 316 317static struct clk **clks; 318 319/* 320 * Structure defining the fields for USB UTMI clocks Parameters. 321 */ 322struct utmi_clk_param { 323 /* Oscillator Frequency in KHz */ 324 u32 osc_frequency; 325 /* UTMIP PLL Enable Delay Count */ 326 u8 enable_delay_count; 327 /* UTMIP PLL Stable count */ 328 u8 stable_count; 329 /* UTMIP PLL Active delay count */ 330 u8 active_delay_count; 331 /* UTMIP PLL Xtal frequency count */ 332 u8 xtal_freq_count; 333}; 334 335static const struct utmi_clk_param utmi_parameters[] = { 336/* OSC_FREQUENCY, ENABLE_DLY, STABLE_CNT, ACTIVE_DLY, XTAL_FREQ_CNT */ 337 {13000000, 0x02, 0x33, 0x05, 0x7F}, 338 {19200000, 0x03, 0x4B, 0x06, 0xBB}, 339 {12000000, 0x02, 0x2F, 0x04, 0x76}, 340 {26000000, 0x04, 0x66, 0x09, 0xFE}, 341 {16800000, 0x03, 0x41, 0x0A, 0xA4}, 342}; 343 344static struct tegra_clk_pll_freq_table pll_c_freq_table[] = { 345 { 12000000, 1040000000, 520, 6, 0, 8}, 346 { 13000000, 1040000000, 480, 6, 0, 8}, 347 { 16800000, 1040000000, 495, 8, 0, 8}, /* actual: 1039.5 MHz */ 348 { 19200000, 1040000000, 325, 6, 0, 6}, 349 { 26000000, 1040000000, 520, 13, 0, 8}, 350 351 { 12000000, 832000000, 416, 6, 0, 8}, 352 { 13000000, 832000000, 832, 13, 0, 8}, 353 { 16800000, 832000000, 396, 8, 0, 8}, /* actual: 831.6 MHz */ 354 { 19200000, 832000000, 260, 6, 0, 8}, 355 { 26000000, 832000000, 416, 13, 0, 8}, 356 357 { 12000000, 624000000, 624, 12, 0, 8}, 358 { 13000000, 624000000, 624, 13, 0, 8}, 359 { 16800000, 600000000, 520, 14, 0, 8}, 360 { 19200000, 624000000, 520, 16, 0, 8}, 361 { 26000000, 624000000, 624, 26, 0, 8}, 362 363 { 12000000, 600000000, 600, 12, 0, 8}, 364 { 13000000, 600000000, 600, 13, 0, 8}, 365 { 16800000, 600000000, 500, 14, 0, 8}, 366 { 19200000, 600000000, 375, 12, 0, 6}, 367 { 26000000, 600000000, 600, 26, 0, 8}, 368 369 { 12000000, 520000000, 520, 12, 0, 8}, 370 { 13000000, 520000000, 520, 13, 0, 8}, 371 { 16800000, 520000000, 495, 16, 0, 8}, /* actual: 519.75 MHz */ 372 { 19200000, 520000000, 325, 12, 0, 6}, 373 { 26000000, 520000000, 520, 26, 0, 8}, 374 375 { 12000000, 416000000, 416, 12, 0, 8}, 376 { 13000000, 416000000, 416, 13, 0, 8}, 377 { 16800000, 416000000, 396, 16, 0, 8}, /* actual: 415.8 MHz */ 378 { 19200000, 416000000, 260, 12, 0, 6}, 379 { 26000000, 416000000, 416, 26, 0, 8}, 380 { 0, 0, 0, 0, 0, 0 }, 381}; 382 383static struct tegra_clk_pll_freq_table pll_m_freq_table[] = { 384 { 12000000, 666000000, 666, 12, 0, 8}, 385 { 13000000, 666000000, 666, 13, 0, 8}, 386 { 16800000, 666000000, 555, 14, 0, 8}, 387 { 19200000, 666000000, 555, 16, 0, 8}, 388 { 26000000, 666000000, 666, 26, 0, 8}, 389 { 12000000, 600000000, 600, 12, 0, 8}, 390 { 13000000, 600000000, 600, 13, 0, 8}, 391 { 16800000, 600000000, 500, 14, 0, 8}, 392 { 19200000, 600000000, 375, 12, 0, 6}, 393 { 26000000, 600000000, 600, 26, 0, 8}, 394 { 0, 0, 0, 0, 0, 0 }, 395}; 396 397static struct tegra_clk_pll_freq_table pll_p_freq_table[] = { 398 { 12000000, 216000000, 432, 12, 1, 8}, 399 { 13000000, 216000000, 432, 13, 1, 8}, 400 { 16800000, 216000000, 360, 14, 1, 8}, 401 { 19200000, 216000000, 360, 16, 1, 8}, 402 { 26000000, 216000000, 432, 26, 1, 8}, 403 { 0, 0, 0, 0, 0, 0 }, 404}; 405 406static struct tegra_clk_pll_freq_table pll_a_freq_table[] = { 407 { 9600000, 564480000, 294, 5, 0, 4}, 408 { 9600000, 552960000, 288, 5, 0, 4}, 409 { 9600000, 24000000, 5, 2, 0, 1}, 410 411 { 28800000, 56448000, 49, 25, 0, 1}, 412 { 28800000, 73728000, 64, 25, 0, 1}, 413 { 28800000, 24000000, 5, 6, 0, 1}, 414 { 0, 0, 0, 0, 0, 0 }, 415}; 416 417static struct tegra_clk_pll_freq_table pll_d_freq_table[] = { 418 { 12000000, 216000000, 216, 12, 0, 4}, 419 { 13000000, 216000000, 216, 13, 0, 4}, 420 { 16800000, 216000000, 180, 14, 0, 4}, 421 { 19200000, 216000000, 180, 16, 0, 4}, 422 { 26000000, 216000000, 216, 26, 0, 4}, 423 424 { 12000000, 594000000, 594, 12, 0, 8}, 425 { 13000000, 594000000, 594, 13, 0, 8}, 426 { 16800000, 594000000, 495, 14, 0, 8}, 427 { 19200000, 594000000, 495, 16, 0, 8}, 428 { 26000000, 594000000, 594, 26, 0, 8}, 429 430 { 12000000, 1000000000, 1000, 12, 0, 12}, 431 { 13000000, 1000000000, 1000, 13, 0, 12}, 432 { 19200000, 1000000000, 625, 12, 0, 8}, 433 { 26000000, 1000000000, 1000, 26, 0, 12}, 434 435 { 0, 0, 0, 0, 0, 0 }, 436}; 437 438static struct pdiv_map pllu_p[] = { 439 { .pdiv = 1, .hw_val = 1 }, 440 { .pdiv = 2, .hw_val = 0 }, 441 { .pdiv = 0, .hw_val = 0 }, 442}; 443 444static struct tegra_clk_pll_freq_table pll_u_freq_table[] = { 445 { 12000000, 480000000, 960, 12, 0, 12}, 446 { 13000000, 480000000, 960, 13, 0, 12}, 447 { 16800000, 480000000, 400, 7, 0, 5}, 448 { 19200000, 480000000, 200, 4, 0, 3}, 449 { 26000000, 480000000, 960, 26, 0, 12}, 450 { 0, 0, 0, 0, 0, 0 }, 451}; 452 453static struct tegra_clk_pll_freq_table pll_x_freq_table[] = { 454 /* 1.7 GHz */ 455 { 12000000, 1700000000, 850, 6, 0, 8}, 456 { 13000000, 1700000000, 915, 7, 0, 8}, /* actual: 1699.2 MHz */ 457 { 16800000, 1700000000, 708, 7, 0, 8}, /* actual: 1699.2 MHz */ 458 { 19200000, 1700000000, 885, 10, 0, 8}, /* actual: 1699.2 MHz */ 459 { 26000000, 1700000000, 850, 13, 0, 8}, 460 461 /* 1.6 GHz */ 462 { 12000000, 1600000000, 800, 6, 0, 8}, 463 { 13000000, 1600000000, 738, 6, 0, 8}, /* actual: 1599.0 MHz */ 464 { 16800000, 1600000000, 857, 9, 0, 8}, /* actual: 1599.7 MHz */ 465 { 19200000, 1600000000, 500, 6, 0, 8}, 466 { 26000000, 1600000000, 800, 13, 0, 8}, 467 468 /* 1.5 GHz */ 469 { 12000000, 1500000000, 750, 6, 0, 8}, 470 { 13000000, 1500000000, 923, 8, 0, 8}, /* actual: 1499.8 MHz */ 471 { 16800000, 1500000000, 625, 7, 0, 8}, 472 { 19200000, 1500000000, 625, 8, 0, 8}, 473 { 26000000, 1500000000, 750, 13, 0, 8}, 474 475 /* 1.4 GHz */ 476 { 12000000, 1400000000, 700, 6, 0, 8}, 477 { 13000000, 1400000000, 969, 9, 0, 8}, /* actual: 1399.7 MHz */ 478 { 16800000, 1400000000, 1000, 12, 0, 8}, 479 { 19200000, 1400000000, 875, 12, 0, 8}, 480 { 26000000, 1400000000, 700, 13, 0, 8}, 481 482 /* 1.3 GHz */ 483 { 12000000, 1300000000, 975, 9, 0, 8}, 484 { 13000000, 1300000000, 1000, 10, 0, 8}, 485 { 16800000, 1300000000, 928, 12, 0, 8}, /* actual: 1299.2 MHz */ 486 { 19200000, 1300000000, 812, 12, 0, 8}, /* actual: 1299.2 MHz */ 487 { 26000000, 1300000000, 650, 13, 0, 8}, 488 489 /* 1.2 GHz */ 490 { 12000000, 1200000000, 1000, 10, 0, 8}, 491 { 13000000, 1200000000, 923, 10, 0, 8}, /* actual: 1199.9 MHz */ 492 { 16800000, 1200000000, 1000, 14, 0, 8}, 493 { 19200000, 1200000000, 1000, 16, 0, 8}, 494 { 26000000, 1200000000, 600, 13, 0, 8}, 495 496 /* 1.1 GHz */ 497 { 12000000, 1100000000, 825, 9, 0, 8}, 498 { 13000000, 1100000000, 846, 10, 0, 8}, /* actual: 1099.8 MHz */ 499 { 16800000, 1100000000, 982, 15, 0, 8}, /* actual: 1099.8 MHz */ 500 { 19200000, 1100000000, 859, 15, 0, 8}, /* actual: 1099.5 MHz */ 501 { 26000000, 1100000000, 550, 13, 0, 8}, 502 503 /* 1 GHz */ 504 { 12000000, 1000000000, 1000, 12, 0, 8}, 505 { 13000000, 1000000000, 1000, 13, 0, 8}, 506 { 16800000, 1000000000, 833, 14, 0, 8}, /* actual: 999.6 MHz */ 507 { 19200000, 1000000000, 625, 12, 0, 8}, 508 { 26000000, 1000000000, 1000, 26, 0, 8}, 509 510 { 0, 0, 0, 0, 0, 0 }, 511}; 512 513static struct tegra_clk_pll_freq_table pll_e_freq_table[] = { 514 /* PLLE special case: use cpcon field to store cml divider value */ 515 { 12000000, 100000000, 150, 1, 18, 11}, 516 { 216000000, 100000000, 200, 18, 24, 13}, 517 { 0, 0, 0, 0, 0, 0 }, 518}; 519 520/* PLL parameters */ 521static struct tegra_clk_pll_params pll_c_params = { 522 .input_min = 2000000, 523 .input_max = 31000000, 524 .cf_min = 1000000, 525 .cf_max = 6000000, 526 .vco_min = 20000000, 527 .vco_max = 1400000000, 528 .base_reg = PLLC_BASE, 529 .misc_reg = PLLC_MISC, 530 .lock_mask = PLL_BASE_LOCK, 531 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE, 532 .lock_delay = 300, 533 .freq_table = pll_c_freq_table, 534 .flags = TEGRA_PLL_HAS_CPCON | TEGRA_PLL_USE_LOCK, 535}; 536 537static struct div_nmp pllm_nmp = { 538 .divn_shift = 8, 539 .divn_width = 10, 540 .override_divn_shift = 5, 541 .divm_shift = 0, 542 .divm_width = 5, 543 .override_divm_shift = 0, 544 .divp_shift = 20, 545 .divp_width = 3, 546 .override_divp_shift = 15, 547}; 548 549static struct tegra_clk_pll_params pll_m_params = { 550 .input_min = 2000000, 551 .input_max = 31000000, 552 .cf_min = 1000000, 553 .cf_max = 6000000, 554 .vco_min = 20000000, 555 .vco_max = 1200000000, 556 .base_reg = PLLM_BASE, 557 .misc_reg = PLLM_MISC, 558 .lock_mask = PLL_BASE_LOCK, 559 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE, 560 .lock_delay = 300, 561 .div_nmp = &pllm_nmp, 562 .pmc_divnm_reg = PMC_PLLM_WB0_OVERRIDE, 563 .pmc_divp_reg = PMC_PLLM_WB0_OVERRIDE, 564 .freq_table = pll_m_freq_table, 565 .flags = TEGRA_PLLM | TEGRA_PLL_HAS_CPCON | 566 TEGRA_PLL_SET_DCCON | TEGRA_PLL_USE_LOCK, 567}; 568 569static struct tegra_clk_pll_params pll_p_params = { 570 .input_min = 2000000, 571 .input_max = 31000000, 572 .cf_min = 1000000, 573 .cf_max = 6000000, 574 .vco_min = 20000000, 575 .vco_max = 1400000000, 576 .base_reg = PLLP_BASE, 577 .misc_reg = PLLP_MISC, 578 .lock_mask = PLL_BASE_LOCK, 579 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE, 580 .lock_delay = 300, 581 .freq_table = pll_p_freq_table, 582 .flags = TEGRA_PLL_FIXED | TEGRA_PLL_HAS_CPCON | TEGRA_PLL_USE_LOCK, 583 .fixed_rate = 408000000, 584}; 585 586static struct tegra_clk_pll_params pll_a_params = { 587 .input_min = 2000000, 588 .input_max = 31000000, 589 .cf_min = 1000000, 590 .cf_max = 6000000, 591 .vco_min = 20000000, 592 .vco_max = 1400000000, 593 .base_reg = PLLA_BASE, 594 .misc_reg = PLLA_MISC, 595 .lock_mask = PLL_BASE_LOCK, 596 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE, 597 .lock_delay = 300, 598 .freq_table = pll_a_freq_table, 599 .flags = TEGRA_PLL_HAS_CPCON | TEGRA_PLL_USE_LOCK, 600}; 601 602static struct tegra_clk_pll_params pll_d_params = { 603 .input_min = 2000000, 604 .input_max = 40000000, 605 .cf_min = 1000000, 606 .cf_max = 6000000, 607 .vco_min = 40000000, 608 .vco_max = 1000000000, 609 .base_reg = PLLD_BASE, 610 .misc_reg = PLLD_MISC, 611 .lock_mask = PLL_BASE_LOCK, 612 .lock_enable_bit_idx = PLLDU_MISC_LOCK_ENABLE, 613 .lock_delay = 1000, 614 .freq_table = pll_d_freq_table, 615 .flags = TEGRA_PLL_HAS_CPCON | TEGRA_PLL_SET_LFCON | 616 TEGRA_PLL_USE_LOCK, 617 618}; 619 620static struct tegra_clk_pll_params pll_d2_params = { 621 .input_min = 2000000, 622 .input_max = 40000000, 623 .cf_min = 1000000, 624 .cf_max = 6000000, 625 .vco_min = 40000000, 626 .vco_max = 1000000000, 627 .base_reg = PLLD2_BASE, 628 .misc_reg = PLLD2_MISC, 629 .lock_mask = PLL_BASE_LOCK, 630 .lock_enable_bit_idx = PLLDU_MISC_LOCK_ENABLE, 631 .lock_delay = 1000, 632 .freq_table = pll_d_freq_table, 633 .flags = TEGRA_PLL_HAS_CPCON | TEGRA_PLL_SET_LFCON | 634 TEGRA_PLL_USE_LOCK, 635}; 636 637static struct tegra_clk_pll_params pll_u_params = { 638 .input_min = 2000000, 639 .input_max = 40000000, 640 .cf_min = 1000000, 641 .cf_max = 6000000, 642 .vco_min = 48000000, 643 .vco_max = 960000000, 644 .base_reg = PLLU_BASE, 645 .misc_reg = PLLU_MISC, 646 .lock_mask = PLL_BASE_LOCK, 647 .lock_enable_bit_idx = PLLDU_MISC_LOCK_ENABLE, 648 .lock_delay = 1000, 649 .pdiv_tohw = pllu_p, 650 .freq_table = pll_u_freq_table, 651 .flags = TEGRA_PLLU | TEGRA_PLL_HAS_CPCON | TEGRA_PLL_SET_LFCON, 652}; 653 654static struct tegra_clk_pll_params pll_x_params = { 655 .input_min = 2000000, 656 .input_max = 31000000, 657 .cf_min = 1000000, 658 .cf_max = 6000000, 659 .vco_min = 20000000, 660 .vco_max = 1700000000, 661 .base_reg = PLLX_BASE, 662 .misc_reg = PLLX_MISC, 663 .lock_mask = PLL_BASE_LOCK, 664 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE, 665 .lock_delay = 300, 666 .freq_table = pll_x_freq_table, 667 .flags = TEGRA_PLL_HAS_CPCON | TEGRA_PLL_SET_DCCON | 668 TEGRA_PLL_USE_LOCK, 669}; 670 671static struct tegra_clk_pll_params pll_e_params = { 672 .input_min = 12000000, 673 .input_max = 216000000, 674 .cf_min = 12000000, 675 .cf_max = 12000000, 676 .vco_min = 1200000000, 677 .vco_max = 2400000000U, 678 .base_reg = PLLE_BASE, 679 .misc_reg = PLLE_MISC, 680 .lock_mask = PLLE_MISC_LOCK, 681 .lock_enable_bit_idx = PLLE_MISC_LOCK_ENABLE, 682 .lock_delay = 300, 683 .freq_table = pll_e_freq_table, 684 .flags = TEGRA_PLLE_CONFIGURE | TEGRA_PLL_FIXED, 685 .fixed_rate = 100000000, 686}; 687 688static void tegra30_clk_measure_input_freq(void) 689{ 690 u32 osc_ctrl = readl_relaxed(clk_base + OSC_CTRL); 691 u32 auto_clk_control = osc_ctrl & OSC_CTRL_OSC_FREQ_MASK; 692 u32 pll_ref_div = osc_ctrl & OSC_CTRL_PLL_REF_DIV_MASK; 693 694 switch (auto_clk_control) { 695 case OSC_CTRL_OSC_FREQ_12MHZ: 696 BUG_ON(pll_ref_div != OSC_CTRL_PLL_REF_DIV_1); 697 input_freq = 12000000; 698 break; 699 case OSC_CTRL_OSC_FREQ_13MHZ: 700 BUG_ON(pll_ref_div != OSC_CTRL_PLL_REF_DIV_1); 701 input_freq = 13000000; 702 break; 703 case OSC_CTRL_OSC_FREQ_19_2MHZ: 704 BUG_ON(pll_ref_div != OSC_CTRL_PLL_REF_DIV_1); 705 input_freq = 19200000; 706 break; 707 case OSC_CTRL_OSC_FREQ_26MHZ: 708 BUG_ON(pll_ref_div != OSC_CTRL_PLL_REF_DIV_1); 709 input_freq = 26000000; 710 break; 711 case OSC_CTRL_OSC_FREQ_16_8MHZ: 712 BUG_ON(pll_ref_div != OSC_CTRL_PLL_REF_DIV_1); 713 input_freq = 16800000; 714 break; 715 case OSC_CTRL_OSC_FREQ_38_4MHZ: 716 BUG_ON(pll_ref_div != OSC_CTRL_PLL_REF_DIV_2); 717 input_freq = 38400000; 718 break; 719 case OSC_CTRL_OSC_FREQ_48MHZ: 720 BUG_ON(pll_ref_div != OSC_CTRL_PLL_REF_DIV_4); 721 input_freq = 48000000; 722 break; 723 default: 724 pr_err("Unexpected auto clock control value %d", 725 auto_clk_control); 726 BUG(); 727 return; 728 } 729} 730 731static unsigned int tegra30_get_pll_ref_div(void) 732{ 733 u32 pll_ref_div = readl_relaxed(clk_base + OSC_CTRL) & 734 OSC_CTRL_PLL_REF_DIV_MASK; 735 736 switch (pll_ref_div) { 737 case OSC_CTRL_PLL_REF_DIV_1: 738 return 1; 739 case OSC_CTRL_PLL_REF_DIV_2: 740 return 2; 741 case OSC_CTRL_PLL_REF_DIV_4: 742 return 4; 743 default: 744 pr_err("Invalid pll ref divider %d", pll_ref_div); 745 BUG(); 746 } 747 return 0; 748} 749 750static void tegra30_utmi_param_configure(void) 751{ 752 u32 reg; 753 int i; 754 755 for (i = 0; i < ARRAY_SIZE(utmi_parameters); i++) { 756 if (input_freq == utmi_parameters[i].osc_frequency) 757 break; 758 } 759 760 if (i >= ARRAY_SIZE(utmi_parameters)) { 761 pr_err("%s: Unexpected input rate %lu\n", __func__, input_freq); 762 return; 763 } 764 765 reg = readl_relaxed(clk_base + UTMIP_PLL_CFG2); 766 767 /* Program UTMIP PLL stable and active counts */ 768 reg &= ~UTMIP_PLL_CFG2_STABLE_COUNT(~0); 769 reg |= UTMIP_PLL_CFG2_STABLE_COUNT( 770 utmi_parameters[i].stable_count); 771 772 reg &= ~UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(~0); 773 774 reg |= UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT( 775 utmi_parameters[i].active_delay_count); 776 777 /* Remove power downs from UTMIP PLL control bits */ 778 reg &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_A_POWERDOWN; 779 reg &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_B_POWERDOWN; 780 reg &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_C_POWERDOWN; 781 782 writel_relaxed(reg, clk_base + UTMIP_PLL_CFG2); 783 784 /* Program UTMIP PLL delay and oscillator frequency counts */ 785 reg = readl_relaxed(clk_base + UTMIP_PLL_CFG1); 786 reg &= ~UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(~0); 787 788 reg |= UTMIP_PLL_CFG1_ENABLE_DLY_COUNT( 789 utmi_parameters[i].enable_delay_count); 790 791 reg &= ~UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(~0); 792 reg |= UTMIP_PLL_CFG1_XTAL_FREQ_COUNT( 793 utmi_parameters[i].xtal_freq_count); 794 795 /* Remove power downs from UTMIP PLL control bits */ 796 reg &= ~UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN; 797 reg &= ~UTMIP_PLL_CFG1_FORCE_PLL_ACTIVE_POWERDOWN; 798 reg &= ~UTMIP_PLL_CFG1_FORCE_PLLU_POWERDOWN; 799 800 writel_relaxed(reg, clk_base + UTMIP_PLL_CFG1); 801} 802 803static const char *pll_e_parents[] = {"pll_ref", "pll_p"}; 804 805static void __init tegra30_pll_init(void) 806{ 807 struct clk *clk; 808 809 /* PLLC */ 810 clk = tegra_clk_register_pll("pll_c", "pll_ref", clk_base, pmc_base, 0, 811 &pll_c_params, NULL); 812 clk_register_clkdev(clk, "pll_c", NULL); 813 clks[pll_c] = clk; 814 815 /* PLLC_OUT1 */ 816 clk = tegra_clk_register_divider("pll_c_out1_div", "pll_c", 817 clk_base + PLLC_OUT, 0, TEGRA_DIVIDER_ROUND_UP, 818 8, 8, 1, NULL); 819 clk = tegra_clk_register_pll_out("pll_c_out1", "pll_c_out1_div", 820 clk_base + PLLC_OUT, 1, 0, CLK_SET_RATE_PARENT, 821 0, NULL); 822 clk_register_clkdev(clk, "pll_c_out1", NULL); 823 clks[pll_c_out1] = clk; 824 825 /* PLLP */ 826 clk = tegra_clk_register_pll("pll_p", "pll_ref", clk_base, pmc_base, 0, 827 &pll_p_params, NULL); 828 clk_register_clkdev(clk, "pll_p", NULL); 829 clks[pll_p] = clk; 830 831 /* PLLP_OUT1 */ 832 clk = tegra_clk_register_divider("pll_p_out1_div", "pll_p", 833 clk_base + PLLP_OUTA, 0, TEGRA_DIVIDER_FIXED | 834 TEGRA_DIVIDER_ROUND_UP, 8, 8, 1, 835 &pll_div_lock); 836 clk = tegra_clk_register_pll_out("pll_p_out1", "pll_p_out1_div", 837 clk_base + PLLP_OUTA, 1, 0, 838 CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0, 839 &pll_div_lock); 840 clk_register_clkdev(clk, "pll_p_out1", NULL); 841 clks[pll_p_out1] = clk; 842 843 /* PLLP_OUT2 */ 844 clk = tegra_clk_register_divider("pll_p_out2_div", "pll_p", 845 clk_base + PLLP_OUTA, 0, TEGRA_DIVIDER_FIXED | 846 TEGRA_DIVIDER_ROUND_UP, 24, 8, 1, 847 &pll_div_lock); 848 clk = tegra_clk_register_pll_out("pll_p_out2", "pll_p_out2_div", 849 clk_base + PLLP_OUTA, 17, 16, 850 CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0, 851 &pll_div_lock); 852 clk_register_clkdev(clk, "pll_p_out2", NULL); 853 clks[pll_p_out2] = clk; 854 855 /* PLLP_OUT3 */ 856 clk = tegra_clk_register_divider("pll_p_out3_div", "pll_p", 857 clk_base + PLLP_OUTB, 0, TEGRA_DIVIDER_FIXED | 858 TEGRA_DIVIDER_ROUND_UP, 8, 8, 1, 859 &pll_div_lock); 860 clk = tegra_clk_register_pll_out("pll_p_out3", "pll_p_out3_div", 861 clk_base + PLLP_OUTB, 1, 0, 862 CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0, 863 &pll_div_lock); 864 clk_register_clkdev(clk, "pll_p_out3", NULL); 865 clks[pll_p_out3] = clk; 866 867 /* PLLP_OUT4 */ 868 clk = tegra_clk_register_divider("pll_p_out4_div", "pll_p", 869 clk_base + PLLP_OUTB, 0, TEGRA_DIVIDER_FIXED | 870 TEGRA_DIVIDER_ROUND_UP, 24, 8, 1, 871 &pll_div_lock); 872 clk = tegra_clk_register_pll_out("pll_p_out4", "pll_p_out4_div", 873 clk_base + PLLP_OUTB, 17, 16, 874 CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0, 875 &pll_div_lock); 876 clk_register_clkdev(clk, "pll_p_out4", NULL); 877 clks[pll_p_out4] = clk; 878 879 /* PLLM */ 880 clk = tegra_clk_register_pll("pll_m", "pll_ref", clk_base, pmc_base, 881 CLK_IGNORE_UNUSED | CLK_SET_RATE_GATE, 882 &pll_m_params, NULL); 883 clk_register_clkdev(clk, "pll_m", NULL); 884 clks[pll_m] = clk; 885 886 /* PLLM_OUT1 */ 887 clk = tegra_clk_register_divider("pll_m_out1_div", "pll_m", 888 clk_base + PLLM_OUT, 0, TEGRA_DIVIDER_ROUND_UP, 889 8, 8, 1, NULL); 890 clk = tegra_clk_register_pll_out("pll_m_out1", "pll_m_out1_div", 891 clk_base + PLLM_OUT, 1, 0, CLK_IGNORE_UNUSED | 892 CLK_SET_RATE_PARENT, 0, NULL); 893 clk_register_clkdev(clk, "pll_m_out1", NULL); 894 clks[pll_m_out1] = clk; 895 896 /* PLLX */ 897 clk = tegra_clk_register_pll("pll_x", "pll_ref", clk_base, pmc_base, 0, 898 &pll_x_params, NULL); 899 clk_register_clkdev(clk, "pll_x", NULL); 900 clks[pll_x] = clk; 901 902 /* PLLX_OUT0 */ 903 clk = clk_register_fixed_factor(NULL, "pll_x_out0", "pll_x", 904 CLK_SET_RATE_PARENT, 1, 2); 905 clk_register_clkdev(clk, "pll_x_out0", NULL); 906 clks[pll_x_out0] = clk; 907 908 /* PLLU */ 909 clk = tegra_clk_register_pll("pll_u", "pll_ref", clk_base, pmc_base, 0, 910 &pll_u_params, NULL); 911 clk_register_clkdev(clk, "pll_u", NULL); 912 clks[pll_u] = clk; 913 914 tegra30_utmi_param_configure(); 915 916 /* PLLD */ 917 clk = tegra_clk_register_pll("pll_d", "pll_ref", clk_base, pmc_base, 0, 918 &pll_d_params, &pll_d_lock); 919 clk_register_clkdev(clk, "pll_d", NULL); 920 clks[pll_d] = clk; 921 922 /* PLLD_OUT0 */ 923 clk = clk_register_fixed_factor(NULL, "pll_d_out0", "pll_d", 924 CLK_SET_RATE_PARENT, 1, 2); 925 clk_register_clkdev(clk, "pll_d_out0", NULL); 926 clks[pll_d_out0] = clk; 927 928 /* PLLD2 */ 929 clk = tegra_clk_register_pll("pll_d2", "pll_ref", clk_base, pmc_base, 0, 930 &pll_d2_params, NULL); 931 clk_register_clkdev(clk, "pll_d2", NULL); 932 clks[pll_d2] = clk; 933 934 /* PLLD2_OUT0 */ 935 clk = clk_register_fixed_factor(NULL, "pll_d2_out0", "pll_d2", 936 CLK_SET_RATE_PARENT, 1, 2); 937 clk_register_clkdev(clk, "pll_d2_out0", NULL); 938 clks[pll_d2_out0] = clk; 939 940 /* PLLA */ 941 clk = tegra_clk_register_pll("pll_a", "pll_p_out1", clk_base, pmc_base, 942 0, &pll_a_params, NULL); 943 clk_register_clkdev(clk, "pll_a", NULL); 944 clks[pll_a] = clk; 945 946 /* PLLA_OUT0 */ 947 clk = tegra_clk_register_divider("pll_a_out0_div", "pll_a", 948 clk_base + PLLA_OUT, 0, TEGRA_DIVIDER_ROUND_UP, 949 8, 8, 1, NULL); 950 clk = tegra_clk_register_pll_out("pll_a_out0", "pll_a_out0_div", 951 clk_base + PLLA_OUT, 1, 0, CLK_IGNORE_UNUSED | 952 CLK_SET_RATE_PARENT, 0, NULL); 953 clk_register_clkdev(clk, "pll_a_out0", NULL); 954 clks[pll_a_out0] = clk; 955 956 /* PLLE */ 957 clk = clk_register_mux(NULL, "pll_e_mux", pll_e_parents, 958 ARRAY_SIZE(pll_e_parents), 959 CLK_SET_RATE_NO_REPARENT, 960 clk_base + PLLE_AUX, 2, 1, 0, NULL); 961 clk = tegra_clk_register_plle("pll_e", "pll_e_mux", clk_base, pmc_base, 962 CLK_GET_RATE_NOCACHE, &pll_e_params, NULL); 963 clk_register_clkdev(clk, "pll_e", NULL); 964 clks[pll_e] = clk; 965} 966 967static const char *mux_audio_sync_clk[] = { "spdif_in_sync", "i2s0_sync", 968 "i2s1_sync", "i2s2_sync", "i2s3_sync", "i2s4_sync", "vimclk_sync",}; 969static const char *clk_out1_parents[] = { "clk_m", "clk_m_div2", 970 "clk_m_div4", "extern1", }; 971static const char *clk_out2_parents[] = { "clk_m", "clk_m_div2", 972 "clk_m_div4", "extern2", }; 973static const char *clk_out3_parents[] = { "clk_m", "clk_m_div2", 974 "clk_m_div4", "extern3", }; 975 976static void __init tegra30_audio_clk_init(void) 977{ 978 struct clk *clk; 979 980 /* spdif_in_sync */ 981 clk = tegra_clk_register_sync_source("spdif_in_sync", 24000000, 982 24000000); 983 clk_register_clkdev(clk, "spdif_in_sync", NULL); 984 clks[spdif_in_sync] = clk; 985 986 /* i2s0_sync */ 987 clk = tegra_clk_register_sync_source("i2s0_sync", 24000000, 24000000); 988 clk_register_clkdev(clk, "i2s0_sync", NULL); 989 clks[i2s0_sync] = clk; 990 991 /* i2s1_sync */ 992 clk = tegra_clk_register_sync_source("i2s1_sync", 24000000, 24000000); 993 clk_register_clkdev(clk, "i2s1_sync", NULL); 994 clks[i2s1_sync] = clk; 995 996 /* i2s2_sync */ 997 clk = tegra_clk_register_sync_source("i2s2_sync", 24000000, 24000000); 998 clk_register_clkdev(clk, "i2s2_sync", NULL); 999 clks[i2s2_sync] = clk; 1000 1001 /* i2s3_sync */ 1002 clk = tegra_clk_register_sync_source("i2s3_sync", 24000000, 24000000); 1003 clk_register_clkdev(clk, "i2s3_sync", NULL); 1004 clks[i2s3_sync] = clk; 1005 1006 /* i2s4_sync */ 1007 clk = tegra_clk_register_sync_source("i2s4_sync", 24000000, 24000000); 1008 clk_register_clkdev(clk, "i2s4_sync", NULL); 1009 clks[i2s4_sync] = clk; 1010 1011 /* vimclk_sync */ 1012 clk = tegra_clk_register_sync_source("vimclk_sync", 24000000, 24000000); 1013 clk_register_clkdev(clk, "vimclk_sync", NULL); 1014 clks[vimclk_sync] = clk; 1015 1016 /* audio0 */ 1017 clk = clk_register_mux(NULL, "audio0_mux", mux_audio_sync_clk, 1018 ARRAY_SIZE(mux_audio_sync_clk), 1019 CLK_SET_RATE_NO_REPARENT, 1020 clk_base + AUDIO_SYNC_CLK_I2S0, 0, 3, 0, NULL); 1021 clk = clk_register_gate(NULL, "audio0", "audio0_mux", 0, 1022 clk_base + AUDIO_SYNC_CLK_I2S0, 4, 1023 CLK_GATE_SET_TO_DISABLE, NULL); 1024 clk_register_clkdev(clk, "audio0", NULL); 1025 clks[audio0] = clk; 1026 1027 /* audio1 */ 1028 clk = clk_register_mux(NULL, "audio1_mux", mux_audio_sync_clk, 1029 ARRAY_SIZE(mux_audio_sync_clk), 1030 CLK_SET_RATE_NO_REPARENT, 1031 clk_base + AUDIO_SYNC_CLK_I2S1, 0, 3, 0, NULL); 1032 clk = clk_register_gate(NULL, "audio1", "audio1_mux", 0, 1033 clk_base + AUDIO_SYNC_CLK_I2S1, 4, 1034 CLK_GATE_SET_TO_DISABLE, NULL); 1035 clk_register_clkdev(clk, "audio1", NULL); 1036 clks[audio1] = clk; 1037 1038 /* audio2 */ 1039 clk = clk_register_mux(NULL, "audio2_mux", mux_audio_sync_clk, 1040 ARRAY_SIZE(mux_audio_sync_clk), 1041 CLK_SET_RATE_NO_REPARENT, 1042 clk_base + AUDIO_SYNC_CLK_I2S2, 0, 3, 0, NULL); 1043 clk = clk_register_gate(NULL, "audio2", "audio2_mux", 0, 1044 clk_base + AUDIO_SYNC_CLK_I2S2, 4, 1045 CLK_GATE_SET_TO_DISABLE, NULL); 1046 clk_register_clkdev(clk, "audio2", NULL); 1047 clks[audio2] = clk; 1048 1049 /* audio3 */ 1050 clk = clk_register_mux(NULL, "audio3_mux", mux_audio_sync_clk, 1051 ARRAY_SIZE(mux_audio_sync_clk), 1052 CLK_SET_RATE_NO_REPARENT, 1053 clk_base + AUDIO_SYNC_CLK_I2S3, 0, 3, 0, NULL); 1054 clk = clk_register_gate(NULL, "audio3", "audio3_mux", 0, 1055 clk_base + AUDIO_SYNC_CLK_I2S3, 4, 1056 CLK_GATE_SET_TO_DISABLE, NULL); 1057 clk_register_clkdev(clk, "audio3", NULL); 1058 clks[audio3] = clk; 1059 1060 /* audio4 */ 1061 clk = clk_register_mux(NULL, "audio4_mux", mux_audio_sync_clk, 1062 ARRAY_SIZE(mux_audio_sync_clk), 1063 CLK_SET_RATE_NO_REPARENT, 1064 clk_base + AUDIO_SYNC_CLK_I2S4, 0, 3, 0, NULL); 1065 clk = clk_register_gate(NULL, "audio4", "audio4_mux", 0, 1066 clk_base + AUDIO_SYNC_CLK_I2S4, 4, 1067 CLK_GATE_SET_TO_DISABLE, NULL); 1068 clk_register_clkdev(clk, "audio4", NULL); 1069 clks[audio4] = clk; 1070 1071 /* spdif */ 1072 clk = clk_register_mux(NULL, "spdif_mux", mux_audio_sync_clk, 1073 ARRAY_SIZE(mux_audio_sync_clk), 1074 CLK_SET_RATE_NO_REPARENT, 1075 clk_base + AUDIO_SYNC_CLK_SPDIF, 0, 3, 0, NULL); 1076 clk = clk_register_gate(NULL, "spdif", "spdif_mux", 0, 1077 clk_base + AUDIO_SYNC_CLK_SPDIF, 4, 1078 CLK_GATE_SET_TO_DISABLE, NULL); 1079 clk_register_clkdev(clk, "spdif", NULL); 1080 clks[spdif] = clk; 1081 1082 /* audio0_2x */ 1083 clk = clk_register_fixed_factor(NULL, "audio0_doubler", "audio0", 1084 CLK_SET_RATE_PARENT, 2, 1); 1085 clk = tegra_clk_register_divider("audio0_div", "audio0_doubler", 1086 clk_base + AUDIO_SYNC_DOUBLER, 0, 0, 24, 1, 0, 1087 &clk_doubler_lock); 1088 clk = tegra_clk_register_periph_gate("audio0_2x", "audio0_div", 1089 TEGRA_PERIPH_NO_RESET, clk_base, 1090 CLK_SET_RATE_PARENT, 113, 1091 periph_clk_enb_refcnt); 1092 clk_register_clkdev(clk, "audio0_2x", NULL); 1093 clks[audio0_2x] = clk; 1094 1095 /* audio1_2x */ 1096 clk = clk_register_fixed_factor(NULL, "audio1_doubler", "audio1", 1097 CLK_SET_RATE_PARENT, 2, 1); 1098 clk = tegra_clk_register_divider("audio1_div", "audio1_doubler", 1099 clk_base + AUDIO_SYNC_DOUBLER, 0, 0, 25, 1, 0, 1100 &clk_doubler_lock); 1101 clk = tegra_clk_register_periph_gate("audio1_2x", "audio1_div", 1102 TEGRA_PERIPH_NO_RESET, clk_base, 1103 CLK_SET_RATE_PARENT, 114, 1104 periph_clk_enb_refcnt); 1105 clk_register_clkdev(clk, "audio1_2x", NULL); 1106 clks[audio1_2x] = clk; 1107 1108 /* audio2_2x */ 1109 clk = clk_register_fixed_factor(NULL, "audio2_doubler", "audio2", 1110 CLK_SET_RATE_PARENT, 2, 1); 1111 clk = tegra_clk_register_divider("audio2_div", "audio2_doubler", 1112 clk_base + AUDIO_SYNC_DOUBLER, 0, 0, 26, 1, 0, 1113 &clk_doubler_lock); 1114 clk = tegra_clk_register_periph_gate("audio2_2x", "audio2_div", 1115 TEGRA_PERIPH_NO_RESET, clk_base, 1116 CLK_SET_RATE_PARENT, 115, 1117 periph_clk_enb_refcnt); 1118 clk_register_clkdev(clk, "audio2_2x", NULL); 1119 clks[audio2_2x] = clk; 1120 1121 /* audio3_2x */ 1122 clk = clk_register_fixed_factor(NULL, "audio3_doubler", "audio3", 1123 CLK_SET_RATE_PARENT, 2, 1); 1124 clk = tegra_clk_register_divider("audio3_div", "audio3_doubler", 1125 clk_base + AUDIO_SYNC_DOUBLER, 0, 0, 27, 1, 0, 1126 &clk_doubler_lock); 1127 clk = tegra_clk_register_periph_gate("audio3_2x", "audio3_div", 1128 TEGRA_PERIPH_NO_RESET, clk_base, 1129 CLK_SET_RATE_PARENT, 116, 1130 periph_clk_enb_refcnt); 1131 clk_register_clkdev(clk, "audio3_2x", NULL); 1132 clks[audio3_2x] = clk; 1133 1134 /* audio4_2x */ 1135 clk = clk_register_fixed_factor(NULL, "audio4_doubler", "audio4", 1136 CLK_SET_RATE_PARENT, 2, 1); 1137 clk = tegra_clk_register_divider("audio4_div", "audio4_doubler", 1138 clk_base + AUDIO_SYNC_DOUBLER, 0, 0, 28, 1, 0, 1139 &clk_doubler_lock); 1140 clk = tegra_clk_register_periph_gate("audio4_2x", "audio4_div", 1141 TEGRA_PERIPH_NO_RESET, clk_base, 1142 CLK_SET_RATE_PARENT, 117, 1143 periph_clk_enb_refcnt); 1144 clk_register_clkdev(clk, "audio4_2x", NULL); 1145 clks[audio4_2x] = clk; 1146 1147 /* spdif_2x */ 1148 clk = clk_register_fixed_factor(NULL, "spdif_doubler", "spdif", 1149 CLK_SET_RATE_PARENT, 2, 1); 1150 clk = tegra_clk_register_divider("spdif_div", "spdif_doubler", 1151 clk_base + AUDIO_SYNC_DOUBLER, 0, 0, 29, 1, 0, 1152 &clk_doubler_lock); 1153 clk = tegra_clk_register_periph_gate("spdif_2x", "spdif_div", 1154 TEGRA_PERIPH_NO_RESET, clk_base, 1155 CLK_SET_RATE_PARENT, 118, 1156 periph_clk_enb_refcnt); 1157 clk_register_clkdev(clk, "spdif_2x", NULL); 1158 clks[spdif_2x] = clk; 1159} 1160 1161static void __init tegra30_pmc_clk_init(void) 1162{ 1163 struct clk *clk; 1164 1165 /* clk_out_1 */ 1166 clk = clk_register_mux(NULL, "clk_out_1_mux", clk_out1_parents, 1167 ARRAY_SIZE(clk_out1_parents), 1168 CLK_SET_RATE_NO_REPARENT, 1169 pmc_base + PMC_CLK_OUT_CNTRL, 6, 3, 0, 1170 &clk_out_lock); 1171 clks[clk_out_1_mux] = clk; 1172 clk = clk_register_gate(NULL, "clk_out_1", "clk_out_1_mux", 0, 1173 pmc_base + PMC_CLK_OUT_CNTRL, 2, 0, 1174 &clk_out_lock); 1175 clk_register_clkdev(clk, "extern1", "clk_out_1"); 1176 clks[clk_out_1] = clk; 1177 1178 /* clk_out_2 */ 1179 clk = clk_register_mux(NULL, "clk_out_2_mux", clk_out2_parents, 1180 ARRAY_SIZE(clk_out2_parents), 1181 CLK_SET_RATE_NO_REPARENT, 1182 pmc_base + PMC_CLK_OUT_CNTRL, 14, 3, 0, 1183 &clk_out_lock); 1184 clk = clk_register_gate(NULL, "clk_out_2", "clk_out_2_mux", 0, 1185 pmc_base + PMC_CLK_OUT_CNTRL, 10, 0, 1186 &clk_out_lock); 1187 clk_register_clkdev(clk, "extern2", "clk_out_2"); 1188 clks[clk_out_2] = clk; 1189 1190 /* clk_out_3 */ 1191 clk = clk_register_mux(NULL, "clk_out_3_mux", clk_out3_parents, 1192 ARRAY_SIZE(clk_out3_parents), 1193 CLK_SET_RATE_NO_REPARENT, 1194 pmc_base + PMC_CLK_OUT_CNTRL, 22, 3, 0, 1195 &clk_out_lock); 1196 clk = clk_register_gate(NULL, "clk_out_3", "clk_out_3_mux", 0, 1197 pmc_base + PMC_CLK_OUT_CNTRL, 18, 0, 1198 &clk_out_lock); 1199 clk_register_clkdev(clk, "extern3", "clk_out_3"); 1200 clks[clk_out_3] = clk; 1201 1202 /* blink */ 1203 writel_relaxed(0, pmc_base + PMC_BLINK_TIMER); 1204 clk = clk_register_gate(NULL, "blink_override", "clk_32k", 0, 1205 pmc_base + PMC_DPD_PADS_ORIDE, 1206 PMC_DPD_PADS_ORIDE_BLINK_ENB, 0, NULL); 1207 clk = clk_register_gate(NULL, "blink", "blink_override", 0, 1208 pmc_base + PMC_CTRL, 1209 PMC_CTRL_BLINK_ENB, 0, NULL); 1210 clk_register_clkdev(clk, "blink", NULL); 1211 clks[blink] = clk; 1212 1213} 1214 1215static const char *cclk_g_parents[] = { "clk_m", "pll_c", "clk_32k", "pll_m", 1216 "pll_p_cclkg", "pll_p_out4_cclkg", 1217 "pll_p_out3_cclkg", "unused", "pll_x" }; 1218static const char *cclk_lp_parents[] = { "clk_m", "pll_c", "clk_32k", "pll_m", 1219 "pll_p_cclklp", "pll_p_out4_cclklp", 1220 "pll_p_out3_cclklp", "unused", "pll_x", 1221 "pll_x_out0" }; 1222static const char *sclk_parents[] = { "clk_m", "pll_c_out1", "pll_p_out4", 1223 "pll_p_out3", "pll_p_out2", "unused", 1224 "clk_32k", "pll_m_out1" }; 1225 1226static void __init tegra30_super_clk_init(void) 1227{ 1228 struct clk *clk; 1229 1230 /* 1231 * Clock input to cclk_g divided from pll_p using 1232 * U71 divider of cclk_g. 1233 */ 1234 clk = tegra_clk_register_divider("pll_p_cclkg", "pll_p", 1235 clk_base + SUPER_CCLKG_DIVIDER, 0, 1236 TEGRA_DIVIDER_INT, 16, 8, 1, NULL); 1237 clk_register_clkdev(clk, "pll_p_cclkg", NULL); 1238 1239 /* 1240 * Clock input to cclk_g divided from pll_p_out3 using 1241 * U71 divider of cclk_g. 1242 */ 1243 clk = tegra_clk_register_divider("pll_p_out3_cclkg", "pll_p_out3", 1244 clk_base + SUPER_CCLKG_DIVIDER, 0, 1245 TEGRA_DIVIDER_INT, 16, 8, 1, NULL); 1246 clk_register_clkdev(clk, "pll_p_out3_cclkg", NULL); 1247 1248 /* 1249 * Clock input to cclk_g divided from pll_p_out4 using 1250 * U71 divider of cclk_g. 1251 */ 1252 clk = tegra_clk_register_divider("pll_p_out4_cclkg", "pll_p_out4", 1253 clk_base + SUPER_CCLKG_DIVIDER, 0, 1254 TEGRA_DIVIDER_INT, 16, 8, 1, NULL); 1255 clk_register_clkdev(clk, "pll_p_out4_cclkg", NULL); 1256 1257 /* CCLKG */ 1258 clk = tegra_clk_register_super_mux("cclk_g", cclk_g_parents, 1259 ARRAY_SIZE(cclk_g_parents), 1260 CLK_SET_RATE_PARENT, 1261 clk_base + CCLKG_BURST_POLICY, 1262 0, 4, 0, 0, NULL); 1263 clk_register_clkdev(clk, "cclk_g", NULL); 1264 clks[cclk_g] = clk; 1265 1266 /* 1267 * Clock input to cclk_lp divided from pll_p using 1268 * U71 divider of cclk_lp. 1269 */ 1270 clk = tegra_clk_register_divider("pll_p_cclklp", "pll_p", 1271 clk_base + SUPER_CCLKLP_DIVIDER, 0, 1272 TEGRA_DIVIDER_INT, 16, 8, 1, NULL); 1273 clk_register_clkdev(clk, "pll_p_cclklp", NULL); 1274 1275 /* 1276 * Clock input to cclk_lp divided from pll_p_out3 using 1277 * U71 divider of cclk_lp. 1278 */ 1279 clk = tegra_clk_register_divider("pll_p_out3_cclklp", "pll_p_out3", 1280 clk_base + SUPER_CCLKG_DIVIDER, 0, 1281 TEGRA_DIVIDER_INT, 16, 8, 1, NULL); 1282 clk_register_clkdev(clk, "pll_p_out3_cclklp", NULL); 1283 1284 /* 1285 * Clock input to cclk_lp divided from pll_p_out4 using 1286 * U71 divider of cclk_lp. 1287 */ 1288 clk = tegra_clk_register_divider("pll_p_out4_cclklp", "pll_p_out4", 1289 clk_base + SUPER_CCLKLP_DIVIDER, 0, 1290 TEGRA_DIVIDER_INT, 16, 8, 1, NULL); 1291 clk_register_clkdev(clk, "pll_p_out4_cclklp", NULL); 1292 1293 /* CCLKLP */ 1294 clk = tegra_clk_register_super_mux("cclk_lp", cclk_lp_parents, 1295 ARRAY_SIZE(cclk_lp_parents), 1296 CLK_SET_RATE_PARENT, 1297 clk_base + CCLKLP_BURST_POLICY, 1298 TEGRA_DIVIDER_2, 4, 8, 9, 1299 NULL); 1300 clk_register_clkdev(clk, "cclk_lp", NULL); 1301 clks[cclk_lp] = clk; 1302 1303 /* SCLK */ 1304 clk = tegra_clk_register_super_mux("sclk", sclk_parents, 1305 ARRAY_SIZE(sclk_parents), 1306 CLK_SET_RATE_PARENT, 1307 clk_base + SCLK_BURST_POLICY, 1308 0, 4, 0, 0, NULL); 1309 clk_register_clkdev(clk, "sclk", NULL); 1310 clks[sclk] = clk; 1311 1312 /* HCLK */ 1313 clk = clk_register_divider(NULL, "hclk_div", "sclk", 0, 1314 clk_base + SYSTEM_CLK_RATE, 4, 2, 0, 1315 &sysrate_lock); 1316 clk = clk_register_gate(NULL, "hclk", "hclk_div", CLK_SET_RATE_PARENT, 1317 clk_base + SYSTEM_CLK_RATE, 7, 1318 CLK_GATE_SET_TO_DISABLE, &sysrate_lock); 1319 clk_register_clkdev(clk, "hclk", NULL); 1320 clks[hclk] = clk; 1321 1322 /* PCLK */ 1323 clk = clk_register_divider(NULL, "pclk_div", "hclk", 0, 1324 clk_base + SYSTEM_CLK_RATE, 0, 2, 0, 1325 &sysrate_lock); 1326 clk = clk_register_gate(NULL, "pclk", "pclk_div", CLK_SET_RATE_PARENT, 1327 clk_base + SYSTEM_CLK_RATE, 3, 1328 CLK_GATE_SET_TO_DISABLE, &sysrate_lock); 1329 clk_register_clkdev(clk, "pclk", NULL); 1330 clks[pclk] = clk; 1331 1332 /* twd */ 1333 clk = clk_register_fixed_factor(NULL, "twd", "cclk_g", 1334 CLK_SET_RATE_PARENT, 1, 2); 1335 clk_register_clkdev(clk, "twd", NULL); 1336 clks[twd] = clk; 1337} 1338 1339static const char *mux_pllacp_clkm[] = { "pll_a_out0", "unused", "pll_p", 1340 "clk_m" }; 1341static const char *mux_pllpcm_clkm[] = { "pll_p", "pll_c", "pll_m", "clk_m" }; 1342static const char *mux_pllmcp_clkm[] = { "pll_m", "pll_c", "pll_p", "clk_m" }; 1343static const char *i2s0_parents[] = { "pll_a_out0", "audio0_2x", "pll_p", 1344 "clk_m" }; 1345static const char *i2s1_parents[] = { "pll_a_out0", "audio1_2x", "pll_p", 1346 "clk_m" }; 1347static const char *i2s2_parents[] = { "pll_a_out0", "audio2_2x", "pll_p", 1348 "clk_m" }; 1349static const char *i2s3_parents[] = { "pll_a_out0", "audio3_2x", "pll_p", 1350 "clk_m" }; 1351static const char *i2s4_parents[] = { "pll_a_out0", "audio4_2x", "pll_p", 1352 "clk_m" }; 1353static const char *spdif_out_parents[] = { "pll_a_out0", "spdif_2x", "pll_p", 1354 "clk_m" }; 1355static const char *spdif_in_parents[] = { "pll_p", "pll_c", "pll_m" }; 1356static const char *mux_pllpc_clk32k_clkm[] = { "pll_p", "pll_c", "clk_32k", 1357 "clk_m" }; 1358static const char *mux_pllpc_clkm_clk32k[] = { "pll_p", "pll_c", "clk_m", 1359 "clk_32k" }; 1360static const char *mux_pllmcpa[] = { "pll_m", "pll_c", "pll_p", "pll_a_out0" }; 1361static const char *mux_pllpdc_clkm[] = { "pll_p", "pll_d_out0", "pll_c", 1362 "clk_m" }; 1363static const char *mux_pllp_clkm[] = { "pll_p", "unused", "unused", "clk_m" }; 1364static const char *mux_pllpmdacd2_clkm[] = { "pll_p", "pll_m", "pll_d_out0", 1365 "pll_a_out0", "pll_c", 1366 "pll_d2_out0", "clk_m" }; 1367static const char *mux_plla_clk32k_pllp_clkm_plle[] = { "pll_a_out0", 1368 "clk_32k", "pll_p", 1369 "clk_m", "pll_e" }; 1370static const char *mux_plld_out0_plld2_out0[] = { "pll_d_out0", 1371 "pll_d2_out0" }; 1372 1373static struct tegra_periph_init_data tegra_periph_clk_list[] = { 1374 TEGRA_INIT_DATA_MUX("i2s0", NULL, "tegra30-i2s.0", i2s0_parents, CLK_SOURCE_I2S0, 30, TEGRA_PERIPH_ON_APB, i2s0), 1375 TEGRA_INIT_DATA_MUX("i2s1", NULL, "tegra30-i2s.1", i2s1_parents, CLK_SOURCE_I2S1, 11, TEGRA_PERIPH_ON_APB, i2s1), 1376 TEGRA_INIT_DATA_MUX("i2s2", NULL, "tegra30-i2s.2", i2s2_parents, CLK_SOURCE_I2S2, 18, TEGRA_PERIPH_ON_APB, i2s2), 1377 TEGRA_INIT_DATA_MUX("i2s3", NULL, "tegra30-i2s.3", i2s3_parents, CLK_SOURCE_I2S3, 101, TEGRA_PERIPH_ON_APB, i2s3), 1378 TEGRA_INIT_DATA_MUX("i2s4", NULL, "tegra30-i2s.4", i2s4_parents, CLK_SOURCE_I2S4, 102, TEGRA_PERIPH_ON_APB, i2s4), 1379 TEGRA_INIT_DATA_MUX("spdif_out", "spdif_out", "tegra30-spdif", spdif_out_parents, CLK_SOURCE_SPDIF_OUT, 10, TEGRA_PERIPH_ON_APB, spdif_out), 1380 TEGRA_INIT_DATA_MUX("spdif_in", "spdif_in", "tegra30-spdif", spdif_in_parents, CLK_SOURCE_SPDIF_IN, 10, TEGRA_PERIPH_ON_APB, spdif_in), 1381 TEGRA_INIT_DATA_MUX("d_audio", "d_audio", "tegra30-ahub", mux_pllacp_clkm, CLK_SOURCE_D_AUDIO, 106, 0, d_audio), 1382 TEGRA_INIT_DATA_MUX("dam0", NULL, "tegra30-dam.0", mux_pllacp_clkm, CLK_SOURCE_DAM0, 108, 0, dam0), 1383 TEGRA_INIT_DATA_MUX("dam1", NULL, "tegra30-dam.1", mux_pllacp_clkm, CLK_SOURCE_DAM1, 109, 0, dam1), 1384 TEGRA_INIT_DATA_MUX("dam2", NULL, "tegra30-dam.2", mux_pllacp_clkm, CLK_SOURCE_DAM2, 110, 0, dam2), 1385 TEGRA_INIT_DATA_MUX("hda", "hda", "tegra30-hda", mux_pllpcm_clkm, CLK_SOURCE_HDA, 125, 0, hda), 1386 TEGRA_INIT_DATA_MUX("hda2codec_2x", "hda2codec", "tegra30-hda", mux_pllpcm_clkm, CLK_SOURCE_HDA2CODEC_2X, 111, 0, hda2codec_2x), 1387 TEGRA_INIT_DATA_MUX("sbc1", NULL, "spi_tegra.0", mux_pllpcm_clkm, CLK_SOURCE_SBC1, 41, TEGRA_PERIPH_ON_APB, sbc1), 1388 TEGRA_INIT_DATA_MUX("sbc2", NULL, "spi_tegra.1", mux_pllpcm_clkm, CLK_SOURCE_SBC2, 44, TEGRA_PERIPH_ON_APB, sbc2), 1389 TEGRA_INIT_DATA_MUX("sbc3", NULL, "spi_tegra.2", mux_pllpcm_clkm, CLK_SOURCE_SBC3, 46, TEGRA_PERIPH_ON_APB, sbc3), 1390 TEGRA_INIT_DATA_MUX("sbc4", NULL, "spi_tegra.3", mux_pllpcm_clkm, CLK_SOURCE_SBC4, 68, TEGRA_PERIPH_ON_APB, sbc4), 1391 TEGRA_INIT_DATA_MUX("sbc5", NULL, "spi_tegra.4", mux_pllpcm_clkm, CLK_SOURCE_SBC5, 104, TEGRA_PERIPH_ON_APB, sbc5), 1392 TEGRA_INIT_DATA_MUX("sbc6", NULL, "spi_tegra.5", mux_pllpcm_clkm, CLK_SOURCE_SBC6, 105, TEGRA_PERIPH_ON_APB, sbc6), 1393 TEGRA_INIT_DATA_MUX("sata_oob", NULL, "tegra_sata_oob", mux_pllpcm_clkm, CLK_SOURCE_SATA_OOB, 123, TEGRA_PERIPH_ON_APB, sata_oob), 1394 TEGRA_INIT_DATA_MUX("sata", NULL, "tegra_sata", mux_pllpcm_clkm, CLK_SOURCE_SATA, 124, TEGRA_PERIPH_ON_APB, sata), 1395 TEGRA_INIT_DATA_MUX("ndflash", NULL, "tegra_nand", mux_pllpcm_clkm, CLK_SOURCE_NDFLASH, 13, TEGRA_PERIPH_ON_APB, ndflash), 1396 TEGRA_INIT_DATA_MUX("ndspeed", NULL, "tegra_nand_speed", mux_pllpcm_clkm, CLK_SOURCE_NDSPEED, 80, TEGRA_PERIPH_ON_APB, ndspeed), 1397 TEGRA_INIT_DATA_MUX("vfir", NULL, "vfir", mux_pllpcm_clkm, CLK_SOURCE_VFIR, 7, TEGRA_PERIPH_ON_APB, vfir), 1398 TEGRA_INIT_DATA_MUX("csite", NULL, "csite", mux_pllpcm_clkm, CLK_SOURCE_CSITE, 73, TEGRA_PERIPH_ON_APB, csite), 1399 TEGRA_INIT_DATA_MUX("la", NULL, "la", mux_pllpcm_clkm, CLK_SOURCE_LA, 76, TEGRA_PERIPH_ON_APB, la), 1400 TEGRA_INIT_DATA_MUX("owr", NULL, "tegra_w1", mux_pllpcm_clkm, CLK_SOURCE_OWR, 71, TEGRA_PERIPH_ON_APB, owr), 1401 TEGRA_INIT_DATA_MUX("mipi", NULL, "mipi", mux_pllpcm_clkm, CLK_SOURCE_MIPI, 50, TEGRA_PERIPH_ON_APB, mipi), 1402 TEGRA_INIT_DATA_MUX("tsensor", NULL, "tegra-tsensor", mux_pllpc_clkm_clk32k, CLK_SOURCE_TSENSOR, 100, TEGRA_PERIPH_ON_APB, tsensor), 1403 TEGRA_INIT_DATA_MUX("i2cslow", NULL, "i2cslow", mux_pllpc_clk32k_clkm, CLK_SOURCE_I2CSLOW, 81, TEGRA_PERIPH_ON_APB, i2cslow), 1404 TEGRA_INIT_DATA_INT("vde", NULL, "vde", mux_pllpcm_clkm, CLK_SOURCE_VDE, 61, 0, vde), 1405 TEGRA_INIT_DATA_INT("vi", "vi", "tegra_camera", mux_pllmcpa, CLK_SOURCE_VI, 20, 0, vi), 1406 TEGRA_INIT_DATA_INT("epp", NULL, "epp", mux_pllmcpa, CLK_SOURCE_EPP, 19, 0, epp), 1407 TEGRA_INIT_DATA_INT("mpe", NULL, "mpe", mux_pllmcpa, CLK_SOURCE_MPE, 60, 0, mpe), 1408 TEGRA_INIT_DATA_INT("host1x", NULL, "host1x", mux_pllmcpa, CLK_SOURCE_HOST1X, 28, 0, host1x), 1409 TEGRA_INIT_DATA_INT("3d", NULL, "3d", mux_pllmcpa, CLK_SOURCE_3D, 24, TEGRA_PERIPH_MANUAL_RESET, gr3d), 1410 TEGRA_INIT_DATA_INT("3d2", NULL, "3d2", mux_pllmcpa, CLK_SOURCE_3D2, 98, TEGRA_PERIPH_MANUAL_RESET, gr3d2), 1411 TEGRA_INIT_DATA_INT("2d", NULL, "2d", mux_pllmcpa, CLK_SOURCE_2D, 21, 0, gr2d), 1412 TEGRA_INIT_DATA_INT("se", NULL, "se", mux_pllpcm_clkm, CLK_SOURCE_SE, 127, 0, se), 1413 TEGRA_INIT_DATA_MUX("mselect", NULL, "mselect", mux_pllp_clkm, CLK_SOURCE_MSELECT, 99, 0, mselect), 1414 TEGRA_INIT_DATA_MUX("nor", NULL, "tegra-nor", mux_pllpcm_clkm, CLK_SOURCE_NOR, 42, 0, nor), 1415 TEGRA_INIT_DATA_MUX("sdmmc1", NULL, "sdhci-tegra.0", mux_pllpcm_clkm, CLK_SOURCE_SDMMC1, 14, 0, sdmmc1), 1416 TEGRA_INIT_DATA_MUX("sdmmc2", NULL, "sdhci-tegra.1", mux_pllpcm_clkm, CLK_SOURCE_SDMMC2, 9, 0, sdmmc2), 1417 TEGRA_INIT_DATA_MUX("sdmmc3", NULL, "sdhci-tegra.2", mux_pllpcm_clkm, CLK_SOURCE_SDMMC3, 69, 0, sdmmc3), 1418 TEGRA_INIT_DATA_MUX("sdmmc4", NULL, "sdhci-tegra.3", mux_pllpcm_clkm, CLK_SOURCE_SDMMC4, 15, 0, sdmmc4), 1419 TEGRA_INIT_DATA_MUX("cve", NULL, "cve", mux_pllpdc_clkm, CLK_SOURCE_CVE, 49, 0, cve), 1420 TEGRA_INIT_DATA_MUX("tvo", NULL, "tvo", mux_pllpdc_clkm, CLK_SOURCE_TVO, 49, 0, tvo), 1421 TEGRA_INIT_DATA_MUX("tvdac", NULL, "tvdac", mux_pllpdc_clkm, CLK_SOURCE_TVDAC, 53, 0, tvdac), 1422 TEGRA_INIT_DATA_MUX("actmon", NULL, "actmon", mux_pllpc_clk32k_clkm, CLK_SOURCE_ACTMON, 119, 0, actmon), 1423 TEGRA_INIT_DATA_MUX("vi_sensor", "vi_sensor", "tegra_camera", mux_pllmcpa, CLK_SOURCE_VI_SENSOR, 20, TEGRA_PERIPH_NO_RESET, vi_sensor), 1424 TEGRA_INIT_DATA_DIV16("i2c1", "div-clk", "tegra-i2c.0", mux_pllp_clkm, CLK_SOURCE_I2C1, 12, TEGRA_PERIPH_ON_APB, i2c1), 1425 TEGRA_INIT_DATA_DIV16("i2c2", "div-clk", "tegra-i2c.1", mux_pllp_clkm, CLK_SOURCE_I2C2, 54, TEGRA_PERIPH_ON_APB, i2c2), 1426 TEGRA_INIT_DATA_DIV16("i2c3", "div-clk", "tegra-i2c.2", mux_pllp_clkm, CLK_SOURCE_I2C3, 67, TEGRA_PERIPH_ON_APB, i2c3), 1427 TEGRA_INIT_DATA_DIV16("i2c4", "div-clk", "tegra-i2c.3", mux_pllp_clkm, CLK_SOURCE_I2C4, 103, TEGRA_PERIPH_ON_APB, i2c4), 1428 TEGRA_INIT_DATA_DIV16("i2c5", "div-clk", "tegra-i2c.4", mux_pllp_clkm, CLK_SOURCE_I2C5, 47, TEGRA_PERIPH_ON_APB, i2c5), 1429 TEGRA_INIT_DATA_UART("uarta", NULL, "tegra_uart.0", mux_pllpcm_clkm, CLK_SOURCE_UARTA, 6, uarta), 1430 TEGRA_INIT_DATA_UART("uartb", NULL, "tegra_uart.1", mux_pllpcm_clkm, CLK_SOURCE_UARTB, 7, uartb), 1431 TEGRA_INIT_DATA_UART("uartc", NULL, "tegra_uart.2", mux_pllpcm_clkm, CLK_SOURCE_UARTC, 55, uartc), 1432 TEGRA_INIT_DATA_UART("uartd", NULL, "tegra_uart.3", mux_pllpcm_clkm, CLK_SOURCE_UARTD, 65, uartd), 1433 TEGRA_INIT_DATA_UART("uarte", NULL, "tegra_uart.4", mux_pllpcm_clkm, CLK_SOURCE_UARTE, 66, uarte), 1434 TEGRA_INIT_DATA_MUX8("hdmi", NULL, "hdmi", mux_pllpmdacd2_clkm, CLK_SOURCE_HDMI, 51, 0, hdmi), 1435 TEGRA_INIT_DATA_MUX8("extern1", NULL, "extern1", mux_plla_clk32k_pllp_clkm_plle, CLK_SOURCE_EXTERN1, 120, 0, extern1), 1436 TEGRA_INIT_DATA_MUX8("extern2", NULL, "extern2", mux_plla_clk32k_pllp_clkm_plle, CLK_SOURCE_EXTERN2, 121, 0, extern2), 1437 TEGRA_INIT_DATA_MUX8("extern3", NULL, "extern3", mux_plla_clk32k_pllp_clkm_plle, CLK_SOURCE_EXTERN3, 122, 0, extern3), 1438 TEGRA_INIT_DATA("pwm", NULL, "pwm", mux_pllpc_clk32k_clkm, CLK_SOURCE_PWM, 28, 2, 0, 0, 8, 1, 0, 17, 0, pwm), 1439}; 1440 1441static struct tegra_periph_init_data tegra_periph_nodiv_clk_list[] = { 1442 TEGRA_INIT_DATA_NODIV("disp1", NULL, "tegradc.0", mux_pllpmdacd2_clkm, CLK_SOURCE_DISP1, 29, 3, 27, 0, disp1), 1443 TEGRA_INIT_DATA_NODIV("disp2", NULL, "tegradc.1", mux_pllpmdacd2_clkm, CLK_SOURCE_DISP2, 29, 3, 26, 0, disp2), 1444 TEGRA_INIT_DATA_NODIV("dsib", NULL, "tegradc.1", mux_plld_out0_plld2_out0, CLK_SOURCE_DSIB, 25, 1, 82, 0, dsib), 1445}; 1446 1447static void __init tegra30_periph_clk_init(void) 1448{ 1449 struct tegra_periph_init_data *data; 1450 struct clk *clk; 1451 int i; 1452 1453 /* apbdma */ 1454 clk = tegra_clk_register_periph_gate("apbdma", "clk_m", 0, clk_base, 0, 34, 1455 periph_clk_enb_refcnt); 1456 clk_register_clkdev(clk, NULL, "tegra-apbdma"); 1457 clks[apbdma] = clk; 1458 1459 /* rtc */ 1460 clk = tegra_clk_register_periph_gate("rtc", "clk_32k", 1461 TEGRA_PERIPH_NO_RESET | TEGRA_PERIPH_ON_APB, 1462 clk_base, 0, 4, periph_clk_enb_refcnt); 1463 clk_register_clkdev(clk, NULL, "rtc-tegra"); 1464 clks[rtc] = clk; 1465 1466 /* timer */ 1467 clk = tegra_clk_register_periph_gate("timer", "clk_m", 0, clk_base, 0, 1468 5, periph_clk_enb_refcnt); 1469 clk_register_clkdev(clk, NULL, "timer"); 1470 clks[timer] = clk; 1471 1472 /* kbc */ 1473 clk = tegra_clk_register_periph_gate("kbc", "clk_32k", 1474 TEGRA_PERIPH_NO_RESET | TEGRA_PERIPH_ON_APB, 1475 clk_base, 0, 36, periph_clk_enb_refcnt); 1476 clk_register_clkdev(clk, NULL, "tegra-kbc"); 1477 clks[kbc] = clk; 1478 1479 /* csus */ 1480 clk = tegra_clk_register_periph_gate("csus", "clk_m", 1481 TEGRA_PERIPH_NO_RESET | TEGRA_PERIPH_ON_APB, 1482 clk_base, 0, 92, periph_clk_enb_refcnt); 1483 clk_register_clkdev(clk, "csus", "tengra_camera"); 1484 clks[csus] = clk; 1485 1486 /* vcp */ 1487 clk = tegra_clk_register_periph_gate("vcp", "clk_m", 0, clk_base, 0, 29, 1488 periph_clk_enb_refcnt); 1489 clk_register_clkdev(clk, "vcp", "tegra-avp"); 1490 clks[vcp] = clk; 1491 1492 /* bsea */ 1493 clk = tegra_clk_register_periph_gate("bsea", "clk_m", 0, clk_base, 0, 1494 62, periph_clk_enb_refcnt); 1495 clk_register_clkdev(clk, "bsea", "tegra-avp"); 1496 clks[bsea] = clk; 1497 1498 /* bsev */ 1499 clk = tegra_clk_register_periph_gate("bsev", "clk_m", 0, clk_base, 0, 1500 63, periph_clk_enb_refcnt); 1501 clk_register_clkdev(clk, "bsev", "tegra-aes"); 1502 clks[bsev] = clk; 1503 1504 /* usbd */ 1505 clk = tegra_clk_register_periph_gate("usbd", "clk_m", 0, clk_base, 0, 1506 22, periph_clk_enb_refcnt); 1507 clk_register_clkdev(clk, NULL, "fsl-tegra-udc"); 1508 clks[usbd] = clk; 1509 1510 /* usb2 */ 1511 clk = tegra_clk_register_periph_gate("usb2", "clk_m", 0, clk_base, 0, 1512 58, periph_clk_enb_refcnt); 1513 clk_register_clkdev(clk, NULL, "tegra-ehci.1"); 1514 clks[usb2] = clk; 1515 1516 /* usb3 */ 1517 clk = tegra_clk_register_periph_gate("usb3", "clk_m", 0, clk_base, 0, 1518 59, periph_clk_enb_refcnt); 1519 clk_register_clkdev(clk, NULL, "tegra-ehci.2"); 1520 clks[usb3] = clk; 1521 1522 /* dsia */ 1523 clk = tegra_clk_register_periph_gate("dsia", "pll_d_out0", 0, clk_base, 1524 0, 48, periph_clk_enb_refcnt); 1525 clk_register_clkdev(clk, "dsia", "tegradc.0"); 1526 clks[dsia] = clk; 1527 1528 /* csi */ 1529 clk = tegra_clk_register_periph_gate("csi", "pll_p_out3", 0, clk_base, 1530 0, 52, periph_clk_enb_refcnt); 1531 clk_register_clkdev(clk, "csi", "tegra_camera"); 1532 clks[csi] = clk; 1533 1534 /* isp */ 1535 clk = tegra_clk_register_periph_gate("isp", "clk_m", 0, clk_base, 0, 23, 1536 periph_clk_enb_refcnt); 1537 clk_register_clkdev(clk, "isp", "tegra_camera"); 1538 clks[isp] = clk; 1539 1540 /* pcie */ 1541 clk = tegra_clk_register_periph_gate("pcie", "clk_m", 0, clk_base, 0, 1542 70, periph_clk_enb_refcnt); 1543 clk_register_clkdev(clk, "pcie", "tegra-pcie"); 1544 clks[pcie] = clk; 1545 1546 /* afi */ 1547 clk = tegra_clk_register_periph_gate("afi", "clk_m", 0, clk_base, 0, 72, 1548 periph_clk_enb_refcnt); 1549 clk_register_clkdev(clk, "afi", "tegra-pcie"); 1550 clks[afi] = clk; 1551 1552 /* pciex */ 1553 clk = tegra_clk_register_periph_gate("pciex", "pll_e", 0, clk_base, 0, 1554 74, periph_clk_enb_refcnt); 1555 clk_register_clkdev(clk, "pciex", "tegra-pcie"); 1556 clks[pciex] = clk; 1557 1558 /* kfuse */ 1559 clk = tegra_clk_register_periph_gate("kfuse", "clk_m", 1560 TEGRA_PERIPH_ON_APB, 1561 clk_base, 0, 40, periph_clk_enb_refcnt); 1562 clk_register_clkdev(clk, NULL, "kfuse-tegra"); 1563 clks[kfuse] = clk; 1564 1565 /* fuse */ 1566 clk = tegra_clk_register_periph_gate("fuse", "clk_m", 1567 TEGRA_PERIPH_ON_APB, 1568 clk_base, 0, 39, periph_clk_enb_refcnt); 1569 clk_register_clkdev(clk, "fuse", "fuse-tegra"); 1570 clks[fuse] = clk; 1571 1572 /* fuse_burn */ 1573 clk = tegra_clk_register_periph_gate("fuse_burn", "clk_m", 1574 TEGRA_PERIPH_ON_APB, 1575 clk_base, 0, 39, periph_clk_enb_refcnt); 1576 clk_register_clkdev(clk, "fuse_burn", "fuse-tegra"); 1577 clks[fuse_burn] = clk; 1578 1579 /* apbif */ 1580 clk = tegra_clk_register_periph_gate("apbif", "clk_m", 0, 1581 clk_base, 0, 107, periph_clk_enb_refcnt); 1582 clk_register_clkdev(clk, "apbif", "tegra30-ahub"); 1583 clks[apbif] = clk; 1584 1585 /* hda2hdmi */ 1586 clk = tegra_clk_register_periph_gate("hda2hdmi", "clk_m", 1587 TEGRA_PERIPH_ON_APB, 1588 clk_base, 0, 128, periph_clk_enb_refcnt); 1589 clk_register_clkdev(clk, "hda2hdmi", "tegra30-hda"); 1590 clks[hda2hdmi] = clk; 1591 1592 /* sata_cold */ 1593 clk = tegra_clk_register_periph_gate("sata_cold", "clk_m", 1594 TEGRA_PERIPH_ON_APB, 1595 clk_base, 0, 129, periph_clk_enb_refcnt); 1596 clk_register_clkdev(clk, NULL, "tegra_sata_cold"); 1597 clks[sata_cold] = clk; 1598 1599 /* dtv */ 1600 clk = tegra_clk_register_periph_gate("dtv", "clk_m", 1601 TEGRA_PERIPH_ON_APB, 1602 clk_base, 0, 79, periph_clk_enb_refcnt); 1603 clk_register_clkdev(clk, NULL, "dtv"); 1604 clks[dtv] = clk; 1605 1606 /* emc */ 1607 clk = clk_register_mux(NULL, "emc_mux", mux_pllmcp_clkm, 1608 ARRAY_SIZE(mux_pllmcp_clkm), 1609 CLK_SET_RATE_NO_REPARENT, 1610 clk_base + CLK_SOURCE_EMC, 1611 30, 2, 0, NULL); 1612 clk = tegra_clk_register_periph_gate("emc", "emc_mux", 0, clk_base, 0, 1613 57, periph_clk_enb_refcnt); 1614 clk_register_clkdev(clk, "emc", NULL); 1615 clks[emc] = clk; 1616 1617 for (i = 0; i < ARRAY_SIZE(tegra_periph_clk_list); i++) { 1618 data = &tegra_periph_clk_list[i]; 1619 clk = tegra_clk_register_periph(data->name, data->p.parent_names, 1620 data->num_parents, &data->periph, 1621 clk_base, data->offset, data->flags); 1622 clk_register_clkdev(clk, data->con_id, data->dev_id); 1623 clks[data->clk_id] = clk; 1624 } 1625 1626 for (i = 0; i < ARRAY_SIZE(tegra_periph_nodiv_clk_list); i++) { 1627 data = &tegra_periph_nodiv_clk_list[i]; 1628 clk = tegra_clk_register_periph_nodiv(data->name, 1629 data->p.parent_names, 1630 data->num_parents, &data->periph, 1631 clk_base, data->offset); 1632 clk_register_clkdev(clk, data->con_id, data->dev_id); 1633 clks[data->clk_id] = clk; 1634 } 1635} 1636 1637static void __init tegra30_fixed_clk_init(void) 1638{ 1639 struct clk *clk; 1640 1641 /* clk_32k */ 1642 clk = clk_register_fixed_rate(NULL, "clk_32k", NULL, CLK_IS_ROOT, 1643 32768); 1644 clk_register_clkdev(clk, "clk_32k", NULL); 1645 clks[clk_32k] = clk; 1646 1647 /* clk_m_div2 */ 1648 clk = clk_register_fixed_factor(NULL, "clk_m_div2", "clk_m", 1649 CLK_SET_RATE_PARENT, 1, 2); 1650 clk_register_clkdev(clk, "clk_m_div2", NULL); 1651 clks[clk_m_div2] = clk; 1652 1653 /* clk_m_div4 */ 1654 clk = clk_register_fixed_factor(NULL, "clk_m_div4", "clk_m", 1655 CLK_SET_RATE_PARENT, 1, 4); 1656 clk_register_clkdev(clk, "clk_m_div4", NULL); 1657 clks[clk_m_div4] = clk; 1658 1659 /* cml0 */ 1660 clk = clk_register_gate(NULL, "cml0", "pll_e", 0, clk_base + PLLE_AUX, 1661 0, 0, &cml_lock); 1662 clk_register_clkdev(clk, "cml0", NULL); 1663 clks[cml0] = clk; 1664 1665 /* cml1 */ 1666 clk = clk_register_gate(NULL, "cml1", "pll_e", 0, clk_base + PLLE_AUX, 1667 1, 0, &cml_lock); 1668 clk_register_clkdev(clk, "cml1", NULL); 1669 clks[cml1] = clk; 1670} 1671 1672static void __init tegra30_osc_clk_init(void) 1673{ 1674 struct clk *clk; 1675 unsigned int pll_ref_div; 1676 1677 tegra30_clk_measure_input_freq(); 1678 1679 /* clk_m */ 1680 clk = clk_register_fixed_rate(NULL, "clk_m", NULL, CLK_IS_ROOT, 1681 input_freq); 1682 clk_register_clkdev(clk, "clk_m", NULL); 1683 clks[clk_m] = clk; 1684 1685 /* pll_ref */ 1686 pll_ref_div = tegra30_get_pll_ref_div(); 1687 clk = clk_register_fixed_factor(NULL, "pll_ref", "clk_m", 1688 CLK_SET_RATE_PARENT, 1, pll_ref_div); 1689 clk_register_clkdev(clk, "pll_ref", NULL); 1690 clks[pll_ref] = clk; 1691} 1692 1693/* Tegra30 CPU clock and reset control functions */ 1694static void tegra30_wait_cpu_in_reset(u32 cpu) 1695{ 1696 unsigned int reg; 1697 1698 do { 1699 reg = readl(clk_base + 1700 TEGRA30_CLK_RST_CONTROLLER_CPU_CMPLX_STATUS); 1701 cpu_relax(); 1702 } while (!(reg & (1 << cpu))); /* check CPU been reset or not */ 1703 1704 return; 1705} 1706 1707static void tegra30_put_cpu_in_reset(u32 cpu) 1708{ 1709 writel(CPU_RESET(cpu), 1710 clk_base + TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET); 1711 dmb(); 1712} 1713 1714static void tegra30_cpu_out_of_reset(u32 cpu) 1715{ 1716 writel(CPU_RESET(cpu), 1717 clk_base + TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR); 1718 wmb(); 1719} 1720 1721 1722static void tegra30_enable_cpu_clock(u32 cpu) 1723{ 1724 unsigned int reg; 1725 1726 writel(CPU_CLOCK(cpu), 1727 clk_base + TEGRA30_CLK_RST_CONTROLLER_CLK_CPU_CMPLX_CLR); 1728 reg = readl(clk_base + 1729 TEGRA30_CLK_RST_CONTROLLER_CLK_CPU_CMPLX_CLR); 1730} 1731 1732static void tegra30_disable_cpu_clock(u32 cpu) 1733{ 1734 1735 unsigned int reg; 1736 1737 reg = readl(clk_base + TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX); 1738 writel(reg | CPU_CLOCK(cpu), 1739 clk_base + TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX); 1740} 1741 1742#ifdef CONFIG_PM_SLEEP 1743static bool tegra30_cpu_rail_off_ready(void) 1744{ 1745 unsigned int cpu_rst_status; 1746 int cpu_pwr_status; 1747 1748 cpu_rst_status = readl(clk_base + 1749 TEGRA30_CLK_RST_CONTROLLER_CPU_CMPLX_STATUS); 1750 cpu_pwr_status = tegra_powergate_is_powered(TEGRA_POWERGATE_CPU1) || 1751 tegra_powergate_is_powered(TEGRA_POWERGATE_CPU2) || 1752 tegra_powergate_is_powered(TEGRA_POWERGATE_CPU3); 1753 1754 if (((cpu_rst_status & 0xE) != 0xE) || cpu_pwr_status) 1755 return false; 1756 1757 return true; 1758} 1759 1760static void tegra30_cpu_clock_suspend(void) 1761{ 1762 /* switch coresite to clk_m, save off original source */ 1763 tegra30_cpu_clk_sctx.clk_csite_src = 1764 readl(clk_base + CLK_RESET_SOURCE_CSITE); 1765 writel(3<<30, clk_base + CLK_RESET_SOURCE_CSITE); 1766 1767 tegra30_cpu_clk_sctx.cpu_burst = 1768 readl(clk_base + CLK_RESET_CCLK_BURST); 1769 tegra30_cpu_clk_sctx.pllx_base = 1770 readl(clk_base + CLK_RESET_PLLX_BASE); 1771 tegra30_cpu_clk_sctx.pllx_misc = 1772 readl(clk_base + CLK_RESET_PLLX_MISC); 1773 tegra30_cpu_clk_sctx.cclk_divider = 1774 readl(clk_base + CLK_RESET_CCLK_DIVIDER); 1775} 1776 1777static void tegra30_cpu_clock_resume(void) 1778{ 1779 unsigned int reg, policy; 1780 1781 /* Is CPU complex already running on PLLX? */ 1782 reg = readl(clk_base + CLK_RESET_CCLK_BURST); 1783 policy = (reg >> CLK_RESET_CCLK_BURST_POLICY_SHIFT) & 0xF; 1784 1785 if (policy == CLK_RESET_CCLK_IDLE_POLICY) 1786 reg = (reg >> CLK_RESET_CCLK_IDLE_POLICY_SHIFT) & 0xF; 1787 else if (policy == CLK_RESET_CCLK_RUN_POLICY) 1788 reg = (reg >> CLK_RESET_CCLK_RUN_POLICY_SHIFT) & 0xF; 1789 else 1790 BUG(); 1791 1792 if (reg != CLK_RESET_CCLK_BURST_POLICY_PLLX) { 1793 /* restore PLLX settings if CPU is on different PLL */ 1794 writel(tegra30_cpu_clk_sctx.pllx_misc, 1795 clk_base + CLK_RESET_PLLX_MISC); 1796 writel(tegra30_cpu_clk_sctx.pllx_base, 1797 clk_base + CLK_RESET_PLLX_BASE); 1798 1799 /* wait for PLL stabilization if PLLX was enabled */ 1800 if (tegra30_cpu_clk_sctx.pllx_base & (1 << 30)) 1801 udelay(300); 1802 } 1803 1804 /* 1805 * Restore original burst policy setting for calls resulting from CPU 1806 * LP2 in idle or system suspend. 1807 */ 1808 writel(tegra30_cpu_clk_sctx.cclk_divider, 1809 clk_base + CLK_RESET_CCLK_DIVIDER); 1810 writel(tegra30_cpu_clk_sctx.cpu_burst, 1811 clk_base + CLK_RESET_CCLK_BURST); 1812 1813 writel(tegra30_cpu_clk_sctx.clk_csite_src, 1814 clk_base + CLK_RESET_SOURCE_CSITE); 1815} 1816#endif 1817 1818static struct tegra_cpu_car_ops tegra30_cpu_car_ops = { 1819 .wait_for_reset = tegra30_wait_cpu_in_reset, 1820 .put_in_reset = tegra30_put_cpu_in_reset, 1821 .out_of_reset = tegra30_cpu_out_of_reset, 1822 .enable_clock = tegra30_enable_cpu_clock, 1823 .disable_clock = tegra30_disable_cpu_clock, 1824#ifdef CONFIG_PM_SLEEP 1825 .rail_off_ready = tegra30_cpu_rail_off_ready, 1826 .suspend = tegra30_cpu_clock_suspend, 1827 .resume = tegra30_cpu_clock_resume, 1828#endif 1829}; 1830 1831static struct tegra_clk_init_table init_table[] __initdata = { 1832 {uarta, pll_p, 408000000, 0}, 1833 {uartb, pll_p, 408000000, 0}, 1834 {uartc, pll_p, 408000000, 0}, 1835 {uartd, pll_p, 408000000, 0}, 1836 {uarte, pll_p, 408000000, 0}, 1837 {pll_a, clk_max, 564480000, 1}, 1838 {pll_a_out0, clk_max, 11289600, 1}, 1839 {extern1, pll_a_out0, 0, 1}, 1840 {clk_out_1_mux, extern1, 0, 0}, 1841 {clk_out_1, clk_max, 0, 1}, 1842 {blink, clk_max, 0, 1}, 1843 {i2s0, pll_a_out0, 11289600, 0}, 1844 {i2s1, pll_a_out0, 11289600, 0}, 1845 {i2s2, pll_a_out0, 11289600, 0}, 1846 {i2s3, pll_a_out0, 11289600, 0}, 1847 {i2s4, pll_a_out0, 11289600, 0}, 1848 {sdmmc1, pll_p, 48000000, 0}, 1849 {sdmmc2, pll_p, 48000000, 0}, 1850 {sdmmc3, pll_p, 48000000, 0}, 1851 {pll_m, clk_max, 0, 1}, 1852 {pclk, clk_max, 0, 1}, 1853 {csite, clk_max, 0, 1}, 1854 {emc, clk_max, 0, 1}, 1855 {mselect, clk_max, 0, 1}, 1856 {sbc1, pll_p, 100000000, 0}, 1857 {sbc2, pll_p, 100000000, 0}, 1858 {sbc3, pll_p, 100000000, 0}, 1859 {sbc4, pll_p, 100000000, 0}, 1860 {sbc5, pll_p, 100000000, 0}, 1861 {sbc6, pll_p, 100000000, 0}, 1862 {host1x, pll_c, 150000000, 0}, 1863 {disp1, pll_p, 600000000, 0}, 1864 {disp2, pll_p, 600000000, 0}, 1865 {twd, clk_max, 0, 1}, 1866 {gr2d, pll_c, 300000000, 0}, 1867 {gr3d, pll_c, 300000000, 0}, 1868 {clk_max, clk_max, 0, 0}, /* This MUST be the last entry. */ 1869}; 1870 1871static void __init tegra30_clock_apply_init_table(void) 1872{ 1873 tegra_init_from_table(init_table, clks, clk_max); 1874} 1875 1876/* 1877 * Some clocks may be used by different drivers depending on the board 1878 * configuration. List those here to register them twice in the clock lookup 1879 * table under two names. 1880 */ 1881static struct tegra_clk_duplicate tegra_clk_duplicates[] = { 1882 TEGRA_CLK_DUPLICATE(usbd, "utmip-pad", NULL), 1883 TEGRA_CLK_DUPLICATE(usbd, "tegra-ehci.0", NULL), 1884 TEGRA_CLK_DUPLICATE(usbd, "tegra-otg", NULL), 1885 TEGRA_CLK_DUPLICATE(bsev, "tegra-avp", "bsev"), 1886 TEGRA_CLK_DUPLICATE(bsev, "nvavp", "bsev"), 1887 TEGRA_CLK_DUPLICATE(vde, "tegra-aes", "vde"), 1888 TEGRA_CLK_DUPLICATE(bsea, "tegra-aes", "bsea"), 1889 TEGRA_CLK_DUPLICATE(bsea, "nvavp", "bsea"), 1890 TEGRA_CLK_DUPLICATE(cml1, "tegra_sata_cml", NULL), 1891 TEGRA_CLK_DUPLICATE(cml0, "tegra_pcie", "cml"), 1892 TEGRA_CLK_DUPLICATE(pciex, "tegra_pcie", "pciex"), 1893 TEGRA_CLK_DUPLICATE(vcp, "nvavp", "vcp"), 1894 TEGRA_CLK_DUPLICATE(clk_max, NULL, NULL), /* MUST be the last entry */ 1895}; 1896 1897static const struct of_device_id pmc_match[] __initconst = { 1898 { .compatible = "nvidia,tegra30-pmc" }, 1899 {}, 1900}; 1901 1902static void __init tegra30_clock_init(struct device_node *np) 1903{ 1904 struct device_node *node; 1905 1906 clk_base = of_iomap(np, 0); 1907 if (!clk_base) { 1908 pr_err("ioremap tegra30 CAR failed\n"); 1909 return; 1910 } 1911 1912 node = of_find_matching_node(NULL, pmc_match); 1913 if (!node) { 1914 pr_err("Failed to find pmc node\n"); 1915 BUG(); 1916 } 1917 1918 pmc_base = of_iomap(node, 0); 1919 if (!pmc_base) { 1920 pr_err("Can't map pmc registers\n"); 1921 BUG(); 1922 } 1923 1924 clks = tegra_clk_init(clk_max, TEGRA30_CLK_PERIPH_BANKS); 1925 if (!clks) 1926 return; 1927 1928 tegra30_osc_clk_init(); 1929 tegra30_fixed_clk_init(); 1930 tegra30_pll_init(); 1931 tegra30_super_clk_init(); 1932 tegra30_periph_clk_init(); 1933 tegra30_audio_clk_init(); 1934 tegra30_pmc_clk_init(); 1935 1936 tegra_init_dup_clks(tegra_clk_duplicates, clks, clk_max); 1937 1938 tegra_add_of_provider(np); 1939 1940 tegra_clk_apply_init_table = tegra30_clock_apply_init_table; 1941 1942 tegra_cpu_car_ops = &tegra30_cpu_car_ops; 1943} 1944CLK_OF_DECLARE(tegra30, "nvidia,tegra30-car", tegra30_clock_init); 1945