clk-tegra30.c revision b08e8c0ecc42afa3a2e1019851af741980dd5a6b
1/* 2 * Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved. 3 * 4 * This program is free software; you can redistribute it and/or modify it 5 * under the terms and conditions of the GNU General Public License, 6 * version 2, as published by the Free Software Foundation. 7 * 8 * This program is distributed in the hope it will be useful, but WITHOUT 9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 11 * more details. 12 * 13 * You should have received a copy of the GNU General Public License 14 * along with this program. If not, see <http://www.gnu.org/licenses/>. 15 */ 16 17#include <linux/io.h> 18#include <linux/delay.h> 19#include <linux/clk.h> 20#include <linux/clk-provider.h> 21#include <linux/clkdev.h> 22#include <linux/of.h> 23#include <linux/of_address.h> 24#include <linux/clk/tegra.h> 25 26#include <mach/powergate.h> 27 28#include "clk.h" 29 30#define RST_DEVICES_L 0x004 31#define RST_DEVICES_H 0x008 32#define RST_DEVICES_U 0x00c 33#define RST_DEVICES_V 0x358 34#define RST_DEVICES_W 0x35c 35#define RST_DEVICES_SET_L 0x300 36#define RST_DEVICES_CLR_L 0x304 37#define RST_DEVICES_SET_H 0x308 38#define RST_DEVICES_CLR_H 0x30c 39#define RST_DEVICES_SET_U 0x310 40#define RST_DEVICES_CLR_U 0x314 41#define RST_DEVICES_SET_V 0x430 42#define RST_DEVICES_CLR_V 0x434 43#define RST_DEVICES_SET_W 0x438 44#define RST_DEVICES_CLR_W 0x43c 45#define RST_DEVICES_NUM 5 46 47#define CLK_OUT_ENB_L 0x010 48#define CLK_OUT_ENB_H 0x014 49#define CLK_OUT_ENB_U 0x018 50#define CLK_OUT_ENB_V 0x360 51#define CLK_OUT_ENB_W 0x364 52#define CLK_OUT_ENB_SET_L 0x320 53#define CLK_OUT_ENB_CLR_L 0x324 54#define CLK_OUT_ENB_SET_H 0x328 55#define CLK_OUT_ENB_CLR_H 0x32c 56#define CLK_OUT_ENB_SET_U 0x330 57#define CLK_OUT_ENB_CLR_U 0x334 58#define CLK_OUT_ENB_SET_V 0x440 59#define CLK_OUT_ENB_CLR_V 0x444 60#define CLK_OUT_ENB_SET_W 0x448 61#define CLK_OUT_ENB_CLR_W 0x44c 62#define CLK_OUT_ENB_NUM 5 63 64#define OSC_CTRL 0x50 65#define OSC_CTRL_OSC_FREQ_MASK (0xF<<28) 66#define OSC_CTRL_OSC_FREQ_13MHZ (0X0<<28) 67#define OSC_CTRL_OSC_FREQ_19_2MHZ (0X4<<28) 68#define OSC_CTRL_OSC_FREQ_12MHZ (0X8<<28) 69#define OSC_CTRL_OSC_FREQ_26MHZ (0XC<<28) 70#define OSC_CTRL_OSC_FREQ_16_8MHZ (0X1<<28) 71#define OSC_CTRL_OSC_FREQ_38_4MHZ (0X5<<28) 72#define OSC_CTRL_OSC_FREQ_48MHZ (0X9<<28) 73#define OSC_CTRL_MASK (0x3f2 | OSC_CTRL_OSC_FREQ_MASK) 74 75#define OSC_CTRL_PLL_REF_DIV_MASK (3<<26) 76#define OSC_CTRL_PLL_REF_DIV_1 (0<<26) 77#define OSC_CTRL_PLL_REF_DIV_2 (1<<26) 78#define OSC_CTRL_PLL_REF_DIV_4 (2<<26) 79 80#define OSC_FREQ_DET 0x58 81#define OSC_FREQ_DET_TRIG BIT(31) 82 83#define OSC_FREQ_DET_STATUS 0x5c 84#define OSC_FREQ_DET_BUSY BIT(31) 85#define OSC_FREQ_DET_CNT_MASK 0xffff 86 87#define CCLKG_BURST_POLICY 0x368 88#define SUPER_CCLKG_DIVIDER 0x36c 89#define CCLKLP_BURST_POLICY 0x370 90#define SUPER_CCLKLP_DIVIDER 0x374 91#define SCLK_BURST_POLICY 0x028 92#define SUPER_SCLK_DIVIDER 0x02c 93 94#define SYSTEM_CLK_RATE 0x030 95 96#define PLLC_BASE 0x80 97#define PLLC_MISC 0x8c 98#define PLLM_BASE 0x90 99#define PLLM_MISC 0x9c 100#define PLLP_BASE 0xa0 101#define PLLP_MISC 0xac 102#define PLLX_BASE 0xe0 103#define PLLX_MISC 0xe4 104#define PLLD_BASE 0xd0 105#define PLLD_MISC 0xdc 106#define PLLD2_BASE 0x4b8 107#define PLLD2_MISC 0x4bc 108#define PLLE_BASE 0xe8 109#define PLLE_MISC 0xec 110#define PLLA_BASE 0xb0 111#define PLLA_MISC 0xbc 112#define PLLU_BASE 0xc0 113#define PLLU_MISC 0xcc 114 115#define PLL_MISC_LOCK_ENABLE 18 116#define PLLDU_MISC_LOCK_ENABLE 22 117#define PLLE_MISC_LOCK_ENABLE 9 118 119#define PLL_BASE_LOCK 27 120#define PLLE_MISC_LOCK 11 121 122#define PLLE_AUX 0x48c 123#define PLLC_OUT 0x84 124#define PLLM_OUT 0x94 125#define PLLP_OUTA 0xa4 126#define PLLP_OUTB 0xa8 127#define PLLA_OUT 0xb4 128 129#define AUDIO_SYNC_CLK_I2S0 0x4a0 130#define AUDIO_SYNC_CLK_I2S1 0x4a4 131#define AUDIO_SYNC_CLK_I2S2 0x4a8 132#define AUDIO_SYNC_CLK_I2S3 0x4ac 133#define AUDIO_SYNC_CLK_I2S4 0x4b0 134#define AUDIO_SYNC_CLK_SPDIF 0x4b4 135 136#define PMC_CLK_OUT_CNTRL 0x1a8 137 138#define CLK_SOURCE_I2S0 0x1d8 139#define CLK_SOURCE_I2S1 0x100 140#define CLK_SOURCE_I2S2 0x104 141#define CLK_SOURCE_I2S3 0x3bc 142#define CLK_SOURCE_I2S4 0x3c0 143#define CLK_SOURCE_SPDIF_OUT 0x108 144#define CLK_SOURCE_SPDIF_IN 0x10c 145#define CLK_SOURCE_PWM 0x110 146#define CLK_SOURCE_D_AUDIO 0x3d0 147#define CLK_SOURCE_DAM0 0x3d8 148#define CLK_SOURCE_DAM1 0x3dc 149#define CLK_SOURCE_DAM2 0x3e0 150#define CLK_SOURCE_HDA 0x428 151#define CLK_SOURCE_HDA2CODEC_2X 0x3e4 152#define CLK_SOURCE_SBC1 0x134 153#define CLK_SOURCE_SBC2 0x118 154#define CLK_SOURCE_SBC3 0x11c 155#define CLK_SOURCE_SBC4 0x1b4 156#define CLK_SOURCE_SBC5 0x3c8 157#define CLK_SOURCE_SBC6 0x3cc 158#define CLK_SOURCE_SATA_OOB 0x420 159#define CLK_SOURCE_SATA 0x424 160#define CLK_SOURCE_NDFLASH 0x160 161#define CLK_SOURCE_NDSPEED 0x3f8 162#define CLK_SOURCE_VFIR 0x168 163#define CLK_SOURCE_SDMMC1 0x150 164#define CLK_SOURCE_SDMMC2 0x154 165#define CLK_SOURCE_SDMMC3 0x1bc 166#define CLK_SOURCE_SDMMC4 0x164 167#define CLK_SOURCE_VDE 0x1c8 168#define CLK_SOURCE_CSITE 0x1d4 169#define CLK_SOURCE_LA 0x1f8 170#define CLK_SOURCE_OWR 0x1cc 171#define CLK_SOURCE_NOR 0x1d0 172#define CLK_SOURCE_MIPI 0x174 173#define CLK_SOURCE_I2C1 0x124 174#define CLK_SOURCE_I2C2 0x198 175#define CLK_SOURCE_I2C3 0x1b8 176#define CLK_SOURCE_I2C4 0x3c4 177#define CLK_SOURCE_I2C5 0x128 178#define CLK_SOURCE_UARTA 0x178 179#define CLK_SOURCE_UARTB 0x17c 180#define CLK_SOURCE_UARTC 0x1a0 181#define CLK_SOURCE_UARTD 0x1c0 182#define CLK_SOURCE_UARTE 0x1c4 183#define CLK_SOURCE_VI 0x148 184#define CLK_SOURCE_VI_SENSOR 0x1a8 185#define CLK_SOURCE_3D 0x158 186#define CLK_SOURCE_3D2 0x3b0 187#define CLK_SOURCE_2D 0x15c 188#define CLK_SOURCE_EPP 0x16c 189#define CLK_SOURCE_MPE 0x170 190#define CLK_SOURCE_HOST1X 0x180 191#define CLK_SOURCE_CVE 0x140 192#define CLK_SOURCE_TVO 0x188 193#define CLK_SOURCE_DTV 0x1dc 194#define CLK_SOURCE_HDMI 0x18c 195#define CLK_SOURCE_TVDAC 0x194 196#define CLK_SOURCE_DISP1 0x138 197#define CLK_SOURCE_DISP2 0x13c 198#define CLK_SOURCE_DSIB 0xd0 199#define CLK_SOURCE_TSENSOR 0x3b8 200#define CLK_SOURCE_ACTMON 0x3e8 201#define CLK_SOURCE_EXTERN1 0x3ec 202#define CLK_SOURCE_EXTERN2 0x3f0 203#define CLK_SOURCE_EXTERN3 0x3f4 204#define CLK_SOURCE_I2CSLOW 0x3fc 205#define CLK_SOURCE_SE 0x42c 206#define CLK_SOURCE_MSELECT 0x3b4 207#define CLK_SOURCE_EMC 0x19c 208 209#define AUDIO_SYNC_DOUBLER 0x49c 210 211#define PMC_CTRL 0 212#define PMC_CTRL_BLINK_ENB 7 213 214#define PMC_DPD_PADS_ORIDE 0x1c 215#define PMC_DPD_PADS_ORIDE_BLINK_ENB 20 216#define PMC_BLINK_TIMER 0x40 217 218#define UTMIP_PLL_CFG2 0x488 219#define UTMIP_PLL_CFG2_STABLE_COUNT(x) (((x) & 0xffff) << 6) 220#define UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(x) (((x) & 0x3f) << 18) 221#define UTMIP_PLL_CFG2_FORCE_PD_SAMP_A_POWERDOWN BIT(0) 222#define UTMIP_PLL_CFG2_FORCE_PD_SAMP_B_POWERDOWN BIT(2) 223#define UTMIP_PLL_CFG2_FORCE_PD_SAMP_C_POWERDOWN BIT(4) 224 225#define UTMIP_PLL_CFG1 0x484 226#define UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(x) (((x) & 0x1f) << 6) 227#define UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(x) (((x) & 0xfff) << 0) 228#define UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN BIT(14) 229#define UTMIP_PLL_CFG1_FORCE_PLL_ACTIVE_POWERDOWN BIT(12) 230#define UTMIP_PLL_CFG1_FORCE_PLLU_POWERDOWN BIT(16) 231 232/* Tegra CPU clock and reset control regs */ 233#define TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX 0x4c 234#define TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET 0x340 235#define TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR 0x344 236#define TEGRA30_CLK_RST_CONTROLLER_CLK_CPU_CMPLX_CLR 0x34c 237#define TEGRA30_CLK_RST_CONTROLLER_CPU_CMPLX_STATUS 0x470 238 239#define CPU_CLOCK(cpu) (0x1 << (8 + cpu)) 240#define CPU_RESET(cpu) (0x1111ul << (cpu)) 241 242#define CLK_RESET_CCLK_BURST 0x20 243#define CLK_RESET_CCLK_DIVIDER 0x24 244#define CLK_RESET_PLLX_BASE 0xe0 245#define CLK_RESET_PLLX_MISC 0xe4 246 247#define CLK_RESET_SOURCE_CSITE 0x1d4 248 249#define CLK_RESET_CCLK_BURST_POLICY_SHIFT 28 250#define CLK_RESET_CCLK_RUN_POLICY_SHIFT 4 251#define CLK_RESET_CCLK_IDLE_POLICY_SHIFT 0 252#define CLK_RESET_CCLK_IDLE_POLICY 1 253#define CLK_RESET_CCLK_RUN_POLICY 2 254#define CLK_RESET_CCLK_BURST_POLICY_PLLX 8 255 256#ifdef CONFIG_PM_SLEEP 257static struct cpu_clk_suspend_context { 258 u32 pllx_misc; 259 u32 pllx_base; 260 261 u32 cpu_burst; 262 u32 clk_csite_src; 263 u32 cclk_divider; 264} tegra30_cpu_clk_sctx; 265#endif 266 267static int periph_clk_enb_refcnt[CLK_OUT_ENB_NUM * 32]; 268 269static void __iomem *clk_base; 270static void __iomem *pmc_base; 271static unsigned long input_freq; 272 273static DEFINE_SPINLOCK(clk_doubler_lock); 274static DEFINE_SPINLOCK(clk_out_lock); 275static DEFINE_SPINLOCK(pll_div_lock); 276static DEFINE_SPINLOCK(cml_lock); 277static DEFINE_SPINLOCK(pll_d_lock); 278 279#define TEGRA_INIT_DATA_MUX(_name, _con_id, _dev_id, _parents, _offset, \ 280 _clk_num, _regs, _gate_flags, _clk_id) \ 281 TEGRA_INIT_DATA(_name, _con_id, _dev_id, _parents, _offset, \ 282 30, 2, 0, 0, 8, 1, 0, _regs, _clk_num, \ 283 periph_clk_enb_refcnt, _gate_flags, _clk_id) 284 285#define TEGRA_INIT_DATA_DIV16(_name, _con_id, _dev_id, _parents, _offset, \ 286 _clk_num, _regs, _gate_flags, _clk_id) \ 287 TEGRA_INIT_DATA(_name, _con_id, _dev_id, _parents, _offset, \ 288 30, 2, 0, 0, 16, 0, TEGRA_DIVIDER_ROUND_UP, \ 289 _regs, _clk_num, periph_clk_enb_refcnt, \ 290 _gate_flags, _clk_id) 291 292#define TEGRA_INIT_DATA_MUX8(_name, _con_id, _dev_id, _parents, _offset, \ 293 _clk_num, _regs, _gate_flags, _clk_id) \ 294 TEGRA_INIT_DATA(_name, _con_id, _dev_id, _parents, _offset, \ 295 29, 3, 0, 0, 8, 1, 0, _regs, _clk_num, \ 296 periph_clk_enb_refcnt, _gate_flags, _clk_id) 297 298#define TEGRA_INIT_DATA_INT(_name, _con_id, _dev_id, _parents, _offset, \ 299 _clk_num, _regs, _gate_flags, _clk_id) \ 300 TEGRA_INIT_DATA(_name, _con_id, _dev_id, _parents, _offset, \ 301 30, 2, 0, 0, 8, 1, TEGRA_DIVIDER_INT, _regs, \ 302 _clk_num, periph_clk_enb_refcnt, _gate_flags, \ 303 _clk_id) 304 305#define TEGRA_INIT_DATA_UART(_name, _con_id, _dev_id, _parents, _offset,\ 306 _clk_num, _regs, _clk_id) \ 307 TEGRA_INIT_DATA(_name, _con_id, _dev_id, _parents, _offset, \ 308 30, 2, 0, 0, 16, 1, TEGRA_DIVIDER_UART, _regs, \ 309 _clk_num, periph_clk_enb_refcnt, 0, _clk_id) 310 311#define TEGRA_INIT_DATA_NODIV(_name, _con_id, _dev_id, _parents, _offset, \ 312 _mux_shift, _mux_width, _clk_num, _regs, \ 313 _gate_flags, _clk_id) \ 314 TEGRA_INIT_DATA(_name, _con_id, _dev_id, _parents, _offset, \ 315 _mux_shift, _mux_width, 0, 0, 0, 0, 0, _regs, \ 316 _clk_num, periph_clk_enb_refcnt, _gate_flags, \ 317 _clk_id) 318 319/* 320 * IDs assigned here must be in sync with DT bindings definition 321 * for Tegra30 clocks. 322 */ 323enum tegra30_clk { 324 cpu, rtc = 4, timer, uarta, gpio = 8, sdmmc2, i2s1 = 11, i2c1, ndflash, 325 sdmmc1, sdmmc4, pwm = 17, i2s2, epp, gr2d = 21, usbd, isp, gr3d, 326 disp2 = 26, disp1, host1x, vcp, i2s0, cop_cache, mc, ahbdma, apbdma, 327 kbc = 36, statmon, pmc, kfuse = 40, sbc1, nor, sbc2 = 44, sbc3 = 46, 328 i2c5, dsia, mipi = 50, hdmi, csi, tvdac, i2c2, uartc, emc = 57, usb2, 329 usb3, mpe, vde, bsea, bsev, speedo, uartd, uarte, i2c3, sbc4, sdmmc3, 330 pcie, owr, afi, csite, pciex, avpucq, la, dtv = 79, ndspeed, i2c_slow, 331 dsib, irama = 84, iramb, iramc, iramd, cram2, audio_2x = 90, csus = 92, 332 cdev1, cdev2, cpu_g = 96, cpu_lp, gr3d2, mselect, tsensor, i2s3, i2s4, 333 i2c4, sbc5, sbc6, d_audio, apbif, dam0, dam1, dam2, hda2codec_2x, 334 atomics, audio0_2x, audio1_2x, audio2_2x, audio3_2x, audio4_2x, 335 spdif_2x, actmon, extern1, extern2, extern3, sata_oob, sata, hda, se, 336 hda2hdmi, sata_cold, uartb = 160, vfir, spdif_out, spdif_in, vi, 337 vi_sensor, fuse, fuse_burn, cve, tvo, clk_32k, clk_m, clk_m_div2, 338 clk_m_div4, pll_ref, pll_c, pll_c_out1, pll_m, pll_m_out1, pll_p, 339 pll_p_out1, pll_p_out2, pll_p_out3, pll_p_out4, pll_a, pll_a_out0, 340 pll_d, pll_d_out0, pll_d2, pll_d2_out0, pll_u, pll_x, pll_x_out0, pll_e, 341 spdif_in_sync, i2s0_sync, i2s1_sync, i2s2_sync, i2s3_sync, i2s4_sync, 342 vimclk_sync, audio0, audio1, audio2, audio3, audio4, spdif, clk_out_1, 343 clk_out_2, clk_out_3, sclk, blink, cclk_g, cclk_lp, twd, cml0, cml1, 344 i2cslow, hclk, pclk, clk_out_1_mux = 300, clk_max 345}; 346 347static struct clk *clks[clk_max]; 348static struct clk_onecell_data clk_data; 349 350/* 351 * Structure defining the fields for USB UTMI clocks Parameters. 352 */ 353struct utmi_clk_param { 354 /* Oscillator Frequency in KHz */ 355 u32 osc_frequency; 356 /* UTMIP PLL Enable Delay Count */ 357 u8 enable_delay_count; 358 /* UTMIP PLL Stable count */ 359 u8 stable_count; 360 /* UTMIP PLL Active delay count */ 361 u8 active_delay_count; 362 /* UTMIP PLL Xtal frequency count */ 363 u8 xtal_freq_count; 364}; 365 366static const struct utmi_clk_param utmi_parameters[] = { 367/* OSC_FREQUENCY, ENABLE_DLY, STABLE_CNT, ACTIVE_DLY, XTAL_FREQ_CNT */ 368 {13000000, 0x02, 0x33, 0x05, 0x7F}, 369 {19200000, 0x03, 0x4B, 0x06, 0xBB}, 370 {12000000, 0x02, 0x2F, 0x04, 0x76}, 371 {26000000, 0x04, 0x66, 0x09, 0xFE}, 372 {16800000, 0x03, 0x41, 0x0A, 0xA4}, 373}; 374 375static struct tegra_clk_pll_freq_table pll_c_freq_table[] = { 376 { 12000000, 1040000000, 520, 6, 1, 8}, 377 { 13000000, 1040000000, 480, 6, 1, 8}, 378 { 16800000, 1040000000, 495, 8, 1, 8}, /* actual: 1039.5 MHz */ 379 { 19200000, 1040000000, 325, 6, 1, 6}, 380 { 26000000, 1040000000, 520, 13, 1, 8}, 381 382 { 12000000, 832000000, 416, 6, 1, 8}, 383 { 13000000, 832000000, 832, 13, 1, 8}, 384 { 16800000, 832000000, 396, 8, 1, 8}, /* actual: 831.6 MHz */ 385 { 19200000, 832000000, 260, 6, 1, 8}, 386 { 26000000, 832000000, 416, 13, 1, 8}, 387 388 { 12000000, 624000000, 624, 12, 1, 8}, 389 { 13000000, 624000000, 624, 13, 1, 8}, 390 { 16800000, 600000000, 520, 14, 1, 8}, 391 { 19200000, 624000000, 520, 16, 1, 8}, 392 { 26000000, 624000000, 624, 26, 1, 8}, 393 394 { 12000000, 600000000, 600, 12, 1, 8}, 395 { 13000000, 600000000, 600, 13, 1, 8}, 396 { 16800000, 600000000, 500, 14, 1, 8}, 397 { 19200000, 600000000, 375, 12, 1, 6}, 398 { 26000000, 600000000, 600, 26, 1, 8}, 399 400 { 12000000, 520000000, 520, 12, 1, 8}, 401 { 13000000, 520000000, 520, 13, 1, 8}, 402 { 16800000, 520000000, 495, 16, 1, 8}, /* actual: 519.75 MHz */ 403 { 19200000, 520000000, 325, 12, 1, 6}, 404 { 26000000, 520000000, 520, 26, 1, 8}, 405 406 { 12000000, 416000000, 416, 12, 1, 8}, 407 { 13000000, 416000000, 416, 13, 1, 8}, 408 { 16800000, 416000000, 396, 16, 1, 8}, /* actual: 415.8 MHz */ 409 { 19200000, 416000000, 260, 12, 1, 6}, 410 { 26000000, 416000000, 416, 26, 1, 8}, 411 { 0, 0, 0, 0, 0, 0 }, 412}; 413 414static struct tegra_clk_pll_freq_table pll_m_freq_table[] = { 415 { 12000000, 666000000, 666, 12, 1, 8}, 416 { 13000000, 666000000, 666, 13, 1, 8}, 417 { 16800000, 666000000, 555, 14, 1, 8}, 418 { 19200000, 666000000, 555, 16, 1, 8}, 419 { 26000000, 666000000, 666, 26, 1, 8}, 420 { 12000000, 600000000, 600, 12, 1, 8}, 421 { 13000000, 600000000, 600, 13, 1, 8}, 422 { 16800000, 600000000, 500, 14, 1, 8}, 423 { 19200000, 600000000, 375, 12, 1, 6}, 424 { 26000000, 600000000, 600, 26, 1, 8}, 425 { 0, 0, 0, 0, 0, 0 }, 426}; 427 428static struct tegra_clk_pll_freq_table pll_p_freq_table[] = { 429 { 12000000, 216000000, 432, 12, 2, 8}, 430 { 13000000, 216000000, 432, 13, 2, 8}, 431 { 16800000, 216000000, 360, 14, 2, 8}, 432 { 19200000, 216000000, 360, 16, 2, 8}, 433 { 26000000, 216000000, 432, 26, 2, 8}, 434 { 0, 0, 0, 0, 0, 0 }, 435}; 436 437static struct tegra_clk_pll_freq_table pll_a_freq_table[] = { 438 { 9600000, 564480000, 294, 5, 1, 4}, 439 { 9600000, 552960000, 288, 5, 1, 4}, 440 { 9600000, 24000000, 5, 2, 1, 1}, 441 442 { 28800000, 56448000, 49, 25, 1, 1}, 443 { 28800000, 73728000, 64, 25, 1, 1}, 444 { 28800000, 24000000, 5, 6, 1, 1}, 445 { 0, 0, 0, 0, 0, 0 }, 446}; 447 448static struct tegra_clk_pll_freq_table pll_d_freq_table[] = { 449 { 12000000, 216000000, 216, 12, 1, 4}, 450 { 13000000, 216000000, 216, 13, 1, 4}, 451 { 16800000, 216000000, 180, 14, 1, 4}, 452 { 19200000, 216000000, 180, 16, 1, 4}, 453 { 26000000, 216000000, 216, 26, 1, 4}, 454 455 { 12000000, 594000000, 594, 12, 1, 8}, 456 { 13000000, 594000000, 594, 13, 1, 8}, 457 { 16800000, 594000000, 495, 14, 1, 8}, 458 { 19200000, 594000000, 495, 16, 1, 8}, 459 { 26000000, 594000000, 594, 26, 1, 8}, 460 461 { 12000000, 1000000000, 1000, 12, 1, 12}, 462 { 13000000, 1000000000, 1000, 13, 1, 12}, 463 { 19200000, 1000000000, 625, 12, 1, 8}, 464 { 26000000, 1000000000, 1000, 26, 1, 12}, 465 466 { 0, 0, 0, 0, 0, 0 }, 467}; 468 469static struct tegra_clk_pll_freq_table pll_u_freq_table[] = { 470 { 12000000, 480000000, 960, 12, 2, 12}, 471 { 13000000, 480000000, 960, 13, 2, 12}, 472 { 16800000, 480000000, 400, 7, 2, 5}, 473 { 19200000, 480000000, 200, 4, 2, 3}, 474 { 26000000, 480000000, 960, 26, 2, 12}, 475 { 0, 0, 0, 0, 0, 0 }, 476}; 477 478static struct tegra_clk_pll_freq_table pll_x_freq_table[] = { 479 /* 1.7 GHz */ 480 { 12000000, 1700000000, 850, 6, 1, 8}, 481 { 13000000, 1700000000, 915, 7, 1, 8}, /* actual: 1699.2 MHz */ 482 { 16800000, 1700000000, 708, 7, 1, 8}, /* actual: 1699.2 MHz */ 483 { 19200000, 1700000000, 885, 10, 1, 8}, /* actual: 1699.2 MHz */ 484 { 26000000, 1700000000, 850, 13, 1, 8}, 485 486 /* 1.6 GHz */ 487 { 12000000, 1600000000, 800, 6, 1, 8}, 488 { 13000000, 1600000000, 738, 6, 1, 8}, /* actual: 1599.0 MHz */ 489 { 16800000, 1600000000, 857, 9, 1, 8}, /* actual: 1599.7 MHz */ 490 { 19200000, 1600000000, 500, 6, 1, 8}, 491 { 26000000, 1600000000, 800, 13, 1, 8}, 492 493 /* 1.5 GHz */ 494 { 12000000, 1500000000, 750, 6, 1, 8}, 495 { 13000000, 1500000000, 923, 8, 1, 8}, /* actual: 1499.8 MHz */ 496 { 16800000, 1500000000, 625, 7, 1, 8}, 497 { 19200000, 1500000000, 625, 8, 1, 8}, 498 { 26000000, 1500000000, 750, 13, 1, 8}, 499 500 /* 1.4 GHz */ 501 { 12000000, 1400000000, 700, 6, 1, 8}, 502 { 13000000, 1400000000, 969, 9, 1, 8}, /* actual: 1399.7 MHz */ 503 { 16800000, 1400000000, 1000, 12, 1, 8}, 504 { 19200000, 1400000000, 875, 12, 1, 8}, 505 { 26000000, 1400000000, 700, 13, 1, 8}, 506 507 /* 1.3 GHz */ 508 { 12000000, 1300000000, 975, 9, 1, 8}, 509 { 13000000, 1300000000, 1000, 10, 1, 8}, 510 { 16800000, 1300000000, 928, 12, 1, 8}, /* actual: 1299.2 MHz */ 511 { 19200000, 1300000000, 812, 12, 1, 8}, /* actual: 1299.2 MHz */ 512 { 26000000, 1300000000, 650, 13, 1, 8}, 513 514 /* 1.2 GHz */ 515 { 12000000, 1200000000, 1000, 10, 1, 8}, 516 { 13000000, 1200000000, 923, 10, 1, 8}, /* actual: 1199.9 MHz */ 517 { 16800000, 1200000000, 1000, 14, 1, 8}, 518 { 19200000, 1200000000, 1000, 16, 1, 8}, 519 { 26000000, 1200000000, 600, 13, 1, 8}, 520 521 /* 1.1 GHz */ 522 { 12000000, 1100000000, 825, 9, 1, 8}, 523 { 13000000, 1100000000, 846, 10, 1, 8}, /* actual: 1099.8 MHz */ 524 { 16800000, 1100000000, 982, 15, 1, 8}, /* actual: 1099.8 MHz */ 525 { 19200000, 1100000000, 859, 15, 1, 8}, /* actual: 1099.5 MHz */ 526 { 26000000, 1100000000, 550, 13, 1, 8}, 527 528 /* 1 GHz */ 529 { 12000000, 1000000000, 1000, 12, 1, 8}, 530 { 13000000, 1000000000, 1000, 13, 1, 8}, 531 { 16800000, 1000000000, 833, 14, 1, 8}, /* actual: 999.6 MHz */ 532 { 19200000, 1000000000, 625, 12, 1, 8}, 533 { 26000000, 1000000000, 1000, 26, 1, 8}, 534 535 { 0, 0, 0, 0, 0, 0 }, 536}; 537 538static struct tegra_clk_pll_freq_table pll_e_freq_table[] = { 539 /* PLLE special case: use cpcon field to store cml divider value */ 540 { 12000000, 100000000, 150, 1, 18, 11}, 541 { 216000000, 100000000, 200, 18, 24, 13}, 542 { 0, 0, 0, 0, 0, 0 }, 543}; 544 545/* PLL parameters */ 546static struct tegra_clk_pll_params pll_c_params = { 547 .input_min = 2000000, 548 .input_max = 31000000, 549 .cf_min = 1000000, 550 .cf_max = 6000000, 551 .vco_min = 20000000, 552 .vco_max = 1400000000, 553 .base_reg = PLLC_BASE, 554 .misc_reg = PLLC_MISC, 555 .lock_bit_idx = PLL_BASE_LOCK, 556 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE, 557 .lock_delay = 300, 558}; 559 560static struct tegra_clk_pll_params pll_m_params = { 561 .input_min = 2000000, 562 .input_max = 31000000, 563 .cf_min = 1000000, 564 .cf_max = 6000000, 565 .vco_min = 20000000, 566 .vco_max = 1200000000, 567 .base_reg = PLLM_BASE, 568 .misc_reg = PLLM_MISC, 569 .lock_bit_idx = PLL_BASE_LOCK, 570 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE, 571 .lock_delay = 300, 572}; 573 574static struct tegra_clk_pll_params pll_p_params = { 575 .input_min = 2000000, 576 .input_max = 31000000, 577 .cf_min = 1000000, 578 .cf_max = 6000000, 579 .vco_min = 20000000, 580 .vco_max = 1400000000, 581 .base_reg = PLLP_BASE, 582 .misc_reg = PLLP_MISC, 583 .lock_bit_idx = PLL_BASE_LOCK, 584 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE, 585 .lock_delay = 300, 586}; 587 588static struct tegra_clk_pll_params pll_a_params = { 589 .input_min = 2000000, 590 .input_max = 31000000, 591 .cf_min = 1000000, 592 .cf_max = 6000000, 593 .vco_min = 20000000, 594 .vco_max = 1400000000, 595 .base_reg = PLLA_BASE, 596 .misc_reg = PLLA_MISC, 597 .lock_bit_idx = PLL_BASE_LOCK, 598 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE, 599 .lock_delay = 300, 600}; 601 602static struct tegra_clk_pll_params pll_d_params = { 603 .input_min = 2000000, 604 .input_max = 40000000, 605 .cf_min = 1000000, 606 .cf_max = 6000000, 607 .vco_min = 40000000, 608 .vco_max = 1000000000, 609 .base_reg = PLLD_BASE, 610 .misc_reg = PLLD_MISC, 611 .lock_bit_idx = PLL_BASE_LOCK, 612 .lock_enable_bit_idx = PLLDU_MISC_LOCK_ENABLE, 613 .lock_delay = 1000, 614}; 615 616static struct tegra_clk_pll_params pll_d2_params = { 617 .input_min = 2000000, 618 .input_max = 40000000, 619 .cf_min = 1000000, 620 .cf_max = 6000000, 621 .vco_min = 40000000, 622 .vco_max = 1000000000, 623 .base_reg = PLLD2_BASE, 624 .misc_reg = PLLD2_MISC, 625 .lock_bit_idx = PLL_BASE_LOCK, 626 .lock_enable_bit_idx = PLLDU_MISC_LOCK_ENABLE, 627 .lock_delay = 1000, 628}; 629 630static struct tegra_clk_pll_params pll_u_params = { 631 .input_min = 2000000, 632 .input_max = 40000000, 633 .cf_min = 1000000, 634 .cf_max = 6000000, 635 .vco_min = 48000000, 636 .vco_max = 960000000, 637 .base_reg = PLLU_BASE, 638 .misc_reg = PLLU_MISC, 639 .lock_bit_idx = PLL_BASE_LOCK, 640 .lock_enable_bit_idx = PLLDU_MISC_LOCK_ENABLE, 641 .lock_delay = 1000, 642}; 643 644static struct tegra_clk_pll_params pll_x_params = { 645 .input_min = 2000000, 646 .input_max = 31000000, 647 .cf_min = 1000000, 648 .cf_max = 6000000, 649 .vco_min = 20000000, 650 .vco_max = 1700000000, 651 .base_reg = PLLX_BASE, 652 .misc_reg = PLLX_MISC, 653 .lock_bit_idx = PLL_BASE_LOCK, 654 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE, 655 .lock_delay = 300, 656}; 657 658static struct tegra_clk_pll_params pll_e_params = { 659 .input_min = 12000000, 660 .input_max = 216000000, 661 .cf_min = 12000000, 662 .cf_max = 12000000, 663 .vco_min = 1200000000, 664 .vco_max = 2400000000U, 665 .base_reg = PLLE_BASE, 666 .misc_reg = PLLE_MISC, 667 .lock_bit_idx = PLLE_MISC_LOCK, 668 .lock_enable_bit_idx = PLLE_MISC_LOCK_ENABLE, 669 .lock_delay = 300, 670}; 671 672/* Peripheral clock registers */ 673static struct tegra_clk_periph_regs periph_l_regs = { 674 .enb_reg = CLK_OUT_ENB_L, 675 .enb_set_reg = CLK_OUT_ENB_SET_L, 676 .enb_clr_reg = CLK_OUT_ENB_CLR_L, 677 .rst_reg = RST_DEVICES_L, 678 .rst_set_reg = RST_DEVICES_SET_L, 679 .rst_clr_reg = RST_DEVICES_CLR_L, 680}; 681 682static struct tegra_clk_periph_regs periph_h_regs = { 683 .enb_reg = CLK_OUT_ENB_H, 684 .enb_set_reg = CLK_OUT_ENB_SET_H, 685 .enb_clr_reg = CLK_OUT_ENB_CLR_H, 686 .rst_reg = RST_DEVICES_H, 687 .rst_set_reg = RST_DEVICES_SET_H, 688 .rst_clr_reg = RST_DEVICES_CLR_H, 689}; 690 691static struct tegra_clk_periph_regs periph_u_regs = { 692 .enb_reg = CLK_OUT_ENB_U, 693 .enb_set_reg = CLK_OUT_ENB_SET_U, 694 .enb_clr_reg = CLK_OUT_ENB_CLR_U, 695 .rst_reg = RST_DEVICES_U, 696 .rst_set_reg = RST_DEVICES_SET_U, 697 .rst_clr_reg = RST_DEVICES_CLR_U, 698}; 699 700static struct tegra_clk_periph_regs periph_v_regs = { 701 .enb_reg = CLK_OUT_ENB_V, 702 .enb_set_reg = CLK_OUT_ENB_SET_V, 703 .enb_clr_reg = CLK_OUT_ENB_CLR_V, 704 .rst_reg = RST_DEVICES_V, 705 .rst_set_reg = RST_DEVICES_SET_V, 706 .rst_clr_reg = RST_DEVICES_CLR_V, 707}; 708 709static struct tegra_clk_periph_regs periph_w_regs = { 710 .enb_reg = CLK_OUT_ENB_W, 711 .enb_set_reg = CLK_OUT_ENB_SET_W, 712 .enb_clr_reg = CLK_OUT_ENB_CLR_W, 713 .rst_reg = RST_DEVICES_W, 714 .rst_set_reg = RST_DEVICES_SET_W, 715 .rst_clr_reg = RST_DEVICES_CLR_W, 716}; 717 718static void tegra30_clk_measure_input_freq(void) 719{ 720 u32 osc_ctrl = readl_relaxed(clk_base + OSC_CTRL); 721 u32 auto_clk_control = osc_ctrl & OSC_CTRL_OSC_FREQ_MASK; 722 u32 pll_ref_div = osc_ctrl & OSC_CTRL_PLL_REF_DIV_MASK; 723 724 switch (auto_clk_control) { 725 case OSC_CTRL_OSC_FREQ_12MHZ: 726 BUG_ON(pll_ref_div != OSC_CTRL_PLL_REF_DIV_1); 727 input_freq = 12000000; 728 break; 729 case OSC_CTRL_OSC_FREQ_13MHZ: 730 BUG_ON(pll_ref_div != OSC_CTRL_PLL_REF_DIV_1); 731 input_freq = 13000000; 732 break; 733 case OSC_CTRL_OSC_FREQ_19_2MHZ: 734 BUG_ON(pll_ref_div != OSC_CTRL_PLL_REF_DIV_1); 735 input_freq = 19200000; 736 break; 737 case OSC_CTRL_OSC_FREQ_26MHZ: 738 BUG_ON(pll_ref_div != OSC_CTRL_PLL_REF_DIV_1); 739 input_freq = 26000000; 740 break; 741 case OSC_CTRL_OSC_FREQ_16_8MHZ: 742 BUG_ON(pll_ref_div != OSC_CTRL_PLL_REF_DIV_1); 743 input_freq = 16800000; 744 break; 745 case OSC_CTRL_OSC_FREQ_38_4MHZ: 746 BUG_ON(pll_ref_div != OSC_CTRL_PLL_REF_DIV_2); 747 input_freq = 38400000; 748 break; 749 case OSC_CTRL_OSC_FREQ_48MHZ: 750 BUG_ON(pll_ref_div != OSC_CTRL_PLL_REF_DIV_4); 751 input_freq = 48000000; 752 break; 753 default: 754 pr_err("Unexpected auto clock control value %d", 755 auto_clk_control); 756 BUG(); 757 return; 758 } 759} 760 761static unsigned int tegra30_get_pll_ref_div(void) 762{ 763 u32 pll_ref_div = readl_relaxed(clk_base + OSC_CTRL) & 764 OSC_CTRL_PLL_REF_DIV_MASK; 765 766 switch (pll_ref_div) { 767 case OSC_CTRL_PLL_REF_DIV_1: 768 return 1; 769 case OSC_CTRL_PLL_REF_DIV_2: 770 return 2; 771 case OSC_CTRL_PLL_REF_DIV_4: 772 return 4; 773 default: 774 pr_err("Invalid pll ref divider %d", pll_ref_div); 775 BUG(); 776 } 777 return 0; 778} 779 780static void tegra30_utmi_param_configure(void) 781{ 782 u32 reg; 783 int i; 784 785 for (i = 0; i < ARRAY_SIZE(utmi_parameters); i++) { 786 if (input_freq == utmi_parameters[i].osc_frequency) 787 break; 788 } 789 790 if (i >= ARRAY_SIZE(utmi_parameters)) { 791 pr_err("%s: Unexpected input rate %lu\n", __func__, input_freq); 792 return; 793 } 794 795 reg = readl_relaxed(clk_base + UTMIP_PLL_CFG2); 796 797 /* Program UTMIP PLL stable and active counts */ 798 reg &= ~UTMIP_PLL_CFG2_STABLE_COUNT(~0); 799 reg |= UTMIP_PLL_CFG2_STABLE_COUNT( 800 utmi_parameters[i].stable_count); 801 802 reg &= ~UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(~0); 803 804 reg |= UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT( 805 utmi_parameters[i].active_delay_count); 806 807 /* Remove power downs from UTMIP PLL control bits */ 808 reg &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_A_POWERDOWN; 809 reg &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_B_POWERDOWN; 810 reg &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_C_POWERDOWN; 811 812 writel_relaxed(reg, clk_base + UTMIP_PLL_CFG2); 813 814 /* Program UTMIP PLL delay and oscillator frequency counts */ 815 reg = readl_relaxed(clk_base + UTMIP_PLL_CFG1); 816 reg &= ~UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(~0); 817 818 reg |= UTMIP_PLL_CFG1_ENABLE_DLY_COUNT( 819 utmi_parameters[i].enable_delay_count); 820 821 reg &= ~UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(~0); 822 reg |= UTMIP_PLL_CFG1_XTAL_FREQ_COUNT( 823 utmi_parameters[i].xtal_freq_count); 824 825 /* Remove power downs from UTMIP PLL control bits */ 826 reg &= ~UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN; 827 reg &= ~UTMIP_PLL_CFG1_FORCE_PLL_ACTIVE_POWERDOWN; 828 reg &= ~UTMIP_PLL_CFG1_FORCE_PLLU_POWERDOWN; 829 830 writel_relaxed(reg, clk_base + UTMIP_PLL_CFG1); 831} 832 833static const char *pll_e_parents[] = {"pll_ref", "pll_p"}; 834 835static void __init tegra30_pll_init(void) 836{ 837 struct clk *clk; 838 839 /* PLLC */ 840 clk = tegra_clk_register_pll("pll_c", "pll_ref", clk_base, pmc_base, 0, 841 0, &pll_c_params, 842 TEGRA_PLL_HAS_CPCON | TEGRA_PLL_USE_LOCK, 843 pll_c_freq_table, NULL); 844 clk_register_clkdev(clk, "pll_c", NULL); 845 clks[pll_c] = clk; 846 847 /* PLLC_OUT1 */ 848 clk = tegra_clk_register_divider("pll_c_out1_div", "pll_c", 849 clk_base + PLLC_OUT, 0, TEGRA_DIVIDER_ROUND_UP, 850 8, 8, 1, NULL); 851 clk = tegra_clk_register_pll_out("pll_c_out1", "pll_c_out1_div", 852 clk_base + PLLC_OUT, 1, 0, CLK_SET_RATE_PARENT, 853 0, NULL); 854 clk_register_clkdev(clk, "pll_c_out1", NULL); 855 clks[pll_c_out1] = clk; 856 857 /* PLLP */ 858 clk = tegra_clk_register_pll("pll_p", "pll_ref", clk_base, pmc_base, 0, 859 408000000, &pll_p_params, 860 TEGRA_PLL_FIXED | TEGRA_PLL_HAS_CPCON | 861 TEGRA_PLL_USE_LOCK, pll_p_freq_table, NULL); 862 clk_register_clkdev(clk, "pll_p", NULL); 863 clks[pll_p] = clk; 864 865 /* PLLP_OUT1 */ 866 clk = tegra_clk_register_divider("pll_p_out1_div", "pll_p", 867 clk_base + PLLP_OUTA, 0, TEGRA_DIVIDER_FIXED | 868 TEGRA_DIVIDER_ROUND_UP, 8, 8, 1, 869 &pll_div_lock); 870 clk = tegra_clk_register_pll_out("pll_p_out1", "pll_p_out1_div", 871 clk_base + PLLP_OUTA, 1, 0, 872 CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0, 873 &pll_div_lock); 874 clk_register_clkdev(clk, "pll_p_out1", NULL); 875 clks[pll_p_out1] = clk; 876 877 /* PLLP_OUT2 */ 878 clk = tegra_clk_register_divider("pll_p_out2_div", "pll_p", 879 clk_base + PLLP_OUTA, 0, TEGRA_DIVIDER_FIXED | 880 TEGRA_DIVIDER_ROUND_UP, 24, 8, 1, 881 &pll_div_lock); 882 clk = tegra_clk_register_pll_out("pll_p_out2", "pll_p_out2_div", 883 clk_base + PLLP_OUTA, 17, 16, 884 CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0, 885 &pll_div_lock); 886 clk_register_clkdev(clk, "pll_p_out2", NULL); 887 clks[pll_p_out2] = clk; 888 889 /* PLLP_OUT3 */ 890 clk = tegra_clk_register_divider("pll_p_out3_div", "pll_p", 891 clk_base + PLLP_OUTB, 0, TEGRA_DIVIDER_FIXED | 892 TEGRA_DIVIDER_ROUND_UP, 8, 8, 1, 893 &pll_div_lock); 894 clk = tegra_clk_register_pll_out("pll_p_out3", "pll_p_out3_div", 895 clk_base + PLLP_OUTB, 1, 0, 896 CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0, 897 &pll_div_lock); 898 clk_register_clkdev(clk, "pll_p_out3", NULL); 899 clks[pll_p_out3] = clk; 900 901 /* PLLP_OUT4 */ 902 clk = tegra_clk_register_divider("pll_p_out4_div", "pll_p", 903 clk_base + PLLP_OUTB, 0, TEGRA_DIVIDER_FIXED | 904 TEGRA_DIVIDER_ROUND_UP, 24, 8, 1, 905 &pll_div_lock); 906 clk = tegra_clk_register_pll_out("pll_p_out4", "pll_p_out4_div", 907 clk_base + PLLP_OUTB, 17, 16, 908 CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0, 909 &pll_div_lock); 910 clk_register_clkdev(clk, "pll_p_out4", NULL); 911 clks[pll_p_out4] = clk; 912 913 /* PLLM */ 914 clk = tegra_clk_register_pll("pll_m", "pll_ref", clk_base, pmc_base, 915 CLK_IGNORE_UNUSED | CLK_SET_RATE_GATE, 0, 916 &pll_m_params, TEGRA_PLLM | TEGRA_PLL_HAS_CPCON | 917 TEGRA_PLL_SET_DCCON | TEGRA_PLL_USE_LOCK, 918 pll_m_freq_table, NULL); 919 clk_register_clkdev(clk, "pll_m", NULL); 920 clks[pll_m] = clk; 921 922 /* PLLM_OUT1 */ 923 clk = tegra_clk_register_divider("pll_m_out1_div", "pll_m", 924 clk_base + PLLM_OUT, 0, TEGRA_DIVIDER_ROUND_UP, 925 8, 8, 1, NULL); 926 clk = tegra_clk_register_pll_out("pll_m_out1", "pll_m_out1_div", 927 clk_base + PLLM_OUT, 1, 0, CLK_IGNORE_UNUSED | 928 CLK_SET_RATE_PARENT, 0, NULL); 929 clk_register_clkdev(clk, "pll_m_out1", NULL); 930 clks[pll_m_out1] = clk; 931 932 /* PLLX */ 933 clk = tegra_clk_register_pll("pll_x", "pll_ref", clk_base, pmc_base, 0, 934 0, &pll_x_params, TEGRA_PLL_HAS_CPCON | 935 TEGRA_PLL_SET_DCCON | TEGRA_PLL_USE_LOCK, 936 pll_x_freq_table, NULL); 937 clk_register_clkdev(clk, "pll_x", NULL); 938 clks[pll_x] = clk; 939 940 /* PLLX_OUT0 */ 941 clk = clk_register_fixed_factor(NULL, "pll_x_out0", "pll_x", 942 CLK_SET_RATE_PARENT, 1, 2); 943 clk_register_clkdev(clk, "pll_x_out0", NULL); 944 clks[pll_x_out0] = clk; 945 946 /* PLLU */ 947 clk = tegra_clk_register_pll("pll_u", "pll_ref", clk_base, pmc_base, 0, 948 0, &pll_u_params, TEGRA_PLLU | TEGRA_PLL_HAS_CPCON | 949 TEGRA_PLL_SET_LFCON | TEGRA_PLL_USE_LOCK, 950 pll_u_freq_table, 951 NULL); 952 clk_register_clkdev(clk, "pll_u", NULL); 953 clks[pll_u] = clk; 954 955 tegra30_utmi_param_configure(); 956 957 /* PLLD */ 958 clk = tegra_clk_register_pll("pll_d", "pll_ref", clk_base, pmc_base, 0, 959 0, &pll_d_params, TEGRA_PLL_HAS_CPCON | 960 TEGRA_PLL_SET_LFCON | TEGRA_PLL_USE_LOCK, 961 pll_d_freq_table, &pll_d_lock); 962 clk_register_clkdev(clk, "pll_d", NULL); 963 clks[pll_d] = clk; 964 965 /* PLLD_OUT0 */ 966 clk = clk_register_fixed_factor(NULL, "pll_d_out0", "pll_d", 967 CLK_SET_RATE_PARENT, 1, 2); 968 clk_register_clkdev(clk, "pll_d_out0", NULL); 969 clks[pll_d_out0] = clk; 970 971 /* PLLD2 */ 972 clk = tegra_clk_register_pll("pll_d2", "pll_ref", clk_base, pmc_base, 0, 973 0, &pll_d2_params, TEGRA_PLL_HAS_CPCON | 974 TEGRA_PLL_SET_LFCON | TEGRA_PLL_USE_LOCK, 975 pll_d_freq_table, NULL); 976 clk_register_clkdev(clk, "pll_d2", NULL); 977 clks[pll_d2] = clk; 978 979 /* PLLD2_OUT0 */ 980 clk = clk_register_fixed_factor(NULL, "pll_d2_out0", "pll_d2", 981 CLK_SET_RATE_PARENT, 1, 2); 982 clk_register_clkdev(clk, "pll_d2_out0", NULL); 983 clks[pll_d2_out0] = clk; 984 985 /* PLLA */ 986 clk = tegra_clk_register_pll("pll_a", "pll_p_out1", clk_base, pmc_base, 987 0, 0, &pll_a_params, TEGRA_PLL_HAS_CPCON | 988 TEGRA_PLL_USE_LOCK, pll_a_freq_table, NULL); 989 clk_register_clkdev(clk, "pll_a", NULL); 990 clks[pll_a] = clk; 991 992 /* PLLA_OUT0 */ 993 clk = tegra_clk_register_divider("pll_a_out0_div", "pll_a", 994 clk_base + PLLA_OUT, 0, TEGRA_DIVIDER_ROUND_UP, 995 8, 8, 1, NULL); 996 clk = tegra_clk_register_pll_out("pll_a_out0", "pll_a_out0_div", 997 clk_base + PLLA_OUT, 1, 0, CLK_IGNORE_UNUSED | 998 CLK_SET_RATE_PARENT, 0, NULL); 999 clk_register_clkdev(clk, "pll_a_out0", NULL); 1000 clks[pll_a_out0] = clk; 1001 1002 /* PLLE */ 1003 clk = clk_register_mux(NULL, "pll_e_mux", pll_e_parents, 1004 ARRAY_SIZE(pll_e_parents), 0, 1005 clk_base + PLLE_AUX, 2, 1, 0, NULL); 1006 clk = tegra_clk_register_plle("pll_e", "pll_e_mux", clk_base, pmc_base, 1007 CLK_GET_RATE_NOCACHE, 100000000, &pll_e_params, 1008 TEGRA_PLLE_CONFIGURE, pll_e_freq_table, NULL); 1009 clk_register_clkdev(clk, "pll_e", NULL); 1010 clks[pll_e] = clk; 1011} 1012 1013static const char *mux_audio_sync_clk[] = { "spdif_in_sync", "i2s0_sync", 1014 "i2s1_sync", "i2s2_sync", "i2s3_sync", "i2s4_sync", "vimclk_sync",}; 1015static const char *clk_out1_parents[] = { "clk_m", "clk_m_div2", 1016 "clk_m_div4", "extern1", }; 1017static const char *clk_out2_parents[] = { "clk_m", "clk_m_div2", 1018 "clk_m_div4", "extern2", }; 1019static const char *clk_out3_parents[] = { "clk_m", "clk_m_div2", 1020 "clk_m_div4", "extern3", }; 1021 1022static void __init tegra30_audio_clk_init(void) 1023{ 1024 struct clk *clk; 1025 1026 /* spdif_in_sync */ 1027 clk = tegra_clk_register_sync_source("spdif_in_sync", 24000000, 1028 24000000); 1029 clk_register_clkdev(clk, "spdif_in_sync", NULL); 1030 clks[spdif_in_sync] = clk; 1031 1032 /* i2s0_sync */ 1033 clk = tegra_clk_register_sync_source("i2s0_sync", 24000000, 24000000); 1034 clk_register_clkdev(clk, "i2s0_sync", NULL); 1035 clks[i2s0_sync] = clk; 1036 1037 /* i2s1_sync */ 1038 clk = tegra_clk_register_sync_source("i2s1_sync", 24000000, 24000000); 1039 clk_register_clkdev(clk, "i2s1_sync", NULL); 1040 clks[i2s1_sync] = clk; 1041 1042 /* i2s2_sync */ 1043 clk = tegra_clk_register_sync_source("i2s2_sync", 24000000, 24000000); 1044 clk_register_clkdev(clk, "i2s2_sync", NULL); 1045 clks[i2s2_sync] = clk; 1046 1047 /* i2s3_sync */ 1048 clk = tegra_clk_register_sync_source("i2s3_sync", 24000000, 24000000); 1049 clk_register_clkdev(clk, "i2s3_sync", NULL); 1050 clks[i2s3_sync] = clk; 1051 1052 /* i2s4_sync */ 1053 clk = tegra_clk_register_sync_source("i2s4_sync", 24000000, 24000000); 1054 clk_register_clkdev(clk, "i2s4_sync", NULL); 1055 clks[i2s4_sync] = clk; 1056 1057 /* vimclk_sync */ 1058 clk = tegra_clk_register_sync_source("vimclk_sync", 24000000, 24000000); 1059 clk_register_clkdev(clk, "vimclk_sync", NULL); 1060 clks[vimclk_sync] = clk; 1061 1062 /* audio0 */ 1063 clk = clk_register_mux(NULL, "audio0_mux", mux_audio_sync_clk, 1064 ARRAY_SIZE(mux_audio_sync_clk), 0, 1065 clk_base + AUDIO_SYNC_CLK_I2S0, 0, 3, 0, NULL); 1066 clk = clk_register_gate(NULL, "audio0", "audio0_mux", 0, 1067 clk_base + AUDIO_SYNC_CLK_I2S0, 4, 1068 CLK_GATE_SET_TO_DISABLE, NULL); 1069 clk_register_clkdev(clk, "audio0", NULL); 1070 clks[audio0] = clk; 1071 1072 /* audio1 */ 1073 clk = clk_register_mux(NULL, "audio1_mux", mux_audio_sync_clk, 1074 ARRAY_SIZE(mux_audio_sync_clk), 0, 1075 clk_base + AUDIO_SYNC_CLK_I2S1, 0, 3, 0, NULL); 1076 clk = clk_register_gate(NULL, "audio1", "audio1_mux", 0, 1077 clk_base + AUDIO_SYNC_CLK_I2S1, 4, 1078 CLK_GATE_SET_TO_DISABLE, NULL); 1079 clk_register_clkdev(clk, "audio1", NULL); 1080 clks[audio1] = clk; 1081 1082 /* audio2 */ 1083 clk = clk_register_mux(NULL, "audio2_mux", mux_audio_sync_clk, 1084 ARRAY_SIZE(mux_audio_sync_clk), 0, 1085 clk_base + AUDIO_SYNC_CLK_I2S2, 0, 3, 0, NULL); 1086 clk = clk_register_gate(NULL, "audio2", "audio2_mux", 0, 1087 clk_base + AUDIO_SYNC_CLK_I2S2, 4, 1088 CLK_GATE_SET_TO_DISABLE, NULL); 1089 clk_register_clkdev(clk, "audio2", NULL); 1090 clks[audio2] = clk; 1091 1092 /* audio3 */ 1093 clk = clk_register_mux(NULL, "audio3_mux", mux_audio_sync_clk, 1094 ARRAY_SIZE(mux_audio_sync_clk), 0, 1095 clk_base + AUDIO_SYNC_CLK_I2S3, 0, 3, 0, NULL); 1096 clk = clk_register_gate(NULL, "audio3", "audio3_mux", 0, 1097 clk_base + AUDIO_SYNC_CLK_I2S3, 4, 1098 CLK_GATE_SET_TO_DISABLE, NULL); 1099 clk_register_clkdev(clk, "audio3", NULL); 1100 clks[audio3] = clk; 1101 1102 /* audio4 */ 1103 clk = clk_register_mux(NULL, "audio4_mux", mux_audio_sync_clk, 1104 ARRAY_SIZE(mux_audio_sync_clk), 0, 1105 clk_base + AUDIO_SYNC_CLK_I2S4, 0, 3, 0, NULL); 1106 clk = clk_register_gate(NULL, "audio4", "audio4_mux", 0, 1107 clk_base + AUDIO_SYNC_CLK_I2S4, 4, 1108 CLK_GATE_SET_TO_DISABLE, NULL); 1109 clk_register_clkdev(clk, "audio4", NULL); 1110 clks[audio4] = clk; 1111 1112 /* spdif */ 1113 clk = clk_register_mux(NULL, "spdif_mux", mux_audio_sync_clk, 1114 ARRAY_SIZE(mux_audio_sync_clk), 0, 1115 clk_base + AUDIO_SYNC_CLK_SPDIF, 0, 3, 0, NULL); 1116 clk = clk_register_gate(NULL, "spdif", "spdif_mux", 0, 1117 clk_base + AUDIO_SYNC_CLK_SPDIF, 4, 1118 CLK_GATE_SET_TO_DISABLE, NULL); 1119 clk_register_clkdev(clk, "spdif", NULL); 1120 clks[spdif] = clk; 1121 1122 /* audio0_2x */ 1123 clk = clk_register_fixed_factor(NULL, "audio0_doubler", "audio0", 1124 CLK_SET_RATE_PARENT, 2, 1); 1125 clk = tegra_clk_register_divider("audio0_div", "audio0_doubler", 1126 clk_base + AUDIO_SYNC_DOUBLER, 0, 0, 24, 1, 0, 1127 &clk_doubler_lock); 1128 clk = tegra_clk_register_periph_gate("audio0_2x", "audio0_div", 1129 TEGRA_PERIPH_NO_RESET, clk_base, 1130 CLK_SET_RATE_PARENT, 113, &periph_v_regs, 1131 periph_clk_enb_refcnt); 1132 clk_register_clkdev(clk, "audio0_2x", NULL); 1133 clks[audio0_2x] = clk; 1134 1135 /* audio1_2x */ 1136 clk = clk_register_fixed_factor(NULL, "audio1_doubler", "audio1", 1137 CLK_SET_RATE_PARENT, 2, 1); 1138 clk = tegra_clk_register_divider("audio1_div", "audio1_doubler", 1139 clk_base + AUDIO_SYNC_DOUBLER, 0, 0, 25, 1, 0, 1140 &clk_doubler_lock); 1141 clk = tegra_clk_register_periph_gate("audio1_2x", "audio1_div", 1142 TEGRA_PERIPH_NO_RESET, clk_base, 1143 CLK_SET_RATE_PARENT, 114, &periph_v_regs, 1144 periph_clk_enb_refcnt); 1145 clk_register_clkdev(clk, "audio1_2x", NULL); 1146 clks[audio1_2x] = clk; 1147 1148 /* audio2_2x */ 1149 clk = clk_register_fixed_factor(NULL, "audio2_doubler", "audio2", 1150 CLK_SET_RATE_PARENT, 2, 1); 1151 clk = tegra_clk_register_divider("audio2_div", "audio2_doubler", 1152 clk_base + AUDIO_SYNC_DOUBLER, 0, 0, 26, 1, 0, 1153 &clk_doubler_lock); 1154 clk = tegra_clk_register_periph_gate("audio2_2x", "audio2_div", 1155 TEGRA_PERIPH_NO_RESET, clk_base, 1156 CLK_SET_RATE_PARENT, 115, &periph_v_regs, 1157 periph_clk_enb_refcnt); 1158 clk_register_clkdev(clk, "audio2_2x", NULL); 1159 clks[audio2_2x] = clk; 1160 1161 /* audio3_2x */ 1162 clk = clk_register_fixed_factor(NULL, "audio3_doubler", "audio3", 1163 CLK_SET_RATE_PARENT, 2, 1); 1164 clk = tegra_clk_register_divider("audio3_div", "audio3_doubler", 1165 clk_base + AUDIO_SYNC_DOUBLER, 0, 0, 27, 1, 0, 1166 &clk_doubler_lock); 1167 clk = tegra_clk_register_periph_gate("audio3_2x", "audio3_div", 1168 TEGRA_PERIPH_NO_RESET, clk_base, 1169 CLK_SET_RATE_PARENT, 116, &periph_v_regs, 1170 periph_clk_enb_refcnt); 1171 clk_register_clkdev(clk, "audio3_2x", NULL); 1172 clks[audio3_2x] = clk; 1173 1174 /* audio4_2x */ 1175 clk = clk_register_fixed_factor(NULL, "audio4_doubler", "audio4", 1176 CLK_SET_RATE_PARENT, 2, 1); 1177 clk = tegra_clk_register_divider("audio4_div", "audio4_doubler", 1178 clk_base + AUDIO_SYNC_DOUBLER, 0, 0, 28, 1, 0, 1179 &clk_doubler_lock); 1180 clk = tegra_clk_register_periph_gate("audio4_2x", "audio4_div", 1181 TEGRA_PERIPH_NO_RESET, clk_base, 1182 CLK_SET_RATE_PARENT, 117, &periph_v_regs, 1183 periph_clk_enb_refcnt); 1184 clk_register_clkdev(clk, "audio4_2x", NULL); 1185 clks[audio4_2x] = clk; 1186 1187 /* spdif_2x */ 1188 clk = clk_register_fixed_factor(NULL, "spdif_doubler", "spdif", 1189 CLK_SET_RATE_PARENT, 2, 1); 1190 clk = tegra_clk_register_divider("spdif_div", "spdif_doubler", 1191 clk_base + AUDIO_SYNC_DOUBLER, 0, 0, 29, 1, 0, 1192 &clk_doubler_lock); 1193 clk = tegra_clk_register_periph_gate("spdif_2x", "spdif_div", 1194 TEGRA_PERIPH_NO_RESET, clk_base, 1195 CLK_SET_RATE_PARENT, 118, &periph_v_regs, 1196 periph_clk_enb_refcnt); 1197 clk_register_clkdev(clk, "spdif_2x", NULL); 1198 clks[spdif_2x] = clk; 1199} 1200 1201static void __init tegra30_pmc_clk_init(void) 1202{ 1203 struct clk *clk; 1204 1205 /* clk_out_1 */ 1206 clk = clk_register_mux(NULL, "clk_out_1_mux", clk_out1_parents, 1207 ARRAY_SIZE(clk_out1_parents), 0, 1208 pmc_base + PMC_CLK_OUT_CNTRL, 6, 3, 0, 1209 &clk_out_lock); 1210 clks[clk_out_1_mux] = clk; 1211 clk = clk_register_gate(NULL, "clk_out_1", "clk_out_1_mux", 0, 1212 pmc_base + PMC_CLK_OUT_CNTRL, 2, 0, 1213 &clk_out_lock); 1214 clk_register_clkdev(clk, "extern1", "clk_out_1"); 1215 clks[clk_out_1] = clk; 1216 1217 /* clk_out_2 */ 1218 clk = clk_register_mux(NULL, "clk_out_2_mux", clk_out2_parents, 1219 ARRAY_SIZE(clk_out1_parents), 0, 1220 pmc_base + PMC_CLK_OUT_CNTRL, 14, 3, 0, 1221 &clk_out_lock); 1222 clk = clk_register_gate(NULL, "clk_out_2", "clk_out_2_mux", 0, 1223 pmc_base + PMC_CLK_OUT_CNTRL, 10, 0, 1224 &clk_out_lock); 1225 clk_register_clkdev(clk, "extern2", "clk_out_2"); 1226 clks[clk_out_2] = clk; 1227 1228 /* clk_out_3 */ 1229 clk = clk_register_mux(NULL, "clk_out_3_mux", clk_out3_parents, 1230 ARRAY_SIZE(clk_out1_parents), 0, 1231 pmc_base + PMC_CLK_OUT_CNTRL, 22, 3, 0, 1232 &clk_out_lock); 1233 clk = clk_register_gate(NULL, "clk_out_3", "clk_out_3_mux", 0, 1234 pmc_base + PMC_CLK_OUT_CNTRL, 18, 0, 1235 &clk_out_lock); 1236 clk_register_clkdev(clk, "extern3", "clk_out_3"); 1237 clks[clk_out_3] = clk; 1238 1239 /* blink */ 1240 writel_relaxed(0, pmc_base + PMC_BLINK_TIMER); 1241 clk = clk_register_gate(NULL, "blink_override", "clk_32k", 0, 1242 pmc_base + PMC_DPD_PADS_ORIDE, 1243 PMC_DPD_PADS_ORIDE_BLINK_ENB, 0, NULL); 1244 clk = clk_register_gate(NULL, "blink", "blink_override", 0, 1245 pmc_base + PMC_CTRL, 1246 PMC_CTRL_BLINK_ENB, 0, NULL); 1247 clk_register_clkdev(clk, "blink", NULL); 1248 clks[blink] = clk; 1249 1250} 1251 1252const char *cclk_g_parents[] = { "clk_m", "pll_c", "clk_32k", "pll_m", 1253 "pll_p_cclkg", "pll_p_out4_cclkg", 1254 "pll_p_out3_cclkg", "unused", "pll_x" }; 1255const char *cclk_lp_parents[] = { "clk_m", "pll_c", "clk_32k", "pll_m", 1256 "pll_p_cclklp", "pll_p_out4_cclklp", 1257 "pll_p_out3_cclklp", "unused", "pll_x", 1258 "pll_x_out0" }; 1259const char *sclk_parents[] = { "clk_m", "pll_c_out1", "pll_p_out4", 1260 "pll_p_out3", "pll_p_out2", "unused", 1261 "clk_32k", "pll_m_out1" }; 1262 1263static void __init tegra30_super_clk_init(void) 1264{ 1265 struct clk *clk; 1266 1267 /* 1268 * Clock input to cclk_g divided from pll_p using 1269 * U71 divider of cclk_g. 1270 */ 1271 clk = tegra_clk_register_divider("pll_p_cclkg", "pll_p", 1272 clk_base + SUPER_CCLKG_DIVIDER, 0, 1273 TEGRA_DIVIDER_INT, 16, 8, 1, NULL); 1274 clk_register_clkdev(clk, "pll_p_cclkg", NULL); 1275 1276 /* 1277 * Clock input to cclk_g divided from pll_p_out3 using 1278 * U71 divider of cclk_g. 1279 */ 1280 clk = tegra_clk_register_divider("pll_p_out3_cclkg", "pll_p_out3", 1281 clk_base + SUPER_CCLKG_DIVIDER, 0, 1282 TEGRA_DIVIDER_INT, 16, 8, 1, NULL); 1283 clk_register_clkdev(clk, "pll_p_out3_cclkg", NULL); 1284 1285 /* 1286 * Clock input to cclk_g divided from pll_p_out4 using 1287 * U71 divider of cclk_g. 1288 */ 1289 clk = tegra_clk_register_divider("pll_p_out4_cclkg", "pll_p_out4", 1290 clk_base + SUPER_CCLKG_DIVIDER, 0, 1291 TEGRA_DIVIDER_INT, 16, 8, 1, NULL); 1292 clk_register_clkdev(clk, "pll_p_out4_cclkg", NULL); 1293 1294 /* CCLKG */ 1295 clk = tegra_clk_register_super_mux("cclk_g", cclk_g_parents, 1296 ARRAY_SIZE(cclk_g_parents), 1297 CLK_SET_RATE_PARENT, 1298 clk_base + CCLKG_BURST_POLICY, 1299 0, 4, 0, 0, NULL); 1300 clk_register_clkdev(clk, "cclk_g", NULL); 1301 clks[cclk_g] = clk; 1302 1303 /* 1304 * Clock input to cclk_lp divided from pll_p using 1305 * U71 divider of cclk_lp. 1306 */ 1307 clk = tegra_clk_register_divider("pll_p_cclklp", "pll_p", 1308 clk_base + SUPER_CCLKLP_DIVIDER, 0, 1309 TEGRA_DIVIDER_INT, 16, 8, 1, NULL); 1310 clk_register_clkdev(clk, "pll_p_cclklp", NULL); 1311 1312 /* 1313 * Clock input to cclk_lp divided from pll_p_out3 using 1314 * U71 divider of cclk_lp. 1315 */ 1316 clk = tegra_clk_register_divider("pll_p_out3_cclklp", "pll_p_out3", 1317 clk_base + SUPER_CCLKG_DIVIDER, 0, 1318 TEGRA_DIVIDER_INT, 16, 8, 1, NULL); 1319 clk_register_clkdev(clk, "pll_p_out3_cclklp", NULL); 1320 1321 /* 1322 * Clock input to cclk_lp divided from pll_p_out4 using 1323 * U71 divider of cclk_lp. 1324 */ 1325 clk = tegra_clk_register_divider("pll_p_out4_cclklp", "pll_p_out4", 1326 clk_base + SUPER_CCLKLP_DIVIDER, 0, 1327 TEGRA_DIVIDER_INT, 16, 8, 1, NULL); 1328 clk_register_clkdev(clk, "pll_p_out4_cclklp", NULL); 1329 1330 /* CCLKLP */ 1331 clk = tegra_clk_register_super_mux("cclk_lp", cclk_lp_parents, 1332 ARRAY_SIZE(cclk_lp_parents), 1333 CLK_SET_RATE_PARENT, 1334 clk_base + CCLKLP_BURST_POLICY, 1335 TEGRA_DIVIDER_2, 4, 8, 9, 1336 NULL); 1337 clk_register_clkdev(clk, "cclk_lp", NULL); 1338 clks[cclk_lp] = clk; 1339 1340 /* SCLK */ 1341 clk = tegra_clk_register_super_mux("sclk", sclk_parents, 1342 ARRAY_SIZE(sclk_parents), 1343 CLK_SET_RATE_PARENT, 1344 clk_base + SCLK_BURST_POLICY, 1345 0, 4, 0, 0, NULL); 1346 clk_register_clkdev(clk, "sclk", NULL); 1347 clks[sclk] = clk; 1348 1349 /* HCLK */ 1350 clk = clk_register_divider(NULL, "hclk_div", "sclk", 0, 1351 clk_base + SYSTEM_CLK_RATE, 4, 2, 0, NULL); 1352 clk = clk_register_gate(NULL, "hclk", "hclk_div", CLK_SET_RATE_PARENT, 1353 clk_base + SYSTEM_CLK_RATE, 7, 1354 CLK_GATE_SET_TO_DISABLE, NULL); 1355 clk_register_clkdev(clk, "hclk", NULL); 1356 clks[hclk] = clk; 1357 1358 /* PCLK */ 1359 clk = clk_register_divider(NULL, "pclk_div", "hclk", 0, 1360 clk_base + SYSTEM_CLK_RATE, 0, 2, 0, NULL); 1361 clk = clk_register_gate(NULL, "pclk", "pclk_div", CLK_SET_RATE_PARENT, 1362 clk_base + SYSTEM_CLK_RATE, 3, 1363 CLK_GATE_SET_TO_DISABLE, NULL); 1364 clk_register_clkdev(clk, "pclk", NULL); 1365 clks[pclk] = clk; 1366 1367 /* twd */ 1368 clk = clk_register_fixed_factor(NULL, "twd", "cclk_g", 1369 CLK_SET_RATE_PARENT, 1, 2); 1370 clk_register_clkdev(clk, "twd", NULL); 1371 clks[twd] = clk; 1372} 1373 1374static const char *mux_pllacp_clkm[] = { "pll_a_out0", "unused", "pll_p", 1375 "clk_m" }; 1376static const char *mux_pllpcm_clkm[] = { "pll_p", "pll_c", "pll_m", "clk_m" }; 1377static const char *mux_pllmcp_clkm[] = { "pll_m", "pll_c", "pll_p", "clk_m" }; 1378static const char *i2s0_parents[] = { "pll_a_out0", "audio0_2x", "pll_p", 1379 "clk_m" }; 1380static const char *i2s1_parents[] = { "pll_a_out0", "audio1_2x", "pll_p", 1381 "clk_m" }; 1382static const char *i2s2_parents[] = { "pll_a_out0", "audio2_2x", "pll_p", 1383 "clk_m" }; 1384static const char *i2s3_parents[] = { "pll_a_out0", "audio3_2x", "pll_p", 1385 "clk_m" }; 1386static const char *i2s4_parents[] = { "pll_a_out0", "audio4_2x", "pll_p", 1387 "clk_m" }; 1388static const char *spdif_out_parents[] = { "pll_a_out0", "spdif_2x", "pll_p", 1389 "clk_m" }; 1390static const char *spdif_in_parents[] = { "pll_p", "pll_c", "pll_m" }; 1391static const char *mux_pllpc_clk32k_clkm[] = { "pll_p", "pll_c", "clk_32k", 1392 "clk_m" }; 1393static const char *mux_pllpc_clkm_clk32k[] = { "pll_p", "pll_c", "clk_m", 1394 "clk_32k" }; 1395static const char *mux_pllmcpa[] = { "pll_m", "pll_c", "pll_p", "pll_a_out0" }; 1396static const char *mux_pllpdc_clkm[] = { "pll_p", "pll_d_out0", "pll_c", 1397 "clk_m" }; 1398static const char *mux_pllp_clkm[] = { "pll_p", "unused", "unused", "clk_m" }; 1399static const char *mux_pllpmdacd2_clkm[] = { "pll_p", "pll_m", "pll_d_out0", 1400 "pll_a_out0", "pll_c", 1401 "pll_d2_out0", "clk_m" }; 1402static const char *mux_plla_clk32k_pllp_clkm_plle[] = { "pll_a_out0", 1403 "clk_32k", "pll_p", 1404 "clk_m", "pll_e" }; 1405static const char *mux_plld_out0_plld2_out0[] = { "pll_d_out0", 1406 "pll_d2_out0" }; 1407 1408static struct tegra_periph_init_data tegra_periph_clk_list[] = { 1409 TEGRA_INIT_DATA_MUX("i2s0", NULL, "tegra30-i2s.0", i2s0_parents, CLK_SOURCE_I2S0, 30, &periph_l_regs, TEGRA_PERIPH_ON_APB, i2s0), 1410 TEGRA_INIT_DATA_MUX("i2s1", NULL, "tegra30-i2s.1", i2s1_parents, CLK_SOURCE_I2S1, 11, &periph_l_regs, TEGRA_PERIPH_ON_APB, i2s1), 1411 TEGRA_INIT_DATA_MUX("i2s2", NULL, "tegra30-i2s.2", i2s2_parents, CLK_SOURCE_I2S2, 18, &periph_l_regs, TEGRA_PERIPH_ON_APB, i2s2), 1412 TEGRA_INIT_DATA_MUX("i2s3", NULL, "tegra30-i2s.3", i2s3_parents, CLK_SOURCE_I2S3, 101, &periph_v_regs, TEGRA_PERIPH_ON_APB, i2s3), 1413 TEGRA_INIT_DATA_MUX("i2s4", NULL, "tegra30-i2s.4", i2s4_parents, CLK_SOURCE_I2S4, 102, &periph_v_regs, TEGRA_PERIPH_ON_APB, i2s4), 1414 TEGRA_INIT_DATA_MUX("spdif_out", "spdif_out", "tegra30-spdif", spdif_out_parents, CLK_SOURCE_SPDIF_OUT, 10, &periph_l_regs, TEGRA_PERIPH_ON_APB, spdif_out), 1415 TEGRA_INIT_DATA_MUX("spdif_in", "spdif_in", "tegra30-spdif", spdif_in_parents, CLK_SOURCE_SPDIF_IN, 10, &periph_l_regs, TEGRA_PERIPH_ON_APB, spdif_in), 1416 TEGRA_INIT_DATA_MUX("d_audio", "d_audio", "tegra30-ahub", mux_pllacp_clkm, CLK_SOURCE_D_AUDIO, 106, &periph_v_regs, 0, d_audio), 1417 TEGRA_INIT_DATA_MUX("dam0", NULL, "tegra30-dam.0", mux_pllacp_clkm, CLK_SOURCE_DAM0, 108, &periph_v_regs, 0, dam0), 1418 TEGRA_INIT_DATA_MUX("dam1", NULL, "tegra30-dam.1", mux_pllacp_clkm, CLK_SOURCE_DAM1, 109, &periph_v_regs, 0, dam1), 1419 TEGRA_INIT_DATA_MUX("dam2", NULL, "tegra30-dam.2", mux_pllacp_clkm, CLK_SOURCE_DAM2, 110, &periph_v_regs, 0, dam2), 1420 TEGRA_INIT_DATA_MUX("hda", "hda", "tegra30-hda", mux_pllpcm_clkm, CLK_SOURCE_HDA, 125, &periph_v_regs, 0, hda), 1421 TEGRA_INIT_DATA_MUX("hda2codec_2x", "hda2codec", "tegra30-hda", mux_pllpcm_clkm, CLK_SOURCE_HDA2CODEC_2X, 111, &periph_v_regs, 0, hda2codec_2x), 1422 TEGRA_INIT_DATA_MUX("sbc1", NULL, "spi_tegra.0", mux_pllpcm_clkm, CLK_SOURCE_SBC1, 41, &periph_h_regs, TEGRA_PERIPH_ON_APB, sbc1), 1423 TEGRA_INIT_DATA_MUX("sbc2", NULL, "spi_tegra.1", mux_pllpcm_clkm, CLK_SOURCE_SBC2, 44, &periph_h_regs, TEGRA_PERIPH_ON_APB, sbc2), 1424 TEGRA_INIT_DATA_MUX("sbc3", NULL, "spi_tegra.2", mux_pllpcm_clkm, CLK_SOURCE_SBC3, 46, &periph_h_regs, TEGRA_PERIPH_ON_APB, sbc3), 1425 TEGRA_INIT_DATA_MUX("sbc4", NULL, "spi_tegra.3", mux_pllpcm_clkm, CLK_SOURCE_SBC4, 68, &periph_u_regs, TEGRA_PERIPH_ON_APB, sbc4), 1426 TEGRA_INIT_DATA_MUX("sbc5", NULL, "spi_tegra.4", mux_pllpcm_clkm, CLK_SOURCE_SBC5, 104, &periph_v_regs, TEGRA_PERIPH_ON_APB, sbc5), 1427 TEGRA_INIT_DATA_MUX("sbc6", NULL, "spi_tegra.5", mux_pllpcm_clkm, CLK_SOURCE_SBC6, 105, &periph_v_regs, TEGRA_PERIPH_ON_APB, sbc6), 1428 TEGRA_INIT_DATA_MUX("sata_oob", NULL, "tegra_sata_oob", mux_pllpcm_clkm, CLK_SOURCE_SATA_OOB, 123, &periph_v_regs, TEGRA_PERIPH_ON_APB, sata_oob), 1429 TEGRA_INIT_DATA_MUX("sata", NULL, "tegra_sata", mux_pllpcm_clkm, CLK_SOURCE_SATA, 124, &periph_v_regs, TEGRA_PERIPH_ON_APB, sata), 1430 TEGRA_INIT_DATA_MUX("ndflash", NULL, "tegra_nand", mux_pllpcm_clkm, CLK_SOURCE_NDFLASH, 13, &periph_l_regs, TEGRA_PERIPH_ON_APB, ndflash), 1431 TEGRA_INIT_DATA_MUX("ndspeed", NULL, "tegra_nand_speed", mux_pllpcm_clkm, CLK_SOURCE_NDSPEED, 80, &periph_u_regs, TEGRA_PERIPH_ON_APB, ndspeed), 1432 TEGRA_INIT_DATA_MUX("vfir", NULL, "vfir", mux_pllpcm_clkm, CLK_SOURCE_VFIR, 7, &periph_l_regs, TEGRA_PERIPH_ON_APB, vfir), 1433 TEGRA_INIT_DATA_MUX("csite", NULL, "csite", mux_pllpcm_clkm, CLK_SOURCE_CSITE, 73, &periph_u_regs, TEGRA_PERIPH_ON_APB, csite), 1434 TEGRA_INIT_DATA_MUX("la", NULL, "la", mux_pllpcm_clkm, CLK_SOURCE_LA, 76, &periph_u_regs, TEGRA_PERIPH_ON_APB, la), 1435 TEGRA_INIT_DATA_MUX("owr", NULL, "tegra_w1", mux_pllpcm_clkm, CLK_SOURCE_OWR, 71, &periph_u_regs, TEGRA_PERIPH_ON_APB, owr), 1436 TEGRA_INIT_DATA_MUX("mipi", NULL, "mipi", mux_pllpcm_clkm, CLK_SOURCE_MIPI, 50, &periph_h_regs, TEGRA_PERIPH_ON_APB, mipi), 1437 TEGRA_INIT_DATA_MUX("tsensor", NULL, "tegra-tsensor", mux_pllpc_clkm_clk32k, CLK_SOURCE_TSENSOR, 100, &periph_v_regs, TEGRA_PERIPH_ON_APB, tsensor), 1438 TEGRA_INIT_DATA_MUX("i2cslow", NULL, "i2cslow", mux_pllpc_clk32k_clkm, CLK_SOURCE_I2CSLOW, 81, &periph_u_regs, TEGRA_PERIPH_ON_APB, i2cslow), 1439 TEGRA_INIT_DATA_INT("vde", NULL, "vde", mux_pllpcm_clkm, CLK_SOURCE_VDE, 61, &periph_h_regs, 0, vde), 1440 TEGRA_INIT_DATA_INT("vi", "vi", "tegra_camera", mux_pllmcpa, CLK_SOURCE_VI, 20, &periph_l_regs, 0, vi), 1441 TEGRA_INIT_DATA_INT("epp", NULL, "epp", mux_pllmcpa, CLK_SOURCE_EPP, 19, &periph_l_regs, 0, epp), 1442 TEGRA_INIT_DATA_INT("mpe", NULL, "mpe", mux_pllmcpa, CLK_SOURCE_MPE, 60, &periph_h_regs, 0, mpe), 1443 TEGRA_INIT_DATA_INT("host1x", NULL, "host1x", mux_pllmcpa, CLK_SOURCE_HOST1X, 28, &periph_l_regs, 0, host1x), 1444 TEGRA_INIT_DATA_INT("3d", NULL, "3d", mux_pllmcpa, CLK_SOURCE_3D, 24, &periph_l_regs, TEGRA_PERIPH_MANUAL_RESET, gr3d), 1445 TEGRA_INIT_DATA_INT("3d2", NULL, "3d2", mux_pllmcpa, CLK_SOURCE_3D2, 98, &periph_v_regs, TEGRA_PERIPH_MANUAL_RESET, gr3d2), 1446 TEGRA_INIT_DATA_INT("2d", NULL, "2d", mux_pllmcpa, CLK_SOURCE_2D, 21, &periph_l_regs, 0, gr2d), 1447 TEGRA_INIT_DATA_INT("se", NULL, "se", mux_pllpcm_clkm, CLK_SOURCE_SE, 127, &periph_v_regs, 0, se), 1448 TEGRA_INIT_DATA_MUX("mselect", NULL, "mselect", mux_pllp_clkm, CLK_SOURCE_MSELECT, 99, &periph_v_regs, 0, mselect), 1449 TEGRA_INIT_DATA_MUX("nor", NULL, "tegra-nor", mux_pllpcm_clkm, CLK_SOURCE_NOR, 42, &periph_h_regs, 0, nor), 1450 TEGRA_INIT_DATA_MUX("sdmmc1", NULL, "sdhci-tegra.0", mux_pllpcm_clkm, CLK_SOURCE_SDMMC1, 14, &periph_l_regs, 0, sdmmc1), 1451 TEGRA_INIT_DATA_MUX("sdmmc2", NULL, "sdhci-tegra.1", mux_pllpcm_clkm, CLK_SOURCE_SDMMC2, 9, &periph_l_regs, 0, sdmmc2), 1452 TEGRA_INIT_DATA_MUX("sdmmc3", NULL, "sdhci-tegra.2", mux_pllpcm_clkm, CLK_SOURCE_SDMMC3, 69, &periph_u_regs, 0, sdmmc3), 1453 TEGRA_INIT_DATA_MUX("sdmmc4", NULL, "sdhci-tegra.3", mux_pllpcm_clkm, CLK_SOURCE_SDMMC4, 15, &periph_l_regs, 0, sdmmc4), 1454 TEGRA_INIT_DATA_MUX("cve", NULL, "cve", mux_pllpdc_clkm, CLK_SOURCE_CVE, 49, &periph_h_regs, 0, cve), 1455 TEGRA_INIT_DATA_MUX("tvo", NULL, "tvo", mux_pllpdc_clkm, CLK_SOURCE_TVO, 49, &periph_h_regs, 0, tvo), 1456 TEGRA_INIT_DATA_MUX("tvdac", NULL, "tvdac", mux_pllpdc_clkm, CLK_SOURCE_TVDAC, 53, &periph_h_regs, 0, tvdac), 1457 TEGRA_INIT_DATA_MUX("actmon", NULL, "actmon", mux_pllpc_clk32k_clkm, CLK_SOURCE_ACTMON, 119, &periph_v_regs, 0, actmon), 1458 TEGRA_INIT_DATA_MUX("vi_sensor", "vi_sensor", "tegra_camera", mux_pllmcpa, CLK_SOURCE_VI_SENSOR, 20, &periph_l_regs, TEGRA_PERIPH_NO_RESET, vi_sensor), 1459 TEGRA_INIT_DATA_DIV16("i2c1", "div-clk", "tegra-i2c.0", mux_pllp_clkm, CLK_SOURCE_I2C1, 12, &periph_l_regs, TEGRA_PERIPH_ON_APB, i2c1), 1460 TEGRA_INIT_DATA_DIV16("i2c2", "div-clk", "tegra-i2c.1", mux_pllp_clkm, CLK_SOURCE_I2C2, 54, &periph_h_regs, TEGRA_PERIPH_ON_APB, i2c2), 1461 TEGRA_INIT_DATA_DIV16("i2c3", "div-clk", "tegra-i2c.2", mux_pllp_clkm, CLK_SOURCE_I2C3, 67, &periph_u_regs, TEGRA_PERIPH_ON_APB, i2c3), 1462 TEGRA_INIT_DATA_DIV16("i2c4", "div-clk", "tegra-i2c.3", mux_pllp_clkm, CLK_SOURCE_I2C4, 103, &periph_v_regs, TEGRA_PERIPH_ON_APB, i2c4), 1463 TEGRA_INIT_DATA_DIV16("i2c5", "div-clk", "tegra-i2c.4", mux_pllp_clkm, CLK_SOURCE_I2C5, 47, &periph_h_regs, TEGRA_PERIPH_ON_APB, i2c5), 1464 TEGRA_INIT_DATA_UART("uarta", NULL, "tegra_uart.0", mux_pllpcm_clkm, CLK_SOURCE_UARTA, 6, &periph_l_regs, uarta), 1465 TEGRA_INIT_DATA_UART("uartb", NULL, "tegra_uart.1", mux_pllpcm_clkm, CLK_SOURCE_UARTB, 7, &periph_l_regs, uartb), 1466 TEGRA_INIT_DATA_UART("uartc", NULL, "tegra_uart.2", mux_pllpcm_clkm, CLK_SOURCE_UARTC, 55, &periph_h_regs, uartc), 1467 TEGRA_INIT_DATA_UART("uartd", NULL, "tegra_uart.3", mux_pllpcm_clkm, CLK_SOURCE_UARTD, 65, &periph_u_regs, uartd), 1468 TEGRA_INIT_DATA_UART("uarte", NULL, "tegra_uart.4", mux_pllpcm_clkm, CLK_SOURCE_UARTE, 66, &periph_u_regs, uarte), 1469 TEGRA_INIT_DATA_MUX8("hdmi", NULL, "hdmi", mux_pllpmdacd2_clkm, CLK_SOURCE_HDMI, 51, &periph_h_regs, 0, hdmi), 1470 TEGRA_INIT_DATA_MUX8("extern1", NULL, "extern1", mux_plla_clk32k_pllp_clkm_plle, CLK_SOURCE_EXTERN1, 120, &periph_v_regs, 0, extern1), 1471 TEGRA_INIT_DATA_MUX8("extern2", NULL, "extern2", mux_plla_clk32k_pllp_clkm_plle, CLK_SOURCE_EXTERN2, 121, &periph_v_regs, 0, extern2), 1472 TEGRA_INIT_DATA_MUX8("extern3", NULL, "extern3", mux_plla_clk32k_pllp_clkm_plle, CLK_SOURCE_EXTERN3, 122, &periph_v_regs, 0, extern3), 1473 TEGRA_INIT_DATA("pwm", NULL, "pwm", mux_pllpc_clk32k_clkm, CLK_SOURCE_PWM, 28, 2, 0, 0, 8, 1, 0, &periph_l_regs, 17, periph_clk_enb_refcnt, 0, pwm), 1474}; 1475 1476static struct tegra_periph_init_data tegra_periph_nodiv_clk_list[] = { 1477 TEGRA_INIT_DATA_NODIV("disp1", NULL, "tegradc.0", mux_pllpmdacd2_clkm, CLK_SOURCE_DISP1, 29, 3, 27, &periph_l_regs, 0, disp1), 1478 TEGRA_INIT_DATA_NODIV("disp2", NULL, "tegradc.1", mux_pllpmdacd2_clkm, CLK_SOURCE_DISP2, 29, 3, 26, &periph_l_regs, 0, disp2), 1479 TEGRA_INIT_DATA_NODIV("dsib", NULL, "tegradc.1", mux_plld_out0_plld2_out0, CLK_SOURCE_DSIB, 25, 1, 82, &periph_u_regs, 0, dsib), 1480}; 1481 1482static void __init tegra30_periph_clk_init(void) 1483{ 1484 struct tegra_periph_init_data *data; 1485 struct clk *clk; 1486 int i; 1487 1488 /* apbdma */ 1489 clk = tegra_clk_register_periph_gate("apbdma", "clk_m", 0, clk_base, 0, 34, 1490 &periph_h_regs, periph_clk_enb_refcnt); 1491 clk_register_clkdev(clk, NULL, "tegra-apbdma"); 1492 clks[apbdma] = clk; 1493 1494 /* rtc */ 1495 clk = tegra_clk_register_periph_gate("rtc", "clk_32k", 1496 TEGRA_PERIPH_NO_RESET | TEGRA_PERIPH_ON_APB, 1497 clk_base, 0, 4, &periph_l_regs, 1498 periph_clk_enb_refcnt); 1499 clk_register_clkdev(clk, NULL, "rtc-tegra"); 1500 clks[rtc] = clk; 1501 1502 /* timer */ 1503 clk = tegra_clk_register_periph_gate("timer", "clk_m", 0, clk_base, 0, 1504 5, &periph_l_regs, periph_clk_enb_refcnt); 1505 clk_register_clkdev(clk, NULL, "timer"); 1506 clks[timer] = clk; 1507 1508 /* kbc */ 1509 clk = tegra_clk_register_periph_gate("kbc", "clk_32k", 1510 TEGRA_PERIPH_NO_RESET | TEGRA_PERIPH_ON_APB, 1511 clk_base, 0, 36, &periph_h_regs, 1512 periph_clk_enb_refcnt); 1513 clk_register_clkdev(clk, NULL, "tegra-kbc"); 1514 clks[kbc] = clk; 1515 1516 /* csus */ 1517 clk = tegra_clk_register_periph_gate("csus", "clk_m", 1518 TEGRA_PERIPH_NO_RESET | TEGRA_PERIPH_ON_APB, 1519 clk_base, 0, 92, &periph_u_regs, 1520 periph_clk_enb_refcnt); 1521 clk_register_clkdev(clk, "csus", "tengra_camera"); 1522 clks[csus] = clk; 1523 1524 /* vcp */ 1525 clk = tegra_clk_register_periph_gate("vcp", "clk_m", 0, clk_base, 0, 29, 1526 &periph_l_regs, periph_clk_enb_refcnt); 1527 clk_register_clkdev(clk, "vcp", "tegra-avp"); 1528 clks[vcp] = clk; 1529 1530 /* bsea */ 1531 clk = tegra_clk_register_periph_gate("bsea", "clk_m", 0, clk_base, 0, 1532 62, &periph_h_regs, periph_clk_enb_refcnt); 1533 clk_register_clkdev(clk, "bsea", "tegra-avp"); 1534 clks[bsea] = clk; 1535 1536 /* bsev */ 1537 clk = tegra_clk_register_periph_gate("bsev", "clk_m", 0, clk_base, 0, 1538 63, &periph_h_regs, periph_clk_enb_refcnt); 1539 clk_register_clkdev(clk, "bsev", "tegra-aes"); 1540 clks[bsev] = clk; 1541 1542 /* usbd */ 1543 clk = tegra_clk_register_periph_gate("usbd", "clk_m", 0, clk_base, 0, 1544 22, &periph_l_regs, periph_clk_enb_refcnt); 1545 clk_register_clkdev(clk, NULL, "fsl-tegra-udc"); 1546 clks[usbd] = clk; 1547 1548 /* usb2 */ 1549 clk = tegra_clk_register_periph_gate("usb2", "clk_m", 0, clk_base, 0, 1550 58, &periph_h_regs, periph_clk_enb_refcnt); 1551 clk_register_clkdev(clk, NULL, "tegra-ehci.1"); 1552 clks[usb2] = clk; 1553 1554 /* usb3 */ 1555 clk = tegra_clk_register_periph_gate("usb3", "clk_m", 0, clk_base, 0, 1556 59, &periph_h_regs, periph_clk_enb_refcnt); 1557 clk_register_clkdev(clk, NULL, "tegra-ehci.2"); 1558 clks[usb3] = clk; 1559 1560 /* dsia */ 1561 clk = tegra_clk_register_periph_gate("dsia", "pll_d_out0", 0, clk_base, 1562 0, 48, &periph_h_regs, 1563 periph_clk_enb_refcnt); 1564 clk_register_clkdev(clk, "dsia", "tegradc.0"); 1565 clks[dsia] = clk; 1566 1567 /* csi */ 1568 clk = tegra_clk_register_periph_gate("csi", "pll_p_out3", 0, clk_base, 1569 0, 52, &periph_h_regs, 1570 periph_clk_enb_refcnt); 1571 clk_register_clkdev(clk, "csi", "tegra_camera"); 1572 clks[csi] = clk; 1573 1574 /* isp */ 1575 clk = tegra_clk_register_periph_gate("isp", "clk_m", 0, clk_base, 0, 23, 1576 &periph_l_regs, periph_clk_enb_refcnt); 1577 clk_register_clkdev(clk, "isp", "tegra_camera"); 1578 clks[isp] = clk; 1579 1580 /* pcie */ 1581 clk = tegra_clk_register_periph_gate("pcie", "clk_m", 0, clk_base, 0, 1582 70, &periph_u_regs, periph_clk_enb_refcnt); 1583 clk_register_clkdev(clk, "pcie", "tegra-pcie"); 1584 clks[pcie] = clk; 1585 1586 /* afi */ 1587 clk = tegra_clk_register_periph_gate("afi", "clk_m", 0, clk_base, 0, 72, 1588 &periph_u_regs, periph_clk_enb_refcnt); 1589 clk_register_clkdev(clk, "afi", "tegra-pcie"); 1590 clks[afi] = clk; 1591 1592 /* kfuse */ 1593 clk = tegra_clk_register_periph_gate("kfuse", "clk_m", 1594 TEGRA_PERIPH_ON_APB, 1595 clk_base, 0, 40, &periph_h_regs, 1596 periph_clk_enb_refcnt); 1597 clk_register_clkdev(clk, NULL, "kfuse-tegra"); 1598 clks[kfuse] = clk; 1599 1600 /* fuse */ 1601 clk = tegra_clk_register_periph_gate("fuse", "clk_m", 1602 TEGRA_PERIPH_ON_APB, 1603 clk_base, 0, 39, &periph_h_regs, 1604 periph_clk_enb_refcnt); 1605 clk_register_clkdev(clk, "fuse", "fuse-tegra"); 1606 clks[fuse] = clk; 1607 1608 /* fuse_burn */ 1609 clk = tegra_clk_register_periph_gate("fuse_burn", "clk_m", 1610 TEGRA_PERIPH_ON_APB, 1611 clk_base, 0, 39, &periph_h_regs, 1612 periph_clk_enb_refcnt); 1613 clk_register_clkdev(clk, "fuse_burn", "fuse-tegra"); 1614 clks[fuse_burn] = clk; 1615 1616 /* apbif */ 1617 clk = tegra_clk_register_periph_gate("apbif", "clk_m", 0, 1618 clk_base, 0, 107, &periph_v_regs, 1619 periph_clk_enb_refcnt); 1620 clk_register_clkdev(clk, "apbif", "tegra30-ahub"); 1621 clks[apbif] = clk; 1622 1623 /* hda2hdmi */ 1624 clk = tegra_clk_register_periph_gate("hda2hdmi", "clk_m", 1625 TEGRA_PERIPH_ON_APB, 1626 clk_base, 0, 128, &periph_w_regs, 1627 periph_clk_enb_refcnt); 1628 clk_register_clkdev(clk, "hda2hdmi", "tegra30-hda"); 1629 clks[hda2hdmi] = clk; 1630 1631 /* sata_cold */ 1632 clk = tegra_clk_register_periph_gate("sata_cold", "clk_m", 1633 TEGRA_PERIPH_ON_APB, 1634 clk_base, 0, 129, &periph_w_regs, 1635 periph_clk_enb_refcnt); 1636 clk_register_clkdev(clk, NULL, "tegra_sata_cold"); 1637 clks[sata_cold] = clk; 1638 1639 /* dtv */ 1640 clk = tegra_clk_register_periph_gate("dtv", "clk_m", 1641 TEGRA_PERIPH_ON_APB, 1642 clk_base, 0, 79, &periph_u_regs, 1643 periph_clk_enb_refcnt); 1644 clk_register_clkdev(clk, NULL, "dtv"); 1645 clks[dtv] = clk; 1646 1647 /* emc */ 1648 clk = clk_register_mux(NULL, "emc_mux", mux_pllmcp_clkm, 1649 ARRAY_SIZE(mux_pllmcp_clkm), 0, 1650 clk_base + CLK_SOURCE_EMC, 1651 30, 2, 0, NULL); 1652 clk = tegra_clk_register_periph_gate("emc", "emc_mux", 0, clk_base, 0, 1653 57, &periph_h_regs, periph_clk_enb_refcnt); 1654 clk_register_clkdev(clk, "emc", NULL); 1655 clks[emc] = clk; 1656 1657 /* i2c1-fast */ 1658 clk = clk_register_fixed_factor(NULL, "i2c1-fast", "pll_p_out3", 1659 CLK_SET_RATE_PARENT, 1, 1); 1660 clk_register_clkdev(clk, "fast-clk", "tegra-i2c.0"); 1661 1662 /* i2c2-fast */ 1663 clk = clk_register_fixed_factor(NULL, "i2c2-fast", "pll_p_out3", 1664 CLK_SET_RATE_PARENT, 1, 1); 1665 clk_register_clkdev(clk, "fast-clk", "tegra-i2c.1"); 1666 1667 /* i2c3-fast */ 1668 clk = clk_register_fixed_factor(NULL, "i2c3-fast", "pll_p_out3", 1669 CLK_SET_RATE_PARENT, 1, 1); 1670 clk_register_clkdev(clk, "fast-clk", "tegra-i2c.2"); 1671 1672 /* i2c4-fast */ 1673 clk = clk_register_fixed_factor(NULL, "i2c4-fast", "pll_p_out3", 1674 CLK_SET_RATE_PARENT, 1, 1); 1675 clk_register_clkdev(clk, "fast-clk", "tegra-i2c.3"); 1676 1677 /* i2c5-fast */ 1678 clk = clk_register_fixed_factor(NULL, "i2c5-fast", "pll_p_out3", 1679 CLK_SET_RATE_PARENT, 1, 1); 1680 clk_register_clkdev(clk, "fast-clk", "tegra-i2c.5"); 1681 1682 /* dsi1-fixed */ 1683 clk = clk_register_fixed_factor(NULL, "dsi1-fixed", "pll_p_out3", 1684 CLK_SET_RATE_PARENT, 1, 1); 1685 clk_register_clkdev(clk, "dsi-fixed", "tegradc.0"); 1686 1687 /* dsi2-fixed */ 1688 clk = clk_register_fixed_factor(NULL, "dsi2-fixed", "pll_p_out3", 1689 CLK_SET_RATE_PARENT, 1, 1); 1690 clk_register_clkdev(clk, "dsi-fixed", "tegradc.1"); 1691 1692 for (i = 0; i < ARRAY_SIZE(tegra_periph_clk_list); i++) { 1693 data = &tegra_periph_clk_list[i]; 1694 clk = tegra_clk_register_periph(data->name, data->parent_names, 1695 data->num_parents, &data->periph, 1696 clk_base, data->offset); 1697 clk_register_clkdev(clk, data->con_id, data->dev_id); 1698 clks[data->clk_id] = clk; 1699 } 1700 1701 for (i = 0; i < ARRAY_SIZE(tegra_periph_nodiv_clk_list); i++) { 1702 data = &tegra_periph_nodiv_clk_list[i]; 1703 clk = tegra_clk_register_periph_nodiv(data->name, 1704 data->parent_names, 1705 data->num_parents, &data->periph, 1706 clk_base, data->offset); 1707 clk_register_clkdev(clk, data->con_id, data->dev_id); 1708 clks[data->clk_id] = clk; 1709 } 1710} 1711 1712static void __init tegra30_fixed_clk_init(void) 1713{ 1714 struct clk *clk; 1715 1716 /* clk_32k */ 1717 clk = clk_register_fixed_rate(NULL, "clk_32k", NULL, CLK_IS_ROOT, 1718 32768); 1719 clk_register_clkdev(clk, "clk_32k", NULL); 1720 clks[clk_32k] = clk; 1721 1722 /* clk_m_div2 */ 1723 clk = clk_register_fixed_factor(NULL, "clk_m_div2", "clk_m", 1724 CLK_SET_RATE_PARENT, 1, 2); 1725 clk_register_clkdev(clk, "clk_m_div2", NULL); 1726 clks[clk_m_div2] = clk; 1727 1728 /* clk_m_div4 */ 1729 clk = clk_register_fixed_factor(NULL, "clk_m_div4", "clk_m", 1730 CLK_SET_RATE_PARENT, 1, 4); 1731 clk_register_clkdev(clk, "clk_m_div4", NULL); 1732 clks[clk_m_div4] = clk; 1733 1734 /* cml0 */ 1735 clk = clk_register_gate(NULL, "cml0", "pll_e", 0, clk_base + PLLE_AUX, 1736 0, 0, &cml_lock); 1737 clk_register_clkdev(clk, "cml0", NULL); 1738 clks[cml0] = clk; 1739 1740 /* cml1 */ 1741 clk = clk_register_gate(NULL, "cml1", "pll_e", 0, clk_base + PLLE_AUX, 1742 1, 0, &cml_lock); 1743 clk_register_clkdev(clk, "cml1", NULL); 1744 clks[cml1] = clk; 1745 1746 /* pciex */ 1747 clk = clk_register_fixed_rate(NULL, "pciex", "pll_e", 0, 100000000); 1748 clk_register_clkdev(clk, "pciex", NULL); 1749 clks[pciex] = clk; 1750} 1751 1752static void __init tegra30_osc_clk_init(void) 1753{ 1754 struct clk *clk; 1755 unsigned int pll_ref_div; 1756 1757 tegra30_clk_measure_input_freq(); 1758 1759 /* clk_m */ 1760 clk = clk_register_fixed_rate(NULL, "clk_m", NULL, CLK_IS_ROOT, 1761 input_freq); 1762 clk_register_clkdev(clk, "clk_m", NULL); 1763 clks[clk_m] = clk; 1764 1765 /* pll_ref */ 1766 pll_ref_div = tegra30_get_pll_ref_div(); 1767 clk = clk_register_fixed_factor(NULL, "pll_ref", "clk_m", 1768 CLK_SET_RATE_PARENT, 1, pll_ref_div); 1769 clk_register_clkdev(clk, "pll_ref", NULL); 1770 clks[pll_ref] = clk; 1771} 1772 1773/* Tegra30 CPU clock and reset control functions */ 1774static void tegra30_wait_cpu_in_reset(u32 cpu) 1775{ 1776 unsigned int reg; 1777 1778 do { 1779 reg = readl(clk_base + 1780 TEGRA30_CLK_RST_CONTROLLER_CPU_CMPLX_STATUS); 1781 cpu_relax(); 1782 } while (!(reg & (1 << cpu))); /* check CPU been reset or not */ 1783 1784 return; 1785} 1786 1787static void tegra30_put_cpu_in_reset(u32 cpu) 1788{ 1789 writel(CPU_RESET(cpu), 1790 clk_base + TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET); 1791 dmb(); 1792} 1793 1794static void tegra30_cpu_out_of_reset(u32 cpu) 1795{ 1796 writel(CPU_RESET(cpu), 1797 clk_base + TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR); 1798 wmb(); 1799} 1800 1801 1802static void tegra30_enable_cpu_clock(u32 cpu) 1803{ 1804 unsigned int reg; 1805 1806 writel(CPU_CLOCK(cpu), 1807 clk_base + TEGRA30_CLK_RST_CONTROLLER_CLK_CPU_CMPLX_CLR); 1808 reg = readl(clk_base + 1809 TEGRA30_CLK_RST_CONTROLLER_CLK_CPU_CMPLX_CLR); 1810} 1811 1812static void tegra30_disable_cpu_clock(u32 cpu) 1813{ 1814 1815 unsigned int reg; 1816 1817 reg = readl(clk_base + TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX); 1818 writel(reg | CPU_CLOCK(cpu), 1819 clk_base + TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX); 1820} 1821 1822#ifdef CONFIG_PM_SLEEP 1823static bool tegra30_cpu_rail_off_ready(void) 1824{ 1825 unsigned int cpu_rst_status; 1826 int cpu_pwr_status; 1827 1828 cpu_rst_status = readl(clk_base + 1829 TEGRA30_CLK_RST_CONTROLLER_CPU_CMPLX_STATUS); 1830 cpu_pwr_status = tegra_powergate_is_powered(TEGRA_POWERGATE_CPU1) || 1831 tegra_powergate_is_powered(TEGRA_POWERGATE_CPU2) || 1832 tegra_powergate_is_powered(TEGRA_POWERGATE_CPU3); 1833 1834 if (((cpu_rst_status & 0xE) != 0xE) || cpu_pwr_status) 1835 return false; 1836 1837 return true; 1838} 1839 1840static void tegra30_cpu_clock_suspend(void) 1841{ 1842 /* switch coresite to clk_m, save off original source */ 1843 tegra30_cpu_clk_sctx.clk_csite_src = 1844 readl(clk_base + CLK_RESET_SOURCE_CSITE); 1845 writel(3<<30, clk_base + CLK_RESET_SOURCE_CSITE); 1846 1847 tegra30_cpu_clk_sctx.cpu_burst = 1848 readl(clk_base + CLK_RESET_CCLK_BURST); 1849 tegra30_cpu_clk_sctx.pllx_base = 1850 readl(clk_base + CLK_RESET_PLLX_BASE); 1851 tegra30_cpu_clk_sctx.pllx_misc = 1852 readl(clk_base + CLK_RESET_PLLX_MISC); 1853 tegra30_cpu_clk_sctx.cclk_divider = 1854 readl(clk_base + CLK_RESET_CCLK_DIVIDER); 1855} 1856 1857static void tegra30_cpu_clock_resume(void) 1858{ 1859 unsigned int reg, policy; 1860 1861 /* Is CPU complex already running on PLLX? */ 1862 reg = readl(clk_base + CLK_RESET_CCLK_BURST); 1863 policy = (reg >> CLK_RESET_CCLK_BURST_POLICY_SHIFT) & 0xF; 1864 1865 if (policy == CLK_RESET_CCLK_IDLE_POLICY) 1866 reg = (reg >> CLK_RESET_CCLK_IDLE_POLICY_SHIFT) & 0xF; 1867 else if (policy == CLK_RESET_CCLK_RUN_POLICY) 1868 reg = (reg >> CLK_RESET_CCLK_RUN_POLICY_SHIFT) & 0xF; 1869 else 1870 BUG(); 1871 1872 if (reg != CLK_RESET_CCLK_BURST_POLICY_PLLX) { 1873 /* restore PLLX settings if CPU is on different PLL */ 1874 writel(tegra30_cpu_clk_sctx.pllx_misc, 1875 clk_base + CLK_RESET_PLLX_MISC); 1876 writel(tegra30_cpu_clk_sctx.pllx_base, 1877 clk_base + CLK_RESET_PLLX_BASE); 1878 1879 /* wait for PLL stabilization if PLLX was enabled */ 1880 if (tegra30_cpu_clk_sctx.pllx_base & (1 << 30)) 1881 udelay(300); 1882 } 1883 1884 /* 1885 * Restore original burst policy setting for calls resulting from CPU 1886 * LP2 in idle or system suspend. 1887 */ 1888 writel(tegra30_cpu_clk_sctx.cclk_divider, 1889 clk_base + CLK_RESET_CCLK_DIVIDER); 1890 writel(tegra30_cpu_clk_sctx.cpu_burst, 1891 clk_base + CLK_RESET_CCLK_BURST); 1892 1893 writel(tegra30_cpu_clk_sctx.clk_csite_src, 1894 clk_base + CLK_RESET_SOURCE_CSITE); 1895} 1896#endif 1897 1898static struct tegra_cpu_car_ops tegra30_cpu_car_ops = { 1899 .wait_for_reset = tegra30_wait_cpu_in_reset, 1900 .put_in_reset = tegra30_put_cpu_in_reset, 1901 .out_of_reset = tegra30_cpu_out_of_reset, 1902 .enable_clock = tegra30_enable_cpu_clock, 1903 .disable_clock = tegra30_disable_cpu_clock, 1904#ifdef CONFIG_PM_SLEEP 1905 .rail_off_ready = tegra30_cpu_rail_off_ready, 1906 .suspend = tegra30_cpu_clock_suspend, 1907 .resume = tegra30_cpu_clock_resume, 1908#endif 1909}; 1910 1911static __initdata struct tegra_clk_init_table init_table[] = { 1912 {uarta, pll_p, 408000000, 1}, 1913 {pll_a, clk_max, 564480000, 1}, 1914 {pll_a_out0, clk_max, 11289600, 1}, 1915 {extern1, pll_a_out0, 0, 1}, 1916 {clk_out_1_mux, extern1, 0, 0}, 1917 {clk_out_1, clk_max, 0, 1}, 1918 {blink, clk_max, 0, 1}, 1919 {i2s0, pll_a_out0, 11289600, 0}, 1920 {i2s1, pll_a_out0, 11289600, 0}, 1921 {i2s2, pll_a_out0, 11289600, 0}, 1922 {i2s3, pll_a_out0, 11289600, 0}, 1923 {i2s4, pll_a_out0, 11289600, 0}, 1924 {sdmmc1, pll_p, 48000000, 0}, 1925 {sdmmc2, pll_p, 48000000, 0}, 1926 {sdmmc3, pll_p, 48000000, 0}, 1927 {pll_m, clk_max, 0, 1}, 1928 {pclk, clk_max, 0, 1}, 1929 {csite, clk_max, 0, 1}, 1930 {emc, clk_max, 0, 1}, 1931 {mselect, clk_max, 0, 1}, 1932 {sbc1, pll_p, 100000000, 0}, 1933 {sbc2, pll_p, 100000000, 0}, 1934 {sbc3, pll_p, 100000000, 0}, 1935 {sbc4, pll_p, 100000000, 0}, 1936 {sbc5, pll_p, 100000000, 0}, 1937 {sbc6, pll_p, 100000000, 0}, 1938 {host1x, pll_c, 150000000, 0}, 1939 {disp1, pll_p, 600000000, 0}, 1940 {disp2, pll_p, 600000000, 0}, 1941 {twd, clk_max, 0, 1}, 1942 {clk_max, clk_max, 0, 0}, /* This MUST be the last entry. */ 1943}; 1944 1945/* 1946 * Some clocks may be used by different drivers depending on the board 1947 * configuration. List those here to register them twice in the clock lookup 1948 * table under two names. 1949 */ 1950static struct tegra_clk_duplicate tegra_clk_duplicates[] = { 1951 TEGRA_CLK_DUPLICATE(uarta, "serial8250.0", NULL), 1952 TEGRA_CLK_DUPLICATE(uartb, "serial8250.1", NULL), 1953 TEGRA_CLK_DUPLICATE(uartc, "serial8250.2", NULL), 1954 TEGRA_CLK_DUPLICATE(uartd, "serial8250.3", NULL), 1955 TEGRA_CLK_DUPLICATE(uarte, "serial8250.4", NULL), 1956 TEGRA_CLK_DUPLICATE(usbd, "utmip-pad", NULL), 1957 TEGRA_CLK_DUPLICATE(usbd, "tegra-ehci.0", NULL), 1958 TEGRA_CLK_DUPLICATE(usbd, "tegra-otg", NULL), 1959 TEGRA_CLK_DUPLICATE(pll_p, "tegradc.0", "parent"), 1960 TEGRA_CLK_DUPLICATE(pll_p, "tegradc.1", "parent"), 1961 TEGRA_CLK_DUPLICATE(pll_d2_out0, "hdmi", "parent"), 1962 TEGRA_CLK_DUPLICATE(dsib, "tegradc.0", "dsib"), 1963 TEGRA_CLK_DUPLICATE(dsia, "tegradc.1", "dsia"), 1964 TEGRA_CLK_DUPLICATE(bsev, "tegra-avp", "bsev"), 1965 TEGRA_CLK_DUPLICATE(bsev, "nvavp", "bsev"), 1966 TEGRA_CLK_DUPLICATE(vde, "tegra-aes", "vde"), 1967 TEGRA_CLK_DUPLICATE(bsea, "tegra-aes", "bsea"), 1968 TEGRA_CLK_DUPLICATE(bsea, "nvavp", "bsea"), 1969 TEGRA_CLK_DUPLICATE(cml1, "tegra_sata_cml", NULL), 1970 TEGRA_CLK_DUPLICATE(cml0, "tegra_pcie", "cml"), 1971 TEGRA_CLK_DUPLICATE(pciex, "tegra_pcie", "pciex"), 1972 TEGRA_CLK_DUPLICATE(i2c1, "tegra-i2c-slave.0", NULL), 1973 TEGRA_CLK_DUPLICATE(i2c2, "tegra-i2c-slave.1", NULL), 1974 TEGRA_CLK_DUPLICATE(i2c3, "tegra-i2c-slave.2", NULL), 1975 TEGRA_CLK_DUPLICATE(i2c4, "tegra-i2c-slave.3", NULL), 1976 TEGRA_CLK_DUPLICATE(i2c5, "tegra-i2c-slave.4", NULL), 1977 TEGRA_CLK_DUPLICATE(sbc1, "spi_slave_tegra.0", NULL), 1978 TEGRA_CLK_DUPLICATE(sbc2, "spi_slave_tegra.1", NULL), 1979 TEGRA_CLK_DUPLICATE(sbc3, "spi_slave_tegra.2", NULL), 1980 TEGRA_CLK_DUPLICATE(sbc4, "spi_slave_tegra.3", NULL), 1981 TEGRA_CLK_DUPLICATE(sbc5, "spi_slave_tegra.4", NULL), 1982 TEGRA_CLK_DUPLICATE(sbc6, "spi_slave_tegra.5", NULL), 1983 TEGRA_CLK_DUPLICATE(twd, "smp_twd", NULL), 1984 TEGRA_CLK_DUPLICATE(vcp, "nvavp", "vcp"), 1985 TEGRA_CLK_DUPLICATE(i2s0, NULL, "i2s0"), 1986 TEGRA_CLK_DUPLICATE(i2s1, NULL, "i2s1"), 1987 TEGRA_CLK_DUPLICATE(i2s2, NULL, "i2s2"), 1988 TEGRA_CLK_DUPLICATE(i2s3, NULL, "i2s3"), 1989 TEGRA_CLK_DUPLICATE(i2s4, NULL, "i2s4"), 1990 TEGRA_CLK_DUPLICATE(dam0, NULL, "dam0"), 1991 TEGRA_CLK_DUPLICATE(dam1, NULL, "dam1"), 1992 TEGRA_CLK_DUPLICATE(dam2, NULL, "dam2"), 1993 TEGRA_CLK_DUPLICATE(spdif_in, NULL, "spdif_in"), 1994 TEGRA_CLK_DUPLICATE(pll_p_out3, "tegra-i2c.0", "fast-clk"), 1995 TEGRA_CLK_DUPLICATE(pll_p_out3, "tegra-i2c.1", "fast-clk"), 1996 TEGRA_CLK_DUPLICATE(pll_p_out3, "tegra-i2c.2", "fast-clk"), 1997 TEGRA_CLK_DUPLICATE(pll_p_out3, "tegra-i2c.3", "fast-clk"), 1998 TEGRA_CLK_DUPLICATE(pll_p_out3, "tegra-i2c.4", "fast-clk"), 1999 TEGRA_CLK_DUPLICATE(clk_max, NULL, NULL), /* MUST be the last entry */ 2000}; 2001 2002static const struct of_device_id pmc_match[] __initconst = { 2003 { .compatible = "nvidia,tegra30-pmc" }, 2004 {}, 2005}; 2006 2007void __init tegra30_clock_init(struct device_node *np) 2008{ 2009 struct device_node *node; 2010 int i; 2011 2012 clk_base = of_iomap(np, 0); 2013 if (!clk_base) { 2014 pr_err("ioremap tegra30 CAR failed\n"); 2015 return; 2016 } 2017 2018 node = of_find_matching_node(NULL, pmc_match); 2019 if (!node) { 2020 pr_err("Failed to find pmc node\n"); 2021 BUG(); 2022 } 2023 2024 pmc_base = of_iomap(node, 0); 2025 if (!pmc_base) { 2026 pr_err("Can't map pmc registers\n"); 2027 BUG(); 2028 } 2029 2030 tegra30_osc_clk_init(); 2031 tegra30_fixed_clk_init(); 2032 tegra30_pll_init(); 2033 tegra30_super_clk_init(); 2034 tegra30_periph_clk_init(); 2035 tegra30_audio_clk_init(); 2036 tegra30_pmc_clk_init(); 2037 2038 for (i = 0; i < ARRAY_SIZE(clks); i++) { 2039 if (IS_ERR(clks[i])) { 2040 pr_err("Tegra30 clk %d: register failed with %ld\n", 2041 i, PTR_ERR(clks[i])); 2042 BUG(); 2043 } 2044 if (!clks[i]) 2045 clks[i] = ERR_PTR(-EINVAL); 2046 } 2047 2048 tegra_init_dup_clks(tegra_clk_duplicates, clks, clk_max); 2049 2050 clk_data.clks = clks; 2051 clk_data.clk_num = ARRAY_SIZE(clks); 2052 of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data); 2053 2054 tegra_init_from_table(init_table, clks, clk_max); 2055 2056 tegra_cpu_car_ops = &tegra30_cpu_car_ops; 2057} 2058