clk-tegra30.c revision c09e32bb67a9fba318ae4387eaabba21e0d07a87
1/* 2 * Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved. 3 * 4 * This program is free software; you can redistribute it and/or modify it 5 * under the terms and conditions of the GNU General Public License, 6 * version 2, as published by the Free Software Foundation. 7 * 8 * This program is distributed in the hope it will be useful, but WITHOUT 9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 11 * more details. 12 * 13 * You should have received a copy of the GNU General Public License 14 * along with this program. If not, see <http://www.gnu.org/licenses/>. 15 */ 16 17#include <linux/io.h> 18#include <linux/delay.h> 19#include <linux/clk.h> 20#include <linux/clk-provider.h> 21#include <linux/clkdev.h> 22#include <linux/of.h> 23#include <linux/of_address.h> 24#include <linux/clk/tegra.h> 25#include <linux/tegra-powergate.h> 26 27#include "clk.h" 28 29#define RST_DEVICES_L 0x004 30#define RST_DEVICES_H 0x008 31#define RST_DEVICES_U 0x00c 32#define RST_DEVICES_V 0x358 33#define RST_DEVICES_W 0x35c 34#define RST_DEVICES_SET_L 0x300 35#define RST_DEVICES_CLR_L 0x304 36#define RST_DEVICES_SET_H 0x308 37#define RST_DEVICES_CLR_H 0x30c 38#define RST_DEVICES_SET_U 0x310 39#define RST_DEVICES_CLR_U 0x314 40#define RST_DEVICES_SET_V 0x430 41#define RST_DEVICES_CLR_V 0x434 42#define RST_DEVICES_SET_W 0x438 43#define RST_DEVICES_CLR_W 0x43c 44#define RST_DEVICES_NUM 5 45 46#define CLK_OUT_ENB_L 0x010 47#define CLK_OUT_ENB_H 0x014 48#define CLK_OUT_ENB_U 0x018 49#define CLK_OUT_ENB_V 0x360 50#define CLK_OUT_ENB_W 0x364 51#define CLK_OUT_ENB_SET_L 0x320 52#define CLK_OUT_ENB_CLR_L 0x324 53#define CLK_OUT_ENB_SET_H 0x328 54#define CLK_OUT_ENB_CLR_H 0x32c 55#define CLK_OUT_ENB_SET_U 0x330 56#define CLK_OUT_ENB_CLR_U 0x334 57#define CLK_OUT_ENB_SET_V 0x440 58#define CLK_OUT_ENB_CLR_V 0x444 59#define CLK_OUT_ENB_SET_W 0x448 60#define CLK_OUT_ENB_CLR_W 0x44c 61#define CLK_OUT_ENB_NUM 5 62 63#define OSC_CTRL 0x50 64#define OSC_CTRL_OSC_FREQ_MASK (0xF<<28) 65#define OSC_CTRL_OSC_FREQ_13MHZ (0X0<<28) 66#define OSC_CTRL_OSC_FREQ_19_2MHZ (0X4<<28) 67#define OSC_CTRL_OSC_FREQ_12MHZ (0X8<<28) 68#define OSC_CTRL_OSC_FREQ_26MHZ (0XC<<28) 69#define OSC_CTRL_OSC_FREQ_16_8MHZ (0X1<<28) 70#define OSC_CTRL_OSC_FREQ_38_4MHZ (0X5<<28) 71#define OSC_CTRL_OSC_FREQ_48MHZ (0X9<<28) 72#define OSC_CTRL_MASK (0x3f2 | OSC_CTRL_OSC_FREQ_MASK) 73 74#define OSC_CTRL_PLL_REF_DIV_MASK (3<<26) 75#define OSC_CTRL_PLL_REF_DIV_1 (0<<26) 76#define OSC_CTRL_PLL_REF_DIV_2 (1<<26) 77#define OSC_CTRL_PLL_REF_DIV_4 (2<<26) 78 79#define OSC_FREQ_DET 0x58 80#define OSC_FREQ_DET_TRIG BIT(31) 81 82#define OSC_FREQ_DET_STATUS 0x5c 83#define OSC_FREQ_DET_BUSY BIT(31) 84#define OSC_FREQ_DET_CNT_MASK 0xffff 85 86#define CCLKG_BURST_POLICY 0x368 87#define SUPER_CCLKG_DIVIDER 0x36c 88#define CCLKLP_BURST_POLICY 0x370 89#define SUPER_CCLKLP_DIVIDER 0x374 90#define SCLK_BURST_POLICY 0x028 91#define SUPER_SCLK_DIVIDER 0x02c 92 93#define SYSTEM_CLK_RATE 0x030 94 95#define PLLC_BASE 0x80 96#define PLLC_MISC 0x8c 97#define PLLM_BASE 0x90 98#define PLLM_MISC 0x9c 99#define PLLP_BASE 0xa0 100#define PLLP_MISC 0xac 101#define PLLX_BASE 0xe0 102#define PLLX_MISC 0xe4 103#define PLLD_BASE 0xd0 104#define PLLD_MISC 0xdc 105#define PLLD2_BASE 0x4b8 106#define PLLD2_MISC 0x4bc 107#define PLLE_BASE 0xe8 108#define PLLE_MISC 0xec 109#define PLLA_BASE 0xb0 110#define PLLA_MISC 0xbc 111#define PLLU_BASE 0xc0 112#define PLLU_MISC 0xcc 113 114#define PLL_MISC_LOCK_ENABLE 18 115#define PLLDU_MISC_LOCK_ENABLE 22 116#define PLLE_MISC_LOCK_ENABLE 9 117 118#define PLL_BASE_LOCK BIT(27) 119#define PLLE_MISC_LOCK BIT(11) 120 121#define PLLE_AUX 0x48c 122#define PLLC_OUT 0x84 123#define PLLM_OUT 0x94 124#define PLLP_OUTA 0xa4 125#define PLLP_OUTB 0xa8 126#define PLLA_OUT 0xb4 127 128#define AUDIO_SYNC_CLK_I2S0 0x4a0 129#define AUDIO_SYNC_CLK_I2S1 0x4a4 130#define AUDIO_SYNC_CLK_I2S2 0x4a8 131#define AUDIO_SYNC_CLK_I2S3 0x4ac 132#define AUDIO_SYNC_CLK_I2S4 0x4b0 133#define AUDIO_SYNC_CLK_SPDIF 0x4b4 134 135#define PMC_CLK_OUT_CNTRL 0x1a8 136 137#define CLK_SOURCE_I2S0 0x1d8 138#define CLK_SOURCE_I2S1 0x100 139#define CLK_SOURCE_I2S2 0x104 140#define CLK_SOURCE_I2S3 0x3bc 141#define CLK_SOURCE_I2S4 0x3c0 142#define CLK_SOURCE_SPDIF_OUT 0x108 143#define CLK_SOURCE_SPDIF_IN 0x10c 144#define CLK_SOURCE_PWM 0x110 145#define CLK_SOURCE_D_AUDIO 0x3d0 146#define CLK_SOURCE_DAM0 0x3d8 147#define CLK_SOURCE_DAM1 0x3dc 148#define CLK_SOURCE_DAM2 0x3e0 149#define CLK_SOURCE_HDA 0x428 150#define CLK_SOURCE_HDA2CODEC_2X 0x3e4 151#define CLK_SOURCE_SBC1 0x134 152#define CLK_SOURCE_SBC2 0x118 153#define CLK_SOURCE_SBC3 0x11c 154#define CLK_SOURCE_SBC4 0x1b4 155#define CLK_SOURCE_SBC5 0x3c8 156#define CLK_SOURCE_SBC6 0x3cc 157#define CLK_SOURCE_SATA_OOB 0x420 158#define CLK_SOURCE_SATA 0x424 159#define CLK_SOURCE_NDFLASH 0x160 160#define CLK_SOURCE_NDSPEED 0x3f8 161#define CLK_SOURCE_VFIR 0x168 162#define CLK_SOURCE_SDMMC1 0x150 163#define CLK_SOURCE_SDMMC2 0x154 164#define CLK_SOURCE_SDMMC3 0x1bc 165#define CLK_SOURCE_SDMMC4 0x164 166#define CLK_SOURCE_VDE 0x1c8 167#define CLK_SOURCE_CSITE 0x1d4 168#define CLK_SOURCE_LA 0x1f8 169#define CLK_SOURCE_OWR 0x1cc 170#define CLK_SOURCE_NOR 0x1d0 171#define CLK_SOURCE_MIPI 0x174 172#define CLK_SOURCE_I2C1 0x124 173#define CLK_SOURCE_I2C2 0x198 174#define CLK_SOURCE_I2C3 0x1b8 175#define CLK_SOURCE_I2C4 0x3c4 176#define CLK_SOURCE_I2C5 0x128 177#define CLK_SOURCE_UARTA 0x178 178#define CLK_SOURCE_UARTB 0x17c 179#define CLK_SOURCE_UARTC 0x1a0 180#define CLK_SOURCE_UARTD 0x1c0 181#define CLK_SOURCE_UARTE 0x1c4 182#define CLK_SOURCE_VI 0x148 183#define CLK_SOURCE_VI_SENSOR 0x1a8 184#define CLK_SOURCE_3D 0x158 185#define CLK_SOURCE_3D2 0x3b0 186#define CLK_SOURCE_2D 0x15c 187#define CLK_SOURCE_EPP 0x16c 188#define CLK_SOURCE_MPE 0x170 189#define CLK_SOURCE_HOST1X 0x180 190#define CLK_SOURCE_CVE 0x140 191#define CLK_SOURCE_TVO 0x188 192#define CLK_SOURCE_DTV 0x1dc 193#define CLK_SOURCE_HDMI 0x18c 194#define CLK_SOURCE_TVDAC 0x194 195#define CLK_SOURCE_DISP1 0x138 196#define CLK_SOURCE_DISP2 0x13c 197#define CLK_SOURCE_DSIB 0xd0 198#define CLK_SOURCE_TSENSOR 0x3b8 199#define CLK_SOURCE_ACTMON 0x3e8 200#define CLK_SOURCE_EXTERN1 0x3ec 201#define CLK_SOURCE_EXTERN2 0x3f0 202#define CLK_SOURCE_EXTERN3 0x3f4 203#define CLK_SOURCE_I2CSLOW 0x3fc 204#define CLK_SOURCE_SE 0x42c 205#define CLK_SOURCE_MSELECT 0x3b4 206#define CLK_SOURCE_EMC 0x19c 207 208#define AUDIO_SYNC_DOUBLER 0x49c 209 210#define PMC_CTRL 0 211#define PMC_CTRL_BLINK_ENB 7 212 213#define PMC_DPD_PADS_ORIDE 0x1c 214#define PMC_DPD_PADS_ORIDE_BLINK_ENB 20 215#define PMC_BLINK_TIMER 0x40 216 217#define UTMIP_PLL_CFG2 0x488 218#define UTMIP_PLL_CFG2_STABLE_COUNT(x) (((x) & 0xffff) << 6) 219#define UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(x) (((x) & 0x3f) << 18) 220#define UTMIP_PLL_CFG2_FORCE_PD_SAMP_A_POWERDOWN BIT(0) 221#define UTMIP_PLL_CFG2_FORCE_PD_SAMP_B_POWERDOWN BIT(2) 222#define UTMIP_PLL_CFG2_FORCE_PD_SAMP_C_POWERDOWN BIT(4) 223 224#define UTMIP_PLL_CFG1 0x484 225#define UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(x) (((x) & 0x1f) << 6) 226#define UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(x) (((x) & 0xfff) << 0) 227#define UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN BIT(14) 228#define UTMIP_PLL_CFG1_FORCE_PLL_ACTIVE_POWERDOWN BIT(12) 229#define UTMIP_PLL_CFG1_FORCE_PLLU_POWERDOWN BIT(16) 230 231/* Tegra CPU clock and reset control regs */ 232#define TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX 0x4c 233#define TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET 0x340 234#define TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR 0x344 235#define TEGRA30_CLK_RST_CONTROLLER_CLK_CPU_CMPLX_CLR 0x34c 236#define TEGRA30_CLK_RST_CONTROLLER_CPU_CMPLX_STATUS 0x470 237 238#define CPU_CLOCK(cpu) (0x1 << (8 + cpu)) 239#define CPU_RESET(cpu) (0x1111ul << (cpu)) 240 241#define CLK_RESET_CCLK_BURST 0x20 242#define CLK_RESET_CCLK_DIVIDER 0x24 243#define CLK_RESET_PLLX_BASE 0xe0 244#define CLK_RESET_PLLX_MISC 0xe4 245 246#define CLK_RESET_SOURCE_CSITE 0x1d4 247 248#define CLK_RESET_CCLK_BURST_POLICY_SHIFT 28 249#define CLK_RESET_CCLK_RUN_POLICY_SHIFT 4 250#define CLK_RESET_CCLK_IDLE_POLICY_SHIFT 0 251#define CLK_RESET_CCLK_IDLE_POLICY 1 252#define CLK_RESET_CCLK_RUN_POLICY 2 253#define CLK_RESET_CCLK_BURST_POLICY_PLLX 8 254 255/* PLLM override registers */ 256#define PMC_PLLM_WB0_OVERRIDE 0x1dc 257 258#ifdef CONFIG_PM_SLEEP 259static struct cpu_clk_suspend_context { 260 u32 pllx_misc; 261 u32 pllx_base; 262 263 u32 cpu_burst; 264 u32 clk_csite_src; 265 u32 cclk_divider; 266} tegra30_cpu_clk_sctx; 267#endif 268 269static int periph_clk_enb_refcnt[CLK_OUT_ENB_NUM * 32]; 270 271static void __iomem *clk_base; 272static void __iomem *pmc_base; 273static unsigned long input_freq; 274 275static DEFINE_SPINLOCK(clk_doubler_lock); 276static DEFINE_SPINLOCK(clk_out_lock); 277static DEFINE_SPINLOCK(pll_div_lock); 278static DEFINE_SPINLOCK(cml_lock); 279static DEFINE_SPINLOCK(pll_d_lock); 280static DEFINE_SPINLOCK(sysrate_lock); 281 282#define TEGRA_INIT_DATA_MUX(_name, _con_id, _dev_id, _parents, _offset, \ 283 _clk_num, _regs, _gate_flags, _clk_id) \ 284 TEGRA_INIT_DATA(_name, _con_id, _dev_id, _parents, _offset, \ 285 30, 2, 0, 0, 8, 1, 0, _regs, _clk_num, \ 286 periph_clk_enb_refcnt, _gate_flags, _clk_id) 287 288#define TEGRA_INIT_DATA_DIV16(_name, _con_id, _dev_id, _parents, _offset, \ 289 _clk_num, _regs, _gate_flags, _clk_id) \ 290 TEGRA_INIT_DATA(_name, _con_id, _dev_id, _parents, _offset, \ 291 30, 2, 0, 0, 16, 0, TEGRA_DIVIDER_ROUND_UP, \ 292 _regs, _clk_num, periph_clk_enb_refcnt, \ 293 _gate_flags, _clk_id) 294 295#define TEGRA_INIT_DATA_MUX8(_name, _con_id, _dev_id, _parents, _offset, \ 296 _clk_num, _regs, _gate_flags, _clk_id) \ 297 TEGRA_INIT_DATA(_name, _con_id, _dev_id, _parents, _offset, \ 298 29, 3, 0, 0, 8, 1, 0, _regs, _clk_num, \ 299 periph_clk_enb_refcnt, _gate_flags, _clk_id) 300 301#define TEGRA_INIT_DATA_INT(_name, _con_id, _dev_id, _parents, _offset, \ 302 _clk_num, _regs, _gate_flags, _clk_id) \ 303 TEGRA_INIT_DATA(_name, _con_id, _dev_id, _parents, _offset, \ 304 30, 2, 0, 0, 8, 1, TEGRA_DIVIDER_INT, _regs, \ 305 _clk_num, periph_clk_enb_refcnt, _gate_flags, \ 306 _clk_id) 307 308#define TEGRA_INIT_DATA_UART(_name, _con_id, _dev_id, _parents, _offset,\ 309 _clk_num, _regs, _clk_id) \ 310 TEGRA_INIT_DATA(_name, _con_id, _dev_id, _parents, _offset, \ 311 30, 2, 0, 0, 16, 1, TEGRA_DIVIDER_UART, _regs, \ 312 _clk_num, periph_clk_enb_refcnt, 0, _clk_id) 313 314#define TEGRA_INIT_DATA_NODIV(_name, _con_id, _dev_id, _parents, _offset, \ 315 _mux_shift, _mux_width, _clk_num, _regs, \ 316 _gate_flags, _clk_id) \ 317 TEGRA_INIT_DATA(_name, _con_id, _dev_id, _parents, _offset, \ 318 _mux_shift, _mux_width, 0, 0, 0, 0, 0, _regs, \ 319 _clk_num, periph_clk_enb_refcnt, _gate_flags, \ 320 _clk_id) 321 322/* 323 * IDs assigned here must be in sync with DT bindings definition 324 * for Tegra30 clocks. 325 */ 326enum tegra30_clk { 327 cpu, rtc = 4, timer, uarta, gpio = 8, sdmmc2, i2s1 = 11, i2c1, ndflash, 328 sdmmc1, sdmmc4, pwm = 17, i2s2, epp, gr2d = 21, usbd, isp, gr3d, 329 disp2 = 26, disp1, host1x, vcp, i2s0, cop_cache, mc, ahbdma, apbdma, 330 kbc = 36, statmon, pmc, kfuse = 40, sbc1, nor, sbc2 = 44, sbc3 = 46, 331 i2c5, dsia, mipi = 50, hdmi, csi, tvdac, i2c2, uartc, emc = 57, usb2, 332 usb3, mpe, vde, bsea, bsev, speedo, uartd, uarte, i2c3, sbc4, sdmmc3, 333 pcie, owr, afi, csite, pciex, avpucq, la, dtv = 79, ndspeed, i2cslow, 334 dsib, irama = 84, iramb, iramc, iramd, cram2, audio_2x = 90, csus = 92, 335 cdev2, cdev1, cpu_g = 96, cpu_lp, gr3d2, mselect, tsensor, i2s3, i2s4, 336 i2c4, sbc5, sbc6, d_audio, apbif, dam0, dam1, dam2, hda2codec_2x, 337 atomics, audio0_2x, audio1_2x, audio2_2x, audio3_2x, audio4_2x, 338 spdif_2x, actmon, extern1, extern2, extern3, sata_oob, sata, hda, 339 se = 127, hda2hdmi, sata_cold, uartb = 160, vfir, spdif_in, spdif_out, 340 vi, vi_sensor, fuse, fuse_burn, cve, tvo, clk_32k, clk_m, clk_m_div2, 341 clk_m_div4, pll_ref, pll_c, pll_c_out1, pll_m, pll_m_out1, pll_p, 342 pll_p_out1, pll_p_out2, pll_p_out3, pll_p_out4, pll_a, pll_a_out0, 343 pll_d, pll_d_out0, pll_d2, pll_d2_out0, pll_u, pll_x, pll_x_out0, pll_e, 344 spdif_in_sync, i2s0_sync, i2s1_sync, i2s2_sync, i2s3_sync, i2s4_sync, 345 vimclk_sync, audio0, audio1, audio2, audio3, audio4, spdif, clk_out_1, 346 clk_out_2, clk_out_3, sclk, blink, cclk_g, cclk_lp, twd, cml0, cml1, 347 hclk, pclk, clk_out_1_mux = 300, clk_max 348}; 349 350static struct clk *clks[clk_max]; 351static struct clk_onecell_data clk_data; 352 353/* 354 * Structure defining the fields for USB UTMI clocks Parameters. 355 */ 356struct utmi_clk_param { 357 /* Oscillator Frequency in KHz */ 358 u32 osc_frequency; 359 /* UTMIP PLL Enable Delay Count */ 360 u8 enable_delay_count; 361 /* UTMIP PLL Stable count */ 362 u8 stable_count; 363 /* UTMIP PLL Active delay count */ 364 u8 active_delay_count; 365 /* UTMIP PLL Xtal frequency count */ 366 u8 xtal_freq_count; 367}; 368 369static const struct utmi_clk_param utmi_parameters[] = { 370/* OSC_FREQUENCY, ENABLE_DLY, STABLE_CNT, ACTIVE_DLY, XTAL_FREQ_CNT */ 371 {13000000, 0x02, 0x33, 0x05, 0x7F}, 372 {19200000, 0x03, 0x4B, 0x06, 0xBB}, 373 {12000000, 0x02, 0x2F, 0x04, 0x76}, 374 {26000000, 0x04, 0x66, 0x09, 0xFE}, 375 {16800000, 0x03, 0x41, 0x0A, 0xA4}, 376}; 377 378static struct tegra_clk_pll_freq_table pll_c_freq_table[] = { 379 { 12000000, 1040000000, 520, 6, 0, 8}, 380 { 13000000, 1040000000, 480, 6, 0, 8}, 381 { 16800000, 1040000000, 495, 8, 0, 8}, /* actual: 1039.5 MHz */ 382 { 19200000, 1040000000, 325, 6, 0, 6}, 383 { 26000000, 1040000000, 520, 13, 0, 8}, 384 385 { 12000000, 832000000, 416, 6, 0, 8}, 386 { 13000000, 832000000, 832, 13, 0, 8}, 387 { 16800000, 832000000, 396, 8, 0, 8}, /* actual: 831.6 MHz */ 388 { 19200000, 832000000, 260, 6, 0, 8}, 389 { 26000000, 832000000, 416, 13, 0, 8}, 390 391 { 12000000, 624000000, 624, 12, 0, 8}, 392 { 13000000, 624000000, 624, 13, 0, 8}, 393 { 16800000, 600000000, 520, 14, 0, 8}, 394 { 19200000, 624000000, 520, 16, 0, 8}, 395 { 26000000, 624000000, 624, 26, 0, 8}, 396 397 { 12000000, 600000000, 600, 12, 0, 8}, 398 { 13000000, 600000000, 600, 13, 0, 8}, 399 { 16800000, 600000000, 500, 14, 0, 8}, 400 { 19200000, 600000000, 375, 12, 0, 6}, 401 { 26000000, 600000000, 600, 26, 0, 8}, 402 403 { 12000000, 520000000, 520, 12, 0, 8}, 404 { 13000000, 520000000, 520, 13, 0, 8}, 405 { 16800000, 520000000, 495, 16, 0, 8}, /* actual: 519.75 MHz */ 406 { 19200000, 520000000, 325, 12, 0, 6}, 407 { 26000000, 520000000, 520, 26, 0, 8}, 408 409 { 12000000, 416000000, 416, 12, 0, 8}, 410 { 13000000, 416000000, 416, 13, 0, 8}, 411 { 16800000, 416000000, 396, 16, 0, 8}, /* actual: 415.8 MHz */ 412 { 19200000, 416000000, 260, 12, 0, 6}, 413 { 26000000, 416000000, 416, 26, 0, 8}, 414 { 0, 0, 0, 0, 0, 0 }, 415}; 416 417static struct tegra_clk_pll_freq_table pll_m_freq_table[] = { 418 { 12000000, 666000000, 666, 12, 0, 8}, 419 { 13000000, 666000000, 666, 13, 0, 8}, 420 { 16800000, 666000000, 555, 14, 0, 8}, 421 { 19200000, 666000000, 555, 16, 0, 8}, 422 { 26000000, 666000000, 666, 26, 0, 8}, 423 { 12000000, 600000000, 600, 12, 0, 8}, 424 { 13000000, 600000000, 600, 13, 0, 8}, 425 { 16800000, 600000000, 500, 14, 0, 8}, 426 { 19200000, 600000000, 375, 12, 0, 6}, 427 { 26000000, 600000000, 600, 26, 0, 8}, 428 { 0, 0, 0, 0, 0, 0 }, 429}; 430 431static struct tegra_clk_pll_freq_table pll_p_freq_table[] = { 432 { 12000000, 216000000, 432, 12, 1, 8}, 433 { 13000000, 216000000, 432, 13, 1, 8}, 434 { 16800000, 216000000, 360, 14, 1, 8}, 435 { 19200000, 216000000, 360, 16, 1, 8}, 436 { 26000000, 216000000, 432, 26, 1, 8}, 437 { 0, 0, 0, 0, 0, 0 }, 438}; 439 440static struct tegra_clk_pll_freq_table pll_a_freq_table[] = { 441 { 9600000, 564480000, 294, 5, 0, 4}, 442 { 9600000, 552960000, 288, 5, 0, 4}, 443 { 9600000, 24000000, 5, 2, 0, 1}, 444 445 { 28800000, 56448000, 49, 25, 0, 1}, 446 { 28800000, 73728000, 64, 25, 0, 1}, 447 { 28800000, 24000000, 5, 6, 0, 1}, 448 { 0, 0, 0, 0, 0, 0 }, 449}; 450 451static struct tegra_clk_pll_freq_table pll_d_freq_table[] = { 452 { 12000000, 216000000, 216, 12, 0, 4}, 453 { 13000000, 216000000, 216, 13, 0, 4}, 454 { 16800000, 216000000, 180, 14, 0, 4}, 455 { 19200000, 216000000, 180, 16, 0, 4}, 456 { 26000000, 216000000, 216, 26, 0, 4}, 457 458 { 12000000, 594000000, 594, 12, 0, 8}, 459 { 13000000, 594000000, 594, 13, 0, 8}, 460 { 16800000, 594000000, 495, 14, 0, 8}, 461 { 19200000, 594000000, 495, 16, 0, 8}, 462 { 26000000, 594000000, 594, 26, 0, 8}, 463 464 { 12000000, 1000000000, 1000, 12, 0, 12}, 465 { 13000000, 1000000000, 1000, 13, 0, 12}, 466 { 19200000, 1000000000, 625, 12, 0, 8}, 467 { 26000000, 1000000000, 1000, 26, 0, 12}, 468 469 { 0, 0, 0, 0, 0, 0 }, 470}; 471 472static struct pdiv_map pllu_p[] = { 473 { .pdiv = 1, .hw_val = 1 }, 474 { .pdiv = 2, .hw_val = 0 }, 475 { .pdiv = 0, .hw_val = 0 }, 476}; 477 478static struct tegra_clk_pll_freq_table pll_u_freq_table[] = { 479 { 12000000, 480000000, 960, 12, 0, 12}, 480 { 13000000, 480000000, 960, 13, 0, 12}, 481 { 16800000, 480000000, 400, 7, 0, 5}, 482 { 19200000, 480000000, 200, 4, 0, 3}, 483 { 26000000, 480000000, 960, 26, 0, 12}, 484 { 0, 0, 0, 0, 0, 0 }, 485}; 486 487static struct tegra_clk_pll_freq_table pll_x_freq_table[] = { 488 /* 1.7 GHz */ 489 { 12000000, 1700000000, 850, 6, 0, 8}, 490 { 13000000, 1700000000, 915, 7, 0, 8}, /* actual: 1699.2 MHz */ 491 { 16800000, 1700000000, 708, 7, 0, 8}, /* actual: 1699.2 MHz */ 492 { 19200000, 1700000000, 885, 10, 0, 8}, /* actual: 1699.2 MHz */ 493 { 26000000, 1700000000, 850, 13, 0, 8}, 494 495 /* 1.6 GHz */ 496 { 12000000, 1600000000, 800, 6, 0, 8}, 497 { 13000000, 1600000000, 738, 6, 0, 8}, /* actual: 1599.0 MHz */ 498 { 16800000, 1600000000, 857, 9, 0, 8}, /* actual: 1599.7 MHz */ 499 { 19200000, 1600000000, 500, 6, 0, 8}, 500 { 26000000, 1600000000, 800, 13, 0, 8}, 501 502 /* 1.5 GHz */ 503 { 12000000, 1500000000, 750, 6, 0, 8}, 504 { 13000000, 1500000000, 923, 8, 0, 8}, /* actual: 1499.8 MHz */ 505 { 16800000, 1500000000, 625, 7, 0, 8}, 506 { 19200000, 1500000000, 625, 8, 0, 8}, 507 { 26000000, 1500000000, 750, 13, 0, 8}, 508 509 /* 1.4 GHz */ 510 { 12000000, 1400000000, 700, 6, 0, 8}, 511 { 13000000, 1400000000, 969, 9, 0, 8}, /* actual: 1399.7 MHz */ 512 { 16800000, 1400000000, 1000, 12, 0, 8}, 513 { 19200000, 1400000000, 875, 12, 0, 8}, 514 { 26000000, 1400000000, 700, 13, 0, 8}, 515 516 /* 1.3 GHz */ 517 { 12000000, 1300000000, 975, 9, 0, 8}, 518 { 13000000, 1300000000, 1000, 10, 0, 8}, 519 { 16800000, 1300000000, 928, 12, 0, 8}, /* actual: 1299.2 MHz */ 520 { 19200000, 1300000000, 812, 12, 0, 8}, /* actual: 1299.2 MHz */ 521 { 26000000, 1300000000, 650, 13, 0, 8}, 522 523 /* 1.2 GHz */ 524 { 12000000, 1200000000, 1000, 10, 0, 8}, 525 { 13000000, 1200000000, 923, 10, 0, 8}, /* actual: 1199.9 MHz */ 526 { 16800000, 1200000000, 1000, 14, 0, 8}, 527 { 19200000, 1200000000, 1000, 16, 0, 8}, 528 { 26000000, 1200000000, 600, 13, 0, 8}, 529 530 /* 1.1 GHz */ 531 { 12000000, 1100000000, 825, 9, 0, 8}, 532 { 13000000, 1100000000, 846, 10, 0, 8}, /* actual: 1099.8 MHz */ 533 { 16800000, 1100000000, 982, 15, 0, 8}, /* actual: 1099.8 MHz */ 534 { 19200000, 1100000000, 859, 15, 0, 8}, /* actual: 1099.5 MHz */ 535 { 26000000, 1100000000, 550, 13, 0, 8}, 536 537 /* 1 GHz */ 538 { 12000000, 1000000000, 1000, 12, 0, 8}, 539 { 13000000, 1000000000, 1000, 13, 0, 8}, 540 { 16800000, 1000000000, 833, 14, 0, 8}, /* actual: 999.6 MHz */ 541 { 19200000, 1000000000, 625, 12, 0, 8}, 542 { 26000000, 1000000000, 1000, 26, 0, 8}, 543 544 { 0, 0, 0, 0, 0, 0 }, 545}; 546 547static struct tegra_clk_pll_freq_table pll_e_freq_table[] = { 548 /* PLLE special case: use cpcon field to store cml divider value */ 549 { 12000000, 100000000, 150, 1, 18, 11}, 550 { 216000000, 100000000, 200, 18, 24, 13}, 551 { 0, 0, 0, 0, 0, 0 }, 552}; 553 554/* PLL parameters */ 555static struct tegra_clk_pll_params pll_c_params = { 556 .input_min = 2000000, 557 .input_max = 31000000, 558 .cf_min = 1000000, 559 .cf_max = 6000000, 560 .vco_min = 20000000, 561 .vco_max = 1400000000, 562 .base_reg = PLLC_BASE, 563 .misc_reg = PLLC_MISC, 564 .lock_mask = PLL_BASE_LOCK, 565 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE, 566 .lock_delay = 300, 567}; 568 569static struct div_nmp pllm_nmp = { 570 .divn_shift = 8, 571 .divn_width = 10, 572 .override_divn_shift = 5, 573 .divm_shift = 0, 574 .divm_width = 5, 575 .override_divm_shift = 0, 576 .divp_shift = 20, 577 .divp_width = 3, 578 .override_divp_shift = 15, 579}; 580 581static struct tegra_clk_pll_params pll_m_params = { 582 .input_min = 2000000, 583 .input_max = 31000000, 584 .cf_min = 1000000, 585 .cf_max = 6000000, 586 .vco_min = 20000000, 587 .vco_max = 1200000000, 588 .base_reg = PLLM_BASE, 589 .misc_reg = PLLM_MISC, 590 .lock_mask = PLL_BASE_LOCK, 591 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE, 592 .lock_delay = 300, 593 .div_nmp = &pllm_nmp, 594 .pmc_divnm_reg = PMC_PLLM_WB0_OVERRIDE, 595 .pmc_divp_reg = PMC_PLLM_WB0_OVERRIDE, 596}; 597 598static struct tegra_clk_pll_params pll_p_params = { 599 .input_min = 2000000, 600 .input_max = 31000000, 601 .cf_min = 1000000, 602 .cf_max = 6000000, 603 .vco_min = 20000000, 604 .vco_max = 1400000000, 605 .base_reg = PLLP_BASE, 606 .misc_reg = PLLP_MISC, 607 .lock_mask = PLL_BASE_LOCK, 608 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE, 609 .lock_delay = 300, 610}; 611 612static struct tegra_clk_pll_params pll_a_params = { 613 .input_min = 2000000, 614 .input_max = 31000000, 615 .cf_min = 1000000, 616 .cf_max = 6000000, 617 .vco_min = 20000000, 618 .vco_max = 1400000000, 619 .base_reg = PLLA_BASE, 620 .misc_reg = PLLA_MISC, 621 .lock_mask = PLL_BASE_LOCK, 622 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE, 623 .lock_delay = 300, 624}; 625 626static struct tegra_clk_pll_params pll_d_params = { 627 .input_min = 2000000, 628 .input_max = 40000000, 629 .cf_min = 1000000, 630 .cf_max = 6000000, 631 .vco_min = 40000000, 632 .vco_max = 1000000000, 633 .base_reg = PLLD_BASE, 634 .misc_reg = PLLD_MISC, 635 .lock_mask = PLL_BASE_LOCK, 636 .lock_enable_bit_idx = PLLDU_MISC_LOCK_ENABLE, 637 .lock_delay = 1000, 638}; 639 640static struct tegra_clk_pll_params pll_d2_params = { 641 .input_min = 2000000, 642 .input_max = 40000000, 643 .cf_min = 1000000, 644 .cf_max = 6000000, 645 .vco_min = 40000000, 646 .vco_max = 1000000000, 647 .base_reg = PLLD2_BASE, 648 .misc_reg = PLLD2_MISC, 649 .lock_mask = PLL_BASE_LOCK, 650 .lock_enable_bit_idx = PLLDU_MISC_LOCK_ENABLE, 651 .lock_delay = 1000, 652}; 653 654static struct tegra_clk_pll_params pll_u_params = { 655 .input_min = 2000000, 656 .input_max = 40000000, 657 .cf_min = 1000000, 658 .cf_max = 6000000, 659 .vco_min = 48000000, 660 .vco_max = 960000000, 661 .base_reg = PLLU_BASE, 662 .misc_reg = PLLU_MISC, 663 .lock_mask = PLL_BASE_LOCK, 664 .lock_enable_bit_idx = PLLDU_MISC_LOCK_ENABLE, 665 .lock_delay = 1000, 666 .pdiv_tohw = pllu_p, 667}; 668 669static struct tegra_clk_pll_params pll_x_params = { 670 .input_min = 2000000, 671 .input_max = 31000000, 672 .cf_min = 1000000, 673 .cf_max = 6000000, 674 .vco_min = 20000000, 675 .vco_max = 1700000000, 676 .base_reg = PLLX_BASE, 677 .misc_reg = PLLX_MISC, 678 .lock_mask = PLL_BASE_LOCK, 679 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE, 680 .lock_delay = 300, 681}; 682 683static struct tegra_clk_pll_params pll_e_params = { 684 .input_min = 12000000, 685 .input_max = 216000000, 686 .cf_min = 12000000, 687 .cf_max = 12000000, 688 .vco_min = 1200000000, 689 .vco_max = 2400000000U, 690 .base_reg = PLLE_BASE, 691 .misc_reg = PLLE_MISC, 692 .lock_mask = PLLE_MISC_LOCK, 693 .lock_enable_bit_idx = PLLE_MISC_LOCK_ENABLE, 694 .lock_delay = 300, 695}; 696 697/* Peripheral clock registers */ 698static struct tegra_clk_periph_regs periph_l_regs = { 699 .enb_reg = CLK_OUT_ENB_L, 700 .enb_set_reg = CLK_OUT_ENB_SET_L, 701 .enb_clr_reg = CLK_OUT_ENB_CLR_L, 702 .rst_reg = RST_DEVICES_L, 703 .rst_set_reg = RST_DEVICES_SET_L, 704 .rst_clr_reg = RST_DEVICES_CLR_L, 705}; 706 707static struct tegra_clk_periph_regs periph_h_regs = { 708 .enb_reg = CLK_OUT_ENB_H, 709 .enb_set_reg = CLK_OUT_ENB_SET_H, 710 .enb_clr_reg = CLK_OUT_ENB_CLR_H, 711 .rst_reg = RST_DEVICES_H, 712 .rst_set_reg = RST_DEVICES_SET_H, 713 .rst_clr_reg = RST_DEVICES_CLR_H, 714}; 715 716static struct tegra_clk_periph_regs periph_u_regs = { 717 .enb_reg = CLK_OUT_ENB_U, 718 .enb_set_reg = CLK_OUT_ENB_SET_U, 719 .enb_clr_reg = CLK_OUT_ENB_CLR_U, 720 .rst_reg = RST_DEVICES_U, 721 .rst_set_reg = RST_DEVICES_SET_U, 722 .rst_clr_reg = RST_DEVICES_CLR_U, 723}; 724 725static struct tegra_clk_periph_regs periph_v_regs = { 726 .enb_reg = CLK_OUT_ENB_V, 727 .enb_set_reg = CLK_OUT_ENB_SET_V, 728 .enb_clr_reg = CLK_OUT_ENB_CLR_V, 729 .rst_reg = RST_DEVICES_V, 730 .rst_set_reg = RST_DEVICES_SET_V, 731 .rst_clr_reg = RST_DEVICES_CLR_V, 732}; 733 734static struct tegra_clk_periph_regs periph_w_regs = { 735 .enb_reg = CLK_OUT_ENB_W, 736 .enb_set_reg = CLK_OUT_ENB_SET_W, 737 .enb_clr_reg = CLK_OUT_ENB_CLR_W, 738 .rst_reg = RST_DEVICES_W, 739 .rst_set_reg = RST_DEVICES_SET_W, 740 .rst_clr_reg = RST_DEVICES_CLR_W, 741}; 742 743static void tegra30_clk_measure_input_freq(void) 744{ 745 u32 osc_ctrl = readl_relaxed(clk_base + OSC_CTRL); 746 u32 auto_clk_control = osc_ctrl & OSC_CTRL_OSC_FREQ_MASK; 747 u32 pll_ref_div = osc_ctrl & OSC_CTRL_PLL_REF_DIV_MASK; 748 749 switch (auto_clk_control) { 750 case OSC_CTRL_OSC_FREQ_12MHZ: 751 BUG_ON(pll_ref_div != OSC_CTRL_PLL_REF_DIV_1); 752 input_freq = 12000000; 753 break; 754 case OSC_CTRL_OSC_FREQ_13MHZ: 755 BUG_ON(pll_ref_div != OSC_CTRL_PLL_REF_DIV_1); 756 input_freq = 13000000; 757 break; 758 case OSC_CTRL_OSC_FREQ_19_2MHZ: 759 BUG_ON(pll_ref_div != OSC_CTRL_PLL_REF_DIV_1); 760 input_freq = 19200000; 761 break; 762 case OSC_CTRL_OSC_FREQ_26MHZ: 763 BUG_ON(pll_ref_div != OSC_CTRL_PLL_REF_DIV_1); 764 input_freq = 26000000; 765 break; 766 case OSC_CTRL_OSC_FREQ_16_8MHZ: 767 BUG_ON(pll_ref_div != OSC_CTRL_PLL_REF_DIV_1); 768 input_freq = 16800000; 769 break; 770 case OSC_CTRL_OSC_FREQ_38_4MHZ: 771 BUG_ON(pll_ref_div != OSC_CTRL_PLL_REF_DIV_2); 772 input_freq = 38400000; 773 break; 774 case OSC_CTRL_OSC_FREQ_48MHZ: 775 BUG_ON(pll_ref_div != OSC_CTRL_PLL_REF_DIV_4); 776 input_freq = 48000000; 777 break; 778 default: 779 pr_err("Unexpected auto clock control value %d", 780 auto_clk_control); 781 BUG(); 782 return; 783 } 784} 785 786static unsigned int tegra30_get_pll_ref_div(void) 787{ 788 u32 pll_ref_div = readl_relaxed(clk_base + OSC_CTRL) & 789 OSC_CTRL_PLL_REF_DIV_MASK; 790 791 switch (pll_ref_div) { 792 case OSC_CTRL_PLL_REF_DIV_1: 793 return 1; 794 case OSC_CTRL_PLL_REF_DIV_2: 795 return 2; 796 case OSC_CTRL_PLL_REF_DIV_4: 797 return 4; 798 default: 799 pr_err("Invalid pll ref divider %d", pll_ref_div); 800 BUG(); 801 } 802 return 0; 803} 804 805static void tegra30_utmi_param_configure(void) 806{ 807 u32 reg; 808 int i; 809 810 for (i = 0; i < ARRAY_SIZE(utmi_parameters); i++) { 811 if (input_freq == utmi_parameters[i].osc_frequency) 812 break; 813 } 814 815 if (i >= ARRAY_SIZE(utmi_parameters)) { 816 pr_err("%s: Unexpected input rate %lu\n", __func__, input_freq); 817 return; 818 } 819 820 reg = readl_relaxed(clk_base + UTMIP_PLL_CFG2); 821 822 /* Program UTMIP PLL stable and active counts */ 823 reg &= ~UTMIP_PLL_CFG2_STABLE_COUNT(~0); 824 reg |= UTMIP_PLL_CFG2_STABLE_COUNT( 825 utmi_parameters[i].stable_count); 826 827 reg &= ~UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(~0); 828 829 reg |= UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT( 830 utmi_parameters[i].active_delay_count); 831 832 /* Remove power downs from UTMIP PLL control bits */ 833 reg &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_A_POWERDOWN; 834 reg &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_B_POWERDOWN; 835 reg &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_C_POWERDOWN; 836 837 writel_relaxed(reg, clk_base + UTMIP_PLL_CFG2); 838 839 /* Program UTMIP PLL delay and oscillator frequency counts */ 840 reg = readl_relaxed(clk_base + UTMIP_PLL_CFG1); 841 reg &= ~UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(~0); 842 843 reg |= UTMIP_PLL_CFG1_ENABLE_DLY_COUNT( 844 utmi_parameters[i].enable_delay_count); 845 846 reg &= ~UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(~0); 847 reg |= UTMIP_PLL_CFG1_XTAL_FREQ_COUNT( 848 utmi_parameters[i].xtal_freq_count); 849 850 /* Remove power downs from UTMIP PLL control bits */ 851 reg &= ~UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN; 852 reg &= ~UTMIP_PLL_CFG1_FORCE_PLL_ACTIVE_POWERDOWN; 853 reg &= ~UTMIP_PLL_CFG1_FORCE_PLLU_POWERDOWN; 854 855 writel_relaxed(reg, clk_base + UTMIP_PLL_CFG1); 856} 857 858static const char *pll_e_parents[] = {"pll_ref", "pll_p"}; 859 860static void __init tegra30_pll_init(void) 861{ 862 struct clk *clk; 863 864 /* PLLC */ 865 clk = tegra_clk_register_pll("pll_c", "pll_ref", clk_base, pmc_base, 0, 866 0, &pll_c_params, 867 TEGRA_PLL_HAS_CPCON | TEGRA_PLL_USE_LOCK, 868 pll_c_freq_table, NULL); 869 clk_register_clkdev(clk, "pll_c", NULL); 870 clks[pll_c] = clk; 871 872 /* PLLC_OUT1 */ 873 clk = tegra_clk_register_divider("pll_c_out1_div", "pll_c", 874 clk_base + PLLC_OUT, 0, TEGRA_DIVIDER_ROUND_UP, 875 8, 8, 1, NULL); 876 clk = tegra_clk_register_pll_out("pll_c_out1", "pll_c_out1_div", 877 clk_base + PLLC_OUT, 1, 0, CLK_SET_RATE_PARENT, 878 0, NULL); 879 clk_register_clkdev(clk, "pll_c_out1", NULL); 880 clks[pll_c_out1] = clk; 881 882 /* PLLP */ 883 clk = tegra_clk_register_pll("pll_p", "pll_ref", clk_base, pmc_base, 0, 884 408000000, &pll_p_params, 885 TEGRA_PLL_FIXED | TEGRA_PLL_HAS_CPCON | 886 TEGRA_PLL_USE_LOCK, pll_p_freq_table, NULL); 887 clk_register_clkdev(clk, "pll_p", NULL); 888 clks[pll_p] = clk; 889 890 /* PLLP_OUT1 */ 891 clk = tegra_clk_register_divider("pll_p_out1_div", "pll_p", 892 clk_base + PLLP_OUTA, 0, TEGRA_DIVIDER_FIXED | 893 TEGRA_DIVIDER_ROUND_UP, 8, 8, 1, 894 &pll_div_lock); 895 clk = tegra_clk_register_pll_out("pll_p_out1", "pll_p_out1_div", 896 clk_base + PLLP_OUTA, 1, 0, 897 CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0, 898 &pll_div_lock); 899 clk_register_clkdev(clk, "pll_p_out1", NULL); 900 clks[pll_p_out1] = clk; 901 902 /* PLLP_OUT2 */ 903 clk = tegra_clk_register_divider("pll_p_out2_div", "pll_p", 904 clk_base + PLLP_OUTA, 0, TEGRA_DIVIDER_FIXED | 905 TEGRA_DIVIDER_ROUND_UP, 24, 8, 1, 906 &pll_div_lock); 907 clk = tegra_clk_register_pll_out("pll_p_out2", "pll_p_out2_div", 908 clk_base + PLLP_OUTA, 17, 16, 909 CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0, 910 &pll_div_lock); 911 clk_register_clkdev(clk, "pll_p_out2", NULL); 912 clks[pll_p_out2] = clk; 913 914 /* PLLP_OUT3 */ 915 clk = tegra_clk_register_divider("pll_p_out3_div", "pll_p", 916 clk_base + PLLP_OUTB, 0, TEGRA_DIVIDER_FIXED | 917 TEGRA_DIVIDER_ROUND_UP, 8, 8, 1, 918 &pll_div_lock); 919 clk = tegra_clk_register_pll_out("pll_p_out3", "pll_p_out3_div", 920 clk_base + PLLP_OUTB, 1, 0, 921 CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0, 922 &pll_div_lock); 923 clk_register_clkdev(clk, "pll_p_out3", NULL); 924 clks[pll_p_out3] = clk; 925 926 /* PLLP_OUT4 */ 927 clk = tegra_clk_register_divider("pll_p_out4_div", "pll_p", 928 clk_base + PLLP_OUTB, 0, TEGRA_DIVIDER_FIXED | 929 TEGRA_DIVIDER_ROUND_UP, 24, 8, 1, 930 &pll_div_lock); 931 clk = tegra_clk_register_pll_out("pll_p_out4", "pll_p_out4_div", 932 clk_base + PLLP_OUTB, 17, 16, 933 CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0, 934 &pll_div_lock); 935 clk_register_clkdev(clk, "pll_p_out4", NULL); 936 clks[pll_p_out4] = clk; 937 938 /* PLLM */ 939 clk = tegra_clk_register_pll("pll_m", "pll_ref", clk_base, pmc_base, 940 CLK_IGNORE_UNUSED | CLK_SET_RATE_GATE, 0, 941 &pll_m_params, TEGRA_PLLM | TEGRA_PLL_HAS_CPCON | 942 TEGRA_PLL_SET_DCCON | TEGRA_PLL_USE_LOCK, 943 pll_m_freq_table, NULL); 944 clk_register_clkdev(clk, "pll_m", NULL); 945 clks[pll_m] = clk; 946 947 /* PLLM_OUT1 */ 948 clk = tegra_clk_register_divider("pll_m_out1_div", "pll_m", 949 clk_base + PLLM_OUT, 0, TEGRA_DIVIDER_ROUND_UP, 950 8, 8, 1, NULL); 951 clk = tegra_clk_register_pll_out("pll_m_out1", "pll_m_out1_div", 952 clk_base + PLLM_OUT, 1, 0, CLK_IGNORE_UNUSED | 953 CLK_SET_RATE_PARENT, 0, NULL); 954 clk_register_clkdev(clk, "pll_m_out1", NULL); 955 clks[pll_m_out1] = clk; 956 957 /* PLLX */ 958 clk = tegra_clk_register_pll("pll_x", "pll_ref", clk_base, pmc_base, 0, 959 0, &pll_x_params, TEGRA_PLL_HAS_CPCON | 960 TEGRA_PLL_SET_DCCON | TEGRA_PLL_USE_LOCK, 961 pll_x_freq_table, NULL); 962 clk_register_clkdev(clk, "pll_x", NULL); 963 clks[pll_x] = clk; 964 965 /* PLLX_OUT0 */ 966 clk = clk_register_fixed_factor(NULL, "pll_x_out0", "pll_x", 967 CLK_SET_RATE_PARENT, 1, 2); 968 clk_register_clkdev(clk, "pll_x_out0", NULL); 969 clks[pll_x_out0] = clk; 970 971 /* PLLU */ 972 clk = tegra_clk_register_pll("pll_u", "pll_ref", clk_base, pmc_base, 0, 973 0, &pll_u_params, TEGRA_PLLU | TEGRA_PLL_HAS_CPCON | 974 TEGRA_PLL_SET_LFCON | TEGRA_PLL_USE_LOCK, 975 pll_u_freq_table, 976 NULL); 977 clk_register_clkdev(clk, "pll_u", NULL); 978 clks[pll_u] = clk; 979 980 tegra30_utmi_param_configure(); 981 982 /* PLLD */ 983 clk = tegra_clk_register_pll("pll_d", "pll_ref", clk_base, pmc_base, 0, 984 0, &pll_d_params, TEGRA_PLL_HAS_CPCON | 985 TEGRA_PLL_SET_LFCON | TEGRA_PLL_USE_LOCK, 986 pll_d_freq_table, &pll_d_lock); 987 clk_register_clkdev(clk, "pll_d", NULL); 988 clks[pll_d] = clk; 989 990 /* PLLD_OUT0 */ 991 clk = clk_register_fixed_factor(NULL, "pll_d_out0", "pll_d", 992 CLK_SET_RATE_PARENT, 1, 2); 993 clk_register_clkdev(clk, "pll_d_out0", NULL); 994 clks[pll_d_out0] = clk; 995 996 /* PLLD2 */ 997 clk = tegra_clk_register_pll("pll_d2", "pll_ref", clk_base, pmc_base, 0, 998 0, &pll_d2_params, TEGRA_PLL_HAS_CPCON | 999 TEGRA_PLL_SET_LFCON | TEGRA_PLL_USE_LOCK, 1000 pll_d_freq_table, NULL); 1001 clk_register_clkdev(clk, "pll_d2", NULL); 1002 clks[pll_d2] = clk; 1003 1004 /* PLLD2_OUT0 */ 1005 clk = clk_register_fixed_factor(NULL, "pll_d2_out0", "pll_d2", 1006 CLK_SET_RATE_PARENT, 1, 2); 1007 clk_register_clkdev(clk, "pll_d2_out0", NULL); 1008 clks[pll_d2_out0] = clk; 1009 1010 /* PLLA */ 1011 clk = tegra_clk_register_pll("pll_a", "pll_p_out1", clk_base, pmc_base, 1012 0, 0, &pll_a_params, TEGRA_PLL_HAS_CPCON | 1013 TEGRA_PLL_USE_LOCK, pll_a_freq_table, NULL); 1014 clk_register_clkdev(clk, "pll_a", NULL); 1015 clks[pll_a] = clk; 1016 1017 /* PLLA_OUT0 */ 1018 clk = tegra_clk_register_divider("pll_a_out0_div", "pll_a", 1019 clk_base + PLLA_OUT, 0, TEGRA_DIVIDER_ROUND_UP, 1020 8, 8, 1, NULL); 1021 clk = tegra_clk_register_pll_out("pll_a_out0", "pll_a_out0_div", 1022 clk_base + PLLA_OUT, 1, 0, CLK_IGNORE_UNUSED | 1023 CLK_SET_RATE_PARENT, 0, NULL); 1024 clk_register_clkdev(clk, "pll_a_out0", NULL); 1025 clks[pll_a_out0] = clk; 1026 1027 /* PLLE */ 1028 clk = clk_register_mux(NULL, "pll_e_mux", pll_e_parents, 1029 ARRAY_SIZE(pll_e_parents), 0, 1030 clk_base + PLLE_AUX, 2, 1, 0, NULL); 1031 clk = tegra_clk_register_plle("pll_e", "pll_e_mux", clk_base, pmc_base, 1032 CLK_GET_RATE_NOCACHE, 100000000, &pll_e_params, 1033 TEGRA_PLLE_CONFIGURE, pll_e_freq_table, NULL); 1034 clk_register_clkdev(clk, "pll_e", NULL); 1035 clks[pll_e] = clk; 1036} 1037 1038static const char *mux_audio_sync_clk[] = { "spdif_in_sync", "i2s0_sync", 1039 "i2s1_sync", "i2s2_sync", "i2s3_sync", "i2s4_sync", "vimclk_sync",}; 1040static const char *clk_out1_parents[] = { "clk_m", "clk_m_div2", 1041 "clk_m_div4", "extern1", }; 1042static const char *clk_out2_parents[] = { "clk_m", "clk_m_div2", 1043 "clk_m_div4", "extern2", }; 1044static const char *clk_out3_parents[] = { "clk_m", "clk_m_div2", 1045 "clk_m_div4", "extern3", }; 1046 1047static void __init tegra30_audio_clk_init(void) 1048{ 1049 struct clk *clk; 1050 1051 /* spdif_in_sync */ 1052 clk = tegra_clk_register_sync_source("spdif_in_sync", 24000000, 1053 24000000); 1054 clk_register_clkdev(clk, "spdif_in_sync", NULL); 1055 clks[spdif_in_sync] = clk; 1056 1057 /* i2s0_sync */ 1058 clk = tegra_clk_register_sync_source("i2s0_sync", 24000000, 24000000); 1059 clk_register_clkdev(clk, "i2s0_sync", NULL); 1060 clks[i2s0_sync] = clk; 1061 1062 /* i2s1_sync */ 1063 clk = tegra_clk_register_sync_source("i2s1_sync", 24000000, 24000000); 1064 clk_register_clkdev(clk, "i2s1_sync", NULL); 1065 clks[i2s1_sync] = clk; 1066 1067 /* i2s2_sync */ 1068 clk = tegra_clk_register_sync_source("i2s2_sync", 24000000, 24000000); 1069 clk_register_clkdev(clk, "i2s2_sync", NULL); 1070 clks[i2s2_sync] = clk; 1071 1072 /* i2s3_sync */ 1073 clk = tegra_clk_register_sync_source("i2s3_sync", 24000000, 24000000); 1074 clk_register_clkdev(clk, "i2s3_sync", NULL); 1075 clks[i2s3_sync] = clk; 1076 1077 /* i2s4_sync */ 1078 clk = tegra_clk_register_sync_source("i2s4_sync", 24000000, 24000000); 1079 clk_register_clkdev(clk, "i2s4_sync", NULL); 1080 clks[i2s4_sync] = clk; 1081 1082 /* vimclk_sync */ 1083 clk = tegra_clk_register_sync_source("vimclk_sync", 24000000, 24000000); 1084 clk_register_clkdev(clk, "vimclk_sync", NULL); 1085 clks[vimclk_sync] = clk; 1086 1087 /* audio0 */ 1088 clk = clk_register_mux(NULL, "audio0_mux", mux_audio_sync_clk, 1089 ARRAY_SIZE(mux_audio_sync_clk), 0, 1090 clk_base + AUDIO_SYNC_CLK_I2S0, 0, 3, 0, NULL); 1091 clk = clk_register_gate(NULL, "audio0", "audio0_mux", 0, 1092 clk_base + AUDIO_SYNC_CLK_I2S0, 4, 1093 CLK_GATE_SET_TO_DISABLE, NULL); 1094 clk_register_clkdev(clk, "audio0", NULL); 1095 clks[audio0] = clk; 1096 1097 /* audio1 */ 1098 clk = clk_register_mux(NULL, "audio1_mux", mux_audio_sync_clk, 1099 ARRAY_SIZE(mux_audio_sync_clk), 0, 1100 clk_base + AUDIO_SYNC_CLK_I2S1, 0, 3, 0, NULL); 1101 clk = clk_register_gate(NULL, "audio1", "audio1_mux", 0, 1102 clk_base + AUDIO_SYNC_CLK_I2S1, 4, 1103 CLK_GATE_SET_TO_DISABLE, NULL); 1104 clk_register_clkdev(clk, "audio1", NULL); 1105 clks[audio1] = clk; 1106 1107 /* audio2 */ 1108 clk = clk_register_mux(NULL, "audio2_mux", mux_audio_sync_clk, 1109 ARRAY_SIZE(mux_audio_sync_clk), 0, 1110 clk_base + AUDIO_SYNC_CLK_I2S2, 0, 3, 0, NULL); 1111 clk = clk_register_gate(NULL, "audio2", "audio2_mux", 0, 1112 clk_base + AUDIO_SYNC_CLK_I2S2, 4, 1113 CLK_GATE_SET_TO_DISABLE, NULL); 1114 clk_register_clkdev(clk, "audio2", NULL); 1115 clks[audio2] = clk; 1116 1117 /* audio3 */ 1118 clk = clk_register_mux(NULL, "audio3_mux", mux_audio_sync_clk, 1119 ARRAY_SIZE(mux_audio_sync_clk), 0, 1120 clk_base + AUDIO_SYNC_CLK_I2S3, 0, 3, 0, NULL); 1121 clk = clk_register_gate(NULL, "audio3", "audio3_mux", 0, 1122 clk_base + AUDIO_SYNC_CLK_I2S3, 4, 1123 CLK_GATE_SET_TO_DISABLE, NULL); 1124 clk_register_clkdev(clk, "audio3", NULL); 1125 clks[audio3] = clk; 1126 1127 /* audio4 */ 1128 clk = clk_register_mux(NULL, "audio4_mux", mux_audio_sync_clk, 1129 ARRAY_SIZE(mux_audio_sync_clk), 0, 1130 clk_base + AUDIO_SYNC_CLK_I2S4, 0, 3, 0, NULL); 1131 clk = clk_register_gate(NULL, "audio4", "audio4_mux", 0, 1132 clk_base + AUDIO_SYNC_CLK_I2S4, 4, 1133 CLK_GATE_SET_TO_DISABLE, NULL); 1134 clk_register_clkdev(clk, "audio4", NULL); 1135 clks[audio4] = clk; 1136 1137 /* spdif */ 1138 clk = clk_register_mux(NULL, "spdif_mux", mux_audio_sync_clk, 1139 ARRAY_SIZE(mux_audio_sync_clk), 0, 1140 clk_base + AUDIO_SYNC_CLK_SPDIF, 0, 3, 0, NULL); 1141 clk = clk_register_gate(NULL, "spdif", "spdif_mux", 0, 1142 clk_base + AUDIO_SYNC_CLK_SPDIF, 4, 1143 CLK_GATE_SET_TO_DISABLE, NULL); 1144 clk_register_clkdev(clk, "spdif", NULL); 1145 clks[spdif] = clk; 1146 1147 /* audio0_2x */ 1148 clk = clk_register_fixed_factor(NULL, "audio0_doubler", "audio0", 1149 CLK_SET_RATE_PARENT, 2, 1); 1150 clk = tegra_clk_register_divider("audio0_div", "audio0_doubler", 1151 clk_base + AUDIO_SYNC_DOUBLER, 0, 0, 24, 1, 0, 1152 &clk_doubler_lock); 1153 clk = tegra_clk_register_periph_gate("audio0_2x", "audio0_div", 1154 TEGRA_PERIPH_NO_RESET, clk_base, 1155 CLK_SET_RATE_PARENT, 113, &periph_v_regs, 1156 periph_clk_enb_refcnt); 1157 clk_register_clkdev(clk, "audio0_2x", NULL); 1158 clks[audio0_2x] = clk; 1159 1160 /* audio1_2x */ 1161 clk = clk_register_fixed_factor(NULL, "audio1_doubler", "audio1", 1162 CLK_SET_RATE_PARENT, 2, 1); 1163 clk = tegra_clk_register_divider("audio1_div", "audio1_doubler", 1164 clk_base + AUDIO_SYNC_DOUBLER, 0, 0, 25, 1, 0, 1165 &clk_doubler_lock); 1166 clk = tegra_clk_register_periph_gate("audio1_2x", "audio1_div", 1167 TEGRA_PERIPH_NO_RESET, clk_base, 1168 CLK_SET_RATE_PARENT, 114, &periph_v_regs, 1169 periph_clk_enb_refcnt); 1170 clk_register_clkdev(clk, "audio1_2x", NULL); 1171 clks[audio1_2x] = clk; 1172 1173 /* audio2_2x */ 1174 clk = clk_register_fixed_factor(NULL, "audio2_doubler", "audio2", 1175 CLK_SET_RATE_PARENT, 2, 1); 1176 clk = tegra_clk_register_divider("audio2_div", "audio2_doubler", 1177 clk_base + AUDIO_SYNC_DOUBLER, 0, 0, 26, 1, 0, 1178 &clk_doubler_lock); 1179 clk = tegra_clk_register_periph_gate("audio2_2x", "audio2_div", 1180 TEGRA_PERIPH_NO_RESET, clk_base, 1181 CLK_SET_RATE_PARENT, 115, &periph_v_regs, 1182 periph_clk_enb_refcnt); 1183 clk_register_clkdev(clk, "audio2_2x", NULL); 1184 clks[audio2_2x] = clk; 1185 1186 /* audio3_2x */ 1187 clk = clk_register_fixed_factor(NULL, "audio3_doubler", "audio3", 1188 CLK_SET_RATE_PARENT, 2, 1); 1189 clk = tegra_clk_register_divider("audio3_div", "audio3_doubler", 1190 clk_base + AUDIO_SYNC_DOUBLER, 0, 0, 27, 1, 0, 1191 &clk_doubler_lock); 1192 clk = tegra_clk_register_periph_gate("audio3_2x", "audio3_div", 1193 TEGRA_PERIPH_NO_RESET, clk_base, 1194 CLK_SET_RATE_PARENT, 116, &periph_v_regs, 1195 periph_clk_enb_refcnt); 1196 clk_register_clkdev(clk, "audio3_2x", NULL); 1197 clks[audio3_2x] = clk; 1198 1199 /* audio4_2x */ 1200 clk = clk_register_fixed_factor(NULL, "audio4_doubler", "audio4", 1201 CLK_SET_RATE_PARENT, 2, 1); 1202 clk = tegra_clk_register_divider("audio4_div", "audio4_doubler", 1203 clk_base + AUDIO_SYNC_DOUBLER, 0, 0, 28, 1, 0, 1204 &clk_doubler_lock); 1205 clk = tegra_clk_register_periph_gate("audio4_2x", "audio4_div", 1206 TEGRA_PERIPH_NO_RESET, clk_base, 1207 CLK_SET_RATE_PARENT, 117, &periph_v_regs, 1208 periph_clk_enb_refcnt); 1209 clk_register_clkdev(clk, "audio4_2x", NULL); 1210 clks[audio4_2x] = clk; 1211 1212 /* spdif_2x */ 1213 clk = clk_register_fixed_factor(NULL, "spdif_doubler", "spdif", 1214 CLK_SET_RATE_PARENT, 2, 1); 1215 clk = tegra_clk_register_divider("spdif_div", "spdif_doubler", 1216 clk_base + AUDIO_SYNC_DOUBLER, 0, 0, 29, 1, 0, 1217 &clk_doubler_lock); 1218 clk = tegra_clk_register_periph_gate("spdif_2x", "spdif_div", 1219 TEGRA_PERIPH_NO_RESET, clk_base, 1220 CLK_SET_RATE_PARENT, 118, &periph_v_regs, 1221 periph_clk_enb_refcnt); 1222 clk_register_clkdev(clk, "spdif_2x", NULL); 1223 clks[spdif_2x] = clk; 1224} 1225 1226static void __init tegra30_pmc_clk_init(void) 1227{ 1228 struct clk *clk; 1229 1230 /* clk_out_1 */ 1231 clk = clk_register_mux(NULL, "clk_out_1_mux", clk_out1_parents, 1232 ARRAY_SIZE(clk_out1_parents), 0, 1233 pmc_base + PMC_CLK_OUT_CNTRL, 6, 3, 0, 1234 &clk_out_lock); 1235 clks[clk_out_1_mux] = clk; 1236 clk = clk_register_gate(NULL, "clk_out_1", "clk_out_1_mux", 0, 1237 pmc_base + PMC_CLK_OUT_CNTRL, 2, 0, 1238 &clk_out_lock); 1239 clk_register_clkdev(clk, "extern1", "clk_out_1"); 1240 clks[clk_out_1] = clk; 1241 1242 /* clk_out_2 */ 1243 clk = clk_register_mux(NULL, "clk_out_2_mux", clk_out2_parents, 1244 ARRAY_SIZE(clk_out2_parents), 0, 1245 pmc_base + PMC_CLK_OUT_CNTRL, 14, 3, 0, 1246 &clk_out_lock); 1247 clk = clk_register_gate(NULL, "clk_out_2", "clk_out_2_mux", 0, 1248 pmc_base + PMC_CLK_OUT_CNTRL, 10, 0, 1249 &clk_out_lock); 1250 clk_register_clkdev(clk, "extern2", "clk_out_2"); 1251 clks[clk_out_2] = clk; 1252 1253 /* clk_out_3 */ 1254 clk = clk_register_mux(NULL, "clk_out_3_mux", clk_out3_parents, 1255 ARRAY_SIZE(clk_out3_parents), 0, 1256 pmc_base + PMC_CLK_OUT_CNTRL, 22, 3, 0, 1257 &clk_out_lock); 1258 clk = clk_register_gate(NULL, "clk_out_3", "clk_out_3_mux", 0, 1259 pmc_base + PMC_CLK_OUT_CNTRL, 18, 0, 1260 &clk_out_lock); 1261 clk_register_clkdev(clk, "extern3", "clk_out_3"); 1262 clks[clk_out_3] = clk; 1263 1264 /* blink */ 1265 writel_relaxed(0, pmc_base + PMC_BLINK_TIMER); 1266 clk = clk_register_gate(NULL, "blink_override", "clk_32k", 0, 1267 pmc_base + PMC_DPD_PADS_ORIDE, 1268 PMC_DPD_PADS_ORIDE_BLINK_ENB, 0, NULL); 1269 clk = clk_register_gate(NULL, "blink", "blink_override", 0, 1270 pmc_base + PMC_CTRL, 1271 PMC_CTRL_BLINK_ENB, 0, NULL); 1272 clk_register_clkdev(clk, "blink", NULL); 1273 clks[blink] = clk; 1274 1275} 1276 1277static const char *cclk_g_parents[] = { "clk_m", "pll_c", "clk_32k", "pll_m", 1278 "pll_p_cclkg", "pll_p_out4_cclkg", 1279 "pll_p_out3_cclkg", "unused", "pll_x" }; 1280static const char *cclk_lp_parents[] = { "clk_m", "pll_c", "clk_32k", "pll_m", 1281 "pll_p_cclklp", "pll_p_out4_cclklp", 1282 "pll_p_out3_cclklp", "unused", "pll_x", 1283 "pll_x_out0" }; 1284static const char *sclk_parents[] = { "clk_m", "pll_c_out1", "pll_p_out4", 1285 "pll_p_out3", "pll_p_out2", "unused", 1286 "clk_32k", "pll_m_out1" }; 1287 1288static void __init tegra30_super_clk_init(void) 1289{ 1290 struct clk *clk; 1291 1292 /* 1293 * Clock input to cclk_g divided from pll_p using 1294 * U71 divider of cclk_g. 1295 */ 1296 clk = tegra_clk_register_divider("pll_p_cclkg", "pll_p", 1297 clk_base + SUPER_CCLKG_DIVIDER, 0, 1298 TEGRA_DIVIDER_INT, 16, 8, 1, NULL); 1299 clk_register_clkdev(clk, "pll_p_cclkg", NULL); 1300 1301 /* 1302 * Clock input to cclk_g divided from pll_p_out3 using 1303 * U71 divider of cclk_g. 1304 */ 1305 clk = tegra_clk_register_divider("pll_p_out3_cclkg", "pll_p_out3", 1306 clk_base + SUPER_CCLKG_DIVIDER, 0, 1307 TEGRA_DIVIDER_INT, 16, 8, 1, NULL); 1308 clk_register_clkdev(clk, "pll_p_out3_cclkg", NULL); 1309 1310 /* 1311 * Clock input to cclk_g divided from pll_p_out4 using 1312 * U71 divider of cclk_g. 1313 */ 1314 clk = tegra_clk_register_divider("pll_p_out4_cclkg", "pll_p_out4", 1315 clk_base + SUPER_CCLKG_DIVIDER, 0, 1316 TEGRA_DIVIDER_INT, 16, 8, 1, NULL); 1317 clk_register_clkdev(clk, "pll_p_out4_cclkg", NULL); 1318 1319 /* CCLKG */ 1320 clk = tegra_clk_register_super_mux("cclk_g", cclk_g_parents, 1321 ARRAY_SIZE(cclk_g_parents), 1322 CLK_SET_RATE_PARENT, 1323 clk_base + CCLKG_BURST_POLICY, 1324 0, 4, 0, 0, NULL); 1325 clk_register_clkdev(clk, "cclk_g", NULL); 1326 clks[cclk_g] = clk; 1327 1328 /* 1329 * Clock input to cclk_lp divided from pll_p using 1330 * U71 divider of cclk_lp. 1331 */ 1332 clk = tegra_clk_register_divider("pll_p_cclklp", "pll_p", 1333 clk_base + SUPER_CCLKLP_DIVIDER, 0, 1334 TEGRA_DIVIDER_INT, 16, 8, 1, NULL); 1335 clk_register_clkdev(clk, "pll_p_cclklp", NULL); 1336 1337 /* 1338 * Clock input to cclk_lp divided from pll_p_out3 using 1339 * U71 divider of cclk_lp. 1340 */ 1341 clk = tegra_clk_register_divider("pll_p_out3_cclklp", "pll_p_out3", 1342 clk_base + SUPER_CCLKG_DIVIDER, 0, 1343 TEGRA_DIVIDER_INT, 16, 8, 1, NULL); 1344 clk_register_clkdev(clk, "pll_p_out3_cclklp", NULL); 1345 1346 /* 1347 * Clock input to cclk_lp divided from pll_p_out4 using 1348 * U71 divider of cclk_lp. 1349 */ 1350 clk = tegra_clk_register_divider("pll_p_out4_cclklp", "pll_p_out4", 1351 clk_base + SUPER_CCLKLP_DIVIDER, 0, 1352 TEGRA_DIVIDER_INT, 16, 8, 1, NULL); 1353 clk_register_clkdev(clk, "pll_p_out4_cclklp", NULL); 1354 1355 /* CCLKLP */ 1356 clk = tegra_clk_register_super_mux("cclk_lp", cclk_lp_parents, 1357 ARRAY_SIZE(cclk_lp_parents), 1358 CLK_SET_RATE_PARENT, 1359 clk_base + CCLKLP_BURST_POLICY, 1360 TEGRA_DIVIDER_2, 4, 8, 9, 1361 NULL); 1362 clk_register_clkdev(clk, "cclk_lp", NULL); 1363 clks[cclk_lp] = clk; 1364 1365 /* SCLK */ 1366 clk = tegra_clk_register_super_mux("sclk", sclk_parents, 1367 ARRAY_SIZE(sclk_parents), 1368 CLK_SET_RATE_PARENT, 1369 clk_base + SCLK_BURST_POLICY, 1370 0, 4, 0, 0, NULL); 1371 clk_register_clkdev(clk, "sclk", NULL); 1372 clks[sclk] = clk; 1373 1374 /* HCLK */ 1375 clk = clk_register_divider(NULL, "hclk_div", "sclk", 0, 1376 clk_base + SYSTEM_CLK_RATE, 4, 2, 0, 1377 &sysrate_lock); 1378 clk = clk_register_gate(NULL, "hclk", "hclk_div", CLK_SET_RATE_PARENT, 1379 clk_base + SYSTEM_CLK_RATE, 7, 1380 CLK_GATE_SET_TO_DISABLE, &sysrate_lock); 1381 clk_register_clkdev(clk, "hclk", NULL); 1382 clks[hclk] = clk; 1383 1384 /* PCLK */ 1385 clk = clk_register_divider(NULL, "pclk_div", "hclk", 0, 1386 clk_base + SYSTEM_CLK_RATE, 0, 2, 0, 1387 &sysrate_lock); 1388 clk = clk_register_gate(NULL, "pclk", "pclk_div", CLK_SET_RATE_PARENT, 1389 clk_base + SYSTEM_CLK_RATE, 3, 1390 CLK_GATE_SET_TO_DISABLE, &sysrate_lock); 1391 clk_register_clkdev(clk, "pclk", NULL); 1392 clks[pclk] = clk; 1393 1394 /* twd */ 1395 clk = clk_register_fixed_factor(NULL, "twd", "cclk_g", 1396 CLK_SET_RATE_PARENT, 1, 2); 1397 clk_register_clkdev(clk, "twd", NULL); 1398 clks[twd] = clk; 1399} 1400 1401static const char *mux_pllacp_clkm[] = { "pll_a_out0", "unused", "pll_p", 1402 "clk_m" }; 1403static const char *mux_pllpcm_clkm[] = { "pll_p", "pll_c", "pll_m", "clk_m" }; 1404static const char *mux_pllmcp_clkm[] = { "pll_m", "pll_c", "pll_p", "clk_m" }; 1405static const char *i2s0_parents[] = { "pll_a_out0", "audio0_2x", "pll_p", 1406 "clk_m" }; 1407static const char *i2s1_parents[] = { "pll_a_out0", "audio1_2x", "pll_p", 1408 "clk_m" }; 1409static const char *i2s2_parents[] = { "pll_a_out0", "audio2_2x", "pll_p", 1410 "clk_m" }; 1411static const char *i2s3_parents[] = { "pll_a_out0", "audio3_2x", "pll_p", 1412 "clk_m" }; 1413static const char *i2s4_parents[] = { "pll_a_out0", "audio4_2x", "pll_p", 1414 "clk_m" }; 1415static const char *spdif_out_parents[] = { "pll_a_out0", "spdif_2x", "pll_p", 1416 "clk_m" }; 1417static const char *spdif_in_parents[] = { "pll_p", "pll_c", "pll_m" }; 1418static const char *mux_pllpc_clk32k_clkm[] = { "pll_p", "pll_c", "clk_32k", 1419 "clk_m" }; 1420static const char *mux_pllpc_clkm_clk32k[] = { "pll_p", "pll_c", "clk_m", 1421 "clk_32k" }; 1422static const char *mux_pllmcpa[] = { "pll_m", "pll_c", "pll_p", "pll_a_out0" }; 1423static const char *mux_pllpdc_clkm[] = { "pll_p", "pll_d_out0", "pll_c", 1424 "clk_m" }; 1425static const char *mux_pllp_clkm[] = { "pll_p", "unused", "unused", "clk_m" }; 1426static const char *mux_pllpmdacd2_clkm[] = { "pll_p", "pll_m", "pll_d_out0", 1427 "pll_a_out0", "pll_c", 1428 "pll_d2_out0", "clk_m" }; 1429static const char *mux_plla_clk32k_pllp_clkm_plle[] = { "pll_a_out0", 1430 "clk_32k", "pll_p", 1431 "clk_m", "pll_e" }; 1432static const char *mux_plld_out0_plld2_out0[] = { "pll_d_out0", 1433 "pll_d2_out0" }; 1434 1435static struct tegra_periph_init_data tegra_periph_clk_list[] = { 1436 TEGRA_INIT_DATA_MUX("i2s0", NULL, "tegra30-i2s.0", i2s0_parents, CLK_SOURCE_I2S0, 30, &periph_l_regs, TEGRA_PERIPH_ON_APB, i2s0), 1437 TEGRA_INIT_DATA_MUX("i2s1", NULL, "tegra30-i2s.1", i2s1_parents, CLK_SOURCE_I2S1, 11, &periph_l_regs, TEGRA_PERIPH_ON_APB, i2s1), 1438 TEGRA_INIT_DATA_MUX("i2s2", NULL, "tegra30-i2s.2", i2s2_parents, CLK_SOURCE_I2S2, 18, &periph_l_regs, TEGRA_PERIPH_ON_APB, i2s2), 1439 TEGRA_INIT_DATA_MUX("i2s3", NULL, "tegra30-i2s.3", i2s3_parents, CLK_SOURCE_I2S3, 101, &periph_v_regs, TEGRA_PERIPH_ON_APB, i2s3), 1440 TEGRA_INIT_DATA_MUX("i2s4", NULL, "tegra30-i2s.4", i2s4_parents, CLK_SOURCE_I2S4, 102, &periph_v_regs, TEGRA_PERIPH_ON_APB, i2s4), 1441 TEGRA_INIT_DATA_MUX("spdif_out", "spdif_out", "tegra30-spdif", spdif_out_parents, CLK_SOURCE_SPDIF_OUT, 10, &periph_l_regs, TEGRA_PERIPH_ON_APB, spdif_out), 1442 TEGRA_INIT_DATA_MUX("spdif_in", "spdif_in", "tegra30-spdif", spdif_in_parents, CLK_SOURCE_SPDIF_IN, 10, &periph_l_regs, TEGRA_PERIPH_ON_APB, spdif_in), 1443 TEGRA_INIT_DATA_MUX("d_audio", "d_audio", "tegra30-ahub", mux_pllacp_clkm, CLK_SOURCE_D_AUDIO, 106, &periph_v_regs, 0, d_audio), 1444 TEGRA_INIT_DATA_MUX("dam0", NULL, "tegra30-dam.0", mux_pllacp_clkm, CLK_SOURCE_DAM0, 108, &periph_v_regs, 0, dam0), 1445 TEGRA_INIT_DATA_MUX("dam1", NULL, "tegra30-dam.1", mux_pllacp_clkm, CLK_SOURCE_DAM1, 109, &periph_v_regs, 0, dam1), 1446 TEGRA_INIT_DATA_MUX("dam2", NULL, "tegra30-dam.2", mux_pllacp_clkm, CLK_SOURCE_DAM2, 110, &periph_v_regs, 0, dam2), 1447 TEGRA_INIT_DATA_MUX("hda", "hda", "tegra30-hda", mux_pllpcm_clkm, CLK_SOURCE_HDA, 125, &periph_v_regs, 0, hda), 1448 TEGRA_INIT_DATA_MUX("hda2codec_2x", "hda2codec", "tegra30-hda", mux_pllpcm_clkm, CLK_SOURCE_HDA2CODEC_2X, 111, &periph_v_regs, 0, hda2codec_2x), 1449 TEGRA_INIT_DATA_MUX("sbc1", NULL, "spi_tegra.0", mux_pllpcm_clkm, CLK_SOURCE_SBC1, 41, &periph_h_regs, TEGRA_PERIPH_ON_APB, sbc1), 1450 TEGRA_INIT_DATA_MUX("sbc2", NULL, "spi_tegra.1", mux_pllpcm_clkm, CLK_SOURCE_SBC2, 44, &periph_h_regs, TEGRA_PERIPH_ON_APB, sbc2), 1451 TEGRA_INIT_DATA_MUX("sbc3", NULL, "spi_tegra.2", mux_pllpcm_clkm, CLK_SOURCE_SBC3, 46, &periph_h_regs, TEGRA_PERIPH_ON_APB, sbc3), 1452 TEGRA_INIT_DATA_MUX("sbc4", NULL, "spi_tegra.3", mux_pllpcm_clkm, CLK_SOURCE_SBC4, 68, &periph_u_regs, TEGRA_PERIPH_ON_APB, sbc4), 1453 TEGRA_INIT_DATA_MUX("sbc5", NULL, "spi_tegra.4", mux_pllpcm_clkm, CLK_SOURCE_SBC5, 104, &periph_v_regs, TEGRA_PERIPH_ON_APB, sbc5), 1454 TEGRA_INIT_DATA_MUX("sbc6", NULL, "spi_tegra.5", mux_pllpcm_clkm, CLK_SOURCE_SBC6, 105, &periph_v_regs, TEGRA_PERIPH_ON_APB, sbc6), 1455 TEGRA_INIT_DATA_MUX("sata_oob", NULL, "tegra_sata_oob", mux_pllpcm_clkm, CLK_SOURCE_SATA_OOB, 123, &periph_v_regs, TEGRA_PERIPH_ON_APB, sata_oob), 1456 TEGRA_INIT_DATA_MUX("sata", NULL, "tegra_sata", mux_pllpcm_clkm, CLK_SOURCE_SATA, 124, &periph_v_regs, TEGRA_PERIPH_ON_APB, sata), 1457 TEGRA_INIT_DATA_MUX("ndflash", NULL, "tegra_nand", mux_pllpcm_clkm, CLK_SOURCE_NDFLASH, 13, &periph_l_regs, TEGRA_PERIPH_ON_APB, ndflash), 1458 TEGRA_INIT_DATA_MUX("ndspeed", NULL, "tegra_nand_speed", mux_pllpcm_clkm, CLK_SOURCE_NDSPEED, 80, &periph_u_regs, TEGRA_PERIPH_ON_APB, ndspeed), 1459 TEGRA_INIT_DATA_MUX("vfir", NULL, "vfir", mux_pllpcm_clkm, CLK_SOURCE_VFIR, 7, &periph_l_regs, TEGRA_PERIPH_ON_APB, vfir), 1460 TEGRA_INIT_DATA_MUX("csite", NULL, "csite", mux_pllpcm_clkm, CLK_SOURCE_CSITE, 73, &periph_u_regs, TEGRA_PERIPH_ON_APB, csite), 1461 TEGRA_INIT_DATA_MUX("la", NULL, "la", mux_pllpcm_clkm, CLK_SOURCE_LA, 76, &periph_u_regs, TEGRA_PERIPH_ON_APB, la), 1462 TEGRA_INIT_DATA_MUX("owr", NULL, "tegra_w1", mux_pllpcm_clkm, CLK_SOURCE_OWR, 71, &periph_u_regs, TEGRA_PERIPH_ON_APB, owr), 1463 TEGRA_INIT_DATA_MUX("mipi", NULL, "mipi", mux_pllpcm_clkm, CLK_SOURCE_MIPI, 50, &periph_h_regs, TEGRA_PERIPH_ON_APB, mipi), 1464 TEGRA_INIT_DATA_MUX("tsensor", NULL, "tegra-tsensor", mux_pllpc_clkm_clk32k, CLK_SOURCE_TSENSOR, 100, &periph_v_regs, TEGRA_PERIPH_ON_APB, tsensor), 1465 TEGRA_INIT_DATA_MUX("i2cslow", NULL, "i2cslow", mux_pllpc_clk32k_clkm, CLK_SOURCE_I2CSLOW, 81, &periph_u_regs, TEGRA_PERIPH_ON_APB, i2cslow), 1466 TEGRA_INIT_DATA_INT("vde", NULL, "vde", mux_pllpcm_clkm, CLK_SOURCE_VDE, 61, &periph_h_regs, 0, vde), 1467 TEGRA_INIT_DATA_INT("vi", "vi", "tegra_camera", mux_pllmcpa, CLK_SOURCE_VI, 20, &periph_l_regs, 0, vi), 1468 TEGRA_INIT_DATA_INT("epp", NULL, "epp", mux_pllmcpa, CLK_SOURCE_EPP, 19, &periph_l_regs, 0, epp), 1469 TEGRA_INIT_DATA_INT("mpe", NULL, "mpe", mux_pllmcpa, CLK_SOURCE_MPE, 60, &periph_h_regs, 0, mpe), 1470 TEGRA_INIT_DATA_INT("host1x", NULL, "host1x", mux_pllmcpa, CLK_SOURCE_HOST1X, 28, &periph_l_regs, 0, host1x), 1471 TEGRA_INIT_DATA_INT("3d", NULL, "3d", mux_pllmcpa, CLK_SOURCE_3D, 24, &periph_l_regs, TEGRA_PERIPH_MANUAL_RESET, gr3d), 1472 TEGRA_INIT_DATA_INT("3d2", NULL, "3d2", mux_pllmcpa, CLK_SOURCE_3D2, 98, &periph_v_regs, TEGRA_PERIPH_MANUAL_RESET, gr3d2), 1473 TEGRA_INIT_DATA_INT("2d", NULL, "2d", mux_pllmcpa, CLK_SOURCE_2D, 21, &periph_l_regs, 0, gr2d), 1474 TEGRA_INIT_DATA_INT("se", NULL, "se", mux_pllpcm_clkm, CLK_SOURCE_SE, 127, &periph_v_regs, 0, se), 1475 TEGRA_INIT_DATA_MUX("mselect", NULL, "mselect", mux_pllp_clkm, CLK_SOURCE_MSELECT, 99, &periph_v_regs, 0, mselect), 1476 TEGRA_INIT_DATA_MUX("nor", NULL, "tegra-nor", mux_pllpcm_clkm, CLK_SOURCE_NOR, 42, &periph_h_regs, 0, nor), 1477 TEGRA_INIT_DATA_MUX("sdmmc1", NULL, "sdhci-tegra.0", mux_pllpcm_clkm, CLK_SOURCE_SDMMC1, 14, &periph_l_regs, 0, sdmmc1), 1478 TEGRA_INIT_DATA_MUX("sdmmc2", NULL, "sdhci-tegra.1", mux_pllpcm_clkm, CLK_SOURCE_SDMMC2, 9, &periph_l_regs, 0, sdmmc2), 1479 TEGRA_INIT_DATA_MUX("sdmmc3", NULL, "sdhci-tegra.2", mux_pllpcm_clkm, CLK_SOURCE_SDMMC3, 69, &periph_u_regs, 0, sdmmc3), 1480 TEGRA_INIT_DATA_MUX("sdmmc4", NULL, "sdhci-tegra.3", mux_pllpcm_clkm, CLK_SOURCE_SDMMC4, 15, &periph_l_regs, 0, sdmmc4), 1481 TEGRA_INIT_DATA_MUX("cve", NULL, "cve", mux_pllpdc_clkm, CLK_SOURCE_CVE, 49, &periph_h_regs, 0, cve), 1482 TEGRA_INIT_DATA_MUX("tvo", NULL, "tvo", mux_pllpdc_clkm, CLK_SOURCE_TVO, 49, &periph_h_regs, 0, tvo), 1483 TEGRA_INIT_DATA_MUX("tvdac", NULL, "tvdac", mux_pllpdc_clkm, CLK_SOURCE_TVDAC, 53, &periph_h_regs, 0, tvdac), 1484 TEGRA_INIT_DATA_MUX("actmon", NULL, "actmon", mux_pllpc_clk32k_clkm, CLK_SOURCE_ACTMON, 119, &periph_v_regs, 0, actmon), 1485 TEGRA_INIT_DATA_MUX("vi_sensor", "vi_sensor", "tegra_camera", mux_pllmcpa, CLK_SOURCE_VI_SENSOR, 20, &periph_l_regs, TEGRA_PERIPH_NO_RESET, vi_sensor), 1486 TEGRA_INIT_DATA_DIV16("i2c1", "div-clk", "tegra-i2c.0", mux_pllp_clkm, CLK_SOURCE_I2C1, 12, &periph_l_regs, TEGRA_PERIPH_ON_APB, i2c1), 1487 TEGRA_INIT_DATA_DIV16("i2c2", "div-clk", "tegra-i2c.1", mux_pllp_clkm, CLK_SOURCE_I2C2, 54, &periph_h_regs, TEGRA_PERIPH_ON_APB, i2c2), 1488 TEGRA_INIT_DATA_DIV16("i2c3", "div-clk", "tegra-i2c.2", mux_pllp_clkm, CLK_SOURCE_I2C3, 67, &periph_u_regs, TEGRA_PERIPH_ON_APB, i2c3), 1489 TEGRA_INIT_DATA_DIV16("i2c4", "div-clk", "tegra-i2c.3", mux_pllp_clkm, CLK_SOURCE_I2C4, 103, &periph_v_regs, TEGRA_PERIPH_ON_APB, i2c4), 1490 TEGRA_INIT_DATA_DIV16("i2c5", "div-clk", "tegra-i2c.4", mux_pllp_clkm, CLK_SOURCE_I2C5, 47, &periph_h_regs, TEGRA_PERIPH_ON_APB, i2c5), 1491 TEGRA_INIT_DATA_UART("uarta", NULL, "tegra_uart.0", mux_pllpcm_clkm, CLK_SOURCE_UARTA, 6, &periph_l_regs, uarta), 1492 TEGRA_INIT_DATA_UART("uartb", NULL, "tegra_uart.1", mux_pllpcm_clkm, CLK_SOURCE_UARTB, 7, &periph_l_regs, uartb), 1493 TEGRA_INIT_DATA_UART("uartc", NULL, "tegra_uart.2", mux_pllpcm_clkm, CLK_SOURCE_UARTC, 55, &periph_h_regs, uartc), 1494 TEGRA_INIT_DATA_UART("uartd", NULL, "tegra_uart.3", mux_pllpcm_clkm, CLK_SOURCE_UARTD, 65, &periph_u_regs, uartd), 1495 TEGRA_INIT_DATA_UART("uarte", NULL, "tegra_uart.4", mux_pllpcm_clkm, CLK_SOURCE_UARTE, 66, &periph_u_regs, uarte), 1496 TEGRA_INIT_DATA_MUX8("hdmi", NULL, "hdmi", mux_pllpmdacd2_clkm, CLK_SOURCE_HDMI, 51, &periph_h_regs, 0, hdmi), 1497 TEGRA_INIT_DATA_MUX8("extern1", NULL, "extern1", mux_plla_clk32k_pllp_clkm_plle, CLK_SOURCE_EXTERN1, 120, &periph_v_regs, 0, extern1), 1498 TEGRA_INIT_DATA_MUX8("extern2", NULL, "extern2", mux_plla_clk32k_pllp_clkm_plle, CLK_SOURCE_EXTERN2, 121, &periph_v_regs, 0, extern2), 1499 TEGRA_INIT_DATA_MUX8("extern3", NULL, "extern3", mux_plla_clk32k_pllp_clkm_plle, CLK_SOURCE_EXTERN3, 122, &periph_v_regs, 0, extern3), 1500 TEGRA_INIT_DATA("pwm", NULL, "pwm", mux_pllpc_clk32k_clkm, CLK_SOURCE_PWM, 28, 2, 0, 0, 8, 1, 0, &periph_l_regs, 17, periph_clk_enb_refcnt, 0, pwm), 1501}; 1502 1503static struct tegra_periph_init_data tegra_periph_nodiv_clk_list[] = { 1504 TEGRA_INIT_DATA_NODIV("disp1", NULL, "tegradc.0", mux_pllpmdacd2_clkm, CLK_SOURCE_DISP1, 29, 3, 27, &periph_l_regs, 0, disp1), 1505 TEGRA_INIT_DATA_NODIV("disp2", NULL, "tegradc.1", mux_pllpmdacd2_clkm, CLK_SOURCE_DISP2, 29, 3, 26, &periph_l_regs, 0, disp2), 1506 TEGRA_INIT_DATA_NODIV("dsib", NULL, "tegradc.1", mux_plld_out0_plld2_out0, CLK_SOURCE_DSIB, 25, 1, 82, &periph_u_regs, 0, dsib), 1507}; 1508 1509static void __init tegra30_periph_clk_init(void) 1510{ 1511 struct tegra_periph_init_data *data; 1512 struct clk *clk; 1513 int i; 1514 1515 /* apbdma */ 1516 clk = tegra_clk_register_periph_gate("apbdma", "clk_m", 0, clk_base, 0, 34, 1517 &periph_h_regs, periph_clk_enb_refcnt); 1518 clk_register_clkdev(clk, NULL, "tegra-apbdma"); 1519 clks[apbdma] = clk; 1520 1521 /* rtc */ 1522 clk = tegra_clk_register_periph_gate("rtc", "clk_32k", 1523 TEGRA_PERIPH_NO_RESET | TEGRA_PERIPH_ON_APB, 1524 clk_base, 0, 4, &periph_l_regs, 1525 periph_clk_enb_refcnt); 1526 clk_register_clkdev(clk, NULL, "rtc-tegra"); 1527 clks[rtc] = clk; 1528 1529 /* timer */ 1530 clk = tegra_clk_register_periph_gate("timer", "clk_m", 0, clk_base, 0, 1531 5, &periph_l_regs, periph_clk_enb_refcnt); 1532 clk_register_clkdev(clk, NULL, "timer"); 1533 clks[timer] = clk; 1534 1535 /* kbc */ 1536 clk = tegra_clk_register_periph_gate("kbc", "clk_32k", 1537 TEGRA_PERIPH_NO_RESET | TEGRA_PERIPH_ON_APB, 1538 clk_base, 0, 36, &periph_h_regs, 1539 periph_clk_enb_refcnt); 1540 clk_register_clkdev(clk, NULL, "tegra-kbc"); 1541 clks[kbc] = clk; 1542 1543 /* csus */ 1544 clk = tegra_clk_register_periph_gate("csus", "clk_m", 1545 TEGRA_PERIPH_NO_RESET | TEGRA_PERIPH_ON_APB, 1546 clk_base, 0, 92, &periph_u_regs, 1547 periph_clk_enb_refcnt); 1548 clk_register_clkdev(clk, "csus", "tengra_camera"); 1549 clks[csus] = clk; 1550 1551 /* vcp */ 1552 clk = tegra_clk_register_periph_gate("vcp", "clk_m", 0, clk_base, 0, 29, 1553 &periph_l_regs, periph_clk_enb_refcnt); 1554 clk_register_clkdev(clk, "vcp", "tegra-avp"); 1555 clks[vcp] = clk; 1556 1557 /* bsea */ 1558 clk = tegra_clk_register_periph_gate("bsea", "clk_m", 0, clk_base, 0, 1559 62, &periph_h_regs, periph_clk_enb_refcnt); 1560 clk_register_clkdev(clk, "bsea", "tegra-avp"); 1561 clks[bsea] = clk; 1562 1563 /* bsev */ 1564 clk = tegra_clk_register_periph_gate("bsev", "clk_m", 0, clk_base, 0, 1565 63, &periph_h_regs, periph_clk_enb_refcnt); 1566 clk_register_clkdev(clk, "bsev", "tegra-aes"); 1567 clks[bsev] = clk; 1568 1569 /* usbd */ 1570 clk = tegra_clk_register_periph_gate("usbd", "clk_m", 0, clk_base, 0, 1571 22, &periph_l_regs, periph_clk_enb_refcnt); 1572 clk_register_clkdev(clk, NULL, "fsl-tegra-udc"); 1573 clks[usbd] = clk; 1574 1575 /* usb2 */ 1576 clk = tegra_clk_register_periph_gate("usb2", "clk_m", 0, clk_base, 0, 1577 58, &periph_h_regs, periph_clk_enb_refcnt); 1578 clk_register_clkdev(clk, NULL, "tegra-ehci.1"); 1579 clks[usb2] = clk; 1580 1581 /* usb3 */ 1582 clk = tegra_clk_register_periph_gate("usb3", "clk_m", 0, clk_base, 0, 1583 59, &periph_h_regs, periph_clk_enb_refcnt); 1584 clk_register_clkdev(clk, NULL, "tegra-ehci.2"); 1585 clks[usb3] = clk; 1586 1587 /* dsia */ 1588 clk = tegra_clk_register_periph_gate("dsia", "pll_d_out0", 0, clk_base, 1589 0, 48, &periph_h_regs, 1590 periph_clk_enb_refcnt); 1591 clk_register_clkdev(clk, "dsia", "tegradc.0"); 1592 clks[dsia] = clk; 1593 1594 /* csi */ 1595 clk = tegra_clk_register_periph_gate("csi", "pll_p_out3", 0, clk_base, 1596 0, 52, &periph_h_regs, 1597 periph_clk_enb_refcnt); 1598 clk_register_clkdev(clk, "csi", "tegra_camera"); 1599 clks[csi] = clk; 1600 1601 /* isp */ 1602 clk = tegra_clk_register_periph_gate("isp", "clk_m", 0, clk_base, 0, 23, 1603 &periph_l_regs, periph_clk_enb_refcnt); 1604 clk_register_clkdev(clk, "isp", "tegra_camera"); 1605 clks[isp] = clk; 1606 1607 /* pcie */ 1608 clk = tegra_clk_register_periph_gate("pcie", "clk_m", 0, clk_base, 0, 1609 70, &periph_u_regs, periph_clk_enb_refcnt); 1610 clk_register_clkdev(clk, "pcie", "tegra-pcie"); 1611 clks[pcie] = clk; 1612 1613 /* afi */ 1614 clk = tegra_clk_register_periph_gate("afi", "clk_m", 0, clk_base, 0, 72, 1615 &periph_u_regs, periph_clk_enb_refcnt); 1616 clk_register_clkdev(clk, "afi", "tegra-pcie"); 1617 clks[afi] = clk; 1618 1619 /* kfuse */ 1620 clk = tegra_clk_register_periph_gate("kfuse", "clk_m", 1621 TEGRA_PERIPH_ON_APB, 1622 clk_base, 0, 40, &periph_h_regs, 1623 periph_clk_enb_refcnt); 1624 clk_register_clkdev(clk, NULL, "kfuse-tegra"); 1625 clks[kfuse] = clk; 1626 1627 /* fuse */ 1628 clk = tegra_clk_register_periph_gate("fuse", "clk_m", 1629 TEGRA_PERIPH_ON_APB, 1630 clk_base, 0, 39, &periph_h_regs, 1631 periph_clk_enb_refcnt); 1632 clk_register_clkdev(clk, "fuse", "fuse-tegra"); 1633 clks[fuse] = clk; 1634 1635 /* fuse_burn */ 1636 clk = tegra_clk_register_periph_gate("fuse_burn", "clk_m", 1637 TEGRA_PERIPH_ON_APB, 1638 clk_base, 0, 39, &periph_h_regs, 1639 periph_clk_enb_refcnt); 1640 clk_register_clkdev(clk, "fuse_burn", "fuse-tegra"); 1641 clks[fuse_burn] = clk; 1642 1643 /* apbif */ 1644 clk = tegra_clk_register_periph_gate("apbif", "clk_m", 0, 1645 clk_base, 0, 107, &periph_v_regs, 1646 periph_clk_enb_refcnt); 1647 clk_register_clkdev(clk, "apbif", "tegra30-ahub"); 1648 clks[apbif] = clk; 1649 1650 /* hda2hdmi */ 1651 clk = tegra_clk_register_periph_gate("hda2hdmi", "clk_m", 1652 TEGRA_PERIPH_ON_APB, 1653 clk_base, 0, 128, &periph_w_regs, 1654 periph_clk_enb_refcnt); 1655 clk_register_clkdev(clk, "hda2hdmi", "tegra30-hda"); 1656 clks[hda2hdmi] = clk; 1657 1658 /* sata_cold */ 1659 clk = tegra_clk_register_periph_gate("sata_cold", "clk_m", 1660 TEGRA_PERIPH_ON_APB, 1661 clk_base, 0, 129, &periph_w_regs, 1662 periph_clk_enb_refcnt); 1663 clk_register_clkdev(clk, NULL, "tegra_sata_cold"); 1664 clks[sata_cold] = clk; 1665 1666 /* dtv */ 1667 clk = tegra_clk_register_periph_gate("dtv", "clk_m", 1668 TEGRA_PERIPH_ON_APB, 1669 clk_base, 0, 79, &periph_u_regs, 1670 periph_clk_enb_refcnt); 1671 clk_register_clkdev(clk, NULL, "dtv"); 1672 clks[dtv] = clk; 1673 1674 /* emc */ 1675 clk = clk_register_mux(NULL, "emc_mux", mux_pllmcp_clkm, 1676 ARRAY_SIZE(mux_pllmcp_clkm), 0, 1677 clk_base + CLK_SOURCE_EMC, 1678 30, 2, 0, NULL); 1679 clk = tegra_clk_register_periph_gate("emc", "emc_mux", 0, clk_base, 0, 1680 57, &periph_h_regs, periph_clk_enb_refcnt); 1681 clk_register_clkdev(clk, "emc", NULL); 1682 clks[emc] = clk; 1683 1684 for (i = 0; i < ARRAY_SIZE(tegra_periph_clk_list); i++) { 1685 data = &tegra_periph_clk_list[i]; 1686 clk = tegra_clk_register_periph(data->name, data->parent_names, 1687 data->num_parents, &data->periph, 1688 clk_base, data->offset, data->flags); 1689 clk_register_clkdev(clk, data->con_id, data->dev_id); 1690 clks[data->clk_id] = clk; 1691 } 1692 1693 for (i = 0; i < ARRAY_SIZE(tegra_periph_nodiv_clk_list); i++) { 1694 data = &tegra_periph_nodiv_clk_list[i]; 1695 clk = tegra_clk_register_periph_nodiv(data->name, 1696 data->parent_names, 1697 data->num_parents, &data->periph, 1698 clk_base, data->offset); 1699 clk_register_clkdev(clk, data->con_id, data->dev_id); 1700 clks[data->clk_id] = clk; 1701 } 1702} 1703 1704static void __init tegra30_fixed_clk_init(void) 1705{ 1706 struct clk *clk; 1707 1708 /* clk_32k */ 1709 clk = clk_register_fixed_rate(NULL, "clk_32k", NULL, CLK_IS_ROOT, 1710 32768); 1711 clk_register_clkdev(clk, "clk_32k", NULL); 1712 clks[clk_32k] = clk; 1713 1714 /* clk_m_div2 */ 1715 clk = clk_register_fixed_factor(NULL, "clk_m_div2", "clk_m", 1716 CLK_SET_RATE_PARENT, 1, 2); 1717 clk_register_clkdev(clk, "clk_m_div2", NULL); 1718 clks[clk_m_div2] = clk; 1719 1720 /* clk_m_div4 */ 1721 clk = clk_register_fixed_factor(NULL, "clk_m_div4", "clk_m", 1722 CLK_SET_RATE_PARENT, 1, 4); 1723 clk_register_clkdev(clk, "clk_m_div4", NULL); 1724 clks[clk_m_div4] = clk; 1725 1726 /* cml0 */ 1727 clk = clk_register_gate(NULL, "cml0", "pll_e", 0, clk_base + PLLE_AUX, 1728 0, 0, &cml_lock); 1729 clk_register_clkdev(clk, "cml0", NULL); 1730 clks[cml0] = clk; 1731 1732 /* cml1 */ 1733 clk = clk_register_gate(NULL, "cml1", "pll_e", 0, clk_base + PLLE_AUX, 1734 1, 0, &cml_lock); 1735 clk_register_clkdev(clk, "cml1", NULL); 1736 clks[cml1] = clk; 1737 1738 /* pciex */ 1739 clk = clk_register_fixed_rate(NULL, "pciex", "pll_e", 0, 100000000); 1740 clk_register_clkdev(clk, "pciex", NULL); 1741 clks[pciex] = clk; 1742} 1743 1744static void __init tegra30_osc_clk_init(void) 1745{ 1746 struct clk *clk; 1747 unsigned int pll_ref_div; 1748 1749 tegra30_clk_measure_input_freq(); 1750 1751 /* clk_m */ 1752 clk = clk_register_fixed_rate(NULL, "clk_m", NULL, CLK_IS_ROOT, 1753 input_freq); 1754 clk_register_clkdev(clk, "clk_m", NULL); 1755 clks[clk_m] = clk; 1756 1757 /* pll_ref */ 1758 pll_ref_div = tegra30_get_pll_ref_div(); 1759 clk = clk_register_fixed_factor(NULL, "pll_ref", "clk_m", 1760 CLK_SET_RATE_PARENT, 1, pll_ref_div); 1761 clk_register_clkdev(clk, "pll_ref", NULL); 1762 clks[pll_ref] = clk; 1763} 1764 1765/* Tegra30 CPU clock and reset control functions */ 1766static void tegra30_wait_cpu_in_reset(u32 cpu) 1767{ 1768 unsigned int reg; 1769 1770 do { 1771 reg = readl(clk_base + 1772 TEGRA30_CLK_RST_CONTROLLER_CPU_CMPLX_STATUS); 1773 cpu_relax(); 1774 } while (!(reg & (1 << cpu))); /* check CPU been reset or not */ 1775 1776 return; 1777} 1778 1779static void tegra30_put_cpu_in_reset(u32 cpu) 1780{ 1781 writel(CPU_RESET(cpu), 1782 clk_base + TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET); 1783 dmb(); 1784} 1785 1786static void tegra30_cpu_out_of_reset(u32 cpu) 1787{ 1788 writel(CPU_RESET(cpu), 1789 clk_base + TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR); 1790 wmb(); 1791} 1792 1793 1794static void tegra30_enable_cpu_clock(u32 cpu) 1795{ 1796 unsigned int reg; 1797 1798 writel(CPU_CLOCK(cpu), 1799 clk_base + TEGRA30_CLK_RST_CONTROLLER_CLK_CPU_CMPLX_CLR); 1800 reg = readl(clk_base + 1801 TEGRA30_CLK_RST_CONTROLLER_CLK_CPU_CMPLX_CLR); 1802} 1803 1804static void tegra30_disable_cpu_clock(u32 cpu) 1805{ 1806 1807 unsigned int reg; 1808 1809 reg = readl(clk_base + TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX); 1810 writel(reg | CPU_CLOCK(cpu), 1811 clk_base + TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX); 1812} 1813 1814#ifdef CONFIG_PM_SLEEP 1815static bool tegra30_cpu_rail_off_ready(void) 1816{ 1817 unsigned int cpu_rst_status; 1818 int cpu_pwr_status; 1819 1820 cpu_rst_status = readl(clk_base + 1821 TEGRA30_CLK_RST_CONTROLLER_CPU_CMPLX_STATUS); 1822 cpu_pwr_status = tegra_powergate_is_powered(TEGRA_POWERGATE_CPU1) || 1823 tegra_powergate_is_powered(TEGRA_POWERGATE_CPU2) || 1824 tegra_powergate_is_powered(TEGRA_POWERGATE_CPU3); 1825 1826 if (((cpu_rst_status & 0xE) != 0xE) || cpu_pwr_status) 1827 return false; 1828 1829 return true; 1830} 1831 1832static void tegra30_cpu_clock_suspend(void) 1833{ 1834 /* switch coresite to clk_m, save off original source */ 1835 tegra30_cpu_clk_sctx.clk_csite_src = 1836 readl(clk_base + CLK_RESET_SOURCE_CSITE); 1837 writel(3<<30, clk_base + CLK_RESET_SOURCE_CSITE); 1838 1839 tegra30_cpu_clk_sctx.cpu_burst = 1840 readl(clk_base + CLK_RESET_CCLK_BURST); 1841 tegra30_cpu_clk_sctx.pllx_base = 1842 readl(clk_base + CLK_RESET_PLLX_BASE); 1843 tegra30_cpu_clk_sctx.pllx_misc = 1844 readl(clk_base + CLK_RESET_PLLX_MISC); 1845 tegra30_cpu_clk_sctx.cclk_divider = 1846 readl(clk_base + CLK_RESET_CCLK_DIVIDER); 1847} 1848 1849static void tegra30_cpu_clock_resume(void) 1850{ 1851 unsigned int reg, policy; 1852 1853 /* Is CPU complex already running on PLLX? */ 1854 reg = readl(clk_base + CLK_RESET_CCLK_BURST); 1855 policy = (reg >> CLK_RESET_CCLK_BURST_POLICY_SHIFT) & 0xF; 1856 1857 if (policy == CLK_RESET_CCLK_IDLE_POLICY) 1858 reg = (reg >> CLK_RESET_CCLK_IDLE_POLICY_SHIFT) & 0xF; 1859 else if (policy == CLK_RESET_CCLK_RUN_POLICY) 1860 reg = (reg >> CLK_RESET_CCLK_RUN_POLICY_SHIFT) & 0xF; 1861 else 1862 BUG(); 1863 1864 if (reg != CLK_RESET_CCLK_BURST_POLICY_PLLX) { 1865 /* restore PLLX settings if CPU is on different PLL */ 1866 writel(tegra30_cpu_clk_sctx.pllx_misc, 1867 clk_base + CLK_RESET_PLLX_MISC); 1868 writel(tegra30_cpu_clk_sctx.pllx_base, 1869 clk_base + CLK_RESET_PLLX_BASE); 1870 1871 /* wait for PLL stabilization if PLLX was enabled */ 1872 if (tegra30_cpu_clk_sctx.pllx_base & (1 << 30)) 1873 udelay(300); 1874 } 1875 1876 /* 1877 * Restore original burst policy setting for calls resulting from CPU 1878 * LP2 in idle or system suspend. 1879 */ 1880 writel(tegra30_cpu_clk_sctx.cclk_divider, 1881 clk_base + CLK_RESET_CCLK_DIVIDER); 1882 writel(tegra30_cpu_clk_sctx.cpu_burst, 1883 clk_base + CLK_RESET_CCLK_BURST); 1884 1885 writel(tegra30_cpu_clk_sctx.clk_csite_src, 1886 clk_base + CLK_RESET_SOURCE_CSITE); 1887} 1888#endif 1889 1890static struct tegra_cpu_car_ops tegra30_cpu_car_ops = { 1891 .wait_for_reset = tegra30_wait_cpu_in_reset, 1892 .put_in_reset = tegra30_put_cpu_in_reset, 1893 .out_of_reset = tegra30_cpu_out_of_reset, 1894 .enable_clock = tegra30_enable_cpu_clock, 1895 .disable_clock = tegra30_disable_cpu_clock, 1896#ifdef CONFIG_PM_SLEEP 1897 .rail_off_ready = tegra30_cpu_rail_off_ready, 1898 .suspend = tegra30_cpu_clock_suspend, 1899 .resume = tegra30_cpu_clock_resume, 1900#endif 1901}; 1902 1903static __initdata struct tegra_clk_init_table init_table[] = { 1904 {uarta, pll_p, 408000000, 0}, 1905 {uartb, pll_p, 408000000, 0}, 1906 {uartc, pll_p, 408000000, 0}, 1907 {uartd, pll_p, 408000000, 0}, 1908 {uarte, pll_p, 408000000, 0}, 1909 {pll_a, clk_max, 564480000, 1}, 1910 {pll_a_out0, clk_max, 11289600, 1}, 1911 {extern1, pll_a_out0, 0, 1}, 1912 {clk_out_1_mux, extern1, 0, 0}, 1913 {clk_out_1, clk_max, 0, 1}, 1914 {blink, clk_max, 0, 1}, 1915 {i2s0, pll_a_out0, 11289600, 0}, 1916 {i2s1, pll_a_out0, 11289600, 0}, 1917 {i2s2, pll_a_out0, 11289600, 0}, 1918 {i2s3, pll_a_out0, 11289600, 0}, 1919 {i2s4, pll_a_out0, 11289600, 0}, 1920 {sdmmc1, pll_p, 48000000, 0}, 1921 {sdmmc2, pll_p, 48000000, 0}, 1922 {sdmmc3, pll_p, 48000000, 0}, 1923 {pll_m, clk_max, 0, 1}, 1924 {pclk, clk_max, 0, 1}, 1925 {csite, clk_max, 0, 1}, 1926 {emc, clk_max, 0, 1}, 1927 {mselect, clk_max, 0, 1}, 1928 {sbc1, pll_p, 100000000, 0}, 1929 {sbc2, pll_p, 100000000, 0}, 1930 {sbc3, pll_p, 100000000, 0}, 1931 {sbc4, pll_p, 100000000, 0}, 1932 {sbc5, pll_p, 100000000, 0}, 1933 {sbc6, pll_p, 100000000, 0}, 1934 {host1x, pll_c, 150000000, 0}, 1935 {disp1, pll_p, 600000000, 0}, 1936 {disp2, pll_p, 600000000, 0}, 1937 {twd, clk_max, 0, 1}, 1938 {gr2d, pll_c, 300000000, 0}, 1939 {gr3d, pll_c, 300000000, 0}, 1940 {clk_max, clk_max, 0, 0}, /* This MUST be the last entry. */ 1941}; 1942 1943static void __init tegra30_clock_apply_init_table(void) 1944{ 1945 tegra_init_from_table(init_table, clks, clk_max); 1946} 1947 1948/* 1949 * Some clocks may be used by different drivers depending on the board 1950 * configuration. List those here to register them twice in the clock lookup 1951 * table under two names. 1952 */ 1953static struct tegra_clk_duplicate tegra_clk_duplicates[] = { 1954 TEGRA_CLK_DUPLICATE(usbd, "utmip-pad", NULL), 1955 TEGRA_CLK_DUPLICATE(usbd, "tegra-ehci.0", NULL), 1956 TEGRA_CLK_DUPLICATE(usbd, "tegra-otg", NULL), 1957 TEGRA_CLK_DUPLICATE(bsev, "tegra-avp", "bsev"), 1958 TEGRA_CLK_DUPLICATE(bsev, "nvavp", "bsev"), 1959 TEGRA_CLK_DUPLICATE(vde, "tegra-aes", "vde"), 1960 TEGRA_CLK_DUPLICATE(bsea, "tegra-aes", "bsea"), 1961 TEGRA_CLK_DUPLICATE(bsea, "nvavp", "bsea"), 1962 TEGRA_CLK_DUPLICATE(cml1, "tegra_sata_cml", NULL), 1963 TEGRA_CLK_DUPLICATE(cml0, "tegra_pcie", "cml"), 1964 TEGRA_CLK_DUPLICATE(pciex, "tegra_pcie", "pciex"), 1965 TEGRA_CLK_DUPLICATE(vcp, "nvavp", "vcp"), 1966 TEGRA_CLK_DUPLICATE(clk_max, NULL, NULL), /* MUST be the last entry */ 1967}; 1968 1969static const struct of_device_id pmc_match[] __initconst = { 1970 { .compatible = "nvidia,tegra30-pmc" }, 1971 {}, 1972}; 1973 1974static void __init tegra30_clock_init(struct device_node *np) 1975{ 1976 struct device_node *node; 1977 int i; 1978 1979 clk_base = of_iomap(np, 0); 1980 if (!clk_base) { 1981 pr_err("ioremap tegra30 CAR failed\n"); 1982 return; 1983 } 1984 1985 node = of_find_matching_node(NULL, pmc_match); 1986 if (!node) { 1987 pr_err("Failed to find pmc node\n"); 1988 BUG(); 1989 } 1990 1991 pmc_base = of_iomap(node, 0); 1992 if (!pmc_base) { 1993 pr_err("Can't map pmc registers\n"); 1994 BUG(); 1995 } 1996 1997 tegra30_osc_clk_init(); 1998 tegra30_fixed_clk_init(); 1999 tegra30_pll_init(); 2000 tegra30_super_clk_init(); 2001 tegra30_periph_clk_init(); 2002 tegra30_audio_clk_init(); 2003 tegra30_pmc_clk_init(); 2004 2005 for (i = 0; i < ARRAY_SIZE(clks); i++) { 2006 if (IS_ERR(clks[i])) { 2007 pr_err("Tegra30 clk %d: register failed with %ld\n", 2008 i, PTR_ERR(clks[i])); 2009 BUG(); 2010 } 2011 if (!clks[i]) 2012 clks[i] = ERR_PTR(-EINVAL); 2013 } 2014 2015 tegra_init_dup_clks(tegra_clk_duplicates, clks, clk_max); 2016 2017 clk_data.clks = clks; 2018 clk_data.clk_num = ARRAY_SIZE(clks); 2019 of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data); 2020 2021 tegra_clk_apply_init_table = tegra30_clock_apply_init_table; 2022 2023 tegra_cpu_car_ops = &tegra30_cpu_car_ops; 2024} 2025CLK_OF_DECLARE(tegra30, "nvidia,tegra30-car", tegra30_clock_init); 2026