clk.h revision 0b6525acd13f2d33cd3be86d0dbd2ddd1ffeda8f
1/* 2 * Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved. 3 * 4 * This program is free software; you can redistribute it and/or modify it 5 * under the terms and conditions of the GNU General Public License, 6 * version 2, as published by the Free Software Foundation. 7 * 8 * This program is distributed in the hope it will be useful, but WITHOUT 9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 11 * more details. 12 * 13 * You should have received a copy of the GNU General Public License 14 * along with this program. If not, see <http://www.gnu.org/licenses/>. 15 */ 16 17#ifndef __TEGRA_CLK_H 18#define __TEGRA_CLK_H 19 20#include <linux/clk-provider.h> 21#include <linux/clkdev.h> 22 23/** 24 * struct tegra_clk_sync_source - external clock source from codec 25 * 26 * @hw: handle between common and hardware-specific interfaces 27 * @rate: input frequency from source 28 * @max_rate: max rate allowed 29 */ 30struct tegra_clk_sync_source { 31 struct clk_hw hw; 32 unsigned long rate; 33 unsigned long max_rate; 34}; 35 36#define to_clk_sync_source(_hw) \ 37 container_of(_hw, struct tegra_clk_sync_source, hw) 38 39extern const struct clk_ops tegra_clk_sync_source_ops; 40struct clk *tegra_clk_register_sync_source(const char *name, 41 unsigned long fixed_rate, unsigned long max_rate); 42 43/** 44 * struct tegra_clk_frac_div - fractional divider clock 45 * 46 * @hw: handle between common and hardware-specific interfaces 47 * @reg: register containing divider 48 * @flags: hardware-specific flags 49 * @shift: shift to the divider bit field 50 * @width: width of the divider bit field 51 * @frac_width: width of the fractional bit field 52 * @lock: register lock 53 * 54 * Flags: 55 * TEGRA_DIVIDER_ROUND_UP - This flags indicates to round up the divider value. 56 * TEGRA_DIVIDER_FIXED - Fixed rate PLL dividers has addition override bit, this 57 * flag indicates that this divider is for fixed rate PLL. 58 * TEGRA_DIVIDER_INT - Some modules can not cope with the duty cycle when 59 * fraction bit is set. This flags indicates to calculate divider for which 60 * fracton bit will be zero. 61 * TEGRA_DIVIDER_UART - UART module divider has additional enable bit which is 62 * set when divider value is not 0. This flags indicates that the divider 63 * is for UART module. 64 */ 65struct tegra_clk_frac_div { 66 struct clk_hw hw; 67 void __iomem *reg; 68 u8 flags; 69 u8 shift; 70 u8 width; 71 u8 frac_width; 72 spinlock_t *lock; 73}; 74 75#define to_clk_frac_div(_hw) container_of(_hw, struct tegra_clk_frac_div, hw) 76 77#define TEGRA_DIVIDER_ROUND_UP BIT(0) 78#define TEGRA_DIVIDER_FIXED BIT(1) 79#define TEGRA_DIVIDER_INT BIT(2) 80#define TEGRA_DIVIDER_UART BIT(3) 81 82extern const struct clk_ops tegra_clk_frac_div_ops; 83struct clk *tegra_clk_register_divider(const char *name, 84 const char *parent_name, void __iomem *reg, 85 unsigned long flags, u8 clk_divider_flags, u8 shift, u8 width, 86 u8 frac_width, spinlock_t *lock); 87 88/* 89 * Tegra PLL: 90 * 91 * In general, there are 3 requirements for each PLL 92 * that SW needs to be comply with. 93 * (1) Input frequency range (REF). 94 * (2) Comparison frequency range (CF). CF = REF/DIVM. 95 * (3) VCO frequency range (VCO). VCO = CF * DIVN. 96 * 97 * The final PLL output frequency (FO) = VCO >> DIVP. 98 */ 99 100/** 101 * struct tegra_clk_pll_freq_table - PLL frequecy table 102 * 103 * @input_rate: input rate from source 104 * @output_rate: output rate from PLL for the input rate 105 * @n: feedback divider 106 * @m: input divider 107 * @p: post divider 108 * @cpcon: charge pump current 109 */ 110struct tegra_clk_pll_freq_table { 111 unsigned long input_rate; 112 unsigned long output_rate; 113 u16 n; 114 u16 m; 115 u8 p; 116 u8 cpcon; 117}; 118 119/** 120 * struct pdiv_map - map post divider to hw value 121 * 122 * @pdiv: post divider 123 * @hw_val: value to be written to the PLL hw 124 */ 125struct pdiv_map { 126 u8 pdiv; 127 u8 hw_val; 128}; 129 130/** 131 * struct clk_pll_params - PLL parameters 132 * 133 * @input_min: Minimum input frequency 134 * @input_max: Maximum input frequency 135 * @cf_min: Minimum comparison frequency 136 * @cf_max: Maximum comparison frequency 137 * @vco_min: Minimum VCO frequency 138 * @vco_max: Maximum VCO frequency 139 * @base_reg: PLL base reg offset 140 * @misc_reg: PLL misc reg offset 141 * @lock_reg: PLL lock reg offset 142 * @lock_bit_idx: Bit index for PLL lock status 143 * @lock_enable_bit_idx: Bit index to enable PLL lock 144 * @lock_delay: Delay in us if PLL lock is not used 145 */ 146struct tegra_clk_pll_params { 147 unsigned long input_min; 148 unsigned long input_max; 149 unsigned long cf_min; 150 unsigned long cf_max; 151 unsigned long vco_min; 152 unsigned long vco_max; 153 154 u32 base_reg; 155 u32 misc_reg; 156 u32 lock_reg; 157 u32 lock_bit_idx; 158 u32 lock_enable_bit_idx; 159 int lock_delay; 160 int max_p; 161 struct pdiv_map *pdiv_tohw; 162}; 163 164/** 165 * struct tegra_clk_pll - Tegra PLL clock 166 * 167 * @hw: handle between common and hardware-specifix interfaces 168 * @clk_base: address of CAR controller 169 * @pmc: address of PMC, required to read override bits 170 * @freq_table: array of frequencies supported by PLL 171 * @params: PLL parameters 172 * @flags: PLL flags 173 * @fixed_rate: PLL rate if it is fixed 174 * @lock: register lock 175 * @divn_shift: shift to the feedback divider bit field 176 * @divn_width: width of the feedback divider bit field 177 * @divm_shift: shift to the input divider bit field 178 * @divm_width: width of the input divider bit field 179 * @divp_shift: shift to the post divider bit field 180 * @divp_width: width of the post divider bit field 181 * 182 * Flags: 183 * TEGRA_PLL_USE_LOCK - This flag indicated to use lock bits for 184 * PLL locking. If not set it will use lock_delay value to wait. 185 * TEGRA_PLL_HAS_CPCON - This flag indicates that CPCON value needs 186 * to be programmed to change output frequency of the PLL. 187 * TEGRA_PLL_SET_LFCON - This flag indicates that LFCON value needs 188 * to be programmed to change output frequency of the PLL. 189 * TEGRA_PLL_SET_DCCON - This flag indicates that DCCON value needs 190 * to be programmed to change output frequency of the PLL. 191 * TEGRA_PLLU - PLLU has inverted post divider. This flags indicated 192 * that it is PLLU and invert post divider value. 193 * TEGRA_PLLM - PLLM has additional override settings in PMC. This 194 * flag indicates that it is PLLM and use override settings. 195 * TEGRA_PLL_FIXED - We are not supposed to change output frequency 196 * of some plls. 197 * TEGRA_PLLE_CONFIGURE - Configure PLLE when enabling. 198 * TEGRA_PLL_LOCK_MISC - Lock bit is in the misc register instead of the 199 * base register. 200 * TEGRA_PLL_BYPASS - PLL has bypass bit 201 * TEGRA_PLL_HAS_LOCK_ENABLE - PLL has bit to enable lock monitoring 202 */ 203struct tegra_clk_pll { 204 struct clk_hw hw; 205 void __iomem *clk_base; 206 void __iomem *pmc; 207 u32 flags; 208 unsigned long fixed_rate; 209 spinlock_t *lock; 210 u8 divn_shift; 211 u8 divn_width; 212 u8 divm_shift; 213 u8 divm_width; 214 u8 divp_shift; 215 u8 divp_width; 216 struct tegra_clk_pll_freq_table *freq_table; 217 struct tegra_clk_pll_params *params; 218}; 219 220#define to_clk_pll(_hw) container_of(_hw, struct tegra_clk_pll, hw) 221 222#define TEGRA_PLL_USE_LOCK BIT(0) 223#define TEGRA_PLL_HAS_CPCON BIT(1) 224#define TEGRA_PLL_SET_LFCON BIT(2) 225#define TEGRA_PLL_SET_DCCON BIT(3) 226#define TEGRA_PLLU BIT(4) 227#define TEGRA_PLLM BIT(5) 228#define TEGRA_PLL_FIXED BIT(6) 229#define TEGRA_PLLE_CONFIGURE BIT(7) 230#define TEGRA_PLL_LOCK_MISC BIT(8) 231#define TEGRA_PLL_BYPASS BIT(9) 232#define TEGRA_PLL_HAS_LOCK_ENABLE BIT(10) 233 234extern const struct clk_ops tegra_clk_pll_ops; 235extern const struct clk_ops tegra_clk_plle_ops; 236struct clk *tegra_clk_register_pll(const char *name, const char *parent_name, 237 void __iomem *clk_base, void __iomem *pmc, 238 unsigned long flags, unsigned long fixed_rate, 239 struct tegra_clk_pll_params *pll_params, u32 pll_flags, 240 struct tegra_clk_pll_freq_table *freq_table, spinlock_t *lock); 241struct clk *tegra_clk_register_plle(const char *name, const char *parent_name, 242 void __iomem *clk_base, void __iomem *pmc, 243 unsigned long flags, unsigned long fixed_rate, 244 struct tegra_clk_pll_params *pll_params, u32 pll_flags, 245 struct tegra_clk_pll_freq_table *freq_table, spinlock_t *lock); 246 247/** 248 * struct tegra_clk_pll_out - PLL divider down clock 249 * 250 * @hw: handle between common and hardware-specific interfaces 251 * @reg: register containing the PLL divider 252 * @enb_bit_idx: bit to enable/disable PLL divider 253 * @rst_bit_idx: bit to reset PLL divider 254 * @lock: register lock 255 * @flags: hardware-specific flags 256 */ 257struct tegra_clk_pll_out { 258 struct clk_hw hw; 259 void __iomem *reg; 260 u8 enb_bit_idx; 261 u8 rst_bit_idx; 262 spinlock_t *lock; 263 u8 flags; 264}; 265 266#define to_clk_pll_out(_hw) container_of(_hw, struct tegra_clk_pll_out, hw) 267 268extern const struct clk_ops tegra_clk_pll_out_ops; 269struct clk *tegra_clk_register_pll_out(const char *name, 270 const char *parent_name, void __iomem *reg, u8 enb_bit_idx, 271 u8 rst_bit_idx, unsigned long flags, u8 pll_div_flags, 272 spinlock_t *lock); 273 274/** 275 * struct tegra_clk_periph_regs - Registers controlling peripheral clock 276 * 277 * @enb_reg: read the enable status 278 * @enb_set_reg: write 1 to enable clock 279 * @enb_clr_reg: write 1 to disable clock 280 * @rst_reg: read the reset status 281 * @rst_set_reg: write 1 to assert the reset of peripheral 282 * @rst_clr_reg: write 1 to deassert the reset of peripheral 283 */ 284struct tegra_clk_periph_regs { 285 u32 enb_reg; 286 u32 enb_set_reg; 287 u32 enb_clr_reg; 288 u32 rst_reg; 289 u32 rst_set_reg; 290 u32 rst_clr_reg; 291}; 292 293/** 294 * struct tegra_clk_periph_gate - peripheral gate clock 295 * 296 * @magic: magic number to validate type 297 * @hw: handle between common and hardware-specific interfaces 298 * @clk_base: address of CAR controller 299 * @regs: Registers to control the peripheral 300 * @flags: hardware-specific flags 301 * @clk_num: Clock number 302 * @enable_refcnt: array to maintain reference count of the clock 303 * 304 * Flags: 305 * TEGRA_PERIPH_NO_RESET - This flag indicates that reset is not allowed 306 * for this module. 307 * TEGRA_PERIPH_MANUAL_RESET - This flag indicates not to reset module 308 * after clock enable and driver for the module is responsible for 309 * doing reset. 310 * TEGRA_PERIPH_ON_APB - If peripheral is in the APB bus then read the 311 * bus to flush the write operation in apb bus. This flag indicates 312 * that this peripheral is in apb bus. 313 */ 314struct tegra_clk_periph_gate { 315 u32 magic; 316 struct clk_hw hw; 317 void __iomem *clk_base; 318 u8 flags; 319 int clk_num; 320 int *enable_refcnt; 321 struct tegra_clk_periph_regs *regs; 322}; 323 324#define to_clk_periph_gate(_hw) \ 325 container_of(_hw, struct tegra_clk_periph_gate, hw) 326 327#define TEGRA_CLK_PERIPH_GATE_MAGIC 0x17760309 328 329#define TEGRA_PERIPH_NO_RESET BIT(0) 330#define TEGRA_PERIPH_MANUAL_RESET BIT(1) 331#define TEGRA_PERIPH_ON_APB BIT(2) 332 333void tegra_periph_reset(struct tegra_clk_periph_gate *gate, bool assert); 334extern const struct clk_ops tegra_clk_periph_gate_ops; 335struct clk *tegra_clk_register_periph_gate(const char *name, 336 const char *parent_name, u8 gate_flags, void __iomem *clk_base, 337 unsigned long flags, int clk_num, 338 struct tegra_clk_periph_regs *pregs, int *enable_refcnt); 339 340/** 341 * struct clk-periph - peripheral clock 342 * 343 * @magic: magic number to validate type 344 * @hw: handle between common and hardware-specific interfaces 345 * @mux: mux clock 346 * @divider: divider clock 347 * @gate: gate clock 348 * @mux_ops: mux clock ops 349 * @div_ops: divider clock ops 350 * @gate_ops: gate clock ops 351 */ 352struct tegra_clk_periph { 353 u32 magic; 354 struct clk_hw hw; 355 struct clk_mux mux; 356 struct tegra_clk_frac_div divider; 357 struct tegra_clk_periph_gate gate; 358 359 const struct clk_ops *mux_ops; 360 const struct clk_ops *div_ops; 361 const struct clk_ops *gate_ops; 362}; 363 364#define to_clk_periph(_hw) container_of(_hw, struct tegra_clk_periph, hw) 365 366#define TEGRA_CLK_PERIPH_MAGIC 0x18221223 367 368extern const struct clk_ops tegra_clk_periph_ops; 369struct clk *tegra_clk_register_periph(const char *name, 370 const char **parent_names, int num_parents, 371 struct tegra_clk_periph *periph, void __iomem *clk_base, 372 u32 offset); 373struct clk *tegra_clk_register_periph_nodiv(const char *name, 374 const char **parent_names, int num_parents, 375 struct tegra_clk_periph *periph, void __iomem *clk_base, 376 u32 offset); 377 378#define TEGRA_CLK_PERIPH(_mux_shift, _mux_mask, _mux_flags, \ 379 _div_shift, _div_width, _div_frac_width, \ 380 _div_flags, _clk_num, _enb_refcnt, _regs, \ 381 _gate_flags, _table) \ 382 { \ 383 .mux = { \ 384 .flags = _mux_flags, \ 385 .shift = _mux_shift, \ 386 .mask = _mux_mask, \ 387 .table = _table, \ 388 }, \ 389 .divider = { \ 390 .flags = _div_flags, \ 391 .shift = _div_shift, \ 392 .width = _div_width, \ 393 .frac_width = _div_frac_width, \ 394 }, \ 395 .gate = { \ 396 .flags = _gate_flags, \ 397 .clk_num = _clk_num, \ 398 .enable_refcnt = _enb_refcnt, \ 399 .regs = _regs, \ 400 }, \ 401 .mux_ops = &clk_mux_ops, \ 402 .div_ops = &tegra_clk_frac_div_ops, \ 403 .gate_ops = &tegra_clk_periph_gate_ops, \ 404 } 405 406struct tegra_periph_init_data { 407 const char *name; 408 int clk_id; 409 const char **parent_names; 410 int num_parents; 411 struct tegra_clk_periph periph; 412 u32 offset; 413 const char *con_id; 414 const char *dev_id; 415}; 416 417#define TEGRA_INIT_DATA_TABLE(_name, _con_id, _dev_id, _parent_names, _offset,\ 418 _mux_shift, _mux_mask, _mux_flags, _div_shift, \ 419 _div_width, _div_frac_width, _div_flags, _regs, \ 420 _clk_num, _enb_refcnt, _gate_flags, _clk_id, _table) \ 421 { \ 422 .name = _name, \ 423 .clk_id = _clk_id, \ 424 .parent_names = _parent_names, \ 425 .num_parents = ARRAY_SIZE(_parent_names), \ 426 .periph = TEGRA_CLK_PERIPH(_mux_shift, _mux_mask, \ 427 _mux_flags, _div_shift, \ 428 _div_width, _div_frac_width, \ 429 _div_flags, _clk_num, \ 430 _enb_refcnt, _regs, \ 431 _gate_flags, _table), \ 432 .offset = _offset, \ 433 .con_id = _con_id, \ 434 .dev_id = _dev_id, \ 435 } 436 437#define TEGRA_INIT_DATA(_name, _con_id, _dev_id, _parent_names, _offset,\ 438 _mux_shift, _mux_width, _mux_flags, _div_shift, \ 439 _div_width, _div_frac_width, _div_flags, _regs, \ 440 _clk_num, _enb_refcnt, _gate_flags, _clk_id) \ 441 TEGRA_INIT_DATA_TABLE(_name, _con_id, _dev_id, _parent_names, _offset,\ 442 _mux_shift, BIT(_mux_width) - 1, _mux_flags, \ 443 _div_shift, _div_width, _div_frac_width, _div_flags, \ 444 _regs, _clk_num, _enb_refcnt, _gate_flags, _clk_id,\ 445 NULL) 446 447/** 448 * struct clk_super_mux - super clock 449 * 450 * @hw: handle between common and hardware-specific interfaces 451 * @reg: register controlling multiplexer 452 * @width: width of the multiplexer bit field 453 * @flags: hardware-specific flags 454 * @div2_index: bit controlling divide-by-2 455 * @pllx_index: PLLX index in the parent list 456 * @lock: register lock 457 * 458 * Flags: 459 * TEGRA_DIVIDER_2 - LP cluster has additional divider. This flag indicates 460 * that this is LP cluster clock. 461 */ 462struct tegra_clk_super_mux { 463 struct clk_hw hw; 464 void __iomem *reg; 465 u8 width; 466 u8 flags; 467 u8 div2_index; 468 u8 pllx_index; 469 spinlock_t *lock; 470}; 471 472#define to_clk_super_mux(_hw) container_of(_hw, struct tegra_clk_super_mux, hw) 473 474#define TEGRA_DIVIDER_2 BIT(0) 475 476extern const struct clk_ops tegra_clk_super_ops; 477struct clk *tegra_clk_register_super_mux(const char *name, 478 const char **parent_names, u8 num_parents, 479 unsigned long flags, void __iomem *reg, u8 clk_super_flags, 480 u8 width, u8 pllx_index, u8 div2_index, spinlock_t *lock); 481 482/** 483 * struct clk_init_tabel - clock initialization table 484 * @clk_id: clock id as mentioned in device tree bindings 485 * @parent_id: parent clock id as mentioned in device tree bindings 486 * @rate: rate to set 487 * @state: enable/disable 488 */ 489struct tegra_clk_init_table { 490 unsigned int clk_id; 491 unsigned int parent_id; 492 unsigned long rate; 493 int state; 494}; 495 496/** 497 * struct clk_duplicate - duplicate clocks 498 * @clk_id: clock id as mentioned in device tree bindings 499 * @lookup: duplicate lookup entry for the clock 500 */ 501struct tegra_clk_duplicate { 502 int clk_id; 503 struct clk_lookup lookup; 504}; 505 506#define TEGRA_CLK_DUPLICATE(_clk_id, _dev, _con) \ 507 { \ 508 .clk_id = _clk_id, \ 509 .lookup = { \ 510 .dev_id = _dev, \ 511 .con_id = _con, \ 512 }, \ 513 } 514 515void tegra_init_from_table(struct tegra_clk_init_table *tbl, 516 struct clk *clks[], int clk_max); 517 518void tegra_init_dup_clks(struct tegra_clk_duplicate *dup_list, 519 struct clk *clks[], int clk_max); 520 521#ifdef CONFIG_ARCH_TEGRA_2x_SOC 522void tegra20_clock_init(struct device_node *np); 523#else 524static inline void tegra20_clock_init(struct device_node *np) {} 525#endif /* CONFIG_ARCH_TEGRA_2x_SOC */ 526 527#ifdef CONFIG_ARCH_TEGRA_3x_SOC 528void tegra30_clock_init(struct device_node *np); 529#else 530static inline void tegra30_clock_init(struct device_node *np) {} 531#endif /* CONFIG_ARCH_TEGRA_3x_SOC */ 532 533typedef void (*tegra_clk_apply_init_table_func)(void); 534extern tegra_clk_apply_init_table_func tegra_clk_apply_init_table; 535 536#endif /* TEGRA_CLK_H */ 537