clk.h revision dd93587be8dc8acf23a0d8a23efc74a91d8f0dfe
1/* 2 * Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved. 3 * 4 * This program is free software; you can redistribute it and/or modify it 5 * under the terms and conditions of the GNU General Public License, 6 * version 2, as published by the Free Software Foundation. 7 * 8 * This program is distributed in the hope it will be useful, but WITHOUT 9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 11 * more details. 12 * 13 * You should have received a copy of the GNU General Public License 14 * along with this program. If not, see <http://www.gnu.org/licenses/>. 15 */ 16 17#ifndef __TEGRA_CLK_H 18#define __TEGRA_CLK_H 19 20#include <linux/clk-provider.h> 21#include <linux/clkdev.h> 22 23/** 24 * struct tegra_clk_sync_source - external clock source from codec 25 * 26 * @hw: handle between common and hardware-specific interfaces 27 * @rate: input frequency from source 28 * @max_rate: max rate allowed 29 */ 30struct tegra_clk_sync_source { 31 struct clk_hw hw; 32 unsigned long rate; 33 unsigned long max_rate; 34}; 35 36#define to_clk_sync_source(_hw) \ 37 container_of(_hw, struct tegra_clk_sync_source, hw) 38 39extern const struct clk_ops tegra_clk_sync_source_ops; 40struct clk *tegra_clk_register_sync_source(const char *name, 41 unsigned long fixed_rate, unsigned long max_rate); 42 43/** 44 * struct tegra_clk_frac_div - fractional divider clock 45 * 46 * @hw: handle between common and hardware-specific interfaces 47 * @reg: register containing divider 48 * @flags: hardware-specific flags 49 * @shift: shift to the divider bit field 50 * @width: width of the divider bit field 51 * @frac_width: width of the fractional bit field 52 * @lock: register lock 53 * 54 * Flags: 55 * TEGRA_DIVIDER_ROUND_UP - This flags indicates to round up the divider value. 56 * TEGRA_DIVIDER_FIXED - Fixed rate PLL dividers has addition override bit, this 57 * flag indicates that this divider is for fixed rate PLL. 58 * TEGRA_DIVIDER_INT - Some modules can not cope with the duty cycle when 59 * fraction bit is set. This flags indicates to calculate divider for which 60 * fracton bit will be zero. 61 * TEGRA_DIVIDER_UART - UART module divider has additional enable bit which is 62 * set when divider value is not 0. This flags indicates that the divider 63 * is for UART module. 64 */ 65struct tegra_clk_frac_div { 66 struct clk_hw hw; 67 void __iomem *reg; 68 u8 flags; 69 u8 shift; 70 u8 width; 71 u8 frac_width; 72 spinlock_t *lock; 73}; 74 75#define to_clk_frac_div(_hw) container_of(_hw, struct tegra_clk_frac_div, hw) 76 77#define TEGRA_DIVIDER_ROUND_UP BIT(0) 78#define TEGRA_DIVIDER_FIXED BIT(1) 79#define TEGRA_DIVIDER_INT BIT(2) 80#define TEGRA_DIVIDER_UART BIT(3) 81 82extern const struct clk_ops tegra_clk_frac_div_ops; 83struct clk *tegra_clk_register_divider(const char *name, 84 const char *parent_name, void __iomem *reg, 85 unsigned long flags, u8 clk_divider_flags, u8 shift, u8 width, 86 u8 frac_width, spinlock_t *lock); 87 88/* 89 * Tegra PLL: 90 * 91 * In general, there are 3 requirements for each PLL 92 * that SW needs to be comply with. 93 * (1) Input frequency range (REF). 94 * (2) Comparison frequency range (CF). CF = REF/DIVM. 95 * (3) VCO frequency range (VCO). VCO = CF * DIVN. 96 * 97 * The final PLL output frequency (FO) = VCO >> DIVP. 98 */ 99 100/** 101 * struct tegra_clk_pll_freq_table - PLL frequecy table 102 * 103 * @input_rate: input rate from source 104 * @output_rate: output rate from PLL for the input rate 105 * @n: feedback divider 106 * @m: input divider 107 * @p: post divider 108 * @cpcon: charge pump current 109 */ 110struct tegra_clk_pll_freq_table { 111 unsigned long input_rate; 112 unsigned long output_rate; 113 u16 n; 114 u16 m; 115 u8 p; 116 u8 cpcon; 117}; 118 119/** 120 * struct clk_pll_params - PLL parameters 121 * 122 * @input_min: Minimum input frequency 123 * @input_max: Maximum input frequency 124 * @cf_min: Minimum comparison frequency 125 * @cf_max: Maximum comparison frequency 126 * @vco_min: Minimum VCO frequency 127 * @vco_max: Maximum VCO frequency 128 * @base_reg: PLL base reg offset 129 * @misc_reg: PLL misc reg offset 130 * @lock_reg: PLL lock reg offset 131 * @lock_bit_idx: Bit index for PLL lock status 132 * @lock_enable_bit_idx: Bit index to enable PLL lock 133 * @lock_delay: Delay in us if PLL lock is not used 134 */ 135struct tegra_clk_pll_params { 136 unsigned long input_min; 137 unsigned long input_max; 138 unsigned long cf_min; 139 unsigned long cf_max; 140 unsigned long vco_min; 141 unsigned long vco_max; 142 143 u32 base_reg; 144 u32 misc_reg; 145 u32 lock_reg; 146 u32 lock_bit_idx; 147 u32 lock_enable_bit_idx; 148 int lock_delay; 149}; 150 151/** 152 * struct tegra_clk_pll - Tegra PLL clock 153 * 154 * @hw: handle between common and hardware-specifix interfaces 155 * @clk_base: address of CAR controller 156 * @pmc: address of PMC, required to read override bits 157 * @freq_table: array of frequencies supported by PLL 158 * @params: PLL parameters 159 * @flags: PLL flags 160 * @fixed_rate: PLL rate if it is fixed 161 * @lock: register lock 162 * @divn_shift: shift to the feedback divider bit field 163 * @divn_width: width of the feedback divider bit field 164 * @divm_shift: shift to the input divider bit field 165 * @divm_width: width of the input divider bit field 166 * @divp_shift: shift to the post divider bit field 167 * @divp_width: width of the post divider bit field 168 * 169 * Flags: 170 * TEGRA_PLL_USE_LOCK - This flag indicated to use lock bits for 171 * PLL locking. If not set it will use lock_delay value to wait. 172 * TEGRA_PLL_HAS_CPCON - This flag indicates that CPCON value needs 173 * to be programmed to change output frequency of the PLL. 174 * TEGRA_PLL_SET_LFCON - This flag indicates that LFCON value needs 175 * to be programmed to change output frequency of the PLL. 176 * TEGRA_PLL_SET_DCCON - This flag indicates that DCCON value needs 177 * to be programmed to change output frequency of the PLL. 178 * TEGRA_PLLU - PLLU has inverted post divider. This flags indicated 179 * that it is PLLU and invert post divider value. 180 * TEGRA_PLLM - PLLM has additional override settings in PMC. This 181 * flag indicates that it is PLLM and use override settings. 182 * TEGRA_PLL_FIXED - We are not supposed to change output frequency 183 * of some plls. 184 * TEGRA_PLLE_CONFIGURE - Configure PLLE when enabling. 185 * TEGRA_PLL_LOCK_MISC - Lock bit is in the misc register instead of the 186 * base register. 187 * TEGRA_PLL_BYPASS - PLL has bypass bit 188 */ 189struct tegra_clk_pll { 190 struct clk_hw hw; 191 void __iomem *clk_base; 192 void __iomem *pmc; 193 u32 flags; 194 unsigned long fixed_rate; 195 spinlock_t *lock; 196 u8 divn_shift; 197 u8 divn_width; 198 u8 divm_shift; 199 u8 divm_width; 200 u8 divp_shift; 201 u8 divp_width; 202 struct tegra_clk_pll_freq_table *freq_table; 203 struct tegra_clk_pll_params *params; 204}; 205 206#define to_clk_pll(_hw) container_of(_hw, struct tegra_clk_pll, hw) 207 208#define TEGRA_PLL_USE_LOCK BIT(0) 209#define TEGRA_PLL_HAS_CPCON BIT(1) 210#define TEGRA_PLL_SET_LFCON BIT(2) 211#define TEGRA_PLL_SET_DCCON BIT(3) 212#define TEGRA_PLLU BIT(4) 213#define TEGRA_PLLM BIT(5) 214#define TEGRA_PLL_FIXED BIT(6) 215#define TEGRA_PLLE_CONFIGURE BIT(7) 216#define TEGRA_PLL_LOCK_MISC BIT(8) 217#define TEGRA_PLL_BYPASS BIT(9) 218 219extern const struct clk_ops tegra_clk_pll_ops; 220extern const struct clk_ops tegra_clk_plle_ops; 221struct clk *tegra_clk_register_pll(const char *name, const char *parent_name, 222 void __iomem *clk_base, void __iomem *pmc, 223 unsigned long flags, unsigned long fixed_rate, 224 struct tegra_clk_pll_params *pll_params, u32 pll_flags, 225 struct tegra_clk_pll_freq_table *freq_table, spinlock_t *lock); 226struct clk *tegra_clk_register_plle(const char *name, const char *parent_name, 227 void __iomem *clk_base, void __iomem *pmc, 228 unsigned long flags, unsigned long fixed_rate, 229 struct tegra_clk_pll_params *pll_params, u32 pll_flags, 230 struct tegra_clk_pll_freq_table *freq_table, spinlock_t *lock); 231 232/** 233 * struct tegra_clk_pll_out - PLL divider down clock 234 * 235 * @hw: handle between common and hardware-specific interfaces 236 * @reg: register containing the PLL divider 237 * @enb_bit_idx: bit to enable/disable PLL divider 238 * @rst_bit_idx: bit to reset PLL divider 239 * @lock: register lock 240 * @flags: hardware-specific flags 241 */ 242struct tegra_clk_pll_out { 243 struct clk_hw hw; 244 void __iomem *reg; 245 u8 enb_bit_idx; 246 u8 rst_bit_idx; 247 spinlock_t *lock; 248 u8 flags; 249}; 250 251#define to_clk_pll_out(_hw) container_of(_hw, struct tegra_clk_pll_out, hw) 252 253extern const struct clk_ops tegra_clk_pll_out_ops; 254struct clk *tegra_clk_register_pll_out(const char *name, 255 const char *parent_name, void __iomem *reg, u8 enb_bit_idx, 256 u8 rst_bit_idx, unsigned long flags, u8 pll_div_flags, 257 spinlock_t *lock); 258 259/** 260 * struct tegra_clk_periph_regs - Registers controlling peripheral clock 261 * 262 * @enb_reg: read the enable status 263 * @enb_set_reg: write 1 to enable clock 264 * @enb_clr_reg: write 1 to disable clock 265 * @rst_reg: read the reset status 266 * @rst_set_reg: write 1 to assert the reset of peripheral 267 * @rst_clr_reg: write 1 to deassert the reset of peripheral 268 */ 269struct tegra_clk_periph_regs { 270 u32 enb_reg; 271 u32 enb_set_reg; 272 u32 enb_clr_reg; 273 u32 rst_reg; 274 u32 rst_set_reg; 275 u32 rst_clr_reg; 276}; 277 278/** 279 * struct tegra_clk_periph_gate - peripheral gate clock 280 * 281 * @magic: magic number to validate type 282 * @hw: handle between common and hardware-specific interfaces 283 * @clk_base: address of CAR controller 284 * @regs: Registers to control the peripheral 285 * @flags: hardware-specific flags 286 * @clk_num: Clock number 287 * @enable_refcnt: array to maintain reference count of the clock 288 * 289 * Flags: 290 * TEGRA_PERIPH_NO_RESET - This flag indicates that reset is not allowed 291 * for this module. 292 * TEGRA_PERIPH_MANUAL_RESET - This flag indicates not to reset module 293 * after clock enable and driver for the module is responsible for 294 * doing reset. 295 * TEGRA_PERIPH_ON_APB - If peripheral is in the APB bus then read the 296 * bus to flush the write operation in apb bus. This flag indicates 297 * that this peripheral is in apb bus. 298 */ 299struct tegra_clk_periph_gate { 300 u32 magic; 301 struct clk_hw hw; 302 void __iomem *clk_base; 303 u8 flags; 304 int clk_num; 305 int *enable_refcnt; 306 struct tegra_clk_periph_regs *regs; 307}; 308 309#define to_clk_periph_gate(_hw) \ 310 container_of(_hw, struct tegra_clk_periph_gate, hw) 311 312#define TEGRA_CLK_PERIPH_GATE_MAGIC 0x17760309 313 314#define TEGRA_PERIPH_NO_RESET BIT(0) 315#define TEGRA_PERIPH_MANUAL_RESET BIT(1) 316#define TEGRA_PERIPH_ON_APB BIT(2) 317 318void tegra_periph_reset(struct tegra_clk_periph_gate *gate, bool assert); 319extern const struct clk_ops tegra_clk_periph_gate_ops; 320struct clk *tegra_clk_register_periph_gate(const char *name, 321 const char *parent_name, u8 gate_flags, void __iomem *clk_base, 322 unsigned long flags, int clk_num, 323 struct tegra_clk_periph_regs *pregs, int *enable_refcnt); 324 325/** 326 * struct clk-periph - peripheral clock 327 * 328 * @magic: magic number to validate type 329 * @hw: handle between common and hardware-specific interfaces 330 * @mux: mux clock 331 * @divider: divider clock 332 * @gate: gate clock 333 * @mux_ops: mux clock ops 334 * @div_ops: divider clock ops 335 * @gate_ops: gate clock ops 336 */ 337struct tegra_clk_periph { 338 u32 magic; 339 struct clk_hw hw; 340 struct clk_mux mux; 341 struct tegra_clk_frac_div divider; 342 struct tegra_clk_periph_gate gate; 343 344 const struct clk_ops *mux_ops; 345 const struct clk_ops *div_ops; 346 const struct clk_ops *gate_ops; 347}; 348 349#define to_clk_periph(_hw) container_of(_hw, struct tegra_clk_periph, hw) 350 351#define TEGRA_CLK_PERIPH_MAGIC 0x18221223 352 353extern const struct clk_ops tegra_clk_periph_ops; 354struct clk *tegra_clk_register_periph(const char *name, 355 const char **parent_names, int num_parents, 356 struct tegra_clk_periph *periph, void __iomem *clk_base, 357 u32 offset); 358struct clk *tegra_clk_register_periph_nodiv(const char *name, 359 const char **parent_names, int num_parents, 360 struct tegra_clk_periph *periph, void __iomem *clk_base, 361 u32 offset); 362 363#define TEGRA_CLK_PERIPH(_mux_shift, _mux_mask, _mux_flags, \ 364 _div_shift, _div_width, _div_frac_width, \ 365 _div_flags, _clk_num, _enb_refcnt, _regs, \ 366 _gate_flags, _table) \ 367 { \ 368 .mux = { \ 369 .flags = _mux_flags, \ 370 .shift = _mux_shift, \ 371 .mask = _mux_mask, \ 372 .table = _table, \ 373 }, \ 374 .divider = { \ 375 .flags = _div_flags, \ 376 .shift = _div_shift, \ 377 .width = _div_width, \ 378 .frac_width = _div_frac_width, \ 379 }, \ 380 .gate = { \ 381 .flags = _gate_flags, \ 382 .clk_num = _clk_num, \ 383 .enable_refcnt = _enb_refcnt, \ 384 .regs = _regs, \ 385 }, \ 386 .mux_ops = &clk_mux_ops, \ 387 .div_ops = &tegra_clk_frac_div_ops, \ 388 .gate_ops = &tegra_clk_periph_gate_ops, \ 389 } 390 391struct tegra_periph_init_data { 392 const char *name; 393 int clk_id; 394 const char **parent_names; 395 int num_parents; 396 struct tegra_clk_periph periph; 397 u32 offset; 398 const char *con_id; 399 const char *dev_id; 400}; 401 402#define TEGRA_INIT_DATA_TABLE(_name, _con_id, _dev_id, _parent_names, _offset,\ 403 _mux_shift, _mux_mask, _mux_flags, _div_shift, \ 404 _div_width, _div_frac_width, _div_flags, _regs, \ 405 _clk_num, _enb_refcnt, _gate_flags, _clk_id, _table) \ 406 { \ 407 .name = _name, \ 408 .clk_id = _clk_id, \ 409 .parent_names = _parent_names, \ 410 .num_parents = ARRAY_SIZE(_parent_names), \ 411 .periph = TEGRA_CLK_PERIPH(_mux_shift, _mux_mask, \ 412 _mux_flags, _div_shift, \ 413 _div_width, _div_frac_width, \ 414 _div_flags, _clk_num, \ 415 _enb_refcnt, _regs, \ 416 _gate_flags, _table), \ 417 .offset = _offset, \ 418 .con_id = _con_id, \ 419 .dev_id = _dev_id, \ 420 } 421 422#define TEGRA_INIT_DATA(_name, _con_id, _dev_id, _parent_names, _offset,\ 423 _mux_shift, _mux_width, _mux_flags, _div_shift, \ 424 _div_width, _div_frac_width, _div_flags, _regs, \ 425 _clk_num, _enb_refcnt, _gate_flags, _clk_id) \ 426 TEGRA_INIT_DATA_TABLE(_name, _con_id, _dev_id, _parent_names, _offset,\ 427 _mux_shift, BIT(_mux_width) - 1, _mux_flags, \ 428 _div_shift, _div_width, _div_frac_width, _div_flags, \ 429 _regs, _clk_num, _enb_refcnt, _gate_flags, _clk_id,\ 430 NULL) 431 432/** 433 * struct clk_super_mux - super clock 434 * 435 * @hw: handle between common and hardware-specific interfaces 436 * @reg: register controlling multiplexer 437 * @width: width of the multiplexer bit field 438 * @flags: hardware-specific flags 439 * @div2_index: bit controlling divide-by-2 440 * @pllx_index: PLLX index in the parent list 441 * @lock: register lock 442 * 443 * Flags: 444 * TEGRA_DIVIDER_2 - LP cluster has additional divider. This flag indicates 445 * that this is LP cluster clock. 446 */ 447struct tegra_clk_super_mux { 448 struct clk_hw hw; 449 void __iomem *reg; 450 u8 width; 451 u8 flags; 452 u8 div2_index; 453 u8 pllx_index; 454 spinlock_t *lock; 455}; 456 457#define to_clk_super_mux(_hw) container_of(_hw, struct tegra_clk_super_mux, hw) 458 459#define TEGRA_DIVIDER_2 BIT(0) 460 461extern const struct clk_ops tegra_clk_super_ops; 462struct clk *tegra_clk_register_super_mux(const char *name, 463 const char **parent_names, u8 num_parents, 464 unsigned long flags, void __iomem *reg, u8 clk_super_flags, 465 u8 width, u8 pllx_index, u8 div2_index, spinlock_t *lock); 466 467/** 468 * struct clk_init_tabel - clock initialization table 469 * @clk_id: clock id as mentioned in device tree bindings 470 * @parent_id: parent clock id as mentioned in device tree bindings 471 * @rate: rate to set 472 * @state: enable/disable 473 */ 474struct tegra_clk_init_table { 475 unsigned int clk_id; 476 unsigned int parent_id; 477 unsigned long rate; 478 int state; 479}; 480 481/** 482 * struct clk_duplicate - duplicate clocks 483 * @clk_id: clock id as mentioned in device tree bindings 484 * @lookup: duplicate lookup entry for the clock 485 */ 486struct tegra_clk_duplicate { 487 int clk_id; 488 struct clk_lookup lookup; 489}; 490 491#define TEGRA_CLK_DUPLICATE(_clk_id, _dev, _con) \ 492 { \ 493 .clk_id = _clk_id, \ 494 .lookup = { \ 495 .dev_id = _dev, \ 496 .con_id = _con, \ 497 }, \ 498 } 499 500void tegra_init_from_table(struct tegra_clk_init_table *tbl, 501 struct clk *clks[], int clk_max); 502 503void tegra_init_dup_clks(struct tegra_clk_duplicate *dup_list, 504 struct clk *clks[], int clk_max); 505 506#ifdef CONFIG_ARCH_TEGRA_2x_SOC 507void tegra20_clock_init(struct device_node *np); 508#else 509static inline void tegra20_clock_init(struct device_node *np) {} 510#endif /* CONFIG_ARCH_TEGRA_2x_SOC */ 511 512#ifdef CONFIG_ARCH_TEGRA_3x_SOC 513void tegra30_clock_init(struct device_node *np); 514#else 515static inline void tegra30_clock_init(struct device_node *np) {} 516#endif /* CONFIG_ARCH_TEGRA_3x_SOC */ 517 518typedef void (*tegra_clk_apply_init_table_func)(void); 519extern tegra_clk_apply_init_table_func tegra_clk_apply_init_table; 520 521#endif /* TEGRA_CLK_H */ 522