exynos_mct.c revision 3252a646aa2cf706b2a26433a8bd9cb2e5dce410 
1/* linux/arch/arm/mach-exynos4/mct.c
2 *
3 * Copyright (c) 2011 Samsung Electronics Co., Ltd.
4 *		http://www.samsung.com
5 *
6 * EXYNOS4 MCT(Multi-Core Timer) support
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#include <linux/sched.h>
14#include <linux/interrupt.h>
15#include <linux/irq.h>
16#include <linux/err.h>
17#include <linux/clk.h>
18#include <linux/clockchips.h>
19#include <linux/cpu.h>
20#include <linux/platform_device.h>
21#include <linux/delay.h>
22#include <linux/percpu.h>
23#include <linux/of.h>
24#include <linux/of_irq.h>
25#include <linux/of_address.h>
26#include <linux/clocksource.h>
27#include <linux/sched_clock.h>
28
29#define EXYNOS4_MCTREG(x)		(x)
30#define EXYNOS4_MCT_G_CNT_L		EXYNOS4_MCTREG(0x100)
31#define EXYNOS4_MCT_G_CNT_U		EXYNOS4_MCTREG(0x104)
32#define EXYNOS4_MCT_G_CNT_WSTAT		EXYNOS4_MCTREG(0x110)
33#define EXYNOS4_MCT_G_COMP0_L		EXYNOS4_MCTREG(0x200)
34#define EXYNOS4_MCT_G_COMP0_U		EXYNOS4_MCTREG(0x204)
35#define EXYNOS4_MCT_G_COMP0_ADD_INCR	EXYNOS4_MCTREG(0x208)
36#define EXYNOS4_MCT_G_TCON		EXYNOS4_MCTREG(0x240)
37#define EXYNOS4_MCT_G_INT_CSTAT		EXYNOS4_MCTREG(0x244)
38#define EXYNOS4_MCT_G_INT_ENB		EXYNOS4_MCTREG(0x248)
39#define EXYNOS4_MCT_G_WSTAT		EXYNOS4_MCTREG(0x24C)
40#define _EXYNOS4_MCT_L_BASE		EXYNOS4_MCTREG(0x300)
41#define EXYNOS4_MCT_L_BASE(x)		(_EXYNOS4_MCT_L_BASE + (0x100 * x))
42#define EXYNOS4_MCT_L_MASK		(0xffffff00)
43
44#define MCT_L_TCNTB_OFFSET		(0x00)
45#define MCT_L_ICNTB_OFFSET		(0x08)
46#define MCT_L_TCON_OFFSET		(0x20)
47#define MCT_L_INT_CSTAT_OFFSET		(0x30)
48#define MCT_L_INT_ENB_OFFSET		(0x34)
49#define MCT_L_WSTAT_OFFSET		(0x40)
50#define MCT_G_TCON_START		(1 << 8)
51#define MCT_G_TCON_COMP0_AUTO_INC	(1 << 1)
52#define MCT_G_TCON_COMP0_ENABLE		(1 << 0)
53#define MCT_L_TCON_INTERVAL_MODE	(1 << 2)
54#define MCT_L_TCON_INT_START		(1 << 1)
55#define MCT_L_TCON_TIMER_START		(1 << 0)
56
57#define TICK_BASE_CNT	1
58
59enum {
60	MCT_INT_SPI,
61	MCT_INT_PPI
62};
63
64enum {
65	MCT_G0_IRQ,
66	MCT_G1_IRQ,
67	MCT_G2_IRQ,
68	MCT_G3_IRQ,
69	MCT_L0_IRQ,
70	MCT_L1_IRQ,
71	MCT_L2_IRQ,
72	MCT_L3_IRQ,
73	MCT_L4_IRQ,
74	MCT_L5_IRQ,
75	MCT_L6_IRQ,
76	MCT_L7_IRQ,
77	MCT_NR_IRQS,
78};
79
80static void __iomem *reg_base;
81static unsigned long clk_rate;
82static unsigned int mct_int_type;
83static int mct_irqs[MCT_NR_IRQS];
84
85struct mct_clock_event_device {
86	struct clock_event_device evt;
87	unsigned long base;
88	char name[10];
89};
90
91static void exynos4_mct_write(unsigned int value, unsigned long offset)
92{
93	unsigned long stat_addr;
94	u32 mask;
95	u32 i;
96
97	writel_relaxed(value, reg_base + offset);
98
99	if (likely(offset >= EXYNOS4_MCT_L_BASE(0))) {
100		stat_addr = (offset & ~EXYNOS4_MCT_L_MASK) + MCT_L_WSTAT_OFFSET;
101		switch (offset & EXYNOS4_MCT_L_MASK) {
102		case MCT_L_TCON_OFFSET:
103			mask = 1 << 3;		/* L_TCON write status */
104			break;
105		case MCT_L_ICNTB_OFFSET:
106			mask = 1 << 1;		/* L_ICNTB write status */
107			break;
108		case MCT_L_TCNTB_OFFSET:
109			mask = 1 << 0;		/* L_TCNTB write status */
110			break;
111		default:
112			return;
113		}
114	} else {
115		switch (offset) {
116		case EXYNOS4_MCT_G_TCON:
117			stat_addr = EXYNOS4_MCT_G_WSTAT;
118			mask = 1 << 16;		/* G_TCON write status */
119			break;
120		case EXYNOS4_MCT_G_COMP0_L:
121			stat_addr = EXYNOS4_MCT_G_WSTAT;
122			mask = 1 << 0;		/* G_COMP0_L write status */
123			break;
124		case EXYNOS4_MCT_G_COMP0_U:
125			stat_addr = EXYNOS4_MCT_G_WSTAT;
126			mask = 1 << 1;		/* G_COMP0_U write status */
127			break;
128		case EXYNOS4_MCT_G_COMP0_ADD_INCR:
129			stat_addr = EXYNOS4_MCT_G_WSTAT;
130			mask = 1 << 2;		/* G_COMP0_ADD_INCR w status */
131			break;
132		case EXYNOS4_MCT_G_CNT_L:
133			stat_addr = EXYNOS4_MCT_G_CNT_WSTAT;
134			mask = 1 << 0;		/* G_CNT_L write status */
135			break;
136		case EXYNOS4_MCT_G_CNT_U:
137			stat_addr = EXYNOS4_MCT_G_CNT_WSTAT;
138			mask = 1 << 1;		/* G_CNT_U write status */
139			break;
140		default:
141			return;
142		}
143	}
144
145	/* Wait maximum 1 ms until written values are applied */
146	for (i = 0; i < loops_per_jiffy / 1000 * HZ; i++)
147		if (readl_relaxed(reg_base + stat_addr) & mask) {
148			writel_relaxed(mask, reg_base + stat_addr);
149			return;
150		}
151
152	panic("MCT hangs after writing %d (offset:0x%lx)\n", value, offset);
153}
154
155/* Clocksource handling */
156static void exynos4_mct_frc_start(void)
157{
158	u32 reg;
159
160	reg = readl_relaxed(reg_base + EXYNOS4_MCT_G_TCON);
161	reg |= MCT_G_TCON_START;
162	exynos4_mct_write(reg, EXYNOS4_MCT_G_TCON);
163}
164
165/**
166 * exynos4_read_count_64 - Read all 64-bits of the global counter
167 *
168 * This will read all 64-bits of the global counter taking care to make sure
169 * that the upper and lower half match.  Note that reading the MCT can be quite
170 * slow (hundreds of nanoseconds) so you should use the 32-bit (lower half
171 * only) version when possible.
172 *
173 * Returns the number of cycles in the global counter.
174 */
175static u64 exynos4_read_count_64(void)
176{
177	unsigned int lo, hi;
178	u32 hi2 = readl_relaxed(reg_base + EXYNOS4_MCT_G_CNT_U);
179
180	do {
181		hi = hi2;
182		lo = readl_relaxed(reg_base + EXYNOS4_MCT_G_CNT_L);
183		hi2 = readl_relaxed(reg_base + EXYNOS4_MCT_G_CNT_U);
184	} while (hi != hi2);
185
186	return ((cycle_t)hi << 32) | lo;
187}
188
189/**
190 * exynos4_read_count_32 - Read the lower 32-bits of the global counter
191 *
192 * This will read just the lower 32-bits of the global counter.  This is marked
193 * as notrace so it can be used by the scheduler clock.
194 *
195 * Returns the number of cycles in the global counter (lower 32 bits).
196 */
197static u32 notrace exynos4_read_count_32(void)
198{
199	return readl_relaxed(reg_base + EXYNOS4_MCT_G_CNT_L);
200}
201
202static cycle_t exynos4_frc_read(struct clocksource *cs)
203{
204	return exynos4_read_count_32();
205}
206
207static void exynos4_frc_resume(struct clocksource *cs)
208{
209	exynos4_mct_frc_start();
210}
211
212struct clocksource mct_frc = {
213	.name		= "mct-frc",
214	.rating		= 400,
215	.read		= exynos4_frc_read,
216	.mask		= CLOCKSOURCE_MASK(32),
217	.flags		= CLOCK_SOURCE_IS_CONTINUOUS,
218	.resume		= exynos4_frc_resume,
219};
220
221static u64 notrace exynos4_read_sched_clock(void)
222{
223	return exynos4_read_count_32();
224}
225
226static struct delay_timer exynos4_delay_timer;
227
228static cycles_t exynos4_read_current_timer(void)
229{
230	BUILD_BUG_ON_MSG(sizeof(cycles_t) != sizeof(u32),
231			 "cycles_t needs to move to 32-bit for ARM64 usage");
232	return exynos4_read_count_32();
233}
234
235static void __init exynos4_clocksource_init(void)
236{
237	exynos4_mct_frc_start();
238
239	exynos4_delay_timer.read_current_timer = &exynos4_read_current_timer;
240	exynos4_delay_timer.freq = clk_rate;
241	register_current_timer_delay(&exynos4_delay_timer);
242
243	if (clocksource_register_hz(&mct_frc, clk_rate))
244		panic("%s: can't register clocksource\n", mct_frc.name);
245
246	sched_clock_register(exynos4_read_sched_clock, 32, clk_rate);
247}
248
249static void exynos4_mct_comp0_stop(void)
250{
251	unsigned int tcon;
252
253	tcon = readl_relaxed(reg_base + EXYNOS4_MCT_G_TCON);
254	tcon &= ~(MCT_G_TCON_COMP0_ENABLE | MCT_G_TCON_COMP0_AUTO_INC);
255
256	exynos4_mct_write(tcon, EXYNOS4_MCT_G_TCON);
257	exynos4_mct_write(0, EXYNOS4_MCT_G_INT_ENB);
258}
259
260static void exynos4_mct_comp0_start(enum clock_event_mode mode,
261				    unsigned long cycles)
262{
263	unsigned int tcon;
264	cycle_t comp_cycle;
265
266	tcon = readl_relaxed(reg_base + EXYNOS4_MCT_G_TCON);
267
268	if (mode == CLOCK_EVT_MODE_PERIODIC) {
269		tcon |= MCT_G_TCON_COMP0_AUTO_INC;
270		exynos4_mct_write(cycles, EXYNOS4_MCT_G_COMP0_ADD_INCR);
271	}
272
273	comp_cycle = exynos4_read_count_64() + cycles;
274	exynos4_mct_write((u32)comp_cycle, EXYNOS4_MCT_G_COMP0_L);
275	exynos4_mct_write((u32)(comp_cycle >> 32), EXYNOS4_MCT_G_COMP0_U);
276
277	exynos4_mct_write(0x1, EXYNOS4_MCT_G_INT_ENB);
278
279	tcon |= MCT_G_TCON_COMP0_ENABLE;
280	exynos4_mct_write(tcon , EXYNOS4_MCT_G_TCON);
281}
282
283static int exynos4_comp_set_next_event(unsigned long cycles,
284				       struct clock_event_device *evt)
285{
286	exynos4_mct_comp0_start(evt->mode, cycles);
287
288	return 0;
289}
290
291static void exynos4_comp_set_mode(enum clock_event_mode mode,
292				  struct clock_event_device *evt)
293{
294	unsigned long cycles_per_jiffy;
295	exynos4_mct_comp0_stop();
296
297	switch (mode) {
298	case CLOCK_EVT_MODE_PERIODIC:
299		cycles_per_jiffy =
300			(((unsigned long long) NSEC_PER_SEC / HZ * evt->mult) >> evt->shift);
301		exynos4_mct_comp0_start(mode, cycles_per_jiffy);
302		break;
303
304	case CLOCK_EVT_MODE_ONESHOT:
305	case CLOCK_EVT_MODE_UNUSED:
306	case CLOCK_EVT_MODE_SHUTDOWN:
307	case CLOCK_EVT_MODE_RESUME:
308		break;
309	}
310}
311
312static struct clock_event_device mct_comp_device = {
313	.name		= "mct-comp",
314	.features       = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
315	.rating		= 250,
316	.set_next_event	= exynos4_comp_set_next_event,
317	.set_mode	= exynos4_comp_set_mode,
318};
319
320static irqreturn_t exynos4_mct_comp_isr(int irq, void *dev_id)
321{
322	struct clock_event_device *evt = dev_id;
323
324	exynos4_mct_write(0x1, EXYNOS4_MCT_G_INT_CSTAT);
325
326	evt->event_handler(evt);
327
328	return IRQ_HANDLED;
329}
330
331static struct irqaction mct_comp_event_irq = {
332	.name		= "mct_comp_irq",
333	.flags		= IRQF_TIMER | IRQF_IRQPOLL,
334	.handler	= exynos4_mct_comp_isr,
335	.dev_id		= &mct_comp_device,
336};
337
338static void exynos4_clockevent_init(void)
339{
340	mct_comp_device.cpumask = cpumask_of(0);
341	clockevents_config_and_register(&mct_comp_device, clk_rate,
342					0xf, 0xffffffff);
343	setup_irq(mct_irqs[MCT_G0_IRQ], &mct_comp_event_irq);
344}
345
346static DEFINE_PER_CPU(struct mct_clock_event_device, percpu_mct_tick);
347
348/* Clock event handling */
349static void exynos4_mct_tick_stop(struct mct_clock_event_device *mevt)
350{
351	unsigned long tmp;
352	unsigned long mask = MCT_L_TCON_INT_START | MCT_L_TCON_TIMER_START;
353	unsigned long offset = mevt->base + MCT_L_TCON_OFFSET;
354
355	tmp = readl_relaxed(reg_base + offset);
356	if (tmp & mask) {
357		tmp &= ~mask;
358		exynos4_mct_write(tmp, offset);
359	}
360}
361
362static void exynos4_mct_tick_start(unsigned long cycles,
363				   struct mct_clock_event_device *mevt)
364{
365	unsigned long tmp;
366
367	exynos4_mct_tick_stop(mevt);
368
369	tmp = (1 << 31) | cycles;	/* MCT_L_UPDATE_ICNTB */
370
371	/* update interrupt count buffer */
372	exynos4_mct_write(tmp, mevt->base + MCT_L_ICNTB_OFFSET);
373
374	/* enable MCT tick interrupt */
375	exynos4_mct_write(0x1, mevt->base + MCT_L_INT_ENB_OFFSET);
376
377	tmp = readl_relaxed(reg_base + mevt->base + MCT_L_TCON_OFFSET);
378	tmp |= MCT_L_TCON_INT_START | MCT_L_TCON_TIMER_START |
379	       MCT_L_TCON_INTERVAL_MODE;
380	exynos4_mct_write(tmp, mevt->base + MCT_L_TCON_OFFSET);
381}
382
383static int exynos4_tick_set_next_event(unsigned long cycles,
384				       struct clock_event_device *evt)
385{
386	struct mct_clock_event_device *mevt = this_cpu_ptr(&percpu_mct_tick);
387
388	exynos4_mct_tick_start(cycles, mevt);
389
390	return 0;
391}
392
393static inline void exynos4_tick_set_mode(enum clock_event_mode mode,
394					 struct clock_event_device *evt)
395{
396	struct mct_clock_event_device *mevt = this_cpu_ptr(&percpu_mct_tick);
397	unsigned long cycles_per_jiffy;
398
399	exynos4_mct_tick_stop(mevt);
400
401	switch (mode) {
402	case CLOCK_EVT_MODE_PERIODIC:
403		cycles_per_jiffy =
404			(((unsigned long long) NSEC_PER_SEC / HZ * evt->mult) >> evt->shift);
405		exynos4_mct_tick_start(cycles_per_jiffy, mevt);
406		break;
407
408	case CLOCK_EVT_MODE_ONESHOT:
409	case CLOCK_EVT_MODE_UNUSED:
410	case CLOCK_EVT_MODE_SHUTDOWN:
411	case CLOCK_EVT_MODE_RESUME:
412		break;
413	}
414}
415
416static int exynos4_mct_tick_clear(struct mct_clock_event_device *mevt)
417{
418	struct clock_event_device *evt = &mevt->evt;
419
420	/*
421	 * This is for supporting oneshot mode.
422	 * Mct would generate interrupt periodically
423	 * without explicit stopping.
424	 */
425	if (evt->mode != CLOCK_EVT_MODE_PERIODIC)
426		exynos4_mct_tick_stop(mevt);
427
428	/* Clear the MCT tick interrupt */
429	if (readl_relaxed(reg_base + mevt->base + MCT_L_INT_CSTAT_OFFSET) & 1) {
430		exynos4_mct_write(0x1, mevt->base + MCT_L_INT_CSTAT_OFFSET);
431		return 1;
432	} else {
433		return 0;
434	}
435}
436
437static irqreturn_t exynos4_mct_tick_isr(int irq, void *dev_id)
438{
439	struct mct_clock_event_device *mevt = dev_id;
440	struct clock_event_device *evt = &mevt->evt;
441
442	exynos4_mct_tick_clear(mevt);
443
444	evt->event_handler(evt);
445
446	return IRQ_HANDLED;
447}
448
449static int exynos4_local_timer_setup(struct clock_event_device *evt)
450{
451	struct mct_clock_event_device *mevt;
452	unsigned int cpu = smp_processor_id();
453
454	mevt = container_of(evt, struct mct_clock_event_device, evt);
455
456	mevt->base = EXYNOS4_MCT_L_BASE(cpu);
457	snprintf(mevt->name, sizeof(mevt->name), "mct_tick%d", cpu);
458
459	evt->name = mevt->name;
460	evt->cpumask = cpumask_of(cpu);
461	evt->set_next_event = exynos4_tick_set_next_event;
462	evt->set_mode = exynos4_tick_set_mode;
463	evt->features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT;
464	evt->rating = 450;
465
466	exynos4_mct_write(TICK_BASE_CNT, mevt->base + MCT_L_TCNTB_OFFSET);
467
468	if (mct_int_type == MCT_INT_SPI) {
469		evt->irq = mct_irqs[MCT_L0_IRQ + cpu];
470		if (request_irq(evt->irq, exynos4_mct_tick_isr,
471				IRQF_TIMER | IRQF_NOBALANCING,
472				evt->name, mevt)) {
473			pr_err("exynos-mct: cannot register IRQ %d\n",
474				evt->irq);
475			return -EIO;
476		}
477		irq_force_affinity(mct_irqs[MCT_L0_IRQ + cpu], cpumask_of(cpu));
478	} else {
479		enable_percpu_irq(mct_irqs[MCT_L0_IRQ], 0);
480	}
481	clockevents_config_and_register(evt, clk_rate / (TICK_BASE_CNT + 1),
482					0xf, 0x7fffffff);
483
484	return 0;
485}
486
487static void exynos4_local_timer_stop(struct clock_event_device *evt)
488{
489	evt->set_mode(CLOCK_EVT_MODE_UNUSED, evt);
490	if (mct_int_type == MCT_INT_SPI)
491		free_irq(evt->irq, this_cpu_ptr(&percpu_mct_tick));
492	else
493		disable_percpu_irq(mct_irqs[MCT_L0_IRQ]);
494}
495
496static int exynos4_mct_cpu_notify(struct notifier_block *self,
497					   unsigned long action, void *hcpu)
498{
499	struct mct_clock_event_device *mevt;
500
501	/*
502	 * Grab cpu pointer in each case to avoid spurious
503	 * preemptible warnings
504	 */
505	switch (action & ~CPU_TASKS_FROZEN) {
506	case CPU_STARTING:
507		mevt = this_cpu_ptr(&percpu_mct_tick);
508		exynos4_local_timer_setup(&mevt->evt);
509		break;
510	case CPU_DYING:
511		mevt = this_cpu_ptr(&percpu_mct_tick);
512		exynos4_local_timer_stop(&mevt->evt);
513		break;
514	}
515
516	return NOTIFY_OK;
517}
518
519static struct notifier_block exynos4_mct_cpu_nb = {
520	.notifier_call = exynos4_mct_cpu_notify,
521};
522
523static void __init exynos4_timer_resources(struct device_node *np, void __iomem *base)
524{
525	int err;
526	struct mct_clock_event_device *mevt = this_cpu_ptr(&percpu_mct_tick);
527	struct clk *mct_clk, *tick_clk;
528
529	tick_clk = np ? of_clk_get_by_name(np, "fin_pll") :
530				clk_get(NULL, "fin_pll");
531	if (IS_ERR(tick_clk))
532		panic("%s: unable to determine tick clock rate\n", __func__);
533	clk_rate = clk_get_rate(tick_clk);
534
535	mct_clk = np ? of_clk_get_by_name(np, "mct") : clk_get(NULL, "mct");
536	if (IS_ERR(mct_clk))
537		panic("%s: unable to retrieve mct clock instance\n", __func__);
538	clk_prepare_enable(mct_clk);
539
540	reg_base = base;
541	if (!reg_base)
542		panic("%s: unable to ioremap mct address space\n", __func__);
543
544	if (mct_int_type == MCT_INT_PPI) {
545
546		err = request_percpu_irq(mct_irqs[MCT_L0_IRQ],
547					 exynos4_mct_tick_isr, "MCT",
548					 &percpu_mct_tick);
549		WARN(err, "MCT: can't request IRQ %d (%d)\n",
550		     mct_irqs[MCT_L0_IRQ], err);
551	} else {
552		irq_set_affinity(mct_irqs[MCT_L0_IRQ], cpumask_of(0));
553	}
554
555	err = register_cpu_notifier(&exynos4_mct_cpu_nb);
556	if (err)
557		goto out_irq;
558
559	/* Immediately configure the timer on the boot CPU */
560	exynos4_local_timer_setup(&mevt->evt);
561	return;
562
563out_irq:
564	free_percpu_irq(mct_irqs[MCT_L0_IRQ], &percpu_mct_tick);
565}
566
567void __init mct_init(void __iomem *base, int irq_g0, int irq_l0, int irq_l1)
568{
569	mct_irqs[MCT_G0_IRQ] = irq_g0;
570	mct_irqs[MCT_L0_IRQ] = irq_l0;
571	mct_irqs[MCT_L1_IRQ] = irq_l1;
572	mct_int_type = MCT_INT_SPI;
573
574	exynos4_timer_resources(NULL, base);
575	exynos4_clocksource_init();
576	exynos4_clockevent_init();
577}
578
579static void __init mct_init_dt(struct device_node *np, unsigned int int_type)
580{
581	u32 nr_irqs, i;
582
583	mct_int_type = int_type;
584
585	/* This driver uses only one global timer interrupt */
586	mct_irqs[MCT_G0_IRQ] = irq_of_parse_and_map(np, MCT_G0_IRQ);
587
588	/*
589	 * Find out the number of local irqs specified. The local
590	 * timer irqs are specified after the four global timer
591	 * irqs are specified.
592	 */
593#ifdef CONFIG_OF
594	nr_irqs = of_irq_count(np);
595#else
596	nr_irqs = 0;
597#endif
598	for (i = MCT_L0_IRQ; i < nr_irqs; i++)
599		mct_irqs[i] = irq_of_parse_and_map(np, i);
600
601	exynos4_timer_resources(np, of_iomap(np, 0));
602	exynos4_clocksource_init();
603	exynos4_clockevent_init();
604}
605
606
607static void __init mct_init_spi(struct device_node *np)
608{
609	return mct_init_dt(np, MCT_INT_SPI);
610}
611
612static void __init mct_init_ppi(struct device_node *np)
613{
614	return mct_init_dt(np, MCT_INT_PPI);
615}
616CLOCKSOURCE_OF_DECLARE(exynos4210, "samsung,exynos4210-mct", mct_init_spi);
617CLOCKSOURCE_OF_DECLARE(exynos4412, "samsung,exynos4412-mct", mct_init_ppi);
618