exynos_mct.c revision 89e6a13b88c8bf7ce1011a8a69113f22889f4585 
1/* linux/arch/arm/mach-exynos4/mct.c
2 *
3 * Copyright (c) 2011 Samsung Electronics Co., Ltd.
4 *		http://www.samsung.com
5 *
6 * EXYNOS4 MCT(Multi-Core Timer) support
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#include <linux/sched.h>
14#include <linux/interrupt.h>
15#include <linux/irq.h>
16#include <linux/err.h>
17#include <linux/clk.h>
18#include <linux/clockchips.h>
19#include <linux/cpu.h>
20#include <linux/platform_device.h>
21#include <linux/delay.h>
22#include <linux/percpu.h>
23#include <linux/of.h>
24#include <linux/of_irq.h>
25#include <linux/of_address.h>
26#include <linux/clocksource.h>
27#include <linux/sched_clock.h>
28
29#define EXYNOS4_MCTREG(x)		(x)
30#define EXYNOS4_MCT_G_CNT_L		EXYNOS4_MCTREG(0x100)
31#define EXYNOS4_MCT_G_CNT_U		EXYNOS4_MCTREG(0x104)
32#define EXYNOS4_MCT_G_CNT_WSTAT		EXYNOS4_MCTREG(0x110)
33#define EXYNOS4_MCT_G_COMP0_L		EXYNOS4_MCTREG(0x200)
34#define EXYNOS4_MCT_G_COMP0_U		EXYNOS4_MCTREG(0x204)
35#define EXYNOS4_MCT_G_COMP0_ADD_INCR	EXYNOS4_MCTREG(0x208)
36#define EXYNOS4_MCT_G_TCON		EXYNOS4_MCTREG(0x240)
37#define EXYNOS4_MCT_G_INT_CSTAT		EXYNOS4_MCTREG(0x244)
38#define EXYNOS4_MCT_G_INT_ENB		EXYNOS4_MCTREG(0x248)
39#define EXYNOS4_MCT_G_WSTAT		EXYNOS4_MCTREG(0x24C)
40#define _EXYNOS4_MCT_L_BASE		EXYNOS4_MCTREG(0x300)
41#define EXYNOS4_MCT_L_BASE(x)		(_EXYNOS4_MCT_L_BASE + (0x100 * x))
42#define EXYNOS4_MCT_L_MASK		(0xffffff00)
43
44#define MCT_L_TCNTB_OFFSET		(0x00)
45#define MCT_L_ICNTB_OFFSET		(0x08)
46#define MCT_L_TCON_OFFSET		(0x20)
47#define MCT_L_INT_CSTAT_OFFSET		(0x30)
48#define MCT_L_INT_ENB_OFFSET		(0x34)
49#define MCT_L_WSTAT_OFFSET		(0x40)
50#define MCT_G_TCON_START		(1 << 8)
51#define MCT_G_TCON_COMP0_AUTO_INC	(1 << 1)
52#define MCT_G_TCON_COMP0_ENABLE		(1 << 0)
53#define MCT_L_TCON_INTERVAL_MODE	(1 << 2)
54#define MCT_L_TCON_INT_START		(1 << 1)
55#define MCT_L_TCON_TIMER_START		(1 << 0)
56
57#define TICK_BASE_CNT	1
58
59enum {
60	MCT_INT_SPI,
61	MCT_INT_PPI
62};
63
64enum {
65	MCT_G0_IRQ,
66	MCT_G1_IRQ,
67	MCT_G2_IRQ,
68	MCT_G3_IRQ,
69	MCT_L0_IRQ,
70	MCT_L1_IRQ,
71	MCT_L2_IRQ,
72	MCT_L3_IRQ,
73	MCT_L4_IRQ,
74	MCT_L5_IRQ,
75	MCT_L6_IRQ,
76	MCT_L7_IRQ,
77	MCT_NR_IRQS,
78};
79
80static void __iomem *reg_base;
81static unsigned long clk_rate;
82static unsigned int mct_int_type;
83static int mct_irqs[MCT_NR_IRQS];
84
85struct mct_clock_event_device {
86	struct clock_event_device evt;
87	unsigned long base;
88	char name[10];
89};
90
91static void exynos4_mct_write(unsigned int value, unsigned long offset)
92{
93	unsigned long stat_addr;
94	u32 mask;
95	u32 i;
96
97	__raw_writel(value, reg_base + offset);
98
99	if (likely(offset >= EXYNOS4_MCT_L_BASE(0))) {
100		stat_addr = (offset & ~EXYNOS4_MCT_L_MASK) + MCT_L_WSTAT_OFFSET;
101		switch (offset & EXYNOS4_MCT_L_MASK) {
102		case MCT_L_TCON_OFFSET:
103			mask = 1 << 3;		/* L_TCON write status */
104			break;
105		case MCT_L_ICNTB_OFFSET:
106			mask = 1 << 1;		/* L_ICNTB write status */
107			break;
108		case MCT_L_TCNTB_OFFSET:
109			mask = 1 << 0;		/* L_TCNTB write status */
110			break;
111		default:
112			return;
113		}
114	} else {
115		switch (offset) {
116		case EXYNOS4_MCT_G_TCON:
117			stat_addr = EXYNOS4_MCT_G_WSTAT;
118			mask = 1 << 16;		/* G_TCON write status */
119			break;
120		case EXYNOS4_MCT_G_COMP0_L:
121			stat_addr = EXYNOS4_MCT_G_WSTAT;
122			mask = 1 << 0;		/* G_COMP0_L write status */
123			break;
124		case EXYNOS4_MCT_G_COMP0_U:
125			stat_addr = EXYNOS4_MCT_G_WSTAT;
126			mask = 1 << 1;		/* G_COMP0_U write status */
127			break;
128		case EXYNOS4_MCT_G_COMP0_ADD_INCR:
129			stat_addr = EXYNOS4_MCT_G_WSTAT;
130			mask = 1 << 2;		/* G_COMP0_ADD_INCR w status */
131			break;
132		case EXYNOS4_MCT_G_CNT_L:
133			stat_addr = EXYNOS4_MCT_G_CNT_WSTAT;
134			mask = 1 << 0;		/* G_CNT_L write status */
135			break;
136		case EXYNOS4_MCT_G_CNT_U:
137			stat_addr = EXYNOS4_MCT_G_CNT_WSTAT;
138			mask = 1 << 1;		/* G_CNT_U write status */
139			break;
140		default:
141			return;
142		}
143	}
144
145	/* Wait maximum 1 ms until written values are applied */
146	for (i = 0; i < loops_per_jiffy / 1000 * HZ; i++)
147		if (__raw_readl(reg_base + stat_addr) & mask) {
148			__raw_writel(mask, reg_base + stat_addr);
149			return;
150		}
151
152	panic("MCT hangs after writing %d (offset:0x%lx)\n", value, offset);
153}
154
155/* Clocksource handling */
156static void exynos4_mct_frc_start(void)
157{
158	u32 reg;
159
160	reg = __raw_readl(reg_base + EXYNOS4_MCT_G_TCON);
161	reg |= MCT_G_TCON_START;
162	exynos4_mct_write(reg, EXYNOS4_MCT_G_TCON);
163}
164
165static cycle_t notrace _exynos4_frc_read(void)
166{
167	unsigned int lo, hi;
168	u32 hi2 = __raw_readl(reg_base + EXYNOS4_MCT_G_CNT_U);
169
170	do {
171		hi = hi2;
172		lo = __raw_readl(reg_base + EXYNOS4_MCT_G_CNT_L);
173		hi2 = __raw_readl(reg_base + EXYNOS4_MCT_G_CNT_U);
174	} while (hi != hi2);
175
176	return ((cycle_t)hi << 32) | lo;
177}
178
179static cycle_t exynos4_frc_read(struct clocksource *cs)
180{
181	return _exynos4_frc_read();
182}
183
184static void exynos4_frc_resume(struct clocksource *cs)
185{
186	exynos4_mct_frc_start();
187}
188
189struct clocksource mct_frc = {
190	.name		= "mct-frc",
191	.rating		= 400,
192	.read		= exynos4_frc_read,
193	.mask		= CLOCKSOURCE_MASK(64),
194	.flags		= CLOCK_SOURCE_IS_CONTINUOUS,
195	.resume		= exynos4_frc_resume,
196};
197
198static u64 notrace exynos4_read_sched_clock(void)
199{
200	return _exynos4_frc_read();
201}
202
203static void __init exynos4_clocksource_init(void)
204{
205	exynos4_mct_frc_start();
206
207	if (clocksource_register_hz(&mct_frc, clk_rate))
208		panic("%s: can't register clocksource\n", mct_frc.name);
209
210	sched_clock_register(exynos4_read_sched_clock, 64, clk_rate);
211}
212
213static void exynos4_mct_comp0_stop(void)
214{
215	unsigned int tcon;
216
217	tcon = __raw_readl(reg_base + EXYNOS4_MCT_G_TCON);
218	tcon &= ~(MCT_G_TCON_COMP0_ENABLE | MCT_G_TCON_COMP0_AUTO_INC);
219
220	exynos4_mct_write(tcon, EXYNOS4_MCT_G_TCON);
221	exynos4_mct_write(0, EXYNOS4_MCT_G_INT_ENB);
222}
223
224static void exynos4_mct_comp0_start(enum clock_event_mode mode,
225				    unsigned long cycles)
226{
227	unsigned int tcon;
228	cycle_t comp_cycle;
229
230	tcon = __raw_readl(reg_base + EXYNOS4_MCT_G_TCON);
231
232	if (mode == CLOCK_EVT_MODE_PERIODIC) {
233		tcon |= MCT_G_TCON_COMP0_AUTO_INC;
234		exynos4_mct_write(cycles, EXYNOS4_MCT_G_COMP0_ADD_INCR);
235	}
236
237	comp_cycle = exynos4_frc_read(&mct_frc) + cycles;
238	exynos4_mct_write((u32)comp_cycle, EXYNOS4_MCT_G_COMP0_L);
239	exynos4_mct_write((u32)(comp_cycle >> 32), EXYNOS4_MCT_G_COMP0_U);
240
241	exynos4_mct_write(0x1, EXYNOS4_MCT_G_INT_ENB);
242
243	tcon |= MCT_G_TCON_COMP0_ENABLE;
244	exynos4_mct_write(tcon , EXYNOS4_MCT_G_TCON);
245}
246
247static int exynos4_comp_set_next_event(unsigned long cycles,
248				       struct clock_event_device *evt)
249{
250	exynos4_mct_comp0_start(evt->mode, cycles);
251
252	return 0;
253}
254
255static void exynos4_comp_set_mode(enum clock_event_mode mode,
256				  struct clock_event_device *evt)
257{
258	unsigned long cycles_per_jiffy;
259	exynos4_mct_comp0_stop();
260
261	switch (mode) {
262	case CLOCK_EVT_MODE_PERIODIC:
263		cycles_per_jiffy =
264			(((unsigned long long) NSEC_PER_SEC / HZ * evt->mult) >> evt->shift);
265		exynos4_mct_comp0_start(mode, cycles_per_jiffy);
266		break;
267
268	case CLOCK_EVT_MODE_ONESHOT:
269	case CLOCK_EVT_MODE_UNUSED:
270	case CLOCK_EVT_MODE_SHUTDOWN:
271	case CLOCK_EVT_MODE_RESUME:
272		break;
273	}
274}
275
276static struct clock_event_device mct_comp_device = {
277	.name		= "mct-comp",
278	.features       = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
279	.rating		= 250,
280	.set_next_event	= exynos4_comp_set_next_event,
281	.set_mode	= exynos4_comp_set_mode,
282};
283
284static irqreturn_t exynos4_mct_comp_isr(int irq, void *dev_id)
285{
286	struct clock_event_device *evt = dev_id;
287
288	exynos4_mct_write(0x1, EXYNOS4_MCT_G_INT_CSTAT);
289
290	evt->event_handler(evt);
291
292	return IRQ_HANDLED;
293}
294
295static struct irqaction mct_comp_event_irq = {
296	.name		= "mct_comp_irq",
297	.flags		= IRQF_TIMER | IRQF_IRQPOLL,
298	.handler	= exynos4_mct_comp_isr,
299	.dev_id		= &mct_comp_device,
300};
301
302static void exynos4_clockevent_init(void)
303{
304	mct_comp_device.cpumask = cpumask_of(0);
305	clockevents_config_and_register(&mct_comp_device, clk_rate,
306					0xf, 0xffffffff);
307	setup_irq(mct_irqs[MCT_G0_IRQ], &mct_comp_event_irq);
308}
309
310static DEFINE_PER_CPU(struct mct_clock_event_device, percpu_mct_tick);
311
312/* Clock event handling */
313static void exynos4_mct_tick_stop(struct mct_clock_event_device *mevt)
314{
315	unsigned long tmp;
316	unsigned long mask = MCT_L_TCON_INT_START | MCT_L_TCON_TIMER_START;
317	unsigned long offset = mevt->base + MCT_L_TCON_OFFSET;
318
319	tmp = __raw_readl(reg_base + offset);
320	if (tmp & mask) {
321		tmp &= ~mask;
322		exynos4_mct_write(tmp, offset);
323	}
324}
325
326static void exynos4_mct_tick_start(unsigned long cycles,
327				   struct mct_clock_event_device *mevt)
328{
329	unsigned long tmp;
330
331	exynos4_mct_tick_stop(mevt);
332
333	tmp = (1 << 31) | cycles;	/* MCT_L_UPDATE_ICNTB */
334
335	/* update interrupt count buffer */
336	exynos4_mct_write(tmp, mevt->base + MCT_L_ICNTB_OFFSET);
337
338	/* enable MCT tick interrupt */
339	exynos4_mct_write(0x1, mevt->base + MCT_L_INT_ENB_OFFSET);
340
341	tmp = __raw_readl(reg_base + mevt->base + MCT_L_TCON_OFFSET);
342	tmp |= MCT_L_TCON_INT_START | MCT_L_TCON_TIMER_START |
343	       MCT_L_TCON_INTERVAL_MODE;
344	exynos4_mct_write(tmp, mevt->base + MCT_L_TCON_OFFSET);
345}
346
347static int exynos4_tick_set_next_event(unsigned long cycles,
348				       struct clock_event_device *evt)
349{
350	struct mct_clock_event_device *mevt = this_cpu_ptr(&percpu_mct_tick);
351
352	exynos4_mct_tick_start(cycles, mevt);
353
354	return 0;
355}
356
357static inline void exynos4_tick_set_mode(enum clock_event_mode mode,
358					 struct clock_event_device *evt)
359{
360	struct mct_clock_event_device *mevt = this_cpu_ptr(&percpu_mct_tick);
361	unsigned long cycles_per_jiffy;
362
363	exynos4_mct_tick_stop(mevt);
364
365	switch (mode) {
366	case CLOCK_EVT_MODE_PERIODIC:
367		cycles_per_jiffy =
368			(((unsigned long long) NSEC_PER_SEC / HZ * evt->mult) >> evt->shift);
369		exynos4_mct_tick_start(cycles_per_jiffy, mevt);
370		break;
371
372	case CLOCK_EVT_MODE_ONESHOT:
373	case CLOCK_EVT_MODE_UNUSED:
374	case CLOCK_EVT_MODE_SHUTDOWN:
375	case CLOCK_EVT_MODE_RESUME:
376		break;
377	}
378}
379
380static int exynos4_mct_tick_clear(struct mct_clock_event_device *mevt)
381{
382	struct clock_event_device *evt = &mevt->evt;
383
384	/*
385	 * This is for supporting oneshot mode.
386	 * Mct would generate interrupt periodically
387	 * without explicit stopping.
388	 */
389	if (evt->mode != CLOCK_EVT_MODE_PERIODIC)
390		exynos4_mct_tick_stop(mevt);
391
392	/* Clear the MCT tick interrupt */
393	if (__raw_readl(reg_base + mevt->base + MCT_L_INT_CSTAT_OFFSET) & 1) {
394		exynos4_mct_write(0x1, mevt->base + MCT_L_INT_CSTAT_OFFSET);
395		return 1;
396	} else {
397		return 0;
398	}
399}
400
401static irqreturn_t exynos4_mct_tick_isr(int irq, void *dev_id)
402{
403	struct mct_clock_event_device *mevt = dev_id;
404	struct clock_event_device *evt = &mevt->evt;
405
406	exynos4_mct_tick_clear(mevt);
407
408	evt->event_handler(evt);
409
410	return IRQ_HANDLED;
411}
412
413static int exynos4_local_timer_setup(struct clock_event_device *evt)
414{
415	struct mct_clock_event_device *mevt;
416	unsigned int cpu = smp_processor_id();
417
418	mevt = container_of(evt, struct mct_clock_event_device, evt);
419
420	mevt->base = EXYNOS4_MCT_L_BASE(cpu);
421	snprintf(mevt->name, sizeof(mevt->name), "mct_tick%d", cpu);
422
423	evt->name = mevt->name;
424	evt->cpumask = cpumask_of(cpu);
425	evt->set_next_event = exynos4_tick_set_next_event;
426	evt->set_mode = exynos4_tick_set_mode;
427	evt->features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT;
428	evt->rating = 450;
429
430	exynos4_mct_write(TICK_BASE_CNT, mevt->base + MCT_L_TCNTB_OFFSET);
431
432	if (mct_int_type == MCT_INT_SPI) {
433		evt->irq = mct_irqs[MCT_L0_IRQ + cpu];
434		if (request_irq(evt->irq, exynos4_mct_tick_isr,
435				IRQF_TIMER | IRQF_NOBALANCING,
436				evt->name, mevt)) {
437			pr_err("exynos-mct: cannot register IRQ %d\n",
438				evt->irq);
439			return -EIO;
440		}
441		irq_force_affinity(mct_irqs[MCT_L0_IRQ + cpu], cpumask_of(cpu));
442	} else {
443		enable_percpu_irq(mct_irqs[MCT_L0_IRQ], 0);
444	}
445	clockevents_config_and_register(evt, clk_rate / (TICK_BASE_CNT + 1),
446					0xf, 0x7fffffff);
447
448	return 0;
449}
450
451static void exynos4_local_timer_stop(struct clock_event_device *evt)
452{
453	evt->set_mode(CLOCK_EVT_MODE_UNUSED, evt);
454	if (mct_int_type == MCT_INT_SPI)
455		free_irq(evt->irq, this_cpu_ptr(&percpu_mct_tick));
456	else
457		disable_percpu_irq(mct_irqs[MCT_L0_IRQ]);
458}
459
460static int exynos4_mct_cpu_notify(struct notifier_block *self,
461					   unsigned long action, void *hcpu)
462{
463	struct mct_clock_event_device *mevt;
464
465	/*
466	 * Grab cpu pointer in each case to avoid spurious
467	 * preemptible warnings
468	 */
469	switch (action & ~CPU_TASKS_FROZEN) {
470	case CPU_STARTING:
471		mevt = this_cpu_ptr(&percpu_mct_tick);
472		exynos4_local_timer_setup(&mevt->evt);
473		break;
474	case CPU_DYING:
475		mevt = this_cpu_ptr(&percpu_mct_tick);
476		exynos4_local_timer_stop(&mevt->evt);
477		break;
478	}
479
480	return NOTIFY_OK;
481}
482
483static struct notifier_block exynos4_mct_cpu_nb = {
484	.notifier_call = exynos4_mct_cpu_notify,
485};
486
487static void __init exynos4_timer_resources(struct device_node *np, void __iomem *base)
488{
489	int err;
490	struct mct_clock_event_device *mevt = this_cpu_ptr(&percpu_mct_tick);
491	struct clk *mct_clk, *tick_clk;
492
493	tick_clk = np ? of_clk_get_by_name(np, "fin_pll") :
494				clk_get(NULL, "fin_pll");
495	if (IS_ERR(tick_clk))
496		panic("%s: unable to determine tick clock rate\n", __func__);
497	clk_rate = clk_get_rate(tick_clk);
498
499	mct_clk = np ? of_clk_get_by_name(np, "mct") : clk_get(NULL, "mct");
500	if (IS_ERR(mct_clk))
501		panic("%s: unable to retrieve mct clock instance\n", __func__);
502	clk_prepare_enable(mct_clk);
503
504	reg_base = base;
505	if (!reg_base)
506		panic("%s: unable to ioremap mct address space\n", __func__);
507
508	if (mct_int_type == MCT_INT_PPI) {
509
510		err = request_percpu_irq(mct_irqs[MCT_L0_IRQ],
511					 exynos4_mct_tick_isr, "MCT",
512					 &percpu_mct_tick);
513		WARN(err, "MCT: can't request IRQ %d (%d)\n",
514		     mct_irqs[MCT_L0_IRQ], err);
515	} else {
516		irq_set_affinity(mct_irqs[MCT_L0_IRQ], cpumask_of(0));
517	}
518
519	err = register_cpu_notifier(&exynos4_mct_cpu_nb);
520	if (err)
521		goto out_irq;
522
523	/* Immediately configure the timer on the boot CPU */
524	exynos4_local_timer_setup(&mevt->evt);
525	return;
526
527out_irq:
528	free_percpu_irq(mct_irqs[MCT_L0_IRQ], &percpu_mct_tick);
529}
530
531void __init mct_init(void __iomem *base, int irq_g0, int irq_l0, int irq_l1)
532{
533	mct_irqs[MCT_G0_IRQ] = irq_g0;
534	mct_irqs[MCT_L0_IRQ] = irq_l0;
535	mct_irqs[MCT_L1_IRQ] = irq_l1;
536	mct_int_type = MCT_INT_SPI;
537
538	exynos4_timer_resources(NULL, base);
539	exynos4_clocksource_init();
540	exynos4_clockevent_init();
541}
542
543static void __init mct_init_dt(struct device_node *np, unsigned int int_type)
544{
545	u32 nr_irqs, i;
546
547	mct_int_type = int_type;
548
549	/* This driver uses only one global timer interrupt */
550	mct_irqs[MCT_G0_IRQ] = irq_of_parse_and_map(np, MCT_G0_IRQ);
551
552	/*
553	 * Find out the number of local irqs specified. The local
554	 * timer irqs are specified after the four global timer
555	 * irqs are specified.
556	 */
557#ifdef CONFIG_OF
558	nr_irqs = of_irq_count(np);
559#else
560	nr_irqs = 0;
561#endif
562	for (i = MCT_L0_IRQ; i < nr_irqs; i++)
563		mct_irqs[i] = irq_of_parse_and_map(np, i);
564
565	exynos4_timer_resources(np, of_iomap(np, 0));
566	exynos4_clocksource_init();
567	exynos4_clockevent_init();
568}
569
570
571static void __init mct_init_spi(struct device_node *np)
572{
573	return mct_init_dt(np, MCT_INT_SPI);
574}
575
576static void __init mct_init_ppi(struct device_node *np)
577{
578	return mct_init_dt(np, MCT_INT_PPI);
579}
580CLOCKSOURCE_OF_DECLARE(exynos4210, "samsung,exynos4210-mct", mct_init_spi);
581CLOCKSOURCE_OF_DECLARE(exynos4412, "samsung,exynos4412-mct", mct_init_ppi);
582