cris-artpec3-cpufreq.c revision 361db10f61b1d113eadd1b7b1db5f16f63c4eb49 
1#include <linux/init.h>
2#include <linux/module.h>
3#include <linux/cpufreq.h>
4#include <hwregs/reg_map.h>
5#include <hwregs/reg_rdwr.h>
6#include <hwregs/clkgen_defs.h>
7#include <hwregs/ddr2_defs.h>
8
9static int
10cris_sdram_freq_notifier(struct notifier_block *nb, unsigned long val,
11	void *data);
12
13static struct notifier_block cris_sdram_freq_notifier_block = {
14	.notifier_call = cris_sdram_freq_notifier
15};
16
17static struct cpufreq_frequency_table cris_freq_table[] = {
18	{0x01,	6000},
19	{0x02,	200000},
20	{0,	CPUFREQ_TABLE_END},
21};
22
23static unsigned int cris_freq_get_cpu_frequency(unsigned int cpu)
24{
25	reg_clkgen_rw_clk_ctrl clk_ctrl;
26	clk_ctrl = REG_RD(clkgen, regi_clkgen, rw_clk_ctrl);
27	return clk_ctrl.pll ? 200000 : 6000;
28}
29
30static void cris_freq_set_cpu_state(struct cpufreq_policy *policy,
31		unsigned int state)
32{
33	struct cpufreq_freqs freqs;
34	reg_clkgen_rw_clk_ctrl clk_ctrl;
35	clk_ctrl = REG_RD(clkgen, regi_clkgen, rw_clk_ctrl);
36
37	freqs.old = cris_freq_get_cpu_frequency(policy->cpu);
38	freqs.new = cris_freq_table[state].frequency;
39
40	cpufreq_notify_transition(policy, &freqs, CPUFREQ_PRECHANGE);
41
42	local_irq_disable();
43
44	/* Even though we may be SMP they will share the same clock
45	 * so all settings are made on CPU0. */
46	if (cris_freq_table[state].frequency == 200000)
47		clk_ctrl.pll = 1;
48	else
49		clk_ctrl.pll = 0;
50	REG_WR(clkgen, regi_clkgen, rw_clk_ctrl, clk_ctrl);
51
52	local_irq_enable();
53
54	cpufreq_notify_transition(policy, &freqs, CPUFREQ_POSTCHANGE);
55};
56
57static int cris_freq_target(struct cpufreq_policy *policy,
58			    unsigned int target_freq,
59			    unsigned int relation)
60{
61	unsigned int newstate = 0;
62
63	if (cpufreq_frequency_table_target(policy, cris_freq_table,
64			target_freq, relation, &newstate))
65		return -EINVAL;
66
67	cris_freq_set_cpu_state(policy, newstate);
68
69	return 0;
70}
71
72static int cris_freq_cpu_init(struct cpufreq_policy *policy)
73{
74	/* cpuinfo and default policy values */
75	policy->cpuinfo.transition_latency = 1000000; /* 1ms */
76	policy->cur = cris_freq_get_cpu_frequency(0);
77
78	return cpufreq_table_validate_and_show(policy, cris_freq_table);
79}
80
81
82static struct cpufreq_driver cris_freq_driver = {
83	.get	= cris_freq_get_cpu_frequency,
84	.verify	= cpufreq_generic_frequency_table_verify,
85	.target	= cris_freq_target,
86	.init	= cris_freq_cpu_init,
87	.exit	= cpufreq_generic_exit,
88	.name	= "cris_freq",
89	.attr	= cpufreq_generic_attr,
90};
91
92static int __init cris_freq_init(void)
93{
94	int ret;
95	ret = cpufreq_register_driver(&cris_freq_driver);
96	cpufreq_register_notifier(&cris_sdram_freq_notifier_block,
97		CPUFREQ_TRANSITION_NOTIFIER);
98	return ret;
99}
100
101static int
102cris_sdram_freq_notifier(struct notifier_block *nb, unsigned long val,
103	void *data)
104{
105	int i;
106	struct cpufreq_freqs *freqs = data;
107	if (val == CPUFREQ_PRECHANGE) {
108		reg_ddr2_rw_cfg cfg =
109		  REG_RD(ddr2, regi_ddr2_ctrl, rw_cfg);
110		cfg.ref_interval = (freqs->new == 200000 ? 1560 : 46);
111
112		if (freqs->new == 200000)
113			for (i = 0; i < 50000; i++);
114		REG_WR(bif_core, regi_bif_core, rw_sdram_timing, timing);
115	}
116	return 0;
117}
118
119
120module_init(cris_freq_init);
121