exynos5250-cpufreq.c revision 184cddd1e004d3ebd473f9e1ce20dec1d2576fd1 
1/*
2 * Copyright (c) 2010-20122Samsung Electronics Co., Ltd.
3 *		http://www.samsung.com
4 *
5 * EXYNOS5250 - CPU frequency scaling support
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10*/
11
12#include <linux/module.h>
13#include <linux/kernel.h>
14#include <linux/err.h>
15#include <linux/clk.h>
16#include <linux/io.h>
17#include <linux/slab.h>
18#include <linux/cpufreq.h>
19
20#include <mach/map.h>
21#include <mach/regs-clock.h>
22#include <mach/cpufreq.h>
23
24#define CPUFREQ_LEVEL_END	(L15 + 1)
25
26static struct clk *cpu_clk;
27static struct clk *moutcore;
28static struct clk *mout_mpll;
29static struct clk *mout_apll;
30
31struct cpufreq_clkdiv {
32	unsigned int	index;
33	unsigned int	clkdiv;
34	unsigned int	clkdiv1;
35};
36
37static unsigned int exynos5250_volt_table[CPUFREQ_LEVEL_END];
38
39static struct cpufreq_frequency_table exynos5250_freq_table[] = {
40	{L0, 1700 * 1000},
41	{L1, 1600 * 1000},
42	{L2, 1500 * 1000},
43	{L3, 1400 * 1000},
44	{L4, 1300 * 1000},
45	{L5, 1200 * 1000},
46	{L6, 1100 * 1000},
47	{L7, 1000 * 1000},
48	{L8, 900 * 1000},
49	{L9, 800 * 1000},
50	{L10, 700 * 1000},
51	{L11, 600 * 1000},
52	{L12, 500 * 1000},
53	{L13, 400 * 1000},
54	{L14, 300 * 1000},
55	{L15, 200 * 1000},
56	{0, CPUFREQ_TABLE_END},
57};
58
59static struct cpufreq_clkdiv exynos5250_clkdiv_table[CPUFREQ_LEVEL_END];
60
61static unsigned int clkdiv_cpu0_5250[CPUFREQ_LEVEL_END][8] = {
62	/*
63	 * Clock divider value for following
64	 * { ARM, CPUD, ACP, PERIPH, ATB, PCLK_DBG, APLL, ARM2 }
65	 */
66	{ 0, 3, 7, 7, 7, 3, 5, 0 },	/* 1700 MHz */
67	{ 0, 3, 7, 7, 7, 1, 4, 0 },	/* 1600 MHz */
68	{ 0, 2, 7, 7, 7, 1, 4, 0 },	/* 1500 MHz */
69	{ 0, 2, 7, 7, 6, 1, 4, 0 },	/* 1400 MHz */
70	{ 0, 2, 7, 7, 6, 1, 3, 0 },	/* 1300 MHz */
71	{ 0, 2, 7, 7, 5, 1, 3, 0 },	/* 1200 MHz */
72	{ 0, 3, 7, 7, 5, 1, 3, 0 },	/* 1100 MHz */
73	{ 0, 1, 7, 7, 4, 1, 2, 0 },	/* 1000 MHz */
74	{ 0, 1, 7, 7, 4, 1, 2, 0 },	/* 900 MHz */
75	{ 0, 1, 7, 7, 4, 1, 2, 0 },	/* 800 MHz */
76	{ 0, 1, 7, 7, 3, 1, 1, 0 },	/* 700 MHz */
77	{ 0, 1, 7, 7, 3, 1, 1, 0 },	/* 600 MHz */
78	{ 0, 1, 7, 7, 2, 1, 1, 0 },	/* 500 MHz */
79	{ 0, 1, 7, 7, 2, 1, 1, 0 },	/* 400 MHz */
80	{ 0, 1, 7, 7, 1, 1, 1, 0 },	/* 300 MHz */
81	{ 0, 1, 7, 7, 1, 1, 1, 0 },	/* 200 MHz */
82};
83
84static unsigned int clkdiv_cpu1_5250[CPUFREQ_LEVEL_END][2] = {
85	/* Clock divider value for following
86	 * { COPY, HPM }
87	 */
88	{ 0, 2 },	/* 1700 MHz */
89	{ 0, 2 },	/* 1600 MHz */
90	{ 0, 2 },	/* 1500 MHz */
91	{ 0, 2 },	/* 1400 MHz */
92	{ 0, 2 },	/* 1300 MHz */
93	{ 0, 2 },	/* 1200 MHz */
94	{ 0, 2 },	/* 1100 MHz */
95	{ 0, 2 },	/* 1000 MHz */
96	{ 0, 2 },	/* 900 MHz */
97	{ 0, 2 },	/* 800 MHz */
98	{ 0, 2 },	/* 700 MHz */
99	{ 0, 2 },	/* 600 MHz */
100	{ 0, 2 },	/* 500 MHz */
101	{ 0, 2 },	/* 400 MHz */
102	{ 0, 2 },	/* 300 MHz */
103	{ 0, 2 },	/* 200 MHz */
104};
105
106static unsigned int exynos5_apll_pms_table[CPUFREQ_LEVEL_END] = {
107	((425 << 16) | (6 << 8) | 0),	/* 1700 MHz */
108	((200 << 16) | (3 << 8) | 0),	/* 1600 MHz */
109	((250 << 16) | (4 << 8) | 0),	/* 1500 MHz */
110	((175 << 16) | (3 << 8) | 0),	/* 1400 MHz */
111	((325 << 16) | (6 << 8) | 0),	/* 1300 MHz */
112	((200 << 16) | (4 << 8) | 0),	/* 1200 MHz */
113	((275 << 16) | (6 << 8) | 0),	/* 1100 MHz */
114	((125 << 16) | (3 << 8) | 0),	/* 1000 MHz */
115	((150 << 16) | (4 << 8) | 0),	/* 900 MHz */
116	((100 << 16) | (3 << 8) | 0),	/* 800 MHz */
117	((175 << 16) | (3 << 8) | 1),	/* 700 MHz */
118	((200 << 16) | (4 << 8) | 1),	/* 600 MHz */
119	((125 << 16) | (3 << 8) | 1),	/* 500 MHz */
120	((100 << 16) | (3 << 8) | 1),	/* 400 MHz */
121	((200 << 16) | (4 << 8) | 2),	/* 300 MHz */
122	((100 << 16) | (3 << 8) | 2),	/* 200 MHz */
123};
124
125/* ASV group voltage table */
126static const unsigned int asv_voltage_5250[CPUFREQ_LEVEL_END] = {
127	1300000, 1250000, 1225000, 1200000, 1150000,
128	1125000, 1100000, 1075000, 1050000, 1025000,
129	1012500, 1000000,  975000,  950000,  937500,
130	925000
131};
132
133static void set_clkdiv(unsigned int div_index)
134{
135	unsigned int tmp;
136
137	/* Change Divider - CPU0 */
138
139	tmp = exynos5250_clkdiv_table[div_index].clkdiv;
140
141	__raw_writel(tmp, EXYNOS5_CLKDIV_CPU0);
142
143	while (__raw_readl(EXYNOS5_CLKDIV_STATCPU0) & 0x11111111)
144		cpu_relax();
145
146	/* Change Divider - CPU1 */
147	tmp = exynos5250_clkdiv_table[div_index].clkdiv1;
148
149	__raw_writel(tmp, EXYNOS5_CLKDIV_CPU1);
150
151	while (__raw_readl(EXYNOS5_CLKDIV_STATCPU1) & 0x11)
152		cpu_relax();
153}
154
155static void set_apll(unsigned int new_index,
156			     unsigned int old_index)
157{
158	unsigned int tmp, pdiv;
159
160	/* 1. MUX_CORE_SEL = MPLL, ARMCLK uses MPLL for lock time */
161	clk_set_parent(moutcore, mout_mpll);
162
163	do {
164		cpu_relax();
165		tmp = (__raw_readl(EXYNOS5_CLKMUX_STATCPU) >> 16);
166		tmp &= 0x7;
167	} while (tmp != 0x2);
168
169	/* 2. Set APLL Lock time */
170	pdiv = ((exynos5_apll_pms_table[new_index] >> 8) & 0x3f);
171
172	__raw_writel((pdiv * 250), EXYNOS5_APLL_LOCK);
173
174	/* 3. Change PLL PMS values */
175	tmp = __raw_readl(EXYNOS5_APLL_CON0);
176	tmp &= ~((0x3ff << 16) | (0x3f << 8) | (0x7 << 0));
177	tmp |= exynos5_apll_pms_table[new_index];
178	__raw_writel(tmp, EXYNOS5_APLL_CON0);
179
180	/* 4. wait_lock_time */
181	do {
182		cpu_relax();
183		tmp = __raw_readl(EXYNOS5_APLL_CON0);
184	} while (!(tmp & (0x1 << 29)));
185
186	/* 5. MUX_CORE_SEL = APLL */
187	clk_set_parent(moutcore, mout_apll);
188
189	do {
190		cpu_relax();
191		tmp = __raw_readl(EXYNOS5_CLKMUX_STATCPU);
192		tmp &= (0x7 << 16);
193	} while (tmp != (0x1 << 16));
194
195}
196
197bool exynos5250_pms_change(unsigned int old_index, unsigned int new_index)
198{
199	unsigned int old_pm = (exynos5_apll_pms_table[old_index] >> 8);
200	unsigned int new_pm = (exynos5_apll_pms_table[new_index] >> 8);
201
202	return (old_pm == new_pm) ? 0 : 1;
203}
204
205static void exynos5250_set_frequency(unsigned int old_index,
206				  unsigned int new_index)
207{
208	unsigned int tmp;
209
210	if (old_index > new_index) {
211		if (!exynos5250_pms_change(old_index, new_index)) {
212			/* 1. Change the system clock divider values */
213			set_clkdiv(new_index);
214			/* 2. Change just s value in apll m,p,s value */
215			tmp = __raw_readl(EXYNOS5_APLL_CON0);
216			tmp &= ~(0x7 << 0);
217			tmp |= (exynos5_apll_pms_table[new_index] & 0x7);
218			__raw_writel(tmp, EXYNOS5_APLL_CON0);
219
220		} else {
221			/* Clock Configuration Procedure */
222			/* 1. Change the system clock divider values */
223			set_clkdiv(new_index);
224			/* 2. Change the apll m,p,s value */
225			set_apll(new_index, old_index);
226		}
227	} else if (old_index < new_index) {
228		if (!exynos5250_pms_change(old_index, new_index)) {
229			/* 1. Change just s value in apll m,p,s value */
230			tmp = __raw_readl(EXYNOS5_APLL_CON0);
231			tmp &= ~(0x7 << 0);
232			tmp |= (exynos5_apll_pms_table[new_index] & 0x7);
233			__raw_writel(tmp, EXYNOS5_APLL_CON0);
234			/* 2. Change the system clock divider values */
235			set_clkdiv(new_index);
236		} else {
237			/* Clock Configuration Procedure */
238			/* 1. Change the apll m,p,s value */
239			set_apll(new_index, old_index);
240			/* 2. Change the system clock divider values */
241			set_clkdiv(new_index);
242		}
243	}
244}
245
246static void __init set_volt_table(void)
247{
248	unsigned int i;
249
250	for (i = 0 ; i < CPUFREQ_LEVEL_END ; i++)
251		exynos5250_volt_table[i] = asv_voltage_5250[i];
252}
253
254int exynos5250_cpufreq_init(struct exynos_dvfs_info *info)
255{
256	int i;
257	unsigned int tmp;
258	unsigned long rate;
259
260	set_volt_table();
261
262	cpu_clk = clk_get(NULL, "armclk");
263	if (IS_ERR(cpu_clk))
264		return PTR_ERR(cpu_clk);
265
266	moutcore = clk_get(NULL, "mout_cpu");
267	if (IS_ERR(moutcore))
268		goto err_moutcore;
269
270	mout_mpll = clk_get(NULL, "mout_mpll");
271	if (IS_ERR(mout_mpll))
272		goto err_mout_mpll;
273
274	rate = clk_get_rate(mout_mpll) / 1000;
275
276	mout_apll = clk_get(NULL, "mout_apll");
277	if (IS_ERR(mout_apll))
278		goto err_mout_apll;
279
280	for (i = L0; i < CPUFREQ_LEVEL_END; i++) {
281
282		exynos5250_clkdiv_table[i].index = i;
283
284		tmp = __raw_readl(EXYNOS5_CLKDIV_CPU0);
285
286		tmp &= ~((0x7 << 0) | (0x7 << 4) | (0x7 << 8) |
287			(0x7 << 12) | (0x7 << 16) | (0x7 << 20) |
288			(0x7 << 24) | (0x7 << 28));
289
290		tmp |= ((clkdiv_cpu0_5250[i][0] << 0) |
291			(clkdiv_cpu0_5250[i][1] << 4) |
292			(clkdiv_cpu0_5250[i][2] << 8) |
293			(clkdiv_cpu0_5250[i][3] << 12) |
294			(clkdiv_cpu0_5250[i][4] << 16) |
295			(clkdiv_cpu0_5250[i][5] << 20) |
296			(clkdiv_cpu0_5250[i][6] << 24) |
297			(clkdiv_cpu0_5250[i][7] << 28));
298
299		exynos5250_clkdiv_table[i].clkdiv = tmp;
300
301		tmp = __raw_readl(EXYNOS5_CLKDIV_CPU1);
302
303		tmp &= ~((0x7 << 0) | (0x7 << 4));
304
305		tmp |= ((clkdiv_cpu1_5250[i][0] << 0) |
306			(clkdiv_cpu1_5250[i][1] << 4));
307
308		exynos5250_clkdiv_table[i].clkdiv1 = tmp;
309	}
310
311	info->mpll_freq_khz = rate;
312	/* 800Mhz */
313	info->pll_safe_idx = L9;
314	info->cpu_clk = cpu_clk;
315	info->volt_table = exynos5250_volt_table;
316	info->freq_table = exynos5250_freq_table;
317	info->set_freq = exynos5250_set_frequency;
318	info->need_apll_change = exynos5250_pms_change;
319
320	return 0;
321
322err_mout_apll:
323	clk_put(mout_mpll);
324err_mout_mpll:
325	clk_put(moutcore);
326err_moutcore:
327	clk_put(cpu_clk);
328
329	pr_err("%s: failed initialization\n", __func__);
330	return -EINVAL;
331}
332EXPORT_SYMBOL(exynos5250_cpufreq_init);
333