powernow-k8.c revision a2060958569a8e8e36202c373a55c458ff84856d
1/* 2 * (c) 2003-2012 Advanced Micro Devices, Inc. 3 * Your use of this code is subject to the terms and conditions of the 4 * GNU general public license version 2. See "COPYING" or 5 * http://www.gnu.org/licenses/gpl.html 6 * 7 * Maintainer: 8 * Andreas Herrmann <andreas.herrmann3@amd.com> 9 * 10 * Based on the powernow-k7.c module written by Dave Jones. 11 * (C) 2003 Dave Jones on behalf of SuSE Labs 12 * (C) 2004 Dominik Brodowski <linux@brodo.de> 13 * (C) 2004 Pavel Machek <pavel@ucw.cz> 14 * Licensed under the terms of the GNU GPL License version 2. 15 * Based upon datasheets & sample CPUs kindly provided by AMD. 16 * 17 * Valuable input gratefully received from Dave Jones, Pavel Machek, 18 * Dominik Brodowski, Jacob Shin, and others. 19 * Originally developed by Paul Devriendt. 20 * 21 * Processor information obtained from Chapter 9 (Power and Thermal 22 * Management) of the "BIOS and Kernel Developer's Guide (BKDG) for 23 * the AMD Athlon 64 and AMD Opteron Processors" and section "2.x 24 * Power Management" in BKDGs for newer AMD CPU families. 25 * 26 * Tables for specific CPUs can be inferred from AMD's processor 27 * power and thermal data sheets, (e.g. 30417.pdf, 30430.pdf, 43375.pdf) 28 */ 29 30#include <linux/kernel.h> 31#include <linux/smp.h> 32#include <linux/module.h> 33#include <linux/init.h> 34#include <linux/cpufreq.h> 35#include <linux/slab.h> 36#include <linux/string.h> 37#include <linux/cpumask.h> 38#include <linux/sched.h> /* for current / set_cpus_allowed() */ 39#include <linux/io.h> 40#include <linux/delay.h> 41 42#include <asm/msr.h> 43#include <asm/cpu_device_id.h> 44 45#include <linux/acpi.h> 46#include <linux/mutex.h> 47#include <acpi/processor.h> 48 49#define PFX "powernow-k8: " 50#define VERSION "version 2.20.00" 51#include "powernow-k8.h" 52#include "mperf.h" 53 54/* serialize freq changes */ 55static DEFINE_MUTEX(fidvid_mutex); 56 57static DEFINE_PER_CPU(struct powernow_k8_data *, powernow_data); 58 59static int cpu_family = CPU_OPTERON; 60 61/* array to map SW pstate number to acpi state */ 62static u32 ps_to_as[8]; 63 64/* core performance boost */ 65static bool cpb_capable, cpb_enabled; 66static struct msr __percpu *msrs; 67 68static struct cpufreq_driver cpufreq_amd64_driver; 69 70#ifndef CONFIG_SMP 71static inline const struct cpumask *cpu_core_mask(int cpu) 72{ 73 return cpumask_of(0); 74} 75#endif 76 77/* Return a frequency in MHz, given an input fid */ 78static u32 find_freq_from_fid(u32 fid) 79{ 80 return 800 + (fid * 100); 81} 82 83/* Return a frequency in KHz, given an input fid */ 84static u32 find_khz_freq_from_fid(u32 fid) 85{ 86 return 1000 * find_freq_from_fid(fid); 87} 88 89static u32 find_khz_freq_from_pstate(struct cpufreq_frequency_table *data, 90 u32 pstate) 91{ 92 return data[ps_to_as[pstate]].frequency; 93} 94 95/* Return the vco fid for an input fid 96 * 97 * Each "low" fid has corresponding "high" fid, and you can get to "low" fids 98 * only from corresponding high fids. This returns "high" fid corresponding to 99 * "low" one. 100 */ 101static u32 convert_fid_to_vco_fid(u32 fid) 102{ 103 if (fid < HI_FID_TABLE_BOTTOM) 104 return 8 + (2 * fid); 105 else 106 return fid; 107} 108 109/* 110 * Return 1 if the pending bit is set. Unless we just instructed the processor 111 * to transition to a new state, seeing this bit set is really bad news. 112 */ 113static int pending_bit_stuck(void) 114{ 115 u32 lo, hi; 116 117 if (cpu_family == CPU_HW_PSTATE) 118 return 0; 119 120 rdmsr(MSR_FIDVID_STATUS, lo, hi); 121 return lo & MSR_S_LO_CHANGE_PENDING ? 1 : 0; 122} 123 124/* 125 * Update the global current fid / vid values from the status msr. 126 * Returns 1 on error. 127 */ 128static int query_current_values_with_pending_wait(struct powernow_k8_data *data) 129{ 130 u32 lo, hi; 131 u32 i = 0; 132 133 if (cpu_family == CPU_HW_PSTATE) { 134 rdmsr(MSR_PSTATE_STATUS, lo, hi); 135 i = lo & HW_PSTATE_MASK; 136 data->currpstate = i; 137 138 /* 139 * a workaround for family 11h erratum 311 might cause 140 * an "out-of-range Pstate if the core is in Pstate-0 141 */ 142 if ((boot_cpu_data.x86 == 0x11) && (i >= data->numps)) 143 data->currpstate = HW_PSTATE_0; 144 145 return 0; 146 } 147 do { 148 if (i++ > 10000) { 149 pr_debug("detected change pending stuck\n"); 150 return 1; 151 } 152 rdmsr(MSR_FIDVID_STATUS, lo, hi); 153 } while (lo & MSR_S_LO_CHANGE_PENDING); 154 155 data->currvid = hi & MSR_S_HI_CURRENT_VID; 156 data->currfid = lo & MSR_S_LO_CURRENT_FID; 157 158 return 0; 159} 160 161/* the isochronous relief time */ 162static void count_off_irt(struct powernow_k8_data *data) 163{ 164 udelay((1 << data->irt) * 10); 165 return; 166} 167 168/* the voltage stabilization time */ 169static void count_off_vst(struct powernow_k8_data *data) 170{ 171 udelay(data->vstable * VST_UNITS_20US); 172 return; 173} 174 175/* need to init the control msr to a safe value (for each cpu) */ 176static void fidvid_msr_init(void) 177{ 178 u32 lo, hi; 179 u8 fid, vid; 180 181 rdmsr(MSR_FIDVID_STATUS, lo, hi); 182 vid = hi & MSR_S_HI_CURRENT_VID; 183 fid = lo & MSR_S_LO_CURRENT_FID; 184 lo = fid | (vid << MSR_C_LO_VID_SHIFT); 185 hi = MSR_C_HI_STP_GNT_BENIGN; 186 pr_debug("cpu%d, init lo 0x%x, hi 0x%x\n", smp_processor_id(), lo, hi); 187 wrmsr(MSR_FIDVID_CTL, lo, hi); 188} 189 190/* write the new fid value along with the other control fields to the msr */ 191static int write_new_fid(struct powernow_k8_data *data, u32 fid) 192{ 193 u32 lo; 194 u32 savevid = data->currvid; 195 u32 i = 0; 196 197 if ((fid & INVALID_FID_MASK) || (data->currvid & INVALID_VID_MASK)) { 198 printk(KERN_ERR PFX "internal error - overflow on fid write\n"); 199 return 1; 200 } 201 202 lo = fid; 203 lo |= (data->currvid << MSR_C_LO_VID_SHIFT); 204 lo |= MSR_C_LO_INIT_FID_VID; 205 206 pr_debug("writing fid 0x%x, lo 0x%x, hi 0x%x\n", 207 fid, lo, data->plllock * PLL_LOCK_CONVERSION); 208 209 do { 210 wrmsr(MSR_FIDVID_CTL, lo, data->plllock * PLL_LOCK_CONVERSION); 211 if (i++ > 100) { 212 printk(KERN_ERR PFX 213 "Hardware error - pending bit very stuck - " 214 "no further pstate changes possible\n"); 215 return 1; 216 } 217 } while (query_current_values_with_pending_wait(data)); 218 219 count_off_irt(data); 220 221 if (savevid != data->currvid) { 222 printk(KERN_ERR PFX 223 "vid change on fid trans, old 0x%x, new 0x%x\n", 224 savevid, data->currvid); 225 return 1; 226 } 227 228 if (fid != data->currfid) { 229 printk(KERN_ERR PFX 230 "fid trans failed, fid 0x%x, curr 0x%x\n", fid, 231 data->currfid); 232 return 1; 233 } 234 235 return 0; 236} 237 238/* Write a new vid to the hardware */ 239static int write_new_vid(struct powernow_k8_data *data, u32 vid) 240{ 241 u32 lo; 242 u32 savefid = data->currfid; 243 int i = 0; 244 245 if ((data->currfid & INVALID_FID_MASK) || (vid & INVALID_VID_MASK)) { 246 printk(KERN_ERR PFX "internal error - overflow on vid write\n"); 247 return 1; 248 } 249 250 lo = data->currfid; 251 lo |= (vid << MSR_C_LO_VID_SHIFT); 252 lo |= MSR_C_LO_INIT_FID_VID; 253 254 pr_debug("writing vid 0x%x, lo 0x%x, hi 0x%x\n", 255 vid, lo, STOP_GRANT_5NS); 256 257 do { 258 wrmsr(MSR_FIDVID_CTL, lo, STOP_GRANT_5NS); 259 if (i++ > 100) { 260 printk(KERN_ERR PFX "internal error - pending bit " 261 "very stuck - no further pstate " 262 "changes possible\n"); 263 return 1; 264 } 265 } while (query_current_values_with_pending_wait(data)); 266 267 if (savefid != data->currfid) { 268 printk(KERN_ERR PFX "fid changed on vid trans, old " 269 "0x%x new 0x%x\n", 270 savefid, data->currfid); 271 return 1; 272 } 273 274 if (vid != data->currvid) { 275 printk(KERN_ERR PFX "vid trans failed, vid 0x%x, " 276 "curr 0x%x\n", 277 vid, data->currvid); 278 return 1; 279 } 280 281 return 0; 282} 283 284/* 285 * Reduce the vid by the max of step or reqvid. 286 * Decreasing vid codes represent increasing voltages: 287 * vid of 0 is 1.550V, vid of 0x1e is 0.800V, vid of VID_OFF is off. 288 */ 289static int decrease_vid_code_by_step(struct powernow_k8_data *data, 290 u32 reqvid, u32 step) 291{ 292 if ((data->currvid - reqvid) > step) 293 reqvid = data->currvid - step; 294 295 if (write_new_vid(data, reqvid)) 296 return 1; 297 298 count_off_vst(data); 299 300 return 0; 301} 302 303/* Change hardware pstate by single MSR write */ 304static int transition_pstate(struct powernow_k8_data *data, u32 pstate) 305{ 306 wrmsr(MSR_PSTATE_CTRL, pstate, 0); 307 data->currpstate = pstate; 308 return 0; 309} 310 311/* Change Opteron/Athlon64 fid and vid, by the 3 phases. */ 312static int transition_fid_vid(struct powernow_k8_data *data, 313 u32 reqfid, u32 reqvid) 314{ 315 if (core_voltage_pre_transition(data, reqvid, reqfid)) 316 return 1; 317 318 if (core_frequency_transition(data, reqfid)) 319 return 1; 320 321 if (core_voltage_post_transition(data, reqvid)) 322 return 1; 323 324 if (query_current_values_with_pending_wait(data)) 325 return 1; 326 327 if ((reqfid != data->currfid) || (reqvid != data->currvid)) { 328 printk(KERN_ERR PFX "failed (cpu%d): req 0x%x 0x%x, " 329 "curr 0x%x 0x%x\n", 330 smp_processor_id(), 331 reqfid, reqvid, data->currfid, data->currvid); 332 return 1; 333 } 334 335 pr_debug("transitioned (cpu%d): new fid 0x%x, vid 0x%x\n", 336 smp_processor_id(), data->currfid, data->currvid); 337 338 return 0; 339} 340 341/* Phase 1 - core voltage transition ... setup voltage */ 342static int core_voltage_pre_transition(struct powernow_k8_data *data, 343 u32 reqvid, u32 reqfid) 344{ 345 u32 rvosteps = data->rvo; 346 u32 savefid = data->currfid; 347 u32 maxvid, lo, rvomult = 1; 348 349 pr_debug("ph1 (cpu%d): start, currfid 0x%x, currvid 0x%x, " 350 "reqvid 0x%x, rvo 0x%x\n", 351 smp_processor_id(), 352 data->currfid, data->currvid, reqvid, data->rvo); 353 354 if ((savefid < LO_FID_TABLE_TOP) && (reqfid < LO_FID_TABLE_TOP)) 355 rvomult = 2; 356 rvosteps *= rvomult; 357 rdmsr(MSR_FIDVID_STATUS, lo, maxvid); 358 maxvid = 0x1f & (maxvid >> 16); 359 pr_debug("ph1 maxvid=0x%x\n", maxvid); 360 if (reqvid < maxvid) /* lower numbers are higher voltages */ 361 reqvid = maxvid; 362 363 while (data->currvid > reqvid) { 364 pr_debug("ph1: curr 0x%x, req vid 0x%x\n", 365 data->currvid, reqvid); 366 if (decrease_vid_code_by_step(data, reqvid, data->vidmvs)) 367 return 1; 368 } 369 370 while ((rvosteps > 0) && 371 ((rvomult * data->rvo + data->currvid) > reqvid)) { 372 if (data->currvid == maxvid) { 373 rvosteps = 0; 374 } else { 375 pr_debug("ph1: changing vid for rvo, req 0x%x\n", 376 data->currvid - 1); 377 if (decrease_vid_code_by_step(data, data->currvid-1, 1)) 378 return 1; 379 rvosteps--; 380 } 381 } 382 383 if (query_current_values_with_pending_wait(data)) 384 return 1; 385 386 if (savefid != data->currfid) { 387 printk(KERN_ERR PFX "ph1 err, currfid changed 0x%x\n", 388 data->currfid); 389 return 1; 390 } 391 392 pr_debug("ph1 complete, currfid 0x%x, currvid 0x%x\n", 393 data->currfid, data->currvid); 394 395 return 0; 396} 397 398/* Phase 2 - core frequency transition */ 399static int core_frequency_transition(struct powernow_k8_data *data, u32 reqfid) 400{ 401 u32 vcoreqfid, vcocurrfid, vcofiddiff; 402 u32 fid_interval, savevid = data->currvid; 403 404 if (data->currfid == reqfid) { 405 printk(KERN_ERR PFX "ph2 null fid transition 0x%x\n", 406 data->currfid); 407 return 0; 408 } 409 410 pr_debug("ph2 (cpu%d): starting, currfid 0x%x, currvid 0x%x, " 411 "reqfid 0x%x\n", 412 smp_processor_id(), 413 data->currfid, data->currvid, reqfid); 414 415 vcoreqfid = convert_fid_to_vco_fid(reqfid); 416 vcocurrfid = convert_fid_to_vco_fid(data->currfid); 417 vcofiddiff = vcocurrfid > vcoreqfid ? vcocurrfid - vcoreqfid 418 : vcoreqfid - vcocurrfid; 419 420 if ((reqfid <= LO_FID_TABLE_TOP) && (data->currfid <= LO_FID_TABLE_TOP)) 421 vcofiddiff = 0; 422 423 while (vcofiddiff > 2) { 424 (data->currfid & 1) ? (fid_interval = 1) : (fid_interval = 2); 425 426 if (reqfid > data->currfid) { 427 if (data->currfid > LO_FID_TABLE_TOP) { 428 if (write_new_fid(data, 429 data->currfid + fid_interval)) 430 return 1; 431 } else { 432 if (write_new_fid 433 (data, 434 2 + convert_fid_to_vco_fid(data->currfid))) 435 return 1; 436 } 437 } else { 438 if (write_new_fid(data, data->currfid - fid_interval)) 439 return 1; 440 } 441 442 vcocurrfid = convert_fid_to_vco_fid(data->currfid); 443 vcofiddiff = vcocurrfid > vcoreqfid ? vcocurrfid - vcoreqfid 444 : vcoreqfid - vcocurrfid; 445 } 446 447 if (write_new_fid(data, reqfid)) 448 return 1; 449 450 if (query_current_values_with_pending_wait(data)) 451 return 1; 452 453 if (data->currfid != reqfid) { 454 printk(KERN_ERR PFX 455 "ph2: mismatch, failed fid transition, " 456 "curr 0x%x, req 0x%x\n", 457 data->currfid, reqfid); 458 return 1; 459 } 460 461 if (savevid != data->currvid) { 462 printk(KERN_ERR PFX "ph2: vid changed, save 0x%x, curr 0x%x\n", 463 savevid, data->currvid); 464 return 1; 465 } 466 467 pr_debug("ph2 complete, currfid 0x%x, currvid 0x%x\n", 468 data->currfid, data->currvid); 469 470 return 0; 471} 472 473/* Phase 3 - core voltage transition flow ... jump to the final vid. */ 474static int core_voltage_post_transition(struct powernow_k8_data *data, 475 u32 reqvid) 476{ 477 u32 savefid = data->currfid; 478 u32 savereqvid = reqvid; 479 480 pr_debug("ph3 (cpu%d): starting, currfid 0x%x, currvid 0x%x\n", 481 smp_processor_id(), 482 data->currfid, data->currvid); 483 484 if (reqvid != data->currvid) { 485 if (write_new_vid(data, reqvid)) 486 return 1; 487 488 if (savefid != data->currfid) { 489 printk(KERN_ERR PFX 490 "ph3: bad fid change, save 0x%x, curr 0x%x\n", 491 savefid, data->currfid); 492 return 1; 493 } 494 495 if (data->currvid != reqvid) { 496 printk(KERN_ERR PFX 497 "ph3: failed vid transition\n, " 498 "req 0x%x, curr 0x%x", 499 reqvid, data->currvid); 500 return 1; 501 } 502 } 503 504 if (query_current_values_with_pending_wait(data)) 505 return 1; 506 507 if (savereqvid != data->currvid) { 508 pr_debug("ph3 failed, currvid 0x%x\n", data->currvid); 509 return 1; 510 } 511 512 if (savefid != data->currfid) { 513 pr_debug("ph3 failed, currfid changed 0x%x\n", 514 data->currfid); 515 return 1; 516 } 517 518 pr_debug("ph3 complete, currfid 0x%x, currvid 0x%x\n", 519 data->currfid, data->currvid); 520 521 return 0; 522} 523 524static const struct x86_cpu_id powernow_k8_ids[] = { 525 /* IO based frequency switching */ 526 { X86_VENDOR_AMD, 0xf }, 527 /* MSR based frequency switching supported */ 528 X86_FEATURE_MATCH(X86_FEATURE_HW_PSTATE), 529 {} 530}; 531MODULE_DEVICE_TABLE(x86cpu, powernow_k8_ids); 532 533static void check_supported_cpu(void *_rc) 534{ 535 u32 eax, ebx, ecx, edx; 536 int *rc = _rc; 537 538 *rc = -ENODEV; 539 540 eax = cpuid_eax(CPUID_PROCESSOR_SIGNATURE); 541 542 if ((eax & CPUID_XFAM) == CPUID_XFAM_K8) { 543 if (((eax & CPUID_USE_XFAM_XMOD) != CPUID_USE_XFAM_XMOD) || 544 ((eax & CPUID_XMOD) > CPUID_XMOD_REV_MASK)) { 545 printk(KERN_INFO PFX 546 "Processor cpuid %x not supported\n", eax); 547 return; 548 } 549 550 eax = cpuid_eax(CPUID_GET_MAX_CAPABILITIES); 551 if (eax < CPUID_FREQ_VOLT_CAPABILITIES) { 552 printk(KERN_INFO PFX 553 "No frequency change capabilities detected\n"); 554 return; 555 } 556 557 cpuid(CPUID_FREQ_VOLT_CAPABILITIES, &eax, &ebx, &ecx, &edx); 558 if ((edx & P_STATE_TRANSITION_CAPABLE) 559 != P_STATE_TRANSITION_CAPABLE) { 560 printk(KERN_INFO PFX 561 "Power state transitions not supported\n"); 562 return; 563 } 564 } else { /* must be a HW Pstate capable processor */ 565 cpuid(CPUID_FREQ_VOLT_CAPABILITIES, &eax, &ebx, &ecx, &edx); 566 if ((edx & USE_HW_PSTATE) == USE_HW_PSTATE) 567 cpu_family = CPU_HW_PSTATE; 568 else 569 return; 570 } 571 572 *rc = 0; 573} 574 575static int check_pst_table(struct powernow_k8_data *data, struct pst_s *pst, 576 u8 maxvid) 577{ 578 unsigned int j; 579 u8 lastfid = 0xff; 580 581 for (j = 0; j < data->numps; j++) { 582 if (pst[j].vid > LEAST_VID) { 583 printk(KERN_ERR FW_BUG PFX "vid %d invalid : 0x%x\n", 584 j, pst[j].vid); 585 return -EINVAL; 586 } 587 if (pst[j].vid < data->rvo) { 588 /* vid + rvo >= 0 */ 589 printk(KERN_ERR FW_BUG PFX "0 vid exceeded with pstate" 590 " %d\n", j); 591 return -ENODEV; 592 } 593 if (pst[j].vid < maxvid + data->rvo) { 594 /* vid + rvo >= maxvid */ 595 printk(KERN_ERR FW_BUG PFX "maxvid exceeded with pstate" 596 " %d\n", j); 597 return -ENODEV; 598 } 599 if (pst[j].fid > MAX_FID) { 600 printk(KERN_ERR FW_BUG PFX "maxfid exceeded with pstate" 601 " %d\n", j); 602 return -ENODEV; 603 } 604 if (j && (pst[j].fid < HI_FID_TABLE_BOTTOM)) { 605 /* Only first fid is allowed to be in "low" range */ 606 printk(KERN_ERR FW_BUG PFX "two low fids - %d : " 607 "0x%x\n", j, pst[j].fid); 608 return -EINVAL; 609 } 610 if (pst[j].fid < lastfid) 611 lastfid = pst[j].fid; 612 } 613 if (lastfid & 1) { 614 printk(KERN_ERR FW_BUG PFX "lastfid invalid\n"); 615 return -EINVAL; 616 } 617 if (lastfid > LO_FID_TABLE_TOP) 618 printk(KERN_INFO FW_BUG PFX 619 "first fid not from lo freq table\n"); 620 621 return 0; 622} 623 624static void invalidate_entry(struct cpufreq_frequency_table *powernow_table, 625 unsigned int entry) 626{ 627 powernow_table[entry].frequency = CPUFREQ_ENTRY_INVALID; 628} 629 630static void print_basics(struct powernow_k8_data *data) 631{ 632 int j; 633 for (j = 0; j < data->numps; j++) { 634 if (data->powernow_table[j].frequency != 635 CPUFREQ_ENTRY_INVALID) { 636 if (cpu_family == CPU_HW_PSTATE) { 637 printk(KERN_INFO PFX 638 " %d : pstate %d (%d MHz)\n", j, 639 data->powernow_table[j].index, 640 data->powernow_table[j].frequency/1000); 641 } else { 642 printk(KERN_INFO PFX 643 "fid 0x%x (%d MHz), vid 0x%x\n", 644 data->powernow_table[j].index & 0xff, 645 data->powernow_table[j].frequency/1000, 646 data->powernow_table[j].index >> 8); 647 } 648 } 649 } 650 if (data->batps) 651 printk(KERN_INFO PFX "Only %d pstates on battery\n", 652 data->batps); 653} 654 655static u32 freq_from_fid_did(u32 fid, u32 did) 656{ 657 u32 mhz = 0; 658 659 if (boot_cpu_data.x86 == 0x10) 660 mhz = (100 * (fid + 0x10)) >> did; 661 else if (boot_cpu_data.x86 == 0x11) 662 mhz = (100 * (fid + 8)) >> did; 663 else 664 BUG(); 665 666 return mhz * 1000; 667} 668 669static int fill_powernow_table(struct powernow_k8_data *data, 670 struct pst_s *pst, u8 maxvid) 671{ 672 struct cpufreq_frequency_table *powernow_table; 673 unsigned int j; 674 675 if (data->batps) { 676 /* use ACPI support to get full speed on mains power */ 677 printk(KERN_WARNING PFX 678 "Only %d pstates usable (use ACPI driver for full " 679 "range\n", data->batps); 680 data->numps = data->batps; 681 } 682 683 for (j = 1; j < data->numps; j++) { 684 if (pst[j-1].fid >= pst[j].fid) { 685 printk(KERN_ERR PFX "PST out of sequence\n"); 686 return -EINVAL; 687 } 688 } 689 690 if (data->numps < 2) { 691 printk(KERN_ERR PFX "no p states to transition\n"); 692 return -ENODEV; 693 } 694 695 if (check_pst_table(data, pst, maxvid)) 696 return -EINVAL; 697 698 powernow_table = kmalloc((sizeof(struct cpufreq_frequency_table) 699 * (data->numps + 1)), GFP_KERNEL); 700 if (!powernow_table) { 701 printk(KERN_ERR PFX "powernow_table memory alloc failure\n"); 702 return -ENOMEM; 703 } 704 705 for (j = 0; j < data->numps; j++) { 706 int freq; 707 powernow_table[j].index = pst[j].fid; /* lower 8 bits */ 708 powernow_table[j].index |= (pst[j].vid << 8); /* upper 8 bits */ 709 freq = find_khz_freq_from_fid(pst[j].fid); 710 powernow_table[j].frequency = freq; 711 } 712 powernow_table[data->numps].frequency = CPUFREQ_TABLE_END; 713 powernow_table[data->numps].index = 0; 714 715 if (query_current_values_with_pending_wait(data)) { 716 kfree(powernow_table); 717 return -EIO; 718 } 719 720 pr_debug("cfid 0x%x, cvid 0x%x\n", data->currfid, data->currvid); 721 data->powernow_table = powernow_table; 722 if (cpumask_first(cpu_core_mask(data->cpu)) == data->cpu) 723 print_basics(data); 724 725 for (j = 0; j < data->numps; j++) 726 if ((pst[j].fid == data->currfid) && 727 (pst[j].vid == data->currvid)) 728 return 0; 729 730 pr_debug("currfid/vid do not match PST, ignoring\n"); 731 return 0; 732} 733 734/* Find and validate the PSB/PST table in BIOS. */ 735static int find_psb_table(struct powernow_k8_data *data) 736{ 737 struct psb_s *psb; 738 unsigned int i; 739 u32 mvs; 740 u8 maxvid; 741 u32 cpst = 0; 742 u32 thiscpuid; 743 744 for (i = 0xc0000; i < 0xffff0; i += 0x10) { 745 /* Scan BIOS looking for the signature. */ 746 /* It can not be at ffff0 - it is too big. */ 747 748 psb = phys_to_virt(i); 749 if (memcmp(psb, PSB_ID_STRING, PSB_ID_STRING_LEN) != 0) 750 continue; 751 752 pr_debug("found PSB header at 0x%p\n", psb); 753 754 pr_debug("table vers: 0x%x\n", psb->tableversion); 755 if (psb->tableversion != PSB_VERSION_1_4) { 756 printk(KERN_ERR FW_BUG PFX "PSB table is not v1.4\n"); 757 return -ENODEV; 758 } 759 760 pr_debug("flags: 0x%x\n", psb->flags1); 761 if (psb->flags1) { 762 printk(KERN_ERR FW_BUG PFX "unknown flags\n"); 763 return -ENODEV; 764 } 765 766 data->vstable = psb->vstable; 767 pr_debug("voltage stabilization time: %d(*20us)\n", 768 data->vstable); 769 770 pr_debug("flags2: 0x%x\n", psb->flags2); 771 data->rvo = psb->flags2 & 3; 772 data->irt = ((psb->flags2) >> 2) & 3; 773 mvs = ((psb->flags2) >> 4) & 3; 774 data->vidmvs = 1 << mvs; 775 data->batps = ((psb->flags2) >> 6) & 3; 776 777 pr_debug("ramp voltage offset: %d\n", data->rvo); 778 pr_debug("isochronous relief time: %d\n", data->irt); 779 pr_debug("maximum voltage step: %d - 0x%x\n", mvs, data->vidmvs); 780 781 pr_debug("numpst: 0x%x\n", psb->num_tables); 782 cpst = psb->num_tables; 783 if ((psb->cpuid == 0x00000fc0) || 784 (psb->cpuid == 0x00000fe0)) { 785 thiscpuid = cpuid_eax(CPUID_PROCESSOR_SIGNATURE); 786 if ((thiscpuid == 0x00000fc0) || 787 (thiscpuid == 0x00000fe0)) 788 cpst = 1; 789 } 790 if (cpst != 1) { 791 printk(KERN_ERR FW_BUG PFX "numpst must be 1\n"); 792 return -ENODEV; 793 } 794 795 data->plllock = psb->plllocktime; 796 pr_debug("plllocktime: 0x%x (units 1us)\n", psb->plllocktime); 797 pr_debug("maxfid: 0x%x\n", psb->maxfid); 798 pr_debug("maxvid: 0x%x\n", psb->maxvid); 799 maxvid = psb->maxvid; 800 801 data->numps = psb->numps; 802 pr_debug("numpstates: 0x%x\n", data->numps); 803 return fill_powernow_table(data, 804 (struct pst_s *)(psb+1), maxvid); 805 } 806 /* 807 * If you see this message, complain to BIOS manufacturer. If 808 * he tells you "we do not support Linux" or some similar 809 * nonsense, remember that Windows 2000 uses the same legacy 810 * mechanism that the old Linux PSB driver uses. Tell them it 811 * is broken with Windows 2000. 812 * 813 * The reference to the AMD documentation is chapter 9 in the 814 * BIOS and Kernel Developer's Guide, which is available on 815 * www.amd.com 816 */ 817 printk(KERN_ERR FW_BUG PFX "No PSB or ACPI _PSS objects\n"); 818 printk(KERN_ERR PFX "Make sure that your BIOS is up to date" 819 " and Cool'N'Quiet support is enabled in BIOS setup\n"); 820 return -ENODEV; 821} 822 823static void powernow_k8_acpi_pst_values(struct powernow_k8_data *data, 824 unsigned int index) 825{ 826 u64 control; 827 828 if (!data->acpi_data.state_count || (cpu_family == CPU_HW_PSTATE)) 829 return; 830 831 control = data->acpi_data.states[index].control; 832 data->irt = (control >> IRT_SHIFT) & IRT_MASK; 833 data->rvo = (control >> RVO_SHIFT) & RVO_MASK; 834 data->exttype = (control >> EXT_TYPE_SHIFT) & EXT_TYPE_MASK; 835 data->plllock = (control >> PLL_L_SHIFT) & PLL_L_MASK; 836 data->vidmvs = 1 << ((control >> MVS_SHIFT) & MVS_MASK); 837 data->vstable = (control >> VST_SHIFT) & VST_MASK; 838} 839 840static int powernow_k8_cpu_init_acpi(struct powernow_k8_data *data) 841{ 842 struct cpufreq_frequency_table *powernow_table; 843 int ret_val = -ENODEV; 844 u64 control, status; 845 846 if (acpi_processor_register_performance(&data->acpi_data, data->cpu)) { 847 pr_debug("register performance failed: bad ACPI data\n"); 848 return -EIO; 849 } 850 851 /* verify the data contained in the ACPI structures */ 852 if (data->acpi_data.state_count <= 1) { 853 pr_debug("No ACPI P-States\n"); 854 goto err_out; 855 } 856 857 control = data->acpi_data.control_register.space_id; 858 status = data->acpi_data.status_register.space_id; 859 860 if ((control != ACPI_ADR_SPACE_FIXED_HARDWARE) || 861 (status != ACPI_ADR_SPACE_FIXED_HARDWARE)) { 862 pr_debug("Invalid control/status registers (%llx - %llx)\n", 863 control, status); 864 goto err_out; 865 } 866 867 /* fill in data->powernow_table */ 868 powernow_table = kmalloc((sizeof(struct cpufreq_frequency_table) 869 * (data->acpi_data.state_count + 1)), GFP_KERNEL); 870 if (!powernow_table) { 871 pr_debug("powernow_table memory alloc failure\n"); 872 goto err_out; 873 } 874 875 /* fill in data */ 876 data->numps = data->acpi_data.state_count; 877 powernow_k8_acpi_pst_values(data, 0); 878 879 if (cpu_family == CPU_HW_PSTATE) 880 ret_val = fill_powernow_table_pstate(data, powernow_table); 881 else 882 ret_val = fill_powernow_table_fidvid(data, powernow_table); 883 if (ret_val) 884 goto err_out_mem; 885 886 powernow_table[data->acpi_data.state_count].frequency = 887 CPUFREQ_TABLE_END; 888 powernow_table[data->acpi_data.state_count].index = 0; 889 data->powernow_table = powernow_table; 890 891 if (cpumask_first(cpu_core_mask(data->cpu)) == data->cpu) 892 print_basics(data); 893 894 /* notify BIOS that we exist */ 895 acpi_processor_notify_smm(THIS_MODULE); 896 897 if (!zalloc_cpumask_var(&data->acpi_data.shared_cpu_map, GFP_KERNEL)) { 898 printk(KERN_ERR PFX 899 "unable to alloc powernow_k8_data cpumask\n"); 900 ret_val = -ENOMEM; 901 goto err_out_mem; 902 } 903 904 return 0; 905 906err_out_mem: 907 kfree(powernow_table); 908 909err_out: 910 acpi_processor_unregister_performance(&data->acpi_data, data->cpu); 911 912 /* data->acpi_data.state_count informs us at ->exit() 913 * whether ACPI was used */ 914 data->acpi_data.state_count = 0; 915 916 return ret_val; 917} 918 919static int fill_powernow_table_pstate(struct powernow_k8_data *data, 920 struct cpufreq_frequency_table *powernow_table) 921{ 922 int i; 923 u32 hi = 0, lo = 0; 924 rdmsr(MSR_PSTATE_CUR_LIMIT, lo, hi); 925 data->max_hw_pstate = (lo & HW_PSTATE_MAX_MASK) >> HW_PSTATE_MAX_SHIFT; 926 927 for (i = 0; i < data->acpi_data.state_count; i++) { 928 u32 index; 929 930 index = data->acpi_data.states[i].control & HW_PSTATE_MASK; 931 if (index > data->max_hw_pstate) { 932 printk(KERN_ERR PFX "invalid pstate %d - " 933 "bad value %d.\n", i, index); 934 printk(KERN_ERR PFX "Please report to BIOS " 935 "manufacturer\n"); 936 invalidate_entry(powernow_table, i); 937 continue; 938 } 939 940 ps_to_as[index] = i; 941 942 /* Frequency may be rounded for these */ 943 if ((boot_cpu_data.x86 == 0x10 && boot_cpu_data.x86_model < 10) 944 || boot_cpu_data.x86 == 0x11) { 945 946 rdmsr(MSR_PSTATE_DEF_BASE + index, lo, hi); 947 if (!(hi & HW_PSTATE_VALID_MASK)) { 948 pr_debug("invalid pstate %d, ignoring\n", index); 949 invalidate_entry(powernow_table, i); 950 continue; 951 } 952 953 powernow_table[i].frequency = 954 freq_from_fid_did(lo & 0x3f, (lo >> 6) & 7); 955 } else 956 powernow_table[i].frequency = 957 data->acpi_data.states[i].core_frequency * 1000; 958 959 powernow_table[i].index = index; 960 } 961 return 0; 962} 963 964static int fill_powernow_table_fidvid(struct powernow_k8_data *data, 965 struct cpufreq_frequency_table *powernow_table) 966{ 967 int i; 968 969 for (i = 0; i < data->acpi_data.state_count; i++) { 970 u32 fid; 971 u32 vid; 972 u32 freq, index; 973 u64 status, control; 974 975 if (data->exttype) { 976 status = data->acpi_data.states[i].status; 977 fid = status & EXT_FID_MASK; 978 vid = (status >> VID_SHIFT) & EXT_VID_MASK; 979 } else { 980 control = data->acpi_data.states[i].control; 981 fid = control & FID_MASK; 982 vid = (control >> VID_SHIFT) & VID_MASK; 983 } 984 985 pr_debug(" %d : fid 0x%x, vid 0x%x\n", i, fid, vid); 986 987 index = fid | (vid<<8); 988 powernow_table[i].index = index; 989 990 freq = find_khz_freq_from_fid(fid); 991 powernow_table[i].frequency = freq; 992 993 /* verify frequency is OK */ 994 if ((freq > (MAX_FREQ * 1000)) || (freq < (MIN_FREQ * 1000))) { 995 pr_debug("invalid freq %u kHz, ignoring\n", freq); 996 invalidate_entry(powernow_table, i); 997 continue; 998 } 999 1000 /* verify voltage is OK - 1001 * BIOSs are using "off" to indicate invalid */ 1002 if (vid == VID_OFF) { 1003 pr_debug("invalid vid %u, ignoring\n", vid); 1004 invalidate_entry(powernow_table, i); 1005 continue; 1006 } 1007 1008 if (freq != (data->acpi_data.states[i].core_frequency * 1000)) { 1009 printk(KERN_INFO PFX "invalid freq entries " 1010 "%u kHz vs. %u kHz\n", freq, 1011 (unsigned int) 1012 (data->acpi_data.states[i].core_frequency 1013 * 1000)); 1014 invalidate_entry(powernow_table, i); 1015 continue; 1016 } 1017 } 1018 return 0; 1019} 1020 1021static void powernow_k8_cpu_exit_acpi(struct powernow_k8_data *data) 1022{ 1023 if (data->acpi_data.state_count) 1024 acpi_processor_unregister_performance(&data->acpi_data, 1025 data->cpu); 1026 free_cpumask_var(data->acpi_data.shared_cpu_map); 1027} 1028 1029static int get_transition_latency(struct powernow_k8_data *data) 1030{ 1031 int max_latency = 0; 1032 int i; 1033 for (i = 0; i < data->acpi_data.state_count; i++) { 1034 int cur_latency = data->acpi_data.states[i].transition_latency 1035 + data->acpi_data.states[i].bus_master_latency; 1036 if (cur_latency > max_latency) 1037 max_latency = cur_latency; 1038 } 1039 if (max_latency == 0) { 1040 /* 1041 * Fam 11h and later may return 0 as transition latency. This 1042 * is intended and means "very fast". While cpufreq core and 1043 * governors currently can handle that gracefully, better set it 1044 * to 1 to avoid problems in the future. 1045 */ 1046 if (boot_cpu_data.x86 < 0x11) 1047 printk(KERN_ERR FW_WARN PFX "Invalid zero transition " 1048 "latency\n"); 1049 max_latency = 1; 1050 } 1051 /* value in usecs, needs to be in nanoseconds */ 1052 return 1000 * max_latency; 1053} 1054 1055/* Take a frequency, and issue the fid/vid transition command */ 1056static int transition_frequency_fidvid(struct powernow_k8_data *data, 1057 unsigned int index) 1058{ 1059 u32 fid = 0; 1060 u32 vid = 0; 1061 int res, i; 1062 struct cpufreq_freqs freqs; 1063 1064 pr_debug("cpu %d transition to index %u\n", smp_processor_id(), index); 1065 1066 /* fid/vid correctness check for k8 */ 1067 /* fid are the lower 8 bits of the index we stored into 1068 * the cpufreq frequency table in find_psb_table, vid 1069 * are the upper 8 bits. 1070 */ 1071 fid = data->powernow_table[index].index & 0xFF; 1072 vid = (data->powernow_table[index].index & 0xFF00) >> 8; 1073 1074 pr_debug("table matched fid 0x%x, giving vid 0x%x\n", fid, vid); 1075 1076 if (query_current_values_with_pending_wait(data)) 1077 return 1; 1078 1079 if ((data->currvid == vid) && (data->currfid == fid)) { 1080 pr_debug("target matches current values (fid 0x%x, vid 0x%x)\n", 1081 fid, vid); 1082 return 0; 1083 } 1084 1085 pr_debug("cpu %d, changing to fid 0x%x, vid 0x%x\n", 1086 smp_processor_id(), fid, vid); 1087 freqs.old = find_khz_freq_from_fid(data->currfid); 1088 freqs.new = find_khz_freq_from_fid(fid); 1089 1090 for_each_cpu(i, data->available_cores) { 1091 freqs.cpu = i; 1092 cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE); 1093 } 1094 1095 res = transition_fid_vid(data, fid, vid); 1096 if (res) 1097 return res; 1098 1099 freqs.new = find_khz_freq_from_fid(data->currfid); 1100 1101 for_each_cpu(i, data->available_cores) { 1102 freqs.cpu = i; 1103 cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE); 1104 } 1105 return res; 1106} 1107 1108/* Take a frequency, and issue the hardware pstate transition command */ 1109static int transition_frequency_pstate(struct powernow_k8_data *data, 1110 unsigned int index) 1111{ 1112 u32 pstate = 0; 1113 int res, i; 1114 struct cpufreq_freqs freqs; 1115 1116 pr_debug("cpu %d transition to index %u\n", smp_processor_id(), index); 1117 1118 /* get MSR index for hardware pstate transition */ 1119 pstate = index & HW_PSTATE_MASK; 1120 if (pstate > data->max_hw_pstate) 1121 return -EINVAL; 1122 1123 freqs.old = find_khz_freq_from_pstate(data->powernow_table, 1124 data->currpstate); 1125 freqs.new = find_khz_freq_from_pstate(data->powernow_table, pstate); 1126 1127 for_each_cpu(i, data->available_cores) { 1128 freqs.cpu = i; 1129 cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE); 1130 } 1131 1132 res = transition_pstate(data, pstate); 1133 freqs.new = find_khz_freq_from_pstate(data->powernow_table, pstate); 1134 1135 for_each_cpu(i, data->available_cores) { 1136 freqs.cpu = i; 1137 cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE); 1138 } 1139 return res; 1140} 1141 1142/* Driver entry point to switch to the target frequency */ 1143static int powernowk8_target(struct cpufreq_policy *pol, 1144 unsigned targfreq, unsigned relation) 1145{ 1146 cpumask_var_t oldmask; 1147 struct powernow_k8_data *data = per_cpu(powernow_data, pol->cpu); 1148 u32 checkfid; 1149 u32 checkvid; 1150 unsigned int newstate; 1151 int ret = -EIO; 1152 1153 if (!data) 1154 return -EINVAL; 1155 1156 checkfid = data->currfid; 1157 checkvid = data->currvid; 1158 1159 /* only run on specific CPU from here on. */ 1160 /* This is poor form: use a workqueue or smp_call_function_single */ 1161 if (!alloc_cpumask_var(&oldmask, GFP_KERNEL)) 1162 return -ENOMEM; 1163 1164 cpumask_copy(oldmask, tsk_cpus_allowed(current)); 1165 set_cpus_allowed_ptr(current, cpumask_of(pol->cpu)); 1166 1167 if (smp_processor_id() != pol->cpu) { 1168 printk(KERN_ERR PFX "limiting to cpu %u failed\n", pol->cpu); 1169 goto err_out; 1170 } 1171 1172 if (pending_bit_stuck()) { 1173 printk(KERN_ERR PFX "failing targ, change pending bit set\n"); 1174 goto err_out; 1175 } 1176 1177 pr_debug("targ: cpu %d, %d kHz, min %d, max %d, relation %d\n", 1178 pol->cpu, targfreq, pol->min, pol->max, relation); 1179 1180 if (query_current_values_with_pending_wait(data)) 1181 goto err_out; 1182 1183 if (cpu_family != CPU_HW_PSTATE) { 1184 pr_debug("targ: curr fid 0x%x, vid 0x%x\n", 1185 data->currfid, data->currvid); 1186 1187 if ((checkvid != data->currvid) || 1188 (checkfid != data->currfid)) { 1189 printk(KERN_INFO PFX 1190 "error - out of sync, fix 0x%x 0x%x, " 1191 "vid 0x%x 0x%x\n", 1192 checkfid, data->currfid, 1193 checkvid, data->currvid); 1194 } 1195 } 1196 1197 if (cpufreq_frequency_table_target(pol, data->powernow_table, 1198 targfreq, relation, &newstate)) 1199 goto err_out; 1200 1201 mutex_lock(&fidvid_mutex); 1202 1203 powernow_k8_acpi_pst_values(data, newstate); 1204 1205 if (cpu_family == CPU_HW_PSTATE) 1206 ret = transition_frequency_pstate(data, 1207 data->powernow_table[newstate].index); 1208 else 1209 ret = transition_frequency_fidvid(data, newstate); 1210 if (ret) { 1211 printk(KERN_ERR PFX "transition frequency failed\n"); 1212 ret = 1; 1213 mutex_unlock(&fidvid_mutex); 1214 goto err_out; 1215 } 1216 mutex_unlock(&fidvid_mutex); 1217 1218 if (cpu_family == CPU_HW_PSTATE) 1219 pol->cur = find_khz_freq_from_pstate(data->powernow_table, 1220 data->powernow_table[newstate].index); 1221 else 1222 pol->cur = find_khz_freq_from_fid(data->currfid); 1223 ret = 0; 1224 1225err_out: 1226 set_cpus_allowed_ptr(current, oldmask); 1227 free_cpumask_var(oldmask); 1228 return ret; 1229} 1230 1231/* Driver entry point to verify the policy and range of frequencies */ 1232static int powernowk8_verify(struct cpufreq_policy *pol) 1233{ 1234 struct powernow_k8_data *data = per_cpu(powernow_data, pol->cpu); 1235 1236 if (!data) 1237 return -EINVAL; 1238 1239 return cpufreq_frequency_table_verify(pol, data->powernow_table); 1240} 1241 1242struct init_on_cpu { 1243 struct powernow_k8_data *data; 1244 int rc; 1245}; 1246 1247static void __cpuinit powernowk8_cpu_init_on_cpu(void *_init_on_cpu) 1248{ 1249 struct init_on_cpu *init_on_cpu = _init_on_cpu; 1250 1251 if (pending_bit_stuck()) { 1252 printk(KERN_ERR PFX "failing init, change pending bit set\n"); 1253 init_on_cpu->rc = -ENODEV; 1254 return; 1255 } 1256 1257 if (query_current_values_with_pending_wait(init_on_cpu->data)) { 1258 init_on_cpu->rc = -ENODEV; 1259 return; 1260 } 1261 1262 if (cpu_family == CPU_OPTERON) 1263 fidvid_msr_init(); 1264 1265 init_on_cpu->rc = 0; 1266} 1267 1268static const char missing_pss_msg[] = 1269 KERN_ERR 1270 FW_BUG PFX "No compatible ACPI _PSS objects found.\n" 1271 FW_BUG PFX "First, make sure Cool'N'Quiet is enabled in the BIOS.\n" 1272 FW_BUG PFX "If that doesn't help, try upgrading your BIOS.\n"; 1273 1274/* per CPU init entry point to the driver */ 1275static int __cpuinit powernowk8_cpu_init(struct cpufreq_policy *pol) 1276{ 1277 struct powernow_k8_data *data; 1278 struct init_on_cpu init_on_cpu; 1279 int rc; 1280 struct cpuinfo_x86 *c = &cpu_data(pol->cpu); 1281 1282 if (!cpu_online(pol->cpu)) 1283 return -ENODEV; 1284 1285 smp_call_function_single(pol->cpu, check_supported_cpu, &rc, 1); 1286 if (rc) 1287 return -ENODEV; 1288 1289 data = kzalloc(sizeof(struct powernow_k8_data), GFP_KERNEL); 1290 if (!data) { 1291 printk(KERN_ERR PFX "unable to alloc powernow_k8_data"); 1292 return -ENOMEM; 1293 } 1294 1295 data->cpu = pol->cpu; 1296 data->currpstate = HW_PSTATE_INVALID; 1297 1298 if (powernow_k8_cpu_init_acpi(data)) { 1299 /* 1300 * Use the PSB BIOS structure. This is only available on 1301 * an UP version, and is deprecated by AMD. 1302 */ 1303 if (num_online_cpus() != 1) { 1304 printk_once(missing_pss_msg); 1305 goto err_out; 1306 } 1307 if (pol->cpu != 0) { 1308 printk(KERN_ERR FW_BUG PFX "No ACPI _PSS objects for " 1309 "CPU other than CPU0. Complain to your BIOS " 1310 "vendor.\n"); 1311 goto err_out; 1312 } 1313 rc = find_psb_table(data); 1314 if (rc) 1315 goto err_out; 1316 1317 /* Take a crude guess here. 1318 * That guess was in microseconds, so multiply with 1000 */ 1319 pol->cpuinfo.transition_latency = ( 1320 ((data->rvo + 8) * data->vstable * VST_UNITS_20US) + 1321 ((1 << data->irt) * 30)) * 1000; 1322 } else /* ACPI _PSS objects available */ 1323 pol->cpuinfo.transition_latency = get_transition_latency(data); 1324 1325 /* only run on specific CPU from here on */ 1326 init_on_cpu.data = data; 1327 smp_call_function_single(data->cpu, powernowk8_cpu_init_on_cpu, 1328 &init_on_cpu, 1); 1329 rc = init_on_cpu.rc; 1330 if (rc != 0) 1331 goto err_out_exit_acpi; 1332 1333 if (cpu_family == CPU_HW_PSTATE) 1334 cpumask_copy(pol->cpus, cpumask_of(pol->cpu)); 1335 else 1336 cpumask_copy(pol->cpus, cpu_core_mask(pol->cpu)); 1337 data->available_cores = pol->cpus; 1338 1339 if (cpu_family == CPU_HW_PSTATE) 1340 pol->cur = find_khz_freq_from_pstate(data->powernow_table, 1341 data->currpstate); 1342 else 1343 pol->cur = find_khz_freq_from_fid(data->currfid); 1344 pr_debug("policy current frequency %d kHz\n", pol->cur); 1345 1346 /* min/max the cpu is capable of */ 1347 if (cpufreq_frequency_table_cpuinfo(pol, data->powernow_table)) { 1348 printk(KERN_ERR FW_BUG PFX "invalid powernow_table\n"); 1349 powernow_k8_cpu_exit_acpi(data); 1350 kfree(data->powernow_table); 1351 kfree(data); 1352 return -EINVAL; 1353 } 1354 1355 /* Check for APERF/MPERF support in hardware */ 1356 if (cpu_has(c, X86_FEATURE_APERFMPERF)) 1357 cpufreq_amd64_driver.getavg = cpufreq_get_measured_perf; 1358 1359 cpufreq_frequency_table_get_attr(data->powernow_table, pol->cpu); 1360 1361 if (cpu_family == CPU_HW_PSTATE) 1362 pr_debug("cpu_init done, current pstate 0x%x\n", 1363 data->currpstate); 1364 else 1365 pr_debug("cpu_init done, current fid 0x%x, vid 0x%x\n", 1366 data->currfid, data->currvid); 1367 1368 per_cpu(powernow_data, pol->cpu) = data; 1369 1370 return 0; 1371 1372err_out_exit_acpi: 1373 powernow_k8_cpu_exit_acpi(data); 1374 1375err_out: 1376 kfree(data); 1377 return -ENODEV; 1378} 1379 1380static int __devexit powernowk8_cpu_exit(struct cpufreq_policy *pol) 1381{ 1382 struct powernow_k8_data *data = per_cpu(powernow_data, pol->cpu); 1383 1384 if (!data) 1385 return -EINVAL; 1386 1387 powernow_k8_cpu_exit_acpi(data); 1388 1389 cpufreq_frequency_table_put_attr(pol->cpu); 1390 1391 kfree(data->powernow_table); 1392 kfree(data); 1393 per_cpu(powernow_data, pol->cpu) = NULL; 1394 1395 return 0; 1396} 1397 1398static void query_values_on_cpu(void *_err) 1399{ 1400 int *err = _err; 1401 struct powernow_k8_data *data = __this_cpu_read(powernow_data); 1402 1403 *err = query_current_values_with_pending_wait(data); 1404} 1405 1406static unsigned int powernowk8_get(unsigned int cpu) 1407{ 1408 struct powernow_k8_data *data = per_cpu(powernow_data, cpu); 1409 unsigned int khz = 0; 1410 int err; 1411 1412 if (!data) 1413 return 0; 1414 1415 smp_call_function_single(cpu, query_values_on_cpu, &err, true); 1416 if (err) 1417 goto out; 1418 1419 if (cpu_family == CPU_HW_PSTATE) 1420 khz = find_khz_freq_from_pstate(data->powernow_table, 1421 data->currpstate); 1422 else 1423 khz = find_khz_freq_from_fid(data->currfid); 1424 1425 1426out: 1427 return khz; 1428} 1429 1430static void _cpb_toggle_msrs(bool t) 1431{ 1432 int cpu; 1433 1434 get_online_cpus(); 1435 1436 rdmsr_on_cpus(cpu_online_mask, MSR_K7_HWCR, msrs); 1437 1438 for_each_cpu(cpu, cpu_online_mask) { 1439 struct msr *reg = per_cpu_ptr(msrs, cpu); 1440 if (t) 1441 reg->l &= ~BIT(25); 1442 else 1443 reg->l |= BIT(25); 1444 } 1445 wrmsr_on_cpus(cpu_online_mask, MSR_K7_HWCR, msrs); 1446 1447 put_online_cpus(); 1448} 1449 1450/* 1451 * Switch on/off core performance boosting. 1452 * 1453 * 0=disable 1454 * 1=enable. 1455 */ 1456static void cpb_toggle(bool t) 1457{ 1458 if (!cpb_capable) 1459 return; 1460 1461 if (t && !cpb_enabled) { 1462 cpb_enabled = true; 1463 _cpb_toggle_msrs(t); 1464 printk(KERN_INFO PFX "Core Boosting enabled.\n"); 1465 } else if (!t && cpb_enabled) { 1466 cpb_enabled = false; 1467 _cpb_toggle_msrs(t); 1468 printk(KERN_INFO PFX "Core Boosting disabled.\n"); 1469 } 1470} 1471 1472static ssize_t store_cpb(struct cpufreq_policy *policy, const char *buf, 1473 size_t count) 1474{ 1475 int ret = -EINVAL; 1476 unsigned long val = 0; 1477 1478 ret = strict_strtoul(buf, 10, &val); 1479 if (!ret && (val == 0 || val == 1) && cpb_capable) 1480 cpb_toggle(val); 1481 else 1482 return -EINVAL; 1483 1484 return count; 1485} 1486 1487static ssize_t show_cpb(struct cpufreq_policy *policy, char *buf) 1488{ 1489 return sprintf(buf, "%u\n", cpb_enabled); 1490} 1491 1492#define define_one_rw(_name) \ 1493static struct freq_attr _name = \ 1494__ATTR(_name, 0644, show_##_name, store_##_name) 1495 1496define_one_rw(cpb); 1497 1498static struct freq_attr *powernow_k8_attr[] = { 1499 &cpufreq_freq_attr_scaling_available_freqs, 1500 &cpb, 1501 NULL, 1502}; 1503 1504static struct cpufreq_driver cpufreq_amd64_driver = { 1505 .verify = powernowk8_verify, 1506 .target = powernowk8_target, 1507 .bios_limit = acpi_processor_get_bios_limit, 1508 .init = powernowk8_cpu_init, 1509 .exit = __devexit_p(powernowk8_cpu_exit), 1510 .get = powernowk8_get, 1511 .name = "powernow-k8", 1512 .owner = THIS_MODULE, 1513 .attr = powernow_k8_attr, 1514}; 1515 1516/* 1517 * Clear the boost-disable flag on the CPU_DOWN path so that this cpu 1518 * cannot block the remaining ones from boosting. On the CPU_UP path we 1519 * simply keep the boost-disable flag in sync with the current global 1520 * state. 1521 */ 1522static int cpb_notify(struct notifier_block *nb, unsigned long action, 1523 void *hcpu) 1524{ 1525 unsigned cpu = (long)hcpu; 1526 u32 lo, hi; 1527 1528 switch (action) { 1529 case CPU_UP_PREPARE: 1530 case CPU_UP_PREPARE_FROZEN: 1531 1532 if (!cpb_enabled) { 1533 rdmsr_on_cpu(cpu, MSR_K7_HWCR, &lo, &hi); 1534 lo |= BIT(25); 1535 wrmsr_on_cpu(cpu, MSR_K7_HWCR, lo, hi); 1536 } 1537 break; 1538 1539 case CPU_DOWN_PREPARE: 1540 case CPU_DOWN_PREPARE_FROZEN: 1541 rdmsr_on_cpu(cpu, MSR_K7_HWCR, &lo, &hi); 1542 lo &= ~BIT(25); 1543 wrmsr_on_cpu(cpu, MSR_K7_HWCR, lo, hi); 1544 break; 1545 1546 default: 1547 break; 1548 } 1549 1550 return NOTIFY_OK; 1551} 1552 1553static struct notifier_block cpb_nb = { 1554 .notifier_call = cpb_notify, 1555}; 1556 1557/* driver entry point for init */ 1558static int __cpuinit powernowk8_init(void) 1559{ 1560 unsigned int i, supported_cpus = 0, cpu; 1561 int rv; 1562 1563 if (!x86_match_cpu(powernow_k8_ids)) 1564 return -ENODEV; 1565 1566 if (static_cpu_has(X86_FEATURE_HW_PSTATE)) 1567 pr_warn(PFX "support for this CPU is deprecated, use acpi-cpufreq instead.\n"); 1568 1569 for_each_online_cpu(i) { 1570 int rc; 1571 smp_call_function_single(i, check_supported_cpu, &rc, 1); 1572 if (rc == 0) 1573 supported_cpus++; 1574 } 1575 1576 if (supported_cpus != num_online_cpus()) 1577 return -ENODEV; 1578 1579 if (boot_cpu_has(X86_FEATURE_CPB)) { 1580 1581 cpb_capable = true; 1582 1583 msrs = msrs_alloc(); 1584 if (!msrs) { 1585 printk(KERN_ERR "%s: Error allocating msrs!\n", __func__); 1586 return -ENOMEM; 1587 } 1588 1589 register_cpu_notifier(&cpb_nb); 1590 1591 rdmsr_on_cpus(cpu_online_mask, MSR_K7_HWCR, msrs); 1592 1593 for_each_cpu(cpu, cpu_online_mask) { 1594 struct msr *reg = per_cpu_ptr(msrs, cpu); 1595 cpb_enabled |= !(!!(reg->l & BIT(25))); 1596 } 1597 } 1598 1599 rv = cpufreq_register_driver(&cpufreq_amd64_driver); 1600 1601 if (!rv) 1602 pr_info(PFX "Found %d %s (%d cpu cores) (" VERSION ")\n", 1603 num_online_nodes(), boot_cpu_data.x86_model_id, 1604 supported_cpus); 1605 1606 if (boot_cpu_has(X86_FEATURE_CPB)) { 1607 if (rv < 0) { 1608 unregister_cpu_notifier(&cpb_nb); 1609 msrs_free(msrs); 1610 msrs = NULL; 1611 } else 1612 pr_info(PFX "Core Performance Boosting: %s.\n", 1613 (cpb_enabled ? "on" : "off")); 1614 } 1615 return rv; 1616} 1617 1618/* driver entry point for term */ 1619static void __exit powernowk8_exit(void) 1620{ 1621 pr_debug("exit\n"); 1622 1623 if (boot_cpu_has(X86_FEATURE_CPB)) { 1624 msrs_free(msrs); 1625 msrs = NULL; 1626 1627 unregister_cpu_notifier(&cpb_nb); 1628 } 1629 1630 cpufreq_unregister_driver(&cpufreq_amd64_driver); 1631} 1632 1633MODULE_AUTHOR("Paul Devriendt <paul.devriendt@amd.com> and " 1634 "Mark Langsdorf <mark.langsdorf@amd.com>"); 1635MODULE_DESCRIPTION("AMD Athlon 64 and Opteron processor frequency driver."); 1636MODULE_LICENSE("GPL"); 1637 1638late_initcall(powernowk8_init); 1639module_exit(powernowk8_exit); 1640