10bbd5f4e97ff9c057b385a1886b4aed1fb0300f1Chris Leech/* 2211a22ce08dbb27eb1a66df8a4bdae5e96092bc8Maciej Sosnowski * Copyright(c) 2004 - 2009 Intel Corporation. All rights reserved. 30bbd5f4e97ff9c057b385a1886b4aed1fb0300f1Chris Leech * 40bbd5f4e97ff9c057b385a1886b4aed1fb0300f1Chris Leech * This program is free software; you can redistribute it and/or modify it 50bbd5f4e97ff9c057b385a1886b4aed1fb0300f1Chris Leech * under the terms of the GNU General Public License as published by the Free 60bbd5f4e97ff9c057b385a1886b4aed1fb0300f1Chris Leech * Software Foundation; either version 2 of the License, or (at your option) 70bbd5f4e97ff9c057b385a1886b4aed1fb0300f1Chris Leech * any later version. 80bbd5f4e97ff9c057b385a1886b4aed1fb0300f1Chris Leech * 90bbd5f4e97ff9c057b385a1886b4aed1fb0300f1Chris Leech * This program is distributed in the hope that it will be useful, but WITHOUT 100bbd5f4e97ff9c057b385a1886b4aed1fb0300f1Chris Leech * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 110bbd5f4e97ff9c057b385a1886b4aed1fb0300f1Chris Leech * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 120bbd5f4e97ff9c057b385a1886b4aed1fb0300f1Chris Leech * more details. 130bbd5f4e97ff9c057b385a1886b4aed1fb0300f1Chris Leech * 140bbd5f4e97ff9c057b385a1886b4aed1fb0300f1Chris Leech * You should have received a copy of the GNU General Public License along with 150bbd5f4e97ff9c057b385a1886b4aed1fb0300f1Chris Leech * this program; if not, write to the Free Software Foundation, Inc., 59 160bbd5f4e97ff9c057b385a1886b4aed1fb0300f1Chris Leech * Temple Place - Suite 330, Boston, MA 02111-1307, USA. 170bbd5f4e97ff9c057b385a1886b4aed1fb0300f1Chris Leech * 180bbd5f4e97ff9c057b385a1886b4aed1fb0300f1Chris Leech * The full GNU General Public License is included in this distribution in the 190bbd5f4e97ff9c057b385a1886b4aed1fb0300f1Chris Leech * file called COPYING. 200bbd5f4e97ff9c057b385a1886b4aed1fb0300f1Chris Leech */ 210bbd5f4e97ff9c057b385a1886b4aed1fb0300f1Chris Leech#ifndef _IOAT_REGISTERS_H_ 220bbd5f4e97ff9c057b385a1886b4aed1fb0300f1Chris Leech#define _IOAT_REGISTERS_H_ 230bbd5f4e97ff9c057b385a1886b4aed1fb0300f1Chris Leech 243e037454bcfa4b187e8293d2121bd8c0f5a5c31cShannon Nelson#define IOAT_PCI_DMACTRL_OFFSET 0x48 253e037454bcfa4b187e8293d2121bd8c0f5a5c31cShannon Nelson#define IOAT_PCI_DMACTRL_DMA_EN 0x00000001 263e037454bcfa4b187e8293d2121bd8c0f5a5c31cShannon Nelson#define IOAT_PCI_DMACTRL_MSI_EN 0x00000002 270bbd5f4e97ff9c057b385a1886b4aed1fb0300f1Chris Leech 287f1b358a236ee9c19657a619ac6f2dcabcaa0924Maciej Sosnowski#define IOAT_PCI_DEVICE_ID_OFFSET 0x02 297f1b358a236ee9c19657a619ac6f2dcabcaa0924Maciej Sosnowski#define IOAT_PCI_DMAUNCERRSTS_OFFSET 0x148 30a6d52d70677e99bdb89b6921c265d0a58c22e597Dan Williams#define IOAT_PCI_CHANERR_INT_OFFSET 0x180 317f1b358a236ee9c19657a619ac6f2dcabcaa0924Maciej Sosnowski#define IOAT_PCI_CHANERRMASK_INT_OFFSET 0x184 327f1b358a236ee9c19657a619ac6f2dcabcaa0924Maciej Sosnowski 330bbd5f4e97ff9c057b385a1886b4aed1fb0300f1Chris Leech/* MMIO Device Registers */ 340bbd5f4e97ff9c057b385a1886b4aed1fb0300f1Chris Leech#define IOAT_CHANCNT_OFFSET 0x00 /* 8-bit */ 350bbd5f4e97ff9c057b385a1886b4aed1fb0300f1Chris Leech 360bbd5f4e97ff9c057b385a1886b4aed1fb0300f1Chris Leech#define IOAT_XFERCAP_OFFSET 0x01 /* 8-bit */ 370bbd5f4e97ff9c057b385a1886b4aed1fb0300f1Chris Leech#define IOAT_XFERCAP_4KB 12 380bbd5f4e97ff9c057b385a1886b4aed1fb0300f1Chris Leech#define IOAT_XFERCAP_8KB 13 390bbd5f4e97ff9c057b385a1886b4aed1fb0300f1Chris Leech#define IOAT_XFERCAP_16KB 14 400bbd5f4e97ff9c057b385a1886b4aed1fb0300f1Chris Leech#define IOAT_XFERCAP_32KB 15 410bbd5f4e97ff9c057b385a1886b4aed1fb0300f1Chris Leech#define IOAT_XFERCAP_32GB 0 420bbd5f4e97ff9c057b385a1886b4aed1fb0300f1Chris Leech 430bbd5f4e97ff9c057b385a1886b4aed1fb0300f1Chris Leech#define IOAT_GENCTRL_OFFSET 0x02 /* 8-bit */ 440bbd5f4e97ff9c057b385a1886b4aed1fb0300f1Chris Leech#define IOAT_GENCTRL_DEBUG_EN 0x01 450bbd5f4e97ff9c057b385a1886b4aed1fb0300f1Chris Leech 460bbd5f4e97ff9c057b385a1886b4aed1fb0300f1Chris Leech#define IOAT_INTRCTRL_OFFSET 0x03 /* 8-bit */ 470bbd5f4e97ff9c057b385a1886b4aed1fb0300f1Chris Leech#define IOAT_INTRCTRL_MASTER_INT_EN 0x01 /* Master Interrupt Enable */ 480bbd5f4e97ff9c057b385a1886b4aed1fb0300f1Chris Leech#define IOAT_INTRCTRL_INT_STATUS 0x02 /* ATTNSTATUS -or- Channel Int */ 490bbd5f4e97ff9c057b385a1886b4aed1fb0300f1Chris Leech#define IOAT_INTRCTRL_INT 0x04 /* INT_STATUS -and- MASTER_INT_EN */ 507bb67c14fd3778504fb77da30ce11582336dfcedShannon Nelson#define IOAT_INTRCTRL_MSIX_VECTOR_CONTROL 0x08 /* Enable all MSI-X vectors */ 510bbd5f4e97ff9c057b385a1886b4aed1fb0300f1Chris Leech 520bbd5f4e97ff9c057b385a1886b4aed1fb0300f1Chris Leech#define IOAT_ATTNSTATUS_OFFSET 0x04 /* Each bit is a channel */ 530bbd5f4e97ff9c057b385a1886b4aed1fb0300f1Chris Leech 540bbd5f4e97ff9c057b385a1886b4aed1fb0300f1Chris Leech#define IOAT_VER_OFFSET 0x08 /* 8-bit */ 550bbd5f4e97ff9c057b385a1886b4aed1fb0300f1Chris Leech#define IOAT_VER_MAJOR_MASK 0xF0 560bbd5f4e97ff9c057b385a1886b4aed1fb0300f1Chris Leech#define IOAT_VER_MINOR_MASK 0x0F 577bb67c14fd3778504fb77da30ce11582336dfcedShannon Nelson#define GET_IOAT_VER_MAJOR(x) (((x) & IOAT_VER_MAJOR_MASK) >> 4) 580bbd5f4e97ff9c057b385a1886b4aed1fb0300f1Chris Leech#define GET_IOAT_VER_MINOR(x) ((x) & IOAT_VER_MINOR_MASK) 590bbd5f4e97ff9c057b385a1886b4aed1fb0300f1Chris Leech 600bbd5f4e97ff9c057b385a1886b4aed1fb0300f1Chris Leech#define IOAT_PERPORTOFFSET_OFFSET 0x0A /* 16-bit */ 610bbd5f4e97ff9c057b385a1886b4aed1fb0300f1Chris Leech 620bbd5f4e97ff9c057b385a1886b4aed1fb0300f1Chris Leech#define IOAT_INTRDELAY_OFFSET 0x0C /* 16-bit */ 63b9cc98697d1ca35a86bbb708acc6d93993c28f0fDan Williams#define IOAT_INTRDELAY_MASK 0x3FFF /* Interrupt Delay Time */ 647bb67c14fd3778504fb77da30ce11582336dfcedShannon Nelson#define IOAT_INTRDELAY_COALESE_SUPPORT 0x8000 /* Interrupt Coalescing Supported */ 650bbd5f4e97ff9c057b385a1886b4aed1fb0300f1Chris Leech 660bbd5f4e97ff9c057b385a1886b4aed1fb0300f1Chris Leech#define IOAT_DEVICE_STATUS_OFFSET 0x0E /* 16-bit */ 670bbd5f4e97ff9c057b385a1886b4aed1fb0300f1Chris Leech#define IOAT_DEVICE_STATUS_DEGRADED_MODE 0x0001 682aec048cdc4a5a81163a42a61df903f76a27e737Dan Williams#define IOAT_DEVICE_MMIO_RESTRICTED 0x0002 692aec048cdc4a5a81163a42a61df903f76a27e737Dan Williams#define IOAT_DEVICE_MEMORY_BYPASS 0x0004 702aec048cdc4a5a81163a42a61df903f76a27e737Dan Williams#define IOAT_DEVICE_ADDRESS_REMAPPING 0x0008 712aec048cdc4a5a81163a42a61df903f76a27e737Dan Williams 722aec048cdc4a5a81163a42a61df903f76a27e737Dan Williams#define IOAT_DMA_CAP_OFFSET 0x10 /* 32-bit */ 732aec048cdc4a5a81163a42a61df903f76a27e737Dan Williams#define IOAT_CAP_PAGE_BREAK 0x00000001 742aec048cdc4a5a81163a42a61df903f76a27e737Dan Williams#define IOAT_CAP_CRC 0x00000002 752aec048cdc4a5a81163a42a61df903f76a27e737Dan Williams#define IOAT_CAP_SKIP_MARKER 0x00000004 762aec048cdc4a5a81163a42a61df903f76a27e737Dan Williams#define IOAT_CAP_DCA 0x00000010 772aec048cdc4a5a81163a42a61df903f76a27e737Dan Williams#define IOAT_CAP_CRC_MOVE 0x00000020 782aec048cdc4a5a81163a42a61df903f76a27e737Dan Williams#define IOAT_CAP_FILL_BLOCK 0x00000040 792aec048cdc4a5a81163a42a61df903f76a27e737Dan Williams#define IOAT_CAP_APIC 0x00000080 802aec048cdc4a5a81163a42a61df903f76a27e737Dan Williams#define IOAT_CAP_XOR 0x00000100 812aec048cdc4a5a81163a42a61df903f76a27e737Dan Williams#define IOAT_CAP_PQ 0x00000200 8275c6f0ab480657269b5014e0e457c7b18ba8597eDave Jiang#define IOAT_CAP_DWBES 0x00002000 837727eaa4490b7244934fe31f05e7329f30715267Dave Jiang#define IOAT_CAP_RAID16SS 0x00020000 840bbd5f4e97ff9c057b385a1886b4aed1fb0300f1Chris Leech 850bbd5f4e97ff9c057b385a1886b4aed1fb0300f1Chris Leech#define IOAT_CHANNEL_MMIO_SIZE 0x80 /* Each Channel MMIO space is this size */ 860bbd5f4e97ff9c057b385a1886b4aed1fb0300f1Chris Leech 870bbd5f4e97ff9c057b385a1886b4aed1fb0300f1Chris Leech/* DMA Channel Registers */ 880bbd5f4e97ff9c057b385a1886b4aed1fb0300f1Chris Leech#define IOAT_CHANCTRL_OFFSET 0x00 /* 16-bit Channel Control Register */ 890bbd5f4e97ff9c057b385a1886b4aed1fb0300f1Chris Leech#define IOAT_CHANCTRL_CHANNEL_PRIORITY_MASK 0xF000 90e61dacaeb3918cd00cd642e8fb0828324ac59819Dan Williams#define IOAT3_CHANCTRL_COMPL_DCA_EN 0x0200 910bbd5f4e97ff9c057b385a1886b4aed1fb0300f1Chris Leech#define IOAT_CHANCTRL_CHANNEL_IN_USE 0x0100 920bbd5f4e97ff9c057b385a1886b4aed1fb0300f1Chris Leech#define IOAT_CHANCTRL_DESCRIPTOR_ADDR_SNOOP_CONTROL 0x0020 930bbd5f4e97ff9c057b385a1886b4aed1fb0300f1Chris Leech#define IOAT_CHANCTRL_ERR_INT_EN 0x0010 940bbd5f4e97ff9c057b385a1886b4aed1fb0300f1Chris Leech#define IOAT_CHANCTRL_ANY_ERR_ABORT_EN 0x0008 950bbd5f4e97ff9c057b385a1886b4aed1fb0300f1Chris Leech#define IOAT_CHANCTRL_ERR_COMPLETION_EN 0x0004 96f6ab95b55735fa03cad8d0f966647e5df206e207Dan Williams#define IOAT_CHANCTRL_INT_REARM 0x0001 97f6ab95b55735fa03cad8d0f966647e5df206e207Dan Williams#define IOAT_CHANCTRL_RUN (IOAT_CHANCTRL_INT_REARM |\ 983f09ede4237fe4691ac687c6c43cb4c1a530777bDave Jiang IOAT_CHANCTRL_ERR_INT_EN |\ 993f09ede4237fe4691ac687c6c43cb4c1a530777bDave Jiang IOAT_CHANCTRL_ERR_COMPLETION_EN |\ 1006f82b83b7a56bc6e9dd6d7b93531dde6027c5309Dan Williams IOAT_CHANCTRL_ANY_ERR_ABORT_EN) 1010bbd5f4e97ff9c057b385a1886b4aed1fb0300f1Chris Leech 1027bb67c14fd3778504fb77da30ce11582336dfcedShannon Nelson#define IOAT_DMA_COMP_OFFSET 0x02 /* 16-bit DMA channel compatibility */ 1037bb67c14fd3778504fb77da30ce11582336dfcedShannon Nelson#define IOAT_DMA_COMP_V1 0x0001 /* Compatibility with DMA version 1 */ 1047bb67c14fd3778504fb77da30ce11582336dfcedShannon Nelson#define IOAT_DMA_COMP_V2 0x0002 /* Compatibility with DMA version 2 */ 1057bb67c14fd3778504fb77da30ce11582336dfcedShannon Nelson 1067bb67c14fd3778504fb77da30ce11582336dfcedShannon Nelson 1077bb67c14fd3778504fb77da30ce11582336dfcedShannon Nelson#define IOAT1_CHANSTS_OFFSET 0x04 /* 64-bit Channel Status Register */ 1087bb67c14fd3778504fb77da30ce11582336dfcedShannon Nelson#define IOAT2_CHANSTS_OFFSET 0x08 /* 64-bit Channel Status Register */ 1097bb67c14fd3778504fb77da30ce11582336dfcedShannon Nelson#define IOAT_CHANSTS_OFFSET(ver) ((ver) < IOAT_VER_2_0 \ 1107bb67c14fd3778504fb77da30ce11582336dfcedShannon Nelson ? IOAT1_CHANSTS_OFFSET : IOAT2_CHANSTS_OFFSET) 1117bb67c14fd3778504fb77da30ce11582336dfcedShannon Nelson#define IOAT1_CHANSTS_OFFSET_LOW 0x04 1127bb67c14fd3778504fb77da30ce11582336dfcedShannon Nelson#define IOAT2_CHANSTS_OFFSET_LOW 0x08 1137bb67c14fd3778504fb77da30ce11582336dfcedShannon Nelson#define IOAT_CHANSTS_OFFSET_LOW(ver) ((ver) < IOAT_VER_2_0 \ 1147bb67c14fd3778504fb77da30ce11582336dfcedShannon Nelson ? IOAT1_CHANSTS_OFFSET_LOW : IOAT2_CHANSTS_OFFSET_LOW) 1157bb67c14fd3778504fb77da30ce11582336dfcedShannon Nelson#define IOAT1_CHANSTS_OFFSET_HIGH 0x08 1167bb67c14fd3778504fb77da30ce11582336dfcedShannon Nelson#define IOAT2_CHANSTS_OFFSET_HIGH 0x0C 1177bb67c14fd3778504fb77da30ce11582336dfcedShannon Nelson#define IOAT_CHANSTS_OFFSET_HIGH(ver) ((ver) < IOAT_VER_2_0 \ 1187bb67c14fd3778504fb77da30ce11582336dfcedShannon Nelson ? IOAT1_CHANSTS_OFFSET_HIGH : IOAT2_CHANSTS_OFFSET_HIGH) 1194fb9b9e8d55880523db550043dfb204696dd0422Dan Williams#define IOAT_CHANSTS_COMPLETED_DESCRIPTOR_ADDR (~0x3fULL) 1204fb9b9e8d55880523db550043dfb204696dd0422Dan Williams#define IOAT_CHANSTS_SOFT_ERR 0x10ULL 1214fb9b9e8d55880523db550043dfb204696dd0422Dan Williams#define IOAT_CHANSTS_UNAFFILIATED_ERR 0x8ULL 12209c8a5b85e5f1e74a19bdd7c85547429d51df1cdDan Williams#define IOAT_CHANSTS_STATUS 0x7ULL 12309c8a5b85e5f1e74a19bdd7c85547429d51df1cdDan Williams#define IOAT_CHANSTS_ACTIVE 0x0 12409c8a5b85e5f1e74a19bdd7c85547429d51df1cdDan Williams#define IOAT_CHANSTS_DONE 0x1 12509c8a5b85e5f1e74a19bdd7c85547429d51df1cdDan Williams#define IOAT_CHANSTS_SUSPENDED 0x2 12609c8a5b85e5f1e74a19bdd7c85547429d51df1cdDan Williams#define IOAT_CHANSTS_HALTED 0x3 1270bbd5f4e97ff9c057b385a1886b4aed1fb0300f1Chris Leech 1280bbd5f4e97ff9c057b385a1886b4aed1fb0300f1Chris Leech 1297bb67c14fd3778504fb77da30ce11582336dfcedShannon Nelson 1307bb67c14fd3778504fb77da30ce11582336dfcedShannon Nelson#define IOAT_CHAN_DMACOUNT_OFFSET 0x06 /* 16-bit DMA Count register */ 1317bb67c14fd3778504fb77da30ce11582336dfcedShannon Nelson 1327bb67c14fd3778504fb77da30ce11582336dfcedShannon Nelson#define IOAT_DCACTRL_OFFSET 0x30 /* 32 bit Direct Cache Access Control Register */ 1337bb67c14fd3778504fb77da30ce11582336dfcedShannon Nelson#define IOAT_DCACTRL_CMPL_WRITE_ENABLE 0x10000 1347bb67c14fd3778504fb77da30ce11582336dfcedShannon Nelson#define IOAT_DCACTRL_TARGET_CPU_MASK 0xFFFF /* APIC ID */ 1357bb67c14fd3778504fb77da30ce11582336dfcedShannon Nelson 1367bb67c14fd3778504fb77da30ce11582336dfcedShannon Nelson/* CB DCA Memory Space Registers */ 1377bb67c14fd3778504fb77da30ce11582336dfcedShannon Nelson#define IOAT_DCAOFFSET_OFFSET 0x14 1387bb67c14fd3778504fb77da30ce11582336dfcedShannon Nelson/* CB_BAR + IOAT_DCAOFFSET value */ 1397bb67c14fd3778504fb77da30ce11582336dfcedShannon Nelson#define IOAT_DCA_VER_OFFSET 0x00 1407bb67c14fd3778504fb77da30ce11582336dfcedShannon Nelson#define IOAT_DCA_VER_MAJOR_MASK 0xF0 1417bb67c14fd3778504fb77da30ce11582336dfcedShannon Nelson#define IOAT_DCA_VER_MINOR_MASK 0x0F 1427bb67c14fd3778504fb77da30ce11582336dfcedShannon Nelson 1437bb67c14fd3778504fb77da30ce11582336dfcedShannon Nelson#define IOAT_DCA_COMP_OFFSET 0x02 1447bb67c14fd3778504fb77da30ce11582336dfcedShannon Nelson#define IOAT_DCA_COMP_V1 0x1 1457bb67c14fd3778504fb77da30ce11582336dfcedShannon Nelson 1467bb67c14fd3778504fb77da30ce11582336dfcedShannon Nelson#define IOAT_FSB_CAPABILITY_OFFSET 0x04 1477bb67c14fd3778504fb77da30ce11582336dfcedShannon Nelson#define IOAT_FSB_CAPABILITY_PREFETCH 0x1 1487bb67c14fd3778504fb77da30ce11582336dfcedShannon Nelson 1497bb67c14fd3778504fb77da30ce11582336dfcedShannon Nelson#define IOAT_PCI_CAPABILITY_OFFSET 0x06 1507bb67c14fd3778504fb77da30ce11582336dfcedShannon Nelson#define IOAT_PCI_CAPABILITY_MEMWR 0x1 1517bb67c14fd3778504fb77da30ce11582336dfcedShannon Nelson 1527bb67c14fd3778504fb77da30ce11582336dfcedShannon Nelson#define IOAT_FSB_CAP_ENABLE_OFFSET 0x08 1537bb67c14fd3778504fb77da30ce11582336dfcedShannon Nelson#define IOAT_FSB_CAP_ENABLE_PREFETCH 0x1 1547bb67c14fd3778504fb77da30ce11582336dfcedShannon Nelson 1557bb67c14fd3778504fb77da30ce11582336dfcedShannon Nelson#define IOAT_PCI_CAP_ENABLE_OFFSET 0x0A 1567bb67c14fd3778504fb77da30ce11582336dfcedShannon Nelson#define IOAT_PCI_CAP_ENABLE_MEMWR 0x1 1577bb67c14fd3778504fb77da30ce11582336dfcedShannon Nelson 1587bb67c14fd3778504fb77da30ce11582336dfcedShannon Nelson#define IOAT_APICID_TAG_MAP_OFFSET 0x0C 1597bb67c14fd3778504fb77da30ce11582336dfcedShannon Nelson#define IOAT_APICID_TAG_MAP_TAG0 0x0000000F 1607bb67c14fd3778504fb77da30ce11582336dfcedShannon Nelson#define IOAT_APICID_TAG_MAP_TAG0_SHIFT 0 1617bb67c14fd3778504fb77da30ce11582336dfcedShannon Nelson#define IOAT_APICID_TAG_MAP_TAG1 0x000000F0 1627bb67c14fd3778504fb77da30ce11582336dfcedShannon Nelson#define IOAT_APICID_TAG_MAP_TAG1_SHIFT 4 1637bb67c14fd3778504fb77da30ce11582336dfcedShannon Nelson#define IOAT_APICID_TAG_MAP_TAG2 0x00000F00 1647bb67c14fd3778504fb77da30ce11582336dfcedShannon Nelson#define IOAT_APICID_TAG_MAP_TAG2_SHIFT 8 1657bb67c14fd3778504fb77da30ce11582336dfcedShannon Nelson#define IOAT_APICID_TAG_MAP_TAG3 0x0000F000 1667bb67c14fd3778504fb77da30ce11582336dfcedShannon Nelson#define IOAT_APICID_TAG_MAP_TAG3_SHIFT 12 1677bb67c14fd3778504fb77da30ce11582336dfcedShannon Nelson#define IOAT_APICID_TAG_MAP_TAG4 0x000F0000 1687bb67c14fd3778504fb77da30ce11582336dfcedShannon Nelson#define IOAT_APICID_TAG_MAP_TAG4_SHIFT 16 1697bb67c14fd3778504fb77da30ce11582336dfcedShannon Nelson#define IOAT_APICID_TAG_CB2_VALID 0x8080808080 1707bb67c14fd3778504fb77da30ce11582336dfcedShannon Nelson 1717bb67c14fd3778504fb77da30ce11582336dfcedShannon Nelson#define IOAT_DCA_GREQID_OFFSET 0x10 1727bb67c14fd3778504fb77da30ce11582336dfcedShannon Nelson#define IOAT_DCA_GREQID_SIZE 0x04 1737bb67c14fd3778504fb77da30ce11582336dfcedShannon Nelson#define IOAT_DCA_GREQID_MASK 0xFFFF 1747bb67c14fd3778504fb77da30ce11582336dfcedShannon Nelson#define IOAT_DCA_GREQID_IGNOREFUN 0x10000000 1757bb67c14fd3778504fb77da30ce11582336dfcedShannon Nelson#define IOAT_DCA_GREQID_VALID 0x20000000 1767bb67c14fd3778504fb77da30ce11582336dfcedShannon Nelson#define IOAT_DCA_GREQID_LASTID 0x80000000 1777bb67c14fd3778504fb77da30ce11582336dfcedShannon Nelson 1787f1b358a236ee9c19657a619ac6f2dcabcaa0924Maciej Sosnowski#define IOAT3_CSI_CAPABILITY_OFFSET 0x08 1797f1b358a236ee9c19657a619ac6f2dcabcaa0924Maciej Sosnowski#define IOAT3_CSI_CAPABILITY_PREFETCH 0x1 1807f1b358a236ee9c19657a619ac6f2dcabcaa0924Maciej Sosnowski 1817f1b358a236ee9c19657a619ac6f2dcabcaa0924Maciej Sosnowski#define IOAT3_PCI_CAPABILITY_OFFSET 0x0A 1827f1b358a236ee9c19657a619ac6f2dcabcaa0924Maciej Sosnowski#define IOAT3_PCI_CAPABILITY_MEMWR 0x1 1837f1b358a236ee9c19657a619ac6f2dcabcaa0924Maciej Sosnowski 1847f1b358a236ee9c19657a619ac6f2dcabcaa0924Maciej Sosnowski#define IOAT3_CSI_CONTROL_OFFSET 0x0C 1857f1b358a236ee9c19657a619ac6f2dcabcaa0924Maciej Sosnowski#define IOAT3_CSI_CONTROL_PREFETCH 0x1 1867f1b358a236ee9c19657a619ac6f2dcabcaa0924Maciej Sosnowski 1877f1b358a236ee9c19657a619ac6f2dcabcaa0924Maciej Sosnowski#define IOAT3_PCI_CONTROL_OFFSET 0x0E 1887f1b358a236ee9c19657a619ac6f2dcabcaa0924Maciej Sosnowski#define IOAT3_PCI_CONTROL_MEMWR 0x1 1897f1b358a236ee9c19657a619ac6f2dcabcaa0924Maciej Sosnowski 1907f1b358a236ee9c19657a619ac6f2dcabcaa0924Maciej Sosnowski#define IOAT3_APICID_TAG_MAP_OFFSET 0x10 1917f1b358a236ee9c19657a619ac6f2dcabcaa0924Maciej Sosnowski#define IOAT3_APICID_TAG_MAP_OFFSET_LOW 0x10 1927f1b358a236ee9c19657a619ac6f2dcabcaa0924Maciej Sosnowski#define IOAT3_APICID_TAG_MAP_OFFSET_HIGH 0x14 1937bb67c14fd3778504fb77da30ce11582336dfcedShannon Nelson 1947f1b358a236ee9c19657a619ac6f2dcabcaa0924Maciej Sosnowski#define IOAT3_DCA_GREQID_OFFSET 0x02 1957bb67c14fd3778504fb77da30ce11582336dfcedShannon Nelson 1967bb67c14fd3778504fb77da30ce11582336dfcedShannon Nelson#define IOAT1_CHAINADDR_OFFSET 0x0C /* 64-bit Descriptor Chain Address Register */ 1977bb67c14fd3778504fb77da30ce11582336dfcedShannon Nelson#define IOAT2_CHAINADDR_OFFSET 0x10 /* 64-bit Descriptor Chain Address Register */ 1987bb67c14fd3778504fb77da30ce11582336dfcedShannon Nelson#define IOAT_CHAINADDR_OFFSET(ver) ((ver) < IOAT_VER_2_0 \ 1997bb67c14fd3778504fb77da30ce11582336dfcedShannon Nelson ? IOAT1_CHAINADDR_OFFSET : IOAT2_CHAINADDR_OFFSET) 2007bb67c14fd3778504fb77da30ce11582336dfcedShannon Nelson#define IOAT1_CHAINADDR_OFFSET_LOW 0x0C 2017bb67c14fd3778504fb77da30ce11582336dfcedShannon Nelson#define IOAT2_CHAINADDR_OFFSET_LOW 0x10 2027bb67c14fd3778504fb77da30ce11582336dfcedShannon Nelson#define IOAT_CHAINADDR_OFFSET_LOW(ver) ((ver) < IOAT_VER_2_0 \ 2037bb67c14fd3778504fb77da30ce11582336dfcedShannon Nelson ? IOAT1_CHAINADDR_OFFSET_LOW : IOAT2_CHAINADDR_OFFSET_LOW) 2047bb67c14fd3778504fb77da30ce11582336dfcedShannon Nelson#define IOAT1_CHAINADDR_OFFSET_HIGH 0x10 2057bb67c14fd3778504fb77da30ce11582336dfcedShannon Nelson#define IOAT2_CHAINADDR_OFFSET_HIGH 0x14 2067bb67c14fd3778504fb77da30ce11582336dfcedShannon Nelson#define IOAT_CHAINADDR_OFFSET_HIGH(ver) ((ver) < IOAT_VER_2_0 \ 2077bb67c14fd3778504fb77da30ce11582336dfcedShannon Nelson ? IOAT1_CHAINADDR_OFFSET_HIGH : IOAT2_CHAINADDR_OFFSET_HIGH) 2087bb67c14fd3778504fb77da30ce11582336dfcedShannon Nelson 2097bb67c14fd3778504fb77da30ce11582336dfcedShannon Nelson#define IOAT1_CHANCMD_OFFSET 0x14 /* 8-bit DMA Channel Command Register */ 2107bb67c14fd3778504fb77da30ce11582336dfcedShannon Nelson#define IOAT2_CHANCMD_OFFSET 0x04 /* 8-bit DMA Channel Command Register */ 2117bb67c14fd3778504fb77da30ce11582336dfcedShannon Nelson#define IOAT_CHANCMD_OFFSET(ver) ((ver) < IOAT_VER_2_0 \ 2127bb67c14fd3778504fb77da30ce11582336dfcedShannon Nelson ? IOAT1_CHANCMD_OFFSET : IOAT2_CHANCMD_OFFSET) 2130bbd5f4e97ff9c057b385a1886b4aed1fb0300f1Chris Leech#define IOAT_CHANCMD_RESET 0x20 2140bbd5f4e97ff9c057b385a1886b4aed1fb0300f1Chris Leech#define IOAT_CHANCMD_RESUME 0x10 2150bbd5f4e97ff9c057b385a1886b4aed1fb0300f1Chris Leech#define IOAT_CHANCMD_ABORT 0x08 2160bbd5f4e97ff9c057b385a1886b4aed1fb0300f1Chris Leech#define IOAT_CHANCMD_SUSPEND 0x04 2170bbd5f4e97ff9c057b385a1886b4aed1fb0300f1Chris Leech#define IOAT_CHANCMD_APPEND 0x02 2180bbd5f4e97ff9c057b385a1886b4aed1fb0300f1Chris Leech#define IOAT_CHANCMD_START 0x01 2190bbd5f4e97ff9c057b385a1886b4aed1fb0300f1Chris Leech 2200bbd5f4e97ff9c057b385a1886b4aed1fb0300f1Chris Leech#define IOAT_CHANCMP_OFFSET 0x18 /* 64-bit Channel Completion Address Register */ 2210bbd5f4e97ff9c057b385a1886b4aed1fb0300f1Chris Leech#define IOAT_CHANCMP_OFFSET_LOW 0x18 2220bbd5f4e97ff9c057b385a1886b4aed1fb0300f1Chris Leech#define IOAT_CHANCMP_OFFSET_HIGH 0x1C 2230bbd5f4e97ff9c057b385a1886b4aed1fb0300f1Chris Leech 2240bbd5f4e97ff9c057b385a1886b4aed1fb0300f1Chris Leech#define IOAT_CDAR_OFFSET 0x20 /* 64-bit Current Descriptor Address Register */ 2250bbd5f4e97ff9c057b385a1886b4aed1fb0300f1Chris Leech#define IOAT_CDAR_OFFSET_LOW 0x20 2260bbd5f4e97ff9c057b385a1886b4aed1fb0300f1Chris Leech#define IOAT_CDAR_OFFSET_HIGH 0x24 2270bbd5f4e97ff9c057b385a1886b4aed1fb0300f1Chris Leech 2280bbd5f4e97ff9c057b385a1886b4aed1fb0300f1Chris Leech#define IOAT_CHANERR_OFFSET 0x28 /* 32-bit Channel Error Register */ 22909c8a5b85e5f1e74a19bdd7c85547429d51df1cdDan Williams#define IOAT_CHANERR_SRC_ADDR_ERR 0x0001 23009c8a5b85e5f1e74a19bdd7c85547429d51df1cdDan Williams#define IOAT_CHANERR_DEST_ADDR_ERR 0x0002 23109c8a5b85e5f1e74a19bdd7c85547429d51df1cdDan Williams#define IOAT_CHANERR_NEXT_ADDR_ERR 0x0004 23209c8a5b85e5f1e74a19bdd7c85547429d51df1cdDan Williams#define IOAT_CHANERR_NEXT_DESC_ALIGN_ERR 0x0008 2330bbd5f4e97ff9c057b385a1886b4aed1fb0300f1Chris Leech#define IOAT_CHANERR_CHAIN_ADDR_VALUE_ERR 0x0010 2340bbd5f4e97ff9c057b385a1886b4aed1fb0300f1Chris Leech#define IOAT_CHANERR_CHANCMD_ERR 0x0020 2350bbd5f4e97ff9c057b385a1886b4aed1fb0300f1Chris Leech#define IOAT_CHANERR_CHIPSET_UNCORRECTABLE_DATA_INTEGRITY_ERR 0x0040 2360bbd5f4e97ff9c057b385a1886b4aed1fb0300f1Chris Leech#define IOAT_CHANERR_DMA_UNCORRECTABLE_DATA_INTEGRITY_ERR 0x0080 2370bbd5f4e97ff9c057b385a1886b4aed1fb0300f1Chris Leech#define IOAT_CHANERR_READ_DATA_ERR 0x0100 2380bbd5f4e97ff9c057b385a1886b4aed1fb0300f1Chris Leech#define IOAT_CHANERR_WRITE_DATA_ERR 0x0200 23909c8a5b85e5f1e74a19bdd7c85547429d51df1cdDan Williams#define IOAT_CHANERR_CONTROL_ERR 0x0400 24009c8a5b85e5f1e74a19bdd7c85547429d51df1cdDan Williams#define IOAT_CHANERR_LENGTH_ERR 0x0800 2410bbd5f4e97ff9c057b385a1886b4aed1fb0300f1Chris Leech#define IOAT_CHANERR_COMPLETION_ADDR_ERR 0x1000 2420bbd5f4e97ff9c057b385a1886b4aed1fb0300f1Chris Leech#define IOAT_CHANERR_INT_CONFIGURATION_ERR 0x2000 2430bbd5f4e97ff9c057b385a1886b4aed1fb0300f1Chris Leech#define IOAT_CHANERR_SOFT_ERR 0x4000 2447bb67c14fd3778504fb77da30ce11582336dfcedShannon Nelson#define IOAT_CHANERR_UNAFFILIATED_ERR 0x8000 2452aec048cdc4a5a81163a42a61df903f76a27e737Dan Williams#define IOAT_CHANERR_XOR_P_OR_CRC_ERR 0x10000 2462aec048cdc4a5a81163a42a61df903f76a27e737Dan Williams#define IOAT_CHANERR_XOR_Q_ERR 0x20000 2472aec048cdc4a5a81163a42a61df903f76a27e737Dan Williams#define IOAT_CHANERR_DESCRIPTOR_COUNT_ERR 0x40000 2480bbd5f4e97ff9c057b385a1886b4aed1fb0300f1Chris Leech 249b094ad3be564e7cc59cca4ff0256550d3a55dd3bDan Williams#define IOAT_CHANERR_HANDLE_MASK (IOAT_CHANERR_XOR_P_OR_CRC_ERR | IOAT_CHANERR_XOR_Q_ERR) 250b094ad3be564e7cc59cca4ff0256550d3a55dd3bDan Williams 2510bbd5f4e97ff9c057b385a1886b4aed1fb0300f1Chris Leech#define IOAT_CHANERR_MASK_OFFSET 0x2C /* 32-bit Channel Error Register */ 2520bbd5f4e97ff9c057b385a1886b4aed1fb0300f1Chris Leech 2530bbd5f4e97ff9c057b385a1886b4aed1fb0300f1Chris Leech#endif /* _IOAT_REGISTERS_H_ */ 254