shdma.h revision 115357e9774ff8d70a84d3c31f271209913637b0 
1/*
2 * Renesas SuperH DMA Engine support
3 *
4 * Copyright (C) 2009 Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>
5 * Copyright (C) 2009 Renesas Solutions, Inc. All rights reserved.
6 *
7 * This is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 */
13#ifndef __DMA_SHDMA_H
14#define __DMA_SHDMA_H
15
16#include <linux/sh_dma.h>
17#include <linux/shdma-base.h>
18#include <linux/dmaengine.h>
19#include <linux/interrupt.h>
20#include <linux/list.h>
21
22#define SH_DMAE_MAX_CHANNELS 20
23#define SH_DMAE_TCR_MAX 0x00FFFFFF	/* 16MB */
24
25struct device;
26
27struct sh_dmae_chan {
28	struct shdma_chan shdma_chan;
29	const struct sh_dmae_slave_config *config; /* Slave DMA configuration */
30	int xmit_shift;			/* log_2(bytes_per_xfer) */
31	void __iomem *base;
32	char dev_id[16];		/* unique name per DMAC of channel */
33	int pm_error;
34};
35
36struct sh_dmae_device {
37	struct shdma_dev shdma_dev;
38	struct sh_dmae_chan *chan[SH_DMAE_MAX_CHANNELS];
39	struct sh_dmae_pdata *pdata;
40	struct list_head node;
41	void __iomem *chan_reg;
42	void __iomem *dmars;
43	unsigned int chcr_offset;
44	u32 chcr_ie_bit;
45};
46
47struct sh_dmae_regs {
48	u32 sar; /* SAR / source address */
49	u32 dar; /* DAR / destination address */
50	u32 tcr; /* TCR / transfer count */
51};
52
53struct sh_dmae_desc {
54	struct sh_dmae_regs hw;
55	struct shdma_desc shdma_desc;
56};
57
58#define to_sh_chan(chan) container_of(chan, struct sh_dmae_chan, shdma_chan)
59#define to_sh_desc(lh) container_of(lh, struct sh_desc, node)
60#define tx_to_sh_desc(tx) container_of(tx, struct sh_desc, async_tx)
61#define to_sh_dev(chan) container_of(chan->shdma_chan.dma_chan.device,\
62				     struct sh_dmae_device, shdma_dev.dma_dev)
63
64#endif	/* __DMA_SHDMA_H */
65