1a35a2818801387f01a145ebe4a99a6a1fda31152Harry Ciao/* 2a35a2818801387f01a145ebe4a99a6a1fda31152Harry Ciao * amd8131_edac.h, EDAC defs for AMD8131 hypertransport chip 3a35a2818801387f01a145ebe4a99a6a1fda31152Harry Ciao * 4a35a2818801387f01a145ebe4a99a6a1fda31152Harry Ciao * Copyright (c) 2008 Wind River Systems, Inc. 5a35a2818801387f01a145ebe4a99a6a1fda31152Harry Ciao * 6a35a2818801387f01a145ebe4a99a6a1fda31152Harry Ciao * Authors: Cao Qingtao <qingtao.cao@windriver.com> 7a35a2818801387f01a145ebe4a99a6a1fda31152Harry Ciao * Benjamin Walsh <benjamin.walsh@windriver.com> 8a35a2818801387f01a145ebe4a99a6a1fda31152Harry Ciao * Hu Yongqi <yongqi.hu@windriver.com> 9a35a2818801387f01a145ebe4a99a6a1fda31152Harry Ciao * 10a35a2818801387f01a145ebe4a99a6a1fda31152Harry Ciao * This program is free software; you can redistribute it and/or modify 11a35a2818801387f01a145ebe4a99a6a1fda31152Harry Ciao * it under the terms of the GNU General Public License version 2 as 12a35a2818801387f01a145ebe4a99a6a1fda31152Harry Ciao * published by the Free Software Foundation. 13a35a2818801387f01a145ebe4a99a6a1fda31152Harry Ciao * 14a35a2818801387f01a145ebe4a99a6a1fda31152Harry Ciao * This program is distributed in the hope that it will be useful, 15a35a2818801387f01a145ebe4a99a6a1fda31152Harry Ciao * but WITHOUT ANY WARRANTY; without even the implied warranty of 16a35a2818801387f01a145ebe4a99a6a1fda31152Harry Ciao * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. 17a35a2818801387f01a145ebe4a99a6a1fda31152Harry Ciao * See the GNU General Public License for more details. 18a35a2818801387f01a145ebe4a99a6a1fda31152Harry Ciao * 19a35a2818801387f01a145ebe4a99a6a1fda31152Harry Ciao * You should have received a copy of the GNU General Public License 20a35a2818801387f01a145ebe4a99a6a1fda31152Harry Ciao * along with this program; if not, write to the Free Software 21a35a2818801387f01a145ebe4a99a6a1fda31152Harry Ciao * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 22a35a2818801387f01a145ebe4a99a6a1fda31152Harry Ciao */ 23a35a2818801387f01a145ebe4a99a6a1fda31152Harry Ciao 24a35a2818801387f01a145ebe4a99a6a1fda31152Harry Ciao#ifndef _AMD8131_EDAC_H_ 25a35a2818801387f01a145ebe4a99a6a1fda31152Harry Ciao#define _AMD8131_EDAC_H_ 26a35a2818801387f01a145ebe4a99a6a1fda31152Harry Ciao 27a35a2818801387f01a145ebe4a99a6a1fda31152Harry Ciao#define DEVFN_PCIX_BRIDGE_NORTH_A 8 28a35a2818801387f01a145ebe4a99a6a1fda31152Harry Ciao#define DEVFN_PCIX_BRIDGE_NORTH_B 16 29a35a2818801387f01a145ebe4a99a6a1fda31152Harry Ciao#define DEVFN_PCIX_BRIDGE_SOUTH_A 24 30a35a2818801387f01a145ebe4a99a6a1fda31152Harry Ciao#define DEVFN_PCIX_BRIDGE_SOUTH_B 32 31a35a2818801387f01a145ebe4a99a6a1fda31152Harry Ciao 32a35a2818801387f01a145ebe4a99a6a1fda31152Harry Ciao/************************************************************ 33a35a2818801387f01a145ebe4a99a6a1fda31152Harry Ciao * PCI-X Bridge Status and Command Register, DevA:0x04 34a35a2818801387f01a145ebe4a99a6a1fda31152Harry Ciao ************************************************************/ 35a35a2818801387f01a145ebe4a99a6a1fda31152Harry Ciao#define REG_STS_CMD 0x04 36a35a2818801387f01a145ebe4a99a6a1fda31152Harry Ciaoenum sts_cmd_bits { 37a35a2818801387f01a145ebe4a99a6a1fda31152Harry Ciao STS_CMD_SSE = BIT(30), 38a35a2818801387f01a145ebe4a99a6a1fda31152Harry Ciao STS_CMD_SERREN = BIT(8) 39a35a2818801387f01a145ebe4a99a6a1fda31152Harry Ciao}; 40a35a2818801387f01a145ebe4a99a6a1fda31152Harry Ciao 41a35a2818801387f01a145ebe4a99a6a1fda31152Harry Ciao/************************************************************ 42a35a2818801387f01a145ebe4a99a6a1fda31152Harry Ciao * PCI-X Bridge Interrupt and Bridge Control Register, 43a35a2818801387f01a145ebe4a99a6a1fda31152Harry Ciao ************************************************************/ 44a35a2818801387f01a145ebe4a99a6a1fda31152Harry Ciao#define REG_INT_CTLR 0x3c 45a35a2818801387f01a145ebe4a99a6a1fda31152Harry Ciaoenum int_ctlr_bits { 46a35a2818801387f01a145ebe4a99a6a1fda31152Harry Ciao INT_CTLR_DTSE = BIT(27), 47a35a2818801387f01a145ebe4a99a6a1fda31152Harry Ciao INT_CTLR_DTS = BIT(26), 48a35a2818801387f01a145ebe4a99a6a1fda31152Harry Ciao INT_CTLR_SERR = BIT(17), 49a35a2818801387f01a145ebe4a99a6a1fda31152Harry Ciao INT_CTLR_PERR = BIT(16) 50a35a2818801387f01a145ebe4a99a6a1fda31152Harry Ciao}; 51a35a2818801387f01a145ebe4a99a6a1fda31152Harry Ciao 52a35a2818801387f01a145ebe4a99a6a1fda31152Harry Ciao/************************************************************ 53a35a2818801387f01a145ebe4a99a6a1fda31152Harry Ciao * PCI-X Bridge Memory Base-Limit Register, DevA:0x1C 54a35a2818801387f01a145ebe4a99a6a1fda31152Harry Ciao ************************************************************/ 55a35a2818801387f01a145ebe4a99a6a1fda31152Harry Ciao#define REG_MEM_LIM 0x1c 56a35a2818801387f01a145ebe4a99a6a1fda31152Harry Ciaoenum mem_limit_bits { 57a35a2818801387f01a145ebe4a99a6a1fda31152Harry Ciao MEM_LIMIT_DPE = BIT(31), 58a35a2818801387f01a145ebe4a99a6a1fda31152Harry Ciao MEM_LIMIT_RSE = BIT(30), 59a35a2818801387f01a145ebe4a99a6a1fda31152Harry Ciao MEM_LIMIT_RMA = BIT(29), 60a35a2818801387f01a145ebe4a99a6a1fda31152Harry Ciao MEM_LIMIT_RTA = BIT(28), 61a35a2818801387f01a145ebe4a99a6a1fda31152Harry Ciao MEM_LIMIT_STA = BIT(27), 62a35a2818801387f01a145ebe4a99a6a1fda31152Harry Ciao MEM_LIMIT_MDPE = BIT(24), 63a35a2818801387f01a145ebe4a99a6a1fda31152Harry Ciao MEM_LIMIT_MASK = MEM_LIMIT_DPE|MEM_LIMIT_RSE|MEM_LIMIT_RMA| 64a35a2818801387f01a145ebe4a99a6a1fda31152Harry Ciao MEM_LIMIT_RTA|MEM_LIMIT_STA|MEM_LIMIT_MDPE 65a35a2818801387f01a145ebe4a99a6a1fda31152Harry Ciao}; 66a35a2818801387f01a145ebe4a99a6a1fda31152Harry Ciao 67a35a2818801387f01a145ebe4a99a6a1fda31152Harry Ciao/************************************************************ 68a35a2818801387f01a145ebe4a99a6a1fda31152Harry Ciao * Link Configuration And Control Register, side A 69a35a2818801387f01a145ebe4a99a6a1fda31152Harry Ciao ************************************************************/ 70a35a2818801387f01a145ebe4a99a6a1fda31152Harry Ciao#define REG_LNK_CTRL_A 0xc4 71a35a2818801387f01a145ebe4a99a6a1fda31152Harry Ciao 72a35a2818801387f01a145ebe4a99a6a1fda31152Harry Ciao/************************************************************ 73a35a2818801387f01a145ebe4a99a6a1fda31152Harry Ciao * Link Configuration And Control Register, side B 74a35a2818801387f01a145ebe4a99a6a1fda31152Harry Ciao ************************************************************/ 75a35a2818801387f01a145ebe4a99a6a1fda31152Harry Ciao#define REG_LNK_CTRL_B 0xc8 76a35a2818801387f01a145ebe4a99a6a1fda31152Harry Ciao 77a35a2818801387f01a145ebe4a99a6a1fda31152Harry Ciaoenum lnk_ctrl_bits { 78a35a2818801387f01a145ebe4a99a6a1fda31152Harry Ciao LNK_CTRL_CRCERR_A = BIT(9), 79a35a2818801387f01a145ebe4a99a6a1fda31152Harry Ciao LNK_CTRL_CRCERR_B = BIT(8), 80a35a2818801387f01a145ebe4a99a6a1fda31152Harry Ciao LNK_CTRL_CRCFEN = BIT(1) 81a35a2818801387f01a145ebe4a99a6a1fda31152Harry Ciao}; 82a35a2818801387f01a145ebe4a99a6a1fda31152Harry Ciao 83a35a2818801387f01a145ebe4a99a6a1fda31152Harry Ciaoenum pcix_bridge_inst { 84a35a2818801387f01a145ebe4a99a6a1fda31152Harry Ciao NORTH_A = 0, 85a35a2818801387f01a145ebe4a99a6a1fda31152Harry Ciao NORTH_B = 1, 86a35a2818801387f01a145ebe4a99a6a1fda31152Harry Ciao SOUTH_A = 2, 87a35a2818801387f01a145ebe4a99a6a1fda31152Harry Ciao SOUTH_B = 3, 88a35a2818801387f01a145ebe4a99a6a1fda31152Harry Ciao NO_BRIDGE = 4 89a35a2818801387f01a145ebe4a99a6a1fda31152Harry Ciao}; 90a35a2818801387f01a145ebe4a99a6a1fda31152Harry Ciao 91a35a2818801387f01a145ebe4a99a6a1fda31152Harry Ciaostruct amd8131_dev_info { 92a35a2818801387f01a145ebe4a99a6a1fda31152Harry Ciao int devfn; 93a35a2818801387f01a145ebe4a99a6a1fda31152Harry Ciao enum pcix_bridge_inst inst; 94a35a2818801387f01a145ebe4a99a6a1fda31152Harry Ciao struct pci_dev *dev; 95a35a2818801387f01a145ebe4a99a6a1fda31152Harry Ciao int edac_idx; /* pci device index */ 96a35a2818801387f01a145ebe4a99a6a1fda31152Harry Ciao char *ctl_name; 97a35a2818801387f01a145ebe4a99a6a1fda31152Harry Ciao struct edac_pci_ctl_info *edac_dev; 98a35a2818801387f01a145ebe4a99a6a1fda31152Harry Ciao}; 99a35a2818801387f01a145ebe4a99a6a1fda31152Harry Ciao 100a35a2818801387f01a145ebe4a99a6a1fda31152Harry Ciao/* 101a35a2818801387f01a145ebe4a99a6a1fda31152Harry Ciao * AMD8131 chipset has two pairs of PCIX Bridge and related IOAPIC 102b595076a180a56d1bb170e6eceda6eb9d76f4cd3Uwe Kleine-König * Controller, and ATCA-6101 has two AMD8131 chipsets, so there are 103a35a2818801387f01a145ebe4a99a6a1fda31152Harry Ciao * four PCIX Bridges on ATCA-6101 altogether. 104a35a2818801387f01a145ebe4a99a6a1fda31152Harry Ciao * 105a35a2818801387f01a145ebe4a99a6a1fda31152Harry Ciao * These PCIX Bridges share the same PCI Device ID and are all of 106a35a2818801387f01a145ebe4a99a6a1fda31152Harry Ciao * Function Zero, they could be discrimated by their pci_dev->devfn. 107a35a2818801387f01a145ebe4a99a6a1fda31152Harry Ciao * They share the same set of init/check/exit methods, and their 108a35a2818801387f01a145ebe4a99a6a1fda31152Harry Ciao * private structures are collected in the devices[] array. 109a35a2818801387f01a145ebe4a99a6a1fda31152Harry Ciao */ 110a35a2818801387f01a145ebe4a99a6a1fda31152Harry Ciaostruct amd8131_info { 111a35a2818801387f01a145ebe4a99a6a1fda31152Harry Ciao u16 err_dev; /* PCI Device ID for AMD8131 APIC*/ 112a35a2818801387f01a145ebe4a99a6a1fda31152Harry Ciao struct amd8131_dev_info *devices; 113a35a2818801387f01a145ebe4a99a6a1fda31152Harry Ciao void (*init)(struct amd8131_dev_info *dev_info); 114a35a2818801387f01a145ebe4a99a6a1fda31152Harry Ciao void (*exit)(struct amd8131_dev_info *dev_info); 115a35a2818801387f01a145ebe4a99a6a1fda31152Harry Ciao void (*check)(struct edac_pci_ctl_info *edac_dev); 116a35a2818801387f01a145ebe4a99a6a1fda31152Harry Ciao}; 117a35a2818801387f01a145ebe4a99a6a1fda31152Harry Ciao 118a35a2818801387f01a145ebe4a99a6a1fda31152Harry Ciao#endif /* _AMD8131_EDAC_H_ */ 119a35a2818801387f01a145ebe4a99a6a1fda31152Harry Ciao 120