1806c35f5057a64d3061ee4e2b1023bf6f6d328e2Alan Cox/* 2806c35f5057a64d3061ee4e2b1023bf6f6d328e2Alan Cox * Intel e7xxx Memory Controller kernel module 3806c35f5057a64d3061ee4e2b1023bf6f6d328e2Alan Cox * (C) 2003 Linux Networx (http://lnxi.com) 4806c35f5057a64d3061ee4e2b1023bf6f6d328e2Alan Cox * This file may be distributed under the terms of the 5806c35f5057a64d3061ee4e2b1023bf6f6d328e2Alan Cox * GNU General Public License. 6806c35f5057a64d3061ee4e2b1023bf6f6d328e2Alan Cox * 7806c35f5057a64d3061ee4e2b1023bf6f6d328e2Alan Cox * See "enum e7xxx_chips" below for supported chipsets 8806c35f5057a64d3061ee4e2b1023bf6f6d328e2Alan Cox * 9806c35f5057a64d3061ee4e2b1023bf6f6d328e2Alan Cox * Written by Thayne Harbaugh 10806c35f5057a64d3061ee4e2b1023bf6f6d328e2Alan Cox * Based on work by Dan Hollis <goemon at anime dot net> and others. 11806c35f5057a64d3061ee4e2b1023bf6f6d328e2Alan Cox * http://www.anime.net/~goemon/linux-ecc/ 12806c35f5057a64d3061ee4e2b1023bf6f6d328e2Alan Cox * 1330ac44068121d7059bf025ed35b27caec408791eMauro Carvalho Chehab * Datasheet: 1430ac44068121d7059bf025ed35b27caec408791eMauro Carvalho Chehab * http://www.intel.com/content/www/us/en/chipsets/e7501-chipset-memory-controller-hub-datasheet.html 1530ac44068121d7059bf025ed35b27caec408791eMauro Carvalho Chehab * 16806c35f5057a64d3061ee4e2b1023bf6f6d328e2Alan Cox * Contributors: 17e7ecd8910293564d357dbaf18eb179e06fa35fd0Dave Peterson * Eric Biederman (Linux Networx) 18e7ecd8910293564d357dbaf18eb179e06fa35fd0Dave Peterson * Tom Zimmerman (Linux Networx) 19e7ecd8910293564d357dbaf18eb179e06fa35fd0Dave Peterson * Jim Garlick (Lawrence Livermore National Labs) 20806c35f5057a64d3061ee4e2b1023bf6f6d328e2Alan Cox * Dave Peterson (Lawrence Livermore National Labs) 21806c35f5057a64d3061ee4e2b1023bf6f6d328e2Alan Cox * That One Guy (Some other place) 22806c35f5057a64d3061ee4e2b1023bf6f6d328e2Alan Cox * Wang Zhenyu (intel.com) 23806c35f5057a64d3061ee4e2b1023bf6f6d328e2Alan Cox * 24806c35f5057a64d3061ee4e2b1023bf6f6d328e2Alan Cox * $Id: edac_e7xxx.c,v 1.5.2.9 2005/10/05 00:43:44 dsp_llnl Exp $ 25806c35f5057a64d3061ee4e2b1023bf6f6d328e2Alan Cox * 26806c35f5057a64d3061ee4e2b1023bf6f6d328e2Alan Cox */ 27806c35f5057a64d3061ee4e2b1023bf6f6d328e2Alan Cox 28806c35f5057a64d3061ee4e2b1023bf6f6d328e2Alan Cox#include <linux/module.h> 29806c35f5057a64d3061ee4e2b1023bf6f6d328e2Alan Cox#include <linux/init.h> 30806c35f5057a64d3061ee4e2b1023bf6f6d328e2Alan Cox#include <linux/pci.h> 31806c35f5057a64d3061ee4e2b1023bf6f6d328e2Alan Cox#include <linux/pci_ids.h> 32c0d121720220584bba2876b032e58a076b843fa1Dave Jiang#include <linux/edac.h> 3320bcb7a81dee21bfa3408f03f46b2891c9b5c84bDouglas Thompson#include "edac_core.h" 34806c35f5057a64d3061ee4e2b1023bf6f6d328e2Alan Cox 35152ba3942276c2a240703669ae4a3099e0a79451Michal Marek#define E7XXX_REVISION " Ver: 2.0.2" 36929a40ec324e947d4ad14cc1ced785c104c560e2Doug Thompson#define EDAC_MOD_STR "e7xxx_edac" 3737f04581abac20444e5b7106c1e1f28bec5b989cDoug Thompson 38537fba28928c01b7db1580627450691a4bb0b9b3Dave Peterson#define e7xxx_printk(level, fmt, arg...) \ 39e7ecd8910293564d357dbaf18eb179e06fa35fd0Dave Peterson edac_printk(level, "e7xxx", fmt, ##arg) 40537fba28928c01b7db1580627450691a4bb0b9b3Dave Peterson 41537fba28928c01b7db1580627450691a4bb0b9b3Dave Peterson#define e7xxx_mc_printk(mci, level, fmt, arg...) \ 42e7ecd8910293564d357dbaf18eb179e06fa35fd0Dave Peterson edac_mc_chipset_printk(mci, level, "e7xxx", fmt, ##arg) 43537fba28928c01b7db1580627450691a4bb0b9b3Dave Peterson 44806c35f5057a64d3061ee4e2b1023bf6f6d328e2Alan Cox#ifndef PCI_DEVICE_ID_INTEL_7205_0 45806c35f5057a64d3061ee4e2b1023bf6f6d328e2Alan Cox#define PCI_DEVICE_ID_INTEL_7205_0 0x255d 46806c35f5057a64d3061ee4e2b1023bf6f6d328e2Alan Cox#endif /* PCI_DEVICE_ID_INTEL_7205_0 */ 47806c35f5057a64d3061ee4e2b1023bf6f6d328e2Alan Cox 48806c35f5057a64d3061ee4e2b1023bf6f6d328e2Alan Cox#ifndef PCI_DEVICE_ID_INTEL_7205_1_ERR 49806c35f5057a64d3061ee4e2b1023bf6f6d328e2Alan Cox#define PCI_DEVICE_ID_INTEL_7205_1_ERR 0x2551 50806c35f5057a64d3061ee4e2b1023bf6f6d328e2Alan Cox#endif /* PCI_DEVICE_ID_INTEL_7205_1_ERR */ 51806c35f5057a64d3061ee4e2b1023bf6f6d328e2Alan Cox 52806c35f5057a64d3061ee4e2b1023bf6f6d328e2Alan Cox#ifndef PCI_DEVICE_ID_INTEL_7500_0 53806c35f5057a64d3061ee4e2b1023bf6f6d328e2Alan Cox#define PCI_DEVICE_ID_INTEL_7500_0 0x2540 54806c35f5057a64d3061ee4e2b1023bf6f6d328e2Alan Cox#endif /* PCI_DEVICE_ID_INTEL_7500_0 */ 55806c35f5057a64d3061ee4e2b1023bf6f6d328e2Alan Cox 56806c35f5057a64d3061ee4e2b1023bf6f6d328e2Alan Cox#ifndef PCI_DEVICE_ID_INTEL_7500_1_ERR 57806c35f5057a64d3061ee4e2b1023bf6f6d328e2Alan Cox#define PCI_DEVICE_ID_INTEL_7500_1_ERR 0x2541 58806c35f5057a64d3061ee4e2b1023bf6f6d328e2Alan Cox#endif /* PCI_DEVICE_ID_INTEL_7500_1_ERR */ 59806c35f5057a64d3061ee4e2b1023bf6f6d328e2Alan Cox 60806c35f5057a64d3061ee4e2b1023bf6f6d328e2Alan Cox#ifndef PCI_DEVICE_ID_INTEL_7501_0 61806c35f5057a64d3061ee4e2b1023bf6f6d328e2Alan Cox#define PCI_DEVICE_ID_INTEL_7501_0 0x254c 62806c35f5057a64d3061ee4e2b1023bf6f6d328e2Alan Cox#endif /* PCI_DEVICE_ID_INTEL_7501_0 */ 63806c35f5057a64d3061ee4e2b1023bf6f6d328e2Alan Cox 64806c35f5057a64d3061ee4e2b1023bf6f6d328e2Alan Cox#ifndef PCI_DEVICE_ID_INTEL_7501_1_ERR 65806c35f5057a64d3061ee4e2b1023bf6f6d328e2Alan Cox#define PCI_DEVICE_ID_INTEL_7501_1_ERR 0x2541 66806c35f5057a64d3061ee4e2b1023bf6f6d328e2Alan Cox#endif /* PCI_DEVICE_ID_INTEL_7501_1_ERR */ 67806c35f5057a64d3061ee4e2b1023bf6f6d328e2Alan Cox 68806c35f5057a64d3061ee4e2b1023bf6f6d328e2Alan Cox#ifndef PCI_DEVICE_ID_INTEL_7505_0 69806c35f5057a64d3061ee4e2b1023bf6f6d328e2Alan Cox#define PCI_DEVICE_ID_INTEL_7505_0 0x2550 70806c35f5057a64d3061ee4e2b1023bf6f6d328e2Alan Cox#endif /* PCI_DEVICE_ID_INTEL_7505_0 */ 71806c35f5057a64d3061ee4e2b1023bf6f6d328e2Alan Cox 72806c35f5057a64d3061ee4e2b1023bf6f6d328e2Alan Cox#ifndef PCI_DEVICE_ID_INTEL_7505_1_ERR 73806c35f5057a64d3061ee4e2b1023bf6f6d328e2Alan Cox#define PCI_DEVICE_ID_INTEL_7505_1_ERR 0x2551 74806c35f5057a64d3061ee4e2b1023bf6f6d328e2Alan Cox#endif /* PCI_DEVICE_ID_INTEL_7505_1_ERR */ 75806c35f5057a64d3061ee4e2b1023bf6f6d328e2Alan Cox 76806c35f5057a64d3061ee4e2b1023bf6f6d328e2Alan Cox#define E7XXX_NR_CSROWS 8 /* number of csrows */ 7730ac44068121d7059bf025ed35b27caec408791eMauro Carvalho Chehab#define E7XXX_NR_DIMMS 8 /* 2 channels, 4 dimms/channel */ 78806c35f5057a64d3061ee4e2b1023bf6f6d328e2Alan Cox 79806c35f5057a64d3061ee4e2b1023bf6f6d328e2Alan Cox/* E7XXX register addresses - device 0 function 0 */ 80806c35f5057a64d3061ee4e2b1023bf6f6d328e2Alan Cox#define E7XXX_DRB 0x60 /* DRAM row boundary register (8b) */ 81806c35f5057a64d3061ee4e2b1023bf6f6d328e2Alan Cox#define E7XXX_DRA 0x70 /* DRAM row attribute register (8b) */ 82806c35f5057a64d3061ee4e2b1023bf6f6d328e2Alan Cox /* 83806c35f5057a64d3061ee4e2b1023bf6f6d328e2Alan Cox * 31 Device width row 7 0=x8 1=x4 84806c35f5057a64d3061ee4e2b1023bf6f6d328e2Alan Cox * 27 Device width row 6 85806c35f5057a64d3061ee4e2b1023bf6f6d328e2Alan Cox * 23 Device width row 5 86806c35f5057a64d3061ee4e2b1023bf6f6d328e2Alan Cox * 19 Device width row 4 87806c35f5057a64d3061ee4e2b1023bf6f6d328e2Alan Cox * 15 Device width row 3 88806c35f5057a64d3061ee4e2b1023bf6f6d328e2Alan Cox * 11 Device width row 2 89806c35f5057a64d3061ee4e2b1023bf6f6d328e2Alan Cox * 7 Device width row 1 90806c35f5057a64d3061ee4e2b1023bf6f6d328e2Alan Cox * 3 Device width row 0 91806c35f5057a64d3061ee4e2b1023bf6f6d328e2Alan Cox */ 92806c35f5057a64d3061ee4e2b1023bf6f6d328e2Alan Cox#define E7XXX_DRC 0x7C /* DRAM controller mode reg (32b) */ 93806c35f5057a64d3061ee4e2b1023bf6f6d328e2Alan Cox /* 94806c35f5057a64d3061ee4e2b1023bf6f6d328e2Alan Cox * 22 Number channels 0=1,1=2 95806c35f5057a64d3061ee4e2b1023bf6f6d328e2Alan Cox * 19:18 DRB Granularity 32/64MB 96806c35f5057a64d3061ee4e2b1023bf6f6d328e2Alan Cox */ 97806c35f5057a64d3061ee4e2b1023bf6f6d328e2Alan Cox#define E7XXX_TOLM 0xC4 /* DRAM top of low memory reg (16b) */ 98806c35f5057a64d3061ee4e2b1023bf6f6d328e2Alan Cox#define E7XXX_REMAPBASE 0xC6 /* DRAM remap base address reg (16b) */ 99806c35f5057a64d3061ee4e2b1023bf6f6d328e2Alan Cox#define E7XXX_REMAPLIMIT 0xC8 /* DRAM remap limit address reg (16b) */ 100806c35f5057a64d3061ee4e2b1023bf6f6d328e2Alan Cox 101806c35f5057a64d3061ee4e2b1023bf6f6d328e2Alan Cox/* E7XXX register addresses - device 0 function 1 */ 102806c35f5057a64d3061ee4e2b1023bf6f6d328e2Alan Cox#define E7XXX_DRAM_FERR 0x80 /* DRAM first error register (8b) */ 103806c35f5057a64d3061ee4e2b1023bf6f6d328e2Alan Cox#define E7XXX_DRAM_NERR 0x82 /* DRAM next error register (8b) */ 104806c35f5057a64d3061ee4e2b1023bf6f6d328e2Alan Cox#define E7XXX_DRAM_CELOG_ADD 0xA0 /* DRAM first correctable memory */ 105806c35f5057a64d3061ee4e2b1023bf6f6d328e2Alan Cox /* error address register (32b) */ 106806c35f5057a64d3061ee4e2b1023bf6f6d328e2Alan Cox /* 107806c35f5057a64d3061ee4e2b1023bf6f6d328e2Alan Cox * 31:28 Reserved 108806c35f5057a64d3061ee4e2b1023bf6f6d328e2Alan Cox * 27:6 CE address (4k block 33:12) 109806c35f5057a64d3061ee4e2b1023bf6f6d328e2Alan Cox * 5:0 Reserved 110806c35f5057a64d3061ee4e2b1023bf6f6d328e2Alan Cox */ 111806c35f5057a64d3061ee4e2b1023bf6f6d328e2Alan Cox#define E7XXX_DRAM_UELOG_ADD 0xB0 /* DRAM first uncorrectable memory */ 112806c35f5057a64d3061ee4e2b1023bf6f6d328e2Alan Cox /* error address register (32b) */ 113806c35f5057a64d3061ee4e2b1023bf6f6d328e2Alan Cox /* 114806c35f5057a64d3061ee4e2b1023bf6f6d328e2Alan Cox * 31:28 Reserved 115806c35f5057a64d3061ee4e2b1023bf6f6d328e2Alan Cox * 27:6 CE address (4k block 33:12) 116806c35f5057a64d3061ee4e2b1023bf6f6d328e2Alan Cox * 5:0 Reserved 117806c35f5057a64d3061ee4e2b1023bf6f6d328e2Alan Cox */ 118806c35f5057a64d3061ee4e2b1023bf6f6d328e2Alan Cox#define E7XXX_DRAM_CELOG_SYNDROME 0xD0 /* DRAM first correctable memory */ 119806c35f5057a64d3061ee4e2b1023bf6f6d328e2Alan Cox /* error syndrome register (16b) */ 120806c35f5057a64d3061ee4e2b1023bf6f6d328e2Alan Cox 121806c35f5057a64d3061ee4e2b1023bf6f6d328e2Alan Coxenum e7xxx_chips { 122806c35f5057a64d3061ee4e2b1023bf6f6d328e2Alan Cox E7500 = 0, 123806c35f5057a64d3061ee4e2b1023bf6f6d328e2Alan Cox E7501, 124806c35f5057a64d3061ee4e2b1023bf6f6d328e2Alan Cox E7505, 125806c35f5057a64d3061ee4e2b1023bf6f6d328e2Alan Cox E7205, 126806c35f5057a64d3061ee4e2b1023bf6f6d328e2Alan Cox}; 127806c35f5057a64d3061ee4e2b1023bf6f6d328e2Alan Cox 128806c35f5057a64d3061ee4e2b1023bf6f6d328e2Alan Coxstruct e7xxx_pvt { 129806c35f5057a64d3061ee4e2b1023bf6f6d328e2Alan Cox struct pci_dev *bridge_ck; 130806c35f5057a64d3061ee4e2b1023bf6f6d328e2Alan Cox u32 tolm; 131806c35f5057a64d3061ee4e2b1023bf6f6d328e2Alan Cox u32 remapbase; 132806c35f5057a64d3061ee4e2b1023bf6f6d328e2Alan Cox u32 remaplimit; 133806c35f5057a64d3061ee4e2b1023bf6f6d328e2Alan Cox const struct e7xxx_dev_info *dev_info; 134806c35f5057a64d3061ee4e2b1023bf6f6d328e2Alan Cox}; 135806c35f5057a64d3061ee4e2b1023bf6f6d328e2Alan Cox 136806c35f5057a64d3061ee4e2b1023bf6f6d328e2Alan Coxstruct e7xxx_dev_info { 137806c35f5057a64d3061ee4e2b1023bf6f6d328e2Alan Cox u16 err_dev; 138806c35f5057a64d3061ee4e2b1023bf6f6d328e2Alan Cox const char *ctl_name; 139806c35f5057a64d3061ee4e2b1023bf6f6d328e2Alan Cox}; 140806c35f5057a64d3061ee4e2b1023bf6f6d328e2Alan Cox 141806c35f5057a64d3061ee4e2b1023bf6f6d328e2Alan Coxstruct e7xxx_error_info { 142806c35f5057a64d3061ee4e2b1023bf6f6d328e2Alan Cox u8 dram_ferr; 143806c35f5057a64d3061ee4e2b1023bf6f6d328e2Alan Cox u8 dram_nerr; 144806c35f5057a64d3061ee4e2b1023bf6f6d328e2Alan Cox u32 dram_celog_add; 145806c35f5057a64d3061ee4e2b1023bf6f6d328e2Alan Cox u16 dram_celog_syndrome; 146806c35f5057a64d3061ee4e2b1023bf6f6d328e2Alan Cox u32 dram_uelog_add; 147806c35f5057a64d3061ee4e2b1023bf6f6d328e2Alan Cox}; 148806c35f5057a64d3061ee4e2b1023bf6f6d328e2Alan Cox 149456a2f9552e7849475f4aea1a9aa4c0e54b3dddaDave Jiangstatic struct edac_pci_ctl_info *e7xxx_pci; 150456a2f9552e7849475f4aea1a9aa4c0e54b3dddaDave Jiang 151806c35f5057a64d3061ee4e2b1023bf6f6d328e2Alan Coxstatic const struct e7xxx_dev_info e7xxx_devs[] = { 152806c35f5057a64d3061ee4e2b1023bf6f6d328e2Alan Cox [E7500] = { 153052dfb45ccb5ea354a426b52556bcfee75b9d2f5Douglas Thompson .err_dev = PCI_DEVICE_ID_INTEL_7500_1_ERR, 154052dfb45ccb5ea354a426b52556bcfee75b9d2f5Douglas Thompson .ctl_name = "E7500"}, 155806c35f5057a64d3061ee4e2b1023bf6f6d328e2Alan Cox [E7501] = { 156052dfb45ccb5ea354a426b52556bcfee75b9d2f5Douglas Thompson .err_dev = PCI_DEVICE_ID_INTEL_7501_1_ERR, 157052dfb45ccb5ea354a426b52556bcfee75b9d2f5Douglas Thompson .ctl_name = "E7501"}, 158806c35f5057a64d3061ee4e2b1023bf6f6d328e2Alan Cox [E7505] = { 159052dfb45ccb5ea354a426b52556bcfee75b9d2f5Douglas Thompson .err_dev = PCI_DEVICE_ID_INTEL_7505_1_ERR, 160052dfb45ccb5ea354a426b52556bcfee75b9d2f5Douglas Thompson .ctl_name = "E7505"}, 161806c35f5057a64d3061ee4e2b1023bf6f6d328e2Alan Cox [E7205] = { 162052dfb45ccb5ea354a426b52556bcfee75b9d2f5Douglas Thompson .err_dev = PCI_DEVICE_ID_INTEL_7205_1_ERR, 163052dfb45ccb5ea354a426b52556bcfee75b9d2f5Douglas Thompson .ctl_name = "E7205"}, 164806c35f5057a64d3061ee4e2b1023bf6f6d328e2Alan Cox}; 165806c35f5057a64d3061ee4e2b1023bf6f6d328e2Alan Cox 166806c35f5057a64d3061ee4e2b1023bf6f6d328e2Alan Cox/* FIXME - is this valid for both SECDED and S4ECD4ED? */ 167806c35f5057a64d3061ee4e2b1023bf6f6d328e2Alan Coxstatic inline int e7xxx_find_channel(u16 syndrome) 168806c35f5057a64d3061ee4e2b1023bf6f6d328e2Alan Cox{ 169956b9ba156dbfdb9cede2b2927ddf8be2233b3a7Joe Perches edac_dbg(3, "\n"); 170806c35f5057a64d3061ee4e2b1023bf6f6d328e2Alan Cox 171806c35f5057a64d3061ee4e2b1023bf6f6d328e2Alan Cox if ((syndrome & 0xff00) == 0) 172806c35f5057a64d3061ee4e2b1023bf6f6d328e2Alan Cox return 0; 173e7ecd8910293564d357dbaf18eb179e06fa35fd0Dave Peterson 174806c35f5057a64d3061ee4e2b1023bf6f6d328e2Alan Cox if ((syndrome & 0x00ff) == 0) 175806c35f5057a64d3061ee4e2b1023bf6f6d328e2Alan Cox return 1; 176e7ecd8910293564d357dbaf18eb179e06fa35fd0Dave Peterson 177806c35f5057a64d3061ee4e2b1023bf6f6d328e2Alan Cox if ((syndrome & 0xf000) == 0 || (syndrome & 0x0f00) == 0) 178806c35f5057a64d3061ee4e2b1023bf6f6d328e2Alan Cox return 0; 179e7ecd8910293564d357dbaf18eb179e06fa35fd0Dave Peterson 180806c35f5057a64d3061ee4e2b1023bf6f6d328e2Alan Cox return 1; 181806c35f5057a64d3061ee4e2b1023bf6f6d328e2Alan Cox} 182806c35f5057a64d3061ee4e2b1023bf6f6d328e2Alan Cox 183e7ecd8910293564d357dbaf18eb179e06fa35fd0Dave Petersonstatic unsigned long ctl_page_to_phys(struct mem_ctl_info *mci, 184052dfb45ccb5ea354a426b52556bcfee75b9d2f5Douglas Thompson unsigned long page) 185806c35f5057a64d3061ee4e2b1023bf6f6d328e2Alan Cox{ 186806c35f5057a64d3061ee4e2b1023bf6f6d328e2Alan Cox u32 remap; 187849a4c375a8e06cd000399dceb25888d356d021fDave Jiang struct e7xxx_pvt *pvt = (struct e7xxx_pvt *)mci->pvt_info; 188806c35f5057a64d3061ee4e2b1023bf6f6d328e2Alan Cox 189956b9ba156dbfdb9cede2b2927ddf8be2233b3a7Joe Perches edac_dbg(3, "\n"); 190806c35f5057a64d3061ee4e2b1023bf6f6d328e2Alan Cox 191806c35f5057a64d3061ee4e2b1023bf6f6d328e2Alan Cox if ((page < pvt->tolm) || 192052dfb45ccb5ea354a426b52556bcfee75b9d2f5Douglas Thompson ((page >= 0x100000) && (page < pvt->remapbase))) 193806c35f5057a64d3061ee4e2b1023bf6f6d328e2Alan Cox return page; 194e7ecd8910293564d357dbaf18eb179e06fa35fd0Dave Peterson 195806c35f5057a64d3061ee4e2b1023bf6f6d328e2Alan Cox remap = (page - pvt->tolm) + pvt->remapbase; 196e7ecd8910293564d357dbaf18eb179e06fa35fd0Dave Peterson 197806c35f5057a64d3061ee4e2b1023bf6f6d328e2Alan Cox if (remap < pvt->remaplimit) 198806c35f5057a64d3061ee4e2b1023bf6f6d328e2Alan Cox return remap; 199e7ecd8910293564d357dbaf18eb179e06fa35fd0Dave Peterson 200537fba28928c01b7db1580627450691a4bb0b9b3Dave Peterson e7xxx_printk(KERN_ERR, "Invalid page %lx - out of range\n", page); 201806c35f5057a64d3061ee4e2b1023bf6f6d328e2Alan Cox return pvt->tolm - 1; 202806c35f5057a64d3061ee4e2b1023bf6f6d328e2Alan Cox} 203806c35f5057a64d3061ee4e2b1023bf6f6d328e2Alan Cox 204849a4c375a8e06cd000399dceb25888d356d021fDave Jiangstatic void process_ce(struct mem_ctl_info *mci, struct e7xxx_error_info *info) 205806c35f5057a64d3061ee4e2b1023bf6f6d328e2Alan Cox{ 206806c35f5057a64d3061ee4e2b1023bf6f6d328e2Alan Cox u32 error_1b, page; 207806c35f5057a64d3061ee4e2b1023bf6f6d328e2Alan Cox u16 syndrome; 208806c35f5057a64d3061ee4e2b1023bf6f6d328e2Alan Cox int row; 209806c35f5057a64d3061ee4e2b1023bf6f6d328e2Alan Cox int channel; 210806c35f5057a64d3061ee4e2b1023bf6f6d328e2Alan Cox 211956b9ba156dbfdb9cede2b2927ddf8be2233b3a7Joe Perches edac_dbg(3, "\n"); 212806c35f5057a64d3061ee4e2b1023bf6f6d328e2Alan Cox /* read the error address */ 213806c35f5057a64d3061ee4e2b1023bf6f6d328e2Alan Cox error_1b = info->dram_celog_add; 214806c35f5057a64d3061ee4e2b1023bf6f6d328e2Alan Cox /* FIXME - should use PAGE_SHIFT */ 215849a4c375a8e06cd000399dceb25888d356d021fDave Jiang page = error_1b >> 6; /* convert the address to 4k page */ 216806c35f5057a64d3061ee4e2b1023bf6f6d328e2Alan Cox /* read the syndrome */ 217806c35f5057a64d3061ee4e2b1023bf6f6d328e2Alan Cox syndrome = info->dram_celog_syndrome; 218806c35f5057a64d3061ee4e2b1023bf6f6d328e2Alan Cox /* FIXME - check for -1 */ 219806c35f5057a64d3061ee4e2b1023bf6f6d328e2Alan Cox row = edac_mc_find_csrow_by_page(mci, page); 220806c35f5057a64d3061ee4e2b1023bf6f6d328e2Alan Cox /* convert syndrome to channel */ 221806c35f5057a64d3061ee4e2b1023bf6f6d328e2Alan Cox channel = e7xxx_find_channel(syndrome); 2229eb07a7fb8a90ee39fa9d5489afc0330cfcfbea7Mauro Carvalho Chehab edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, mci, 1, page, 0, syndrome, 22303f7eae80f4b913929be84e0c883ee98196fd6ffMauro Carvalho Chehab row, channel, -1, "e7xxx CE", ""); 224806c35f5057a64d3061ee4e2b1023bf6f6d328e2Alan Cox} 225806c35f5057a64d3061ee4e2b1023bf6f6d328e2Alan Cox 226806c35f5057a64d3061ee4e2b1023bf6f6d328e2Alan Coxstatic void process_ce_no_info(struct mem_ctl_info *mci) 227806c35f5057a64d3061ee4e2b1023bf6f6d328e2Alan Cox{ 228956b9ba156dbfdb9cede2b2927ddf8be2233b3a7Joe Perches edac_dbg(3, "\n"); 2298030122a9ccf939186f8db96c318dbb99b5463f6Jason Baron edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, mci, 1, 0, 0, 0, -1, -1, -1, 23003f7eae80f4b913929be84e0c883ee98196fd6ffMauro Carvalho Chehab "e7xxx CE log register overflow", ""); 231806c35f5057a64d3061ee4e2b1023bf6f6d328e2Alan Cox} 232806c35f5057a64d3061ee4e2b1023bf6f6d328e2Alan Cox 233849a4c375a8e06cd000399dceb25888d356d021fDave Jiangstatic void process_ue(struct mem_ctl_info *mci, struct e7xxx_error_info *info) 234806c35f5057a64d3061ee4e2b1023bf6f6d328e2Alan Cox{ 235806c35f5057a64d3061ee4e2b1023bf6f6d328e2Alan Cox u32 error_2b, block_page; 236806c35f5057a64d3061ee4e2b1023bf6f6d328e2Alan Cox int row; 237806c35f5057a64d3061ee4e2b1023bf6f6d328e2Alan Cox 238956b9ba156dbfdb9cede2b2927ddf8be2233b3a7Joe Perches edac_dbg(3, "\n"); 239806c35f5057a64d3061ee4e2b1023bf6f6d328e2Alan Cox /* read the error address */ 240806c35f5057a64d3061ee4e2b1023bf6f6d328e2Alan Cox error_2b = info->dram_uelog_add; 241806c35f5057a64d3061ee4e2b1023bf6f6d328e2Alan Cox /* FIXME - should use PAGE_SHIFT */ 242849a4c375a8e06cd000399dceb25888d356d021fDave Jiang block_page = error_2b >> 6; /* convert to 4k address */ 243806c35f5057a64d3061ee4e2b1023bf6f6d328e2Alan Cox row = edac_mc_find_csrow_by_page(mci, block_page); 24430ac44068121d7059bf025ed35b27caec408791eMauro Carvalho Chehab 2459eb07a7fb8a90ee39fa9d5489afc0330cfcfbea7Mauro Carvalho Chehab edac_mc_handle_error(HW_EVENT_ERR_UNCORRECTED, mci, 1, block_page, 0, 0, 24603f7eae80f4b913929be84e0c883ee98196fd6ffMauro Carvalho Chehab row, -1, -1, "e7xxx UE", ""); 247806c35f5057a64d3061ee4e2b1023bf6f6d328e2Alan Cox} 248806c35f5057a64d3061ee4e2b1023bf6f6d328e2Alan Cox 249806c35f5057a64d3061ee4e2b1023bf6f6d328e2Alan Coxstatic void process_ue_no_info(struct mem_ctl_info *mci) 250806c35f5057a64d3061ee4e2b1023bf6f6d328e2Alan Cox{ 251956b9ba156dbfdb9cede2b2927ddf8be2233b3a7Joe Perches edac_dbg(3, "\n"); 25230ac44068121d7059bf025ed35b27caec408791eMauro Carvalho Chehab 2539eb07a7fb8a90ee39fa9d5489afc0330cfcfbea7Mauro Carvalho Chehab edac_mc_handle_error(HW_EVENT_ERR_UNCORRECTED, mci, 1, 0, 0, 0, -1, -1, -1, 25403f7eae80f4b913929be84e0c883ee98196fd6ffMauro Carvalho Chehab "e7xxx UE log register overflow", ""); 255806c35f5057a64d3061ee4e2b1023bf6f6d328e2Alan Cox} 256806c35f5057a64d3061ee4e2b1023bf6f6d328e2Alan Cox 257849a4c375a8e06cd000399dceb25888d356d021fDave Jiangstatic void e7xxx_get_error_info(struct mem_ctl_info *mci, 258849a4c375a8e06cd000399dceb25888d356d021fDave Jiang struct e7xxx_error_info *info) 259806c35f5057a64d3061ee4e2b1023bf6f6d328e2Alan Cox{ 260806c35f5057a64d3061ee4e2b1023bf6f6d328e2Alan Cox struct e7xxx_pvt *pvt; 261806c35f5057a64d3061ee4e2b1023bf6f6d328e2Alan Cox 262849a4c375a8e06cd000399dceb25888d356d021fDave Jiang pvt = (struct e7xxx_pvt *)mci->pvt_info; 263849a4c375a8e06cd000399dceb25888d356d021fDave Jiang pci_read_config_byte(pvt->bridge_ck, E7XXX_DRAM_FERR, &info->dram_ferr); 264849a4c375a8e06cd000399dceb25888d356d021fDave Jiang pci_read_config_byte(pvt->bridge_ck, E7XXX_DRAM_NERR, &info->dram_nerr); 265806c35f5057a64d3061ee4e2b1023bf6f6d328e2Alan Cox 266806c35f5057a64d3061ee4e2b1023bf6f6d328e2Alan Cox if ((info->dram_ferr & 1) || (info->dram_nerr & 1)) { 267806c35f5057a64d3061ee4e2b1023bf6f6d328e2Alan Cox pci_read_config_dword(pvt->bridge_ck, E7XXX_DRAM_CELOG_ADD, 268052dfb45ccb5ea354a426b52556bcfee75b9d2f5Douglas Thompson &info->dram_celog_add); 269806c35f5057a64d3061ee4e2b1023bf6f6d328e2Alan Cox pci_read_config_word(pvt->bridge_ck, 270052dfb45ccb5ea354a426b52556bcfee75b9d2f5Douglas Thompson E7XXX_DRAM_CELOG_SYNDROME, 271052dfb45ccb5ea354a426b52556bcfee75b9d2f5Douglas Thompson &info->dram_celog_syndrome); 272806c35f5057a64d3061ee4e2b1023bf6f6d328e2Alan Cox } 273806c35f5057a64d3061ee4e2b1023bf6f6d328e2Alan Cox 274806c35f5057a64d3061ee4e2b1023bf6f6d328e2Alan Cox if ((info->dram_ferr & 2) || (info->dram_nerr & 2)) 275806c35f5057a64d3061ee4e2b1023bf6f6d328e2Alan Cox pci_read_config_dword(pvt->bridge_ck, E7XXX_DRAM_UELOG_ADD, 276052dfb45ccb5ea354a426b52556bcfee75b9d2f5Douglas Thompson &info->dram_uelog_add); 277806c35f5057a64d3061ee4e2b1023bf6f6d328e2Alan Cox 278806c35f5057a64d3061ee4e2b1023bf6f6d328e2Alan Cox if (info->dram_ferr & 3) 279e7ecd8910293564d357dbaf18eb179e06fa35fd0Dave Peterson pci_write_bits8(pvt->bridge_ck, E7XXX_DRAM_FERR, 0x03, 0x03); 280806c35f5057a64d3061ee4e2b1023bf6f6d328e2Alan Cox 281806c35f5057a64d3061ee4e2b1023bf6f6d328e2Alan Cox if (info->dram_nerr & 3) 282e7ecd8910293564d357dbaf18eb179e06fa35fd0Dave Peterson pci_write_bits8(pvt->bridge_ck, E7XXX_DRAM_NERR, 0x03, 0x03); 283806c35f5057a64d3061ee4e2b1023bf6f6d328e2Alan Cox} 284806c35f5057a64d3061ee4e2b1023bf6f6d328e2Alan Cox 285849a4c375a8e06cd000399dceb25888d356d021fDave Jiangstatic int e7xxx_process_error_info(struct mem_ctl_info *mci, 286052dfb45ccb5ea354a426b52556bcfee75b9d2f5Douglas Thompson struct e7xxx_error_info *info, 287052dfb45ccb5ea354a426b52556bcfee75b9d2f5Douglas Thompson int handle_errors) 288806c35f5057a64d3061ee4e2b1023bf6f6d328e2Alan Cox{ 289806c35f5057a64d3061ee4e2b1023bf6f6d328e2Alan Cox int error_found; 290806c35f5057a64d3061ee4e2b1023bf6f6d328e2Alan Cox 291806c35f5057a64d3061ee4e2b1023bf6f6d328e2Alan Cox error_found = 0; 292806c35f5057a64d3061ee4e2b1023bf6f6d328e2Alan Cox 293806c35f5057a64d3061ee4e2b1023bf6f6d328e2Alan Cox /* decode and report errors */ 294806c35f5057a64d3061ee4e2b1023bf6f6d328e2Alan Cox if (info->dram_ferr & 1) { /* check first error correctable */ 295806c35f5057a64d3061ee4e2b1023bf6f6d328e2Alan Cox error_found = 1; 296806c35f5057a64d3061ee4e2b1023bf6f6d328e2Alan Cox 297806c35f5057a64d3061ee4e2b1023bf6f6d328e2Alan Cox if (handle_errors) 298806c35f5057a64d3061ee4e2b1023bf6f6d328e2Alan Cox process_ce(mci, info); 299806c35f5057a64d3061ee4e2b1023bf6f6d328e2Alan Cox } 300806c35f5057a64d3061ee4e2b1023bf6f6d328e2Alan Cox 301806c35f5057a64d3061ee4e2b1023bf6f6d328e2Alan Cox if (info->dram_ferr & 2) { /* check first error uncorrectable */ 302806c35f5057a64d3061ee4e2b1023bf6f6d328e2Alan Cox error_found = 1; 303806c35f5057a64d3061ee4e2b1023bf6f6d328e2Alan Cox 304806c35f5057a64d3061ee4e2b1023bf6f6d328e2Alan Cox if (handle_errors) 305806c35f5057a64d3061ee4e2b1023bf6f6d328e2Alan Cox process_ue(mci, info); 306806c35f5057a64d3061ee4e2b1023bf6f6d328e2Alan Cox } 307806c35f5057a64d3061ee4e2b1023bf6f6d328e2Alan Cox 308806c35f5057a64d3061ee4e2b1023bf6f6d328e2Alan Cox if (info->dram_nerr & 1) { /* check next error correctable */ 309806c35f5057a64d3061ee4e2b1023bf6f6d328e2Alan Cox error_found = 1; 310806c35f5057a64d3061ee4e2b1023bf6f6d328e2Alan Cox 311806c35f5057a64d3061ee4e2b1023bf6f6d328e2Alan Cox if (handle_errors) { 312806c35f5057a64d3061ee4e2b1023bf6f6d328e2Alan Cox if (info->dram_ferr & 1) 313806c35f5057a64d3061ee4e2b1023bf6f6d328e2Alan Cox process_ce_no_info(mci); 314806c35f5057a64d3061ee4e2b1023bf6f6d328e2Alan Cox else 315806c35f5057a64d3061ee4e2b1023bf6f6d328e2Alan Cox process_ce(mci, info); 316806c35f5057a64d3061ee4e2b1023bf6f6d328e2Alan Cox } 317806c35f5057a64d3061ee4e2b1023bf6f6d328e2Alan Cox } 318806c35f5057a64d3061ee4e2b1023bf6f6d328e2Alan Cox 319806c35f5057a64d3061ee4e2b1023bf6f6d328e2Alan Cox if (info->dram_nerr & 2) { /* check next error uncorrectable */ 320806c35f5057a64d3061ee4e2b1023bf6f6d328e2Alan Cox error_found = 1; 321806c35f5057a64d3061ee4e2b1023bf6f6d328e2Alan Cox 322806c35f5057a64d3061ee4e2b1023bf6f6d328e2Alan Cox if (handle_errors) { 323806c35f5057a64d3061ee4e2b1023bf6f6d328e2Alan Cox if (info->dram_ferr & 2) 324806c35f5057a64d3061ee4e2b1023bf6f6d328e2Alan Cox process_ue_no_info(mci); 325806c35f5057a64d3061ee4e2b1023bf6f6d328e2Alan Cox else 326806c35f5057a64d3061ee4e2b1023bf6f6d328e2Alan Cox process_ue(mci, info); 327806c35f5057a64d3061ee4e2b1023bf6f6d328e2Alan Cox } 328806c35f5057a64d3061ee4e2b1023bf6f6d328e2Alan Cox } 329806c35f5057a64d3061ee4e2b1023bf6f6d328e2Alan Cox 330806c35f5057a64d3061ee4e2b1023bf6f6d328e2Alan Cox return error_found; 331806c35f5057a64d3061ee4e2b1023bf6f6d328e2Alan Cox} 332806c35f5057a64d3061ee4e2b1023bf6f6d328e2Alan Cox 333806c35f5057a64d3061ee4e2b1023bf6f6d328e2Alan Coxstatic void e7xxx_check(struct mem_ctl_info *mci) 334806c35f5057a64d3061ee4e2b1023bf6f6d328e2Alan Cox{ 335806c35f5057a64d3061ee4e2b1023bf6f6d328e2Alan Cox struct e7xxx_error_info info; 336806c35f5057a64d3061ee4e2b1023bf6f6d328e2Alan Cox 337956b9ba156dbfdb9cede2b2927ddf8be2233b3a7Joe Perches edac_dbg(3, "\n"); 338806c35f5057a64d3061ee4e2b1023bf6f6d328e2Alan Cox e7xxx_get_error_info(mci, &info); 339806c35f5057a64d3061ee4e2b1023bf6f6d328e2Alan Cox e7xxx_process_error_info(mci, &info, 1); 340806c35f5057a64d3061ee4e2b1023bf6f6d328e2Alan Cox} 341806c35f5057a64d3061ee4e2b1023bf6f6d328e2Alan Cox 3421318952514d5651c453d89989595a9df3b37267bDoug Thompson/* Return 1 if dual channel mode is active. Else return 0. */ 3431318952514d5651c453d89989595a9df3b37267bDoug Thompsonstatic inline int dual_channel_active(u32 drc, int dev_idx) 344806c35f5057a64d3061ee4e2b1023bf6f6d328e2Alan Cox{ 3451318952514d5651c453d89989595a9df3b37267bDoug Thompson return (dev_idx == E7501) ? ((drc >> 22) & 0x1) : 1; 3461318952514d5651c453d89989595a9df3b37267bDoug Thompson} 347806c35f5057a64d3061ee4e2b1023bf6f6d328e2Alan Cox 3481318952514d5651c453d89989595a9df3b37267bDoug Thompson/* Return DRB granularity (0=32mb, 1=64mb). */ 3491318952514d5651c453d89989595a9df3b37267bDoug Thompsonstatic inline int drb_granularity(u32 drc, int dev_idx) 3501318952514d5651c453d89989595a9df3b37267bDoug Thompson{ 351806c35f5057a64d3061ee4e2b1023bf6f6d328e2Alan Cox /* only e7501 can be single channel */ 3521318952514d5651c453d89989595a9df3b37267bDoug Thompson return (dev_idx == E7501) ? ((drc >> 18) & 0x3) : 1; 3531318952514d5651c453d89989595a9df3b37267bDoug Thompson} 354e7ecd8910293564d357dbaf18eb179e06fa35fd0Dave Peterson 3551318952514d5651c453d89989595a9df3b37267bDoug Thompsonstatic void e7xxx_init_csrows(struct mem_ctl_info *mci, struct pci_dev *pdev, 356052dfb45ccb5ea354a426b52556bcfee75b9d2f5Douglas Thompson int dev_idx, u32 drc) 3571318952514d5651c453d89989595a9df3b37267bDoug Thompson{ 3581318952514d5651c453d89989595a9df3b37267bDoug Thompson unsigned long last_cumul_size; 359084a4fccef39ac7abb039511f32380f28d0b67e6Mauro Carvalho Chehab int index, j; 3601318952514d5651c453d89989595a9df3b37267bDoug Thompson u8 value; 361a895bf8b1e1ea4c032a8fa8a09475a2ce09fe77aMauro Carvalho Chehab u32 dra, cumul_size, nr_pages; 3621318952514d5651c453d89989595a9df3b37267bDoug Thompson int drc_chan, drc_drbg, drc_ddim, mem_dev; 3631318952514d5651c453d89989595a9df3b37267bDoug Thompson struct csrow_info *csrow; 364084a4fccef39ac7abb039511f32380f28d0b67e6Mauro Carvalho Chehab struct dimm_info *dimm; 365fd63312dfe70b8279618b4d77dc951b6e309ffa2Mauro Carvalho Chehab enum edac_type edac_mode; 366806c35f5057a64d3061ee4e2b1023bf6f6d328e2Alan Cox 367806c35f5057a64d3061ee4e2b1023bf6f6d328e2Alan Cox pci_read_config_dword(pdev, E7XXX_DRA, &dra); 3681318952514d5651c453d89989595a9df3b37267bDoug Thompson drc_chan = dual_channel_active(drc, dev_idx); 3691318952514d5651c453d89989595a9df3b37267bDoug Thompson drc_drbg = drb_granularity(drc, dev_idx); 3701318952514d5651c453d89989595a9df3b37267bDoug Thompson drc_ddim = (drc >> 20) & 0x3; 3711318952514d5651c453d89989595a9df3b37267bDoug Thompson last_cumul_size = 0; 372806c35f5057a64d3061ee4e2b1023bf6f6d328e2Alan Cox 3731318952514d5651c453d89989595a9df3b37267bDoug Thompson /* The dram row boundary (DRB) reg values are boundary address 374806c35f5057a64d3061ee4e2b1023bf6f6d328e2Alan Cox * for each DRAM row with a granularity of 32 or 64MB (single/dual 375806c35f5057a64d3061ee4e2b1023bf6f6d328e2Alan Cox * channel operation). DRB regs are cumulative; therefore DRB7 will 376806c35f5057a64d3061ee4e2b1023bf6f6d328e2Alan Cox * contain the total memory contained in all eight rows. 377806c35f5057a64d3061ee4e2b1023bf6f6d328e2Alan Cox */ 3781318952514d5651c453d89989595a9df3b37267bDoug Thompson for (index = 0; index < mci->nr_csrows; index++) { 379806c35f5057a64d3061ee4e2b1023bf6f6d328e2Alan Cox /* mem_dev 0=x8, 1=x4 */ 3801318952514d5651c453d89989595a9df3b37267bDoug Thompson mem_dev = (dra >> (index * 4 + 3)) & 0x1; 381de3910eb79ac8c0f29a11224661c0ebaaf813039Mauro Carvalho Chehab csrow = mci->csrows[index]; 382806c35f5057a64d3061ee4e2b1023bf6f6d328e2Alan Cox 38337f04581abac20444e5b7106c1e1f28bec5b989cDoug Thompson pci_read_config_byte(pdev, E7XXX_DRB + index, &value); 384806c35f5057a64d3061ee4e2b1023bf6f6d328e2Alan Cox /* convert a 64 or 32 MiB DRB to a page size. */ 385806c35f5057a64d3061ee4e2b1023bf6f6d328e2Alan Cox cumul_size = value << (25 + drc_drbg - PAGE_SHIFT); 386956b9ba156dbfdb9cede2b2927ddf8be2233b3a7Joe Perches edac_dbg(3, "(%d) cumul_size 0x%x\n", index, cumul_size); 387806c35f5057a64d3061ee4e2b1023bf6f6d328e2Alan Cox if (cumul_size == last_cumul_size) 3881318952514d5651c453d89989595a9df3b37267bDoug Thompson continue; /* not populated */ 389806c35f5057a64d3061ee4e2b1023bf6f6d328e2Alan Cox 390806c35f5057a64d3061ee4e2b1023bf6f6d328e2Alan Cox csrow->first_page = last_cumul_size; 391806c35f5057a64d3061ee4e2b1023bf6f6d328e2Alan Cox csrow->last_page = cumul_size - 1; 392a895bf8b1e1ea4c032a8fa8a09475a2ce09fe77aMauro Carvalho Chehab nr_pages = cumul_size - last_cumul_size; 393806c35f5057a64d3061ee4e2b1023bf6f6d328e2Alan Cox last_cumul_size = cumul_size; 394084a4fccef39ac7abb039511f32380f28d0b67e6Mauro Carvalho Chehab 395fd63312dfe70b8279618b4d77dc951b6e309ffa2Mauro Carvalho Chehab /* 396fd63312dfe70b8279618b4d77dc951b6e309ffa2Mauro Carvalho Chehab * if single channel or x8 devices then SECDED 397fd63312dfe70b8279618b4d77dc951b6e309ffa2Mauro Carvalho Chehab * if dual channel and x4 then S4ECD4ED 398fd63312dfe70b8279618b4d77dc951b6e309ffa2Mauro Carvalho Chehab */ 399fd63312dfe70b8279618b4d77dc951b6e309ffa2Mauro Carvalho Chehab if (drc_ddim) { 400fd63312dfe70b8279618b4d77dc951b6e309ffa2Mauro Carvalho Chehab if (drc_chan && mem_dev) { 401fd63312dfe70b8279618b4d77dc951b6e309ffa2Mauro Carvalho Chehab edac_mode = EDAC_S4ECD4ED; 402fd63312dfe70b8279618b4d77dc951b6e309ffa2Mauro Carvalho Chehab mci->edac_cap |= EDAC_FLAG_S4ECD4ED; 403fd63312dfe70b8279618b4d77dc951b6e309ffa2Mauro Carvalho Chehab } else { 404fd63312dfe70b8279618b4d77dc951b6e309ffa2Mauro Carvalho Chehab edac_mode = EDAC_SECDED; 405fd63312dfe70b8279618b4d77dc951b6e309ffa2Mauro Carvalho Chehab mci->edac_cap |= EDAC_FLAG_SECDED; 406fd63312dfe70b8279618b4d77dc951b6e309ffa2Mauro Carvalho Chehab } 407fd63312dfe70b8279618b4d77dc951b6e309ffa2Mauro Carvalho Chehab } else 408fd63312dfe70b8279618b4d77dc951b6e309ffa2Mauro Carvalho Chehab edac_mode = EDAC_NONE; 409fd63312dfe70b8279618b4d77dc951b6e309ffa2Mauro Carvalho Chehab 410084a4fccef39ac7abb039511f32380f28d0b67e6Mauro Carvalho Chehab for (j = 0; j < drc_chan + 1; j++) { 411de3910eb79ac8c0f29a11224661c0ebaaf813039Mauro Carvalho Chehab dimm = csrow->channels[j]->dimm; 412084a4fccef39ac7abb039511f32380f28d0b67e6Mauro Carvalho Chehab 413a895bf8b1e1ea4c032a8fa8a09475a2ce09fe77aMauro Carvalho Chehab dimm->nr_pages = nr_pages / (drc_chan + 1); 414084a4fccef39ac7abb039511f32380f28d0b67e6Mauro Carvalho Chehab dimm->grain = 1 << 12; /* 4KiB - resolution of CELOG */ 415084a4fccef39ac7abb039511f32380f28d0b67e6Mauro Carvalho Chehab dimm->mtype = MEM_RDDR; /* only one type supported */ 416084a4fccef39ac7abb039511f32380f28d0b67e6Mauro Carvalho Chehab dimm->dtype = mem_dev ? DEV_X4 : DEV_X8; 417fd63312dfe70b8279618b4d77dc951b6e309ffa2Mauro Carvalho Chehab dimm->edac_mode = edac_mode; 418084a4fccef39ac7abb039511f32380f28d0b67e6Mauro Carvalho Chehab } 419806c35f5057a64d3061ee4e2b1023bf6f6d328e2Alan Cox } 4201318952514d5651c453d89989595a9df3b37267bDoug Thompson} 421806c35f5057a64d3061ee4e2b1023bf6f6d328e2Alan Cox 4221318952514d5651c453d89989595a9df3b37267bDoug Thompsonstatic int e7xxx_probe1(struct pci_dev *pdev, int dev_idx) 4231318952514d5651c453d89989595a9df3b37267bDoug Thompson{ 4241318952514d5651c453d89989595a9df3b37267bDoug Thompson u16 pci_data; 4251318952514d5651c453d89989595a9df3b37267bDoug Thompson struct mem_ctl_info *mci = NULL; 42630ac44068121d7059bf025ed35b27caec408791eMauro Carvalho Chehab struct edac_mc_layer layers[2]; 4271318952514d5651c453d89989595a9df3b37267bDoug Thompson struct e7xxx_pvt *pvt = NULL; 4281318952514d5651c453d89989595a9df3b37267bDoug Thompson u32 drc; 4291318952514d5651c453d89989595a9df3b37267bDoug Thompson int drc_chan; 4301318952514d5651c453d89989595a9df3b37267bDoug Thompson struct e7xxx_error_info discard; 4311318952514d5651c453d89989595a9df3b37267bDoug Thompson 432956b9ba156dbfdb9cede2b2927ddf8be2233b3a7Joe Perches edac_dbg(0, "mci\n"); 433c0d121720220584bba2876b032e58a076b843fa1Dave Jiang 4341318952514d5651c453d89989595a9df3b37267bDoug Thompson pci_read_config_dword(pdev, E7XXX_DRC, &drc); 4351318952514d5651c453d89989595a9df3b37267bDoug Thompson 4361318952514d5651c453d89989595a9df3b37267bDoug Thompson drc_chan = dual_channel_active(drc, dev_idx); 43730ac44068121d7059bf025ed35b27caec408791eMauro Carvalho Chehab /* 43830ac44068121d7059bf025ed35b27caec408791eMauro Carvalho Chehab * According with the datasheet, this device has a maximum of 43930ac44068121d7059bf025ed35b27caec408791eMauro Carvalho Chehab * 4 DIMMS per channel, either single-rank or dual-rank. So, the 44030ac44068121d7059bf025ed35b27caec408791eMauro Carvalho Chehab * total amount of dimms is 8 (E7XXX_NR_DIMMS). 44130ac44068121d7059bf025ed35b27caec408791eMauro Carvalho Chehab * That means that the DIMM is mapped as CSROWs, and the channel 44230ac44068121d7059bf025ed35b27caec408791eMauro Carvalho Chehab * will map the rank. So, an error to either channel should be 44330ac44068121d7059bf025ed35b27caec408791eMauro Carvalho Chehab * attributed to the same dimm. 44430ac44068121d7059bf025ed35b27caec408791eMauro Carvalho Chehab */ 44530ac44068121d7059bf025ed35b27caec408791eMauro Carvalho Chehab layers[0].type = EDAC_MC_LAYER_CHIP_SELECT; 44630ac44068121d7059bf025ed35b27caec408791eMauro Carvalho Chehab layers[0].size = E7XXX_NR_CSROWS; 44730ac44068121d7059bf025ed35b27caec408791eMauro Carvalho Chehab layers[0].is_virt_csrow = true; 44830ac44068121d7059bf025ed35b27caec408791eMauro Carvalho Chehab layers[1].type = EDAC_MC_LAYER_CHANNEL; 44930ac44068121d7059bf025ed35b27caec408791eMauro Carvalho Chehab layers[1].size = drc_chan + 1; 45030ac44068121d7059bf025ed35b27caec408791eMauro Carvalho Chehab layers[1].is_virt_csrow = false; 451ca0907b9e413bb1d1f3ea123b663535b74928846Mauro Carvalho Chehab mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers, sizeof(*pvt)); 4521318952514d5651c453d89989595a9df3b37267bDoug Thompson if (mci == NULL) 4531318952514d5651c453d89989595a9df3b37267bDoug Thompson return -ENOMEM; 454806c35f5057a64d3061ee4e2b1023bf6f6d328e2Alan Cox 455956b9ba156dbfdb9cede2b2927ddf8be2233b3a7Joe Perches edac_dbg(3, "init mci\n"); 4561318952514d5651c453d89989595a9df3b37267bDoug Thompson mci->mtype_cap = MEM_FLAG_RDDR; 4571318952514d5651c453d89989595a9df3b37267bDoug Thompson mci->edac_ctl_cap = EDAC_FLAG_NONE | EDAC_FLAG_SECDED | 458052dfb45ccb5ea354a426b52556bcfee75b9d2f5Douglas Thompson EDAC_FLAG_S4ECD4ED; 4591318952514d5651c453d89989595a9df3b37267bDoug Thompson /* FIXME - what if different memory types are in different csrows? */ 4601318952514d5651c453d89989595a9df3b37267bDoug Thompson mci->mod_name = EDAC_MOD_STR; 4611318952514d5651c453d89989595a9df3b37267bDoug Thompson mci->mod_ver = E7XXX_REVISION; 462fd687502dc8037aa5a4b84c570ada971106574eeMauro Carvalho Chehab mci->pdev = &pdev->dev; 463956b9ba156dbfdb9cede2b2927ddf8be2233b3a7Joe Perches edac_dbg(3, "init pvt\n"); 464849a4c375a8e06cd000399dceb25888d356d021fDave Jiang pvt = (struct e7xxx_pvt *)mci->pvt_info; 4651318952514d5651c453d89989595a9df3b37267bDoug Thompson pvt->dev_info = &e7xxx_devs[dev_idx]; 4661318952514d5651c453d89989595a9df3b37267bDoug Thompson pvt->bridge_ck = pci_get_device(PCI_VENDOR_ID_INTEL, 467849a4c375a8e06cd000399dceb25888d356d021fDave Jiang pvt->dev_info->err_dev, pvt->bridge_ck); 4681318952514d5651c453d89989595a9df3b37267bDoug Thompson 4691318952514d5651c453d89989595a9df3b37267bDoug Thompson if (!pvt->bridge_ck) { 4701318952514d5651c453d89989595a9df3b37267bDoug Thompson e7xxx_printk(KERN_ERR, "error reporting device not found:" 471052dfb45ccb5ea354a426b52556bcfee75b9d2f5Douglas Thompson "vendor %x device 0x%x (broken BIOS?)\n", 472052dfb45ccb5ea354a426b52556bcfee75b9d2f5Douglas Thompson PCI_VENDOR_ID_INTEL, e7xxx_devs[dev_idx].err_dev); 4731318952514d5651c453d89989595a9df3b37267bDoug Thompson goto fail0; 4741318952514d5651c453d89989595a9df3b37267bDoug Thompson } 4751318952514d5651c453d89989595a9df3b37267bDoug Thompson 476956b9ba156dbfdb9cede2b2927ddf8be2233b3a7Joe Perches edac_dbg(3, "more mci init\n"); 4771318952514d5651c453d89989595a9df3b37267bDoug Thompson mci->ctl_name = pvt->dev_info->ctl_name; 478c4192705fec85219086231a1c0fa61e8776e2c3bDave Jiang mci->dev_name = pci_name(pdev); 4791318952514d5651c453d89989595a9df3b37267bDoug Thompson mci->edac_check = e7xxx_check; 4801318952514d5651c453d89989595a9df3b37267bDoug Thompson mci->ctl_page_to_phys = ctl_page_to_phys; 4811318952514d5651c453d89989595a9df3b37267bDoug Thompson e7xxx_init_csrows(mci, pdev, dev_idx, drc); 4821318952514d5651c453d89989595a9df3b37267bDoug Thompson mci->edac_cap |= EDAC_FLAG_NONE; 483956b9ba156dbfdb9cede2b2927ddf8be2233b3a7Joe Perches edac_dbg(3, "tolm, remapbase, remaplimit\n"); 484806c35f5057a64d3061ee4e2b1023bf6f6d328e2Alan Cox /* load the top of low memory, remap base, and remap limit vars */ 48537f04581abac20444e5b7106c1e1f28bec5b989cDoug Thompson pci_read_config_word(pdev, E7XXX_TOLM, &pci_data); 486806c35f5057a64d3061ee4e2b1023bf6f6d328e2Alan Cox pvt->tolm = ((u32) pci_data) << 4; 48737f04581abac20444e5b7106c1e1f28bec5b989cDoug Thompson pci_read_config_word(pdev, E7XXX_REMAPBASE, &pci_data); 488806c35f5057a64d3061ee4e2b1023bf6f6d328e2Alan Cox pvt->remapbase = ((u32) pci_data) << 14; 48937f04581abac20444e5b7106c1e1f28bec5b989cDoug Thompson pci_read_config_word(pdev, E7XXX_REMAPLIMIT, &pci_data); 490806c35f5057a64d3061ee4e2b1023bf6f6d328e2Alan Cox pvt->remaplimit = ((u32) pci_data) << 14; 491537fba28928c01b7db1580627450691a4bb0b9b3Dave Peterson e7xxx_printk(KERN_INFO, 492052dfb45ccb5ea354a426b52556bcfee75b9d2f5Douglas Thompson "tolm = %x, remapbase = %x, remaplimit = %x\n", pvt->tolm, 493052dfb45ccb5ea354a426b52556bcfee75b9d2f5Douglas Thompson pvt->remapbase, pvt->remaplimit); 494806c35f5057a64d3061ee4e2b1023bf6f6d328e2Alan Cox 495806c35f5057a64d3061ee4e2b1023bf6f6d328e2Alan Cox /* clear any pending errors, or initial state bits */ 496749ede57443b2a7ede2db105145f21047efcea6aDave Peterson e7xxx_get_error_info(mci, &discard); 497806c35f5057a64d3061ee4e2b1023bf6f6d328e2Alan Cox 4982d7bbb91c8df26c60d223205a087507430024177Doug Thompson /* Here we assume that we will never see multiple instances of this 4992d7bbb91c8df26c60d223205a087507430024177Doug Thompson * type of memory controller. The ID is therefore hardcoded to 0. 5002d7bbb91c8df26c60d223205a087507430024177Doug Thompson */ 501b8f6f9755248026f21282e25cac49a1af698056cDoug Thompson if (edac_mc_add_mc(mci)) { 502956b9ba156dbfdb9cede2b2927ddf8be2233b3a7Joe Perches edac_dbg(3, "failed edac_mc_add_mc()\n"); 5031318952514d5651c453d89989595a9df3b37267bDoug Thompson goto fail1; 504806c35f5057a64d3061ee4e2b1023bf6f6d328e2Alan Cox } 505806c35f5057a64d3061ee4e2b1023bf6f6d328e2Alan Cox 506456a2f9552e7849475f4aea1a9aa4c0e54b3dddaDave Jiang /* allocating generic PCI control info */ 507456a2f9552e7849475f4aea1a9aa4c0e54b3dddaDave Jiang e7xxx_pci = edac_pci_create_generic_ctl(&pdev->dev, EDAC_MOD_STR); 508456a2f9552e7849475f4aea1a9aa4c0e54b3dddaDave Jiang if (!e7xxx_pci) { 509456a2f9552e7849475f4aea1a9aa4c0e54b3dddaDave Jiang printk(KERN_WARNING 510456a2f9552e7849475f4aea1a9aa4c0e54b3dddaDave Jiang "%s(): Unable to create PCI control\n", 511456a2f9552e7849475f4aea1a9aa4c0e54b3dddaDave Jiang __func__); 512456a2f9552e7849475f4aea1a9aa4c0e54b3dddaDave Jiang printk(KERN_WARNING 513456a2f9552e7849475f4aea1a9aa4c0e54b3dddaDave Jiang "%s(): PCI error report via EDAC not setup\n", 514456a2f9552e7849475f4aea1a9aa4c0e54b3dddaDave Jiang __func__); 515456a2f9552e7849475f4aea1a9aa4c0e54b3dddaDave Jiang } 516456a2f9552e7849475f4aea1a9aa4c0e54b3dddaDave Jiang 517806c35f5057a64d3061ee4e2b1023bf6f6d328e2Alan Cox /* get this far and it's successful */ 518956b9ba156dbfdb9cede2b2927ddf8be2233b3a7Joe Perches edac_dbg(3, "success\n"); 519806c35f5057a64d3061ee4e2b1023bf6f6d328e2Alan Cox return 0; 520806c35f5057a64d3061ee4e2b1023bf6f6d328e2Alan Cox 521052dfb45ccb5ea354a426b52556bcfee75b9d2f5Douglas Thompsonfail1: 5221318952514d5651c453d89989595a9df3b37267bDoug Thompson pci_dev_put(pvt->bridge_ck); 5231318952514d5651c453d89989595a9df3b37267bDoug Thompson 524052dfb45ccb5ea354a426b52556bcfee75b9d2f5Douglas Thompsonfail0: 5251318952514d5651c453d89989595a9df3b37267bDoug Thompson edac_mc_free(mci); 526806c35f5057a64d3061ee4e2b1023bf6f6d328e2Alan Cox 5271318952514d5651c453d89989595a9df3b37267bDoug Thompson return -ENODEV; 528806c35f5057a64d3061ee4e2b1023bf6f6d328e2Alan Cox} 529806c35f5057a64d3061ee4e2b1023bf6f6d328e2Alan Cox 530806c35f5057a64d3061ee4e2b1023bf6f6d328e2Alan Cox/* returns count (>= 0), or negative on error */ 5319b3c6e85c2cfa731cf67d5a8c49f7d8c60ec0b04Greg Kroah-Hartmanstatic int e7xxx_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) 532806c35f5057a64d3061ee4e2b1023bf6f6d328e2Alan Cox{ 533956b9ba156dbfdb9cede2b2927ddf8be2233b3a7Joe Perches edac_dbg(0, "\n"); 534806c35f5057a64d3061ee4e2b1023bf6f6d328e2Alan Cox 535806c35f5057a64d3061ee4e2b1023bf6f6d328e2Alan Cox /* wake up and enable device */ 536806c35f5057a64d3061ee4e2b1023bf6f6d328e2Alan Cox return pci_enable_device(pdev) ? 537052dfb45ccb5ea354a426b52556bcfee75b9d2f5Douglas Thompson -EIO : e7xxx_probe1(pdev, ent->driver_data); 538806c35f5057a64d3061ee4e2b1023bf6f6d328e2Alan Cox} 539806c35f5057a64d3061ee4e2b1023bf6f6d328e2Alan Cox 5409b3c6e85c2cfa731cf67d5a8c49f7d8c60ec0b04Greg Kroah-Hartmanstatic void e7xxx_remove_one(struct pci_dev *pdev) 541806c35f5057a64d3061ee4e2b1023bf6f6d328e2Alan Cox{ 542806c35f5057a64d3061ee4e2b1023bf6f6d328e2Alan Cox struct mem_ctl_info *mci; 543806c35f5057a64d3061ee4e2b1023bf6f6d328e2Alan Cox struct e7xxx_pvt *pvt; 544806c35f5057a64d3061ee4e2b1023bf6f6d328e2Alan Cox 545956b9ba156dbfdb9cede2b2927ddf8be2233b3a7Joe Perches edac_dbg(0, "\n"); 546806c35f5057a64d3061ee4e2b1023bf6f6d328e2Alan Cox 547456a2f9552e7849475f4aea1a9aa4c0e54b3dddaDave Jiang if (e7xxx_pci) 548456a2f9552e7849475f4aea1a9aa4c0e54b3dddaDave Jiang edac_pci_release_generic_ctl(e7xxx_pci); 549456a2f9552e7849475f4aea1a9aa4c0e54b3dddaDave Jiang 55037f04581abac20444e5b7106c1e1f28bec5b989cDoug Thompson if ((mci = edac_mc_del_mc(&pdev->dev)) == NULL) 55118dbc337af5d6efd30cb9291e74722c8ad134fd3Dave Peterson return; 55218dbc337af5d6efd30cb9291e74722c8ad134fd3Dave Peterson 553849a4c375a8e06cd000399dceb25888d356d021fDave Jiang pvt = (struct e7xxx_pvt *)mci->pvt_info; 55418dbc337af5d6efd30cb9291e74722c8ad134fd3Dave Peterson pci_dev_put(pvt->bridge_ck); 55518dbc337af5d6efd30cb9291e74722c8ad134fd3Dave Peterson edac_mc_free(mci); 556806c35f5057a64d3061ee4e2b1023bf6f6d328e2Alan Cox} 557806c35f5057a64d3061ee4e2b1023bf6f6d328e2Alan Cox 558ba935f40979b32924824759111ed95d35469c5faJingoo Hanstatic const struct pci_device_id e7xxx_pci_tbl[] = { 559e7ecd8910293564d357dbaf18eb179e06fa35fd0Dave Peterson { 560849a4c375a8e06cd000399dceb25888d356d021fDave Jiang PCI_VEND_DEV(INTEL, 7205_0), PCI_ANY_ID, PCI_ANY_ID, 0, 0, 561849a4c375a8e06cd000399dceb25888d356d021fDave Jiang E7205}, 562e7ecd8910293564d357dbaf18eb179e06fa35fd0Dave Peterson { 563849a4c375a8e06cd000399dceb25888d356d021fDave Jiang PCI_VEND_DEV(INTEL, 7500_0), PCI_ANY_ID, PCI_ANY_ID, 0, 0, 564849a4c375a8e06cd000399dceb25888d356d021fDave Jiang E7500}, 565e7ecd8910293564d357dbaf18eb179e06fa35fd0Dave Peterson { 566849a4c375a8e06cd000399dceb25888d356d021fDave Jiang PCI_VEND_DEV(INTEL, 7501_0), PCI_ANY_ID, PCI_ANY_ID, 0, 0, 567849a4c375a8e06cd000399dceb25888d356d021fDave Jiang E7501}, 568e7ecd8910293564d357dbaf18eb179e06fa35fd0Dave Peterson { 569849a4c375a8e06cd000399dceb25888d356d021fDave Jiang PCI_VEND_DEV(INTEL, 7505_0), PCI_ANY_ID, PCI_ANY_ID, 0, 0, 570849a4c375a8e06cd000399dceb25888d356d021fDave Jiang E7505}, 571e7ecd8910293564d357dbaf18eb179e06fa35fd0Dave Peterson { 572849a4c375a8e06cd000399dceb25888d356d021fDave Jiang 0, 573849a4c375a8e06cd000399dceb25888d356d021fDave Jiang } /* 0 terminated list. */ 574806c35f5057a64d3061ee4e2b1023bf6f6d328e2Alan Cox}; 575806c35f5057a64d3061ee4e2b1023bf6f6d328e2Alan Cox 576806c35f5057a64d3061ee4e2b1023bf6f6d328e2Alan CoxMODULE_DEVICE_TABLE(pci, e7xxx_pci_tbl); 577806c35f5057a64d3061ee4e2b1023bf6f6d328e2Alan Cox 578806c35f5057a64d3061ee4e2b1023bf6f6d328e2Alan Coxstatic struct pci_driver e7xxx_driver = { 579680cbbbb0e336b04b74be48b8ddd870537f1e226Dave Peterson .name = EDAC_MOD_STR, 580806c35f5057a64d3061ee4e2b1023bf6f6d328e2Alan Cox .probe = e7xxx_init_one, 5819b3c6e85c2cfa731cf67d5a8c49f7d8c60ec0b04Greg Kroah-Hartman .remove = e7xxx_remove_one, 582806c35f5057a64d3061ee4e2b1023bf6f6d328e2Alan Cox .id_table = e7xxx_pci_tbl, 583806c35f5057a64d3061ee4e2b1023bf6f6d328e2Alan Cox}; 584806c35f5057a64d3061ee4e2b1023bf6f6d328e2Alan Cox 585da9bb1d27b21cb24cbb6a2efb5d3c464d357a01eAlan Coxstatic int __init e7xxx_init(void) 586806c35f5057a64d3061ee4e2b1023bf6f6d328e2Alan Cox{ 587c3c52bce6993c6d37af2c2de9b482a7013d646a7Hitoshi Mitake /* Ensure that the OPSTATE is set correctly for POLL or NMI */ 588c3c52bce6993c6d37af2c2de9b482a7013d646a7Hitoshi Mitake opstate_init(); 589c3c52bce6993c6d37af2c2de9b482a7013d646a7Hitoshi Mitake 590806c35f5057a64d3061ee4e2b1023bf6f6d328e2Alan Cox return pci_register_driver(&e7xxx_driver); 591806c35f5057a64d3061ee4e2b1023bf6f6d328e2Alan Cox} 592806c35f5057a64d3061ee4e2b1023bf6f6d328e2Alan Cox 593806c35f5057a64d3061ee4e2b1023bf6f6d328e2Alan Coxstatic void __exit e7xxx_exit(void) 594806c35f5057a64d3061ee4e2b1023bf6f6d328e2Alan Cox{ 595806c35f5057a64d3061ee4e2b1023bf6f6d328e2Alan Cox pci_unregister_driver(&e7xxx_driver); 596806c35f5057a64d3061ee4e2b1023bf6f6d328e2Alan Cox} 597806c35f5057a64d3061ee4e2b1023bf6f6d328e2Alan Cox 598806c35f5057a64d3061ee4e2b1023bf6f6d328e2Alan Coxmodule_init(e7xxx_init); 599806c35f5057a64d3061ee4e2b1023bf6f6d328e2Alan Coxmodule_exit(e7xxx_exit); 600806c35f5057a64d3061ee4e2b1023bf6f6d328e2Alan Cox 601806c35f5057a64d3061ee4e2b1023bf6f6d328e2Alan CoxMODULE_LICENSE("GPL"); 602806c35f5057a64d3061ee4e2b1023bf6f6d328e2Alan CoxMODULE_AUTHOR("Linux Networx (http://lnxi.com) Thayne Harbaugh et al\n" 603052dfb45ccb5ea354a426b52556bcfee75b9d2f5Douglas Thompson "Based on.work by Dan Hollis et al"); 604806c35f5057a64d3061ee4e2b1023bf6f6d328e2Alan CoxMODULE_DESCRIPTION("MC support for Intel e7xxx memory controllers"); 605c0d121720220584bba2876b032e58a076b843fa1Dave Jiangmodule_param(edac_op_state, int, 0444); 606c0d121720220584bba2876b032e58a076b843fa1Dave JiangMODULE_PARM_DESC(edac_op_state, "EDAC Error Reporting state: 0=Poll,1=NMI"); 607