highbank_mc_edac.c revision 41ec0e8da05267120c99bd4f66277939fad81a07 
1/*
2 * Copyright 2011-2012 Calxeda, Inc.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License along with
14 * this program.  If not, see <http://www.gnu.org/licenses/>.
15 */
16#include <linux/types.h>
17#include <linux/kernel.h>
18#include <linux/ctype.h>
19#include <linux/edac.h>
20#include <linux/interrupt.h>
21#include <linux/platform_device.h>
22#include <linux/of_platform.h>
23#include <linux/uaccess.h>
24
25#include "edac_core.h"
26#include "edac_module.h"
27
28/* DDR Ctrlr Error Registers */
29
30#define HB_DDR_ECC_ERR_BASE		0x128
31#define MW_DDR_ECC_ERR_BASE		0x1b4
32
33#define HB_DDR_ECC_OPT			0x00
34#define HB_DDR_ECC_U_ERR_ADDR		0x08
35#define HB_DDR_ECC_U_ERR_STAT		0x0c
36#define HB_DDR_ECC_U_ERR_DATAL		0x10
37#define HB_DDR_ECC_U_ERR_DATAH		0x14
38#define HB_DDR_ECC_C_ERR_ADDR		0x18
39#define HB_DDR_ECC_C_ERR_STAT		0x1c
40#define HB_DDR_ECC_C_ERR_DATAL		0x20
41#define HB_DDR_ECC_C_ERR_DATAH		0x24
42
43#define HB_DDR_ECC_OPT_MODE_MASK	0x3
44#define HB_DDR_ECC_OPT_FWC		0x100
45#define HB_DDR_ECC_OPT_XOR_SHIFT	16
46
47/* DDR Ctrlr Interrupt Registers */
48
49#define HB_DDR_ECC_INT_BASE		0x180
50#define MW_DDR_ECC_INT_BASE		0x218
51
52#define HB_DDR_ECC_INT_STATUS		0x00
53#define HB_DDR_ECC_INT_ACK		0x04
54
55#define HB_DDR_ECC_INT_STAT_CE		0x8
56#define HB_DDR_ECC_INT_STAT_DOUBLE_CE	0x10
57#define HB_DDR_ECC_INT_STAT_UE		0x20
58#define HB_DDR_ECC_INT_STAT_DOUBLE_UE	0x40
59
60struct hb_mc_drvdata {
61	void __iomem *mc_err_base;
62	void __iomem *mc_int_base;
63};
64
65static irqreturn_t highbank_mc_err_handler(int irq, void *dev_id)
66{
67	struct mem_ctl_info *mci = dev_id;
68	struct hb_mc_drvdata *drvdata = mci->pvt_info;
69	u32 status, err_addr;
70
71	/* Read the interrupt status register */
72	status = readl(drvdata->mc_int_base + HB_DDR_ECC_INT_STATUS);
73
74	if (status & HB_DDR_ECC_INT_STAT_UE) {
75		err_addr = readl(drvdata->mc_err_base + HB_DDR_ECC_U_ERR_ADDR);
76		edac_mc_handle_error(HW_EVENT_ERR_UNCORRECTED, mci, 1,
77				     err_addr >> PAGE_SHIFT,
78				     err_addr & ~PAGE_MASK, 0,
79				     0, 0, -1,
80				     mci->ctl_name, "");
81	}
82	if (status & HB_DDR_ECC_INT_STAT_CE) {
83		u32 syndrome = readl(drvdata->mc_err_base + HB_DDR_ECC_C_ERR_STAT);
84		syndrome = (syndrome >> 8) & 0xff;
85		err_addr = readl(drvdata->mc_err_base + HB_DDR_ECC_C_ERR_ADDR);
86		edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, mci, 1,
87				     err_addr >> PAGE_SHIFT,
88				     err_addr & ~PAGE_MASK, syndrome,
89				     0, 0, -1,
90				     mci->ctl_name, "");
91	}
92
93	/* clear the error, clears the interrupt */
94	writel(status, drvdata->mc_int_base + HB_DDR_ECC_INT_ACK);
95	return IRQ_HANDLED;
96}
97
98#ifdef CONFIG_EDAC_DEBUG
99static ssize_t highbank_mc_err_inject_write(struct file *file,
100				      const char __user *data,
101				      size_t count, loff_t *ppos)
102{
103	struct mem_ctl_info *mci = file->private_data;
104	struct hb_mc_drvdata *pdata = mci->pvt_info;
105	char buf[32];
106	size_t buf_size;
107	u32 reg;
108	u8 synd;
109
110	buf_size = min(count, (sizeof(buf)-1));
111	if (copy_from_user(buf, data, buf_size))
112		return -EFAULT;
113	buf[buf_size] = 0;
114
115	if (!kstrtou8(buf, 16, &synd)) {
116		reg = readl(pdata->mc_err_base + HB_DDR_ECC_OPT);
117		reg &= HB_DDR_ECC_OPT_MODE_MASK;
118		reg |= (synd << HB_DDR_ECC_OPT_XOR_SHIFT) | HB_DDR_ECC_OPT_FWC;
119		writel(reg, pdata->mc_err_base + HB_DDR_ECC_OPT);
120	}
121
122	return count;
123}
124
125static const struct file_operations highbank_mc_debug_inject_fops = {
126	.open = simple_open,
127	.write = highbank_mc_err_inject_write,
128	.llseek = generic_file_llseek,
129};
130
131static void highbank_mc_create_debugfs_nodes(struct mem_ctl_info *mci)
132{
133	if (mci->debugfs)
134		debugfs_create_file("inject_ctrl", S_IWUSR, mci->debugfs, mci,
135				    &highbank_mc_debug_inject_fops);
136;
137}
138#else
139static void highbank_mc_create_debugfs_nodes(struct mem_ctl_info *mci)
140{}
141#endif
142
143struct hb_mc_settings {
144	int	err_offset;
145	int	int_offset;
146};
147
148static struct hb_mc_settings hb_settings = {
149	.err_offset = HB_DDR_ECC_ERR_BASE,
150	.int_offset = HB_DDR_ECC_INT_BASE,
151};
152
153static struct hb_mc_settings mw_settings = {
154	.err_offset = MW_DDR_ECC_ERR_BASE,
155	.int_offset = MW_DDR_ECC_INT_BASE,
156};
157
158static struct of_device_id hb_ddr_ctrl_of_match[] = {
159	{ .compatible = "calxeda,hb-ddr-ctrl",		.data = &hb_settings },
160	{ .compatible = "calxeda,ecx-2000-ddr-ctrl",	.data = &mw_settings },
161	{},
162};
163MODULE_DEVICE_TABLE(of, hb_ddr_ctrl_of_match);
164
165static int highbank_mc_probe(struct platform_device *pdev)
166{
167	const struct of_device_id *id;
168	const struct hb_mc_settings *settings;
169	struct edac_mc_layer layers[2];
170	struct mem_ctl_info *mci;
171	struct hb_mc_drvdata *drvdata;
172	struct dimm_info *dimm;
173	struct resource *r;
174	void __iomem *base;
175	u32 control;
176	int irq;
177	int res = 0;
178
179	id = of_match_device(hb_ddr_ctrl_of_match, &pdev->dev);
180	if (!id)
181		return -ENODEV;
182
183	layers[0].type = EDAC_MC_LAYER_CHIP_SELECT;
184	layers[0].size = 1;
185	layers[0].is_virt_csrow = true;
186	layers[1].type = EDAC_MC_LAYER_CHANNEL;
187	layers[1].size = 1;
188	layers[1].is_virt_csrow = false;
189	mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers,
190			    sizeof(struct hb_mc_drvdata));
191	if (!mci)
192		return -ENOMEM;
193
194	mci->pdev = &pdev->dev;
195	drvdata = mci->pvt_info;
196	platform_set_drvdata(pdev, mci);
197
198	if (!devres_open_group(&pdev->dev, NULL, GFP_KERNEL))
199		return -ENOMEM;
200
201	r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
202	if (!r) {
203		dev_err(&pdev->dev, "Unable to get mem resource\n");
204		res = -ENODEV;
205		goto err;
206	}
207
208	if (!devm_request_mem_region(&pdev->dev, r->start,
209				     resource_size(r), dev_name(&pdev->dev))) {
210		dev_err(&pdev->dev, "Error while requesting mem region\n");
211		res = -EBUSY;
212		goto err;
213	}
214
215	base = devm_ioremap(&pdev->dev, r->start, resource_size(r));
216	if (!base) {
217		dev_err(&pdev->dev, "Unable to map regs\n");
218		res = -ENOMEM;
219		goto err;
220	}
221
222	settings = id->data;
223	drvdata->mc_err_base = base + settings->err_offset;
224	drvdata->mc_int_base = base + settings->int_offset;
225
226	control = readl(drvdata->mc_err_base + HB_DDR_ECC_OPT) & 0x3;
227	if (!control || (control == 0x2)) {
228		dev_err(&pdev->dev, "No ECC present, or ECC disabled\n");
229		res = -ENODEV;
230		goto err;
231	}
232
233	mci->mtype_cap = MEM_FLAG_DDR3;
234	mci->edac_ctl_cap = EDAC_FLAG_NONE | EDAC_FLAG_SECDED;
235	mci->edac_cap = EDAC_FLAG_SECDED;
236	mci->mod_name = pdev->dev.driver->name;
237	mci->mod_ver = "1";
238	mci->ctl_name = id->compatible;
239	mci->dev_name = dev_name(&pdev->dev);
240	mci->scrub_mode = SCRUB_SW_SRC;
241
242	/* Only a single 4GB DIMM is supported */
243	dimm = *mci->dimms;
244	dimm->nr_pages = (~0UL >> PAGE_SHIFT) + 1;
245	dimm->grain = 8;
246	dimm->dtype = DEV_X8;
247	dimm->mtype = MEM_DDR3;
248	dimm->edac_mode = EDAC_SECDED;
249
250	res = edac_mc_add_mc(mci);
251	if (res < 0)
252		goto err;
253
254	irq = platform_get_irq(pdev, 0);
255	res = devm_request_irq(&pdev->dev, irq, highbank_mc_err_handler,
256			       0, dev_name(&pdev->dev), mci);
257	if (res < 0) {
258		dev_err(&pdev->dev, "Unable to request irq %d\n", irq);
259		goto err2;
260	}
261
262	highbank_mc_create_debugfs_nodes(mci);
263
264	devres_close_group(&pdev->dev, NULL);
265	return 0;
266err2:
267	edac_mc_del_mc(&pdev->dev);
268err:
269	devres_release_group(&pdev->dev, NULL);
270	edac_mc_free(mci);
271	return res;
272}
273
274static int highbank_mc_remove(struct platform_device *pdev)
275{
276	struct mem_ctl_info *mci = platform_get_drvdata(pdev);
277
278	edac_mc_del_mc(&pdev->dev);
279	edac_mc_free(mci);
280	return 0;
281}
282
283static struct platform_driver highbank_mc_edac_driver = {
284	.probe = highbank_mc_probe,
285	.remove = highbank_mc_remove,
286	.driver = {
287		.name = "hb_mc_edac",
288		.of_match_table = hb_ddr_ctrl_of_match,
289	},
290};
291
292module_platform_driver(highbank_mc_edac_driver);
293
294MODULE_LICENSE("GPL v2");
295MODULE_AUTHOR("Calxeda, Inc.");
296MODULE_DESCRIPTION("EDAC Driver for Calxeda Highbank");
297