12f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox/* 22f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox * Radisys 82600 Embedded chipset Memory Controller kernel module 32f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox * (C) 2005 EADS Astrium 42f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox * This file may be distributed under the terms of the 52f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox * GNU General Public License. 62f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox * 72f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox * Written by Tim Small <tim@buttersideup.com>, based on work by Thayne 82f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox * Harbaugh, Dan Hollis <goemon at anime dot net> and others. 92f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox * 102f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox * $Id: edac_r82600.c,v 1.1.2.6 2005/10/05 00:43:44 dsp_llnl Exp $ 112f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox * 122f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox * Written with reference to 82600 High Integration Dual PCI System 132f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox * Controller Data Book: 14c4192705fec85219086231a1c0fa61e8776e2c3bDave Jiang * www.radisys.com/files/support_downloads/007-01277-0002.82600DataBook.pdf 152f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox * references to this document given in [] 162f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox */ 172f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox 182f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox#include <linux/module.h> 192f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox#include <linux/init.h> 202f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox#include <linux/pci.h> 212f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox#include <linux/pci_ids.h> 22c3c52bce6993c6d37af2c2de9b482a7013d646a7Hitoshi Mitake#include <linux/edac.h> 2320bcb7a81dee21bfa3408f03f46b2891c9b5c84bDouglas Thompson#include "edac_core.h" 242f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox 25152ba3942276c2a240703669ae4a3099e0a79451Michal Marek#define R82600_REVISION " Ver: 2.0.2" 26929a40ec324e947d4ad14cc1ced785c104c560e2Doug Thompson#define EDAC_MOD_STR "r82600_edac" 2737f04581abac20444e5b7106c1e1f28bec5b989cDoug Thompson 28537fba28928c01b7db1580627450691a4bb0b9b3Dave Peterson#define r82600_printk(level, fmt, arg...) \ 29e7ecd8910293564d357dbaf18eb179e06fa35fd0Dave Peterson edac_printk(level, "r82600", fmt, ##arg) 30537fba28928c01b7db1580627450691a4bb0b9b3Dave Peterson 31537fba28928c01b7db1580627450691a4bb0b9b3Dave Peterson#define r82600_mc_printk(mci, level, fmt, arg...) \ 32e7ecd8910293564d357dbaf18eb179e06fa35fd0Dave Peterson edac_mc_chipset_printk(mci, level, "r82600", fmt, ##arg) 33537fba28928c01b7db1580627450691a4bb0b9b3Dave Peterson 342f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox/* Radisys say "The 82600 integrates a main memory SDRAM controller that 352f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox * supports up to four banks of memory. The four banks can support a mix of 362f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox * sizes of 64 bit wide (72 bits with ECC) Synchronous DRAM (SDRAM) DIMMs, 372f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox * each of which can be any size from 16MB to 512MB. Both registered (control 382f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox * signals buffered) and unbuffered DIMM types are supported. Mixing of 392f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox * registered and unbuffered DIMMs as well as mixing of ECC and non-ECC DIMMs 402f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox * is not allowed. The 82600 SDRAM interface operates at the same frequency as 412f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox * the CPU bus, 66MHz, 100MHz or 133MHz." 422f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox */ 432f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox 442f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox#define R82600_NR_CSROWS 4 452f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox#define R82600_NR_CHANS 1 462f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox#define R82600_NR_DIMMS 4 472f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox 482f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox#define R82600_BRIDGE_ID 0x8200 492f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox 502f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox/* Radisys 82600 register addresses - device 0 function 0 - PCI bridge */ 512f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox#define R82600_DRAMC 0x57 /* Various SDRAM related control bits 522f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox * all bits are R/W 532f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox * 542f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox * 7 SDRAM ISA Hole Enable 552f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox * 6 Flash Page Mode Enable 562f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox * 5 ECC Enable: 1=ECC 0=noECC 572f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox * 4 DRAM DIMM Type: 1= 582f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox * 3 BIOS Alias Disable 592f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox * 2 SDRAM BIOS Flash Write Enable 602f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox * 1:0 SDRAM Refresh Rate: 00=Disabled 612f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox * 01=7.8usec (256Mbit SDRAMs) 622f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox * 10=15.6us 11=125usec 632f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox */ 642f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox 652f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox#define R82600_SDRAMC 0x76 /* "SDRAM Control Register" 662f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox * More SDRAM related control bits 672f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox * all bits are R/W 682f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox * 692f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox * 15:8 Reserved. 702f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox * 712f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox * 7:5 Special SDRAM Mode Select 722f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox * 732f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox * 4 Force ECC 742f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox * 752f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox * 1=Drive ECC bits to 0 during 762f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox * write cycles (i.e. ECC test mode) 772f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox * 782f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox * 0=Normal ECC functioning 792f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox * 802f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox * 3 Enhanced Paging Enable 812f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox * 822f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox * 2 CAS# Latency 0=3clks 1=2clks 832f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox * 842f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox * 1 RAS# to CAS# Delay 0=3 1=2 852f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox * 862f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox * 0 RAS# Precharge 0=3 1=2 872f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox */ 882f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox 892f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox#define R82600_EAP 0x80 /* ECC Error Address Pointer Register 902f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox * 912f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox * 31 Disable Hardware Scrubbing (RW) 922f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox * 0=Scrub on corrected read 932f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox * 1=Don't scrub on corrected read 942f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox * 952f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox * 30:12 Error Address Pointer (RO) 962f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox * Upper 19 bits of error address 972f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox * 982f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox * 11:4 Syndrome Bits (RO) 992f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox * 1002f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox * 3 BSERR# on multibit error (RW) 1012f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox * 1=enable 0=disable 1022f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox * 1032f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox * 2 NMI on Single Bit Eror (RW) 1042f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox * 1=NMI triggered by SBE n.b. other 1052f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox * prerequeists 1062f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox * 0=NMI not triggered 1072f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox * 1082f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox * 1 MBE (R/WC) 1092f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox * read 1=MBE at EAP (see above) 1102f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox * read 0=no MBE, or SBE occurred first 1112f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox * write 1=Clear MBE status (must also 1122f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox * clear SBE) 1132f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox * write 0=NOP 1142f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox * 1152f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox * 1 SBE (R/WC) 1162f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox * read 1=SBE at EAP (see above) 1172f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox * read 0=no SBE, or MBE occurred first 1182f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox * write 1=Clear SBE status (must also 1192f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox * clear MBE) 1202f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox * write 0=NOP 1212f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox */ 1222f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox 12325985edcedea6396277003854657b5f3cb31a628Lucas De Marchi#define R82600_DRBA 0x60 /* + 0x60..0x63 SDRAM Row Boundary Address 1242f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox * Registers 1252f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox * 1262f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox * 7:0 Address lines 30:24 - upper limit of 1272f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox * each row [p57] 1282f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox */ 1292f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox 1302f768af73fea4c70f9046388a7ff648ad11f028eAlan Coxstruct r82600_error_info { 1312f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox u32 eapr; 1322f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox}; 1332f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox 13490ab5ee94171b3e28de6bb42ee30b527014e0be7Rusty Russellstatic bool disable_hardware_scrub; 1352f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox 136456a2f9552e7849475f4aea1a9aa4c0e54b3dddaDave Jiangstatic struct edac_pci_ctl_info *r82600_pci; 137456a2f9552e7849475f4aea1a9aa4c0e54b3dddaDave Jiang 138cddbfcacf02dc2d5b074fc2717358a7529a190dbDouglas Thompsonstatic void r82600_get_error_info(struct mem_ctl_info *mci, 139052dfb45ccb5ea354a426b52556bcfee75b9d2f5Douglas Thompson struct r82600_error_info *info) 1402f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox{ 14137f04581abac20444e5b7106c1e1f28bec5b989cDoug Thompson struct pci_dev *pdev; 14237f04581abac20444e5b7106c1e1f28bec5b989cDoug Thompson 143fd687502dc8037aa5a4b84c570ada971106574eeMauro Carvalho Chehab pdev = to_pci_dev(mci->pdev); 14437f04581abac20444e5b7106c1e1f28bec5b989cDoug Thompson pci_read_config_dword(pdev, R82600_EAP, &info->eapr); 1452f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox 1462f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox if (info->eapr & BIT(0)) 1472f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox /* Clear error to allow next error to be reported [p.62] */ 14837f04581abac20444e5b7106c1e1f28bec5b989cDoug Thompson pci_write_bits32(pdev, R82600_EAP, 149cddbfcacf02dc2d5b074fc2717358a7529a190dbDouglas Thompson ((u32) BIT(0) & (u32) BIT(1)), 150cddbfcacf02dc2d5b074fc2717358a7529a190dbDouglas Thompson ((u32) BIT(0) & (u32) BIT(1))); 1512f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox 1522f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox if (info->eapr & BIT(1)) 1532f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox /* Clear error to allow next error to be reported [p.62] */ 15437f04581abac20444e5b7106c1e1f28bec5b989cDoug Thompson pci_write_bits32(pdev, R82600_EAP, 155cddbfcacf02dc2d5b074fc2717358a7529a190dbDouglas Thompson ((u32) BIT(0) & (u32) BIT(1)), 156cddbfcacf02dc2d5b074fc2717358a7529a190dbDouglas Thompson ((u32) BIT(0) & (u32) BIT(1))); 1572f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox} 1582f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox 159cddbfcacf02dc2d5b074fc2717358a7529a190dbDouglas Thompsonstatic int r82600_process_error_info(struct mem_ctl_info *mci, 160052dfb45ccb5ea354a426b52556bcfee75b9d2f5Douglas Thompson struct r82600_error_info *info, 161052dfb45ccb5ea354a426b52556bcfee75b9d2f5Douglas Thompson int handle_errors) 1622f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox{ 1632f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox int error_found; 1642f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox u32 eapaddr, page; 1652f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox u32 syndrome; 1662f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox 1672f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox error_found = 0; 1682f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox 1692f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox /* bits 30:12 store the upper 19 bits of the 32 bit error address */ 1702f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox eapaddr = ((info->eapr >> 12) & 0x7FFF) << 13; 1712f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox /* Syndrome in bits 11:4 [p.62] */ 1722f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox syndrome = (info->eapr >> 4) & 0xFF; 1732f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox 1742f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox /* the R82600 reports at less than page * 1752f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox * granularity (upper 19 bits only) */ 1762f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox page = eapaddr >> PAGE_SHIFT; 1772f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox 178cddbfcacf02dc2d5b074fc2717358a7529a190dbDouglas Thompson if (info->eapr & BIT(0)) { /* CE? */ 1792f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox error_found = 1; 1802f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox 1812f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox if (handle_errors) 1829eb07a7fb8a90ee39fa9d5489afc0330cfcfbea7Mauro Carvalho Chehab edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, mci, 1, 18363b5d1d9aa4b59847ce6279b8798ed28c686a459Mauro Carvalho Chehab page, 0, syndrome, 18463b5d1d9aa4b59847ce6279b8798ed28c686a459Mauro Carvalho Chehab edac_mc_find_csrow_by_page(mci, page), 18563b5d1d9aa4b59847ce6279b8798ed28c686a459Mauro Carvalho Chehab 0, -1, 18603f7eae80f4b913929be84e0c883ee98196fd6ffMauro Carvalho Chehab mci->ctl_name, ""); 1872f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox } 1882f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox 189cddbfcacf02dc2d5b074fc2717358a7529a190dbDouglas Thompson if (info->eapr & BIT(1)) { /* UE? */ 1902f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox error_found = 1; 1912f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox 1922f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox if (handle_errors) 1932f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox /* 82600 doesn't give enough info */ 1949eb07a7fb8a90ee39fa9d5489afc0330cfcfbea7Mauro Carvalho Chehab edac_mc_handle_error(HW_EVENT_ERR_UNCORRECTED, mci, 1, 19563b5d1d9aa4b59847ce6279b8798ed28c686a459Mauro Carvalho Chehab page, 0, 0, 19663b5d1d9aa4b59847ce6279b8798ed28c686a459Mauro Carvalho Chehab edac_mc_find_csrow_by_page(mci, page), 19763b5d1d9aa4b59847ce6279b8798ed28c686a459Mauro Carvalho Chehab 0, -1, 19803f7eae80f4b913929be84e0c883ee98196fd6ffMauro Carvalho Chehab mci->ctl_name, ""); 1992f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox } 2002f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox 2012f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox return error_found; 2022f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox} 2032f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox 2042f768af73fea4c70f9046388a7ff648ad11f028eAlan Coxstatic void r82600_check(struct mem_ctl_info *mci) 2052f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox{ 2062f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox struct r82600_error_info info; 2072f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox 208956b9ba156dbfdb9cede2b2927ddf8be2233b3a7Joe Perches edac_dbg(1, "MC%d\n", mci->mc_idx); 2092f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox r82600_get_error_info(mci, &info); 2102f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox r82600_process_error_info(mci, &info, 1); 2112f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox} 2122f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox 2131318952514d5651c453d89989595a9df3b37267bDoug Thompsonstatic inline int ecc_enabled(u8 dramcr) 2142f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox{ 2151318952514d5651c453d89989595a9df3b37267bDoug Thompson return dramcr & BIT(5); 2161318952514d5651c453d89989595a9df3b37267bDoug Thompson} 2171318952514d5651c453d89989595a9df3b37267bDoug Thompson 2181318952514d5651c453d89989595a9df3b37267bDoug Thompsonstatic void r82600_init_csrows(struct mem_ctl_info *mci, struct pci_dev *pdev, 219052dfb45ccb5ea354a426b52556bcfee75b9d2f5Douglas Thompson u8 dramcr) 2201318952514d5651c453d89989595a9df3b37267bDoug Thompson{ 2211318952514d5651c453d89989595a9df3b37267bDoug Thompson struct csrow_info *csrow; 222084a4fccef39ac7abb039511f32380f28d0b67e6Mauro Carvalho Chehab struct dimm_info *dimm; 2232f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox int index; 22425985edcedea6396277003854657b5f3cb31a628Lucas De Marchi u8 drbar; /* SDRAM Row Boundary Address Register */ 2251318952514d5651c453d89989595a9df3b37267bDoug Thompson u32 row_high_limit, row_high_limit_last; 2261318952514d5651c453d89989595a9df3b37267bDoug Thompson u32 reg_sdram, ecc_on, row_base; 2271318952514d5651c453d89989595a9df3b37267bDoug Thompson 2281318952514d5651c453d89989595a9df3b37267bDoug Thompson ecc_on = ecc_enabled(dramcr); 2291318952514d5651c453d89989595a9df3b37267bDoug Thompson reg_sdram = dramcr & BIT(4); 2301318952514d5651c453d89989595a9df3b37267bDoug Thompson row_high_limit_last = 0; 2311318952514d5651c453d89989595a9df3b37267bDoug Thompson 2321318952514d5651c453d89989595a9df3b37267bDoug Thompson for (index = 0; index < mci->nr_csrows; index++) { 233de3910eb79ac8c0f29a11224661c0ebaaf813039Mauro Carvalho Chehab csrow = mci->csrows[index]; 234de3910eb79ac8c0f29a11224661c0ebaaf813039Mauro Carvalho Chehab dimm = csrow->channels[0]->dimm; 2351318952514d5651c453d89989595a9df3b37267bDoug Thompson 2361318952514d5651c453d89989595a9df3b37267bDoug Thompson /* find the DRAM Chip Select Base address and mask */ 2371318952514d5651c453d89989595a9df3b37267bDoug Thompson pci_read_config_byte(pdev, R82600_DRBA + index, &drbar); 2381318952514d5651c453d89989595a9df3b37267bDoug Thompson 239956b9ba156dbfdb9cede2b2927ddf8be2233b3a7Joe Perches edac_dbg(1, "Row=%d DRBA = %#0x\n", index, drbar); 2401318952514d5651c453d89989595a9df3b37267bDoug Thompson 2411318952514d5651c453d89989595a9df3b37267bDoug Thompson row_high_limit = ((u32) drbar << 24); 2421318952514d5651c453d89989595a9df3b37267bDoug Thompson/* row_high_limit = ((u32)drbar << 24) | 0xffffffUL; */ 2431318952514d5651c453d89989595a9df3b37267bDoug Thompson 244956b9ba156dbfdb9cede2b2927ddf8be2233b3a7Joe Perches edac_dbg(1, "Row=%d, Boundary Address=%#0x, Last = %#0x\n", 245956b9ba156dbfdb9cede2b2927ddf8be2233b3a7Joe Perches index, row_high_limit, row_high_limit_last); 2461318952514d5651c453d89989595a9df3b37267bDoug Thompson 2471318952514d5651c453d89989595a9df3b37267bDoug Thompson /* Empty row [p.57] */ 2481318952514d5651c453d89989595a9df3b37267bDoug Thompson if (row_high_limit == row_high_limit_last) 2491318952514d5651c453d89989595a9df3b37267bDoug Thompson continue; 2501318952514d5651c453d89989595a9df3b37267bDoug Thompson 2511318952514d5651c453d89989595a9df3b37267bDoug Thompson row_base = row_high_limit_last; 2521318952514d5651c453d89989595a9df3b37267bDoug Thompson 2531318952514d5651c453d89989595a9df3b37267bDoug Thompson csrow->first_page = row_base >> PAGE_SHIFT; 2541318952514d5651c453d89989595a9df3b37267bDoug Thompson csrow->last_page = (row_high_limit >> PAGE_SHIFT) - 1; 255a895bf8b1e1ea4c032a8fa8a09475a2ce09fe77aMauro Carvalho Chehab 256a895bf8b1e1ea4c032a8fa8a09475a2ce09fe77aMauro Carvalho Chehab dimm->nr_pages = csrow->last_page - csrow->first_page + 1; 2571318952514d5651c453d89989595a9df3b37267bDoug Thompson /* Error address is top 19 bits - so granularity is * 2581318952514d5651c453d89989595a9df3b37267bDoug Thompson * 14 bits */ 259084a4fccef39ac7abb039511f32380f28d0b67e6Mauro Carvalho Chehab dimm->grain = 1 << 14; 260084a4fccef39ac7abb039511f32380f28d0b67e6Mauro Carvalho Chehab dimm->mtype = reg_sdram ? MEM_RDDR : MEM_DDR; 2611318952514d5651c453d89989595a9df3b37267bDoug Thompson /* FIXME - check that this is unknowable with this chipset */ 262084a4fccef39ac7abb039511f32380f28d0b67e6Mauro Carvalho Chehab dimm->dtype = DEV_UNKNOWN; 2631318952514d5651c453d89989595a9df3b37267bDoug Thompson 2641318952514d5651c453d89989595a9df3b37267bDoug Thompson /* Mode is global on 82600 */ 265084a4fccef39ac7abb039511f32380f28d0b67e6Mauro Carvalho Chehab dimm->edac_mode = ecc_on ? EDAC_SECDED : EDAC_NONE; 2661318952514d5651c453d89989595a9df3b37267bDoug Thompson row_high_limit_last = row_high_limit; 2671318952514d5651c453d89989595a9df3b37267bDoug Thompson } 2681318952514d5651c453d89989595a9df3b37267bDoug Thompson} 2691318952514d5651c453d89989595a9df3b37267bDoug Thompson 2701318952514d5651c453d89989595a9df3b37267bDoug Thompsonstatic int r82600_probe1(struct pci_dev *pdev, int dev_idx) 2711318952514d5651c453d89989595a9df3b37267bDoug Thompson{ 2721318952514d5651c453d89989595a9df3b37267bDoug Thompson struct mem_ctl_info *mci; 27363b5d1d9aa4b59847ce6279b8798ed28c686a459Mauro Carvalho Chehab struct edac_mc_layer layers[2]; 2742f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox u8 dramcr; 2752f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox u32 eapr; 2762f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox u32 scrub_disabled; 2772f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox u32 sdram_refresh_rate; 278749ede57443b2a7ede2db105145f21047efcea6aDave Peterson struct r82600_error_info discard; 2792f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox 280956b9ba156dbfdb9cede2b2927ddf8be2233b3a7Joe Perches edac_dbg(0, "\n"); 2812f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox pci_read_config_byte(pdev, R82600_DRAMC, &dramcr); 2822f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox pci_read_config_dword(pdev, R82600_EAP, &eapr); 2832f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox scrub_disabled = eapr & BIT(31); 2842f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox sdram_refresh_rate = dramcr & (BIT(0) | BIT(1)); 285956b9ba156dbfdb9cede2b2927ddf8be2233b3a7Joe Perches edac_dbg(2, "sdram refresh rate = %#0x\n", sdram_refresh_rate); 286956b9ba156dbfdb9cede2b2927ddf8be2233b3a7Joe Perches edac_dbg(2, "DRAMC register = %#0x\n", dramcr); 28763b5d1d9aa4b59847ce6279b8798ed28c686a459Mauro Carvalho Chehab layers[0].type = EDAC_MC_LAYER_CHIP_SELECT; 28863b5d1d9aa4b59847ce6279b8798ed28c686a459Mauro Carvalho Chehab layers[0].size = R82600_NR_CSROWS; 28963b5d1d9aa4b59847ce6279b8798ed28c686a459Mauro Carvalho Chehab layers[0].is_virt_csrow = true; 29063b5d1d9aa4b59847ce6279b8798ed28c686a459Mauro Carvalho Chehab layers[1].type = EDAC_MC_LAYER_CHANNEL; 29163b5d1d9aa4b59847ce6279b8798ed28c686a459Mauro Carvalho Chehab layers[1].size = R82600_NR_CHANS; 29263b5d1d9aa4b59847ce6279b8798ed28c686a459Mauro Carvalho Chehab layers[1].is_virt_csrow = false; 293ca0907b9e413bb1d1f3ea123b663535b74928846Mauro Carvalho Chehab mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers, 0); 2941318952514d5651c453d89989595a9df3b37267bDoug Thompson if (mci == NULL) 2951318952514d5651c453d89989595a9df3b37267bDoug Thompson return -ENOMEM; 2962f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox 297956b9ba156dbfdb9cede2b2927ddf8be2233b3a7Joe Perches edac_dbg(0, "mci = %p\n", mci); 298fd687502dc8037aa5a4b84c570ada971106574eeMauro Carvalho Chehab mci->pdev = &pdev->dev; 2992f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox mci->mtype_cap = MEM_FLAG_RDDR | MEM_FLAG_DDR; 3002f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox mci->edac_ctl_cap = EDAC_FLAG_NONE | EDAC_FLAG_EC | EDAC_FLAG_SECDED; 301e7ecd8910293564d357dbaf18eb179e06fa35fd0Dave Peterson /* FIXME try to work out if the chip leads have been used for COM2 302e7ecd8910293564d357dbaf18eb179e06fa35fd0Dave Peterson * instead on this board? [MA6?] MAYBE: 303e7ecd8910293564d357dbaf18eb179e06fa35fd0Dave Peterson */ 3042f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox 3052f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox /* On the R82600, the pins for memory bits 72:65 - i.e. the * 3062f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox * EC bits are shared with the pins for COM2 (!), so if COM2 * 3072f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox * is enabled, we assume COM2 is wired up, and thus no EDAC * 3082f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox * is possible. */ 3092f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox mci->edac_cap = EDAC_FLAG_NONE | EDAC_FLAG_EC | EDAC_FLAG_SECDED; 310e7ecd8910293564d357dbaf18eb179e06fa35fd0Dave Peterson 3111318952514d5651c453d89989595a9df3b37267bDoug Thompson if (ecc_enabled(dramcr)) { 3122f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox if (scrub_disabled) 313956b9ba156dbfdb9cede2b2927ddf8be2233b3a7Joe Perches edac_dbg(3, "mci = %p - Scrubbing disabled! EAP: %#0x\n", 314956b9ba156dbfdb9cede2b2927ddf8be2233b3a7Joe Perches mci, eapr); 3152f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox } else 3162f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox mci->edac_cap = EDAC_FLAG_NONE; 3172f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox 318680cbbbb0e336b04b74be48b8ddd870537f1e226Dave Peterson mci->mod_name = EDAC_MOD_STR; 31937f04581abac20444e5b7106c1e1f28bec5b989cDoug Thompson mci->mod_ver = R82600_REVISION; 3202f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox mci->ctl_name = "R82600"; 321c4192705fec85219086231a1c0fa61e8776e2c3bDave Jiang mci->dev_name = pci_name(pdev); 3222f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox mci->edac_check = r82600_check; 3232f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox mci->ctl_page_to_phys = NULL; 3241318952514d5651c453d89989595a9df3b37267bDoug Thompson r82600_init_csrows(mci, pdev, dramcr); 325cddbfcacf02dc2d5b074fc2717358a7529a190dbDouglas Thompson r82600_get_error_info(mci, &discard); /* clear counters */ 3262f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox 3272d7bbb91c8df26c60d223205a087507430024177Doug Thompson /* Here we assume that we will never see multiple instances of this 3282d7bbb91c8df26c60d223205a087507430024177Doug Thompson * type of memory controller. The ID is therefore hardcoded to 0. 3292d7bbb91c8df26c60d223205a087507430024177Doug Thompson */ 330b8f6f9755248026f21282e25cac49a1af698056cDoug Thompson if (edac_mc_add_mc(mci)) { 331956b9ba156dbfdb9cede2b2927ddf8be2233b3a7Joe Perches edac_dbg(3, "failed edac_mc_add_mc()\n"); 3322f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox goto fail; 3332f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox } 3342f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox 3352f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox /* get this far and it's successful */ 3362f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox 3372f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox if (disable_hardware_scrub) { 338956b9ba156dbfdb9cede2b2927ddf8be2233b3a7Joe Perches edac_dbg(3, "Disabling Hardware Scrub (scrub on error)\n"); 33937f04581abac20444e5b7106c1e1f28bec5b989cDoug Thompson pci_write_bits32(pdev, R82600_EAP, BIT(31), BIT(31)); 3402f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox } 3412f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox 342456a2f9552e7849475f4aea1a9aa4c0e54b3dddaDave Jiang /* allocating generic PCI control info */ 343456a2f9552e7849475f4aea1a9aa4c0e54b3dddaDave Jiang r82600_pci = edac_pci_create_generic_ctl(&pdev->dev, EDAC_MOD_STR); 344456a2f9552e7849475f4aea1a9aa4c0e54b3dddaDave Jiang if (!r82600_pci) { 345456a2f9552e7849475f4aea1a9aa4c0e54b3dddaDave Jiang printk(KERN_WARNING 346456a2f9552e7849475f4aea1a9aa4c0e54b3dddaDave Jiang "%s(): Unable to create PCI control\n", 347456a2f9552e7849475f4aea1a9aa4c0e54b3dddaDave Jiang __func__); 348456a2f9552e7849475f4aea1a9aa4c0e54b3dddaDave Jiang printk(KERN_WARNING 349456a2f9552e7849475f4aea1a9aa4c0e54b3dddaDave Jiang "%s(): PCI error report via EDAC not setup\n", 350456a2f9552e7849475f4aea1a9aa4c0e54b3dddaDave Jiang __func__); 351456a2f9552e7849475f4aea1a9aa4c0e54b3dddaDave Jiang } 352456a2f9552e7849475f4aea1a9aa4c0e54b3dddaDave Jiang 353956b9ba156dbfdb9cede2b2927ddf8be2233b3a7Joe Perches edac_dbg(3, "success\n"); 3542f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox return 0; 3552f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox 356052dfb45ccb5ea354a426b52556bcfee75b9d2f5Douglas Thompsonfail: 3571318952514d5651c453d89989595a9df3b37267bDoug Thompson edac_mc_free(mci); 3581318952514d5651c453d89989595a9df3b37267bDoug Thompson return -ENODEV; 3592f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox} 3602f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox 3612f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox/* returns count (>= 0), or negative on error */ 3629b3c6e85c2cfa731cf67d5a8c49f7d8c60ec0b04Greg Kroah-Hartmanstatic int r82600_init_one(struct pci_dev *pdev, 3639b3c6e85c2cfa731cf67d5a8c49f7d8c60ec0b04Greg Kroah-Hartman const struct pci_device_id *ent) 3642f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox{ 365956b9ba156dbfdb9cede2b2927ddf8be2233b3a7Joe Perches edac_dbg(0, "\n"); 3662f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox 367ee6583f6e8f8dad4a53985dbabcd7c242d66a6b6Roman Fietze /* don't need to call pci_enable_device() */ 3682f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox return r82600_probe1(pdev, ent->driver_data); 3692f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox} 3702f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox 3719b3c6e85c2cfa731cf67d5a8c49f7d8c60ec0b04Greg Kroah-Hartmanstatic void r82600_remove_one(struct pci_dev *pdev) 3722f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox{ 3732f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox struct mem_ctl_info *mci; 3742f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox 375956b9ba156dbfdb9cede2b2927ddf8be2233b3a7Joe Perches edac_dbg(0, "\n"); 3762f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox 377456a2f9552e7849475f4aea1a9aa4c0e54b3dddaDave Jiang if (r82600_pci) 378456a2f9552e7849475f4aea1a9aa4c0e54b3dddaDave Jiang edac_pci_release_generic_ctl(r82600_pci); 379456a2f9552e7849475f4aea1a9aa4c0e54b3dddaDave Jiang 38037f04581abac20444e5b7106c1e1f28bec5b989cDoug Thompson if ((mci = edac_mc_del_mc(&pdev->dev)) == NULL) 38118dbc337af5d6efd30cb9291e74722c8ad134fd3Dave Peterson return; 38218dbc337af5d6efd30cb9291e74722c8ad134fd3Dave Peterson 38318dbc337af5d6efd30cb9291e74722c8ad134fd3Dave Peterson edac_mc_free(mci); 3842f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox} 3852f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox 386ba935f40979b32924824759111ed95d35469c5faJingoo Hanstatic const struct pci_device_id r82600_pci_tbl[] = { 387e7ecd8910293564d357dbaf18eb179e06fa35fd0Dave Peterson { 388cddbfcacf02dc2d5b074fc2717358a7529a190dbDouglas Thompson PCI_DEVICE(PCI_VENDOR_ID_RADISYS, R82600_BRIDGE_ID) 389cddbfcacf02dc2d5b074fc2717358a7529a190dbDouglas Thompson }, 390e7ecd8910293564d357dbaf18eb179e06fa35fd0Dave Peterson { 391cddbfcacf02dc2d5b074fc2717358a7529a190dbDouglas Thompson 0, 392cddbfcacf02dc2d5b074fc2717358a7529a190dbDouglas Thompson } /* 0 terminated list. */ 3932f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox}; 3942f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox 3952f768af73fea4c70f9046388a7ff648ad11f028eAlan CoxMODULE_DEVICE_TABLE(pci, r82600_pci_tbl); 3962f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox 3972f768af73fea4c70f9046388a7ff648ad11f028eAlan Coxstatic struct pci_driver r82600_driver = { 398680cbbbb0e336b04b74be48b8ddd870537f1e226Dave Peterson .name = EDAC_MOD_STR, 3992f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox .probe = r82600_init_one, 4009b3c6e85c2cfa731cf67d5a8c49f7d8c60ec0b04Greg Kroah-Hartman .remove = r82600_remove_one, 4012f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox .id_table = r82600_pci_tbl, 4022f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox}; 4032f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox 404da9bb1d27b21cb24cbb6a2efb5d3c464d357a01eAlan Coxstatic int __init r82600_init(void) 4052f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox{ 406c3c52bce6993c6d37af2c2de9b482a7013d646a7Hitoshi Mitake /* Ensure that the OPSTATE is set correctly for POLL or NMI */ 407c3c52bce6993c6d37af2c2de9b482a7013d646a7Hitoshi Mitake opstate_init(); 408c3c52bce6993c6d37af2c2de9b482a7013d646a7Hitoshi Mitake 4092f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox return pci_register_driver(&r82600_driver); 4102f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox} 4112f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox 4122f768af73fea4c70f9046388a7ff648ad11f028eAlan Coxstatic void __exit r82600_exit(void) 4132f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox{ 4142f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox pci_unregister_driver(&r82600_driver); 4152f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox} 4162f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox 4172f768af73fea4c70f9046388a7ff648ad11f028eAlan Coxmodule_init(r82600_init); 4182f768af73fea4c70f9046388a7ff648ad11f028eAlan Coxmodule_exit(r82600_exit); 4192f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox 4202f768af73fea4c70f9046388a7ff648ad11f028eAlan CoxMODULE_LICENSE("GPL"); 4212f768af73fea4c70f9046388a7ff648ad11f028eAlan CoxMODULE_AUTHOR("Tim Small <tim@buttersideup.com> - WPAD Ltd. " 422052dfb45ccb5ea354a426b52556bcfee75b9d2f5Douglas Thompson "on behalf of EADS Astrium"); 4232f768af73fea4c70f9046388a7ff648ad11f028eAlan CoxMODULE_DESCRIPTION("MC support for Radisys 82600 memory controllers"); 4242f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox 4252f768af73fea4c70f9046388a7ff648ad11f028eAlan Coxmodule_param(disable_hardware_scrub, bool, 0644); 4262f768af73fea4c70f9046388a7ff648ad11f028eAlan CoxMODULE_PARM_DESC(disable_hardware_scrub, 4272f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox "If set, disable the chipset's automatic scrub for CEs"); 428c3c52bce6993c6d37af2c2de9b482a7013d646a7Hitoshi Mitake 429c3c52bce6993c6d37af2c2de9b482a7013d646a7Hitoshi Mitakemodule_param(edac_op_state, int, 0444); 430c3c52bce6993c6d37af2c2de9b482a7013d646a7Hitoshi MitakeMODULE_PARM_DESC(edac_op_state, "EDAC Error Reporting state: 0=Poll,1=NMI"); 431