r82600_edac.c revision 680cbbbb0e336b04b74be48b8ddd870537f1e226
12f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox/* 22f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox * Radisys 82600 Embedded chipset Memory Controller kernel module 32f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox * (C) 2005 EADS Astrium 42f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox * This file may be distributed under the terms of the 52f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox * GNU General Public License. 62f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox * 72f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox * Written by Tim Small <tim@buttersideup.com>, based on work by Thayne 82f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox * Harbaugh, Dan Hollis <goemon at anime dot net> and others. 92f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox * 102f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox * $Id: edac_r82600.c,v 1.1.2.6 2005/10/05 00:43:44 dsp_llnl Exp $ 112f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox * 122f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox * Written with reference to 82600 High Integration Dual PCI System 132f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox * Controller Data Book: 142f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox * http://www.radisys.com/files/support_downloads/007-01277-0002.82600DataBook.pdf 152f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox * references to this document given in [] 162f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox */ 172f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox 182f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox#include <linux/config.h> 192f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox#include <linux/module.h> 202f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox#include <linux/init.h> 212f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox 222f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox#include <linux/pci.h> 232f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox#include <linux/pci_ids.h> 242f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox 252f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox#include <linux/slab.h> 262f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox 272f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox#include "edac_mc.h" 282f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox 29537fba28928c01b7db1580627450691a4bb0b9b3Dave Peterson#define r82600_printk(level, fmt, arg...) \ 30537fba28928c01b7db1580627450691a4bb0b9b3Dave Peterson edac_printk(level, "r82600", fmt, ##arg) 31537fba28928c01b7db1580627450691a4bb0b9b3Dave Peterson 32537fba28928c01b7db1580627450691a4bb0b9b3Dave Peterson#define r82600_mc_printk(mci, level, fmt, arg...) \ 33537fba28928c01b7db1580627450691a4bb0b9b3Dave Peterson edac_mc_chipset_printk(mci, level, "r82600", fmt, ##arg) 34537fba28928c01b7db1580627450691a4bb0b9b3Dave Peterson 352f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox/* Radisys say "The 82600 integrates a main memory SDRAM controller that 362f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox * supports up to four banks of memory. The four banks can support a mix of 372f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox * sizes of 64 bit wide (72 bits with ECC) Synchronous DRAM (SDRAM) DIMMs, 382f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox * each of which can be any size from 16MB to 512MB. Both registered (control 392f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox * signals buffered) and unbuffered DIMM types are supported. Mixing of 402f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox * registered and unbuffered DIMMs as well as mixing of ECC and non-ECC DIMMs 412f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox * is not allowed. The 82600 SDRAM interface operates at the same frequency as 422f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox * the CPU bus, 66MHz, 100MHz or 133MHz." 432f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox */ 442f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox 452f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox#define R82600_NR_CSROWS 4 462f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox#define R82600_NR_CHANS 1 472f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox#define R82600_NR_DIMMS 4 482f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox 492f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox#define R82600_BRIDGE_ID 0x8200 502f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox 512f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox/* Radisys 82600 register addresses - device 0 function 0 - PCI bridge */ 522f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox#define R82600_DRAMC 0x57 /* Various SDRAM related control bits 532f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox * all bits are R/W 542f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox * 552f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox * 7 SDRAM ISA Hole Enable 562f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox * 6 Flash Page Mode Enable 572f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox * 5 ECC Enable: 1=ECC 0=noECC 582f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox * 4 DRAM DIMM Type: 1= 592f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox * 3 BIOS Alias Disable 602f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox * 2 SDRAM BIOS Flash Write Enable 612f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox * 1:0 SDRAM Refresh Rate: 00=Disabled 622f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox * 01=7.8usec (256Mbit SDRAMs) 632f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox * 10=15.6us 11=125usec 642f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox */ 652f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox 662f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox#define R82600_SDRAMC 0x76 /* "SDRAM Control Register" 672f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox * More SDRAM related control bits 682f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox * all bits are R/W 692f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox * 702f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox * 15:8 Reserved. 712f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox * 722f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox * 7:5 Special SDRAM Mode Select 732f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox * 742f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox * 4 Force ECC 752f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox * 762f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox * 1=Drive ECC bits to 0 during 772f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox * write cycles (i.e. ECC test mode) 782f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox * 792f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox * 0=Normal ECC functioning 802f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox * 812f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox * 3 Enhanced Paging Enable 822f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox * 832f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox * 2 CAS# Latency 0=3clks 1=2clks 842f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox * 852f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox * 1 RAS# to CAS# Delay 0=3 1=2 862f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox * 872f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox * 0 RAS# Precharge 0=3 1=2 882f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox */ 892f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox 902f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox#define R82600_EAP 0x80 /* ECC Error Address Pointer Register 912f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox * 922f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox * 31 Disable Hardware Scrubbing (RW) 932f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox * 0=Scrub on corrected read 942f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox * 1=Don't scrub on corrected read 952f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox * 962f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox * 30:12 Error Address Pointer (RO) 972f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox * Upper 19 bits of error address 982f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox * 992f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox * 11:4 Syndrome Bits (RO) 1002f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox * 1012f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox * 3 BSERR# on multibit error (RW) 1022f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox * 1=enable 0=disable 1032f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox * 1042f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox * 2 NMI on Single Bit Eror (RW) 1052f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox * 1=NMI triggered by SBE n.b. other 1062f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox * prerequeists 1072f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox * 0=NMI not triggered 1082f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox * 1092f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox * 1 MBE (R/WC) 1102f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox * read 1=MBE at EAP (see above) 1112f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox * read 0=no MBE, or SBE occurred first 1122f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox * write 1=Clear MBE status (must also 1132f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox * clear SBE) 1142f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox * write 0=NOP 1152f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox * 1162f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox * 1 SBE (R/WC) 1172f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox * read 1=SBE at EAP (see above) 1182f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox * read 0=no SBE, or MBE occurred first 1192f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox * write 1=Clear SBE status (must also 1202f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox * clear MBE) 1212f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox * write 0=NOP 1222f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox */ 1232f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox 1242f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox#define R82600_DRBA 0x60 /* + 0x60..0x63 SDRAM Row Boundry Address 1252f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox * Registers 1262f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox * 1272f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox * 7:0 Address lines 30:24 - upper limit of 1282f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox * each row [p57] 1292f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox */ 1302f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox 1312f768af73fea4c70f9046388a7ff648ad11f028eAlan Coxstruct r82600_error_info { 1322f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox u32 eapr; 1332f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox}; 1342f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox 1352f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox 1362f768af73fea4c70f9046388a7ff648ad11f028eAlan Coxstatic unsigned int disable_hardware_scrub = 0; 1372f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox 1382f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox 1392f768af73fea4c70f9046388a7ff648ad11f028eAlan Coxstatic void r82600_get_error_info (struct mem_ctl_info *mci, 1402f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox struct r82600_error_info *info) 1412f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox{ 1422f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox pci_read_config_dword(mci->pdev, R82600_EAP, &info->eapr); 1432f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox 1442f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox if (info->eapr & BIT(0)) 1452f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox /* Clear error to allow next error to be reported [p.62] */ 1462f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox pci_write_bits32(mci->pdev, R82600_EAP, 1472f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox ((u32) BIT(0) & (u32) BIT(1)), 1482f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox ((u32) BIT(0) & (u32) BIT(1))); 1492f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox 1502f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox if (info->eapr & BIT(1)) 1512f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox /* Clear error to allow next error to be reported [p.62] */ 1522f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox pci_write_bits32(mci->pdev, R82600_EAP, 1532f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox ((u32) BIT(0) & (u32) BIT(1)), 1542f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox ((u32) BIT(0) & (u32) BIT(1))); 1552f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox} 1562f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox 1572f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox 1582f768af73fea4c70f9046388a7ff648ad11f028eAlan Coxstatic int r82600_process_error_info (struct mem_ctl_info *mci, 1592f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox struct r82600_error_info *info, int handle_errors) 1602f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox{ 1612f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox int error_found; 1622f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox u32 eapaddr, page; 1632f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox u32 syndrome; 1642f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox 1652f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox error_found = 0; 1662f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox 1672f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox /* bits 30:12 store the upper 19 bits of the 32 bit error address */ 1682f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox eapaddr = ((info->eapr >> 12) & 0x7FFF) << 13; 1692f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox /* Syndrome in bits 11:4 [p.62] */ 1702f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox syndrome = (info->eapr >> 4) & 0xFF; 1712f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox 1722f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox /* the R82600 reports at less than page * 1732f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox * granularity (upper 19 bits only) */ 1742f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox page = eapaddr >> PAGE_SHIFT; 1752f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox 1762f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox if (info->eapr & BIT(0)) { /* CE? */ 1772f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox error_found = 1; 1782f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox 1792f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox if (handle_errors) 1802f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox edac_mc_handle_ce( 1812f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox mci, page, 0, /* not avail */ 1822f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox syndrome, 1832f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox edac_mc_find_csrow_by_page(mci, page), 1842f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox 0, /* channel */ 1852f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox mci->ctl_name); 1862f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox } 1872f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox 1882f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox if (info->eapr & BIT(1)) { /* UE? */ 1892f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox error_found = 1; 1902f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox 1912f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox if (handle_errors) 1922f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox /* 82600 doesn't give enough info */ 1932f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox edac_mc_handle_ue(mci, page, 0, 1942f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox edac_mc_find_csrow_by_page(mci, page), 1952f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox mci->ctl_name); 1962f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox } 1972f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox 1982f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox return error_found; 1992f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox} 2002f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox 2012f768af73fea4c70f9046388a7ff648ad11f028eAlan Coxstatic void r82600_check(struct mem_ctl_info *mci) 2022f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox{ 2032f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox struct r82600_error_info info; 2042f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox 205537fba28928c01b7db1580627450691a4bb0b9b3Dave Peterson debugf1("MC%d: %s()\n", mci->mc_idx, __func__); 2062f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox r82600_get_error_info(mci, &info); 2072f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox r82600_process_error_info(mci, &info, 1); 2082f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox} 2092f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox 2102f768af73fea4c70f9046388a7ff648ad11f028eAlan Coxstatic int r82600_probe1(struct pci_dev *pdev, int dev_idx) 2112f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox{ 2122f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox int rc = -ENODEV; 2132f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox int index; 2142f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox struct mem_ctl_info *mci = NULL; 2152f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox u8 dramcr; 2162f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox u32 ecc_on; 2172f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox u32 reg_sdram; 2182f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox u32 eapr; 2192f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox u32 scrub_disabled; 2202f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox u32 sdram_refresh_rate; 2212f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox u32 row_high_limit_last = 0; 2222f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox u32 eap_init_bits; 2232f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox 224537fba28928c01b7db1580627450691a4bb0b9b3Dave Peterson debugf0("%s()\n", __func__); 2252f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox 2262f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox 2272f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox pci_read_config_byte(pdev, R82600_DRAMC, &dramcr); 2282f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox pci_read_config_dword(pdev, R82600_EAP, &eapr); 2292f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox 2302f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox ecc_on = dramcr & BIT(5); 2312f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox reg_sdram = dramcr & BIT(4); 2322f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox scrub_disabled = eapr & BIT(31); 2332f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox sdram_refresh_rate = dramcr & (BIT(0) | BIT(1)); 2342f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox 235537fba28928c01b7db1580627450691a4bb0b9b3Dave Peterson debugf2("%s(): sdram refresh rate = %#0x\n", __func__, 236537fba28928c01b7db1580627450691a4bb0b9b3Dave Peterson sdram_refresh_rate); 2372f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox 238537fba28928c01b7db1580627450691a4bb0b9b3Dave Peterson debugf2("%s(): DRAMC register = %#0x\n", __func__, dramcr); 2392f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox 2402f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox mci = edac_mc_alloc(0, R82600_NR_CSROWS, R82600_NR_CHANS); 2412f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox 2422f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox if (mci == NULL) { 2432f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox rc = -ENOMEM; 2442f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox goto fail; 2452f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox } 2462f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox 247537fba28928c01b7db1580627450691a4bb0b9b3Dave Peterson debugf0("%s(): mci = %p\n", __func__, mci); 2482f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox 2492f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox mci->pdev = pdev; 2502f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox mci->mtype_cap = MEM_FLAG_RDDR | MEM_FLAG_DDR; 2512f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox 2522f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox mci->edac_ctl_cap = EDAC_FLAG_NONE | EDAC_FLAG_EC | EDAC_FLAG_SECDED; 2532f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox /* FIXME try to work out if the chip leads have been * 2542f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox * used for COM2 instead on this board? [MA6?] MAYBE: */ 2552f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox 2562f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox /* On the R82600, the pins for memory bits 72:65 - i.e. the * 2572f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox * EC bits are shared with the pins for COM2 (!), so if COM2 * 2582f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox * is enabled, we assume COM2 is wired up, and thus no EDAC * 2592f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox * is possible. */ 2602f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox mci->edac_cap = EDAC_FLAG_NONE | EDAC_FLAG_EC | EDAC_FLAG_SECDED; 2612f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox if (ecc_on) { 2622f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox if (scrub_disabled) 263537fba28928c01b7db1580627450691a4bb0b9b3Dave Peterson debugf3("%s(): mci = %p - Scrubbing disabled! EAP: " 264537fba28928c01b7db1580627450691a4bb0b9b3Dave Peterson "%#0x\n", __func__, mci, eapr); 2652f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox } else 2662f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox mci->edac_cap = EDAC_FLAG_NONE; 2672f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox 268680cbbbb0e336b04b74be48b8ddd870537f1e226Dave Peterson mci->mod_name = EDAC_MOD_STR; 2692f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox mci->mod_ver = "$Revision: 1.1.2.6 $"; 2702f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox mci->ctl_name = "R82600"; 2712f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox mci->edac_check = r82600_check; 2722f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox mci->ctl_page_to_phys = NULL; 2732f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox 2742f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox for (index = 0; index < mci->nr_csrows; index++) { 2752f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox struct csrow_info *csrow = &mci->csrows[index]; 2762f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox u8 drbar; /* sDram Row Boundry Address Register */ 2772f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox u32 row_high_limit; 2782f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox u32 row_base; 2792f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox 2802f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox /* find the DRAM Chip Select Base address and mask */ 2812f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox pci_read_config_byte(mci->pdev, R82600_DRBA + index, &drbar); 2822f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox 283537fba28928c01b7db1580627450691a4bb0b9b3Dave Peterson debugf1("MC%d: %s() Row=%d DRBA = %#0x\n", mci->mc_idx, 284537fba28928c01b7db1580627450691a4bb0b9b3Dave Peterson __func__, index, drbar); 2852f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox 2862f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox row_high_limit = ((u32) drbar << 24); 2872f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox/* row_high_limit = ((u32)drbar << 24) | 0xffffffUL; */ 2882f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox 289537fba28928c01b7db1580627450691a4bb0b9b3Dave Peterson debugf1("MC%d: %s() Row=%d, Boundry Address=%#0x, Last = " 290537fba28928c01b7db1580627450691a4bb0b9b3Dave Peterson "%#0x \n", mci->mc_idx, __func__, index, 291537fba28928c01b7db1580627450691a4bb0b9b3Dave Peterson row_high_limit, row_high_limit_last); 2922f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox 2932f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox /* Empty row [p.57] */ 2942f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox if (row_high_limit == row_high_limit_last) 2952f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox continue; 2962f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox 2972f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox row_base = row_high_limit_last; 2982f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox 2992f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox csrow->first_page = row_base >> PAGE_SHIFT; 3002f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox csrow->last_page = (row_high_limit >> PAGE_SHIFT) - 1; 3012f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox csrow->nr_pages = csrow->last_page - csrow->first_page + 1; 3022f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox /* Error address is top 19 bits - so granularity is * 3032f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox * 14 bits */ 3042f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox csrow->grain = 1 << 14; 3052f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox csrow->mtype = reg_sdram ? MEM_RDDR : MEM_DDR; 3062f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox /* FIXME - check that this is unknowable with this chipset */ 3072f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox csrow->dtype = DEV_UNKNOWN; 3082f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox 3092f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox /* Mode is global on 82600 */ 3102f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox csrow->edac_mode = ecc_on ? EDAC_SECDED : EDAC_NONE; 3112f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox row_high_limit_last = row_high_limit; 3122f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox } 3132f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox 3142f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox /* clear counters */ 3152f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox /* FIXME should we? */ 3162f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox 3172f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox if (edac_mc_add_mc(mci)) { 318537fba28928c01b7db1580627450691a4bb0b9b3Dave Peterson debugf3("%s(): failed edac_mc_add_mc()\n", __func__); 3192f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox goto fail; 3202f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox } 3212f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox 3222f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox /* get this far and it's successful */ 3232f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox 3242f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox /* Clear error flags to allow next error to be reported [p.62] */ 3252f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox /* Test systems seem to always have the UE flag raised on boot */ 3262f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox 3272f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox eap_init_bits = BIT(0) & BIT(1); 3282f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox if (disable_hardware_scrub) { 3292f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox eap_init_bits |= BIT(31); 330537fba28928c01b7db1580627450691a4bb0b9b3Dave Peterson debugf3("%s(): Disabling Hardware Scrub (scrub on error)\n", 331537fba28928c01b7db1580627450691a4bb0b9b3Dave Peterson __func__); 3322f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox } 3332f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox 3342f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox pci_write_bits32(mci->pdev, R82600_EAP, eap_init_bits, 3352f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox eap_init_bits); 3362f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox 337537fba28928c01b7db1580627450691a4bb0b9b3Dave Peterson debugf3("%s(): success\n", __func__); 3382f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox return 0; 3392f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox 3402f768af73fea4c70f9046388a7ff648ad11f028eAlan Coxfail: 3412f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox if (mci) 3422f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox edac_mc_free(mci); 3432f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox 3442f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox return rc; 3452f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox} 3462f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox 3472f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox/* returns count (>= 0), or negative on error */ 3482f768af73fea4c70f9046388a7ff648ad11f028eAlan Coxstatic int __devinit r82600_init_one(struct pci_dev *pdev, 3492f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox const struct pci_device_id *ent) 3502f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox{ 351537fba28928c01b7db1580627450691a4bb0b9b3Dave Peterson debugf0("%s()\n", __func__); 3522f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox 3532f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox /* don't need to call pci_device_enable() */ 3542f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox return r82600_probe1(pdev, ent->driver_data); 3552f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox} 3562f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox 3572f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox 3582f768af73fea4c70f9046388a7ff648ad11f028eAlan Coxstatic void __devexit r82600_remove_one(struct pci_dev *pdev) 3592f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox{ 3602f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox struct mem_ctl_info *mci; 3612f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox 362537fba28928c01b7db1580627450691a4bb0b9b3Dave Peterson debugf0("%s()\n", __func__); 3632f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox 3642f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox if (((mci = edac_mc_find_mci_by_pdev(pdev)) != NULL) && 3652f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox !edac_mc_del_mc(mci)) 3662f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox edac_mc_free(mci); 3672f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox} 3682f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox 3692f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox 3702f768af73fea4c70f9046388a7ff648ad11f028eAlan Coxstatic const struct pci_device_id r82600_pci_tbl[] __devinitdata = { 3712f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox {PCI_DEVICE(PCI_VENDOR_ID_RADISYS, R82600_BRIDGE_ID)}, 3722f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox {0,} /* 0 terminated list. */ 3732f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox}; 3742f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox 3752f768af73fea4c70f9046388a7ff648ad11f028eAlan CoxMODULE_DEVICE_TABLE(pci, r82600_pci_tbl); 3762f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox 3772f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox 3782f768af73fea4c70f9046388a7ff648ad11f028eAlan Coxstatic struct pci_driver r82600_driver = { 379680cbbbb0e336b04b74be48b8ddd870537f1e226Dave Peterson .name = EDAC_MOD_STR, 3802f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox .probe = r82600_init_one, 3812f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox .remove = __devexit_p(r82600_remove_one), 3822f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox .id_table = r82600_pci_tbl, 3832f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox}; 3842f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox 3852f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox 386da9bb1d27b21cb24cbb6a2efb5d3c464d357a01eAlan Coxstatic int __init r82600_init(void) 3872f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox{ 3882f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox return pci_register_driver(&r82600_driver); 3892f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox} 3902f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox 3912f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox 3922f768af73fea4c70f9046388a7ff648ad11f028eAlan Coxstatic void __exit r82600_exit(void) 3932f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox{ 3942f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox pci_unregister_driver(&r82600_driver); 3952f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox} 3962f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox 3972f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox 3982f768af73fea4c70f9046388a7ff648ad11f028eAlan Coxmodule_init(r82600_init); 3992f768af73fea4c70f9046388a7ff648ad11f028eAlan Coxmodule_exit(r82600_exit); 4002f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox 4012f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox 4022f768af73fea4c70f9046388a7ff648ad11f028eAlan CoxMODULE_LICENSE("GPL"); 4032f768af73fea4c70f9046388a7ff648ad11f028eAlan CoxMODULE_AUTHOR("Tim Small <tim@buttersideup.com> - WPAD Ltd. " 4042f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox "on behalf of EADS Astrium"); 4052f768af73fea4c70f9046388a7ff648ad11f028eAlan CoxMODULE_DESCRIPTION("MC support for Radisys 82600 memory controllers"); 4062f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox 4072f768af73fea4c70f9046388a7ff648ad11f028eAlan Coxmodule_param(disable_hardware_scrub, bool, 0644); 4082f768af73fea4c70f9046388a7ff648ad11f028eAlan CoxMODULE_PARM_DESC(disable_hardware_scrub, 4092f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox "If set, disable the chipset's automatic scrub for CEs"); 410