r82600_edac.c revision cddbfcacf02dc2d5b074fc2717358a7529a190db
12f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox/*
22f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox * Radisys 82600 Embedded chipset Memory Controller kernel module
32f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox * (C) 2005 EADS Astrium
42f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox * This file may be distributed under the terms of the
52f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox * GNU General Public License.
62f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox *
72f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox * Written by Tim Small <tim@buttersideup.com>, based on work by Thayne
82f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox * Harbaugh, Dan Hollis <goemon at anime dot net> and others.
92f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox *
102f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox * $Id: edac_r82600.c,v 1.1.2.6 2005/10/05 00:43:44 dsp_llnl Exp $
112f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox *
122f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox * Written with reference to 82600 High Integration Dual PCI System
132f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox * Controller Data Book:
14c4192705fec85219086231a1c0fa61e8776e2c3bDave Jiang * www.radisys.com/files/support_downloads/007-01277-0002.82600DataBook.pdf
152f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox * references to this document given in []
162f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox */
172f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox
182f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox#include <linux/module.h>
192f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox#include <linux/init.h>
202f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox#include <linux/pci.h>
212f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox#include <linux/pci_ids.h>
222f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox#include <linux/slab.h>
2320bcb7a81dee21bfa3408f03f46b2891c9b5c84bDouglas Thompson#include "edac_core.h"
242f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox
2520bcb7a81dee21bfa3408f03f46b2891c9b5c84bDouglas Thompson#define R82600_REVISION	" Ver: 2.0.2 " __DATE__
26929a40ec324e947d4ad14cc1ced785c104c560e2Doug Thompson#define EDAC_MOD_STR	"r82600_edac"
2737f04581abac20444e5b7106c1e1f28bec5b989cDoug Thompson
28537fba28928c01b7db1580627450691a4bb0b9b3Dave Peterson#define r82600_printk(level, fmt, arg...) \
29e7ecd8910293564d357dbaf18eb179e06fa35fd0Dave Peterson	edac_printk(level, "r82600", fmt, ##arg)
30537fba28928c01b7db1580627450691a4bb0b9b3Dave Peterson
31537fba28928c01b7db1580627450691a4bb0b9b3Dave Peterson#define r82600_mc_printk(mci, level, fmt, arg...) \
32e7ecd8910293564d357dbaf18eb179e06fa35fd0Dave Peterson	edac_mc_chipset_printk(mci, level, "r82600", fmt, ##arg)
33537fba28928c01b7db1580627450691a4bb0b9b3Dave Peterson
342f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox/* Radisys say "The 82600 integrates a main memory SDRAM controller that
352f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox * supports up to four banks of memory. The four banks can support a mix of
362f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox * sizes of 64 bit wide (72 bits with ECC) Synchronous DRAM (SDRAM) DIMMs,
372f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox * each of which can be any size from 16MB to 512MB. Both registered (control
382f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox * signals buffered) and unbuffered DIMM types are supported. Mixing of
392f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox * registered and unbuffered DIMMs as well as mixing of ECC and non-ECC DIMMs
402f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox * is not allowed. The 82600 SDRAM interface operates at the same frequency as
412f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox * the CPU bus, 66MHz, 100MHz or 133MHz."
422f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox */
432f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox
442f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox#define R82600_NR_CSROWS 4
452f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox#define R82600_NR_CHANS  1
462f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox#define R82600_NR_DIMMS  4
472f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox
482f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox#define R82600_BRIDGE_ID  0x8200
492f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox
502f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox/* Radisys 82600 register addresses - device 0 function 0 - PCI bridge */
512f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox#define R82600_DRAMC	0x57	/* Various SDRAM related control bits
522f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox				 * all bits are R/W
532f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox				 *
542f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox				 * 7    SDRAM ISA Hole Enable
552f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox				 * 6    Flash Page Mode Enable
562f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox				 * 5    ECC Enable: 1=ECC 0=noECC
572f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox				 * 4    DRAM DIMM Type: 1=
582f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox				 * 3    BIOS Alias Disable
592f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox				 * 2    SDRAM BIOS Flash Write Enable
602f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox				 * 1:0  SDRAM Refresh Rate: 00=Disabled
612f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox				 *          01=7.8usec (256Mbit SDRAMs)
622f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox				 *          10=15.6us 11=125usec
632f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox				 */
642f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox
652f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox#define R82600_SDRAMC	0x76	/* "SDRAM Control Register"
662f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox				 * More SDRAM related control bits
672f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox				 * all bits are R/W
682f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox				 *
692f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox				 * 15:8 Reserved.
702f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox				 *
712f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox				 * 7:5  Special SDRAM Mode Select
722f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox				 *
732f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox				 * 4    Force ECC
742f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox				 *
752f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox				 *        1=Drive ECC bits to 0 during
762f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox				 *          write cycles (i.e. ECC test mode)
772f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox				 *
782f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox				 *        0=Normal ECC functioning
792f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox				 *
802f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox				 * 3    Enhanced Paging Enable
812f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox				 *
822f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox				 * 2    CAS# Latency 0=3clks 1=2clks
832f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox				 *
842f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox				 * 1    RAS# to CAS# Delay 0=3 1=2
852f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox				 *
862f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox				 * 0    RAS# Precharge     0=3 1=2
872f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox				 */
882f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox
892f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox#define R82600_EAP	0x80	/* ECC Error Address Pointer Register
902f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox				 *
912f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox				 * 31    Disable Hardware Scrubbing (RW)
922f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox				 *        0=Scrub on corrected read
932f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox				 *        1=Don't scrub on corrected read
942f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox				 *
952f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox				 * 30:12 Error Address Pointer (RO)
962f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox				 *        Upper 19 bits of error address
972f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox				 *
982f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox				 * 11:4  Syndrome Bits (RO)
992f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox				 *
1002f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox				 * 3     BSERR# on multibit error (RW)
1012f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox				 *        1=enable 0=disable
1022f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox				 *
1032f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox				 * 2     NMI on Single Bit Eror (RW)
1042f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox				 *        1=NMI triggered by SBE n.b. other
1052f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox				 *          prerequeists
1062f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox				 *        0=NMI not triggered
1072f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox				 *
1082f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox				 * 1     MBE (R/WC)
1092f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox				 *        read 1=MBE at EAP (see above)
1102f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox				 *        read 0=no MBE, or SBE occurred first
1112f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox				 *        write 1=Clear MBE status (must also
1122f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox				 *          clear SBE)
1132f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox				 *        write 0=NOP
1142f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox				 *
1152f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox				 * 1     SBE (R/WC)
1162f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox				 *        read 1=SBE at EAP (see above)
1172f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox				 *        read 0=no SBE, or MBE occurred first
1182f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox				 *        write 1=Clear SBE status (must also
1192f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox				 *          clear MBE)
1202f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox				 *        write 0=NOP
1212f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox				 */
1222f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox
1232f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox#define R82600_DRBA	0x60	/* + 0x60..0x63 SDRAM Row Boundry Address
1242f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox				 *  Registers
1252f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox				 *
1262f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox				 * 7:0  Address lines 30:24 - upper limit of
1272f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox				 * each row [p57]
1282f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox				 */
1292f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox
1302f768af73fea4c70f9046388a7ff648ad11f028eAlan Coxstruct r82600_error_info {
1312f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox	u32 eapr;
1322f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox};
1332f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox
1342f768af73fea4c70f9046388a7ff648ad11f028eAlan Coxstatic unsigned int disable_hardware_scrub = 0;
1352f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox
136cddbfcacf02dc2d5b074fc2717358a7529a190dbDouglas Thompsonstatic void r82600_get_error_info(struct mem_ctl_info *mci,
137cddbfcacf02dc2d5b074fc2717358a7529a190dbDouglas Thompson				  struct r82600_error_info *info)
1382f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox{
13937f04581abac20444e5b7106c1e1f28bec5b989cDoug Thompson	struct pci_dev *pdev;
14037f04581abac20444e5b7106c1e1f28bec5b989cDoug Thompson
14137f04581abac20444e5b7106c1e1f28bec5b989cDoug Thompson	pdev = to_pci_dev(mci->dev);
14237f04581abac20444e5b7106c1e1f28bec5b989cDoug Thompson	pci_read_config_dword(pdev, R82600_EAP, &info->eapr);
1432f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox
1442f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox	if (info->eapr & BIT(0))
1452f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox		/* Clear error to allow next error to be reported [p.62] */
14637f04581abac20444e5b7106c1e1f28bec5b989cDoug Thompson		pci_write_bits32(pdev, R82600_EAP,
147cddbfcacf02dc2d5b074fc2717358a7529a190dbDouglas Thompson				 ((u32) BIT(0) & (u32) BIT(1)),
148cddbfcacf02dc2d5b074fc2717358a7529a190dbDouglas Thompson				 ((u32) BIT(0) & (u32) BIT(1)));
1492f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox
1502f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox	if (info->eapr & BIT(1))
1512f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox		/* Clear error to allow next error to be reported [p.62] */
15237f04581abac20444e5b7106c1e1f28bec5b989cDoug Thompson		pci_write_bits32(pdev, R82600_EAP,
153cddbfcacf02dc2d5b074fc2717358a7529a190dbDouglas Thompson				 ((u32) BIT(0) & (u32) BIT(1)),
154cddbfcacf02dc2d5b074fc2717358a7529a190dbDouglas Thompson				 ((u32) BIT(0) & (u32) BIT(1)));
1552f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox}
1562f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox
157cddbfcacf02dc2d5b074fc2717358a7529a190dbDouglas Thompsonstatic int r82600_process_error_info(struct mem_ctl_info *mci,
158cddbfcacf02dc2d5b074fc2717358a7529a190dbDouglas Thompson				     struct r82600_error_info *info,
159cddbfcacf02dc2d5b074fc2717358a7529a190dbDouglas Thompson				     int handle_errors)
1602f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox{
1612f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox	int error_found;
1622f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox	u32 eapaddr, page;
1632f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox	u32 syndrome;
1642f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox
1652f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox	error_found = 0;
1662f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox
1672f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox	/* bits 30:12 store the upper 19 bits of the 32 bit error address */
1682f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox	eapaddr = ((info->eapr >> 12) & 0x7FFF) << 13;
1692f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox	/* Syndrome in bits 11:4 [p.62]       */
1702f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox	syndrome = (info->eapr >> 4) & 0xFF;
1712f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox
1722f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox	/* the R82600 reports at less than page *
1732f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox	 * granularity (upper 19 bits only)     */
1742f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox	page = eapaddr >> PAGE_SHIFT;
1752f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox
176cddbfcacf02dc2d5b074fc2717358a7529a190dbDouglas Thompson	if (info->eapr & BIT(0)) {	/* CE? */
1772f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox		error_found = 1;
1782f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox
1792f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox		if (handle_errors)
180cddbfcacf02dc2d5b074fc2717358a7529a190dbDouglas Thompson			edac_mc_handle_ce(mci, page, 0,	/* not avail */
181cddbfcacf02dc2d5b074fc2717358a7529a190dbDouglas Thompson					  syndrome, edac_mc_find_csrow_by_page(mci, page), 0,	/* channel */
182cddbfcacf02dc2d5b074fc2717358a7529a190dbDouglas Thompson					  mci->ctl_name);
1832f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox	}
1842f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox
185cddbfcacf02dc2d5b074fc2717358a7529a190dbDouglas Thompson	if (info->eapr & BIT(1)) {	/* UE? */
1862f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox		error_found = 1;
1872f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox
1882f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox		if (handle_errors)
1892f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox			/* 82600 doesn't give enough info */
1902f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox			edac_mc_handle_ue(mci, page, 0,
191cddbfcacf02dc2d5b074fc2717358a7529a190dbDouglas Thompson					  edac_mc_find_csrow_by_page(mci, page),
192cddbfcacf02dc2d5b074fc2717358a7529a190dbDouglas Thompson					  mci->ctl_name);
1932f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox	}
1942f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox
1952f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox	return error_found;
1962f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox}
1972f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox
1982f768af73fea4c70f9046388a7ff648ad11f028eAlan Coxstatic void r82600_check(struct mem_ctl_info *mci)
1992f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox{
2002f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox	struct r82600_error_info info;
2012f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox
202537fba28928c01b7db1580627450691a4bb0b9b3Dave Peterson	debugf1("MC%d: %s()\n", mci->mc_idx, __func__);
2032f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox	r82600_get_error_info(mci, &info);
2042f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox	r82600_process_error_info(mci, &info, 1);
2052f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox}
2062f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox
2071318952514d5651c453d89989595a9df3b37267bDoug Thompsonstatic inline int ecc_enabled(u8 dramcr)
2082f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox{
2091318952514d5651c453d89989595a9df3b37267bDoug Thompson	return dramcr & BIT(5);
2101318952514d5651c453d89989595a9df3b37267bDoug Thompson}
2111318952514d5651c453d89989595a9df3b37267bDoug Thompson
2121318952514d5651c453d89989595a9df3b37267bDoug Thompsonstatic void r82600_init_csrows(struct mem_ctl_info *mci, struct pci_dev *pdev,
213cddbfcacf02dc2d5b074fc2717358a7529a190dbDouglas Thompson			       u8 dramcr)
2141318952514d5651c453d89989595a9df3b37267bDoug Thompson{
2151318952514d5651c453d89989595a9df3b37267bDoug Thompson	struct csrow_info *csrow;
2162f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox	int index;
217cddbfcacf02dc2d5b074fc2717358a7529a190dbDouglas Thompson	u8 drbar;		/* SDRAM Row Boundry Address Register */
2181318952514d5651c453d89989595a9df3b37267bDoug Thompson	u32 row_high_limit, row_high_limit_last;
2191318952514d5651c453d89989595a9df3b37267bDoug Thompson	u32 reg_sdram, ecc_on, row_base;
2201318952514d5651c453d89989595a9df3b37267bDoug Thompson
2211318952514d5651c453d89989595a9df3b37267bDoug Thompson	ecc_on = ecc_enabled(dramcr);
2221318952514d5651c453d89989595a9df3b37267bDoug Thompson	reg_sdram = dramcr & BIT(4);
2231318952514d5651c453d89989595a9df3b37267bDoug Thompson	row_high_limit_last = 0;
2241318952514d5651c453d89989595a9df3b37267bDoug Thompson
2251318952514d5651c453d89989595a9df3b37267bDoug Thompson	for (index = 0; index < mci->nr_csrows; index++) {
2261318952514d5651c453d89989595a9df3b37267bDoug Thompson		csrow = &mci->csrows[index];
2271318952514d5651c453d89989595a9df3b37267bDoug Thompson
2281318952514d5651c453d89989595a9df3b37267bDoug Thompson		/* find the DRAM Chip Select Base address and mask */
2291318952514d5651c453d89989595a9df3b37267bDoug Thompson		pci_read_config_byte(pdev, R82600_DRBA + index, &drbar);
2301318952514d5651c453d89989595a9df3b37267bDoug Thompson
2311318952514d5651c453d89989595a9df3b37267bDoug Thompson		debugf1("%s() Row=%d DRBA = %#0x\n", __func__, index, drbar);
2321318952514d5651c453d89989595a9df3b37267bDoug Thompson
2331318952514d5651c453d89989595a9df3b37267bDoug Thompson		row_high_limit = ((u32) drbar << 24);
2341318952514d5651c453d89989595a9df3b37267bDoug Thompson/*		row_high_limit = ((u32)drbar << 24) | 0xffffffUL; */
2351318952514d5651c453d89989595a9df3b37267bDoug Thompson
2361318952514d5651c453d89989595a9df3b37267bDoug Thompson		debugf1("%s() Row=%d, Boundry Address=%#0x, Last = %#0x\n",
2371318952514d5651c453d89989595a9df3b37267bDoug Thompson			__func__, index, row_high_limit, row_high_limit_last);
2381318952514d5651c453d89989595a9df3b37267bDoug Thompson
2391318952514d5651c453d89989595a9df3b37267bDoug Thompson		/* Empty row [p.57] */
2401318952514d5651c453d89989595a9df3b37267bDoug Thompson		if (row_high_limit == row_high_limit_last)
2411318952514d5651c453d89989595a9df3b37267bDoug Thompson			continue;
2421318952514d5651c453d89989595a9df3b37267bDoug Thompson
2431318952514d5651c453d89989595a9df3b37267bDoug Thompson		row_base = row_high_limit_last;
2441318952514d5651c453d89989595a9df3b37267bDoug Thompson
2451318952514d5651c453d89989595a9df3b37267bDoug Thompson		csrow->first_page = row_base >> PAGE_SHIFT;
2461318952514d5651c453d89989595a9df3b37267bDoug Thompson		csrow->last_page = (row_high_limit >> PAGE_SHIFT) - 1;
2471318952514d5651c453d89989595a9df3b37267bDoug Thompson		csrow->nr_pages = csrow->last_page - csrow->first_page + 1;
2481318952514d5651c453d89989595a9df3b37267bDoug Thompson		/* Error address is top 19 bits - so granularity is      *
2491318952514d5651c453d89989595a9df3b37267bDoug Thompson		 * 14 bits                                               */
2501318952514d5651c453d89989595a9df3b37267bDoug Thompson		csrow->grain = 1 << 14;
2511318952514d5651c453d89989595a9df3b37267bDoug Thompson		csrow->mtype = reg_sdram ? MEM_RDDR : MEM_DDR;
2521318952514d5651c453d89989595a9df3b37267bDoug Thompson		/* FIXME - check that this is unknowable with this chipset */
2531318952514d5651c453d89989595a9df3b37267bDoug Thompson		csrow->dtype = DEV_UNKNOWN;
2541318952514d5651c453d89989595a9df3b37267bDoug Thompson
2551318952514d5651c453d89989595a9df3b37267bDoug Thompson		/* Mode is global on 82600 */
2561318952514d5651c453d89989595a9df3b37267bDoug Thompson		csrow->edac_mode = ecc_on ? EDAC_SECDED : EDAC_NONE;
2571318952514d5651c453d89989595a9df3b37267bDoug Thompson		row_high_limit_last = row_high_limit;
2581318952514d5651c453d89989595a9df3b37267bDoug Thompson	}
2591318952514d5651c453d89989595a9df3b37267bDoug Thompson}
2601318952514d5651c453d89989595a9df3b37267bDoug Thompson
2611318952514d5651c453d89989595a9df3b37267bDoug Thompsonstatic int r82600_probe1(struct pci_dev *pdev, int dev_idx)
2621318952514d5651c453d89989595a9df3b37267bDoug Thompson{
2631318952514d5651c453d89989595a9df3b37267bDoug Thompson	struct mem_ctl_info *mci;
2642f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox	u8 dramcr;
2652f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox	u32 eapr;
2662f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox	u32 scrub_disabled;
2672f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox	u32 sdram_refresh_rate;
268749ede57443b2a7ede2db105145f21047efcea6aDave Peterson	struct r82600_error_info discard;
2692f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox
270537fba28928c01b7db1580627450691a4bb0b9b3Dave Peterson	debugf0("%s()\n", __func__);
2712f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox	pci_read_config_byte(pdev, R82600_DRAMC, &dramcr);
2722f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox	pci_read_config_dword(pdev, R82600_EAP, &eapr);
2732f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox	scrub_disabled = eapr & BIT(31);
2742f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox	sdram_refresh_rate = dramcr & (BIT(0) | BIT(1));
275537fba28928c01b7db1580627450691a4bb0b9b3Dave Peterson	debugf2("%s(): sdram refresh rate = %#0x\n", __func__,
276537fba28928c01b7db1580627450691a4bb0b9b3Dave Peterson		sdram_refresh_rate);
277537fba28928c01b7db1580627450691a4bb0b9b3Dave Peterson	debugf2("%s(): DRAMC register = %#0x\n", __func__, dramcr);
2782f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox	mci = edac_mc_alloc(0, R82600_NR_CSROWS, R82600_NR_CHANS);
2792f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox
2801318952514d5651c453d89989595a9df3b37267bDoug Thompson	if (mci == NULL)
2811318952514d5651c453d89989595a9df3b37267bDoug Thompson		return -ENOMEM;
2822f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox
283537fba28928c01b7db1580627450691a4bb0b9b3Dave Peterson	debugf0("%s(): mci = %p\n", __func__, mci);
28437f04581abac20444e5b7106c1e1f28bec5b989cDoug Thompson	mci->dev = &pdev->dev;
2852f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox	mci->mtype_cap = MEM_FLAG_RDDR | MEM_FLAG_DDR;
2862f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox	mci->edac_ctl_cap = EDAC_FLAG_NONE | EDAC_FLAG_EC | EDAC_FLAG_SECDED;
287e7ecd8910293564d357dbaf18eb179e06fa35fd0Dave Peterson	/* FIXME try to work out if the chip leads have been used for COM2
288e7ecd8910293564d357dbaf18eb179e06fa35fd0Dave Peterson	 * instead on this board? [MA6?] MAYBE:
289e7ecd8910293564d357dbaf18eb179e06fa35fd0Dave Peterson	 */
2902f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox
2912f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox	/* On the R82600, the pins for memory bits 72:65 - i.e. the   *
2922f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox	 * EC bits are shared with the pins for COM2 (!), so if COM2  *
2932f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox	 * is enabled, we assume COM2 is wired up, and thus no EDAC   *
2942f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox	 * is possible.                                               */
2952f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox	mci->edac_cap = EDAC_FLAG_NONE | EDAC_FLAG_EC | EDAC_FLAG_SECDED;
296e7ecd8910293564d357dbaf18eb179e06fa35fd0Dave Peterson
2971318952514d5651c453d89989595a9df3b37267bDoug Thompson	if (ecc_enabled(dramcr)) {
2982f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox		if (scrub_disabled)
299537fba28928c01b7db1580627450691a4bb0b9b3Dave Peterson			debugf3("%s(): mci = %p - Scrubbing disabled! EAP: "
300537fba28928c01b7db1580627450691a4bb0b9b3Dave Peterson				"%#0x\n", __func__, mci, eapr);
3012f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox	} else
3022f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox		mci->edac_cap = EDAC_FLAG_NONE;
3032f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox
304680cbbbb0e336b04b74be48b8ddd870537f1e226Dave Peterson	mci->mod_name = EDAC_MOD_STR;
30537f04581abac20444e5b7106c1e1f28bec5b989cDoug Thompson	mci->mod_ver = R82600_REVISION;
3062f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox	mci->ctl_name = "R82600";
307c4192705fec85219086231a1c0fa61e8776e2c3bDave Jiang	mci->dev_name = pci_name(pdev);
3082f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox	mci->edac_check = r82600_check;
3092f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox	mci->ctl_page_to_phys = NULL;
3101318952514d5651c453d89989595a9df3b37267bDoug Thompson	r82600_init_csrows(mci, pdev, dramcr);
311cddbfcacf02dc2d5b074fc2717358a7529a190dbDouglas Thompson	r82600_get_error_info(mci, &discard);	/* clear counters */
3122f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox
3132d7bbb91c8df26c60d223205a087507430024177Doug Thompson	/* Here we assume that we will never see multiple instances of this
3142d7bbb91c8df26c60d223205a087507430024177Doug Thompson	 * type of memory controller.  The ID is therefore hardcoded to 0.
3152d7bbb91c8df26c60d223205a087507430024177Doug Thompson	 */
316cddbfcacf02dc2d5b074fc2717358a7529a190dbDouglas Thompson	if (edac_mc_add_mc(mci, 0)) {
317537fba28928c01b7db1580627450691a4bb0b9b3Dave Peterson		debugf3("%s(): failed edac_mc_add_mc()\n", __func__);
3182f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox		goto fail;
3192f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox	}
3202f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox
3212f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox	/* get this far and it's successful */
3222f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox
3232f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox	if (disable_hardware_scrub) {
324537fba28928c01b7db1580627450691a4bb0b9b3Dave Peterson		debugf3("%s(): Disabling Hardware Scrub (scrub on error)\n",
325537fba28928c01b7db1580627450691a4bb0b9b3Dave Peterson			__func__);
32637f04581abac20444e5b7106c1e1f28bec5b989cDoug Thompson		pci_write_bits32(pdev, R82600_EAP, BIT(31), BIT(31));
3272f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox	}
3282f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox
329537fba28928c01b7db1580627450691a4bb0b9b3Dave Peterson	debugf3("%s(): success\n", __func__);
3302f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox	return 0;
3312f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox
332cddbfcacf02dc2d5b074fc2717358a7529a190dbDouglas Thompson      fail:
3331318952514d5651c453d89989595a9df3b37267bDoug Thompson	edac_mc_free(mci);
3341318952514d5651c453d89989595a9df3b37267bDoug Thompson	return -ENODEV;
3352f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox}
3362f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox
3372f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox/* returns count (>= 0), or negative on error */
3382f768af73fea4c70f9046388a7ff648ad11f028eAlan Coxstatic int __devinit r82600_init_one(struct pci_dev *pdev,
339cddbfcacf02dc2d5b074fc2717358a7529a190dbDouglas Thompson				     const struct pci_device_id *ent)
3402f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox{
341537fba28928c01b7db1580627450691a4bb0b9b3Dave Peterson	debugf0("%s()\n", __func__);
3422f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox
3432f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox	/* don't need to call pci_device_enable() */
3442f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox	return r82600_probe1(pdev, ent->driver_data);
3452f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox}
3462f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox
3472f768af73fea4c70f9046388a7ff648ad11f028eAlan Coxstatic void __devexit r82600_remove_one(struct pci_dev *pdev)
3482f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox{
3492f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox	struct mem_ctl_info *mci;
3502f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox
351537fba28928c01b7db1580627450691a4bb0b9b3Dave Peterson	debugf0("%s()\n", __func__);
3522f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox
35337f04581abac20444e5b7106c1e1f28bec5b989cDoug Thompson	if ((mci = edac_mc_del_mc(&pdev->dev)) == NULL)
35418dbc337af5d6efd30cb9291e74722c8ad134fd3Dave Peterson		return;
35518dbc337af5d6efd30cb9291e74722c8ad134fd3Dave Peterson
35618dbc337af5d6efd30cb9291e74722c8ad134fd3Dave Peterson	edac_mc_free(mci);
3572f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox}
3582f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox
3592f768af73fea4c70f9046388a7ff648ad11f028eAlan Coxstatic const struct pci_device_id r82600_pci_tbl[] __devinitdata = {
360e7ecd8910293564d357dbaf18eb179e06fa35fd0Dave Peterson	{
361cddbfcacf02dc2d5b074fc2717358a7529a190dbDouglas Thompson	 PCI_DEVICE(PCI_VENDOR_ID_RADISYS, R82600_BRIDGE_ID)
362cddbfcacf02dc2d5b074fc2717358a7529a190dbDouglas Thompson	 },
363e7ecd8910293564d357dbaf18eb179e06fa35fd0Dave Peterson	{
364cddbfcacf02dc2d5b074fc2717358a7529a190dbDouglas Thompson	 0,
365cddbfcacf02dc2d5b074fc2717358a7529a190dbDouglas Thompson	 }			/* 0 terminated list. */
3662f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox};
3672f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox
3682f768af73fea4c70f9046388a7ff648ad11f028eAlan CoxMODULE_DEVICE_TABLE(pci, r82600_pci_tbl);
3692f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox
3702f768af73fea4c70f9046388a7ff648ad11f028eAlan Coxstatic struct pci_driver r82600_driver = {
371680cbbbb0e336b04b74be48b8ddd870537f1e226Dave Peterson	.name = EDAC_MOD_STR,
3722f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox	.probe = r82600_init_one,
3732f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox	.remove = __devexit_p(r82600_remove_one),
3742f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox	.id_table = r82600_pci_tbl,
3752f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox};
3762f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox
377da9bb1d27b21cb24cbb6a2efb5d3c464d357a01eAlan Coxstatic int __init r82600_init(void)
3782f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox{
3792f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox	return pci_register_driver(&r82600_driver);
3802f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox}
3812f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox
3822f768af73fea4c70f9046388a7ff648ad11f028eAlan Coxstatic void __exit r82600_exit(void)
3832f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox{
3842f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox	pci_unregister_driver(&r82600_driver);
3852f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox}
3862f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox
3872f768af73fea4c70f9046388a7ff648ad11f028eAlan Coxmodule_init(r82600_init);
3882f768af73fea4c70f9046388a7ff648ad11f028eAlan Coxmodule_exit(r82600_exit);
3892f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox
3902f768af73fea4c70f9046388a7ff648ad11f028eAlan CoxMODULE_LICENSE("GPL");
3912f768af73fea4c70f9046388a7ff648ad11f028eAlan CoxMODULE_AUTHOR("Tim Small <tim@buttersideup.com> - WPAD Ltd. "
392cddbfcacf02dc2d5b074fc2717358a7529a190dbDouglas Thompson	      "on behalf of EADS Astrium");
3932f768af73fea4c70f9046388a7ff648ad11f028eAlan CoxMODULE_DESCRIPTION("MC support for Radisys 82600 memory controllers");
3942f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox
3952f768af73fea4c70f9046388a7ff648ad11f028eAlan Coxmodule_param(disable_hardware_scrub, bool, 0644);
3962f768af73fea4c70f9046388a7ff648ad11f028eAlan CoxMODULE_PARM_DESC(disable_hardware_scrub,
3972f768af73fea4c70f9046388a7ff648ad11f028eAlan Cox		 "If set, disable the chipset's automatic scrub for CEs");
398