r82600_edac.c revision 20bcb7a81dee21bfa3408f03f46b2891c9b5c84b 
1/*
2 * Radisys 82600 Embedded chipset Memory Controller kernel module
3 * (C) 2005 EADS Astrium
4 * This file may be distributed under the terms of the
5 * GNU General Public License.
6 *
7 * Written by Tim Small <tim@buttersideup.com>, based on work by Thayne
8 * Harbaugh, Dan Hollis <goemon at anime dot net> and others.
9 *
10 * $Id: edac_r82600.c,v 1.1.2.6 2005/10/05 00:43:44 dsp_llnl Exp $
11 *
12 * Written with reference to 82600 High Integration Dual PCI System
13 * Controller Data Book:
14 * http://www.radisys.com/files/support_downloads/007-01277-0002.82600DataBook.pdf
15 * references to this document given in []
16 */
17
18#include <linux/module.h>
19#include <linux/init.h>
20#include <linux/pci.h>
21#include <linux/pci_ids.h>
22#include <linux/slab.h>
23#include "edac_core.h"
24
25#define R82600_REVISION	" Ver: 2.0.2 " __DATE__
26#define EDAC_MOD_STR	"r82600_edac"
27
28#define r82600_printk(level, fmt, arg...) \
29	edac_printk(level, "r82600", fmt, ##arg)
30
31#define r82600_mc_printk(mci, level, fmt, arg...) \
32	edac_mc_chipset_printk(mci, level, "r82600", fmt, ##arg)
33
34/* Radisys say "The 82600 integrates a main memory SDRAM controller that
35 * supports up to four banks of memory. The four banks can support a mix of
36 * sizes of 64 bit wide (72 bits with ECC) Synchronous DRAM (SDRAM) DIMMs,
37 * each of which can be any size from 16MB to 512MB. Both registered (control
38 * signals buffered) and unbuffered DIMM types are supported. Mixing of
39 * registered and unbuffered DIMMs as well as mixing of ECC and non-ECC DIMMs
40 * is not allowed. The 82600 SDRAM interface operates at the same frequency as
41 * the CPU bus, 66MHz, 100MHz or 133MHz."
42 */
43
44#define R82600_NR_CSROWS 4
45#define R82600_NR_CHANS  1
46#define R82600_NR_DIMMS  4
47
48#define R82600_BRIDGE_ID  0x8200
49
50/* Radisys 82600 register addresses - device 0 function 0 - PCI bridge */
51#define R82600_DRAMC	0x57	/* Various SDRAM related control bits
52				 * all bits are R/W
53				 *
54				 * 7    SDRAM ISA Hole Enable
55				 * 6    Flash Page Mode Enable
56				 * 5    ECC Enable: 1=ECC 0=noECC
57				 * 4    DRAM DIMM Type: 1=
58				 * 3    BIOS Alias Disable
59				 * 2    SDRAM BIOS Flash Write Enable
60				 * 1:0  SDRAM Refresh Rate: 00=Disabled
61				 *          01=7.8usec (256Mbit SDRAMs)
62				 *          10=15.6us 11=125usec
63				 */
64
65#define R82600_SDRAMC	0x76	/* "SDRAM Control Register"
66				 * More SDRAM related control bits
67				 * all bits are R/W
68				 *
69				 * 15:8 Reserved.
70				 *
71				 * 7:5  Special SDRAM Mode Select
72				 *
73				 * 4    Force ECC
74				 *
75				 *        1=Drive ECC bits to 0 during
76				 *          write cycles (i.e. ECC test mode)
77				 *
78				 *        0=Normal ECC functioning
79				 *
80				 * 3    Enhanced Paging Enable
81				 *
82				 * 2    CAS# Latency 0=3clks 1=2clks
83				 *
84				 * 1    RAS# to CAS# Delay 0=3 1=2
85				 *
86				 * 0    RAS# Precharge     0=3 1=2
87				 */
88
89#define R82600_EAP	0x80	/* ECC Error Address Pointer Register
90				 *
91				 * 31    Disable Hardware Scrubbing (RW)
92				 *        0=Scrub on corrected read
93				 *        1=Don't scrub on corrected read
94				 *
95				 * 30:12 Error Address Pointer (RO)
96				 *        Upper 19 bits of error address
97				 *
98				 * 11:4  Syndrome Bits (RO)
99				 *
100				 * 3     BSERR# on multibit error (RW)
101				 *        1=enable 0=disable
102				 *
103				 * 2     NMI on Single Bit Eror (RW)
104				 *        1=NMI triggered by SBE n.b. other
105				 *          prerequeists
106				 *        0=NMI not triggered
107				 *
108				 * 1     MBE (R/WC)
109				 *        read 1=MBE at EAP (see above)
110				 *        read 0=no MBE, or SBE occurred first
111				 *        write 1=Clear MBE status (must also
112				 *          clear SBE)
113				 *        write 0=NOP
114				 *
115				 * 1     SBE (R/WC)
116				 *        read 1=SBE at EAP (see above)
117				 *        read 0=no SBE, or MBE occurred first
118				 *        write 1=Clear SBE status (must also
119				 *          clear MBE)
120				 *        write 0=NOP
121				 */
122
123#define R82600_DRBA	0x60	/* + 0x60..0x63 SDRAM Row Boundry Address
124				 *  Registers
125				 *
126				 * 7:0  Address lines 30:24 - upper limit of
127				 * each row [p57]
128				 */
129
130struct r82600_error_info {
131	u32 eapr;
132};
133
134static unsigned int disable_hardware_scrub = 0;
135
136static void r82600_get_error_info (struct mem_ctl_info *mci,
137		struct r82600_error_info *info)
138{
139	struct pci_dev *pdev;
140
141	pdev = to_pci_dev(mci->dev);
142	pci_read_config_dword(pdev, R82600_EAP, &info->eapr);
143
144	if (info->eapr & BIT(0))
145		/* Clear error to allow next error to be reported [p.62] */
146		pci_write_bits32(pdev, R82600_EAP,
147				((u32) BIT(0) & (u32) BIT(1)),
148				((u32) BIT(0) & (u32) BIT(1)));
149
150	if (info->eapr & BIT(1))
151		/* Clear error to allow next error to be reported [p.62] */
152		pci_write_bits32(pdev, R82600_EAP,
153				((u32) BIT(0) & (u32) BIT(1)),
154				((u32) BIT(0) & (u32) BIT(1)));
155}
156
157static int r82600_process_error_info (struct mem_ctl_info *mci,
158		struct r82600_error_info *info, int handle_errors)
159{
160	int error_found;
161	u32 eapaddr, page;
162	u32 syndrome;
163
164	error_found = 0;
165
166	/* bits 30:12 store the upper 19 bits of the 32 bit error address */
167	eapaddr = ((info->eapr >> 12) & 0x7FFF) << 13;
168	/* Syndrome in bits 11:4 [p.62]       */
169	syndrome = (info->eapr >> 4) & 0xFF;
170
171	/* the R82600 reports at less than page *
172	 * granularity (upper 19 bits only)     */
173	page = eapaddr >> PAGE_SHIFT;
174
175	if (info->eapr & BIT(0)) {  /* CE? */
176		error_found = 1;
177
178		if (handle_errors)
179			edac_mc_handle_ce(mci, page, 0,  /* not avail */
180					syndrome,
181					edac_mc_find_csrow_by_page(mci, page),
182					0,  /* channel */
183					mci->ctl_name);
184	}
185
186	if (info->eapr & BIT(1)) {  /* UE? */
187		error_found = 1;
188
189		if (handle_errors)
190			/* 82600 doesn't give enough info */
191			edac_mc_handle_ue(mci, page, 0,
192				edac_mc_find_csrow_by_page(mci, page),
193				mci->ctl_name);
194	}
195
196	return error_found;
197}
198
199static void r82600_check(struct mem_ctl_info *mci)
200{
201	struct r82600_error_info info;
202
203	debugf1("MC%d: %s()\n", mci->mc_idx, __func__);
204	r82600_get_error_info(mci, &info);
205	r82600_process_error_info(mci, &info, 1);
206}
207
208static inline int ecc_enabled(u8 dramcr)
209{
210	return dramcr & BIT(5);
211}
212
213static void r82600_init_csrows(struct mem_ctl_info *mci, struct pci_dev *pdev,
214		u8 dramcr)
215{
216	struct csrow_info *csrow;
217	int index;
218	u8 drbar;  /* SDRAM Row Boundry Address Register */
219	u32 row_high_limit, row_high_limit_last;
220	u32 reg_sdram, ecc_on, row_base;
221
222	ecc_on = ecc_enabled(dramcr);
223	reg_sdram = dramcr & BIT(4);
224	row_high_limit_last = 0;
225
226	for (index = 0; index < mci->nr_csrows; index++) {
227		csrow = &mci->csrows[index];
228
229		/* find the DRAM Chip Select Base address and mask */
230		pci_read_config_byte(pdev, R82600_DRBA + index, &drbar);
231
232		debugf1("%s() Row=%d DRBA = %#0x\n", __func__, index, drbar);
233
234		row_high_limit = ((u32) drbar << 24);
235/*		row_high_limit = ((u32)drbar << 24) | 0xffffffUL; */
236
237		debugf1("%s() Row=%d, Boundry Address=%#0x, Last = %#0x\n",
238			__func__, index, row_high_limit, row_high_limit_last);
239
240		/* Empty row [p.57] */
241		if (row_high_limit == row_high_limit_last)
242			continue;
243
244		row_base = row_high_limit_last;
245
246		csrow->first_page = row_base >> PAGE_SHIFT;
247		csrow->last_page = (row_high_limit >> PAGE_SHIFT) - 1;
248		csrow->nr_pages = csrow->last_page - csrow->first_page + 1;
249		/* Error address is top 19 bits - so granularity is      *
250		 * 14 bits                                               */
251		csrow->grain = 1 << 14;
252		csrow->mtype = reg_sdram ? MEM_RDDR : MEM_DDR;
253		/* FIXME - check that this is unknowable with this chipset */
254		csrow->dtype = DEV_UNKNOWN;
255
256		/* Mode is global on 82600 */
257		csrow->edac_mode = ecc_on ? EDAC_SECDED : EDAC_NONE;
258		row_high_limit_last = row_high_limit;
259	}
260}
261
262static int r82600_probe1(struct pci_dev *pdev, int dev_idx)
263{
264	struct mem_ctl_info *mci;
265	u8 dramcr;
266	u32 eapr;
267	u32 scrub_disabled;
268	u32 sdram_refresh_rate;
269	struct r82600_error_info discard;
270
271	debugf0("%s()\n", __func__);
272	pci_read_config_byte(pdev, R82600_DRAMC, &dramcr);
273	pci_read_config_dword(pdev, R82600_EAP, &eapr);
274	scrub_disabled = eapr & BIT(31);
275	sdram_refresh_rate = dramcr & (BIT(0) | BIT(1));
276	debugf2("%s(): sdram refresh rate = %#0x\n", __func__,
277		sdram_refresh_rate);
278	debugf2("%s(): DRAMC register = %#0x\n", __func__, dramcr);
279	mci = edac_mc_alloc(0, R82600_NR_CSROWS, R82600_NR_CHANS);
280
281	if (mci == NULL)
282		return -ENOMEM;
283
284	debugf0("%s(): mci = %p\n", __func__, mci);
285	mci->dev = &pdev->dev;
286	mci->mtype_cap = MEM_FLAG_RDDR | MEM_FLAG_DDR;
287	mci->edac_ctl_cap = EDAC_FLAG_NONE | EDAC_FLAG_EC | EDAC_FLAG_SECDED;
288	/* FIXME try to work out if the chip leads have been used for COM2
289	 * instead on this board? [MA6?] MAYBE:
290	 */
291
292	/* On the R82600, the pins for memory bits 72:65 - i.e. the   *
293	 * EC bits are shared with the pins for COM2 (!), so if COM2  *
294	 * is enabled, we assume COM2 is wired up, and thus no EDAC   *
295	 * is possible.                                               */
296	mci->edac_cap = EDAC_FLAG_NONE | EDAC_FLAG_EC | EDAC_FLAG_SECDED;
297
298	if (ecc_enabled(dramcr)) {
299		if (scrub_disabled)
300			debugf3("%s(): mci = %p - Scrubbing disabled! EAP: "
301				"%#0x\n", __func__, mci, eapr);
302	} else
303		mci->edac_cap = EDAC_FLAG_NONE;
304
305	mci->mod_name = EDAC_MOD_STR;
306	mci->mod_ver = R82600_REVISION;
307	mci->ctl_name = "R82600";
308	mci->edac_check = r82600_check;
309	mci->ctl_page_to_phys = NULL;
310	r82600_init_csrows(mci, pdev, dramcr);
311	r82600_get_error_info(mci, &discard);  /* clear counters */
312
313	/* Here we assume that we will never see multiple instances of this
314	 * type of memory controller.  The ID is therefore hardcoded to 0.
315	 */
316	if (edac_mc_add_mc(mci,0)) {
317		debugf3("%s(): failed edac_mc_add_mc()\n", __func__);
318		goto fail;
319	}
320
321	/* get this far and it's successful */
322
323	if (disable_hardware_scrub) {
324		debugf3("%s(): Disabling Hardware Scrub (scrub on error)\n",
325			__func__);
326		pci_write_bits32(pdev, R82600_EAP, BIT(31), BIT(31));
327	}
328
329	debugf3("%s(): success\n", __func__);
330	return 0;
331
332fail:
333	edac_mc_free(mci);
334	return -ENODEV;
335}
336
337/* returns count (>= 0), or negative on error */
338static int __devinit r82600_init_one(struct pci_dev *pdev,
339		const struct pci_device_id *ent)
340{
341	debugf0("%s()\n", __func__);
342
343	/* don't need to call pci_device_enable() */
344	return r82600_probe1(pdev, ent->driver_data);
345}
346
347static void __devexit r82600_remove_one(struct pci_dev *pdev)
348{
349	struct mem_ctl_info *mci;
350
351	debugf0("%s()\n", __func__);
352
353	if ((mci = edac_mc_del_mc(&pdev->dev)) == NULL)
354		return;
355
356	edac_mc_free(mci);
357}
358
359static const struct pci_device_id r82600_pci_tbl[] __devinitdata = {
360	{
361		PCI_DEVICE(PCI_VENDOR_ID_RADISYS, R82600_BRIDGE_ID)
362	},
363	{
364		0,
365	}	/* 0 terminated list. */
366};
367
368MODULE_DEVICE_TABLE(pci, r82600_pci_tbl);
369
370static struct pci_driver r82600_driver = {
371	.name = EDAC_MOD_STR,
372	.probe = r82600_init_one,
373	.remove = __devexit_p(r82600_remove_one),
374	.id_table = r82600_pci_tbl,
375};
376
377static int __init r82600_init(void)
378{
379	return pci_register_driver(&r82600_driver);
380}
381
382static void __exit r82600_exit(void)
383{
384	pci_unregister_driver(&r82600_driver);
385}
386
387module_init(r82600_init);
388module_exit(r82600_exit);
389
390MODULE_LICENSE("GPL");
391MODULE_AUTHOR("Tim Small <tim@buttersideup.com> - WPAD Ltd. "
392	"on behalf of EADS Astrium");
393MODULE_DESCRIPTION("MC support for Radisys 82600 memory controllers");
394
395module_param(disable_hardware_scrub, bool, 0644);
396MODULE_PARM_DESC(disable_hardware_scrub,
397		 "If set, disable the chipset's automatic scrub for CEs");
398