1/*
2 * Driver for Aeroflex Gaisler GRGPIO General Purpose I/O cores.
3 *
4 * 2013 (c) Aeroflex Gaisler AB
5 *
6 * This driver supports the GRGPIO GPIO core available in the GRLIB VHDL
7 * IP core library.
8 *
9 * Full documentation of the GRGPIO core can be found here:
10 * http://www.gaisler.com/products/grlib/grip.pdf
11 *
12 * See "Documentation/devicetree/bindings/gpio/gpio-grgpio.txt" for
13 * information on open firmware properties.
14 *
15 * This program is free software; you can redistribute it and/or modify it
16 * under the terms of the GNU General Public License as published by the
17 * Free Software Foundation; either version 2 of the License, or (at your
18 * option) any later version.
19 *
20 * Contributors: Andreas Larsson <andreas@gaisler.com>
21 */
22
23#include <linux/kernel.h>
24#include <linux/module.h>
25#include <linux/init.h>
26#include <linux/spinlock.h>
27#include <linux/io.h>
28#include <linux/of.h>
29#include <linux/of_gpio.h>
30#include <linux/of_platform.h>
31#include <linux/gpio.h>
32#include <linux/slab.h>
33#include <linux/err.h>
34#include <linux/basic_mmio_gpio.h>
35#include <linux/interrupt.h>
36#include <linux/irq.h>
37#include <linux/irqdomain.h>
38
39#define GRGPIO_MAX_NGPIO 32
40
41#define GRGPIO_DATA		0x00
42#define GRGPIO_OUTPUT		0x04
43#define GRGPIO_DIR		0x08
44#define GRGPIO_IMASK		0x0c
45#define GRGPIO_IPOL		0x10
46#define GRGPIO_IEDGE		0x14
47#define GRGPIO_BYPASS		0x18
48#define GRGPIO_IMAP_BASE	0x20
49
50/* Structure for an irq of the core - called an underlying irq */
51struct grgpio_uirq {
52	u8 refcnt; /* Reference counter to manage requesting/freeing of uirq */
53	u8 uirq; /* Underlying irq of the gpio driver */
54};
55
56/*
57 * Structure for an irq of a gpio line handed out by this driver. The index is
58 * used to map to the corresponding underlying irq.
59 */
60struct grgpio_lirq {
61	s8 index; /* Index into struct grgpio_priv's uirqs, or -1 */
62	u8 irq; /* irq for the gpio line */
63};
64
65struct grgpio_priv {
66	struct bgpio_chip bgc;
67	void __iomem *regs;
68	struct device *dev;
69
70	u32 imask; /* irq mask shadow register */
71
72	/*
73	 * The grgpio core can have multiple "underlying" irqs. The gpio lines
74	 * can be mapped to any one or none of these underlying irqs
75	 * independently of each other. This driver sets up an irq domain and
76	 * hands out separate irqs to each gpio line
77	 */
78	struct irq_domain *domain;
79
80	/*
81	 * This array contains information on each underlying irq, each
82	 * irq of the grgpio core itself.
83	 */
84	struct grgpio_uirq uirqs[GRGPIO_MAX_NGPIO];
85
86	/*
87	 * This array contains information for each gpio line on the irqs
88	 * obtains from this driver. An index value of -1 for a certain gpio
89	 * line indicates that the line has no irq. Otherwise the index connects
90	 * the irq to the underlying irq by pointing into the uirqs array.
91	 */
92	struct grgpio_lirq lirqs[GRGPIO_MAX_NGPIO];
93};
94
95static inline struct grgpio_priv *grgpio_gc_to_priv(struct gpio_chip *gc)
96{
97	struct bgpio_chip *bgc = to_bgpio_chip(gc);
98
99	return container_of(bgc, struct grgpio_priv, bgc);
100}
101
102static void grgpio_set_imask(struct grgpio_priv *priv, unsigned int offset,
103			     int val)
104{
105	struct bgpio_chip *bgc = &priv->bgc;
106	unsigned long mask = bgc->pin2mask(bgc, offset);
107	unsigned long flags;
108
109	spin_lock_irqsave(&bgc->lock, flags);
110
111	if (val)
112		priv->imask |= mask;
113	else
114		priv->imask &= ~mask;
115	bgc->write_reg(priv->regs + GRGPIO_IMASK, priv->imask);
116
117	spin_unlock_irqrestore(&bgc->lock, flags);
118}
119
120static int grgpio_to_irq(struct gpio_chip *gc, unsigned offset)
121{
122	struct grgpio_priv *priv = grgpio_gc_to_priv(gc);
123
124	if (offset > gc->ngpio)
125		return -ENXIO;
126
127	if (priv->lirqs[offset].index < 0)
128		return -ENXIO;
129
130	return irq_create_mapping(priv->domain, offset);
131}
132
133/* -------------------- IRQ chip functions -------------------- */
134
135static int grgpio_irq_set_type(struct irq_data *d, unsigned int type)
136{
137	struct grgpio_priv *priv = irq_data_get_irq_chip_data(d);
138	unsigned long flags;
139	u32 mask = BIT(d->hwirq);
140	u32 ipol;
141	u32 iedge;
142	u32 pol;
143	u32 edge;
144
145	switch (type) {
146	case IRQ_TYPE_LEVEL_LOW:
147		pol = 0;
148		edge = 0;
149		break;
150	case IRQ_TYPE_LEVEL_HIGH:
151		pol = mask;
152		edge = 0;
153		break;
154	case IRQ_TYPE_EDGE_FALLING:
155		pol = 0;
156		edge = mask;
157		break;
158	case IRQ_TYPE_EDGE_RISING:
159		pol = mask;
160		edge = mask;
161		break;
162	default:
163		return -EINVAL;
164	}
165
166	spin_lock_irqsave(&priv->bgc.lock, flags);
167
168	ipol = priv->bgc.read_reg(priv->regs + GRGPIO_IPOL) & ~mask;
169	iedge = priv->bgc.read_reg(priv->regs + GRGPIO_IEDGE) & ~mask;
170
171	priv->bgc.write_reg(priv->regs + GRGPIO_IPOL, ipol | pol);
172	priv->bgc.write_reg(priv->regs + GRGPIO_IEDGE, iedge | edge);
173
174	spin_unlock_irqrestore(&priv->bgc.lock, flags);
175
176	return 0;
177}
178
179static void grgpio_irq_mask(struct irq_data *d)
180{
181	struct grgpio_priv *priv = irq_data_get_irq_chip_data(d);
182	int offset = d->hwirq;
183
184	grgpio_set_imask(priv, offset, 0);
185}
186
187static void grgpio_irq_unmask(struct irq_data *d)
188{
189	struct grgpio_priv *priv = irq_data_get_irq_chip_data(d);
190	int offset = d->hwirq;
191
192	grgpio_set_imask(priv, offset, 1);
193}
194
195static struct irq_chip grgpio_irq_chip = {
196	.name			= "grgpio",
197	.irq_mask		= grgpio_irq_mask,
198	.irq_unmask		= grgpio_irq_unmask,
199	.irq_set_type		= grgpio_irq_set_type,
200};
201
202static irqreturn_t grgpio_irq_handler(int irq, void *dev)
203{
204	struct grgpio_priv *priv = dev;
205	int ngpio = priv->bgc.gc.ngpio;
206	unsigned long flags;
207	int i;
208	int match = 0;
209
210	spin_lock_irqsave(&priv->bgc.lock, flags);
211
212	/*
213	 * For each gpio line, call its interrupt handler if it its underlying
214	 * irq matches the current irq that is handled.
215	 */
216	for (i = 0; i < ngpio; i++) {
217		struct grgpio_lirq *lirq = &priv->lirqs[i];
218
219		if (priv->imask & BIT(i) && lirq->index >= 0 &&
220		    priv->uirqs[lirq->index].uirq == irq) {
221			generic_handle_irq(lirq->irq);
222			match = 1;
223		}
224	}
225
226	spin_unlock_irqrestore(&priv->bgc.lock, flags);
227
228	if (!match)
229		dev_warn(priv->dev, "No gpio line matched irq %d\n", irq);
230
231	return IRQ_HANDLED;
232}
233
234/*
235 * This function will be called as a consequence of the call to
236 * irq_create_mapping in grgpio_to_irq
237 */
238static int grgpio_irq_map(struct irq_domain *d, unsigned int irq,
239			  irq_hw_number_t hwirq)
240{
241	struct grgpio_priv *priv = d->host_data;
242	struct grgpio_lirq *lirq;
243	struct grgpio_uirq *uirq;
244	unsigned long flags;
245	int offset = hwirq;
246	int ret = 0;
247
248	if (!priv)
249		return -EINVAL;
250
251	lirq = &priv->lirqs[offset];
252	if (lirq->index < 0)
253		return -EINVAL;
254
255	dev_dbg(priv->dev, "Mapping irq %d for gpio line %d\n",
256		irq, offset);
257
258	spin_lock_irqsave(&priv->bgc.lock, flags);
259
260	/* Request underlying irq if not already requested */
261	lirq->irq = irq;
262	uirq = &priv->uirqs[lirq->index];
263	if (uirq->refcnt == 0) {
264		ret = request_irq(uirq->uirq, grgpio_irq_handler, 0,
265				  dev_name(priv->dev), priv);
266		if (ret) {
267			dev_err(priv->dev,
268				"Could not request underlying irq %d\n",
269				uirq->uirq);
270
271			spin_unlock_irqrestore(&priv->bgc.lock, flags);
272
273			return ret;
274		}
275	}
276	uirq->refcnt++;
277
278	spin_unlock_irqrestore(&priv->bgc.lock, flags);
279
280	/* Setup irq  */
281	irq_set_chip_data(irq, priv);
282	irq_set_chip_and_handler(irq, &grgpio_irq_chip,
283				 handle_simple_irq);
284	irq_clear_status_flags(irq, IRQ_NOREQUEST);
285#ifdef CONFIG_ARM
286	set_irq_flags(irq, IRQF_VALID);
287#else
288	irq_set_noprobe(irq);
289#endif
290
291	return ret;
292}
293
294static void grgpio_irq_unmap(struct irq_domain *d, unsigned int irq)
295{
296	struct grgpio_priv *priv = d->host_data;
297	int index;
298	struct grgpio_lirq *lirq;
299	struct grgpio_uirq *uirq;
300	unsigned long flags;
301	int ngpio = priv->bgc.gc.ngpio;
302	int i;
303
304#ifdef CONFIG_ARM
305	set_irq_flags(irq, 0);
306#endif
307	irq_set_chip_and_handler(irq, NULL, NULL);
308	irq_set_chip_data(irq, NULL);
309
310	spin_lock_irqsave(&priv->bgc.lock, flags);
311
312	/* Free underlying irq if last user unmapped */
313	index = -1;
314	for (i = 0; i < ngpio; i++) {
315		lirq = &priv->lirqs[i];
316		if (lirq->irq == irq) {
317			grgpio_set_imask(priv, i, 0);
318			lirq->irq = 0;
319			index = lirq->index;
320			break;
321		}
322	}
323	WARN_ON(index < 0);
324
325	if (index >= 0) {
326		uirq = &priv->uirqs[lirq->index];
327		uirq->refcnt--;
328		if (uirq->refcnt == 0)
329			free_irq(uirq->uirq, priv);
330	}
331
332	spin_unlock_irqrestore(&priv->bgc.lock, flags);
333}
334
335static struct irq_domain_ops grgpio_irq_domain_ops = {
336	.map	= grgpio_irq_map,
337	.unmap	= grgpio_irq_unmap,
338};
339
340/* ------------------------------------------------------------ */
341
342static int grgpio_probe(struct platform_device *ofdev)
343{
344	struct device_node *np = ofdev->dev.of_node;
345	void  __iomem *regs;
346	struct gpio_chip *gc;
347	struct bgpio_chip *bgc;
348	struct grgpio_priv *priv;
349	struct resource *res;
350	int err;
351	u32 prop;
352	s32 *irqmap;
353	int size;
354	int i;
355
356	priv = devm_kzalloc(&ofdev->dev, sizeof(*priv), GFP_KERNEL);
357	if (!priv)
358		return -ENOMEM;
359
360	res = platform_get_resource(ofdev, IORESOURCE_MEM, 0);
361	regs = devm_ioremap_resource(&ofdev->dev, res);
362	if (IS_ERR(regs))
363		return PTR_ERR(regs);
364
365	bgc = &priv->bgc;
366	err = bgpio_init(bgc, &ofdev->dev, 4, regs + GRGPIO_DATA,
367			 regs + GRGPIO_OUTPUT, NULL, regs + GRGPIO_DIR, NULL,
368			 BGPIOF_BIG_ENDIAN_BYTE_ORDER);
369	if (err) {
370		dev_err(&ofdev->dev, "bgpio_init() failed\n");
371		return err;
372	}
373
374	priv->regs = regs;
375	priv->imask = bgc->read_reg(regs + GRGPIO_IMASK);
376	priv->dev = &ofdev->dev;
377
378	gc = &bgc->gc;
379	gc->of_node = np;
380	gc->owner = THIS_MODULE;
381	gc->to_irq = grgpio_to_irq;
382	gc->label = np->full_name;
383	gc->base = -1;
384
385	err = of_property_read_u32(np, "nbits", &prop);
386	if (err || prop <= 0 || prop > GRGPIO_MAX_NGPIO) {
387		gc->ngpio = GRGPIO_MAX_NGPIO;
388		dev_dbg(&ofdev->dev,
389			"No or invalid nbits property: assume %d\n", gc->ngpio);
390	} else {
391		gc->ngpio = prop;
392	}
393
394	/*
395	 * The irqmap contains the index values indicating which underlying irq,
396	 * if anyone, is connected to that line
397	 */
398	irqmap = (s32 *)of_get_property(np, "irqmap", &size);
399	if (irqmap) {
400		if (size < gc->ngpio) {
401			dev_err(&ofdev->dev,
402				"irqmap shorter than ngpio (%d < %d)\n",
403				size, gc->ngpio);
404			return -EINVAL;
405		}
406
407		priv->domain = irq_domain_add_linear(np, gc->ngpio,
408						     &grgpio_irq_domain_ops,
409						     priv);
410		if (!priv->domain) {
411			dev_err(&ofdev->dev, "Could not add irq domain\n");
412			return -EINVAL;
413		}
414
415		for (i = 0; i < gc->ngpio; i++) {
416			struct grgpio_lirq *lirq;
417			int ret;
418
419			lirq = &priv->lirqs[i];
420			lirq->index = irqmap[i];
421
422			if (lirq->index < 0)
423				continue;
424
425			ret = platform_get_irq(ofdev, lirq->index);
426			if (ret <= 0) {
427				/*
428				 * Continue without irq functionality for that
429				 * gpio line
430				 */
431				dev_err(priv->dev,
432					"Failed to get irq for offset %d\n", i);
433				continue;
434			}
435			priv->uirqs[lirq->index].uirq = ret;
436		}
437	}
438
439	platform_set_drvdata(ofdev, priv);
440
441	err = gpiochip_add(gc);
442	if (err) {
443		dev_err(&ofdev->dev, "Could not add gpiochip\n");
444		return err;
445	}
446
447	dev_info(&ofdev->dev, "regs=0x%p, base=%d, ngpio=%d, irqs=%s\n",
448		 priv->regs, gc->base, gc->ngpio, priv->domain ? "on" : "off");
449
450	return 0;
451}
452
453static int grgpio_remove(struct platform_device *ofdev)
454{
455	struct grgpio_priv *priv = platform_get_drvdata(ofdev);
456	unsigned long flags;
457	int i;
458	int ret = 0;
459
460	spin_lock_irqsave(&priv->bgc.lock, flags);
461
462	if (priv->domain) {
463		for (i = 0; i < GRGPIO_MAX_NGPIO; i++) {
464			if (priv->uirqs[i].refcnt != 0) {
465				ret = -EBUSY;
466				goto out;
467			}
468		}
469	}
470
471	gpiochip_remove(&priv->bgc.gc);
472
473	if (priv->domain)
474		irq_domain_remove(priv->domain);
475
476out:
477	spin_unlock_irqrestore(&priv->bgc.lock, flags);
478
479	return ret;
480}
481
482static const struct of_device_id grgpio_match[] = {
483	{.name = "GAISLER_GPIO"},
484	{.name = "01_01a"},
485	{},
486};
487
488MODULE_DEVICE_TABLE(of, grgpio_match);
489
490static struct platform_driver grgpio_driver = {
491	.driver = {
492		.name = "grgpio",
493		.owner = THIS_MODULE,
494		.of_match_table = grgpio_match,
495	},
496	.probe = grgpio_probe,
497	.remove = grgpio_remove,
498};
499module_platform_driver(grgpio_driver);
500
501MODULE_AUTHOR("Aeroflex Gaisler AB.");
502MODULE_DESCRIPTION("Driver for Aeroflex Gaisler GRGPIO");
503MODULE_LICENSE("GPL");
504