exynos_drm_dsi.c revision cdfb8694dc107c3b004b67dfbb392ae62d358e77 
1/*
2 * Samsung SoC MIPI DSI Master driver.
3 *
4 * Copyright (c) 2014 Samsung Electronics Co., Ltd
5 *
6 * Contacts: Tomasz Figa <t.figa@samsung.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#include <drm/drmP.h>
14#include <drm/drm_crtc_helper.h>
15#include <drm/drm_mipi_dsi.h>
16#include <drm/drm_panel.h>
17
18#include <linux/clk.h>
19#include <linux/irq.h>
20#include <linux/phy/phy.h>
21#include <linux/regulator/consumer.h>
22#include <linux/component.h>
23
24#include <video/mipi_display.h>
25#include <video/videomode.h>
26
27#include "exynos_drm_drv.h"
28
29/* returns true iff both arguments logically differs */
30#define NEQV(a, b) (!(a) ^ !(b))
31
32#define DSIM_STATUS_REG		0x0	/* Status register */
33#define DSIM_SWRST_REG		0x4	/* Software reset register */
34#define DSIM_CLKCTRL_REG	0x8	/* Clock control register */
35#define DSIM_TIMEOUT_REG	0xc	/* Time out register */
36#define DSIM_CONFIG_REG		0x10	/* Configuration register */
37#define DSIM_ESCMODE_REG	0x14	/* Escape mode register */
38
39/* Main display image resolution register */
40#define DSIM_MDRESOL_REG	0x18
41#define DSIM_MVPORCH_REG	0x1c	/* Main display Vporch register */
42#define DSIM_MHPORCH_REG	0x20	/* Main display Hporch register */
43#define DSIM_MSYNC_REG		0x24	/* Main display sync area register */
44
45/* Sub display image resolution register */
46#define DSIM_SDRESOL_REG	0x28
47#define DSIM_INTSRC_REG		0x2c	/* Interrupt source register */
48#define DSIM_INTMSK_REG		0x30	/* Interrupt mask register */
49#define DSIM_PKTHDR_REG		0x34	/* Packet Header FIFO register */
50#define DSIM_PAYLOAD_REG	0x38	/* Payload FIFO register */
51#define DSIM_RXFIFO_REG		0x3c	/* Read FIFO register */
52#define DSIM_FIFOTHLD_REG	0x40	/* FIFO threshold level register */
53#define DSIM_FIFOCTRL_REG	0x44	/* FIFO status and control register */
54
55/* FIFO memory AC characteristic register */
56#define DSIM_PLLCTRL_REG	0x4c	/* PLL control register */
57#define DSIM_PLLTMR_REG		0x50	/* PLL timer register */
58#define DSIM_PHYACCHR_REG	0x54	/* D-PHY AC characteristic register */
59#define DSIM_PHYACCHR1_REG	0x58	/* D-PHY AC characteristic register1 */
60
61/* DSIM_STATUS */
62#define DSIM_STOP_STATE_DAT(x)		(((x) & 0xf) << 0)
63#define DSIM_STOP_STATE_CLK		(1 << 8)
64#define DSIM_TX_READY_HS_CLK		(1 << 10)
65#define DSIM_PLL_STABLE			(1 << 31)
66
67/* DSIM_SWRST */
68#define DSIM_FUNCRST			(1 << 16)
69#define DSIM_SWRST			(1 << 0)
70
71/* DSIM_TIMEOUT */
72#define DSIM_LPDR_TIMEOUT(x)		((x) << 0)
73#define DSIM_BTA_TIMEOUT(x)		((x) << 16)
74
75/* DSIM_CLKCTRL */
76#define DSIM_ESC_PRESCALER(x)		(((x) & 0xffff) << 0)
77#define DSIM_ESC_PRESCALER_MASK		(0xffff << 0)
78#define DSIM_LANE_ESC_CLK_EN_CLK	(1 << 19)
79#define DSIM_LANE_ESC_CLK_EN_DATA(x)	(((x) & 0xf) << 20)
80#define DSIM_LANE_ESC_CLK_EN_DATA_MASK	(0xf << 20)
81#define DSIM_BYTE_CLKEN			(1 << 24)
82#define DSIM_BYTE_CLK_SRC(x)		(((x) & 0x3) << 25)
83#define DSIM_BYTE_CLK_SRC_MASK		(0x3 << 25)
84#define DSIM_PLL_BYPASS			(1 << 27)
85#define DSIM_ESC_CLKEN			(1 << 28)
86#define DSIM_TX_REQUEST_HSCLK		(1 << 31)
87
88/* DSIM_CONFIG */
89#define DSIM_LANE_EN_CLK		(1 << 0)
90#define DSIM_LANE_EN(x)			(((x) & 0xf) << 1)
91#define DSIM_NUM_OF_DATA_LANE(x)	(((x) & 0x3) << 5)
92#define DSIM_SUB_PIX_FORMAT(x)		(((x) & 0x7) << 8)
93#define DSIM_MAIN_PIX_FORMAT_MASK	(0x7 << 12)
94#define DSIM_MAIN_PIX_FORMAT_RGB888	(0x7 << 12)
95#define DSIM_MAIN_PIX_FORMAT_RGB666	(0x6 << 12)
96#define DSIM_MAIN_PIX_FORMAT_RGB666_P	(0x5 << 12)
97#define DSIM_MAIN_PIX_FORMAT_RGB565	(0x4 << 12)
98#define DSIM_SUB_VC			(((x) & 0x3) << 16)
99#define DSIM_MAIN_VC			(((x) & 0x3) << 18)
100#define DSIM_HSA_MODE			(1 << 20)
101#define DSIM_HBP_MODE			(1 << 21)
102#define DSIM_HFP_MODE			(1 << 22)
103#define DSIM_HSE_MODE			(1 << 23)
104#define DSIM_AUTO_MODE			(1 << 24)
105#define DSIM_VIDEO_MODE			(1 << 25)
106#define DSIM_BURST_MODE			(1 << 26)
107#define DSIM_SYNC_INFORM		(1 << 27)
108#define DSIM_EOT_DISABLE		(1 << 28)
109#define DSIM_MFLUSH_VS			(1 << 29)
110
111/* DSIM_ESCMODE */
112#define DSIM_TX_TRIGGER_RST		(1 << 4)
113#define DSIM_TX_LPDT_LP			(1 << 6)
114#define DSIM_CMD_LPDT_LP		(1 << 7)
115#define DSIM_FORCE_BTA			(1 << 16)
116#define DSIM_FORCE_STOP_STATE		(1 << 20)
117#define DSIM_STOP_STATE_CNT(x)		(((x) & 0x7ff) << 21)
118#define DSIM_STOP_STATE_CNT_MASK	(0x7ff << 21)
119
120/* DSIM_MDRESOL */
121#define DSIM_MAIN_STAND_BY		(1 << 31)
122#define DSIM_MAIN_VRESOL(x)		(((x) & 0x7ff) << 16)
123#define DSIM_MAIN_HRESOL(x)		(((x) & 0X7ff) << 0)
124
125/* DSIM_MVPORCH */
126#define DSIM_CMD_ALLOW(x)		((x) << 28)
127#define DSIM_STABLE_VFP(x)		((x) << 16)
128#define DSIM_MAIN_VBP(x)		((x) << 0)
129#define DSIM_CMD_ALLOW_MASK		(0xf << 28)
130#define DSIM_STABLE_VFP_MASK		(0x7ff << 16)
131#define DSIM_MAIN_VBP_MASK		(0x7ff << 0)
132
133/* DSIM_MHPORCH */
134#define DSIM_MAIN_HFP(x)		((x) << 16)
135#define DSIM_MAIN_HBP(x)		((x) << 0)
136#define DSIM_MAIN_HFP_MASK		((0xffff) << 16)
137#define DSIM_MAIN_HBP_MASK		((0xffff) << 0)
138
139/* DSIM_MSYNC */
140#define DSIM_MAIN_VSA(x)		((x) << 22)
141#define DSIM_MAIN_HSA(x)		((x) << 0)
142#define DSIM_MAIN_VSA_MASK		((0x3ff) << 22)
143#define DSIM_MAIN_HSA_MASK		((0xffff) << 0)
144
145/* DSIM_SDRESOL */
146#define DSIM_SUB_STANDY(x)		((x) << 31)
147#define DSIM_SUB_VRESOL(x)		((x) << 16)
148#define DSIM_SUB_HRESOL(x)		((x) << 0)
149#define DSIM_SUB_STANDY_MASK		((0x1) << 31)
150#define DSIM_SUB_VRESOL_MASK		((0x7ff) << 16)
151#define DSIM_SUB_HRESOL_MASK		((0x7ff) << 0)
152
153/* DSIM_INTSRC */
154#define DSIM_INT_PLL_STABLE		(1 << 31)
155#define DSIM_INT_SW_RST_RELEASE		(1 << 30)
156#define DSIM_INT_SFR_FIFO_EMPTY		(1 << 29)
157#define DSIM_INT_BTA			(1 << 25)
158#define DSIM_INT_FRAME_DONE		(1 << 24)
159#define DSIM_INT_RX_TIMEOUT		(1 << 21)
160#define DSIM_INT_BTA_TIMEOUT		(1 << 20)
161#define DSIM_INT_RX_DONE		(1 << 18)
162#define DSIM_INT_RX_TE			(1 << 17)
163#define DSIM_INT_RX_ACK			(1 << 16)
164#define DSIM_INT_RX_ECC_ERR		(1 << 15)
165#define DSIM_INT_RX_CRC_ERR		(1 << 14)
166
167/* DSIM_FIFOCTRL */
168#define DSIM_RX_DATA_FULL		(1 << 25)
169#define DSIM_RX_DATA_EMPTY		(1 << 24)
170#define DSIM_SFR_HEADER_FULL		(1 << 23)
171#define DSIM_SFR_HEADER_EMPTY		(1 << 22)
172#define DSIM_SFR_PAYLOAD_FULL		(1 << 21)
173#define DSIM_SFR_PAYLOAD_EMPTY		(1 << 20)
174#define DSIM_I80_HEADER_FULL		(1 << 19)
175#define DSIM_I80_HEADER_EMPTY		(1 << 18)
176#define DSIM_I80_PAYLOAD_FULL		(1 << 17)
177#define DSIM_I80_PAYLOAD_EMPTY		(1 << 16)
178#define DSIM_SD_HEADER_FULL		(1 << 15)
179#define DSIM_SD_HEADER_EMPTY		(1 << 14)
180#define DSIM_SD_PAYLOAD_FULL		(1 << 13)
181#define DSIM_SD_PAYLOAD_EMPTY		(1 << 12)
182#define DSIM_MD_HEADER_FULL		(1 << 11)
183#define DSIM_MD_HEADER_EMPTY		(1 << 10)
184#define DSIM_MD_PAYLOAD_FULL		(1 << 9)
185#define DSIM_MD_PAYLOAD_EMPTY		(1 << 8)
186#define DSIM_RX_FIFO			(1 << 4)
187#define DSIM_SFR_FIFO			(1 << 3)
188#define DSIM_I80_FIFO			(1 << 2)
189#define DSIM_SD_FIFO			(1 << 1)
190#define DSIM_MD_FIFO			(1 << 0)
191
192/* DSIM_PHYACCHR */
193#define DSIM_AFC_EN			(1 << 14)
194#define DSIM_AFC_CTL(x)			(((x) & 0x7) << 5)
195
196/* DSIM_PLLCTRL */
197#define DSIM_FREQ_BAND(x)		((x) << 24)
198#define DSIM_PLL_EN			(1 << 23)
199#define DSIM_PLL_P(x)			((x) << 13)
200#define DSIM_PLL_M(x)			((x) << 4)
201#define DSIM_PLL_S(x)			((x) << 1)
202
203#define DSI_MAX_BUS_WIDTH		4
204#define DSI_NUM_VIRTUAL_CHANNELS	4
205#define DSI_TX_FIFO_SIZE		2048
206#define DSI_RX_FIFO_SIZE		256
207#define DSI_XFER_TIMEOUT_MS		100
208#define DSI_RX_FIFO_EMPTY		0x30800002
209
210enum exynos_dsi_transfer_type {
211	EXYNOS_DSI_TX,
212	EXYNOS_DSI_RX,
213};
214
215struct exynos_dsi_transfer {
216	struct list_head list;
217	struct completion completed;
218	int result;
219	u8 data_id;
220	u8 data[2];
221	u16 flags;
222
223	const u8 *tx_payload;
224	u16 tx_len;
225	u16 tx_done;
226
227	u8 *rx_payload;
228	u16 rx_len;
229	u16 rx_done;
230};
231
232#define DSIM_STATE_ENABLED		BIT(0)
233#define DSIM_STATE_INITIALIZED		BIT(1)
234#define DSIM_STATE_CMD_LPM		BIT(2)
235
236struct exynos_dsi {
237	struct mipi_dsi_host dsi_host;
238	struct drm_connector connector;
239	struct drm_encoder *encoder;
240	struct device_node *panel_node;
241	struct drm_panel *panel;
242	struct device *dev;
243
244	void __iomem *reg_base;
245	struct phy *phy;
246	struct clk *pll_clk;
247	struct clk *bus_clk;
248	struct regulator_bulk_data supplies[2];
249	int irq;
250
251	u32 pll_clk_rate;
252	u32 burst_clk_rate;
253	u32 esc_clk_rate;
254	u32 lanes;
255	u32 mode_flags;
256	u32 format;
257	struct videomode vm;
258
259	int state;
260	struct drm_property *brightness;
261	struct completion completed;
262
263	spinlock_t transfer_lock; /* protects transfer_list */
264	struct list_head transfer_list;
265};
266
267#define host_to_dsi(host) container_of(host, struct exynos_dsi, dsi_host)
268#define connector_to_dsi(c) container_of(c, struct exynos_dsi, connector)
269
270static void exynos_dsi_wait_for_reset(struct exynos_dsi *dsi)
271{
272	if (wait_for_completion_timeout(&dsi->completed, msecs_to_jiffies(300)))
273		return;
274
275	dev_err(dsi->dev, "timeout waiting for reset\n");
276}
277
278static void exynos_dsi_reset(struct exynos_dsi *dsi)
279{
280	reinit_completion(&dsi->completed);
281	writel(DSIM_SWRST, dsi->reg_base + DSIM_SWRST_REG);
282}
283
284#ifndef MHZ
285#define MHZ	(1000*1000)
286#endif
287
288static unsigned long exynos_dsi_pll_find_pms(struct exynos_dsi *dsi,
289		unsigned long fin, unsigned long fout, u8 *p, u16 *m, u8 *s)
290{
291	unsigned long best_freq = 0;
292	u32 min_delta = 0xffffffff;
293	u8 p_min, p_max;
294	u8 _p, uninitialized_var(best_p);
295	u16 _m, uninitialized_var(best_m);
296	u8 _s, uninitialized_var(best_s);
297
298	p_min = DIV_ROUND_UP(fin, (12 * MHZ));
299	p_max = fin / (6 * MHZ);
300
301	for (_p = p_min; _p <= p_max; ++_p) {
302		for (_s = 0; _s <= 5; ++_s) {
303			u64 tmp;
304			u32 delta;
305
306			tmp = (u64)fout * (_p << _s);
307			do_div(tmp, fin);
308			_m = tmp;
309			if (_m < 41 || _m > 125)
310				continue;
311
312			tmp = (u64)_m * fin;
313			do_div(tmp, _p);
314			if (tmp < 500 * MHZ || tmp > 1000 * MHZ)
315				continue;
316
317			tmp = (u64)_m * fin;
318			do_div(tmp, _p << _s);
319
320			delta = abs(fout - tmp);
321			if (delta < min_delta) {
322				best_p = _p;
323				best_m = _m;
324				best_s = _s;
325				min_delta = delta;
326				best_freq = tmp;
327			}
328		}
329	}
330
331	if (best_freq) {
332		*p = best_p;
333		*m = best_m;
334		*s = best_s;
335	}
336
337	return best_freq;
338}
339
340static unsigned long exynos_dsi_set_pll(struct exynos_dsi *dsi,
341					unsigned long freq)
342{
343	static const unsigned long freq_bands[] = {
344		100 * MHZ, 120 * MHZ, 160 * MHZ, 200 * MHZ,
345		270 * MHZ, 320 * MHZ, 390 * MHZ, 450 * MHZ,
346		510 * MHZ, 560 * MHZ, 640 * MHZ, 690 * MHZ,
347		770 * MHZ, 870 * MHZ, 950 * MHZ,
348	};
349	unsigned long fin, fout;
350	int timeout, band;
351	u8 p, s;
352	u16 m;
353	u32 reg;
354
355	clk_set_rate(dsi->pll_clk, dsi->pll_clk_rate);
356
357	fin = clk_get_rate(dsi->pll_clk);
358	if (!fin) {
359		dev_err(dsi->dev, "failed to get PLL clock frequency\n");
360		return 0;
361	}
362
363	dev_dbg(dsi->dev, "PLL input frequency: %lu\n", fin);
364
365	fout = exynos_dsi_pll_find_pms(dsi, fin, freq, &p, &m, &s);
366	if (!fout) {
367		dev_err(dsi->dev,
368			"failed to find PLL PMS for requested frequency\n");
369		return -EFAULT;
370	}
371
372	for (band = 0; band < ARRAY_SIZE(freq_bands); ++band)
373		if (fout < freq_bands[band])
374			break;
375
376	dev_dbg(dsi->dev, "PLL freq %lu, (p %d, m %d, s %d), band %d\n", fout,
377		p, m, s, band);
378
379	writel(500, dsi->reg_base + DSIM_PLLTMR_REG);
380
381	reg = DSIM_FREQ_BAND(band) | DSIM_PLL_EN
382			| DSIM_PLL_P(p) | DSIM_PLL_M(m) | DSIM_PLL_S(s);
383	writel(reg, dsi->reg_base + DSIM_PLLCTRL_REG);
384
385	timeout = 1000;
386	do {
387		if (timeout-- == 0) {
388			dev_err(dsi->dev, "PLL failed to stabilize\n");
389			return -EFAULT;
390		}
391		reg = readl(dsi->reg_base + DSIM_STATUS_REG);
392	} while ((reg & DSIM_PLL_STABLE) == 0);
393
394	return fout;
395}
396
397static int exynos_dsi_enable_clock(struct exynos_dsi *dsi)
398{
399	unsigned long hs_clk, byte_clk, esc_clk;
400	unsigned long esc_div;
401	u32 reg;
402
403	hs_clk = exynos_dsi_set_pll(dsi, dsi->burst_clk_rate);
404	if (!hs_clk) {
405		dev_err(dsi->dev, "failed to configure DSI PLL\n");
406		return -EFAULT;
407	}
408
409	byte_clk = hs_clk / 8;
410	esc_div = DIV_ROUND_UP(byte_clk, dsi->esc_clk_rate);
411	esc_clk = byte_clk / esc_div;
412
413	if (esc_clk > 20 * MHZ) {
414		++esc_div;
415		esc_clk = byte_clk / esc_div;
416	}
417
418	dev_dbg(dsi->dev, "hs_clk = %lu, byte_clk = %lu, esc_clk = %lu\n",
419		hs_clk, byte_clk, esc_clk);
420
421	reg = readl(dsi->reg_base + DSIM_CLKCTRL_REG);
422	reg &= ~(DSIM_ESC_PRESCALER_MASK | DSIM_LANE_ESC_CLK_EN_CLK
423			| DSIM_LANE_ESC_CLK_EN_DATA_MASK | DSIM_PLL_BYPASS
424			| DSIM_BYTE_CLK_SRC_MASK);
425	reg |= DSIM_ESC_CLKEN | DSIM_BYTE_CLKEN
426			| DSIM_ESC_PRESCALER(esc_div)
427			| DSIM_LANE_ESC_CLK_EN_CLK
428			| DSIM_LANE_ESC_CLK_EN_DATA(BIT(dsi->lanes) - 1)
429			| DSIM_BYTE_CLK_SRC(0)
430			| DSIM_TX_REQUEST_HSCLK;
431	writel(reg, dsi->reg_base + DSIM_CLKCTRL_REG);
432
433	return 0;
434}
435
436static void exynos_dsi_disable_clock(struct exynos_dsi *dsi)
437{
438	u32 reg;
439
440	reg = readl(dsi->reg_base + DSIM_CLKCTRL_REG);
441	reg &= ~(DSIM_LANE_ESC_CLK_EN_CLK | DSIM_LANE_ESC_CLK_EN_DATA_MASK
442			| DSIM_ESC_CLKEN | DSIM_BYTE_CLKEN);
443	writel(reg, dsi->reg_base + DSIM_CLKCTRL_REG);
444
445	reg = readl(dsi->reg_base + DSIM_PLLCTRL_REG);
446	reg &= ~DSIM_PLL_EN;
447	writel(reg, dsi->reg_base + DSIM_PLLCTRL_REG);
448}
449
450static int exynos_dsi_init_link(struct exynos_dsi *dsi)
451{
452	int timeout;
453	u32 reg;
454	u32 lanes_mask;
455
456	/* Initialize FIFO pointers */
457	reg = readl(dsi->reg_base + DSIM_FIFOCTRL_REG);
458	reg &= ~0x1f;
459	writel(reg, dsi->reg_base + DSIM_FIFOCTRL_REG);
460
461	usleep_range(9000, 11000);
462
463	reg |= 0x1f;
464	writel(reg, dsi->reg_base + DSIM_FIFOCTRL_REG);
465
466	usleep_range(9000, 11000);
467
468	/* DSI configuration */
469	reg = 0;
470
471	if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO) {
472		reg |= DSIM_VIDEO_MODE;
473
474		if (!(dsi->mode_flags & MIPI_DSI_MODE_VSYNC_FLUSH))
475			reg |= DSIM_MFLUSH_VS;
476		if (!(dsi->mode_flags & MIPI_DSI_MODE_EOT_PACKET))
477			reg |= DSIM_EOT_DISABLE;
478		if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE)
479			reg |= DSIM_SYNC_INFORM;
480		if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_BURST)
481			reg |= DSIM_BURST_MODE;
482		if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_AUTO_VERT)
483			reg |= DSIM_AUTO_MODE;
484		if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_HSE)
485			reg |= DSIM_HSE_MODE;
486		if (!(dsi->mode_flags & MIPI_DSI_MODE_VIDEO_HFP))
487			reg |= DSIM_HFP_MODE;
488		if (!(dsi->mode_flags & MIPI_DSI_MODE_VIDEO_HBP))
489			reg |= DSIM_HBP_MODE;
490		if (!(dsi->mode_flags & MIPI_DSI_MODE_VIDEO_HSA))
491			reg |= DSIM_HSA_MODE;
492	}
493
494	switch (dsi->format) {
495	case MIPI_DSI_FMT_RGB888:
496		reg |= DSIM_MAIN_PIX_FORMAT_RGB888;
497		break;
498	case MIPI_DSI_FMT_RGB666:
499		reg |= DSIM_MAIN_PIX_FORMAT_RGB666;
500		break;
501	case MIPI_DSI_FMT_RGB666_PACKED:
502		reg |= DSIM_MAIN_PIX_FORMAT_RGB666_P;
503		break;
504	case MIPI_DSI_FMT_RGB565:
505		reg |= DSIM_MAIN_PIX_FORMAT_RGB565;
506		break;
507	default:
508		dev_err(dsi->dev, "invalid pixel format\n");
509		return -EINVAL;
510	}
511
512	reg |= DSIM_NUM_OF_DATA_LANE(dsi->lanes - 1);
513
514	writel(reg, dsi->reg_base + DSIM_CONFIG_REG);
515
516	reg |= DSIM_LANE_EN_CLK;
517	writel(reg, dsi->reg_base + DSIM_CONFIG_REG);
518
519	lanes_mask = BIT(dsi->lanes) - 1;
520	reg |= DSIM_LANE_EN(lanes_mask);
521	writel(reg, dsi->reg_base + DSIM_CONFIG_REG);
522
523	/* Check clock and data lane state are stop state */
524	timeout = 100;
525	do {
526		if (timeout-- == 0) {
527			dev_err(dsi->dev, "waiting for bus lanes timed out\n");
528			return -EFAULT;
529		}
530
531		reg = readl(dsi->reg_base + DSIM_STATUS_REG);
532		if ((reg & DSIM_STOP_STATE_DAT(lanes_mask))
533		    != DSIM_STOP_STATE_DAT(lanes_mask))
534			continue;
535	} while (!(reg & (DSIM_STOP_STATE_CLK | DSIM_TX_READY_HS_CLK)));
536
537	reg = readl(dsi->reg_base + DSIM_ESCMODE_REG);
538	reg &= ~DSIM_STOP_STATE_CNT_MASK;
539	reg |= DSIM_STOP_STATE_CNT(0xf);
540	writel(reg, dsi->reg_base + DSIM_ESCMODE_REG);
541
542	reg = DSIM_BTA_TIMEOUT(0xff) | DSIM_LPDR_TIMEOUT(0xffff);
543	writel(reg, dsi->reg_base + DSIM_TIMEOUT_REG);
544
545	return 0;
546}
547
548static void exynos_dsi_set_display_mode(struct exynos_dsi *dsi)
549{
550	struct videomode *vm = &dsi->vm;
551	u32 reg;
552
553	if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO) {
554		reg = DSIM_CMD_ALLOW(0xf)
555			| DSIM_STABLE_VFP(vm->vfront_porch)
556			| DSIM_MAIN_VBP(vm->vback_porch);
557		writel(reg, dsi->reg_base + DSIM_MVPORCH_REG);
558
559		reg = DSIM_MAIN_HFP(vm->hfront_porch)
560			| DSIM_MAIN_HBP(vm->hback_porch);
561		writel(reg, dsi->reg_base + DSIM_MHPORCH_REG);
562
563		reg = DSIM_MAIN_VSA(vm->vsync_len)
564			| DSIM_MAIN_HSA(vm->hsync_len);
565		writel(reg, dsi->reg_base + DSIM_MSYNC_REG);
566	}
567
568	reg = DSIM_MAIN_HRESOL(vm->hactive) | DSIM_MAIN_VRESOL(vm->vactive);
569	writel(reg, dsi->reg_base + DSIM_MDRESOL_REG);
570
571	dev_dbg(dsi->dev, "LCD size = %dx%d\n", vm->hactive, vm->vactive);
572}
573
574static void exynos_dsi_set_display_enable(struct exynos_dsi *dsi, bool enable)
575{
576	u32 reg;
577
578	reg = readl(dsi->reg_base + DSIM_MDRESOL_REG);
579	if (enable)
580		reg |= DSIM_MAIN_STAND_BY;
581	else
582		reg &= ~DSIM_MAIN_STAND_BY;
583	writel(reg, dsi->reg_base + DSIM_MDRESOL_REG);
584}
585
586static int exynos_dsi_wait_for_hdr_fifo(struct exynos_dsi *dsi)
587{
588	int timeout = 2000;
589
590	do {
591		u32 reg = readl(dsi->reg_base + DSIM_FIFOCTRL_REG);
592
593		if (!(reg & DSIM_SFR_HEADER_FULL))
594			return 0;
595
596		if (!cond_resched())
597			usleep_range(950, 1050);
598	} while (--timeout);
599
600	return -ETIMEDOUT;
601}
602
603static void exynos_dsi_set_cmd_lpm(struct exynos_dsi *dsi, bool lpm)
604{
605	u32 v = readl(dsi->reg_base + DSIM_ESCMODE_REG);
606
607	if (lpm)
608		v |= DSIM_CMD_LPDT_LP;
609	else
610		v &= ~DSIM_CMD_LPDT_LP;
611
612	writel(v, dsi->reg_base + DSIM_ESCMODE_REG);
613}
614
615static void exynos_dsi_force_bta(struct exynos_dsi *dsi)
616{
617	u32 v = readl(dsi->reg_base + DSIM_ESCMODE_REG);
618
619	v |= DSIM_FORCE_BTA;
620	writel(v, dsi->reg_base + DSIM_ESCMODE_REG);
621}
622
623static void exynos_dsi_send_to_fifo(struct exynos_dsi *dsi,
624					struct exynos_dsi_transfer *xfer)
625{
626	struct device *dev = dsi->dev;
627	const u8 *payload = xfer->tx_payload + xfer->tx_done;
628	u16 length = xfer->tx_len - xfer->tx_done;
629	bool first = !xfer->tx_done;
630	u32 reg;
631
632	dev_dbg(dev, "< xfer %p: tx len %u, done %u, rx len %u, done %u\n",
633		xfer, xfer->tx_len, xfer->tx_done, xfer->rx_len, xfer->rx_done);
634
635	if (length > DSI_TX_FIFO_SIZE)
636		length = DSI_TX_FIFO_SIZE;
637
638	xfer->tx_done += length;
639
640	/* Send payload */
641	while (length >= 4) {
642		reg = (payload[3] << 24) | (payload[2] << 16)
643					| (payload[1] << 8) | payload[0];
644		writel(reg, dsi->reg_base + DSIM_PAYLOAD_REG);
645		payload += 4;
646		length -= 4;
647	}
648
649	reg = 0;
650	switch (length) {
651	case 3:
652		reg |= payload[2] << 16;
653		/* Fall through */
654	case 2:
655		reg |= payload[1] << 8;
656		/* Fall through */
657	case 1:
658		reg |= payload[0];
659		writel(reg, dsi->reg_base + DSIM_PAYLOAD_REG);
660		break;
661	case 0:
662		/* Do nothing */
663		break;
664	}
665
666	/* Send packet header */
667	if (!first)
668		return;
669
670	reg = (xfer->data[1] << 16) | (xfer->data[0] << 8) | xfer->data_id;
671	if (exynos_dsi_wait_for_hdr_fifo(dsi)) {
672		dev_err(dev, "waiting for header FIFO timed out\n");
673		return;
674	}
675
676	if (NEQV(xfer->flags & MIPI_DSI_MSG_USE_LPM,
677		 dsi->state & DSIM_STATE_CMD_LPM)) {
678		exynos_dsi_set_cmd_lpm(dsi, xfer->flags & MIPI_DSI_MSG_USE_LPM);
679		dsi->state ^= DSIM_STATE_CMD_LPM;
680	}
681
682	writel(reg, dsi->reg_base + DSIM_PKTHDR_REG);
683
684	if (xfer->flags & MIPI_DSI_MSG_REQ_ACK)
685		exynos_dsi_force_bta(dsi);
686}
687
688static void exynos_dsi_read_from_fifo(struct exynos_dsi *dsi,
689					struct exynos_dsi_transfer *xfer)
690{
691	u8 *payload = xfer->rx_payload + xfer->rx_done;
692	bool first = !xfer->rx_done;
693	struct device *dev = dsi->dev;
694	u16 length;
695	u32 reg;
696
697	if (first) {
698		reg = readl(dsi->reg_base + DSIM_RXFIFO_REG);
699
700		switch (reg & 0x3f) {
701		case MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_2BYTE:
702		case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_2BYTE:
703			if (xfer->rx_len >= 2) {
704				payload[1] = reg >> 16;
705				++xfer->rx_done;
706			}
707			/* Fall through */
708		case MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_1BYTE:
709		case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_1BYTE:
710			payload[0] = reg >> 8;
711			++xfer->rx_done;
712			xfer->rx_len = xfer->rx_done;
713			xfer->result = 0;
714			goto clear_fifo;
715		case MIPI_DSI_RX_ACKNOWLEDGE_AND_ERROR_REPORT:
716			dev_err(dev, "DSI Error Report: 0x%04x\n",
717				(reg >> 8) & 0xffff);
718			xfer->result = 0;
719			goto clear_fifo;
720		}
721
722		length = (reg >> 8) & 0xffff;
723		if (length > xfer->rx_len) {
724			dev_err(dev,
725				"response too long (%u > %u bytes), stripping\n",
726				xfer->rx_len, length);
727			length = xfer->rx_len;
728		} else if (length < xfer->rx_len)
729			xfer->rx_len = length;
730	}
731
732	length = xfer->rx_len - xfer->rx_done;
733	xfer->rx_done += length;
734
735	/* Receive payload */
736	while (length >= 4) {
737		reg = readl(dsi->reg_base + DSIM_RXFIFO_REG);
738		payload[0] = (reg >>  0) & 0xff;
739		payload[1] = (reg >>  8) & 0xff;
740		payload[2] = (reg >> 16) & 0xff;
741		payload[3] = (reg >> 24) & 0xff;
742		payload += 4;
743		length -= 4;
744	}
745
746	if (length) {
747		reg = readl(dsi->reg_base + DSIM_RXFIFO_REG);
748		switch (length) {
749		case 3:
750			payload[2] = (reg >> 16) & 0xff;
751			/* Fall through */
752		case 2:
753			payload[1] = (reg >> 8) & 0xff;
754			/* Fall through */
755		case 1:
756			payload[0] = reg & 0xff;
757		}
758	}
759
760	if (xfer->rx_done == xfer->rx_len)
761		xfer->result = 0;
762
763clear_fifo:
764	length = DSI_RX_FIFO_SIZE / 4;
765	do {
766		reg = readl(dsi->reg_base + DSIM_RXFIFO_REG);
767		if (reg == DSI_RX_FIFO_EMPTY)
768			break;
769	} while (--length);
770}
771
772static void exynos_dsi_transfer_start(struct exynos_dsi *dsi)
773{
774	unsigned long flags;
775	struct exynos_dsi_transfer *xfer;
776	bool start = false;
777
778again:
779	spin_lock_irqsave(&dsi->transfer_lock, flags);
780
781	if (list_empty(&dsi->transfer_list)) {
782		spin_unlock_irqrestore(&dsi->transfer_lock, flags);
783		return;
784	}
785
786	xfer = list_first_entry(&dsi->transfer_list,
787					struct exynos_dsi_transfer, list);
788
789	spin_unlock_irqrestore(&dsi->transfer_lock, flags);
790
791	if (xfer->tx_len && xfer->tx_done == xfer->tx_len)
792		/* waiting for RX */
793		return;
794
795	exynos_dsi_send_to_fifo(dsi, xfer);
796
797	if (xfer->tx_len || xfer->rx_len)
798		return;
799
800	xfer->result = 0;
801	complete(&xfer->completed);
802
803	spin_lock_irqsave(&dsi->transfer_lock, flags);
804
805	list_del_init(&xfer->list);
806	start = !list_empty(&dsi->transfer_list);
807
808	spin_unlock_irqrestore(&dsi->transfer_lock, flags);
809
810	if (start)
811		goto again;
812}
813
814static bool exynos_dsi_transfer_finish(struct exynos_dsi *dsi)
815{
816	struct exynos_dsi_transfer *xfer;
817	unsigned long flags;
818	bool start = true;
819
820	spin_lock_irqsave(&dsi->transfer_lock, flags);
821
822	if (list_empty(&dsi->transfer_list)) {
823		spin_unlock_irqrestore(&dsi->transfer_lock, flags);
824		return false;
825	}
826
827	xfer = list_first_entry(&dsi->transfer_list,
828					struct exynos_dsi_transfer, list);
829
830	spin_unlock_irqrestore(&dsi->transfer_lock, flags);
831
832	dev_dbg(dsi->dev,
833		"> xfer %p, tx_len %u, tx_done %u, rx_len %u, rx_done %u\n",
834		xfer, xfer->tx_len, xfer->tx_done, xfer->rx_len, xfer->rx_done);
835
836	if (xfer->tx_done != xfer->tx_len)
837		return true;
838
839	if (xfer->rx_done != xfer->rx_len)
840		exynos_dsi_read_from_fifo(dsi, xfer);
841
842	if (xfer->rx_done != xfer->rx_len)
843		return true;
844
845	spin_lock_irqsave(&dsi->transfer_lock, flags);
846
847	list_del_init(&xfer->list);
848	start = !list_empty(&dsi->transfer_list);
849
850	spin_unlock_irqrestore(&dsi->transfer_lock, flags);
851
852	if (!xfer->rx_len)
853		xfer->result = 0;
854	complete(&xfer->completed);
855
856	return start;
857}
858
859static void exynos_dsi_remove_transfer(struct exynos_dsi *dsi,
860					struct exynos_dsi_transfer *xfer)
861{
862	unsigned long flags;
863	bool start;
864
865	spin_lock_irqsave(&dsi->transfer_lock, flags);
866
867	if (!list_empty(&dsi->transfer_list) &&
868	    xfer == list_first_entry(&dsi->transfer_list,
869				     struct exynos_dsi_transfer, list)) {
870		list_del_init(&xfer->list);
871		start = !list_empty(&dsi->transfer_list);
872		spin_unlock_irqrestore(&dsi->transfer_lock, flags);
873		if (start)
874			exynos_dsi_transfer_start(dsi);
875		return;
876	}
877
878	list_del_init(&xfer->list);
879
880	spin_unlock_irqrestore(&dsi->transfer_lock, flags);
881}
882
883static int exynos_dsi_transfer(struct exynos_dsi *dsi,
884					struct exynos_dsi_transfer *xfer)
885{
886	unsigned long flags;
887	bool stopped;
888
889	xfer->tx_done = 0;
890	xfer->rx_done = 0;
891	xfer->result = -ETIMEDOUT;
892	init_completion(&xfer->completed);
893
894	spin_lock_irqsave(&dsi->transfer_lock, flags);
895
896	stopped = list_empty(&dsi->transfer_list);
897	list_add_tail(&xfer->list, &dsi->transfer_list);
898
899	spin_unlock_irqrestore(&dsi->transfer_lock, flags);
900
901	if (stopped)
902		exynos_dsi_transfer_start(dsi);
903
904	wait_for_completion_timeout(&xfer->completed,
905				    msecs_to_jiffies(DSI_XFER_TIMEOUT_MS));
906	if (xfer->result == -ETIMEDOUT) {
907		exynos_dsi_remove_transfer(dsi, xfer);
908		dev_err(dsi->dev, "xfer timed out: %*ph %*ph\n", 2, xfer->data,
909			xfer->tx_len, xfer->tx_payload);
910		return -ETIMEDOUT;
911	}
912
913	/* Also covers hardware timeout condition */
914	return xfer->result;
915}
916
917static irqreturn_t exynos_dsi_irq(int irq, void *dev_id)
918{
919	struct exynos_dsi *dsi = dev_id;
920	u32 status;
921
922	status = readl(dsi->reg_base + DSIM_INTSRC_REG);
923	if (!status) {
924		static unsigned long int j;
925		if (printk_timed_ratelimit(&j, 500))
926			dev_warn(dsi->dev, "spurious interrupt\n");
927		return IRQ_HANDLED;
928	}
929	writel(status, dsi->reg_base + DSIM_INTSRC_REG);
930
931	if (status & DSIM_INT_SW_RST_RELEASE) {
932		u32 mask = ~(DSIM_INT_RX_DONE | DSIM_INT_SFR_FIFO_EMPTY);
933		writel(mask, dsi->reg_base + DSIM_INTMSK_REG);
934		complete(&dsi->completed);
935		return IRQ_HANDLED;
936	}
937
938	if (!(status & (DSIM_INT_RX_DONE | DSIM_INT_SFR_FIFO_EMPTY)))
939		return IRQ_HANDLED;
940
941	if (exynos_dsi_transfer_finish(dsi))
942		exynos_dsi_transfer_start(dsi);
943
944	return IRQ_HANDLED;
945}
946
947static int exynos_dsi_init(struct exynos_dsi *dsi)
948{
949	exynos_dsi_enable_clock(dsi);
950	exynos_dsi_reset(dsi);
951	enable_irq(dsi->irq);
952	exynos_dsi_wait_for_reset(dsi);
953	exynos_dsi_init_link(dsi);
954
955	return 0;
956}
957
958static int exynos_dsi_host_attach(struct mipi_dsi_host *host,
959				  struct mipi_dsi_device *device)
960{
961	struct exynos_dsi *dsi = host_to_dsi(host);
962
963	dsi->lanes = device->lanes;
964	dsi->format = device->format;
965	dsi->mode_flags = device->mode_flags;
966	dsi->panel_node = device->dev.of_node;
967
968	if (dsi->connector.dev)
969		drm_helper_hpd_irq_event(dsi->connector.dev);
970
971	return 0;
972}
973
974static int exynos_dsi_host_detach(struct mipi_dsi_host *host,
975				  struct mipi_dsi_device *device)
976{
977	struct exynos_dsi *dsi = host_to_dsi(host);
978
979	dsi->panel_node = NULL;
980
981	if (dsi->connector.dev)
982		drm_helper_hpd_irq_event(dsi->connector.dev);
983
984	return 0;
985}
986
987/* distinguish between short and long DSI packet types */
988static bool exynos_dsi_is_short_dsi_type(u8 type)
989{
990	return (type & 0x0f) <= 8;
991}
992
993static ssize_t exynos_dsi_host_transfer(struct mipi_dsi_host *host,
994				       struct mipi_dsi_msg *msg)
995{
996	struct exynos_dsi *dsi = host_to_dsi(host);
997	struct exynos_dsi_transfer xfer;
998	int ret;
999
1000	if (!(dsi->state & DSIM_STATE_INITIALIZED)) {
1001		ret = exynos_dsi_init(dsi);
1002		if (ret)
1003			return ret;
1004		dsi->state |= DSIM_STATE_INITIALIZED;
1005	}
1006
1007	if (msg->tx_len == 0)
1008		return -EINVAL;
1009
1010	xfer.data_id = msg->type | (msg->channel << 6);
1011
1012	if (exynos_dsi_is_short_dsi_type(msg->type)) {
1013		const char *tx_buf = msg->tx_buf;
1014
1015		if (msg->tx_len > 2)
1016			return -EINVAL;
1017		xfer.tx_len = 0;
1018		xfer.data[0] = tx_buf[0];
1019		xfer.data[1] = (msg->tx_len == 2) ? tx_buf[1] : 0;
1020	} else {
1021		xfer.tx_len = msg->tx_len;
1022		xfer.data[0] = msg->tx_len & 0xff;
1023		xfer.data[1] = msg->tx_len >> 8;
1024		xfer.tx_payload = msg->tx_buf;
1025	}
1026
1027	xfer.rx_len = msg->rx_len;
1028	xfer.rx_payload = msg->rx_buf;
1029	xfer.flags = msg->flags;
1030
1031	ret = exynos_dsi_transfer(dsi, &xfer);
1032	return (ret < 0) ? ret : xfer.rx_done;
1033}
1034
1035static const struct mipi_dsi_host_ops exynos_dsi_ops = {
1036	.attach = exynos_dsi_host_attach,
1037	.detach = exynos_dsi_host_detach,
1038	.transfer = exynos_dsi_host_transfer,
1039};
1040
1041static int exynos_dsi_poweron(struct exynos_dsi *dsi)
1042{
1043	int ret;
1044
1045	ret = regulator_bulk_enable(ARRAY_SIZE(dsi->supplies), dsi->supplies);
1046	if (ret < 0) {
1047		dev_err(dsi->dev, "cannot enable regulators %d\n", ret);
1048		return ret;
1049	}
1050
1051	ret = clk_prepare_enable(dsi->bus_clk);
1052	if (ret < 0) {
1053		dev_err(dsi->dev, "cannot enable bus clock %d\n", ret);
1054		goto err_bus_clk;
1055	}
1056
1057	ret = clk_prepare_enable(dsi->pll_clk);
1058	if (ret < 0) {
1059		dev_err(dsi->dev, "cannot enable pll clock %d\n", ret);
1060		goto err_pll_clk;
1061	}
1062
1063	ret = phy_power_on(dsi->phy);
1064	if (ret < 0) {
1065		dev_err(dsi->dev, "cannot enable phy %d\n", ret);
1066		goto err_phy;
1067	}
1068
1069	return 0;
1070
1071err_phy:
1072	clk_disable_unprepare(dsi->pll_clk);
1073err_pll_clk:
1074	clk_disable_unprepare(dsi->bus_clk);
1075err_bus_clk:
1076	regulator_bulk_disable(ARRAY_SIZE(dsi->supplies), dsi->supplies);
1077
1078	return ret;
1079}
1080
1081static void exynos_dsi_poweroff(struct exynos_dsi *dsi)
1082{
1083	int ret;
1084
1085	usleep_range(10000, 20000);
1086
1087	if (dsi->state & DSIM_STATE_INITIALIZED) {
1088		dsi->state &= ~DSIM_STATE_INITIALIZED;
1089
1090		exynos_dsi_disable_clock(dsi);
1091
1092		disable_irq(dsi->irq);
1093	}
1094
1095	dsi->state &= ~DSIM_STATE_CMD_LPM;
1096
1097	phy_power_off(dsi->phy);
1098
1099	clk_disable_unprepare(dsi->pll_clk);
1100	clk_disable_unprepare(dsi->bus_clk);
1101
1102	ret = regulator_bulk_disable(ARRAY_SIZE(dsi->supplies), dsi->supplies);
1103	if (ret < 0)
1104		dev_err(dsi->dev, "cannot disable regulators %d\n", ret);
1105}
1106
1107static int exynos_dsi_enable(struct exynos_dsi *dsi)
1108{
1109	int ret;
1110
1111	if (dsi->state & DSIM_STATE_ENABLED)
1112		return 0;
1113
1114	ret = exynos_dsi_poweron(dsi);
1115	if (ret < 0)
1116		return ret;
1117
1118	ret = drm_panel_prepare(dsi->panel);
1119	if (ret < 0) {
1120		exynos_dsi_poweroff(dsi);
1121		return ret;
1122	}
1123
1124	exynos_dsi_set_display_mode(dsi);
1125	exynos_dsi_set_display_enable(dsi, true);
1126
1127	ret = drm_panel_enable(dsi->panel);
1128	if (ret < 0) {
1129		exynos_dsi_set_display_enable(dsi, false);
1130		drm_panel_unprepare(dsi->panel);
1131		exynos_dsi_poweroff(dsi);
1132		return ret;
1133	}
1134
1135	dsi->state |= DSIM_STATE_ENABLED;
1136
1137	return 0;
1138}
1139
1140static void exynos_dsi_disable(struct exynos_dsi *dsi)
1141{
1142	if (!(dsi->state & DSIM_STATE_ENABLED))
1143		return;
1144
1145	drm_panel_disable(dsi->panel);
1146	exynos_dsi_set_display_enable(dsi, false);
1147	drm_panel_unprepare(dsi->panel);
1148	exynos_dsi_poweroff(dsi);
1149
1150	dsi->state &= ~DSIM_STATE_ENABLED;
1151}
1152
1153static void exynos_dsi_dpms(struct exynos_drm_display *display, int mode)
1154{
1155	struct exynos_dsi *dsi = display->ctx;
1156
1157	if (dsi->panel) {
1158		switch (mode) {
1159		case DRM_MODE_DPMS_ON:
1160			exynos_dsi_enable(dsi);
1161			break;
1162		case DRM_MODE_DPMS_STANDBY:
1163		case DRM_MODE_DPMS_SUSPEND:
1164		case DRM_MODE_DPMS_OFF:
1165			exynos_dsi_disable(dsi);
1166			break;
1167		default:
1168			break;
1169		}
1170	}
1171}
1172
1173static enum drm_connector_status
1174exynos_dsi_detect(struct drm_connector *connector, bool force)
1175{
1176	struct exynos_dsi *dsi = connector_to_dsi(connector);
1177
1178	if (!dsi->panel) {
1179		dsi->panel = of_drm_find_panel(dsi->panel_node);
1180		if (dsi->panel)
1181			drm_panel_attach(dsi->panel, &dsi->connector);
1182	} else if (!dsi->panel_node) {
1183		struct exynos_drm_display *display;
1184
1185		display = platform_get_drvdata(to_platform_device(dsi->dev));
1186		exynos_dsi_dpms(display, DRM_MODE_DPMS_OFF);
1187		drm_panel_detach(dsi->panel);
1188		dsi->panel = NULL;
1189	}
1190
1191	if (dsi->panel)
1192		return connector_status_connected;
1193
1194	return connector_status_disconnected;
1195}
1196
1197static void exynos_dsi_connector_destroy(struct drm_connector *connector)
1198{
1199}
1200
1201static struct drm_connector_funcs exynos_dsi_connector_funcs = {
1202	.dpms = drm_helper_connector_dpms,
1203	.detect = exynos_dsi_detect,
1204	.fill_modes = drm_helper_probe_single_connector_modes,
1205	.destroy = exynos_dsi_connector_destroy,
1206};
1207
1208static int exynos_dsi_get_modes(struct drm_connector *connector)
1209{
1210	struct exynos_dsi *dsi = connector_to_dsi(connector);
1211
1212	if (dsi->panel)
1213		return dsi->panel->funcs->get_modes(dsi->panel);
1214
1215	return 0;
1216}
1217
1218static int exynos_dsi_mode_valid(struct drm_connector *connector,
1219				 struct drm_display_mode *mode)
1220{
1221	return MODE_OK;
1222}
1223
1224static struct drm_encoder *
1225exynos_dsi_best_encoder(struct drm_connector *connector)
1226{
1227	struct exynos_dsi *dsi = connector_to_dsi(connector);
1228
1229	return dsi->encoder;
1230}
1231
1232static struct drm_connector_helper_funcs exynos_dsi_connector_helper_funcs = {
1233	.get_modes = exynos_dsi_get_modes,
1234	.mode_valid = exynos_dsi_mode_valid,
1235	.best_encoder = exynos_dsi_best_encoder,
1236};
1237
1238static int exynos_dsi_create_connector(struct exynos_drm_display *display,
1239				       struct drm_encoder *encoder)
1240{
1241	struct exynos_dsi *dsi = display->ctx;
1242	struct drm_connector *connector = &dsi->connector;
1243	int ret;
1244
1245	dsi->encoder = encoder;
1246
1247	connector->polled = DRM_CONNECTOR_POLL_HPD;
1248
1249	ret = drm_connector_init(encoder->dev, connector,
1250				 &exynos_dsi_connector_funcs,
1251				 DRM_MODE_CONNECTOR_DSI);
1252	if (ret) {
1253		DRM_ERROR("Failed to initialize connector with drm\n");
1254		return ret;
1255	}
1256
1257	drm_connector_helper_add(connector, &exynos_dsi_connector_helper_funcs);
1258	drm_sysfs_connector_add(connector);
1259	drm_mode_connector_attach_encoder(connector, encoder);
1260
1261	return 0;
1262}
1263
1264static void exynos_dsi_mode_set(struct exynos_drm_display *display,
1265			 struct drm_display_mode *mode)
1266{
1267	struct exynos_dsi *dsi = display->ctx;
1268	struct videomode *vm = &dsi->vm;
1269
1270	vm->hactive = mode->hdisplay;
1271	vm->vactive = mode->vdisplay;
1272	vm->vfront_porch = mode->vsync_start - mode->vdisplay;
1273	vm->vback_porch = mode->vtotal - mode->vsync_end;
1274	vm->vsync_len = mode->vsync_end - mode->vsync_start;
1275	vm->hfront_porch = mode->hsync_start - mode->hdisplay;
1276	vm->hback_porch = mode->htotal - mode->hsync_end;
1277	vm->hsync_len = mode->hsync_end - mode->hsync_start;
1278}
1279
1280static struct exynos_drm_display_ops exynos_dsi_display_ops = {
1281	.create_connector = exynos_dsi_create_connector,
1282	.mode_set = exynos_dsi_mode_set,
1283	.dpms = exynos_dsi_dpms
1284};
1285
1286static struct exynos_drm_display exynos_dsi_display = {
1287	.type = EXYNOS_DISPLAY_TYPE_LCD,
1288	.ops = &exynos_dsi_display_ops,
1289};
1290
1291/* of_* functions will be removed after merge of of_graph patches */
1292static struct device_node *
1293of_get_child_by_name_reg(struct device_node *parent, const char *name, u32 reg)
1294{
1295	struct device_node *np;
1296
1297	for_each_child_of_node(parent, np) {
1298		u32 r;
1299
1300		if (!np->name || of_node_cmp(np->name, name))
1301			continue;
1302
1303		if (of_property_read_u32(np, "reg", &r) < 0)
1304			r = 0;
1305
1306		if (reg == r)
1307			break;
1308	}
1309
1310	return np;
1311}
1312
1313static struct device_node *of_graph_get_port_by_reg(struct device_node *parent,
1314						    u32 reg)
1315{
1316	struct device_node *ports, *port;
1317
1318	ports = of_get_child_by_name(parent, "ports");
1319	if (ports)
1320		parent = ports;
1321
1322	port = of_get_child_by_name_reg(parent, "port", reg);
1323
1324	of_node_put(ports);
1325
1326	return port;
1327}
1328
1329static struct device_node *
1330of_graph_get_endpoint_by_reg(struct device_node *port, u32 reg)
1331{
1332	return of_get_child_by_name_reg(port, "endpoint", reg);
1333}
1334
1335static int exynos_dsi_of_read_u32(const struct device_node *np,
1336				  const char *propname, u32 *out_value)
1337{
1338	int ret = of_property_read_u32(np, propname, out_value);
1339
1340	if (ret < 0)
1341		pr_err("%s: failed to get '%s' property\n", np->full_name,
1342		       propname);
1343
1344	return ret;
1345}
1346
1347enum {
1348	DSI_PORT_IN,
1349	DSI_PORT_OUT
1350};
1351
1352static int exynos_dsi_parse_dt(struct exynos_dsi *dsi)
1353{
1354	struct device *dev = dsi->dev;
1355	struct device_node *node = dev->of_node;
1356	struct device_node *port, *ep;
1357	int ret;
1358
1359	ret = exynos_dsi_of_read_u32(node, "samsung,pll-clock-frequency",
1360				     &dsi->pll_clk_rate);
1361	if (ret < 0)
1362		return ret;
1363
1364	port = of_graph_get_port_by_reg(node, DSI_PORT_OUT);
1365	if (!port) {
1366		dev_err(dev, "no output port specified\n");
1367		return -EINVAL;
1368	}
1369
1370	ep = of_graph_get_endpoint_by_reg(port, 0);
1371	of_node_put(port);
1372	if (!ep) {
1373		dev_err(dev, "no endpoint specified in output port\n");
1374		return -EINVAL;
1375	}
1376
1377	ret = exynos_dsi_of_read_u32(ep, "samsung,burst-clock-frequency",
1378				     &dsi->burst_clk_rate);
1379	if (ret < 0)
1380		goto end;
1381
1382	ret = exynos_dsi_of_read_u32(ep, "samsung,esc-clock-frequency",
1383				     &dsi->esc_clk_rate);
1384
1385end:
1386	of_node_put(ep);
1387
1388	return ret;
1389}
1390
1391static int exynos_dsi_bind(struct device *dev, struct device *master,
1392				void *data)
1393{
1394	struct drm_device *drm_dev = data;
1395	struct exynos_dsi *dsi;
1396	int ret;
1397
1398	ret = exynos_drm_create_enc_conn(drm_dev, &exynos_dsi_display);
1399	if (ret) {
1400		DRM_ERROR("Encoder create [%d] failed with %d\n",
1401				exynos_dsi_display.type, ret);
1402		return ret;
1403	}
1404
1405	dsi = exynos_dsi_display.ctx;
1406
1407	return mipi_dsi_host_register(&dsi->dsi_host);
1408}
1409
1410static void exynos_dsi_unbind(struct device *dev, struct device *master,
1411				void *data)
1412{
1413	struct exynos_dsi *dsi = exynos_dsi_display.ctx;
1414	struct drm_encoder *encoder = dsi->encoder;
1415
1416	exynos_dsi_dpms(&exynos_dsi_display, DRM_MODE_DPMS_OFF);
1417
1418	mipi_dsi_host_unregister(&dsi->dsi_host);
1419
1420	encoder->funcs->destroy(encoder);
1421	drm_connector_cleanup(&dsi->connector);
1422}
1423
1424static const struct component_ops exynos_dsi_component_ops = {
1425	.bind	= exynos_dsi_bind,
1426	.unbind	= exynos_dsi_unbind,
1427};
1428
1429static int exynos_dsi_probe(struct platform_device *pdev)
1430{
1431	struct resource *res;
1432	struct exynos_dsi *dsi;
1433	int ret;
1434
1435	ret = exynos_drm_component_add(&pdev->dev, EXYNOS_DEVICE_TYPE_CONNECTOR,
1436					exynos_dsi_display.type);
1437	if (ret)
1438		return ret;
1439
1440	dsi = devm_kzalloc(&pdev->dev, sizeof(*dsi), GFP_KERNEL);
1441	if (!dsi) {
1442		dev_err(&pdev->dev, "failed to allocate dsi object.\n");
1443		ret = -ENOMEM;
1444		goto err_del_component;
1445	}
1446
1447	init_completion(&dsi->completed);
1448	spin_lock_init(&dsi->transfer_lock);
1449	INIT_LIST_HEAD(&dsi->transfer_list);
1450
1451	dsi->dsi_host.ops = &exynos_dsi_ops;
1452	dsi->dsi_host.dev = &pdev->dev;
1453
1454	dsi->dev = &pdev->dev;
1455
1456	ret = exynos_dsi_parse_dt(dsi);
1457	if (ret)
1458		goto err_del_component;
1459
1460	dsi->supplies[0].supply = "vddcore";
1461	dsi->supplies[1].supply = "vddio";
1462	ret = devm_regulator_bulk_get(&pdev->dev, ARRAY_SIZE(dsi->supplies),
1463				      dsi->supplies);
1464	if (ret) {
1465		dev_info(&pdev->dev, "failed to get regulators: %d\n", ret);
1466		return -EPROBE_DEFER;
1467	}
1468
1469	dsi->pll_clk = devm_clk_get(&pdev->dev, "pll_clk");
1470	if (IS_ERR(dsi->pll_clk)) {
1471		dev_info(&pdev->dev, "failed to get dsi pll input clock\n");
1472		ret = PTR_ERR(dsi->pll_clk);
1473		goto err_del_component;
1474	}
1475
1476	dsi->bus_clk = devm_clk_get(&pdev->dev, "bus_clk");
1477	if (IS_ERR(dsi->bus_clk)) {
1478		dev_info(&pdev->dev, "failed to get dsi bus clock\n");
1479		ret = PTR_ERR(dsi->bus_clk);
1480		goto err_del_component;
1481	}
1482
1483	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1484	dsi->reg_base = devm_ioremap_resource(&pdev->dev, res);
1485	if (IS_ERR(dsi->reg_base)) {
1486		dev_err(&pdev->dev, "failed to remap io region\n");
1487		ret = PTR_ERR(dsi->reg_base);
1488		goto err_del_component;
1489	}
1490
1491	dsi->phy = devm_phy_get(&pdev->dev, "dsim");
1492	if (IS_ERR(dsi->phy)) {
1493		dev_info(&pdev->dev, "failed to get dsim phy\n");
1494		ret = PTR_ERR(dsi->phy);
1495		goto err_del_component;
1496	}
1497
1498	dsi->irq = platform_get_irq(pdev, 0);
1499	if (dsi->irq < 0) {
1500		dev_err(&pdev->dev, "failed to request dsi irq resource\n");
1501		ret = dsi->irq;
1502		goto err_del_component;
1503	}
1504
1505	irq_set_status_flags(dsi->irq, IRQ_NOAUTOEN);
1506	ret = devm_request_threaded_irq(&pdev->dev, dsi->irq, NULL,
1507					exynos_dsi_irq, IRQF_ONESHOT,
1508					dev_name(&pdev->dev), dsi);
1509	if (ret) {
1510		dev_err(&pdev->dev, "failed to request dsi irq\n");
1511		goto err_del_component;
1512	}
1513
1514	exynos_dsi_display.ctx = dsi;
1515
1516	platform_set_drvdata(pdev, &exynos_dsi_display);
1517
1518	ret = component_add(&pdev->dev, &exynos_dsi_component_ops);
1519	if (ret)
1520		goto err_del_component;
1521
1522	return ret;
1523
1524err_del_component:
1525	exynos_drm_component_del(&pdev->dev, EXYNOS_DEVICE_TYPE_CONNECTOR);
1526	return ret;
1527}
1528
1529static int exynos_dsi_remove(struct platform_device *pdev)
1530{
1531	component_del(&pdev->dev, &exynos_dsi_component_ops);
1532	exynos_drm_component_del(&pdev->dev, EXYNOS_DEVICE_TYPE_CONNECTOR);
1533
1534	return 0;
1535}
1536
1537static struct of_device_id exynos_dsi_of_match[] = {
1538	{ .compatible = "samsung,exynos4210-mipi-dsi" },
1539	{ }
1540};
1541
1542struct platform_driver dsi_driver = {
1543	.probe = exynos_dsi_probe,
1544	.remove = exynos_dsi_remove,
1545	.driver = {
1546		   .name = "exynos-dsi",
1547		   .owner = THIS_MODULE,
1548		   .of_match_table = exynos_dsi_of_match,
1549	},
1550};
1551
1552MODULE_AUTHOR("Tomasz Figa <t.figa@samsung.com>");
1553MODULE_AUTHOR("Andrzej Hajda <a.hajda@samsung.com>");
1554MODULE_DESCRIPTION("Samsung SoC MIPI DSI Master");
1555MODULE_LICENSE("GPL v2");
1556