1026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov/* 2026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov * Copyright © 2010 Intel Corporation 3026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov * 4026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov * Permission is hereby granted, free of charge, to any person obtaining a 5026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov * copy of this software and associated documentation files (the "Software"), 6026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov * to deal in the Software without restriction, including without limitation 7026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov * and/or sell copies of the Software, and to permit persons to whom the 9026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov * Software is furnished to do so, subject to the following conditions: 10026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov * 11026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov * The above copyright notice and this permission notice (including the next 12026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov * paragraph) shall be included in all copies or substantial portions of the 13026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov * Software. 14026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov * 15026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov * DEALINGS IN THE SOFTWARE. 22026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov * 23026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov * Authors: 24026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov * jim liu <jim.liu@intel.com> 25026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov * Jackie Li<yaodong.li@intel.com> 26026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov */ 27026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov 28026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov#include "mdfld_dsi_dpi.h" 29026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov#include "mdfld_output.h" 30026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov#include "mdfld_dsi_pkg_sender.h" 31026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov#include "psb_drv.h" 32026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov#include "tc35876x-dsi-lvds.h" 33026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov 34026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemovstatic void mdfld_dsi_dpi_shut_down(struct mdfld_dsi_dpi_output *output, 35026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov int pipe); 36026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov 37026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemovstatic void mdfld_wait_for_HS_DATA_FIFO(struct drm_device *dev, u32 pipe) 38026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov{ 39026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov u32 gen_fifo_stat_reg = MIPI_GEN_FIFO_STAT_REG(pipe); 40026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov int timeout = 0; 41026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov 42026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov udelay(500); 43026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov 44026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov /* This will time out after approximately 2+ seconds */ 45026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov while ((timeout < 20000) && 46026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov (REG_READ(gen_fifo_stat_reg) & DSI_FIFO_GEN_HS_DATA_FULL)) { 47026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov udelay(100); 48026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov timeout++; 49026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov } 50026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov 51026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov if (timeout == 20000) 52026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov DRM_INFO("MIPI: HS Data FIFO was never cleared!\n"); 53026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov} 54026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov 55026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemovstatic void mdfld_wait_for_HS_CTRL_FIFO(struct drm_device *dev, u32 pipe) 56026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov{ 57026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov u32 gen_fifo_stat_reg = MIPI_GEN_FIFO_STAT_REG(pipe); 58026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov int timeout = 0; 59026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov 60026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov udelay(500); 61026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov 62026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov /* This will time out after approximately 2+ seconds */ 63026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov while ((timeout < 20000) && (REG_READ(gen_fifo_stat_reg) 64026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov & DSI_FIFO_GEN_HS_CTRL_FULL)) { 65026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov udelay(100); 66026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov timeout++; 67026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov } 68026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov if (timeout == 20000) 69026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov DRM_INFO("MIPI: HS CMD FIFO was never cleared!\n"); 70026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov} 71026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov 72026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemovstatic void mdfld_wait_for_DPI_CTRL_FIFO(struct drm_device *dev, u32 pipe) 73026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov{ 74026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov u32 gen_fifo_stat_reg = MIPI_GEN_FIFO_STAT_REG(pipe); 75026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov int timeout = 0; 76026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov 77026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov udelay(500); 78026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov 79026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov /* This will time out after approximately 2+ seconds */ 80026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov while ((timeout < 20000) && ((REG_READ(gen_fifo_stat_reg) & 81026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov DPI_FIFO_EMPTY) != DPI_FIFO_EMPTY)) { 82026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov udelay(100); 83026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov timeout++; 84026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov } 85026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov 86026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov if (timeout == 20000) 87026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov DRM_ERROR("MIPI: DPI FIFO was never cleared\n"); 88026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov} 89026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov 90026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemovstatic void mdfld_wait_for_SPL_PKG_SENT(struct drm_device *dev, u32 pipe) 91026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov{ 92026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov u32 intr_stat_reg = MIPI_INTR_STAT_REG(pipe); 93026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov int timeout = 0; 94026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov 95026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov udelay(500); 96026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov 97026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov /* This will time out after approximately 2+ seconds */ 98026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov while ((timeout < 20000) && (!(REG_READ(intr_stat_reg) 99026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov & DSI_INTR_STATE_SPL_PKG_SENT))) { 100026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov udelay(100); 101026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov timeout++; 102026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov } 103026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov 104026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov if (timeout == 20000) 105026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov DRM_ERROR("MIPI: SPL_PKT_SENT_INTERRUPT was not sent successfully!\n"); 106026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov} 107026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov 108026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov/* For TC35876X */ 109026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov 110026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemovstatic void dsi_set_device_ready_state(struct drm_device *dev, int state, 111026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov int pipe) 112026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov{ 113026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov REG_FLD_MOD(MIPI_DEVICE_READY_REG(pipe), !!state, 0, 0); 114026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov} 115026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov 116026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemovstatic void dsi_set_pipe_plane_enable_state(struct drm_device *dev, 117026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov int state, int pipe) 118026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov{ 119026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov struct drm_psb_private *dev_priv = dev->dev_private; 120026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov u32 pipeconf_reg = PIPEACONF; 121026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov u32 dspcntr_reg = DSPACNTR; 122026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov 123026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov u32 dspcntr = dev_priv->dspcntr[pipe]; 124026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov u32 mipi = MIPI_PORT_EN | PASS_FROM_SPHY_TO_AFE | SEL_FLOPPED_HSTX; 125026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov 126026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov if (pipe) { 127026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov pipeconf_reg = PIPECCONF; 128026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov dspcntr_reg = DSPCCNTR; 129026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov } else 130026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov mipi &= (~0x03); 131026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov 132026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov if (state) { 133026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov /*Set up pipe */ 134026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov REG_WRITE(pipeconf_reg, BIT(31)); 135026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov 136026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov if (REG_BIT_WAIT(pipeconf_reg, 1, 30)) 137026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov dev_err(&dev->pdev->dev, "%s: Pipe enable timeout\n", 138026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov __func__); 139026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov 140026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov /*Set up display plane */ 141026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov REG_WRITE(dspcntr_reg, dspcntr); 142026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov } else { 143026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov u32 dspbase_reg = pipe ? MDFLD_DSPCBASE : MRST_DSPABASE; 144026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov 145026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov /* Put DSI lanes to ULPS to disable pipe */ 146026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov REG_FLD_MOD(MIPI_DEVICE_READY_REG(pipe), 2, 2, 1); 147026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov REG_READ(MIPI_DEVICE_READY_REG(pipe)); /* posted write? */ 148026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov 149026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov /* LP Hold */ 150026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov REG_FLD_MOD(MIPI_PORT_CONTROL(pipe), 0, 16, 16); 151026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov REG_READ(MIPI_PORT_CONTROL(pipe)); /* posted write? */ 152026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov 153026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov /* Disable display plane */ 154026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov REG_FLD_MOD(dspcntr_reg, 0, 31, 31); 155026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov 156026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov /* Flush the plane changes ??? posted write? */ 157026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov REG_WRITE(dspbase_reg, REG_READ(dspbase_reg)); 158026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov REG_READ(dspbase_reg); 159026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov 160026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov /* Disable PIPE */ 161026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov REG_FLD_MOD(pipeconf_reg, 0, 31, 31); 162026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov 163026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov if (REG_BIT_WAIT(pipeconf_reg, 0, 30)) 164026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov dev_err(&dev->pdev->dev, "%s: Pipe disable timeout\n", 165026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov __func__); 166026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov 167026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov if (REG_BIT_WAIT(MIPI_GEN_FIFO_STAT_REG(pipe), 1, 28)) 168026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov dev_err(&dev->pdev->dev, "%s: FIFO not empty\n", 169026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov __func__); 170026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov } 171026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov} 172026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov 173026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemovstatic void mdfld_dsi_configure_down(struct mdfld_dsi_encoder *dsi_encoder, 174026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov int pipe) 175026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov{ 176026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov struct mdfld_dsi_dpi_output *dpi_output = 177026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov MDFLD_DSI_DPI_OUTPUT(dsi_encoder); 178026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov struct mdfld_dsi_config *dsi_config = 179026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov mdfld_dsi_encoder_get_config(dsi_encoder); 180026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov struct drm_device *dev = dsi_config->dev; 181026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov struct drm_psb_private *dev_priv = dev->dev_private; 182026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov 183026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov if (!dev_priv->dpi_panel_on[pipe]) { 184026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov dev_err(dev->dev, "DPI panel is already off\n"); 185026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov return; 186026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov } 187026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov tc35876x_toshiba_bridge_panel_off(dev); 188026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov tc35876x_set_bridge_reset_state(dev, 1); 189026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov dsi_set_pipe_plane_enable_state(dev, 0, pipe); 190026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov mdfld_dsi_dpi_shut_down(dpi_output, pipe); 191026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov dsi_set_device_ready_state(dev, 0, pipe); 192026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov} 193026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov 194026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemovstatic void mdfld_dsi_configure_up(struct mdfld_dsi_encoder *dsi_encoder, 195026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov int pipe) 196026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov{ 197026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov struct mdfld_dsi_dpi_output *dpi_output = 198026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov MDFLD_DSI_DPI_OUTPUT(dsi_encoder); 199026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov struct mdfld_dsi_config *dsi_config = 200026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov mdfld_dsi_encoder_get_config(dsi_encoder); 201026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov struct drm_device *dev = dsi_config->dev; 202026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov struct drm_psb_private *dev_priv = dev->dev_private; 203026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov 204026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov if (dev_priv->dpi_panel_on[pipe]) { 205026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov dev_err(dev->dev, "DPI panel is already on\n"); 206026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov return; 207026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov } 208026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov 209026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov /* For resume path sequence */ 210026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov mdfld_dsi_dpi_shut_down(dpi_output, pipe); 211026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov dsi_set_device_ready_state(dev, 0, pipe); 212026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov 213026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov dsi_set_device_ready_state(dev, 1, pipe); 214026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov tc35876x_set_bridge_reset_state(dev, 0); 215026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov tc35876x_configure_lvds_bridge(dev); 216026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov mdfld_dsi_dpi_turn_on(dpi_output, pipe); /* Send turn on command */ 217026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov dsi_set_pipe_plane_enable_state(dev, 1, pipe); 218026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov} 219026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov/* End for TC35876X */ 220026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov 221026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov/* ************************************************************************* *\ 222026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov * FUNCTION: mdfld_dsi_tpo_ic_init 223026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov * 224026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov * DESCRIPTION: This function is called only by mrst_dsi_mode_set and 225026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov * restore_display_registers. since this function does not 226026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov * acquire the mutex, it is important that the calling function 227026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov * does! 228026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov\* ************************************************************************* */ 229026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemovstatic void mdfld_dsi_tpo_ic_init(struct mdfld_dsi_config *dsi_config, u32 pipe) 230026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov{ 231026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov struct drm_device *dev = dsi_config->dev; 232026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov u32 dcsChannelNumber = dsi_config->channel_num; 233026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov u32 gen_data_reg = MIPI_HS_GEN_DATA_REG(pipe); 234026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov u32 gen_ctrl_reg = MIPI_HS_GEN_CTRL_REG(pipe); 235026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov u32 gen_ctrl_val = GEN_LONG_WRITE; 236026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov 237026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov DRM_INFO("Enter mrst init TPO MIPI display.\n"); 238026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov 239026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov gen_ctrl_val |= dcsChannelNumber << DCS_CHANNEL_NUMBER_POS; 240026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov 241026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov /* Flip page order */ 242026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov mdfld_wait_for_HS_DATA_FIFO(dev, pipe); 243026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov REG_WRITE(gen_data_reg, 0x00008036); 244026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov mdfld_wait_for_HS_CTRL_FIFO(dev, pipe); 245026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov REG_WRITE(gen_ctrl_reg, gen_ctrl_val | (0x02 << WORD_COUNTS_POS)); 246026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov 247026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov /* 0xF0 */ 248026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov mdfld_wait_for_HS_DATA_FIFO(dev, pipe); 249026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov REG_WRITE(gen_data_reg, 0x005a5af0); 250026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov mdfld_wait_for_HS_CTRL_FIFO(dev, pipe); 251026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov REG_WRITE(gen_ctrl_reg, gen_ctrl_val | (0x03 << WORD_COUNTS_POS)); 252026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov 253026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov /* Write protection key */ 254026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov mdfld_wait_for_HS_DATA_FIFO(dev, pipe); 255026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov REG_WRITE(gen_data_reg, 0x005a5af1); 256026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov mdfld_wait_for_HS_CTRL_FIFO(dev, pipe); 257026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov REG_WRITE(gen_ctrl_reg, gen_ctrl_val | (0x03 << WORD_COUNTS_POS)); 258026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov 259026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov /* 0xFC */ 260026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov mdfld_wait_for_HS_DATA_FIFO(dev, pipe); 261026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov REG_WRITE(gen_data_reg, 0x005a5afc); 262026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov mdfld_wait_for_HS_CTRL_FIFO(dev, pipe); 263026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov REG_WRITE(gen_ctrl_reg, gen_ctrl_val | (0x03 << WORD_COUNTS_POS)); 264026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov 265026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov /* 0xB7 */ 266026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov mdfld_wait_for_HS_DATA_FIFO(dev, pipe); 267026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov REG_WRITE(gen_data_reg, 0x770000b7); 268026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov mdfld_wait_for_HS_DATA_FIFO(dev, pipe); 269026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov REG_WRITE(gen_data_reg, 0x00000044); 270026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov mdfld_wait_for_HS_CTRL_FIFO(dev, pipe); 271026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov REG_WRITE(gen_ctrl_reg, gen_ctrl_val | (0x05 << WORD_COUNTS_POS)); 272026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov 273026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov /* 0xB6 */ 274026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov mdfld_wait_for_HS_DATA_FIFO(dev, pipe); 275026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov REG_WRITE(gen_data_reg, 0x000a0ab6); 276026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov mdfld_wait_for_HS_CTRL_FIFO(dev, pipe); 277026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov REG_WRITE(gen_ctrl_reg, gen_ctrl_val | (0x03 << WORD_COUNTS_POS)); 278026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov 279026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov /* 0xF2 */ 280026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov mdfld_wait_for_HS_DATA_FIFO(dev, pipe); 281026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov REG_WRITE(gen_data_reg, 0x081010f2); 282026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov mdfld_wait_for_HS_DATA_FIFO(dev, pipe); 283026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov REG_WRITE(gen_data_reg, 0x4a070708); 284026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov mdfld_wait_for_HS_DATA_FIFO(dev, pipe); 285026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov REG_WRITE(gen_data_reg, 0x000000c5); 286026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov mdfld_wait_for_HS_CTRL_FIFO(dev, pipe); 287026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov REG_WRITE(gen_ctrl_reg, gen_ctrl_val | (0x09 << WORD_COUNTS_POS)); 288026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov 289026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov /* 0xF8 */ 290026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov mdfld_wait_for_HS_DATA_FIFO(dev, pipe); 291026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov REG_WRITE(gen_data_reg, 0x024003f8); 292026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov mdfld_wait_for_HS_DATA_FIFO(dev, pipe); 293026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov REG_WRITE(gen_data_reg, 0x01030a04); 294026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov mdfld_wait_for_HS_DATA_FIFO(dev, pipe); 295026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov REG_WRITE(gen_data_reg, 0x0e020220); 296026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov mdfld_wait_for_HS_DATA_FIFO(dev, pipe); 297026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov REG_WRITE(gen_data_reg, 0x00000004); 298026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov mdfld_wait_for_HS_CTRL_FIFO(dev, pipe); 299026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov REG_WRITE(gen_ctrl_reg, gen_ctrl_val | (0x0d << WORD_COUNTS_POS)); 300026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov 301026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov /* 0xE2 */ 302026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov mdfld_wait_for_HS_DATA_FIFO(dev, pipe); 303026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov REG_WRITE(gen_data_reg, 0x398fc3e2); 304026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov mdfld_wait_for_HS_DATA_FIFO(dev, pipe); 305026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov REG_WRITE(gen_data_reg, 0x0000916f); 306026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov mdfld_wait_for_HS_CTRL_FIFO(dev, pipe); 307026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov REG_WRITE(gen_ctrl_reg, gen_ctrl_val | (0x06 << WORD_COUNTS_POS)); 308026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov 309026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov /* 0xB0 */ 310026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov mdfld_wait_for_HS_DATA_FIFO(dev, pipe); 311026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov REG_WRITE(gen_data_reg, 0x000000b0); 312026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov mdfld_wait_for_HS_CTRL_FIFO(dev, pipe); 313026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov REG_WRITE(gen_ctrl_reg, gen_ctrl_val | (0x02 << WORD_COUNTS_POS)); 314026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov 315026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov /* 0xF4 */ 316026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov mdfld_wait_for_HS_DATA_FIFO(dev, pipe); 317026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov REG_WRITE(gen_data_reg, 0x240242f4); 318026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov mdfld_wait_for_HS_DATA_FIFO(dev, pipe); 319026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov REG_WRITE(gen_data_reg, 0x78ee2002); 320026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov mdfld_wait_for_HS_DATA_FIFO(dev, pipe); 321026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov REG_WRITE(gen_data_reg, 0x2a071050); 322026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov mdfld_wait_for_HS_DATA_FIFO(dev, pipe); 323026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov REG_WRITE(gen_data_reg, 0x507fee10); 324026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov mdfld_wait_for_HS_DATA_FIFO(dev, pipe); 325026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov REG_WRITE(gen_data_reg, 0x10300710); 326026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov mdfld_wait_for_HS_CTRL_FIFO(dev, pipe); 327026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov REG_WRITE(gen_ctrl_reg, gen_ctrl_val | (0x14 << WORD_COUNTS_POS)); 328026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov 329026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov /* 0xBA */ 330026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov mdfld_wait_for_HS_DATA_FIFO(dev, pipe); 331026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov REG_WRITE(gen_data_reg, 0x19fe07ba); 332026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov mdfld_wait_for_HS_DATA_FIFO(dev, pipe); 333026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov REG_WRITE(gen_data_reg, 0x101c0a31); 334026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov mdfld_wait_for_HS_DATA_FIFO(dev, pipe); 335026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov REG_WRITE(gen_data_reg, 0x00000010); 336026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov mdfld_wait_for_HS_CTRL_FIFO(dev, pipe); 337026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov REG_WRITE(gen_ctrl_reg, gen_ctrl_val | (0x09 << WORD_COUNTS_POS)); 338026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov 339026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov /* 0xBB */ 340026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov mdfld_wait_for_HS_DATA_FIFO(dev, pipe); 341026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov REG_WRITE(gen_data_reg, 0x28ff07bb); 342026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov mdfld_wait_for_HS_DATA_FIFO(dev, pipe); 343026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov REG_WRITE(gen_data_reg, 0x24280a31); 344026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov mdfld_wait_for_HS_DATA_FIFO(dev, pipe); 345026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov REG_WRITE(gen_data_reg, 0x00000034); 346026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov mdfld_wait_for_HS_CTRL_FIFO(dev, pipe); 347026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov REG_WRITE(gen_ctrl_reg, gen_ctrl_val | (0x09 << WORD_COUNTS_POS)); 348026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov 349026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov /* 0xFB */ 350026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov mdfld_wait_for_HS_DATA_FIFO(dev, pipe); 351026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov REG_WRITE(gen_data_reg, 0x535d05fb); 352026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov mdfld_wait_for_HS_DATA_FIFO(dev, pipe); 353026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov REG_WRITE(gen_data_reg, 0x1b1a2130); 354026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov mdfld_wait_for_HS_DATA_FIFO(dev, pipe); 355026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov REG_WRITE(gen_data_reg, 0x221e180e); 356026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov mdfld_wait_for_HS_DATA_FIFO(dev, pipe); 357026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov REG_WRITE(gen_data_reg, 0x131d2120); 358026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov mdfld_wait_for_HS_DATA_FIFO(dev, pipe); 359026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov REG_WRITE(gen_data_reg, 0x535d0508); 360026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov mdfld_wait_for_HS_DATA_FIFO(dev, pipe); 361026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov REG_WRITE(gen_data_reg, 0x1c1a2131); 362026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov mdfld_wait_for_HS_DATA_FIFO(dev, pipe); 363026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov REG_WRITE(gen_data_reg, 0x231f160d); 364026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov mdfld_wait_for_HS_DATA_FIFO(dev, pipe); 365026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov REG_WRITE(gen_data_reg, 0x111b2220); 366026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov mdfld_wait_for_HS_DATA_FIFO(dev, pipe); 367026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov REG_WRITE(gen_data_reg, 0x535c2008); 368026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov mdfld_wait_for_HS_DATA_FIFO(dev, pipe); 369026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov REG_WRITE(gen_data_reg, 0x1f1d2433); 370026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov mdfld_wait_for_HS_DATA_FIFO(dev, pipe); 371026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov REG_WRITE(gen_data_reg, 0x2c251a10); 372026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov mdfld_wait_for_HS_DATA_FIFO(dev, pipe); 373026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov REG_WRITE(gen_data_reg, 0x2c34372d); 374026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov mdfld_wait_for_HS_DATA_FIFO(dev, pipe); 375026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov REG_WRITE(gen_data_reg, 0x00000023); 376026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov mdfld_wait_for_HS_CTRL_FIFO(dev, pipe); 377026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov REG_WRITE(gen_ctrl_reg, gen_ctrl_val | (0x31 << WORD_COUNTS_POS)); 378026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov 379026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov /* 0xFA */ 380026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov mdfld_wait_for_HS_DATA_FIFO(dev, pipe); 381026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov REG_WRITE(gen_data_reg, 0x525c0bfa); 382026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov mdfld_wait_for_HS_DATA_FIFO(dev, pipe); 383026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov REG_WRITE(gen_data_reg, 0x1c1c232f); 384026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov mdfld_wait_for_HS_DATA_FIFO(dev, pipe); 385026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov REG_WRITE(gen_data_reg, 0x2623190e); 386026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov mdfld_wait_for_HS_DATA_FIFO(dev, pipe); 387026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov REG_WRITE(gen_data_reg, 0x18212625); 388026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov mdfld_wait_for_HS_DATA_FIFO(dev, pipe); 389026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov REG_WRITE(gen_data_reg, 0x545d0d0e); 390026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov mdfld_wait_for_HS_DATA_FIFO(dev, pipe); 391026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov REG_WRITE(gen_data_reg, 0x1e1d2333); 392026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov mdfld_wait_for_HS_DATA_FIFO(dev, pipe); 393026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov REG_WRITE(gen_data_reg, 0x26231a10); 394026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov mdfld_wait_for_HS_DATA_FIFO(dev, pipe); 395026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov REG_WRITE(gen_data_reg, 0x1a222725); 396026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov mdfld_wait_for_HS_DATA_FIFO(dev, pipe); 397026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov REG_WRITE(gen_data_reg, 0x545d280f); 398026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov mdfld_wait_for_HS_DATA_FIFO(dev, pipe); 399026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov REG_WRITE(gen_data_reg, 0x21202635); 400026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov mdfld_wait_for_HS_DATA_FIFO(dev, pipe); 401026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov REG_WRITE(gen_data_reg, 0x31292013); 402026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov mdfld_wait_for_HS_DATA_FIFO(dev, pipe); 403026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov REG_WRITE(gen_data_reg, 0x31393d33); 404026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov mdfld_wait_for_HS_DATA_FIFO(dev, pipe); 405026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov REG_WRITE(gen_data_reg, 0x00000029); 406026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov mdfld_wait_for_HS_CTRL_FIFO(dev, pipe); 407026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov REG_WRITE(gen_ctrl_reg, gen_ctrl_val | (0x31 << WORD_COUNTS_POS)); 408026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov 409026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov /* Set DM */ 410026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov mdfld_wait_for_HS_DATA_FIFO(dev, pipe); 411026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov REG_WRITE(gen_data_reg, 0x000100f7); 412026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov mdfld_wait_for_HS_CTRL_FIFO(dev, pipe); 413026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov REG_WRITE(gen_ctrl_reg, gen_ctrl_val | (0x03 << WORD_COUNTS_POS)); 414026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov} 415026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov 416026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemovstatic u16 mdfld_dsi_dpi_to_byte_clock_count(int pixel_clock_count, 417026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov int num_lane, int bpp) 418026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov{ 419026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov return (u16)((pixel_clock_count * bpp) / (num_lane * 8)); 420026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov} 421026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov 422026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov/* 423026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov * Calculate the dpi time basing on a given drm mode @mode 424026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov * return 0 on success. 425026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov * FIXME: I was using proposed mode value for calculation, may need to 426026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov * use crtc mode values later 427026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov */ 428026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemovint mdfld_dsi_dpi_timing_calculation(struct drm_display_mode *mode, 429026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov struct mdfld_dsi_dpi_timing *dpi_timing, 430026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov int num_lane, int bpp) 431026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov{ 432026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov int pclk_hsync, pclk_hfp, pclk_hbp, pclk_hactive; 433e4b9ff716fd6b49b062884e339882efe305e922fKirill A. Shutemov int pclk_vsync, pclk_vfp, pclk_vbp; 434026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov 435026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov pclk_hactive = mode->hdisplay; 436026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov pclk_hfp = mode->hsync_start - mode->hdisplay; 437026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov pclk_hsync = mode->hsync_end - mode->hsync_start; 438026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov pclk_hbp = mode->htotal - mode->hsync_end; 439026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov 440026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov pclk_vfp = mode->vsync_start - mode->vdisplay; 441026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov pclk_vsync = mode->vsync_end - mode->vsync_start; 442026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov pclk_vbp = mode->vtotal - mode->vsync_end; 443026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov 444026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov /* 445026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov * byte clock counts were calculated by following formula 446026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov * bclock_count = pclk_count * bpp / num_lane / 8 447026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov */ 448026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov dpi_timing->hsync_count = mdfld_dsi_dpi_to_byte_clock_count( 449026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov pclk_hsync, num_lane, bpp); 450026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov dpi_timing->hbp_count = mdfld_dsi_dpi_to_byte_clock_count( 451026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov pclk_hbp, num_lane, bpp); 452026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov dpi_timing->hfp_count = mdfld_dsi_dpi_to_byte_clock_count( 453026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov pclk_hfp, num_lane, bpp); 454026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov dpi_timing->hactive_count = mdfld_dsi_dpi_to_byte_clock_count( 455026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov pclk_hactive, num_lane, bpp); 456026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov dpi_timing->vsync_count = mdfld_dsi_dpi_to_byte_clock_count( 457026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov pclk_vsync, num_lane, bpp); 458026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov dpi_timing->vbp_count = mdfld_dsi_dpi_to_byte_clock_count( 459026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov pclk_vbp, num_lane, bpp); 460026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov dpi_timing->vfp_count = mdfld_dsi_dpi_to_byte_clock_count( 461026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov pclk_vfp, num_lane, bpp); 462026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov 463026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov return 0; 464026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov} 465026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov 466026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemovvoid mdfld_dsi_dpi_controller_init(struct mdfld_dsi_config *dsi_config, 467026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov int pipe) 468026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov{ 469026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov struct drm_device *dev = dsi_config->dev; 470026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov int lane_count = dsi_config->lane_count; 471026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov struct mdfld_dsi_dpi_timing dpi_timing; 472026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov struct drm_display_mode *mode = dsi_config->mode; 473026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov u32 val; 474026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov 475026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov /*un-ready device*/ 476026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov REG_FLD_MOD(MIPI_DEVICE_READY_REG(pipe), 0, 0, 0); 477026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov 478026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov /*init dsi adapter before kicking off*/ 479026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov REG_WRITE(MIPI_CTRL_REG(pipe), 0x00000018); 480026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov 481026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov /*enable all interrupts*/ 482026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov REG_WRITE(MIPI_INTR_EN_REG(pipe), 0xffffffff); 483026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov 484026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov /*set up func_prg*/ 485026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov val = lane_count; 486026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov val |= dsi_config->channel_num << DSI_DPI_VIRT_CHANNEL_OFFSET; 487026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov 488026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov switch (dsi_config->bpp) { 489026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov case 16: 490026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov val |= DSI_DPI_COLOR_FORMAT_RGB565; 491026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov break; 492026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov case 18: 493026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov val |= DSI_DPI_COLOR_FORMAT_RGB666; 494026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov break; 495026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov case 24: 496026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov val |= DSI_DPI_COLOR_FORMAT_RGB888; 497026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov break; 498026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov default: 499026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov DRM_ERROR("unsupported color format, bpp = %d\n", 500026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov dsi_config->bpp); 501026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov } 502026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov REG_WRITE(MIPI_DSI_FUNC_PRG_REG(pipe), val); 503026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov 504026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov REG_WRITE(MIPI_HS_TX_TIMEOUT_REG(pipe), 505026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov (mode->vtotal * mode->htotal * dsi_config->bpp / 506026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov (8 * lane_count)) & DSI_HS_TX_TIMEOUT_MASK); 507026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov REG_WRITE(MIPI_LP_RX_TIMEOUT_REG(pipe), 508026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov 0xffff & DSI_LP_RX_TIMEOUT_MASK); 509026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov 510026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov /*max value: 20 clock cycles of txclkesc*/ 511026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov REG_WRITE(MIPI_TURN_AROUND_TIMEOUT_REG(pipe), 512026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov 0x14 & DSI_TURN_AROUND_TIMEOUT_MASK); 513026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov 514026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov /*min 21 txclkesc, max: ffffh*/ 515026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov REG_WRITE(MIPI_DEVICE_RESET_TIMER_REG(pipe), 516026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov 0xffff & DSI_RESET_TIMER_MASK); 517026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov 518026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov REG_WRITE(MIPI_DPI_RESOLUTION_REG(pipe), 519026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov mode->vdisplay << 16 | mode->hdisplay); 520026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov 521026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov /*set DPI timing registers*/ 522026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov mdfld_dsi_dpi_timing_calculation(mode, &dpi_timing, 523026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov dsi_config->lane_count, dsi_config->bpp); 524026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov 525026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov REG_WRITE(MIPI_HSYNC_COUNT_REG(pipe), 526026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov dpi_timing.hsync_count & DSI_DPI_TIMING_MASK); 527026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov REG_WRITE(MIPI_HBP_COUNT_REG(pipe), 528026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov dpi_timing.hbp_count & DSI_DPI_TIMING_MASK); 529026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov REG_WRITE(MIPI_HFP_COUNT_REG(pipe), 530026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov dpi_timing.hfp_count & DSI_DPI_TIMING_MASK); 531026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov REG_WRITE(MIPI_HACTIVE_COUNT_REG(pipe), 532026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov dpi_timing.hactive_count & DSI_DPI_TIMING_MASK); 533026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov REG_WRITE(MIPI_VSYNC_COUNT_REG(pipe), 534026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov dpi_timing.vsync_count & DSI_DPI_TIMING_MASK); 535026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov REG_WRITE(MIPI_VBP_COUNT_REG(pipe), 536026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov dpi_timing.vbp_count & DSI_DPI_TIMING_MASK); 537026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov REG_WRITE(MIPI_VFP_COUNT_REG(pipe), 538026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov dpi_timing.vfp_count & DSI_DPI_TIMING_MASK); 539026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov 540026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov REG_WRITE(MIPI_HIGH_LOW_SWITCH_COUNT_REG(pipe), 0x46); 541026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov 542026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov /*min: 7d0 max: 4e20*/ 543026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov REG_WRITE(MIPI_INIT_COUNT_REG(pipe), 0x000007d0); 544026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov 545026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov /*set up video mode*/ 546026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov val = dsi_config->video_mode | DSI_DPI_COMPLETE_LAST_LINE; 547026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov REG_WRITE(MIPI_VIDEO_MODE_FORMAT_REG(pipe), val); 548026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov 549026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov REG_WRITE(MIPI_EOT_DISABLE_REG(pipe), 0x00000000); 550026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov 551026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov REG_WRITE(MIPI_LP_BYTECLK_REG(pipe), 0x00000004); 552026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov 553026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov /*TODO: figure out how to setup these registers*/ 554026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov if (mdfld_get_panel_type(dev, pipe) == TC35876X) 555026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov REG_WRITE(MIPI_DPHY_PARAM_REG(pipe), 0x2A0c6008); 556026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov else 557026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov REG_WRITE(MIPI_DPHY_PARAM_REG(pipe), 0x150c3408); 558026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov 559026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov REG_WRITE(MIPI_CLK_LANE_SWITCH_TIME_CNT_REG(pipe), (0xa << 16) | 0x14); 560026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov 561026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov if (mdfld_get_panel_type(dev, pipe) == TC35876X) 562026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov tc35876x_set_bridge_reset_state(dev, 0); /*Pull High Reset */ 563026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov 564026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov /*set device ready*/ 565026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov REG_FLD_MOD(MIPI_DEVICE_READY_REG(pipe), 1, 0, 0); 566026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov} 567026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov 568026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemovvoid mdfld_dsi_dpi_turn_on(struct mdfld_dsi_dpi_output *output, int pipe) 569026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov{ 570026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov struct drm_device *dev = output->dev; 571026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov 572026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov /* clear special packet sent bit */ 573026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov if (REG_READ(MIPI_INTR_STAT_REG(pipe)) & DSI_INTR_STATE_SPL_PKG_SENT) 574026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov REG_WRITE(MIPI_INTR_STAT_REG(pipe), 575026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov DSI_INTR_STATE_SPL_PKG_SENT); 576026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov 577026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov /*send turn on package*/ 578026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov REG_WRITE(MIPI_DPI_CONTROL_REG(pipe), DSI_DPI_CTRL_HS_TURN_ON); 579026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov 580026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov /*wait for SPL_PKG_SENT interrupt*/ 581026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov mdfld_wait_for_SPL_PKG_SENT(dev, pipe); 582026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov 583026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov if (REG_READ(MIPI_INTR_STAT_REG(pipe)) & DSI_INTR_STATE_SPL_PKG_SENT) 584026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov REG_WRITE(MIPI_INTR_STAT_REG(pipe), 585026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov DSI_INTR_STATE_SPL_PKG_SENT); 586026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov 587026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov output->panel_on = 1; 588026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov 589026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov /* FIXME the following is disabled to WA the X slow start issue 590026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov for TMD panel 591026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov if (pipe == 2) 592026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov dev_priv->dpi_panel_on2 = true; 593026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov else if (pipe == 0) 594026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov dev_priv->dpi_panel_on = true; */ 595026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov} 596026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov 597026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemovstatic void mdfld_dsi_dpi_shut_down(struct mdfld_dsi_dpi_output *output, 598026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov int pipe) 599026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov{ 600026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov struct drm_device *dev = output->dev; 601026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov 602026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov /*if output is on, or mode setting didn't happen, ignore this*/ 603026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov if ((!output->panel_on) || output->first_boot) { 604026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov output->first_boot = 0; 605026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov return; 606026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov } 607026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov 608026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov /* Wait for dpi fifo to empty */ 609026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov mdfld_wait_for_DPI_CTRL_FIFO(dev, pipe); 610026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov 611026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov /* Clear the special packet interrupt bit if set */ 612026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov if (REG_READ(MIPI_INTR_STAT_REG(pipe)) & DSI_INTR_STATE_SPL_PKG_SENT) 613026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov REG_WRITE(MIPI_INTR_STAT_REG(pipe), 614026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov DSI_INTR_STATE_SPL_PKG_SENT); 615026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov 616026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov if (REG_READ(MIPI_DPI_CONTROL_REG(pipe)) == DSI_DPI_CTRL_HS_SHUTDOWN) 617026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov goto shutdown_out; 618026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov 619026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov REG_WRITE(MIPI_DPI_CONTROL_REG(pipe), DSI_DPI_CTRL_HS_SHUTDOWN); 620026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov 621026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemovshutdown_out: 622026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov output->panel_on = 0; 623026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov output->first_boot = 0; 624026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov 625026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov /* FIXME the following is disabled to WA the X slow start issue 626026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov for TMD panel 627026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov if (pipe == 2) 628026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov dev_priv->dpi_panel_on2 = false; 629026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov else if (pipe == 0) 630026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov dev_priv->dpi_panel_on = false; */ 631026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov} 632026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov 633026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemovstatic void mdfld_dsi_dpi_set_power(struct drm_encoder *encoder, bool on) 634026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov{ 635026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov struct mdfld_dsi_encoder *dsi_encoder = mdfld_dsi_encoder(encoder); 636026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov struct mdfld_dsi_dpi_output *dpi_output = 637026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov MDFLD_DSI_DPI_OUTPUT(dsi_encoder); 638026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov struct mdfld_dsi_config *dsi_config = 639026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov mdfld_dsi_encoder_get_config(dsi_encoder); 640026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov int pipe = mdfld_dsi_encoder_get_pipe(dsi_encoder); 641026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov struct drm_device *dev = dsi_config->dev; 642026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov struct drm_psb_private *dev_priv = dev->dev_private; 643026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov 644026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov /*start up display island if it was shutdown*/ 645026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov if (!gma_power_begin(dev, true)) 646026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov return; 647026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov 648026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov if (on) { 649026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov if (mdfld_get_panel_type(dev, pipe) == TMD_VID) 650026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov mdfld_dsi_dpi_turn_on(dpi_output, pipe); 651026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov else if (mdfld_get_panel_type(dev, pipe) == TC35876X) 652026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov mdfld_dsi_configure_up(dsi_encoder, pipe); 653026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov else { 654026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov /*enable mipi port*/ 655026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov REG_WRITE(MIPI_PORT_CONTROL(pipe), 656026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov REG_READ(MIPI_PORT_CONTROL(pipe)) | BIT(31)); 657026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov REG_READ(MIPI_PORT_CONTROL(pipe)); 658026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov 659026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov mdfld_dsi_dpi_turn_on(dpi_output, pipe); 660026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov mdfld_dsi_tpo_ic_init(dsi_config, pipe); 661026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov } 662026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov dev_priv->dpi_panel_on[pipe] = true; 663026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov } else { 664026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov if (mdfld_get_panel_type(dev, pipe) == TMD_VID) 665026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov mdfld_dsi_dpi_shut_down(dpi_output, pipe); 666026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov else if (mdfld_get_panel_type(dev, pipe) == TC35876X) 667026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov mdfld_dsi_configure_down(dsi_encoder, pipe); 668026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov else { 669026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov mdfld_dsi_dpi_shut_down(dpi_output, pipe); 670026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov 671026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov /*disable mipi port*/ 672026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov REG_WRITE(MIPI_PORT_CONTROL(pipe), 673026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov REG_READ(MIPI_PORT_CONTROL(pipe)) & ~BIT(31)); 674026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov REG_READ(MIPI_PORT_CONTROL(pipe)); 675026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov } 676026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov dev_priv->dpi_panel_on[pipe] = false; 677026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov } 678026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov gma_power_end(dev); 679026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov} 680026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov 681026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemovvoid mdfld_dsi_dpi_dpms(struct drm_encoder *encoder, int mode) 682026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov{ 683026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov mdfld_dsi_dpi_set_power(encoder, mode == DRM_MODE_DPMS_ON); 684026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov} 685026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov 686026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemovbool mdfld_dsi_dpi_mode_fixup(struct drm_encoder *encoder, 687e811f5ae19043b2ac2c28e147a4274038e655598Laurent Pinchart const struct drm_display_mode *mode, 688026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov struct drm_display_mode *adjusted_mode) 689026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov{ 690026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov struct mdfld_dsi_encoder *dsi_encoder = mdfld_dsi_encoder(encoder); 691026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov struct mdfld_dsi_config *dsi_config = 692026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov mdfld_dsi_encoder_get_config(dsi_encoder); 693026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov struct drm_display_mode *fixed_mode = dsi_config->fixed_mode; 694026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov 695026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov if (fixed_mode) { 696026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov adjusted_mode->hdisplay = fixed_mode->hdisplay; 697026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov adjusted_mode->hsync_start = fixed_mode->hsync_start; 698026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov adjusted_mode->hsync_end = fixed_mode->hsync_end; 699026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov adjusted_mode->htotal = fixed_mode->htotal; 700026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov adjusted_mode->vdisplay = fixed_mode->vdisplay; 701026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov adjusted_mode->vsync_start = fixed_mode->vsync_start; 702026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov adjusted_mode->vsync_end = fixed_mode->vsync_end; 703026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov adjusted_mode->vtotal = fixed_mode->vtotal; 704026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov adjusted_mode->clock = fixed_mode->clock; 705026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov drm_mode_set_crtcinfo(adjusted_mode, CRTC_INTERLACE_HALVE_V); 706026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov } 707026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov return true; 708026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov} 709026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov 710026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemovvoid mdfld_dsi_dpi_prepare(struct drm_encoder *encoder) 711026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov{ 712026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov mdfld_dsi_dpi_set_power(encoder, false); 713026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov} 714026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov 715026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemovvoid mdfld_dsi_dpi_commit(struct drm_encoder *encoder) 716026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov{ 717026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov mdfld_dsi_dpi_set_power(encoder, true); 718026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov} 719026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov 720026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov/* For TC35876X */ 721026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov/* This functionality was implemented in FW in iCDK */ 722026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov/* But removed in DV0 and later. So need to add here. */ 723026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemovstatic void mipi_set_properties(struct mdfld_dsi_config *dsi_config, int pipe) 724026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov{ 725026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov struct drm_device *dev = dsi_config->dev; 726026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov 727026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov REG_WRITE(MIPI_CTRL_REG(pipe), 0x00000018); 728026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov REG_WRITE(MIPI_INTR_EN_REG(pipe), 0xffffffff); 729026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov REG_WRITE(MIPI_HS_TX_TIMEOUT_REG(pipe), 0xffffff); 730026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov REG_WRITE(MIPI_LP_RX_TIMEOUT_REG(pipe), 0xffffff); 731026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov REG_WRITE(MIPI_TURN_AROUND_TIMEOUT_REG(pipe), 0x14); 732026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov REG_WRITE(MIPI_DEVICE_RESET_TIMER_REG(pipe), 0xff); 733026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov REG_WRITE(MIPI_HIGH_LOW_SWITCH_COUNT_REG(pipe), 0x25); 734026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov REG_WRITE(MIPI_INIT_COUNT_REG(pipe), 0xf0); 735026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov REG_WRITE(MIPI_EOT_DISABLE_REG(pipe), 0x00000000); 736026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov REG_WRITE(MIPI_LP_BYTECLK_REG(pipe), 0x00000004); 737026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov REG_WRITE(MIPI_DBI_BW_CTRL_REG(pipe), 0x00000820); 738026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov REG_WRITE(MIPI_CLK_LANE_SWITCH_TIME_CNT_REG(pipe), (0xa << 16) | 0x14); 739026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov} 740026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov 741026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemovstatic void mdfld_mipi_set_video_timing(struct mdfld_dsi_config *dsi_config, 742026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov int pipe) 743026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov{ 744026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov struct drm_device *dev = dsi_config->dev; 745026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov struct mdfld_dsi_dpi_timing dpi_timing; 746026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov struct drm_display_mode *mode = dsi_config->mode; 747026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov 748026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov mdfld_dsi_dpi_timing_calculation(mode, &dpi_timing, 749026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov dsi_config->lane_count, 750026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov dsi_config->bpp); 751026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov 752026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov REG_WRITE(MIPI_DPI_RESOLUTION_REG(pipe), 753026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov mode->vdisplay << 16 | mode->hdisplay); 754026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov REG_WRITE(MIPI_HSYNC_COUNT_REG(pipe), 755026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov dpi_timing.hsync_count & DSI_DPI_TIMING_MASK); 756026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov REG_WRITE(MIPI_HBP_COUNT_REG(pipe), 757026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov dpi_timing.hbp_count & DSI_DPI_TIMING_MASK); 758026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov REG_WRITE(MIPI_HFP_COUNT_REG(pipe), 759026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov dpi_timing.hfp_count & DSI_DPI_TIMING_MASK); 760026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov REG_WRITE(MIPI_HACTIVE_COUNT_REG(pipe), 761026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov dpi_timing.hactive_count & DSI_DPI_TIMING_MASK); 762026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov REG_WRITE(MIPI_VSYNC_COUNT_REG(pipe), 763026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov dpi_timing.vsync_count & DSI_DPI_TIMING_MASK); 764026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov REG_WRITE(MIPI_VBP_COUNT_REG(pipe), 765026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov dpi_timing.vbp_count & DSI_DPI_TIMING_MASK); 766026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov REG_WRITE(MIPI_VFP_COUNT_REG(pipe), 767026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov dpi_timing.vfp_count & DSI_DPI_TIMING_MASK); 768026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov} 769026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov 770026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemovstatic void mdfld_mipi_config(struct mdfld_dsi_config *dsi_config, int pipe) 771026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov{ 772026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov struct drm_device *dev = dsi_config->dev; 773026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov int lane_count = dsi_config->lane_count; 774026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov 775026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov if (pipe) { 776026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov REG_WRITE(MIPI_PORT_CONTROL(0), 0x00000002); 777026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov REG_WRITE(MIPI_PORT_CONTROL(2), 0x80000000); 778026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov } else { 779026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov REG_WRITE(MIPI_PORT_CONTROL(0), 0x80010000); 780026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov REG_WRITE(MIPI_PORT_CONTROL(2), 0x00); 781026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov } 782026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov 783026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov REG_WRITE(MIPI_DPHY_PARAM_REG(pipe), 0x150A600F); 784026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov REG_WRITE(MIPI_VIDEO_MODE_FORMAT_REG(pipe), 0x0000000F); 785026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov 786026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov /* lane_count = 3 */ 787026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov REG_WRITE(MIPI_DSI_FUNC_PRG_REG(pipe), 0x00000200 | lane_count); 788026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov 789026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov mdfld_mipi_set_video_timing(dsi_config, pipe); 790026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov} 791026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov 792026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemovstatic void mdfld_set_pipe_timing(struct mdfld_dsi_config *dsi_config, int pipe) 793026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov{ 794026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov struct drm_device *dev = dsi_config->dev; 795026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov struct drm_display_mode *mode = dsi_config->mode; 796026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov 797026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov REG_WRITE(HTOTAL_A, ((mode->htotal - 1) << 16) | (mode->hdisplay - 1)); 798026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov REG_WRITE(HBLANK_A, ((mode->htotal - 1) << 16) | (mode->hdisplay - 1)); 799026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov REG_WRITE(HSYNC_A, 800026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov ((mode->hsync_end - 1) << 16) | (mode->hsync_start - 1)); 801026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov 802026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov REG_WRITE(VTOTAL_A, ((mode->vtotal - 1) << 16) | (mode->vdisplay - 1)); 803026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov REG_WRITE(VBLANK_A, ((mode->vtotal - 1) << 16) | (mode->vdisplay - 1)); 804026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov REG_WRITE(VSYNC_A, 805026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov ((mode->vsync_end - 1) << 16) | (mode->vsync_start - 1)); 806026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov 807026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov REG_WRITE(PIPEASRC, 808026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1)); 809026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov} 810026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov/* End for TC35876X */ 811026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov 812026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemovvoid mdfld_dsi_dpi_mode_set(struct drm_encoder *encoder, 813026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov struct drm_display_mode *mode, 814026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov struct drm_display_mode *adjusted_mode) 815026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov{ 816026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov struct mdfld_dsi_encoder *dsi_encoder = mdfld_dsi_encoder(encoder); 817026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov struct mdfld_dsi_dpi_output *dpi_output = 818026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov MDFLD_DSI_DPI_OUTPUT(dsi_encoder); 819026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov struct mdfld_dsi_config *dsi_config = 820026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov mdfld_dsi_encoder_get_config(dsi_encoder); 821026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov struct drm_device *dev = dsi_config->dev; 822026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov struct drm_psb_private *dev_priv = dev->dev_private; 823026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov int pipe = mdfld_dsi_encoder_get_pipe(dsi_encoder); 824026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov 825026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov u32 pipeconf_reg = PIPEACONF; 826026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov u32 dspcntr_reg = DSPACNTR; 827026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov 828026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov u32 pipeconf = dev_priv->pipeconf[pipe]; 829026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov u32 dspcntr = dev_priv->dspcntr[pipe]; 830026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov u32 mipi = MIPI_PORT_EN | PASS_FROM_SPHY_TO_AFE | SEL_FLOPPED_HSTX; 831026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov 832026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov if (pipe) { 833026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov pipeconf_reg = PIPECCONF; 834026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov dspcntr_reg = DSPCCNTR; 835026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov } else { 836026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov if (mdfld_get_panel_type(dev, pipe) == TC35876X) 837026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov mipi &= (~0x03); /* Use all four lanes */ 838026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov else 839026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov mipi |= 2; 840026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov } 841026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov 842026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov /*start up display island if it was shutdown*/ 843026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov if (!gma_power_begin(dev, true)) 844026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov return; 845026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov 846026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov if (mdfld_get_panel_type(dev, pipe) == TC35876X) { 847026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov /* 848026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov * The following logic is required to reset the bridge and 849026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov * configure. This also starts the DSI clock at 200MHz. 850026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov */ 851026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov tc35876x_set_bridge_reset_state(dev, 0); /*Pull High Reset */ 852026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov tc35876x_toshiba_bridge_panel_on(dev); 853026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov udelay(100); 854026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov /* Now start the DSI clock */ 855026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov REG_WRITE(MRST_DPLL_A, 0x00); 856026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov REG_WRITE(MRST_FPA0, 0xC1); 857026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov REG_WRITE(MRST_DPLL_A, 0x00800000); 858026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov udelay(500); 859026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov REG_WRITE(MRST_DPLL_A, 0x80800000); 860026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov 861026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov if (REG_BIT_WAIT(pipeconf_reg, 1, 29)) 862026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov dev_err(&dev->pdev->dev, "%s: DSI PLL lock timeout\n", 863026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov __func__); 864026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov 865026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov REG_WRITE(MIPI_DPHY_PARAM_REG(pipe), 0x2A0c6008); 866026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov 867026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov mipi_set_properties(dsi_config, pipe); 868026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov mdfld_mipi_config(dsi_config, pipe); 869026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov mdfld_set_pipe_timing(dsi_config, pipe); 870026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov 871026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov REG_WRITE(DSPABASE, 0x00); 872026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov REG_WRITE(DSPASIZE, 873026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov ((mode->vdisplay - 1) << 16) | (mode->hdisplay - 1)); 874026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov 875026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov REG_WRITE(DSPACNTR, 0x98000000); 876026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov REG_WRITE(DSPASURF, 0x00); 877026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov 878026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov REG_WRITE(VGACNTRL, 0x80000000); 879026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov REG_WRITE(DEVICE_READY_REG, 0x00000001); 880026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov 881026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov REG_WRITE(MIPI_PORT_CONTROL(pipe), 0x80810000); 882026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov } else { 883026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov /*set up mipi port FIXME: do at init time */ 884026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov REG_WRITE(MIPI_PORT_CONTROL(pipe), mipi); 885026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov } 886026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov REG_READ(MIPI_PORT_CONTROL(pipe)); 887026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov 888026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov if (mdfld_get_panel_type(dev, pipe) == TMD_VID) { 889026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov /* NOP */ 890026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov } else if (mdfld_get_panel_type(dev, pipe) == TC35876X) { 891026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov /* set up DSI controller DPI interface */ 892026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov mdfld_dsi_dpi_controller_init(dsi_config, pipe); 893026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov 894026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov /* Configure MIPI Bridge and Panel */ 895026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov tc35876x_configure_lvds_bridge(dev); 896026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov dev_priv->dpi_panel_on[pipe] = true; 897026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov } else { 898026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov /*turn on DPI interface*/ 899026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov mdfld_dsi_dpi_turn_on(dpi_output, pipe); 900026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov } 901026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov 902026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov /*set up pipe*/ 903026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov REG_WRITE(pipeconf_reg, pipeconf); 904026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov REG_READ(pipeconf_reg); 905026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov 906026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov /*set up display plane*/ 907026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov REG_WRITE(dspcntr_reg, dspcntr); 908026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov REG_READ(dspcntr_reg); 909026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov 910026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov msleep(20); /* FIXME: this should wait for vblank */ 911026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov 912026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov if (mdfld_get_panel_type(dev, pipe) == TMD_VID) { 913026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov /* NOP */ 914026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov } else if (mdfld_get_panel_type(dev, pipe) == TC35876X) { 915026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov mdfld_dsi_dpi_turn_on(dpi_output, pipe); 916026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov } else { 917026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov /* init driver ic */ 918026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov mdfld_dsi_tpo_ic_init(dsi_config, pipe); 919026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov /*init backlight*/ 920026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov mdfld_dsi_brightness_init(dsi_config, pipe); 921026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov } 922026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov 923026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov gma_power_end(dev); 924026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov} 925026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov 926026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov/* 927026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov * Init DSI DPI encoder. 928026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov * Allocate an mdfld_dsi_encoder and attach it to given @dsi_connector 929026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov * return pointer of newly allocated DPI encoder, NULL on error 930026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov */ 931026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemovstruct mdfld_dsi_encoder *mdfld_dsi_dpi_init(struct drm_device *dev, 932026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov struct mdfld_dsi_connector *dsi_connector, 933026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov const struct panel_funcs *p_funcs) 934026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov{ 935026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov struct mdfld_dsi_dpi_output *dpi_output = NULL; 936026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov struct mdfld_dsi_config *dsi_config; 937026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov struct drm_connector *connector = NULL; 938026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov struct drm_encoder *encoder = NULL; 939026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov int pipe; 940026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov u32 data; 941026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov int ret; 942026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov 943026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov pipe = dsi_connector->pipe; 944026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov 945026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov if (mdfld_get_panel_type(dev, pipe) != TC35876X) { 946026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov dsi_config = mdfld_dsi_get_config(dsi_connector); 947026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov 948026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov /* panel hard-reset */ 949026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov if (p_funcs->reset) { 950026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov ret = p_funcs->reset(pipe); 951026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov if (ret) { 952026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov DRM_ERROR("Panel %d hard-reset failed\n", pipe); 953026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov return NULL; 954026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov } 955026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov } 956026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov 957026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov /* panel drvIC init */ 958026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov if (p_funcs->drv_ic_init) 959026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov p_funcs->drv_ic_init(dsi_config, pipe); 960026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov 961026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov /* panel power mode detect */ 962026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov ret = mdfld_dsi_get_power_mode(dsi_config, &data, false); 963026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov if (ret) { 964026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov DRM_ERROR("Panel %d get power mode failed\n", pipe); 965026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov dsi_connector->status = connector_status_disconnected; 966026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov } else { 967026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov DRM_INFO("pipe %d power mode 0x%x\n", pipe, data); 968026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov dsi_connector->status = connector_status_connected; 969026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov } 970026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov } 971026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov 972026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov dpi_output = kzalloc(sizeof(struct mdfld_dsi_dpi_output), GFP_KERNEL); 973026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov if (!dpi_output) { 974026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov DRM_ERROR("No memory\n"); 975026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov return NULL; 976026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov } 977026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov 978026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov if (dsi_connector->pipe) 979026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov dpi_output->panel_on = 0; 980026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov else 981026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov dpi_output->panel_on = 0; 982026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov 983026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov dpi_output->dev = dev; 984026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov if (mdfld_get_panel_type(dev, pipe) != TC35876X) 985026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov dpi_output->p_funcs = p_funcs; 986026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov dpi_output->first_boot = 1; 987026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov 988026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov /*get fixed mode*/ 989026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov dsi_config = mdfld_dsi_get_config(dsi_connector); 990026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov 991026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov /*create drm encoder object*/ 992026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov connector = &dsi_connector->base.base; 993026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov encoder = &dpi_output->base.base.base; 994026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov drm_encoder_init(dev, 995026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov encoder, 996026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov p_funcs->encoder_funcs, 997026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov DRM_MODE_ENCODER_LVDS); 998026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov drm_encoder_helper_add(encoder, 999026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov p_funcs->encoder_helper_funcs); 1000026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov 1001026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov /*attach to given connector*/ 1002026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov drm_mode_connector_attach_encoder(connector, encoder); 1003026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov 1004026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov /*set possible crtcs and clones*/ 1005026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov if (dsi_connector->pipe) { 1006026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov encoder->possible_crtcs = (1 << 2); 1007026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov encoder->possible_clones = (1 << 1); 1008026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov } else { 1009026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov encoder->possible_crtcs = (1 << 0); 1010026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov encoder->possible_clones = (1 << 0); 1011026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov } 1012026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov 1013026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov dsi_connector->base.encoder = &dpi_output->base.base; 1014026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov 1015026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov return &dpi_output->base; 1016026abc333205c1fff80138b8c2cac3d0347685f4Kirill A. Shutemov} 1017