189c78134cc54dff016c83367912eb055637fa50cAlan Cox/* 289c78134cc54dff016c83367912eb055637fa50cAlan Cox * Copyright (c) 2009, Intel Corporation. 389c78134cc54dff016c83367912eb055637fa50cAlan Cox * 489c78134cc54dff016c83367912eb055637fa50cAlan Cox * This program is free software; you can redistribute it and/or modify it 589c78134cc54dff016c83367912eb055637fa50cAlan Cox * under the terms and conditions of the GNU General Public License, 689c78134cc54dff016c83367912eb055637fa50cAlan Cox * version 2, as published by the Free Software Foundation. 789c78134cc54dff016c83367912eb055637fa50cAlan Cox * 889c78134cc54dff016c83367912eb055637fa50cAlan Cox * This program is distributed in the hope it will be useful, but WITHOUT 989c78134cc54dff016c83367912eb055637fa50cAlan Cox * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 1089c78134cc54dff016c83367912eb055637fa50cAlan Cox * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 1189c78134cc54dff016c83367912eb055637fa50cAlan Cox * more details. 1289c78134cc54dff016c83367912eb055637fa50cAlan Cox * 1389c78134cc54dff016c83367912eb055637fa50cAlan Cox * You should have received a copy of the GNU General Public License along with 1489c78134cc54dff016c83367912eb055637fa50cAlan Cox * this program; if not, write to the Free Software Foundation, Inc., 1589c78134cc54dff016c83367912eb055637fa50cAlan Cox * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. 1689c78134cc54dff016c83367912eb055637fa50cAlan Cox */ 1789c78134cc54dff016c83367912eb055637fa50cAlan Cox#ifndef __PSB_INTEL_REG_H__ 1889c78134cc54dff016c83367912eb055637fa50cAlan Cox#define __PSB_INTEL_REG_H__ 1989c78134cc54dff016c83367912eb055637fa50cAlan Cox 205c0c1d50d7ba7a678b7d6e2c4f2ff31edafb1067Patrik Jakobsson/* 215c0c1d50d7ba7a678b7d6e2c4f2ff31edafb1067Patrik Jakobsson * GPIO regs 225c0c1d50d7ba7a678b7d6e2c4f2ff31edafb1067Patrik Jakobsson */ 235c0c1d50d7ba7a678b7d6e2c4f2ff31edafb1067Patrik Jakobsson#define GPIOA 0x5010 245c0c1d50d7ba7a678b7d6e2c4f2ff31edafb1067Patrik Jakobsson#define GPIOB 0x5014 255c0c1d50d7ba7a678b7d6e2c4f2ff31edafb1067Patrik Jakobsson#define GPIOC 0x5018 265c0c1d50d7ba7a678b7d6e2c4f2ff31edafb1067Patrik Jakobsson#define GPIOD 0x501c 275c0c1d50d7ba7a678b7d6e2c4f2ff31edafb1067Patrik Jakobsson#define GPIOE 0x5020 285c0c1d50d7ba7a678b7d6e2c4f2ff31edafb1067Patrik Jakobsson#define GPIOF 0x5024 295c0c1d50d7ba7a678b7d6e2c4f2ff31edafb1067Patrik Jakobsson#define GPIOG 0x5028 305c0c1d50d7ba7a678b7d6e2c4f2ff31edafb1067Patrik Jakobsson#define GPIOH 0x502c 315c0c1d50d7ba7a678b7d6e2c4f2ff31edafb1067Patrik Jakobsson# define GPIO_CLOCK_DIR_MASK (1 << 0) 325c0c1d50d7ba7a678b7d6e2c4f2ff31edafb1067Patrik Jakobsson# define GPIO_CLOCK_DIR_IN (0 << 1) 335c0c1d50d7ba7a678b7d6e2c4f2ff31edafb1067Patrik Jakobsson# define GPIO_CLOCK_DIR_OUT (1 << 1) 345c0c1d50d7ba7a678b7d6e2c4f2ff31edafb1067Patrik Jakobsson# define GPIO_CLOCK_VAL_MASK (1 << 2) 355c0c1d50d7ba7a678b7d6e2c4f2ff31edafb1067Patrik Jakobsson# define GPIO_CLOCK_VAL_OUT (1 << 3) 365c0c1d50d7ba7a678b7d6e2c4f2ff31edafb1067Patrik Jakobsson# define GPIO_CLOCK_VAL_IN (1 << 4) 375c0c1d50d7ba7a678b7d6e2c4f2ff31edafb1067Patrik Jakobsson# define GPIO_CLOCK_PULLUP_DISABLE (1 << 5) 385c0c1d50d7ba7a678b7d6e2c4f2ff31edafb1067Patrik Jakobsson# define GPIO_DATA_DIR_MASK (1 << 8) 395c0c1d50d7ba7a678b7d6e2c4f2ff31edafb1067Patrik Jakobsson# define GPIO_DATA_DIR_IN (0 << 9) 405c0c1d50d7ba7a678b7d6e2c4f2ff31edafb1067Patrik Jakobsson# define GPIO_DATA_DIR_OUT (1 << 9) 415c0c1d50d7ba7a678b7d6e2c4f2ff31edafb1067Patrik Jakobsson# define GPIO_DATA_VAL_MASK (1 << 10) 425c0c1d50d7ba7a678b7d6e2c4f2ff31edafb1067Patrik Jakobsson# define GPIO_DATA_VAL_OUT (1 << 11) 435c0c1d50d7ba7a678b7d6e2c4f2ff31edafb1067Patrik Jakobsson# define GPIO_DATA_VAL_IN (1 << 12) 445c0c1d50d7ba7a678b7d6e2c4f2ff31edafb1067Patrik Jakobsson# define GPIO_DATA_PULLUP_DISABLE (1 << 13) 455c0c1d50d7ba7a678b7d6e2c4f2ff31edafb1067Patrik Jakobsson 465c0c1d50d7ba7a678b7d6e2c4f2ff31edafb1067Patrik Jakobsson#define GMBUS0 0x5100 /* clock/port select */ 475c0c1d50d7ba7a678b7d6e2c4f2ff31edafb1067Patrik Jakobsson#define GMBUS_RATE_100KHZ (0<<8) 485c0c1d50d7ba7a678b7d6e2c4f2ff31edafb1067Patrik Jakobsson#define GMBUS_RATE_50KHZ (1<<8) 495c0c1d50d7ba7a678b7d6e2c4f2ff31edafb1067Patrik Jakobsson#define GMBUS_RATE_400KHZ (2<<8) /* reserved on Pineview */ 505c0c1d50d7ba7a678b7d6e2c4f2ff31edafb1067Patrik Jakobsson#define GMBUS_RATE_1MHZ (3<<8) /* reserved on Pineview */ 515c0c1d50d7ba7a678b7d6e2c4f2ff31edafb1067Patrik Jakobsson#define GMBUS_HOLD_EXT (1<<7) /* 300ns hold time, rsvd on Pineview */ 525c0c1d50d7ba7a678b7d6e2c4f2ff31edafb1067Patrik Jakobsson#define GMBUS_PORT_DISABLED 0 535c0c1d50d7ba7a678b7d6e2c4f2ff31edafb1067Patrik Jakobsson#define GMBUS_PORT_SSC 1 545c0c1d50d7ba7a678b7d6e2c4f2ff31edafb1067Patrik Jakobsson#define GMBUS_PORT_VGADDC 2 555c0c1d50d7ba7a678b7d6e2c4f2ff31edafb1067Patrik Jakobsson#define GMBUS_PORT_PANEL 3 565c0c1d50d7ba7a678b7d6e2c4f2ff31edafb1067Patrik Jakobsson#define GMBUS_PORT_DPC 4 /* HDMIC */ 575c0c1d50d7ba7a678b7d6e2c4f2ff31edafb1067Patrik Jakobsson#define GMBUS_PORT_DPB 5 /* SDVO, HDMIB */ 585c0c1d50d7ba7a678b7d6e2c4f2ff31edafb1067Patrik Jakobsson /* 6 reserved */ 595c0c1d50d7ba7a678b7d6e2c4f2ff31edafb1067Patrik Jakobsson#define GMBUS_PORT_DPD 7 /* HDMID */ 605c0c1d50d7ba7a678b7d6e2c4f2ff31edafb1067Patrik Jakobsson#define GMBUS_NUM_PORTS 8 615c0c1d50d7ba7a678b7d6e2c4f2ff31edafb1067Patrik Jakobsson#define GMBUS1 0x5104 /* command/status */ 625c0c1d50d7ba7a678b7d6e2c4f2ff31edafb1067Patrik Jakobsson#define GMBUS_SW_CLR_INT (1<<31) 635c0c1d50d7ba7a678b7d6e2c4f2ff31edafb1067Patrik Jakobsson#define GMBUS_SW_RDY (1<<30) 645c0c1d50d7ba7a678b7d6e2c4f2ff31edafb1067Patrik Jakobsson#define GMBUS_ENT (1<<29) /* enable timeout */ 655c0c1d50d7ba7a678b7d6e2c4f2ff31edafb1067Patrik Jakobsson#define GMBUS_CYCLE_NONE (0<<25) 665c0c1d50d7ba7a678b7d6e2c4f2ff31edafb1067Patrik Jakobsson#define GMBUS_CYCLE_WAIT (1<<25) 675c0c1d50d7ba7a678b7d6e2c4f2ff31edafb1067Patrik Jakobsson#define GMBUS_CYCLE_INDEX (2<<25) 685c0c1d50d7ba7a678b7d6e2c4f2ff31edafb1067Patrik Jakobsson#define GMBUS_CYCLE_STOP (4<<25) 695c0c1d50d7ba7a678b7d6e2c4f2ff31edafb1067Patrik Jakobsson#define GMBUS_BYTE_COUNT_SHIFT 16 705c0c1d50d7ba7a678b7d6e2c4f2ff31edafb1067Patrik Jakobsson#define GMBUS_SLAVE_INDEX_SHIFT 8 715c0c1d50d7ba7a678b7d6e2c4f2ff31edafb1067Patrik Jakobsson#define GMBUS_SLAVE_ADDR_SHIFT 1 725c0c1d50d7ba7a678b7d6e2c4f2ff31edafb1067Patrik Jakobsson#define GMBUS_SLAVE_READ (1<<0) 735c0c1d50d7ba7a678b7d6e2c4f2ff31edafb1067Patrik Jakobsson#define GMBUS_SLAVE_WRITE (0<<0) 745c0c1d50d7ba7a678b7d6e2c4f2ff31edafb1067Patrik Jakobsson#define GMBUS2 0x5108 /* status */ 755c0c1d50d7ba7a678b7d6e2c4f2ff31edafb1067Patrik Jakobsson#define GMBUS_INUSE (1<<15) 765c0c1d50d7ba7a678b7d6e2c4f2ff31edafb1067Patrik Jakobsson#define GMBUS_HW_WAIT_PHASE (1<<14) 775c0c1d50d7ba7a678b7d6e2c4f2ff31edafb1067Patrik Jakobsson#define GMBUS_STALL_TIMEOUT (1<<13) 785c0c1d50d7ba7a678b7d6e2c4f2ff31edafb1067Patrik Jakobsson#define GMBUS_INT (1<<12) 795c0c1d50d7ba7a678b7d6e2c4f2ff31edafb1067Patrik Jakobsson#define GMBUS_HW_RDY (1<<11) 805c0c1d50d7ba7a678b7d6e2c4f2ff31edafb1067Patrik Jakobsson#define GMBUS_SATOER (1<<10) 815c0c1d50d7ba7a678b7d6e2c4f2ff31edafb1067Patrik Jakobsson#define GMBUS_ACTIVE (1<<9) 825c0c1d50d7ba7a678b7d6e2c4f2ff31edafb1067Patrik Jakobsson#define GMBUS3 0x510c /* data buffer bytes 3-0 */ 835c0c1d50d7ba7a678b7d6e2c4f2ff31edafb1067Patrik Jakobsson#define GMBUS4 0x5110 /* interrupt mask (Pineview+) */ 845c0c1d50d7ba7a678b7d6e2c4f2ff31edafb1067Patrik Jakobsson#define GMBUS_SLAVE_TIMEOUT_EN (1<<4) 855c0c1d50d7ba7a678b7d6e2c4f2ff31edafb1067Patrik Jakobsson#define GMBUS_NAK_EN (1<<3) 865c0c1d50d7ba7a678b7d6e2c4f2ff31edafb1067Patrik Jakobsson#define GMBUS_IDLE_EN (1<<2) 875c0c1d50d7ba7a678b7d6e2c4f2ff31edafb1067Patrik Jakobsson#define GMBUS_HW_WAIT_EN (1<<1) 885c0c1d50d7ba7a678b7d6e2c4f2ff31edafb1067Patrik Jakobsson#define GMBUS_HW_RDY_EN (1<<0) 895c0c1d50d7ba7a678b7d6e2c4f2ff31edafb1067Patrik Jakobsson#define GMBUS5 0x5120 /* byte index */ 905c0c1d50d7ba7a678b7d6e2c4f2ff31edafb1067Patrik Jakobsson#define GMBUS_2BYTE_INDEX_EN (1<<31) 915c0c1d50d7ba7a678b7d6e2c4f2ff31edafb1067Patrik Jakobsson 9289c78134cc54dff016c83367912eb055637fa50cAlan Cox#define BLC_PWM_CTL 0x61254 9389c78134cc54dff016c83367912eb055637fa50cAlan Cox#define BLC_PWM_CTL2 0x61250 94d235e64a4367ad3ff204309490c4325b4f89b25bAlan Cox#define PWM_ENABLE (1 << 31) 95d235e64a4367ad3ff204309490c4325b4f89b25bAlan Cox#define PWM_LEGACY_MODE (1 << 30) 96d235e64a4367ad3ff204309490c4325b4f89b25bAlan Cox#define PWM_PIPE_B (1 << 29) 9789c78134cc54dff016c83367912eb055637fa50cAlan Cox#define BLC_PWM_CTL_C 0x62254 9889c78134cc54dff016c83367912eb055637fa50cAlan Cox#define BLC_PWM_CTL2_C 0x62250 9989c78134cc54dff016c83367912eb055637fa50cAlan Cox#define BACKLIGHT_MODULATION_FREQ_SHIFT (17) 10089c78134cc54dff016c83367912eb055637fa50cAlan Cox/* 10189c78134cc54dff016c83367912eb055637fa50cAlan Cox * This is the most significant 15 bits of the number of backlight cycles in a 10289c78134cc54dff016c83367912eb055637fa50cAlan Cox * complete cycle of the modulated backlight control. 10389c78134cc54dff016c83367912eb055637fa50cAlan Cox * 10489c78134cc54dff016c83367912eb055637fa50cAlan Cox * The actual value is this field multiplied by two. 10589c78134cc54dff016c83367912eb055637fa50cAlan Cox */ 10689c78134cc54dff016c83367912eb055637fa50cAlan Cox#define BACKLIGHT_MODULATION_FREQ_MASK (0x7fff << 17) 10789c78134cc54dff016c83367912eb055637fa50cAlan Cox#define BLM_LEGACY_MODE (1 << 16) 10889c78134cc54dff016c83367912eb055637fa50cAlan Cox/* 10989c78134cc54dff016c83367912eb055637fa50cAlan Cox * This is the number of cycles out of the backlight modulation cycle for which 11089c78134cc54dff016c83367912eb055637fa50cAlan Cox * the backlight is on. 11189c78134cc54dff016c83367912eb055637fa50cAlan Cox * 11289c78134cc54dff016c83367912eb055637fa50cAlan Cox * This field must be no greater than the number of cycles in the complete 11389c78134cc54dff016c83367912eb055637fa50cAlan Cox * backlight modulation cycle. 11489c78134cc54dff016c83367912eb055637fa50cAlan Cox */ 11589c78134cc54dff016c83367912eb055637fa50cAlan Cox#define BACKLIGHT_DUTY_CYCLE_SHIFT (0) 11689c78134cc54dff016c83367912eb055637fa50cAlan Cox#define BACKLIGHT_DUTY_CYCLE_MASK (0xffff) 11789c78134cc54dff016c83367912eb055637fa50cAlan Cox 11889c78134cc54dff016c83367912eb055637fa50cAlan Cox#define I915_GCFGC 0xf0 11989c78134cc54dff016c83367912eb055637fa50cAlan Cox#define I915_LOW_FREQUENCY_ENABLE (1 << 7) 12089c78134cc54dff016c83367912eb055637fa50cAlan Cox#define I915_DISPLAY_CLOCK_190_200_MHZ (0 << 4) 12189c78134cc54dff016c83367912eb055637fa50cAlan Cox#define I915_DISPLAY_CLOCK_333_MHZ (4 << 4) 12289c78134cc54dff016c83367912eb055637fa50cAlan Cox#define I915_DISPLAY_CLOCK_MASK (7 << 4) 12389c78134cc54dff016c83367912eb055637fa50cAlan Cox 12489c78134cc54dff016c83367912eb055637fa50cAlan Cox#define I855_HPLLCC 0xc0 12589c78134cc54dff016c83367912eb055637fa50cAlan Cox#define I855_CLOCK_CONTROL_MASK (3 << 0) 12689c78134cc54dff016c83367912eb055637fa50cAlan Cox#define I855_CLOCK_133_200 (0 << 0) 12789c78134cc54dff016c83367912eb055637fa50cAlan Cox#define I855_CLOCK_100_200 (1 << 0) 12889c78134cc54dff016c83367912eb055637fa50cAlan Cox#define I855_CLOCK_100_133 (2 << 0) 12989c78134cc54dff016c83367912eb055637fa50cAlan Cox#define I855_CLOCK_166_250 (3 << 0) 13089c78134cc54dff016c83367912eb055637fa50cAlan Cox 13189c78134cc54dff016c83367912eb055637fa50cAlan Cox/* I830 CRTC registers */ 13289c78134cc54dff016c83367912eb055637fa50cAlan Cox#define HTOTAL_A 0x60000 13389c78134cc54dff016c83367912eb055637fa50cAlan Cox#define HBLANK_A 0x60004 13489c78134cc54dff016c83367912eb055637fa50cAlan Cox#define HSYNC_A 0x60008 13589c78134cc54dff016c83367912eb055637fa50cAlan Cox#define VTOTAL_A 0x6000c 13689c78134cc54dff016c83367912eb055637fa50cAlan Cox#define VBLANK_A 0x60010 13789c78134cc54dff016c83367912eb055637fa50cAlan Cox#define VSYNC_A 0x60014 13889c78134cc54dff016c83367912eb055637fa50cAlan Cox#define PIPEASRC 0x6001c 13989c78134cc54dff016c83367912eb055637fa50cAlan Cox#define BCLRPAT_A 0x60020 14089c78134cc54dff016c83367912eb055637fa50cAlan Cox#define VSYNCSHIFT_A 0x60028 14189c78134cc54dff016c83367912eb055637fa50cAlan Cox 14289c78134cc54dff016c83367912eb055637fa50cAlan Cox#define HTOTAL_B 0x61000 14389c78134cc54dff016c83367912eb055637fa50cAlan Cox#define HBLANK_B 0x61004 14489c78134cc54dff016c83367912eb055637fa50cAlan Cox#define HSYNC_B 0x61008 14589c78134cc54dff016c83367912eb055637fa50cAlan Cox#define VTOTAL_B 0x6100c 14689c78134cc54dff016c83367912eb055637fa50cAlan Cox#define VBLANK_B 0x61010 14789c78134cc54dff016c83367912eb055637fa50cAlan Cox#define VSYNC_B 0x61014 14889c78134cc54dff016c83367912eb055637fa50cAlan Cox#define PIPEBSRC 0x6101c 14989c78134cc54dff016c83367912eb055637fa50cAlan Cox#define BCLRPAT_B 0x61020 15089c78134cc54dff016c83367912eb055637fa50cAlan Cox#define VSYNCSHIFT_B 0x61028 15189c78134cc54dff016c83367912eb055637fa50cAlan Cox 15289c78134cc54dff016c83367912eb055637fa50cAlan Cox#define HTOTAL_C 0x62000 15389c78134cc54dff016c83367912eb055637fa50cAlan Cox#define HBLANK_C 0x62004 15489c78134cc54dff016c83367912eb055637fa50cAlan Cox#define HSYNC_C 0x62008 15589c78134cc54dff016c83367912eb055637fa50cAlan Cox#define VTOTAL_C 0x6200c 15689c78134cc54dff016c83367912eb055637fa50cAlan Cox#define VBLANK_C 0x62010 15789c78134cc54dff016c83367912eb055637fa50cAlan Cox#define VSYNC_C 0x62014 15889c78134cc54dff016c83367912eb055637fa50cAlan Cox#define PIPECSRC 0x6201c 15989c78134cc54dff016c83367912eb055637fa50cAlan Cox#define BCLRPAT_C 0x62020 16089c78134cc54dff016c83367912eb055637fa50cAlan Cox#define VSYNCSHIFT_C 0x62028 16189c78134cc54dff016c83367912eb055637fa50cAlan Cox 16289c78134cc54dff016c83367912eb055637fa50cAlan Cox#define PP_STATUS 0x61200 16389c78134cc54dff016c83367912eb055637fa50cAlan Cox# define PP_ON (1 << 31) 16489c78134cc54dff016c83367912eb055637fa50cAlan Cox/* 16589c78134cc54dff016c83367912eb055637fa50cAlan Cox * Indicates that all dependencies of the panel are on: 16689c78134cc54dff016c83367912eb055637fa50cAlan Cox * 16789c78134cc54dff016c83367912eb055637fa50cAlan Cox * - PLL enabled 16889c78134cc54dff016c83367912eb055637fa50cAlan Cox * - pipe enabled 16989c78134cc54dff016c83367912eb055637fa50cAlan Cox * - LVDS/DVOB/DVOC on 17089c78134cc54dff016c83367912eb055637fa50cAlan Cox */ 17189c78134cc54dff016c83367912eb055637fa50cAlan Cox#define PP_READY (1 << 30) 17289c78134cc54dff016c83367912eb055637fa50cAlan Cox#define PP_SEQUENCE_NONE (0 << 28) 17389c78134cc54dff016c83367912eb055637fa50cAlan Cox#define PP_SEQUENCE_ON (1 << 28) 17489c78134cc54dff016c83367912eb055637fa50cAlan Cox#define PP_SEQUENCE_OFF (2 << 28) 17589c78134cc54dff016c83367912eb055637fa50cAlan Cox#define PP_SEQUENCE_MASK 0x30000000 176d112a8163f83752361dd639a9a579ae5cc05c6cfZhao Yakui#define PP_CYCLE_DELAY_ACTIVE (1 << 27) 177d112a8163f83752361dd639a9a579ae5cc05c6cfZhao Yakui#define PP_SEQUENCE_STATE_ON_IDLE (1 << 3) 178d112a8163f83752361dd639a9a579ae5cc05c6cfZhao Yakui#define PP_SEQUENCE_STATE_MASK 0x0000000f 179d112a8163f83752361dd639a9a579ae5cc05c6cfZhao Yakui 18089c78134cc54dff016c83367912eb055637fa50cAlan Cox#define PP_CONTROL 0x61204 18189c78134cc54dff016c83367912eb055637fa50cAlan Cox#define POWER_TARGET_ON (1 << 0) 182d112a8163f83752361dd639a9a579ae5cc05c6cfZhao Yakui#define PANEL_UNLOCK_REGS (0xabcd << 16) 183d112a8163f83752361dd639a9a579ae5cc05c6cfZhao Yakui#define PANEL_UNLOCK_MASK (0xffff << 16) 184d112a8163f83752361dd639a9a579ae5cc05c6cfZhao Yakui#define EDP_FORCE_VDD (1 << 3) 185d112a8163f83752361dd639a9a579ae5cc05c6cfZhao Yakui#define EDP_BLC_ENABLE (1 << 2) 186d112a8163f83752361dd639a9a579ae5cc05c6cfZhao Yakui#define PANEL_POWER_RESET (1 << 1) 187d112a8163f83752361dd639a9a579ae5cc05c6cfZhao Yakui#define PANEL_POWER_OFF (0 << 0) 188d112a8163f83752361dd639a9a579ae5cc05c6cfZhao Yakui#define PANEL_POWER_ON (1 << 0) 189d112a8163f83752361dd639a9a579ae5cc05c6cfZhao Yakui 190d112a8163f83752361dd639a9a579ae5cc05c6cfZhao Yakui/* Poulsbo/Oaktrail */ 19189c78134cc54dff016c83367912eb055637fa50cAlan Cox#define LVDSPP_ON 0x61208 19289c78134cc54dff016c83367912eb055637fa50cAlan Cox#define LVDSPP_OFF 0x6120c 19389c78134cc54dff016c83367912eb055637fa50cAlan Cox#define PP_CYCLE 0x61210 19489c78134cc54dff016c83367912eb055637fa50cAlan Cox 195d112a8163f83752361dd639a9a579ae5cc05c6cfZhao Yakui/* Cedartrail */ 19609016a11fc738e82ca1303e2332473b517bbd660Alan Cox#define PP_ON_DELAYS 0x61208 /* Cedartrail */ 197d112a8163f83752361dd639a9a579ae5cc05c6cfZhao Yakui#define PANEL_PORT_SELECT_MASK (3 << 30) 198d112a8163f83752361dd639a9a579ae5cc05c6cfZhao Yakui#define PANEL_PORT_SELECT_LVDS (0 << 30) 199d112a8163f83752361dd639a9a579ae5cc05c6cfZhao Yakui#define PANEL_PORT_SELECT_EDP (1 << 30) 200d112a8163f83752361dd639a9a579ae5cc05c6cfZhao Yakui#define PANEL_POWER_UP_DELAY_MASK (0x1fff0000) 201d112a8163f83752361dd639a9a579ae5cc05c6cfZhao Yakui#define PANEL_POWER_UP_DELAY_SHIFT 16 202d112a8163f83752361dd639a9a579ae5cc05c6cfZhao Yakui#define PANEL_LIGHT_ON_DELAY_MASK (0x1fff) 203d112a8163f83752361dd639a9a579ae5cc05c6cfZhao Yakui#define PANEL_LIGHT_ON_DELAY_SHIFT 0 204d112a8163f83752361dd639a9a579ae5cc05c6cfZhao Yakui 20509016a11fc738e82ca1303e2332473b517bbd660Alan Cox#define PP_OFF_DELAYS 0x6120c /* Cedartrail */ 206d112a8163f83752361dd639a9a579ae5cc05c6cfZhao Yakui#define PANEL_POWER_DOWN_DELAY_MASK (0x1fff0000) 207d112a8163f83752361dd639a9a579ae5cc05c6cfZhao Yakui#define PANEL_POWER_DOWN_DELAY_SHIFT 16 208d112a8163f83752361dd639a9a579ae5cc05c6cfZhao Yakui#define PANEL_LIGHT_OFF_DELAY_MASK (0x1fff) 209d112a8163f83752361dd639a9a579ae5cc05c6cfZhao Yakui#define PANEL_LIGHT_OFF_DELAY_SHIFT 0 210d112a8163f83752361dd639a9a579ae5cc05c6cfZhao Yakui 211d112a8163f83752361dd639a9a579ae5cc05c6cfZhao Yakui#define PP_DIVISOR 0x61210 /* Cedartrail */ 212d112a8163f83752361dd639a9a579ae5cc05c6cfZhao Yakui#define PP_REFERENCE_DIVIDER_MASK (0xffffff00) 213d112a8163f83752361dd639a9a579ae5cc05c6cfZhao Yakui#define PP_REFERENCE_DIVIDER_SHIFT 8 214d112a8163f83752361dd639a9a579ae5cc05c6cfZhao Yakui#define PANEL_POWER_CYCLE_DELAY_MASK (0x1f) 215d112a8163f83752361dd639a9a579ae5cc05c6cfZhao Yakui#define PANEL_POWER_CYCLE_DELAY_SHIFT 0 21609016a11fc738e82ca1303e2332473b517bbd660Alan Cox 21789c78134cc54dff016c83367912eb055637fa50cAlan Cox#define PFIT_CONTROL 0x61230 21889c78134cc54dff016c83367912eb055637fa50cAlan Cox#define PFIT_ENABLE (1 << 31) 21989c78134cc54dff016c83367912eb055637fa50cAlan Cox#define PFIT_PIPE_MASK (3 << 29) 22089c78134cc54dff016c83367912eb055637fa50cAlan Cox#define PFIT_PIPE_SHIFT 29 22189c78134cc54dff016c83367912eb055637fa50cAlan Cox#define PFIT_SCALING_MODE_PILLARBOX (1 << 27) 22289c78134cc54dff016c83367912eb055637fa50cAlan Cox#define PFIT_SCALING_MODE_LETTERBOX (3 << 26) 22389c78134cc54dff016c83367912eb055637fa50cAlan Cox#define VERT_INTERP_DISABLE (0 << 10) 22489c78134cc54dff016c83367912eb055637fa50cAlan Cox#define VERT_INTERP_BILINEAR (1 << 10) 22589c78134cc54dff016c83367912eb055637fa50cAlan Cox#define VERT_INTERP_MASK (3 << 10) 22689c78134cc54dff016c83367912eb055637fa50cAlan Cox#define VERT_AUTO_SCALE (1 << 9) 22789c78134cc54dff016c83367912eb055637fa50cAlan Cox#define HORIZ_INTERP_DISABLE (0 << 6) 22889c78134cc54dff016c83367912eb055637fa50cAlan Cox#define HORIZ_INTERP_BILINEAR (1 << 6) 22989c78134cc54dff016c83367912eb055637fa50cAlan Cox#define HORIZ_INTERP_MASK (3 << 6) 23089c78134cc54dff016c83367912eb055637fa50cAlan Cox#define HORIZ_AUTO_SCALE (1 << 5) 23189c78134cc54dff016c83367912eb055637fa50cAlan Cox#define PANEL_8TO6_DITHER_ENABLE (1 << 3) 23289c78134cc54dff016c83367912eb055637fa50cAlan Cox 23389c78134cc54dff016c83367912eb055637fa50cAlan Cox#define PFIT_PGM_RATIOS 0x61234 23489c78134cc54dff016c83367912eb055637fa50cAlan Cox#define PFIT_VERT_SCALE_MASK 0xfff00000 23589c78134cc54dff016c83367912eb055637fa50cAlan Cox#define PFIT_HORIZ_SCALE_MASK 0x0000fff0 23689c78134cc54dff016c83367912eb055637fa50cAlan Cox 23789c78134cc54dff016c83367912eb055637fa50cAlan Cox#define PFIT_AUTO_RATIOS 0x61238 23889c78134cc54dff016c83367912eb055637fa50cAlan Cox 23989c78134cc54dff016c83367912eb055637fa50cAlan Cox#define DPLL_A 0x06014 24089c78134cc54dff016c83367912eb055637fa50cAlan Cox#define DPLL_B 0x06018 24189c78134cc54dff016c83367912eb055637fa50cAlan Cox#define DPLL_VCO_ENABLE (1 << 31) 24289c78134cc54dff016c83367912eb055637fa50cAlan Cox#define DPLL_DVO_HIGH_SPEED (1 << 30) 24389c78134cc54dff016c83367912eb055637fa50cAlan Cox#define DPLL_SYNCLOCK_ENABLE (1 << 29) 24489c78134cc54dff016c83367912eb055637fa50cAlan Cox#define DPLL_VGA_MODE_DIS (1 << 28) 24589c78134cc54dff016c83367912eb055637fa50cAlan Cox#define DPLLB_MODE_DAC_SERIAL (1 << 26) /* i915 */ 24689c78134cc54dff016c83367912eb055637fa50cAlan Cox#define DPLLB_MODE_LVDS (2 << 26) /* i915 */ 24789c78134cc54dff016c83367912eb055637fa50cAlan Cox#define DPLL_MODE_MASK (3 << 26) 24889c78134cc54dff016c83367912eb055637fa50cAlan Cox#define DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 (0 << 24) /* i915 */ 24989c78134cc54dff016c83367912eb055637fa50cAlan Cox#define DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 (1 << 24) /* i915 */ 25089c78134cc54dff016c83367912eb055637fa50cAlan Cox#define DPLLB_LVDS_P2_CLOCK_DIV_14 (0 << 24) /* i915 */ 25189c78134cc54dff016c83367912eb055637fa50cAlan Cox#define DPLLB_LVDS_P2_CLOCK_DIV_7 (1 << 24) /* i915 */ 25289c78134cc54dff016c83367912eb055637fa50cAlan Cox#define DPLL_P2_CLOCK_DIV_MASK 0x03000000 /* i915 */ 253ae0a246aef0d185db2947912fe9cf7dae1d91b7aAlan Cox#define DPLL_FPA0h1_P1_POST_DIV_MASK 0x00ff0000 /* i915 */ 25489c78134cc54dff016c83367912eb055637fa50cAlan Cox#define DPLL_LOCK (1 << 15) /* CDV */ 25589c78134cc54dff016c83367912eb055637fa50cAlan Cox 25689c78134cc54dff016c83367912eb055637fa50cAlan Cox/* 25789c78134cc54dff016c83367912eb055637fa50cAlan Cox * The i830 generation, in DAC/serial mode, defines p1 as two plus this 25889c78134cc54dff016c83367912eb055637fa50cAlan Cox * bitfield, or just 2 if PLL_P1_DIVIDE_BY_TWO is set. 25989c78134cc54dff016c83367912eb055637fa50cAlan Cox */ 26089c78134cc54dff016c83367912eb055637fa50cAlan Cox# define DPLL_FPA01_P1_POST_DIV_MASK_I830 0x001f0000 26189c78134cc54dff016c83367912eb055637fa50cAlan Cox/* 26289c78134cc54dff016c83367912eb055637fa50cAlan Cox * The i830 generation, in LVDS mode, defines P1 as the bit number set within 26389c78134cc54dff016c83367912eb055637fa50cAlan Cox * this field (only one bit may be set). 26489c78134cc54dff016c83367912eb055637fa50cAlan Cox */ 26589c78134cc54dff016c83367912eb055637fa50cAlan Cox#define DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS 0x003f0000 26689c78134cc54dff016c83367912eb055637fa50cAlan Cox#define DPLL_FPA01_P1_POST_DIV_SHIFT 16 26789c78134cc54dff016c83367912eb055637fa50cAlan Cox#define PLL_P2_DIVIDE_BY_4 (1 << 23) /* i830, required 26889c78134cc54dff016c83367912eb055637fa50cAlan Cox * in DVO non-gang */ 26989c78134cc54dff016c83367912eb055637fa50cAlan Cox# define PLL_P1_DIVIDE_BY_TWO (1 << 21) /* i830 */ 27089c78134cc54dff016c83367912eb055637fa50cAlan Cox#define PLL_REF_INPUT_DREFCLK (0 << 13) 27189c78134cc54dff016c83367912eb055637fa50cAlan Cox#define PLL_REF_INPUT_TVCLKINA (1 << 13) /* i830 */ 27289c78134cc54dff016c83367912eb055637fa50cAlan Cox#define PLL_REF_INPUT_TVCLKINBC (2 << 13) /* SDVO 27389c78134cc54dff016c83367912eb055637fa50cAlan Cox * TVCLKIN */ 27489c78134cc54dff016c83367912eb055637fa50cAlan Cox#define PLLB_REF_INPUT_SPREADSPECTRUMIN (3 << 13) 27589c78134cc54dff016c83367912eb055637fa50cAlan Cox#define PLL_REF_INPUT_MASK (3 << 13) 27689c78134cc54dff016c83367912eb055637fa50cAlan Cox#define PLL_LOAD_PULSE_PHASE_SHIFT 9 27789c78134cc54dff016c83367912eb055637fa50cAlan Cox/* 27889c78134cc54dff016c83367912eb055637fa50cAlan Cox * Parallel to Serial Load Pulse phase selection. 27989c78134cc54dff016c83367912eb055637fa50cAlan Cox * Selects the phase for the 10X DPLL clock for the PCIe 28089c78134cc54dff016c83367912eb055637fa50cAlan Cox * digital display port. The range is 4 to 13; 10 or more 28189c78134cc54dff016c83367912eb055637fa50cAlan Cox * is just a flip delay. The default is 6 28289c78134cc54dff016c83367912eb055637fa50cAlan Cox */ 28389c78134cc54dff016c83367912eb055637fa50cAlan Cox#define PLL_LOAD_PULSE_PHASE_MASK (0xf << PLL_LOAD_PULSE_PHASE_SHIFT) 28489c78134cc54dff016c83367912eb055637fa50cAlan Cox#define DISPLAY_RATE_SELECT_FPA1 (1 << 8) 28589c78134cc54dff016c83367912eb055637fa50cAlan Cox 28689c78134cc54dff016c83367912eb055637fa50cAlan Cox/* 28789c78134cc54dff016c83367912eb055637fa50cAlan Cox * SDVO multiplier for 945G/GM. Not used on 965. 28889c78134cc54dff016c83367912eb055637fa50cAlan Cox * 28989c78134cc54dff016c83367912eb055637fa50cAlan Cox * DPLL_MD_UDI_MULTIPLIER_MASK 29089c78134cc54dff016c83367912eb055637fa50cAlan Cox */ 29189c78134cc54dff016c83367912eb055637fa50cAlan Cox#define SDVO_MULTIPLIER_MASK 0x000000ff 29289c78134cc54dff016c83367912eb055637fa50cAlan Cox#define SDVO_MULTIPLIER_SHIFT_HIRES 4 29389c78134cc54dff016c83367912eb055637fa50cAlan Cox#define SDVO_MULTIPLIER_SHIFT_VGA 0 29489c78134cc54dff016c83367912eb055637fa50cAlan Cox 29589c78134cc54dff016c83367912eb055637fa50cAlan Cox/* 29689c78134cc54dff016c83367912eb055637fa50cAlan Cox * PLL_MD 29789c78134cc54dff016c83367912eb055637fa50cAlan Cox */ 29889c78134cc54dff016c83367912eb055637fa50cAlan Cox/* Pipe A SDVO/UDI clock multiplier/divider register for G965. */ 29989c78134cc54dff016c83367912eb055637fa50cAlan Cox#define DPLL_A_MD 0x0601c 30089c78134cc54dff016c83367912eb055637fa50cAlan Cox/* Pipe B SDVO/UDI clock multiplier/divider register for G965. */ 30189c78134cc54dff016c83367912eb055637fa50cAlan Cox#define DPLL_B_MD 0x06020 30289c78134cc54dff016c83367912eb055637fa50cAlan Cox/* 30389c78134cc54dff016c83367912eb055637fa50cAlan Cox * UDI pixel divider, controlling how many pixels are stuffed into a packet. 30489c78134cc54dff016c83367912eb055637fa50cAlan Cox * 30589c78134cc54dff016c83367912eb055637fa50cAlan Cox * Value is pixels minus 1. Must be set to 1 pixel for SDVO. 30689c78134cc54dff016c83367912eb055637fa50cAlan Cox */ 30789c78134cc54dff016c83367912eb055637fa50cAlan Cox#define DPLL_MD_UDI_DIVIDER_MASK 0x3f000000 30889c78134cc54dff016c83367912eb055637fa50cAlan Cox#define DPLL_MD_UDI_DIVIDER_SHIFT 24 30989c78134cc54dff016c83367912eb055637fa50cAlan Cox/* UDI pixel divider for VGA, same as DPLL_MD_UDI_DIVIDER_MASK. */ 31089c78134cc54dff016c83367912eb055637fa50cAlan Cox#define DPLL_MD_VGA_UDI_DIVIDER_MASK 0x003f0000 31189c78134cc54dff016c83367912eb055637fa50cAlan Cox#define DPLL_MD_VGA_UDI_DIVIDER_SHIFT 16 31289c78134cc54dff016c83367912eb055637fa50cAlan Cox/* 31389c78134cc54dff016c83367912eb055637fa50cAlan Cox * SDVO/UDI pixel multiplier. 31489c78134cc54dff016c83367912eb055637fa50cAlan Cox * 31589c78134cc54dff016c83367912eb055637fa50cAlan Cox * SDVO requires that the bus clock rate be between 1 and 2 Ghz, and the bus 31689c78134cc54dff016c83367912eb055637fa50cAlan Cox * clock rate is 10 times the DPLL clock. At low resolution/refresh rate 31789c78134cc54dff016c83367912eb055637fa50cAlan Cox * modes, the bus rate would be below the limits, so SDVO allows for stuffing 31889c78134cc54dff016c83367912eb055637fa50cAlan Cox * dummy bytes in the datastream at an increased clock rate, with both sides of 31989c78134cc54dff016c83367912eb055637fa50cAlan Cox * the link knowing how many bytes are fill. 32089c78134cc54dff016c83367912eb055637fa50cAlan Cox * 32189c78134cc54dff016c83367912eb055637fa50cAlan Cox * So, for a mode with a dotclock of 65Mhz, we would want to double the clock 32289c78134cc54dff016c83367912eb055637fa50cAlan Cox * rate to 130Mhz to get a bus rate of 1.30Ghz. The DPLL clock rate would be 32389c78134cc54dff016c83367912eb055637fa50cAlan Cox * set to 130Mhz, and the SDVO multiplier set to 2x in this register and 32489c78134cc54dff016c83367912eb055637fa50cAlan Cox * through an SDVO command. 32589c78134cc54dff016c83367912eb055637fa50cAlan Cox * 32689c78134cc54dff016c83367912eb055637fa50cAlan Cox * This register field has values of multiplication factor minus 1, with 32789c78134cc54dff016c83367912eb055637fa50cAlan Cox * a maximum multiplier of 5 for SDVO. 32889c78134cc54dff016c83367912eb055637fa50cAlan Cox */ 32989c78134cc54dff016c83367912eb055637fa50cAlan Cox#define DPLL_MD_UDI_MULTIPLIER_MASK 0x00003f00 33089c78134cc54dff016c83367912eb055637fa50cAlan Cox#define DPLL_MD_UDI_MULTIPLIER_SHIFT 8 33189c78134cc54dff016c83367912eb055637fa50cAlan Cox/* 33289c78134cc54dff016c83367912eb055637fa50cAlan Cox * SDVO/UDI pixel multiplier for VGA, same as DPLL_MD_UDI_MULTIPLIER_MASK. 33389c78134cc54dff016c83367912eb055637fa50cAlan Cox * This best be set to the default value (3) or the CRT won't work. No, 33489c78134cc54dff016c83367912eb055637fa50cAlan Cox * I don't entirely understand what this does... 33589c78134cc54dff016c83367912eb055637fa50cAlan Cox */ 33689c78134cc54dff016c83367912eb055637fa50cAlan Cox#define DPLL_MD_VGA_UDI_MULTIPLIER_MASK 0x0000003f 33789c78134cc54dff016c83367912eb055637fa50cAlan Cox#define DPLL_MD_VGA_UDI_MULTIPLIER_SHIFT 0 33889c78134cc54dff016c83367912eb055637fa50cAlan Cox 33989c78134cc54dff016c83367912eb055637fa50cAlan Cox#define DPLL_TEST 0x606c 34089c78134cc54dff016c83367912eb055637fa50cAlan Cox#define DPLLB_TEST_SDVO_DIV_1 (0 << 22) 34189c78134cc54dff016c83367912eb055637fa50cAlan Cox#define DPLLB_TEST_SDVO_DIV_2 (1 << 22) 34289c78134cc54dff016c83367912eb055637fa50cAlan Cox#define DPLLB_TEST_SDVO_DIV_4 (2 << 22) 34389c78134cc54dff016c83367912eb055637fa50cAlan Cox#define DPLLB_TEST_SDVO_DIV_MASK (3 << 22) 34489c78134cc54dff016c83367912eb055637fa50cAlan Cox#define DPLLB_TEST_N_BYPASS (1 << 19) 34589c78134cc54dff016c83367912eb055637fa50cAlan Cox#define DPLLB_TEST_M_BYPASS (1 << 18) 34689c78134cc54dff016c83367912eb055637fa50cAlan Cox#define DPLLB_INPUT_BUFFER_ENABLE (1 << 16) 34789c78134cc54dff016c83367912eb055637fa50cAlan Cox#define DPLLA_TEST_N_BYPASS (1 << 3) 34889c78134cc54dff016c83367912eb055637fa50cAlan Cox#define DPLLA_TEST_M_BYPASS (1 << 2) 34989c78134cc54dff016c83367912eb055637fa50cAlan Cox#define DPLLA_INPUT_BUFFER_ENABLE (1 << 0) 35089c78134cc54dff016c83367912eb055637fa50cAlan Cox 35189c78134cc54dff016c83367912eb055637fa50cAlan Cox#define ADPA 0x61100 35289c78134cc54dff016c83367912eb055637fa50cAlan Cox#define ADPA_DAC_ENABLE (1 << 31) 35389c78134cc54dff016c83367912eb055637fa50cAlan Cox#define ADPA_DAC_DISABLE 0 35489c78134cc54dff016c83367912eb055637fa50cAlan Cox#define ADPA_PIPE_SELECT_MASK (1 << 30) 35589c78134cc54dff016c83367912eb055637fa50cAlan Cox#define ADPA_PIPE_A_SELECT 0 35689c78134cc54dff016c83367912eb055637fa50cAlan Cox#define ADPA_PIPE_B_SELECT (1 << 30) 35789c78134cc54dff016c83367912eb055637fa50cAlan Cox#define ADPA_USE_VGA_HVPOLARITY (1 << 15) 35889c78134cc54dff016c83367912eb055637fa50cAlan Cox#define ADPA_SETS_HVPOLARITY 0 35989c78134cc54dff016c83367912eb055637fa50cAlan Cox#define ADPA_VSYNC_CNTL_DISABLE (1 << 11) 36089c78134cc54dff016c83367912eb055637fa50cAlan Cox#define ADPA_VSYNC_CNTL_ENABLE 0 36189c78134cc54dff016c83367912eb055637fa50cAlan Cox#define ADPA_HSYNC_CNTL_DISABLE (1 << 10) 36289c78134cc54dff016c83367912eb055637fa50cAlan Cox#define ADPA_HSYNC_CNTL_ENABLE 0 36389c78134cc54dff016c83367912eb055637fa50cAlan Cox#define ADPA_VSYNC_ACTIVE_HIGH (1 << 4) 36489c78134cc54dff016c83367912eb055637fa50cAlan Cox#define ADPA_VSYNC_ACTIVE_LOW 0 36589c78134cc54dff016c83367912eb055637fa50cAlan Cox#define ADPA_HSYNC_ACTIVE_HIGH (1 << 3) 36689c78134cc54dff016c83367912eb055637fa50cAlan Cox#define ADPA_HSYNC_ACTIVE_LOW 0 36789c78134cc54dff016c83367912eb055637fa50cAlan Cox 36889c78134cc54dff016c83367912eb055637fa50cAlan Cox#define FPA0 0x06040 36989c78134cc54dff016c83367912eb055637fa50cAlan Cox#define FPA1 0x06044 37089c78134cc54dff016c83367912eb055637fa50cAlan Cox#define FPB0 0x06048 37189c78134cc54dff016c83367912eb055637fa50cAlan Cox#define FPB1 0x0604c 37289c78134cc54dff016c83367912eb055637fa50cAlan Cox#define FP_N_DIV_MASK 0x003f0000 37389c78134cc54dff016c83367912eb055637fa50cAlan Cox#define FP_N_DIV_SHIFT 16 37489c78134cc54dff016c83367912eb055637fa50cAlan Cox#define FP_M1_DIV_MASK 0x00003f00 37589c78134cc54dff016c83367912eb055637fa50cAlan Cox#define FP_M1_DIV_SHIFT 8 37689c78134cc54dff016c83367912eb055637fa50cAlan Cox#define FP_M2_DIV_MASK 0x0000003f 37789c78134cc54dff016c83367912eb055637fa50cAlan Cox#define FP_M2_DIV_SHIFT 0 37889c78134cc54dff016c83367912eb055637fa50cAlan Cox 37989c78134cc54dff016c83367912eb055637fa50cAlan Cox#define PORT_HOTPLUG_EN 0x61110 380ae0a246aef0d185db2947912fe9cf7dae1d91b7aAlan Cox#define HDMIB_HOTPLUG_INT_EN (1 << 29) 381ae0a246aef0d185db2947912fe9cf7dae1d91b7aAlan Cox#define HDMIC_HOTPLUG_INT_EN (1 << 28) 382ae0a246aef0d185db2947912fe9cf7dae1d91b7aAlan Cox#define HDMID_HOTPLUG_INT_EN (1 << 27) 38389c78134cc54dff016c83367912eb055637fa50cAlan Cox#define SDVOB_HOTPLUG_INT_EN (1 << 26) 38489c78134cc54dff016c83367912eb055637fa50cAlan Cox#define SDVOC_HOTPLUG_INT_EN (1 << 25) 38589c78134cc54dff016c83367912eb055637fa50cAlan Cox#define TV_HOTPLUG_INT_EN (1 << 18) 38689c78134cc54dff016c83367912eb055637fa50cAlan Cox#define CRT_HOTPLUG_INT_EN (1 << 9) 38789c78134cc54dff016c83367912eb055637fa50cAlan Cox#define CRT_HOTPLUG_FORCE_DETECT (1 << 3) 38889c78134cc54dff016c83367912eb055637fa50cAlan Cox/* CDV.. */ 38989c78134cc54dff016c83367912eb055637fa50cAlan Cox#define CRT_HOTPLUG_ACTIVATION_PERIOD_64 (1 << 8) 39089c78134cc54dff016c83367912eb055637fa50cAlan Cox#define CRT_HOTPLUG_DAC_ON_TIME_2M (0 << 7) 39189c78134cc54dff016c83367912eb055637fa50cAlan Cox#define CRT_HOTPLUG_DAC_ON_TIME_4M (1 << 7) 39289c78134cc54dff016c83367912eb055637fa50cAlan Cox#define CRT_HOTPLUG_VOLTAGE_COMPARE_40 (0 << 5) 39389c78134cc54dff016c83367912eb055637fa50cAlan Cox#define CRT_HOTPLUG_VOLTAGE_COMPARE_50 (1 << 5) 39489c78134cc54dff016c83367912eb055637fa50cAlan Cox#define CRT_HOTPLUG_VOLTAGE_COMPARE_60 (2 << 5) 39589c78134cc54dff016c83367912eb055637fa50cAlan Cox#define CRT_HOTPLUG_VOLTAGE_COMPARE_70 (3 << 5) 39689c78134cc54dff016c83367912eb055637fa50cAlan Cox#define CRT_HOTPLUG_VOLTAGE_COMPARE_MASK (3 << 5) 39789c78134cc54dff016c83367912eb055637fa50cAlan Cox#define CRT_HOTPLUG_DETECT_DELAY_1G (0 << 4) 39889c78134cc54dff016c83367912eb055637fa50cAlan Cox#define CRT_HOTPLUG_DETECT_DELAY_2G (1 << 4) 39989c78134cc54dff016c83367912eb055637fa50cAlan Cox#define CRT_HOTPLUG_DETECT_VOLTAGE_325MV (0 << 2) 40089c78134cc54dff016c83367912eb055637fa50cAlan Cox#define CRT_HOTPLUG_DETECT_VOLTAGE_475MV (1 << 2) 40189c78134cc54dff016c83367912eb055637fa50cAlan Cox#define CRT_HOTPLUG_DETECT_MASK 0x000000F8 40289c78134cc54dff016c83367912eb055637fa50cAlan Cox 40389c78134cc54dff016c83367912eb055637fa50cAlan Cox#define PORT_HOTPLUG_STAT 0x61114 40489c78134cc54dff016c83367912eb055637fa50cAlan Cox#define CRT_HOTPLUG_INT_STATUS (1 << 11) 40589c78134cc54dff016c83367912eb055637fa50cAlan Cox#define TV_HOTPLUG_INT_STATUS (1 << 10) 40689c78134cc54dff016c83367912eb055637fa50cAlan Cox#define CRT_HOTPLUG_MONITOR_MASK (3 << 8) 40789c78134cc54dff016c83367912eb055637fa50cAlan Cox#define CRT_HOTPLUG_MONITOR_COLOR (3 << 8) 40889c78134cc54dff016c83367912eb055637fa50cAlan Cox#define CRT_HOTPLUG_MONITOR_MONO (2 << 8) 40989c78134cc54dff016c83367912eb055637fa50cAlan Cox#define CRT_HOTPLUG_MONITOR_NONE (0 << 8) 41089c78134cc54dff016c83367912eb055637fa50cAlan Cox#define SDVOC_HOTPLUG_INT_STATUS (1 << 7) 41189c78134cc54dff016c83367912eb055637fa50cAlan Cox#define SDVOB_HOTPLUG_INT_STATUS (1 << 6) 41289c78134cc54dff016c83367912eb055637fa50cAlan Cox 41389c78134cc54dff016c83367912eb055637fa50cAlan Cox#define SDVOB 0x61140 41489c78134cc54dff016c83367912eb055637fa50cAlan Cox#define SDVOC 0x61160 41589c78134cc54dff016c83367912eb055637fa50cAlan Cox#define SDVO_ENABLE (1 << 31) 41689c78134cc54dff016c83367912eb055637fa50cAlan Cox#define SDVO_PIPE_B_SELECT (1 << 30) 41789c78134cc54dff016c83367912eb055637fa50cAlan Cox#define SDVO_STALL_SELECT (1 << 29) 41889c78134cc54dff016c83367912eb055637fa50cAlan Cox#define SDVO_INTERRUPT_ENABLE (1 << 26) 4195736995b473b8853d5ee048c7dfb9c1d20ebf0eaPatrik Jakobsson#define SDVO_COLOR_RANGE_16_235 (1 << 8) 4205736995b473b8853d5ee048c7dfb9c1d20ebf0eaPatrik Jakobsson#define SDVO_AUDIO_ENABLE (1 << 6) 42189c78134cc54dff016c83367912eb055637fa50cAlan Cox 42289c78134cc54dff016c83367912eb055637fa50cAlan Cox/** 42389c78134cc54dff016c83367912eb055637fa50cAlan Cox * 915G/GM SDVO pixel multiplier. 42489c78134cc54dff016c83367912eb055637fa50cAlan Cox * 42589c78134cc54dff016c83367912eb055637fa50cAlan Cox * Programmed value is multiplier - 1, up to 5x. 42689c78134cc54dff016c83367912eb055637fa50cAlan Cox * 42789c78134cc54dff016c83367912eb055637fa50cAlan Cox * DPLL_MD_UDI_MULTIPLIER_MASK 42889c78134cc54dff016c83367912eb055637fa50cAlan Cox */ 42989c78134cc54dff016c83367912eb055637fa50cAlan Cox#define SDVO_PORT_MULTIPLY_MASK (7 << 23) 43089c78134cc54dff016c83367912eb055637fa50cAlan Cox#define SDVO_PORT_MULTIPLY_SHIFT 23 43189c78134cc54dff016c83367912eb055637fa50cAlan Cox#define SDVO_PHASE_SELECT_MASK (15 << 19) 43289c78134cc54dff016c83367912eb055637fa50cAlan Cox#define SDVO_PHASE_SELECT_DEFAULT (6 << 19) 43389c78134cc54dff016c83367912eb055637fa50cAlan Cox#define SDVO_CLOCK_OUTPUT_INVERT (1 << 18) 43489c78134cc54dff016c83367912eb055637fa50cAlan Cox#define SDVOC_GANG_MODE (1 << 16) 43589c78134cc54dff016c83367912eb055637fa50cAlan Cox#define SDVO_BORDER_ENABLE (1 << 7) 43689c78134cc54dff016c83367912eb055637fa50cAlan Cox#define SDVOB_PCIE_CONCURRENCY (1 << 3) 43789c78134cc54dff016c83367912eb055637fa50cAlan Cox#define SDVO_DETECTED (1 << 2) 43889c78134cc54dff016c83367912eb055637fa50cAlan Cox/* Bits to be preserved when writing */ 43989c78134cc54dff016c83367912eb055637fa50cAlan Cox#define SDVOB_PRESERVE_MASK ((1 << 17) | (1 << 16) | (1 << 14)) 44089c78134cc54dff016c83367912eb055637fa50cAlan Cox#define SDVOC_PRESERVE_MASK (1 << 17) 44189c78134cc54dff016c83367912eb055637fa50cAlan Cox 44289c78134cc54dff016c83367912eb055637fa50cAlan Cox/* 44389c78134cc54dff016c83367912eb055637fa50cAlan Cox * This register controls the LVDS output enable, pipe selection, and data 44489c78134cc54dff016c83367912eb055637fa50cAlan Cox * format selection. 44589c78134cc54dff016c83367912eb055637fa50cAlan Cox * 44689c78134cc54dff016c83367912eb055637fa50cAlan Cox * All of the clock/data pairs are force powered down by power sequencing. 44789c78134cc54dff016c83367912eb055637fa50cAlan Cox */ 44889c78134cc54dff016c83367912eb055637fa50cAlan Cox#define LVDS 0x61180 44989c78134cc54dff016c83367912eb055637fa50cAlan Cox/* 45089c78134cc54dff016c83367912eb055637fa50cAlan Cox * Enables the LVDS port. This bit must be set before DPLLs are enabled, as 45189c78134cc54dff016c83367912eb055637fa50cAlan Cox * the DPLL semantics change when the LVDS is assigned to that pipe. 45289c78134cc54dff016c83367912eb055637fa50cAlan Cox */ 45389c78134cc54dff016c83367912eb055637fa50cAlan Cox#define LVDS_PORT_EN (1 << 31) 45489c78134cc54dff016c83367912eb055637fa50cAlan Cox/* Selects pipe B for LVDS data. Must be set on pre-965. */ 45589c78134cc54dff016c83367912eb055637fa50cAlan Cox#define LVDS_PIPEB_SELECT (1 << 30) 45689c78134cc54dff016c83367912eb055637fa50cAlan Cox 45789c78134cc54dff016c83367912eb055637fa50cAlan Cox/* Turns on border drawing to allow centered display. */ 45889c78134cc54dff016c83367912eb055637fa50cAlan Cox#define LVDS_BORDER_EN (1 << 15) 45989c78134cc54dff016c83367912eb055637fa50cAlan Cox 46089c78134cc54dff016c83367912eb055637fa50cAlan Cox/* 46189c78134cc54dff016c83367912eb055637fa50cAlan Cox * Enables the A0-A2 data pairs and CLKA, containing 18 bits of color data per 46289c78134cc54dff016c83367912eb055637fa50cAlan Cox * pixel. 46389c78134cc54dff016c83367912eb055637fa50cAlan Cox */ 46489c78134cc54dff016c83367912eb055637fa50cAlan Cox#define LVDS_A0A2_CLKA_POWER_MASK (3 << 8) 46589c78134cc54dff016c83367912eb055637fa50cAlan Cox#define LVDS_A0A2_CLKA_POWER_DOWN (0 << 8) 46689c78134cc54dff016c83367912eb055637fa50cAlan Cox#define LVDS_A0A2_CLKA_POWER_UP (3 << 8) 46789c78134cc54dff016c83367912eb055637fa50cAlan Cox/* 46889c78134cc54dff016c83367912eb055637fa50cAlan Cox * Controls the A3 data pair, which contains the additional LSBs for 24 bit 46989c78134cc54dff016c83367912eb055637fa50cAlan Cox * mode. Only enabled if LVDS_A0A2_CLKA_POWER_UP also indicates it should be 47089c78134cc54dff016c83367912eb055637fa50cAlan Cox * on. 47189c78134cc54dff016c83367912eb055637fa50cAlan Cox */ 47289c78134cc54dff016c83367912eb055637fa50cAlan Cox#define LVDS_A3_POWER_MASK (3 << 6) 47389c78134cc54dff016c83367912eb055637fa50cAlan Cox#define LVDS_A3_POWER_DOWN (0 << 6) 47489c78134cc54dff016c83367912eb055637fa50cAlan Cox#define LVDS_A3_POWER_UP (3 << 6) 47589c78134cc54dff016c83367912eb055637fa50cAlan Cox/* 47689c78134cc54dff016c83367912eb055637fa50cAlan Cox * Controls the CLKB pair. This should only be set when LVDS_B0B3_POWER_UP 47789c78134cc54dff016c83367912eb055637fa50cAlan Cox * is set. 47889c78134cc54dff016c83367912eb055637fa50cAlan Cox */ 47989c78134cc54dff016c83367912eb055637fa50cAlan Cox#define LVDS_CLKB_POWER_MASK (3 << 4) 48089c78134cc54dff016c83367912eb055637fa50cAlan Cox#define LVDS_CLKB_POWER_DOWN (0 << 4) 48189c78134cc54dff016c83367912eb055637fa50cAlan Cox#define LVDS_CLKB_POWER_UP (3 << 4) 48289c78134cc54dff016c83367912eb055637fa50cAlan Cox/* 48389c78134cc54dff016c83367912eb055637fa50cAlan Cox * Controls the B0-B3 data pairs. This must be set to match the DPLL p2 48489c78134cc54dff016c83367912eb055637fa50cAlan Cox * setting for whether we are in dual-channel mode. The B3 pair will 48589c78134cc54dff016c83367912eb055637fa50cAlan Cox * additionally only be powered up when LVDS_A3_POWER_UP is set. 48689c78134cc54dff016c83367912eb055637fa50cAlan Cox */ 48789c78134cc54dff016c83367912eb055637fa50cAlan Cox#define LVDS_B0B3_POWER_MASK (3 << 2) 48889c78134cc54dff016c83367912eb055637fa50cAlan Cox#define LVDS_B0B3_POWER_DOWN (0 << 2) 48989c78134cc54dff016c83367912eb055637fa50cAlan Cox#define LVDS_B0B3_POWER_UP (3 << 2) 49089c78134cc54dff016c83367912eb055637fa50cAlan Cox 49189c78134cc54dff016c83367912eb055637fa50cAlan Cox#define PIPEACONF 0x70008 49289c78134cc54dff016c83367912eb055637fa50cAlan Cox#define PIPEACONF_ENABLE (1 << 31) 49389c78134cc54dff016c83367912eb055637fa50cAlan Cox#define PIPEACONF_DISABLE 0 49489c78134cc54dff016c83367912eb055637fa50cAlan Cox#define PIPEACONF_DOUBLE_WIDE (1 << 30) 49589c78134cc54dff016c83367912eb055637fa50cAlan Cox#define PIPECONF_ACTIVE (1 << 30) 49689c78134cc54dff016c83367912eb055637fa50cAlan Cox#define PIPECONF_DSIPLL_LOCK (1 << 29) 49789c78134cc54dff016c83367912eb055637fa50cAlan Cox#define PIPEACONF_SINGLE_WIDE 0 49889c78134cc54dff016c83367912eb055637fa50cAlan Cox#define PIPEACONF_PIPE_UNLOCKED 0 49989c78134cc54dff016c83367912eb055637fa50cAlan Cox#define PIPEACONF_DSR (1 << 26) 50089c78134cc54dff016c83367912eb055637fa50cAlan Cox#define PIPEACONF_PIPE_LOCKED (1 << 25) 50189c78134cc54dff016c83367912eb055637fa50cAlan Cox#define PIPEACONF_PALETTE 0 50289c78134cc54dff016c83367912eb055637fa50cAlan Cox#define PIPECONF_FORCE_BORDER (1 << 25) 50389c78134cc54dff016c83367912eb055637fa50cAlan Cox#define PIPEACONF_GAMMA (1 << 24) 50489c78134cc54dff016c83367912eb055637fa50cAlan Cox#define PIPECONF_PROGRESSIVE (0 << 21) 50589c78134cc54dff016c83367912eb055637fa50cAlan Cox#define PIPECONF_INTERLACE_W_FIELD_INDICATION (6 << 21) 50689c78134cc54dff016c83367912eb055637fa50cAlan Cox#define PIPECONF_INTERLACE_FIELD_0_ONLY (7 << 21) 50789c78134cc54dff016c83367912eb055637fa50cAlan Cox#define PIPECONF_PLANE_OFF (1 << 19) 50889c78134cc54dff016c83367912eb055637fa50cAlan Cox#define PIPECONF_CURSOR_OFF (1 << 18) 50989c78134cc54dff016c83367912eb055637fa50cAlan Cox 51089c78134cc54dff016c83367912eb055637fa50cAlan Cox#define PIPEBCONF 0x71008 51189c78134cc54dff016c83367912eb055637fa50cAlan Cox#define PIPEBCONF_ENABLE (1 << 31) 51289c78134cc54dff016c83367912eb055637fa50cAlan Cox#define PIPEBCONF_DISABLE 0 51389c78134cc54dff016c83367912eb055637fa50cAlan Cox#define PIPEBCONF_DOUBLE_WIDE (1 << 30) 51489c78134cc54dff016c83367912eb055637fa50cAlan Cox#define PIPEBCONF_DISABLE 0 51589c78134cc54dff016c83367912eb055637fa50cAlan Cox#define PIPEBCONF_GAMMA (1 << 24) 51689c78134cc54dff016c83367912eb055637fa50cAlan Cox#define PIPEBCONF_PALETTE 0 51789c78134cc54dff016c83367912eb055637fa50cAlan Cox 51889c78134cc54dff016c83367912eb055637fa50cAlan Cox#define PIPECCONF 0x72008 51989c78134cc54dff016c83367912eb055637fa50cAlan Cox 52089c78134cc54dff016c83367912eb055637fa50cAlan Cox#define PIPEBGCMAXRED 0x71010 52189c78134cc54dff016c83367912eb055637fa50cAlan Cox#define PIPEBGCMAXGREEN 0x71014 52289c78134cc54dff016c83367912eb055637fa50cAlan Cox#define PIPEBGCMAXBLUE 0x71018 52389c78134cc54dff016c83367912eb055637fa50cAlan Cox 52489c78134cc54dff016c83367912eb055637fa50cAlan Cox#define PIPEASTAT 0x70024 52589c78134cc54dff016c83367912eb055637fa50cAlan Cox#define PIPEBSTAT 0x71024 52689c78134cc54dff016c83367912eb055637fa50cAlan Cox#define PIPECSTAT 0x72024 52789c78134cc54dff016c83367912eb055637fa50cAlan Cox#define PIPE_VBLANK_INTERRUPT_STATUS (1UL << 1) 52889c78134cc54dff016c83367912eb055637fa50cAlan Cox#define PIPE_START_VBLANK_INTERRUPT_STATUS (1UL << 2) 52989c78134cc54dff016c83367912eb055637fa50cAlan Cox#define PIPE_VBLANK_CLEAR (1 << 1) 53089c78134cc54dff016c83367912eb055637fa50cAlan Cox#define PIPE_VBLANK_STATUS (1 << 1) 53189c78134cc54dff016c83367912eb055637fa50cAlan Cox#define PIPE_TE_STATUS (1UL << 6) 53289c78134cc54dff016c83367912eb055637fa50cAlan Cox#define PIPE_DPST_EVENT_STATUS (1UL << 7) 53389c78134cc54dff016c83367912eb055637fa50cAlan Cox#define PIPE_VSYNC_CLEAR (1UL << 9) 53489c78134cc54dff016c83367912eb055637fa50cAlan Cox#define PIPE_VSYNC_STATUS (1UL << 9) 53589c78134cc54dff016c83367912eb055637fa50cAlan Cox#define PIPE_HDMI_AUDIO_UNDERRUN_STATUS (1UL << 10) 53689c78134cc54dff016c83367912eb055637fa50cAlan Cox#define PIPE_HDMI_AUDIO_BUFFER_DONE_STATUS (1UL << 11) 53789c78134cc54dff016c83367912eb055637fa50cAlan Cox#define PIPE_VBLANK_INTERRUPT_ENABLE (1UL << 17) 53889c78134cc54dff016c83367912eb055637fa50cAlan Cox#define PIPE_START_VBLANK_INTERRUPT_ENABLE (1UL << 18) 53989c78134cc54dff016c83367912eb055637fa50cAlan Cox#define PIPE_TE_ENABLE (1UL << 22) 540d839ede47a56ff5f316c88391818488f8e5913afAlan Cox#define PIPE_LEGACY_BLC_EVENT_ENABLE (1UL << 22) 54189c78134cc54dff016c83367912eb055637fa50cAlan Cox#define PIPE_DPST_EVENT_ENABLE (1UL << 23) 54289c78134cc54dff016c83367912eb055637fa50cAlan Cox#define PIPE_VSYNC_ENABL (1UL << 25) 54389c78134cc54dff016c83367912eb055637fa50cAlan Cox#define PIPE_HDMI_AUDIO_UNDERRUN (1UL << 26) 54489c78134cc54dff016c83367912eb055637fa50cAlan Cox#define PIPE_HDMI_AUDIO_BUFFER_DONE (1UL << 27) 545acd7ef927e06510fbfeec8d307f4726a156b2733Alan Cox#define PIPE_FIFO_UNDERRUN (1UL << 31) 54689c78134cc54dff016c83367912eb055637fa50cAlan Cox#define PIPE_HDMI_AUDIO_INT_MASK (PIPE_HDMI_AUDIO_UNDERRUN | \ 54789c78134cc54dff016c83367912eb055637fa50cAlan Cox PIPE_HDMI_AUDIO_BUFFER_DONE) 54889c78134cc54dff016c83367912eb055637fa50cAlan Cox#define PIPE_EVENT_MASK ((1 << 29)|(1 << 28)|(1 << 27)|(1 << 26)|(1 << 24)|(1 << 23)|(1 << 22)|(1 << 21)|(1 << 20)|(1 << 16)) 54989c78134cc54dff016c83367912eb055637fa50cAlan Cox#define PIPE_VBLANK_MASK ((1 << 25)|(1 << 24)|(1 << 18)|(1 << 17)) 55089c78134cc54dff016c83367912eb055637fa50cAlan Cox#define HISTOGRAM_INT_CONTROL 0x61268 55189c78134cc54dff016c83367912eb055637fa50cAlan Cox#define HISTOGRAM_BIN_DATA 0X61264 55289c78134cc54dff016c83367912eb055637fa50cAlan Cox#define HISTOGRAM_LOGIC_CONTROL 0x61260 55389c78134cc54dff016c83367912eb055637fa50cAlan Cox#define PWM_CONTROL_LOGIC 0x61250 55489c78134cc54dff016c83367912eb055637fa50cAlan Cox#define PIPE_HOTPLUG_INTERRUPT_STATUS (1UL << 10) 55589c78134cc54dff016c83367912eb055637fa50cAlan Cox#define HISTOGRAM_INTERRUPT_ENABLE (1UL << 31) 55689c78134cc54dff016c83367912eb055637fa50cAlan Cox#define HISTOGRAM_LOGIC_ENABLE (1UL << 31) 55789c78134cc54dff016c83367912eb055637fa50cAlan Cox#define PWM_LOGIC_ENABLE (1UL << 31) 55889c78134cc54dff016c83367912eb055637fa50cAlan Cox#define PWM_PHASEIN_ENABLE (1UL << 25) 55989c78134cc54dff016c83367912eb055637fa50cAlan Cox#define PWM_PHASEIN_INT_ENABLE (1UL << 24) 56089c78134cc54dff016c83367912eb055637fa50cAlan Cox#define PWM_PHASEIN_VB_COUNT 0x00001f00 56189c78134cc54dff016c83367912eb055637fa50cAlan Cox#define PWM_PHASEIN_INC 0x0000001f 56289c78134cc54dff016c83367912eb055637fa50cAlan Cox#define HISTOGRAM_INT_CTRL_CLEAR (1UL << 30) 56389c78134cc54dff016c83367912eb055637fa50cAlan Cox#define DPST_YUV_LUMA_MODE 0 56489c78134cc54dff016c83367912eb055637fa50cAlan Cox 56589c78134cc54dff016c83367912eb055637fa50cAlan Coxstruct dpst_ie_histogram_control { 56689c78134cc54dff016c83367912eb055637fa50cAlan Cox union { 56789c78134cc54dff016c83367912eb055637fa50cAlan Cox uint32_t data; 56889c78134cc54dff016c83367912eb055637fa50cAlan Cox struct { 56989c78134cc54dff016c83367912eb055637fa50cAlan Cox uint32_t bin_reg_index:7; 57089c78134cc54dff016c83367912eb055637fa50cAlan Cox uint32_t reserved:4; 57189c78134cc54dff016c83367912eb055637fa50cAlan Cox uint32_t bin_reg_func_select:1; 57289c78134cc54dff016c83367912eb055637fa50cAlan Cox uint32_t sync_to_phase_in:1; 57389c78134cc54dff016c83367912eb055637fa50cAlan Cox uint32_t alt_enhancement_mode:2; 57489c78134cc54dff016c83367912eb055637fa50cAlan Cox uint32_t reserved1:1; 57589c78134cc54dff016c83367912eb055637fa50cAlan Cox uint32_t sync_to_phase_in_count:8; 57689c78134cc54dff016c83367912eb055637fa50cAlan Cox uint32_t histogram_mode_select:1; 57789c78134cc54dff016c83367912eb055637fa50cAlan Cox uint32_t reserved2:4; 57889c78134cc54dff016c83367912eb055637fa50cAlan Cox uint32_t ie_pipe_assignment:1; 57989c78134cc54dff016c83367912eb055637fa50cAlan Cox uint32_t ie_mode_table_enabled:1; 58089c78134cc54dff016c83367912eb055637fa50cAlan Cox uint32_t ie_histogram_enable:1; 58189c78134cc54dff016c83367912eb055637fa50cAlan Cox }; 58289c78134cc54dff016c83367912eb055637fa50cAlan Cox }; 58389c78134cc54dff016c83367912eb055637fa50cAlan Cox}; 58489c78134cc54dff016c83367912eb055637fa50cAlan Cox 58589c78134cc54dff016c83367912eb055637fa50cAlan Coxstruct dpst_guardband { 58689c78134cc54dff016c83367912eb055637fa50cAlan Cox union { 58789c78134cc54dff016c83367912eb055637fa50cAlan Cox uint32_t data; 58889c78134cc54dff016c83367912eb055637fa50cAlan Cox struct { 58989c78134cc54dff016c83367912eb055637fa50cAlan Cox uint32_t guardband:22; 59089c78134cc54dff016c83367912eb055637fa50cAlan Cox uint32_t guardband_interrupt_delay:8; 59189c78134cc54dff016c83367912eb055637fa50cAlan Cox uint32_t interrupt_status:1; 59289c78134cc54dff016c83367912eb055637fa50cAlan Cox uint32_t interrupt_enable:1; 59389c78134cc54dff016c83367912eb055637fa50cAlan Cox }; 59489c78134cc54dff016c83367912eb055637fa50cAlan Cox }; 59589c78134cc54dff016c83367912eb055637fa50cAlan Cox}; 59689c78134cc54dff016c83367912eb055637fa50cAlan Cox 59789c78134cc54dff016c83367912eb055637fa50cAlan Cox#define PIPEAFRAMEHIGH 0x70040 59889c78134cc54dff016c83367912eb055637fa50cAlan Cox#define PIPEAFRAMEPIXEL 0x70044 59989c78134cc54dff016c83367912eb055637fa50cAlan Cox#define PIPEBFRAMEHIGH 0x71040 60089c78134cc54dff016c83367912eb055637fa50cAlan Cox#define PIPEBFRAMEPIXEL 0x71044 60189c78134cc54dff016c83367912eb055637fa50cAlan Cox#define PIPECFRAMEHIGH 0x72040 60289c78134cc54dff016c83367912eb055637fa50cAlan Cox#define PIPECFRAMEPIXEL 0x72044 60389c78134cc54dff016c83367912eb055637fa50cAlan Cox#define PIPE_FRAME_HIGH_MASK 0x0000ffff 60489c78134cc54dff016c83367912eb055637fa50cAlan Cox#define PIPE_FRAME_HIGH_SHIFT 0 60589c78134cc54dff016c83367912eb055637fa50cAlan Cox#define PIPE_FRAME_LOW_MASK 0xff000000 60689c78134cc54dff016c83367912eb055637fa50cAlan Cox#define PIPE_FRAME_LOW_SHIFT 24 60789c78134cc54dff016c83367912eb055637fa50cAlan Cox#define PIPE_PIXEL_MASK 0x00ffffff 60889c78134cc54dff016c83367912eb055637fa50cAlan Cox#define PIPE_PIXEL_SHIFT 0 60989c78134cc54dff016c83367912eb055637fa50cAlan Cox 610acd7ef927e06510fbfeec8d307f4726a156b2733Alan Cox#define FW_BLC_SELF 0x20e0 611acd7ef927e06510fbfeec8d307f4726a156b2733Alan Cox#define FW_BLC_SELF_EN (1<<15) 612acd7ef927e06510fbfeec8d307f4726a156b2733Alan Cox 61389c78134cc54dff016c83367912eb055637fa50cAlan Cox#define DSPARB 0x70030 61489c78134cc54dff016c83367912eb055637fa50cAlan Cox#define DSPFW1 0x70034 615acd7ef927e06510fbfeec8d307f4726a156b2733Alan Cox#define DSP_FIFO_SR_WM_MASK 0xFF800000 616acd7ef927e06510fbfeec8d307f4726a156b2733Alan Cox#define DSP_FIFO_SR_WM_SHIFT 23 617acd7ef927e06510fbfeec8d307f4726a156b2733Alan Cox#define CURSOR_B_FIFO_WM_MASK 0x003F0000 618acd7ef927e06510fbfeec8d307f4726a156b2733Alan Cox#define CURSOR_B_FIFO_WM_SHIFT 16 61989c78134cc54dff016c83367912eb055637fa50cAlan Cox#define DSPFW2 0x70038 620acd7ef927e06510fbfeec8d307f4726a156b2733Alan Cox#define CURSOR_A_FIFO_WM_MASK 0x3F00 621acd7ef927e06510fbfeec8d307f4726a156b2733Alan Cox#define CURSOR_A_FIFO_WM_SHIFT 8 622acd7ef927e06510fbfeec8d307f4726a156b2733Alan Cox#define DSP_PLANE_C_FIFO_WM_MASK 0x7F 623acd7ef927e06510fbfeec8d307f4726a156b2733Alan Cox#define DSP_PLANE_C_FIFO_WM_SHIFT 0 62489c78134cc54dff016c83367912eb055637fa50cAlan Cox#define DSPFW3 0x7003c 62589c78134cc54dff016c83367912eb055637fa50cAlan Cox#define DSPFW4 0x70050 62689c78134cc54dff016c83367912eb055637fa50cAlan Cox#define DSPFW5 0x70054 627acd7ef927e06510fbfeec8d307f4726a156b2733Alan Cox#define DSP_PLANE_B_FIFO_WM1_SHIFT 24 628acd7ef927e06510fbfeec8d307f4726a156b2733Alan Cox#define DSP_PLANE_A_FIFO_WM1_SHIFT 16 629acd7ef927e06510fbfeec8d307f4726a156b2733Alan Cox#define CURSOR_B_FIFO_WM1_SHIFT 8 630acd7ef927e06510fbfeec8d307f4726a156b2733Alan Cox#define CURSOR_FIFO_SR_WM1_SHIFT 0 63189c78134cc54dff016c83367912eb055637fa50cAlan Cox#define DSPFW6 0x70058 63289c78134cc54dff016c83367912eb055637fa50cAlan Cox#define DSPCHICKENBIT 0x70400 63389c78134cc54dff016c83367912eb055637fa50cAlan Cox#define DSPACNTR 0x70180 63489c78134cc54dff016c83367912eb055637fa50cAlan Cox#define DSPBCNTR 0x71180 63589c78134cc54dff016c83367912eb055637fa50cAlan Cox#define DSPCCNTR 0x72180 63689c78134cc54dff016c83367912eb055637fa50cAlan Cox#define DISPLAY_PLANE_ENABLE (1 << 31) 63789c78134cc54dff016c83367912eb055637fa50cAlan Cox#define DISPLAY_PLANE_DISABLE 0 63889c78134cc54dff016c83367912eb055637fa50cAlan Cox#define DISPPLANE_GAMMA_ENABLE (1 << 30) 63989c78134cc54dff016c83367912eb055637fa50cAlan Cox#define DISPPLANE_GAMMA_DISABLE 0 64089c78134cc54dff016c83367912eb055637fa50cAlan Cox#define DISPPLANE_PIXFORMAT_MASK (0xf << 26) 64189c78134cc54dff016c83367912eb055637fa50cAlan Cox#define DISPPLANE_8BPP (0x2 << 26) 64289c78134cc54dff016c83367912eb055637fa50cAlan Cox#define DISPPLANE_15_16BPP (0x4 << 26) 64389c78134cc54dff016c83367912eb055637fa50cAlan Cox#define DISPPLANE_16BPP (0x5 << 26) 64489c78134cc54dff016c83367912eb055637fa50cAlan Cox#define DISPPLANE_32BPP_NO_ALPHA (0x6 << 26) 64589c78134cc54dff016c83367912eb055637fa50cAlan Cox#define DISPPLANE_32BPP (0x7 << 26) 64689c78134cc54dff016c83367912eb055637fa50cAlan Cox#define DISPPLANE_STEREO_ENABLE (1 << 25) 64789c78134cc54dff016c83367912eb055637fa50cAlan Cox#define DISPPLANE_STEREO_DISABLE 0 64889c78134cc54dff016c83367912eb055637fa50cAlan Cox#define DISPPLANE_SEL_PIPE_MASK (1 << 24) 64989c78134cc54dff016c83367912eb055637fa50cAlan Cox#define DISPPLANE_SEL_PIPE_POS 24 65089c78134cc54dff016c83367912eb055637fa50cAlan Cox#define DISPPLANE_SEL_PIPE_A 0 65189c78134cc54dff016c83367912eb055637fa50cAlan Cox#define DISPPLANE_SEL_PIPE_B (1 << 24) 65289c78134cc54dff016c83367912eb055637fa50cAlan Cox#define DISPPLANE_SRC_KEY_ENABLE (1 << 22) 65389c78134cc54dff016c83367912eb055637fa50cAlan Cox#define DISPPLANE_SRC_KEY_DISABLE 0 65489c78134cc54dff016c83367912eb055637fa50cAlan Cox#define DISPPLANE_LINE_DOUBLE (1 << 20) 65589c78134cc54dff016c83367912eb055637fa50cAlan Cox#define DISPPLANE_NO_LINE_DOUBLE 0 65689c78134cc54dff016c83367912eb055637fa50cAlan Cox#define DISPPLANE_STEREO_POLARITY_FIRST 0 65789c78134cc54dff016c83367912eb055637fa50cAlan Cox#define DISPPLANE_STEREO_POLARITY_SECOND (1 << 18) 65889c78134cc54dff016c83367912eb055637fa50cAlan Cox/* plane B only */ 65989c78134cc54dff016c83367912eb055637fa50cAlan Cox#define DISPPLANE_ALPHA_TRANS_ENABLE (1 << 15) 66089c78134cc54dff016c83367912eb055637fa50cAlan Cox#define DISPPLANE_ALPHA_TRANS_DISABLE 0 66189c78134cc54dff016c83367912eb055637fa50cAlan Cox#define DISPPLANE_SPRITE_ABOVE_DISPLAYA 0 66289c78134cc54dff016c83367912eb055637fa50cAlan Cox#define DISPPLANE_SPRITE_ABOVE_OVERLAY (1) 66389c78134cc54dff016c83367912eb055637fa50cAlan Cox#define DISPPLANE_BOTTOM (4) 66489c78134cc54dff016c83367912eb055637fa50cAlan Cox 66589c78134cc54dff016c83367912eb055637fa50cAlan Cox#define DSPABASE 0x70184 66689c78134cc54dff016c83367912eb055637fa50cAlan Cox#define DSPALINOFF 0x70184 66789c78134cc54dff016c83367912eb055637fa50cAlan Cox#define DSPASTRIDE 0x70188 66889c78134cc54dff016c83367912eb055637fa50cAlan Cox 66989c78134cc54dff016c83367912eb055637fa50cAlan Cox#define DSPBBASE 0x71184 67089c78134cc54dff016c83367912eb055637fa50cAlan Cox#define DSPBLINOFF 0X71184 67189c78134cc54dff016c83367912eb055637fa50cAlan Cox#define DSPBADDR DSPBBASE 67289c78134cc54dff016c83367912eb055637fa50cAlan Cox#define DSPBSTRIDE 0x71188 67389c78134cc54dff016c83367912eb055637fa50cAlan Cox 67489c78134cc54dff016c83367912eb055637fa50cAlan Cox#define DSPCBASE 0x72184 67589c78134cc54dff016c83367912eb055637fa50cAlan Cox#define DSPCLINOFF 0x72184 67689c78134cc54dff016c83367912eb055637fa50cAlan Cox#define DSPCSTRIDE 0x72188 67789c78134cc54dff016c83367912eb055637fa50cAlan Cox 67889c78134cc54dff016c83367912eb055637fa50cAlan Cox#define DSPAKEYVAL 0x70194 67989c78134cc54dff016c83367912eb055637fa50cAlan Cox#define DSPAKEYMASK 0x70198 68089c78134cc54dff016c83367912eb055637fa50cAlan Cox 68189c78134cc54dff016c83367912eb055637fa50cAlan Cox#define DSPAPOS 0x7018C /* reserved */ 68289c78134cc54dff016c83367912eb055637fa50cAlan Cox#define DSPASIZE 0x70190 68389c78134cc54dff016c83367912eb055637fa50cAlan Cox#define DSPBPOS 0x7118C 68489c78134cc54dff016c83367912eb055637fa50cAlan Cox#define DSPBSIZE 0x71190 68589c78134cc54dff016c83367912eb055637fa50cAlan Cox#define DSPCPOS 0x7218C 68689c78134cc54dff016c83367912eb055637fa50cAlan Cox#define DSPCSIZE 0x72190 68789c78134cc54dff016c83367912eb055637fa50cAlan Cox 68889c78134cc54dff016c83367912eb055637fa50cAlan Cox#define DSPASURF 0x7019C 68989c78134cc54dff016c83367912eb055637fa50cAlan Cox#define DSPATILEOFF 0x701A4 69089c78134cc54dff016c83367912eb055637fa50cAlan Cox 69189c78134cc54dff016c83367912eb055637fa50cAlan Cox#define DSPBSURF 0x7119C 69289c78134cc54dff016c83367912eb055637fa50cAlan Cox#define DSPBTILEOFF 0x711A4 69389c78134cc54dff016c83367912eb055637fa50cAlan Cox 69489c78134cc54dff016c83367912eb055637fa50cAlan Cox#define DSPCSURF 0x7219C 69589c78134cc54dff016c83367912eb055637fa50cAlan Cox#define DSPCTILEOFF 0x721A4 69689c78134cc54dff016c83367912eb055637fa50cAlan Cox#define DSPCKEYMAXVAL 0x721A0 69789c78134cc54dff016c83367912eb055637fa50cAlan Cox#define DSPCKEYMINVAL 0x72194 69889c78134cc54dff016c83367912eb055637fa50cAlan Cox#define DSPCKEYMSK 0x72198 69989c78134cc54dff016c83367912eb055637fa50cAlan Cox 70089c78134cc54dff016c83367912eb055637fa50cAlan Cox#define VGACNTRL 0x71400 70189c78134cc54dff016c83367912eb055637fa50cAlan Cox#define VGA_DISP_DISABLE (1 << 31) 70289c78134cc54dff016c83367912eb055637fa50cAlan Cox#define VGA_2X_MODE (1 << 30) 70389c78134cc54dff016c83367912eb055637fa50cAlan Cox#define VGA_PIPE_B_SELECT (1 << 29) 70489c78134cc54dff016c83367912eb055637fa50cAlan Cox 70589c78134cc54dff016c83367912eb055637fa50cAlan Cox/* 70689c78134cc54dff016c83367912eb055637fa50cAlan Cox * Overlay registers 70789c78134cc54dff016c83367912eb055637fa50cAlan Cox */ 70889c78134cc54dff016c83367912eb055637fa50cAlan Cox#define OV_C_OFFSET 0x08000 70989c78134cc54dff016c83367912eb055637fa50cAlan Cox#define OV_OVADD 0x30000 71089c78134cc54dff016c83367912eb055637fa50cAlan Cox#define OV_DOVASTA 0x30008 71189c78134cc54dff016c83367912eb055637fa50cAlan Cox# define OV_PIPE_SELECT ((1 << 6)|(1 << 7)) 71289c78134cc54dff016c83367912eb055637fa50cAlan Cox# define OV_PIPE_SELECT_POS 6 71389c78134cc54dff016c83367912eb055637fa50cAlan Cox# define OV_PIPE_A 0 71489c78134cc54dff016c83367912eb055637fa50cAlan Cox# define OV_PIPE_C 1 71589c78134cc54dff016c83367912eb055637fa50cAlan Cox#define OV_OGAMC5 0x30010 71689c78134cc54dff016c83367912eb055637fa50cAlan Cox#define OV_OGAMC4 0x30014 71789c78134cc54dff016c83367912eb055637fa50cAlan Cox#define OV_OGAMC3 0x30018 71889c78134cc54dff016c83367912eb055637fa50cAlan Cox#define OV_OGAMC2 0x3001C 71989c78134cc54dff016c83367912eb055637fa50cAlan Cox#define OV_OGAMC1 0x30020 72089c78134cc54dff016c83367912eb055637fa50cAlan Cox#define OV_OGAMC0 0x30024 72189c78134cc54dff016c83367912eb055637fa50cAlan Cox#define OVC_OVADD 0x38000 72289c78134cc54dff016c83367912eb055637fa50cAlan Cox#define OVC_DOVCSTA 0x38008 72389c78134cc54dff016c83367912eb055637fa50cAlan Cox#define OVC_OGAMC5 0x38010 72489c78134cc54dff016c83367912eb055637fa50cAlan Cox#define OVC_OGAMC4 0x38014 72589c78134cc54dff016c83367912eb055637fa50cAlan Cox#define OVC_OGAMC3 0x38018 72689c78134cc54dff016c83367912eb055637fa50cAlan Cox#define OVC_OGAMC2 0x3801C 72789c78134cc54dff016c83367912eb055637fa50cAlan Cox#define OVC_OGAMC1 0x38020 72889c78134cc54dff016c83367912eb055637fa50cAlan Cox#define OVC_OGAMC0 0x38024 72989c78134cc54dff016c83367912eb055637fa50cAlan Cox 73089c78134cc54dff016c83367912eb055637fa50cAlan Cox/* 73189c78134cc54dff016c83367912eb055637fa50cAlan Cox * Some BIOS scratch area registers. The 845 (and 830?) store the amount 73289c78134cc54dff016c83367912eb055637fa50cAlan Cox * of video memory available to the BIOS in SWF1. 73389c78134cc54dff016c83367912eb055637fa50cAlan Cox */ 73489c78134cc54dff016c83367912eb055637fa50cAlan Cox#define SWF0 0x71410 73589c78134cc54dff016c83367912eb055637fa50cAlan Cox#define SWF1 0x71414 73689c78134cc54dff016c83367912eb055637fa50cAlan Cox#define SWF2 0x71418 73789c78134cc54dff016c83367912eb055637fa50cAlan Cox#define SWF3 0x7141c 73889c78134cc54dff016c83367912eb055637fa50cAlan Cox#define SWF4 0x71420 73989c78134cc54dff016c83367912eb055637fa50cAlan Cox#define SWF5 0x71424 74089c78134cc54dff016c83367912eb055637fa50cAlan Cox#define SWF6 0x71428 74189c78134cc54dff016c83367912eb055637fa50cAlan Cox 74289c78134cc54dff016c83367912eb055637fa50cAlan Cox/* 74389c78134cc54dff016c83367912eb055637fa50cAlan Cox * 855 scratch registers. 74489c78134cc54dff016c83367912eb055637fa50cAlan Cox */ 74589c78134cc54dff016c83367912eb055637fa50cAlan Cox#define SWF00 0x70410 74689c78134cc54dff016c83367912eb055637fa50cAlan Cox#define SWF01 0x70414 74789c78134cc54dff016c83367912eb055637fa50cAlan Cox#define SWF02 0x70418 74889c78134cc54dff016c83367912eb055637fa50cAlan Cox#define SWF03 0x7041c 74989c78134cc54dff016c83367912eb055637fa50cAlan Cox#define SWF04 0x70420 75089c78134cc54dff016c83367912eb055637fa50cAlan Cox#define SWF05 0x70424 75189c78134cc54dff016c83367912eb055637fa50cAlan Cox#define SWF06 0x70428 75289c78134cc54dff016c83367912eb055637fa50cAlan Cox 75389c78134cc54dff016c83367912eb055637fa50cAlan Cox#define SWF10 SWF0 75489c78134cc54dff016c83367912eb055637fa50cAlan Cox#define SWF11 SWF1 75589c78134cc54dff016c83367912eb055637fa50cAlan Cox#define SWF12 SWF2 75689c78134cc54dff016c83367912eb055637fa50cAlan Cox#define SWF13 SWF3 75789c78134cc54dff016c83367912eb055637fa50cAlan Cox#define SWF14 SWF4 75889c78134cc54dff016c83367912eb055637fa50cAlan Cox#define SWF15 SWF5 75989c78134cc54dff016c83367912eb055637fa50cAlan Cox#define SWF16 SWF6 76089c78134cc54dff016c83367912eb055637fa50cAlan Cox 76189c78134cc54dff016c83367912eb055637fa50cAlan Cox#define SWF30 0x72414 76289c78134cc54dff016c83367912eb055637fa50cAlan Cox#define SWF31 0x72418 76389c78134cc54dff016c83367912eb055637fa50cAlan Cox#define SWF32 0x7241c 76489c78134cc54dff016c83367912eb055637fa50cAlan Cox 76589c78134cc54dff016c83367912eb055637fa50cAlan Cox 76689c78134cc54dff016c83367912eb055637fa50cAlan Cox/* 76789c78134cc54dff016c83367912eb055637fa50cAlan Cox * Palette registers 76889c78134cc54dff016c83367912eb055637fa50cAlan Cox */ 76989c78134cc54dff016c83367912eb055637fa50cAlan Cox#define PALETTE_A 0x0a000 77089c78134cc54dff016c83367912eb055637fa50cAlan Cox#define PALETTE_B 0x0a800 77189c78134cc54dff016c83367912eb055637fa50cAlan Cox#define PALETTE_C 0x0ac00 77289c78134cc54dff016c83367912eb055637fa50cAlan Cox 77389c78134cc54dff016c83367912eb055637fa50cAlan Cox/* Cursor A & B regs */ 77489c78134cc54dff016c83367912eb055637fa50cAlan Cox#define CURACNTR 0x70080 77589c78134cc54dff016c83367912eb055637fa50cAlan Cox#define CURSOR_MODE_DISABLE 0x00 77689c78134cc54dff016c83367912eb055637fa50cAlan Cox#define CURSOR_MODE_64_32B_AX 0x07 77789c78134cc54dff016c83367912eb055637fa50cAlan Cox#define CURSOR_MODE_64_ARGB_AX ((1 << 5) | CURSOR_MODE_64_32B_AX) 77889c78134cc54dff016c83367912eb055637fa50cAlan Cox#define MCURSOR_GAMMA_ENABLE (1 << 26) 77989c78134cc54dff016c83367912eb055637fa50cAlan Cox#define CURABASE 0x70084 78089c78134cc54dff016c83367912eb055637fa50cAlan Cox#define CURAPOS 0x70088 78189c78134cc54dff016c83367912eb055637fa50cAlan Cox#define CURSOR_POS_MASK 0x007FF 78289c78134cc54dff016c83367912eb055637fa50cAlan Cox#define CURSOR_POS_SIGN 0x8000 78389c78134cc54dff016c83367912eb055637fa50cAlan Cox#define CURSOR_X_SHIFT 0 78489c78134cc54dff016c83367912eb055637fa50cAlan Cox#define CURSOR_Y_SHIFT 16 78589c78134cc54dff016c83367912eb055637fa50cAlan Cox#define CURBCNTR 0x700c0 78689c78134cc54dff016c83367912eb055637fa50cAlan Cox#define CURBBASE 0x700c4 78789c78134cc54dff016c83367912eb055637fa50cAlan Cox#define CURBPOS 0x700c8 78889c78134cc54dff016c83367912eb055637fa50cAlan Cox#define CURCCNTR 0x700e0 78989c78134cc54dff016c83367912eb055637fa50cAlan Cox#define CURCBASE 0x700e4 79089c78134cc54dff016c83367912eb055637fa50cAlan Cox#define CURCPOS 0x700e8 79189c78134cc54dff016c83367912eb055637fa50cAlan Cox 79289c78134cc54dff016c83367912eb055637fa50cAlan Cox/* 79389c78134cc54dff016c83367912eb055637fa50cAlan Cox * Interrupt Registers 79489c78134cc54dff016c83367912eb055637fa50cAlan Cox */ 79589c78134cc54dff016c83367912eb055637fa50cAlan Cox#define IER 0x020a0 79689c78134cc54dff016c83367912eb055637fa50cAlan Cox#define IIR 0x020a4 79789c78134cc54dff016c83367912eb055637fa50cAlan Cox#define IMR 0x020a8 79889c78134cc54dff016c83367912eb055637fa50cAlan Cox#define ISR 0x020ac 79989c78134cc54dff016c83367912eb055637fa50cAlan Cox 80089c78134cc54dff016c83367912eb055637fa50cAlan Cox/* 80189c78134cc54dff016c83367912eb055637fa50cAlan Cox * MOORESTOWN delta registers 80289c78134cc54dff016c83367912eb055637fa50cAlan Cox */ 80389c78134cc54dff016c83367912eb055637fa50cAlan Cox#define MRST_DPLL_A 0x0f014 80489c78134cc54dff016c83367912eb055637fa50cAlan Cox#define MDFLD_DPLL_B 0x0f018 80589c78134cc54dff016c83367912eb055637fa50cAlan Cox#define MDFLD_INPUT_REF_SEL (1 << 14) 80689c78134cc54dff016c83367912eb055637fa50cAlan Cox#define MDFLD_VCO_SEL (1 << 16) 80789c78134cc54dff016c83367912eb055637fa50cAlan Cox#define DPLLA_MODE_LVDS (2 << 26) /* mrst */ 80889c78134cc54dff016c83367912eb055637fa50cAlan Cox#define MDFLD_PLL_LATCHEN (1 << 28) 80989c78134cc54dff016c83367912eb055637fa50cAlan Cox#define MDFLD_PWR_GATE_EN (1 << 30) 81089c78134cc54dff016c83367912eb055637fa50cAlan Cox#define MDFLD_P1_MASK (0x1FF << 17) 81189c78134cc54dff016c83367912eb055637fa50cAlan Cox#define MRST_FPA0 0x0f040 81289c78134cc54dff016c83367912eb055637fa50cAlan Cox#define MRST_FPA1 0x0f044 81389c78134cc54dff016c83367912eb055637fa50cAlan Cox#define MDFLD_DPLL_DIV0 0x0f048 81489c78134cc54dff016c83367912eb055637fa50cAlan Cox#define MDFLD_DPLL_DIV1 0x0f04c 81589c78134cc54dff016c83367912eb055637fa50cAlan Cox#define MRST_PERF_MODE 0x020f4 81689c78134cc54dff016c83367912eb055637fa50cAlan Cox 81789c78134cc54dff016c83367912eb055637fa50cAlan Cox/* 81889c78134cc54dff016c83367912eb055637fa50cAlan Cox * MEDFIELD HDMI registers 81989c78134cc54dff016c83367912eb055637fa50cAlan Cox */ 82089c78134cc54dff016c83367912eb055637fa50cAlan Cox#define HDMIPHYMISCCTL 0x61134 82189c78134cc54dff016c83367912eb055637fa50cAlan Cox#define HDMI_PHY_POWER_DOWN 0x7f 82289c78134cc54dff016c83367912eb055637fa50cAlan Cox#define HDMIB_CONTROL 0x61140 82389c78134cc54dff016c83367912eb055637fa50cAlan Cox#define HDMIB_PORT_EN (1 << 31) 82489c78134cc54dff016c83367912eb055637fa50cAlan Cox#define HDMIB_PIPE_B_SELECT (1 << 30) 82589c78134cc54dff016c83367912eb055637fa50cAlan Cox#define HDMIB_NULL_PACKET (1 << 9) 82689c78134cc54dff016c83367912eb055637fa50cAlan Cox#define HDMIB_HDCP_PORT (1 << 5) 82789c78134cc54dff016c83367912eb055637fa50cAlan Cox 82889c78134cc54dff016c83367912eb055637fa50cAlan Cox/* #define LVDS 0x61180 */ 82989c78134cc54dff016c83367912eb055637fa50cAlan Cox#define MRST_PANEL_8TO6_DITHER_ENABLE (1 << 25) 83089c78134cc54dff016c83367912eb055637fa50cAlan Cox#define MRST_PANEL_24_DOT_1_FORMAT (1 << 24) 83189c78134cc54dff016c83367912eb055637fa50cAlan Cox#define LVDS_A3_POWER_UP_0_OUTPUT (1 << 6) 83289c78134cc54dff016c83367912eb055637fa50cAlan Cox 83389c78134cc54dff016c83367912eb055637fa50cAlan Cox#define MIPI 0x61190 83489c78134cc54dff016c83367912eb055637fa50cAlan Cox#define MIPI_C 0x62190 83589c78134cc54dff016c83367912eb055637fa50cAlan Cox#define MIPI_PORT_EN (1 << 31) 83689c78134cc54dff016c83367912eb055637fa50cAlan Cox/* Turns on border drawing to allow centered display. */ 83789c78134cc54dff016c83367912eb055637fa50cAlan Cox#define SEL_FLOPPED_HSTX (1 << 23) 83889c78134cc54dff016c83367912eb055637fa50cAlan Cox#define PASS_FROM_SPHY_TO_AFE (1 << 16) 83989c78134cc54dff016c83367912eb055637fa50cAlan Cox#define MIPI_BORDER_EN (1 << 15) 84089c78134cc54dff016c83367912eb055637fa50cAlan Cox#define MIPIA_3LANE_MIPIC_1LANE 0x1 84189c78134cc54dff016c83367912eb055637fa50cAlan Cox#define MIPIA_2LANE_MIPIC_2LANE 0x2 84289c78134cc54dff016c83367912eb055637fa50cAlan Cox#define TE_TRIGGER_DSI_PROTOCOL (1 << 2) 84389c78134cc54dff016c83367912eb055637fa50cAlan Cox#define TE_TRIGGER_GPIO_PIN (1 << 3) 84489c78134cc54dff016c83367912eb055637fa50cAlan Cox#define MIPI_TE_COUNT 0x61194 84589c78134cc54dff016c83367912eb055637fa50cAlan Cox 84689c78134cc54dff016c83367912eb055637fa50cAlan Cox/* #define PP_CONTROL 0x61204 */ 84789c78134cc54dff016c83367912eb055637fa50cAlan Cox#define POWER_DOWN_ON_RESET (1 << 1) 84889c78134cc54dff016c83367912eb055637fa50cAlan Cox 84989c78134cc54dff016c83367912eb055637fa50cAlan Cox/* #define PFIT_CONTROL 0x61230 */ 85089c78134cc54dff016c83367912eb055637fa50cAlan Cox#define PFIT_PIPE_SELECT (3 << 29) 85189c78134cc54dff016c83367912eb055637fa50cAlan Cox#define PFIT_PIPE_SELECT_SHIFT (29) 85289c78134cc54dff016c83367912eb055637fa50cAlan Cox 85389c78134cc54dff016c83367912eb055637fa50cAlan Cox/* #define BLC_PWM_CTL 0x61254 */ 85489c78134cc54dff016c83367912eb055637fa50cAlan Cox#define MRST_BACKLIGHT_MODULATION_FREQ_SHIFT (16) 85589c78134cc54dff016c83367912eb055637fa50cAlan Cox#define MRST_BACKLIGHT_MODULATION_FREQ_MASK (0xffff << 16) 85689c78134cc54dff016c83367912eb055637fa50cAlan Cox 85789c78134cc54dff016c83367912eb055637fa50cAlan Cox/* #define PIPEACONF 0x70008 */ 85889c78134cc54dff016c83367912eb055637fa50cAlan Cox#define PIPEACONF_PIPE_STATE (1 << 30) 85989c78134cc54dff016c83367912eb055637fa50cAlan Cox/* #define DSPACNTR 0x70180 */ 86089c78134cc54dff016c83367912eb055637fa50cAlan Cox 86189c78134cc54dff016c83367912eb055637fa50cAlan Cox#define MRST_DSPABASE 0x7019c 86289c78134cc54dff016c83367912eb055637fa50cAlan Cox#define MRST_DSPBBASE 0x7119c 86389c78134cc54dff016c83367912eb055637fa50cAlan Cox#define MDFLD_DSPCBASE 0x7219c 86489c78134cc54dff016c83367912eb055637fa50cAlan Cox 86589c78134cc54dff016c83367912eb055637fa50cAlan Cox/* 86689c78134cc54dff016c83367912eb055637fa50cAlan Cox * Moorestown registers. 86789c78134cc54dff016c83367912eb055637fa50cAlan Cox */ 86889c78134cc54dff016c83367912eb055637fa50cAlan Cox 86989c78134cc54dff016c83367912eb055637fa50cAlan Cox/* 87089c78134cc54dff016c83367912eb055637fa50cAlan Cox * MIPI IP registers 87189c78134cc54dff016c83367912eb055637fa50cAlan Cox */ 87289c78134cc54dff016c83367912eb055637fa50cAlan Cox#define MIPIC_REG_OFFSET 0x800 87389c78134cc54dff016c83367912eb055637fa50cAlan Cox 87489c78134cc54dff016c83367912eb055637fa50cAlan Cox#define DEVICE_READY_REG 0xb000 87589c78134cc54dff016c83367912eb055637fa50cAlan Cox#define LP_OUTPUT_HOLD (1 << 16) 87689c78134cc54dff016c83367912eb055637fa50cAlan Cox#define EXIT_ULPS_DEV_READY 0x3 87789c78134cc54dff016c83367912eb055637fa50cAlan Cox#define LP_OUTPUT_HOLD_RELEASE 0x810000 87889c78134cc54dff016c83367912eb055637fa50cAlan Cox# define ENTERING_ULPS (2 << 1) 87989c78134cc54dff016c83367912eb055637fa50cAlan Cox# define EXITING_ULPS (1 << 1) 88089c78134cc54dff016c83367912eb055637fa50cAlan Cox# define ULPS_MASK (3 << 1) 88189c78134cc54dff016c83367912eb055637fa50cAlan Cox# define BUS_POSSESSION (1 << 3) 88289c78134cc54dff016c83367912eb055637fa50cAlan Cox#define INTR_STAT_REG 0xb004 88389c78134cc54dff016c83367912eb055637fa50cAlan Cox#define RX_SOT_ERROR (1 << 0) 88489c78134cc54dff016c83367912eb055637fa50cAlan Cox#define RX_SOT_SYNC_ERROR (1 << 1) 88589c78134cc54dff016c83367912eb055637fa50cAlan Cox#define RX_ESCAPE_MODE_ENTRY_ERROR (1 << 3) 88689c78134cc54dff016c83367912eb055637fa50cAlan Cox#define RX_LP_TX_SYNC_ERROR (1 << 4) 88789c78134cc54dff016c83367912eb055637fa50cAlan Cox#define RX_HS_RECEIVE_TIMEOUT_ERROR (1 << 5) 88889c78134cc54dff016c83367912eb055637fa50cAlan Cox#define RX_FALSE_CONTROL_ERROR (1 << 6) 88989c78134cc54dff016c83367912eb055637fa50cAlan Cox#define RX_ECC_SINGLE_BIT_ERROR (1 << 7) 89089c78134cc54dff016c83367912eb055637fa50cAlan Cox#define RX_ECC_MULTI_BIT_ERROR (1 << 8) 89189c78134cc54dff016c83367912eb055637fa50cAlan Cox#define RX_CHECKSUM_ERROR (1 << 9) 89289c78134cc54dff016c83367912eb055637fa50cAlan Cox#define RX_DSI_DATA_TYPE_NOT_RECOGNIZED (1 << 10) 89389c78134cc54dff016c83367912eb055637fa50cAlan Cox#define RX_DSI_VC_ID_INVALID (1 << 11) 89489c78134cc54dff016c83367912eb055637fa50cAlan Cox#define TX_FALSE_CONTROL_ERROR (1 << 12) 89589c78134cc54dff016c83367912eb055637fa50cAlan Cox#define TX_ECC_SINGLE_BIT_ERROR (1 << 13) 89689c78134cc54dff016c83367912eb055637fa50cAlan Cox#define TX_ECC_MULTI_BIT_ERROR (1 << 14) 89789c78134cc54dff016c83367912eb055637fa50cAlan Cox#define TX_CHECKSUM_ERROR (1 << 15) 89889c78134cc54dff016c83367912eb055637fa50cAlan Cox#define TX_DSI_DATA_TYPE_NOT_RECOGNIZED (1 << 16) 89989c78134cc54dff016c83367912eb055637fa50cAlan Cox#define TX_DSI_VC_ID_INVALID (1 << 17) 90089c78134cc54dff016c83367912eb055637fa50cAlan Cox#define HIGH_CONTENTION (1 << 18) 90189c78134cc54dff016c83367912eb055637fa50cAlan Cox#define LOW_CONTENTION (1 << 19) 90289c78134cc54dff016c83367912eb055637fa50cAlan Cox#define DPI_FIFO_UNDER_RUN (1 << 20) 90389c78134cc54dff016c83367912eb055637fa50cAlan Cox#define HS_TX_TIMEOUT (1 << 21) 90489c78134cc54dff016c83367912eb055637fa50cAlan Cox#define LP_RX_TIMEOUT (1 << 22) 90589c78134cc54dff016c83367912eb055637fa50cAlan Cox#define TURN_AROUND_ACK_TIMEOUT (1 << 23) 90689c78134cc54dff016c83367912eb055637fa50cAlan Cox#define ACK_WITH_NO_ERROR (1 << 24) 90789c78134cc54dff016c83367912eb055637fa50cAlan Cox#define HS_GENERIC_WR_FIFO_FULL (1 << 27) 90889c78134cc54dff016c83367912eb055637fa50cAlan Cox#define LP_GENERIC_WR_FIFO_FULL (1 << 28) 90989c78134cc54dff016c83367912eb055637fa50cAlan Cox#define SPL_PKT_SENT (1 << 30) 91089c78134cc54dff016c83367912eb055637fa50cAlan Cox#define INTR_EN_REG 0xb008 91189c78134cc54dff016c83367912eb055637fa50cAlan Cox#define DSI_FUNC_PRG_REG 0xb00c 91289c78134cc54dff016c83367912eb055637fa50cAlan Cox#define DPI_CHANNEL_NUMBER_POS 0x03 91389c78134cc54dff016c83367912eb055637fa50cAlan Cox#define DBI_CHANNEL_NUMBER_POS 0x05 91489c78134cc54dff016c83367912eb055637fa50cAlan Cox#define FMT_DPI_POS 0x07 91589c78134cc54dff016c83367912eb055637fa50cAlan Cox#define FMT_DBI_POS 0x0A 91689c78134cc54dff016c83367912eb055637fa50cAlan Cox#define DBI_DATA_WIDTH_POS 0x0D 91789c78134cc54dff016c83367912eb055637fa50cAlan Cox 91889c78134cc54dff016c83367912eb055637fa50cAlan Cox/* DPI PIXEL FORMATS */ 91989c78134cc54dff016c83367912eb055637fa50cAlan Cox#define RGB_565_FMT 0x01 /* RGB 565 FORMAT */ 92089c78134cc54dff016c83367912eb055637fa50cAlan Cox#define RGB_666_FMT 0x02 /* RGB 666 FORMAT */ 92189c78134cc54dff016c83367912eb055637fa50cAlan Cox#define LRGB_666_FMT 0x03 /* RGB LOOSELY PACKED 92289c78134cc54dff016c83367912eb055637fa50cAlan Cox * 666 FORMAT 92389c78134cc54dff016c83367912eb055637fa50cAlan Cox */ 92489c78134cc54dff016c83367912eb055637fa50cAlan Cox#define RGB_888_FMT 0x04 /* RGB 888 FORMAT */ 92589c78134cc54dff016c83367912eb055637fa50cAlan Cox#define VIRTUAL_CHANNEL_NUMBER_0 0x00 /* Virtual channel 0 */ 92689c78134cc54dff016c83367912eb055637fa50cAlan Cox#define VIRTUAL_CHANNEL_NUMBER_1 0x01 /* Virtual channel 1 */ 92789c78134cc54dff016c83367912eb055637fa50cAlan Cox#define VIRTUAL_CHANNEL_NUMBER_2 0x02 /* Virtual channel 2 */ 92889c78134cc54dff016c83367912eb055637fa50cAlan Cox#define VIRTUAL_CHANNEL_NUMBER_3 0x03 /* Virtual channel 3 */ 92989c78134cc54dff016c83367912eb055637fa50cAlan Cox 93089c78134cc54dff016c83367912eb055637fa50cAlan Cox#define DBI_NOT_SUPPORTED 0x00 /* command mode 93189c78134cc54dff016c83367912eb055637fa50cAlan Cox * is not supported 93289c78134cc54dff016c83367912eb055637fa50cAlan Cox */ 93389c78134cc54dff016c83367912eb055637fa50cAlan Cox#define DBI_DATA_WIDTH_16BIT 0x01 /* 16 bit data */ 93489c78134cc54dff016c83367912eb055637fa50cAlan Cox#define DBI_DATA_WIDTH_9BIT 0x02 /* 9 bit data */ 93589c78134cc54dff016c83367912eb055637fa50cAlan Cox#define DBI_DATA_WIDTH_8BIT 0x03 /* 8 bit data */ 93689c78134cc54dff016c83367912eb055637fa50cAlan Cox#define DBI_DATA_WIDTH_OPT1 0x04 /* option 1 */ 93789c78134cc54dff016c83367912eb055637fa50cAlan Cox#define DBI_DATA_WIDTH_OPT2 0x05 /* option 2 */ 93889c78134cc54dff016c83367912eb055637fa50cAlan Cox 93989c78134cc54dff016c83367912eb055637fa50cAlan Cox#define HS_TX_TIMEOUT_REG 0xb010 94089c78134cc54dff016c83367912eb055637fa50cAlan Cox#define LP_RX_TIMEOUT_REG 0xb014 94189c78134cc54dff016c83367912eb055637fa50cAlan Cox#define TURN_AROUND_TIMEOUT_REG 0xb018 94289c78134cc54dff016c83367912eb055637fa50cAlan Cox#define DEVICE_RESET_REG 0xb01C 94389c78134cc54dff016c83367912eb055637fa50cAlan Cox#define DPI_RESOLUTION_REG 0xb020 94489c78134cc54dff016c83367912eb055637fa50cAlan Cox#define RES_V_POS 0x10 94589c78134cc54dff016c83367912eb055637fa50cAlan Cox#define DBI_RESOLUTION_REG 0xb024 /* Reserved for MDFLD */ 94689c78134cc54dff016c83367912eb055637fa50cAlan Cox#define HORIZ_SYNC_PAD_COUNT_REG 0xb028 94789c78134cc54dff016c83367912eb055637fa50cAlan Cox#define HORIZ_BACK_PORCH_COUNT_REG 0xb02C 94889c78134cc54dff016c83367912eb055637fa50cAlan Cox#define HORIZ_FRONT_PORCH_COUNT_REG 0xb030 94989c78134cc54dff016c83367912eb055637fa50cAlan Cox#define HORIZ_ACTIVE_AREA_COUNT_REG 0xb034 95089c78134cc54dff016c83367912eb055637fa50cAlan Cox#define VERT_SYNC_PAD_COUNT_REG 0xb038 95189c78134cc54dff016c83367912eb055637fa50cAlan Cox#define VERT_BACK_PORCH_COUNT_REG 0xb03c 95289c78134cc54dff016c83367912eb055637fa50cAlan Cox#define VERT_FRONT_PORCH_COUNT_REG 0xb040 95389c78134cc54dff016c83367912eb055637fa50cAlan Cox#define HIGH_LOW_SWITCH_COUNT_REG 0xb044 95489c78134cc54dff016c83367912eb055637fa50cAlan Cox#define DPI_CONTROL_REG 0xb048 95589c78134cc54dff016c83367912eb055637fa50cAlan Cox#define DPI_SHUT_DOWN (1 << 0) 95689c78134cc54dff016c83367912eb055637fa50cAlan Cox#define DPI_TURN_ON (1 << 1) 95789c78134cc54dff016c83367912eb055637fa50cAlan Cox#define DPI_COLOR_MODE_ON (1 << 2) 95889c78134cc54dff016c83367912eb055637fa50cAlan Cox#define DPI_COLOR_MODE_OFF (1 << 3) 95989c78134cc54dff016c83367912eb055637fa50cAlan Cox#define DPI_BACK_LIGHT_ON (1 << 4) 96089c78134cc54dff016c83367912eb055637fa50cAlan Cox#define DPI_BACK_LIGHT_OFF (1 << 5) 96189c78134cc54dff016c83367912eb055637fa50cAlan Cox#define DPI_LP (1 << 6) 96289c78134cc54dff016c83367912eb055637fa50cAlan Cox#define DPI_DATA_REG 0xb04c 96389c78134cc54dff016c83367912eb055637fa50cAlan Cox#define DPI_BACK_LIGHT_ON_DATA 0x07 96489c78134cc54dff016c83367912eb055637fa50cAlan Cox#define DPI_BACK_LIGHT_OFF_DATA 0x17 96589c78134cc54dff016c83367912eb055637fa50cAlan Cox#define INIT_COUNT_REG 0xb050 96689c78134cc54dff016c83367912eb055637fa50cAlan Cox#define MAX_RET_PAK_REG 0xb054 96789c78134cc54dff016c83367912eb055637fa50cAlan Cox#define VIDEO_FMT_REG 0xb058 96889c78134cc54dff016c83367912eb055637fa50cAlan Cox#define COMPLETE_LAST_PCKT (1 << 2) 96989c78134cc54dff016c83367912eb055637fa50cAlan Cox#define EOT_DISABLE_REG 0xb05c 97089c78134cc54dff016c83367912eb055637fa50cAlan Cox#define ENABLE_CLOCK_STOPPING (1 << 1) 97189c78134cc54dff016c83367912eb055637fa50cAlan Cox#define LP_BYTECLK_REG 0xb060 97289c78134cc54dff016c83367912eb055637fa50cAlan Cox#define LP_GEN_DATA_REG 0xb064 97389c78134cc54dff016c83367912eb055637fa50cAlan Cox#define HS_GEN_DATA_REG 0xb068 97489c78134cc54dff016c83367912eb055637fa50cAlan Cox#define LP_GEN_CTRL_REG 0xb06C 97589c78134cc54dff016c83367912eb055637fa50cAlan Cox#define HS_GEN_CTRL_REG 0xb070 97689c78134cc54dff016c83367912eb055637fa50cAlan Cox#define DCS_CHANNEL_NUMBER_POS 0x6 97789c78134cc54dff016c83367912eb055637fa50cAlan Cox#define MCS_COMMANDS_POS 0x8 97889c78134cc54dff016c83367912eb055637fa50cAlan Cox#define WORD_COUNTS_POS 0x8 97989c78134cc54dff016c83367912eb055637fa50cAlan Cox#define MCS_PARAMETER_POS 0x10 98089c78134cc54dff016c83367912eb055637fa50cAlan Cox#define GEN_FIFO_STAT_REG 0xb074 98189c78134cc54dff016c83367912eb055637fa50cAlan Cox#define HS_DATA_FIFO_FULL (1 << 0) 98289c78134cc54dff016c83367912eb055637fa50cAlan Cox#define HS_DATA_FIFO_HALF_EMPTY (1 << 1) 98389c78134cc54dff016c83367912eb055637fa50cAlan Cox#define HS_DATA_FIFO_EMPTY (1 << 2) 98489c78134cc54dff016c83367912eb055637fa50cAlan Cox#define LP_DATA_FIFO_FULL (1 << 8) 98589c78134cc54dff016c83367912eb055637fa50cAlan Cox#define LP_DATA_FIFO_HALF_EMPTY (1 << 9) 98689c78134cc54dff016c83367912eb055637fa50cAlan Cox#define LP_DATA_FIFO_EMPTY (1 << 10) 98789c78134cc54dff016c83367912eb055637fa50cAlan Cox#define HS_CTRL_FIFO_FULL (1 << 16) 98889c78134cc54dff016c83367912eb055637fa50cAlan Cox#define HS_CTRL_FIFO_HALF_EMPTY (1 << 17) 98989c78134cc54dff016c83367912eb055637fa50cAlan Cox#define HS_CTRL_FIFO_EMPTY (1 << 18) 99089c78134cc54dff016c83367912eb055637fa50cAlan Cox#define LP_CTRL_FIFO_FULL (1 << 24) 99189c78134cc54dff016c83367912eb055637fa50cAlan Cox#define LP_CTRL_FIFO_HALF_EMPTY (1 << 25) 99289c78134cc54dff016c83367912eb055637fa50cAlan Cox#define LP_CTRL_FIFO_EMPTY (1 << 26) 99389c78134cc54dff016c83367912eb055637fa50cAlan Cox#define DBI_FIFO_EMPTY (1 << 27) 99489c78134cc54dff016c83367912eb055637fa50cAlan Cox#define DPI_FIFO_EMPTY (1 << 28) 99589c78134cc54dff016c83367912eb055637fa50cAlan Cox#define HS_LS_DBI_ENABLE_REG 0xb078 99689c78134cc54dff016c83367912eb055637fa50cAlan Cox#define TXCLKESC_REG 0xb07c 99789c78134cc54dff016c83367912eb055637fa50cAlan Cox#define DPHY_PARAM_REG 0xb080 99889c78134cc54dff016c83367912eb055637fa50cAlan Cox#define DBI_BW_CTRL_REG 0xb084 99989c78134cc54dff016c83367912eb055637fa50cAlan Cox#define CLK_LANE_SWT_REG 0xb088 100089c78134cc54dff016c83367912eb055637fa50cAlan Cox 100189c78134cc54dff016c83367912eb055637fa50cAlan Cox/* 100289c78134cc54dff016c83367912eb055637fa50cAlan Cox * MIPI Adapter registers 100389c78134cc54dff016c83367912eb055637fa50cAlan Cox */ 100489c78134cc54dff016c83367912eb055637fa50cAlan Cox#define MIPI_CONTROL_REG 0xb104 100589c78134cc54dff016c83367912eb055637fa50cAlan Cox#define MIPI_2X_CLOCK_BITS ((1 << 0) | (1 << 1)) 100689c78134cc54dff016c83367912eb055637fa50cAlan Cox#define MIPI_DATA_ADDRESS_REG 0xb108 100789c78134cc54dff016c83367912eb055637fa50cAlan Cox#define MIPI_DATA_LENGTH_REG 0xb10C 100889c78134cc54dff016c83367912eb055637fa50cAlan Cox#define MIPI_COMMAND_ADDRESS_REG 0xb110 100989c78134cc54dff016c83367912eb055637fa50cAlan Cox#define MIPI_COMMAND_LENGTH_REG 0xb114 101089c78134cc54dff016c83367912eb055637fa50cAlan Cox#define MIPI_READ_DATA_RETURN_REG0 0xb118 101189c78134cc54dff016c83367912eb055637fa50cAlan Cox#define MIPI_READ_DATA_RETURN_REG1 0xb11C 101289c78134cc54dff016c83367912eb055637fa50cAlan Cox#define MIPI_READ_DATA_RETURN_REG2 0xb120 101389c78134cc54dff016c83367912eb055637fa50cAlan Cox#define MIPI_READ_DATA_RETURN_REG3 0xb124 101489c78134cc54dff016c83367912eb055637fa50cAlan Cox#define MIPI_READ_DATA_RETURN_REG4 0xb128 101589c78134cc54dff016c83367912eb055637fa50cAlan Cox#define MIPI_READ_DATA_RETURN_REG5 0xb12C 101689c78134cc54dff016c83367912eb055637fa50cAlan Cox#define MIPI_READ_DATA_RETURN_REG6 0xb130 101789c78134cc54dff016c83367912eb055637fa50cAlan Cox#define MIPI_READ_DATA_RETURN_REG7 0xb134 101889c78134cc54dff016c83367912eb055637fa50cAlan Cox#define MIPI_READ_DATA_VALID_REG 0xb138 101989c78134cc54dff016c83367912eb055637fa50cAlan Cox 102089c78134cc54dff016c83367912eb055637fa50cAlan Cox/* DBI COMMANDS */ 102189c78134cc54dff016c83367912eb055637fa50cAlan Cox#define soft_reset 0x01 102289c78134cc54dff016c83367912eb055637fa50cAlan Cox/* 102389c78134cc54dff016c83367912eb055637fa50cAlan Cox * The display module performs a software reset. 102489c78134cc54dff016c83367912eb055637fa50cAlan Cox * Registers are written with their SW Reset default values. 102589c78134cc54dff016c83367912eb055637fa50cAlan Cox */ 102689c78134cc54dff016c83367912eb055637fa50cAlan Cox#define get_power_mode 0x0a 102789c78134cc54dff016c83367912eb055637fa50cAlan Cox/* 102889c78134cc54dff016c83367912eb055637fa50cAlan Cox * The display module returns the current power mode 102989c78134cc54dff016c83367912eb055637fa50cAlan Cox */ 103089c78134cc54dff016c83367912eb055637fa50cAlan Cox#define get_address_mode 0x0b 103189c78134cc54dff016c83367912eb055637fa50cAlan Cox/* 103289c78134cc54dff016c83367912eb055637fa50cAlan Cox * The display module returns the current status. 103389c78134cc54dff016c83367912eb055637fa50cAlan Cox */ 103489c78134cc54dff016c83367912eb055637fa50cAlan Cox#define get_pixel_format 0x0c 103589c78134cc54dff016c83367912eb055637fa50cAlan Cox/* 103689c78134cc54dff016c83367912eb055637fa50cAlan Cox * This command gets the pixel format for the RGB image data 103789c78134cc54dff016c83367912eb055637fa50cAlan Cox * used by the interface. 103889c78134cc54dff016c83367912eb055637fa50cAlan Cox */ 103989c78134cc54dff016c83367912eb055637fa50cAlan Cox#define get_display_mode 0x0d 104089c78134cc54dff016c83367912eb055637fa50cAlan Cox/* 104189c78134cc54dff016c83367912eb055637fa50cAlan Cox * The display module returns the Display Image Mode status. 104289c78134cc54dff016c83367912eb055637fa50cAlan Cox */ 104389c78134cc54dff016c83367912eb055637fa50cAlan Cox#define get_signal_mode 0x0e 104489c78134cc54dff016c83367912eb055637fa50cAlan Cox/* 104589c78134cc54dff016c83367912eb055637fa50cAlan Cox * The display module returns the Display Signal Mode. 104689c78134cc54dff016c83367912eb055637fa50cAlan Cox */ 104789c78134cc54dff016c83367912eb055637fa50cAlan Cox#define get_diagnostic_result 0x0f 104889c78134cc54dff016c83367912eb055637fa50cAlan Cox/* 104989c78134cc54dff016c83367912eb055637fa50cAlan Cox * The display module returns the self-diagnostic results following 105089c78134cc54dff016c83367912eb055637fa50cAlan Cox * a Sleep Out command. 105189c78134cc54dff016c83367912eb055637fa50cAlan Cox */ 105289c78134cc54dff016c83367912eb055637fa50cAlan Cox#define enter_sleep_mode 0x10 105389c78134cc54dff016c83367912eb055637fa50cAlan Cox/* 105489c78134cc54dff016c83367912eb055637fa50cAlan Cox * This command causes the display module to enter the Sleep mode. 105589c78134cc54dff016c83367912eb055637fa50cAlan Cox * In this mode, all unnecessary blocks inside the display module are 105689c78134cc54dff016c83367912eb055637fa50cAlan Cox * disabled except interface communication. This is the lowest power 105789c78134cc54dff016c83367912eb055637fa50cAlan Cox * mode the display module supports. 105889c78134cc54dff016c83367912eb055637fa50cAlan Cox */ 105989c78134cc54dff016c83367912eb055637fa50cAlan Cox#define exit_sleep_mode 0x11 106089c78134cc54dff016c83367912eb055637fa50cAlan Cox/* 106189c78134cc54dff016c83367912eb055637fa50cAlan Cox * This command causes the display module to exit Sleep mode. 106289c78134cc54dff016c83367912eb055637fa50cAlan Cox * All blocks inside the display module are enabled. 106389c78134cc54dff016c83367912eb055637fa50cAlan Cox */ 106489c78134cc54dff016c83367912eb055637fa50cAlan Cox#define enter_partial_mode 0x12 106589c78134cc54dff016c83367912eb055637fa50cAlan Cox/* 106689c78134cc54dff016c83367912eb055637fa50cAlan Cox * This command causes the display module to enter the Partial Display 106789c78134cc54dff016c83367912eb055637fa50cAlan Cox * Mode. The Partial Display Mode window is described by the 106889c78134cc54dff016c83367912eb055637fa50cAlan Cox * set_partial_area command. 106989c78134cc54dff016c83367912eb055637fa50cAlan Cox */ 107089c78134cc54dff016c83367912eb055637fa50cAlan Cox#define enter_normal_mode 0x13 107189c78134cc54dff016c83367912eb055637fa50cAlan Cox/* 107289c78134cc54dff016c83367912eb055637fa50cAlan Cox * This command causes the display module to enter the Normal mode. 107389c78134cc54dff016c83367912eb055637fa50cAlan Cox * Normal Mode is defined as Partial Display mode and Scroll mode are off 107489c78134cc54dff016c83367912eb055637fa50cAlan Cox */ 107589c78134cc54dff016c83367912eb055637fa50cAlan Cox#define exit_invert_mode 0x20 107689c78134cc54dff016c83367912eb055637fa50cAlan Cox/* 107789c78134cc54dff016c83367912eb055637fa50cAlan Cox * This command causes the display module to stop inverting the image 107889c78134cc54dff016c83367912eb055637fa50cAlan Cox * data on the display device. The frame memory contents remain unchanged. 107989c78134cc54dff016c83367912eb055637fa50cAlan Cox * No status bits are changed. 108089c78134cc54dff016c83367912eb055637fa50cAlan Cox */ 108189c78134cc54dff016c83367912eb055637fa50cAlan Cox#define enter_invert_mode 0x21 108289c78134cc54dff016c83367912eb055637fa50cAlan Cox/* 108389c78134cc54dff016c83367912eb055637fa50cAlan Cox * This command causes the display module to invert the image data only on 108489c78134cc54dff016c83367912eb055637fa50cAlan Cox * the display device. The frame memory contents remain unchanged. 108589c78134cc54dff016c83367912eb055637fa50cAlan Cox * No status bits are changed. 108689c78134cc54dff016c83367912eb055637fa50cAlan Cox */ 108789c78134cc54dff016c83367912eb055637fa50cAlan Cox#define set_gamma_curve 0x26 108889c78134cc54dff016c83367912eb055637fa50cAlan Cox/* 108989c78134cc54dff016c83367912eb055637fa50cAlan Cox * This command selects the desired gamma curve for the display device. 109089c78134cc54dff016c83367912eb055637fa50cAlan Cox * Four fixed gamma curves are defined in section DCS spec. 109189c78134cc54dff016c83367912eb055637fa50cAlan Cox */ 109289c78134cc54dff016c83367912eb055637fa50cAlan Cox#define set_display_off 0x28 109389c78134cc54dff016c83367912eb055637fa50cAlan Cox/* ************************************************************************* *\ 109489c78134cc54dff016c83367912eb055637fa50cAlan CoxThis command causes the display module to stop displaying the image data 109589c78134cc54dff016c83367912eb055637fa50cAlan Coxon the display device. The frame memory contents remain unchanged. 109689c78134cc54dff016c83367912eb055637fa50cAlan CoxNo status bits are changed. 109789c78134cc54dff016c83367912eb055637fa50cAlan Cox\* ************************************************************************* */ 109889c78134cc54dff016c83367912eb055637fa50cAlan Cox#define set_display_on 0x29 109989c78134cc54dff016c83367912eb055637fa50cAlan Cox/* ************************************************************************* *\ 110089c78134cc54dff016c83367912eb055637fa50cAlan CoxThis command causes the display module to start displaying the image data 110189c78134cc54dff016c83367912eb055637fa50cAlan Coxon the display device. The frame memory contents remain unchanged. 110289c78134cc54dff016c83367912eb055637fa50cAlan CoxNo status bits are changed. 110389c78134cc54dff016c83367912eb055637fa50cAlan Cox\* ************************************************************************* */ 110489c78134cc54dff016c83367912eb055637fa50cAlan Cox#define set_column_address 0x2a 110589c78134cc54dff016c83367912eb055637fa50cAlan Cox/* 110689c78134cc54dff016c83367912eb055637fa50cAlan Cox * This command defines the column extent of the frame memory accessed by 110789c78134cc54dff016c83367912eb055637fa50cAlan Cox * the hostprocessor with the read_memory_continue and 110889c78134cc54dff016c83367912eb055637fa50cAlan Cox * write_memory_continue commands. 110989c78134cc54dff016c83367912eb055637fa50cAlan Cox * No status bits are changed. 111089c78134cc54dff016c83367912eb055637fa50cAlan Cox */ 111189c78134cc54dff016c83367912eb055637fa50cAlan Cox#define set_page_addr 0x2b 111289c78134cc54dff016c83367912eb055637fa50cAlan Cox/* 111389c78134cc54dff016c83367912eb055637fa50cAlan Cox * This command defines the page extent of the frame memory accessed by 111489c78134cc54dff016c83367912eb055637fa50cAlan Cox * the host processor with the write_memory_continue and 111589c78134cc54dff016c83367912eb055637fa50cAlan Cox * read_memory_continue command. 111689c78134cc54dff016c83367912eb055637fa50cAlan Cox * No status bits are changed. 111789c78134cc54dff016c83367912eb055637fa50cAlan Cox */ 111889c78134cc54dff016c83367912eb055637fa50cAlan Cox#define write_mem_start 0x2c 111989c78134cc54dff016c83367912eb055637fa50cAlan Cox/* 112089c78134cc54dff016c83367912eb055637fa50cAlan Cox * This command transfers image data from the host processor to the 112189c78134cc54dff016c83367912eb055637fa50cAlan Cox * display modules frame memory starting at the pixel location specified 112289c78134cc54dff016c83367912eb055637fa50cAlan Cox * by preceding set_column_address and set_page_address commands. 112389c78134cc54dff016c83367912eb055637fa50cAlan Cox */ 112489c78134cc54dff016c83367912eb055637fa50cAlan Cox#define set_partial_area 0x30 112589c78134cc54dff016c83367912eb055637fa50cAlan Cox/* 112689c78134cc54dff016c83367912eb055637fa50cAlan Cox * This command defines the Partial Display mode s display area. 112789c78134cc54dff016c83367912eb055637fa50cAlan Cox * There are two parameters associated with this command, the first 112889c78134cc54dff016c83367912eb055637fa50cAlan Cox * defines the Start Row (SR) and the second the End Row (ER). SR and ER 112989c78134cc54dff016c83367912eb055637fa50cAlan Cox * refer to the Frame Memory Line Pointer. 113089c78134cc54dff016c83367912eb055637fa50cAlan Cox */ 113189c78134cc54dff016c83367912eb055637fa50cAlan Cox#define set_scroll_area 0x33 113289c78134cc54dff016c83367912eb055637fa50cAlan Cox/* 113389c78134cc54dff016c83367912eb055637fa50cAlan Cox * This command defines the display modules Vertical Scrolling Area. 113489c78134cc54dff016c83367912eb055637fa50cAlan Cox */ 113589c78134cc54dff016c83367912eb055637fa50cAlan Cox#define set_tear_off 0x34 113689c78134cc54dff016c83367912eb055637fa50cAlan Cox/* 113789c78134cc54dff016c83367912eb055637fa50cAlan Cox * This command turns off the display modules Tearing Effect output 113889c78134cc54dff016c83367912eb055637fa50cAlan Cox * signal on the TE signal line. 113989c78134cc54dff016c83367912eb055637fa50cAlan Cox */ 114089c78134cc54dff016c83367912eb055637fa50cAlan Cox#define set_tear_on 0x35 114189c78134cc54dff016c83367912eb055637fa50cAlan Cox/* 114289c78134cc54dff016c83367912eb055637fa50cAlan Cox * This command turns on the display modules Tearing Effect output signal 114389c78134cc54dff016c83367912eb055637fa50cAlan Cox * on the TE signal line. 114489c78134cc54dff016c83367912eb055637fa50cAlan Cox */ 114589c78134cc54dff016c83367912eb055637fa50cAlan Cox#define set_address_mode 0x36 114689c78134cc54dff016c83367912eb055637fa50cAlan Cox/* 114789c78134cc54dff016c83367912eb055637fa50cAlan Cox * This command sets the data order for transfers from the host processor 114889c78134cc54dff016c83367912eb055637fa50cAlan Cox * to display modules frame memory,bits B[7:5] and B3, and from the 114989c78134cc54dff016c83367912eb055637fa50cAlan Cox * display modules frame memory to the display device, bits B[2:0] and B4. 115089c78134cc54dff016c83367912eb055637fa50cAlan Cox */ 115189c78134cc54dff016c83367912eb055637fa50cAlan Cox#define set_scroll_start 0x37 115289c78134cc54dff016c83367912eb055637fa50cAlan Cox/* 115389c78134cc54dff016c83367912eb055637fa50cAlan Cox * This command sets the start of the vertical scrolling area in the frame 115489c78134cc54dff016c83367912eb055637fa50cAlan Cox * memory. The vertical scrolling area is fully defined when this command 115589c78134cc54dff016c83367912eb055637fa50cAlan Cox * is used with the set_scroll_area command The set_scroll_start command 115689c78134cc54dff016c83367912eb055637fa50cAlan Cox * has one parameter, the Vertical Scroll Pointer. The VSP defines the 115789c78134cc54dff016c83367912eb055637fa50cAlan Cox * line in the frame memory that is written to the display device as the 115889c78134cc54dff016c83367912eb055637fa50cAlan Cox * first line of the vertical scroll area. 115989c78134cc54dff016c83367912eb055637fa50cAlan Cox */ 116089c78134cc54dff016c83367912eb055637fa50cAlan Cox#define exit_idle_mode 0x38 116189c78134cc54dff016c83367912eb055637fa50cAlan Cox/* 116289c78134cc54dff016c83367912eb055637fa50cAlan Cox * This command causes the display module to exit Idle mode. 116389c78134cc54dff016c83367912eb055637fa50cAlan Cox */ 116489c78134cc54dff016c83367912eb055637fa50cAlan Cox#define enter_idle_mode 0x39 116589c78134cc54dff016c83367912eb055637fa50cAlan Cox/* 116689c78134cc54dff016c83367912eb055637fa50cAlan Cox * This command causes the display module to enter Idle Mode. 116789c78134cc54dff016c83367912eb055637fa50cAlan Cox * In Idle Mode, color expression is reduced. Colors are shown on the 116889c78134cc54dff016c83367912eb055637fa50cAlan Cox * display device using the MSB of each of the R, G and B color 116989c78134cc54dff016c83367912eb055637fa50cAlan Cox * components in the frame memory 117089c78134cc54dff016c83367912eb055637fa50cAlan Cox */ 117189c78134cc54dff016c83367912eb055637fa50cAlan Cox#define set_pixel_format 0x3a 117289c78134cc54dff016c83367912eb055637fa50cAlan Cox/* 117389c78134cc54dff016c83367912eb055637fa50cAlan Cox * This command sets the pixel format for the RGB image data used by the 117489c78134cc54dff016c83367912eb055637fa50cAlan Cox * interface. 117589c78134cc54dff016c83367912eb055637fa50cAlan Cox * Bits D[6:4] DPI Pixel Format Definition 117689c78134cc54dff016c83367912eb055637fa50cAlan Cox * Bits D[2:0] DBI Pixel Format Definition 117789c78134cc54dff016c83367912eb055637fa50cAlan Cox * Bits D7 and D3 are not used. 117889c78134cc54dff016c83367912eb055637fa50cAlan Cox */ 117989c78134cc54dff016c83367912eb055637fa50cAlan Cox#define DCS_PIXEL_FORMAT_3bpp 0x1 118089c78134cc54dff016c83367912eb055637fa50cAlan Cox#define DCS_PIXEL_FORMAT_8bpp 0x2 118189c78134cc54dff016c83367912eb055637fa50cAlan Cox#define DCS_PIXEL_FORMAT_12bpp 0x3 118289c78134cc54dff016c83367912eb055637fa50cAlan Cox#define DCS_PIXEL_FORMAT_16bpp 0x5 118389c78134cc54dff016c83367912eb055637fa50cAlan Cox#define DCS_PIXEL_FORMAT_18bpp 0x6 118489c78134cc54dff016c83367912eb055637fa50cAlan Cox#define DCS_PIXEL_FORMAT_24bpp 0x7 118589c78134cc54dff016c83367912eb055637fa50cAlan Cox 118689c78134cc54dff016c83367912eb055637fa50cAlan Cox#define write_mem_cont 0x3c 118789c78134cc54dff016c83367912eb055637fa50cAlan Cox 118889c78134cc54dff016c83367912eb055637fa50cAlan Cox/* 118989c78134cc54dff016c83367912eb055637fa50cAlan Cox * This command transfers image data from the host processor to the 119089c78134cc54dff016c83367912eb055637fa50cAlan Cox * display module's frame memory continuing from the pixel location 119189c78134cc54dff016c83367912eb055637fa50cAlan Cox * following the previous write_memory_continue or write_memory_start 119289c78134cc54dff016c83367912eb055637fa50cAlan Cox * command. 119389c78134cc54dff016c83367912eb055637fa50cAlan Cox */ 119489c78134cc54dff016c83367912eb055637fa50cAlan Cox#define set_tear_scanline 0x44 119589c78134cc54dff016c83367912eb055637fa50cAlan Cox/* 119689c78134cc54dff016c83367912eb055637fa50cAlan Cox * This command turns on the display modules Tearing Effect output signal 119789c78134cc54dff016c83367912eb055637fa50cAlan Cox * on the TE signal line when the display module reaches line N. 119889c78134cc54dff016c83367912eb055637fa50cAlan Cox */ 119989c78134cc54dff016c83367912eb055637fa50cAlan Cox#define get_scanline 0x45 120089c78134cc54dff016c83367912eb055637fa50cAlan Cox/* 120189c78134cc54dff016c83367912eb055637fa50cAlan Cox * The display module returns the current scanline, N, used to update the 120289c78134cc54dff016c83367912eb055637fa50cAlan Cox * display device. The total number of scanlines on a display device is 120389c78134cc54dff016c83367912eb055637fa50cAlan Cox * defined as VSYNC + VBP + VACT + VFP.The first scanline is defined as 120489c78134cc54dff016c83367912eb055637fa50cAlan Cox * the first line of V Sync and is denoted as Line 0. 120589c78134cc54dff016c83367912eb055637fa50cAlan Cox * When in Sleep Mode, the value returned by get_scanline is undefined. 120689c78134cc54dff016c83367912eb055637fa50cAlan Cox */ 120789c78134cc54dff016c83367912eb055637fa50cAlan Cox 120889c78134cc54dff016c83367912eb055637fa50cAlan Cox/* MCS or Generic COMMANDS */ 120989c78134cc54dff016c83367912eb055637fa50cAlan Cox/* MCS/generic data type */ 121089c78134cc54dff016c83367912eb055637fa50cAlan Cox#define GEN_SHORT_WRITE_0 0x03 /* generic short write, no parameters */ 121189c78134cc54dff016c83367912eb055637fa50cAlan Cox#define GEN_SHORT_WRITE_1 0x13 /* generic short write, 1 parameters */ 121289c78134cc54dff016c83367912eb055637fa50cAlan Cox#define GEN_SHORT_WRITE_2 0x23 /* generic short write, 2 parameters */ 121389c78134cc54dff016c83367912eb055637fa50cAlan Cox#define GEN_READ_0 0x04 /* generic read, no parameters */ 121489c78134cc54dff016c83367912eb055637fa50cAlan Cox#define GEN_READ_1 0x14 /* generic read, 1 parameters */ 121589c78134cc54dff016c83367912eb055637fa50cAlan Cox#define GEN_READ_2 0x24 /* generic read, 2 parameters */ 121689c78134cc54dff016c83367912eb055637fa50cAlan Cox#define GEN_LONG_WRITE 0x29 /* generic long write */ 121789c78134cc54dff016c83367912eb055637fa50cAlan Cox#define MCS_SHORT_WRITE_0 0x05 /* MCS short write, no parameters */ 121889c78134cc54dff016c83367912eb055637fa50cAlan Cox#define MCS_SHORT_WRITE_1 0x15 /* MCS short write, 1 parameters */ 121989c78134cc54dff016c83367912eb055637fa50cAlan Cox#define MCS_READ 0x06 /* MCS read, no parameters */ 122089c78134cc54dff016c83367912eb055637fa50cAlan Cox#define MCS_LONG_WRITE 0x39 /* MCS long write */ 122189c78134cc54dff016c83367912eb055637fa50cAlan Cox/* MCS/generic commands */ 122289c78134cc54dff016c83367912eb055637fa50cAlan Cox/* TPO MCS */ 122389c78134cc54dff016c83367912eb055637fa50cAlan Cox#define write_display_profile 0x50 122489c78134cc54dff016c83367912eb055637fa50cAlan Cox#define write_display_brightness 0x51 122589c78134cc54dff016c83367912eb055637fa50cAlan Cox#define write_ctrl_display 0x53 122689c78134cc54dff016c83367912eb055637fa50cAlan Cox#define write_ctrl_cabc 0x55 122789c78134cc54dff016c83367912eb055637fa50cAlan Cox #define UI_IMAGE 0x01 122889c78134cc54dff016c83367912eb055637fa50cAlan Cox #define STILL_IMAGE 0x02 122989c78134cc54dff016c83367912eb055637fa50cAlan Cox #define MOVING_IMAGE 0x03 123089c78134cc54dff016c83367912eb055637fa50cAlan Cox#define write_hysteresis 0x57 123189c78134cc54dff016c83367912eb055637fa50cAlan Cox#define write_gamma_setting 0x58 123289c78134cc54dff016c83367912eb055637fa50cAlan Cox#define write_cabc_min_bright 0x5e 123389c78134cc54dff016c83367912eb055637fa50cAlan Cox#define write_kbbc_profile 0x60 123489c78134cc54dff016c83367912eb055637fa50cAlan Cox/* TMD MCS */ 123589c78134cc54dff016c83367912eb055637fa50cAlan Cox#define tmd_write_display_brightness 0x8c 123689c78134cc54dff016c83367912eb055637fa50cAlan Cox 123789c78134cc54dff016c83367912eb055637fa50cAlan Cox/* 123889c78134cc54dff016c83367912eb055637fa50cAlan Cox * This command is used to control ambient light, panel backlight 123989c78134cc54dff016c83367912eb055637fa50cAlan Cox * brightness and gamma settings. 124089c78134cc54dff016c83367912eb055637fa50cAlan Cox */ 124189c78134cc54dff016c83367912eb055637fa50cAlan Cox#define BRIGHT_CNTL_BLOCK_ON (1 << 5) 124289c78134cc54dff016c83367912eb055637fa50cAlan Cox#define AMBIENT_LIGHT_SENSE_ON (1 << 4) 124389c78134cc54dff016c83367912eb055637fa50cAlan Cox#define DISPLAY_DIMMING_ON (1 << 3) 124489c78134cc54dff016c83367912eb055637fa50cAlan Cox#define BACKLIGHT_ON (1 << 2) 124589c78134cc54dff016c83367912eb055637fa50cAlan Cox#define DISPLAY_BRIGHTNESS_AUTO (1 << 1) 124689c78134cc54dff016c83367912eb055637fa50cAlan Cox#define GAMMA_AUTO (1 << 0) 124789c78134cc54dff016c83367912eb055637fa50cAlan Cox 124889c78134cc54dff016c83367912eb055637fa50cAlan Cox/* DCS Interface Pixel Formats */ 124989c78134cc54dff016c83367912eb055637fa50cAlan Cox#define DCS_PIXEL_FORMAT_3BPP 0x1 125089c78134cc54dff016c83367912eb055637fa50cAlan Cox#define DCS_PIXEL_FORMAT_8BPP 0x2 125189c78134cc54dff016c83367912eb055637fa50cAlan Cox#define DCS_PIXEL_FORMAT_12BPP 0x3 125289c78134cc54dff016c83367912eb055637fa50cAlan Cox#define DCS_PIXEL_FORMAT_16BPP 0x5 125389c78134cc54dff016c83367912eb055637fa50cAlan Cox#define DCS_PIXEL_FORMAT_18BPP 0x6 125489c78134cc54dff016c83367912eb055637fa50cAlan Cox#define DCS_PIXEL_FORMAT_24BPP 0x7 125589c78134cc54dff016c83367912eb055637fa50cAlan Cox/* ONE PARAMETER READ DATA */ 125689c78134cc54dff016c83367912eb055637fa50cAlan Cox#define addr_mode_data 0xfc 125789c78134cc54dff016c83367912eb055637fa50cAlan Cox#define diag_res_data 0x00 125889c78134cc54dff016c83367912eb055637fa50cAlan Cox#define disp_mode_data 0x23 125989c78134cc54dff016c83367912eb055637fa50cAlan Cox#define pxl_fmt_data 0x77 126089c78134cc54dff016c83367912eb055637fa50cAlan Cox#define pwr_mode_data 0x74 126189c78134cc54dff016c83367912eb055637fa50cAlan Cox#define sig_mode_data 0x00 126289c78134cc54dff016c83367912eb055637fa50cAlan Cox/* TWO PARAMETERS READ DATA */ 126389c78134cc54dff016c83367912eb055637fa50cAlan Cox#define scanline_data1 0xff 126489c78134cc54dff016c83367912eb055637fa50cAlan Cox#define scanline_data2 0xff 126589c78134cc54dff016c83367912eb055637fa50cAlan Cox#define NON_BURST_MODE_SYNC_PULSE 0x01 /* Non Burst Mode 126689c78134cc54dff016c83367912eb055637fa50cAlan Cox * with Sync Pulse 126789c78134cc54dff016c83367912eb055637fa50cAlan Cox */ 126889c78134cc54dff016c83367912eb055637fa50cAlan Cox#define NON_BURST_MODE_SYNC_EVENTS 0x02 /* Non Burst Mode 126989c78134cc54dff016c83367912eb055637fa50cAlan Cox * with Sync events 127089c78134cc54dff016c83367912eb055637fa50cAlan Cox */ 127189c78134cc54dff016c83367912eb055637fa50cAlan Cox#define BURST_MODE 0x03 /* Burst Mode */ 127289c78134cc54dff016c83367912eb055637fa50cAlan Cox#define DBI_COMMAND_BUFFER_SIZE 0x240 /* 0x32 */ /* 0x120 */ 127389c78134cc54dff016c83367912eb055637fa50cAlan Cox /* Allocate at least 127489c78134cc54dff016c83367912eb055637fa50cAlan Cox * 0x100 Byte with 32 127589c78134cc54dff016c83367912eb055637fa50cAlan Cox * byte alignment 127689c78134cc54dff016c83367912eb055637fa50cAlan Cox */ 127789c78134cc54dff016c83367912eb055637fa50cAlan Cox#define DBI_DATA_BUFFER_SIZE 0x120 /* Allocate at least 127889c78134cc54dff016c83367912eb055637fa50cAlan Cox * 0x100 Byte with 32 127989c78134cc54dff016c83367912eb055637fa50cAlan Cox * byte alignment 128089c78134cc54dff016c83367912eb055637fa50cAlan Cox */ 128189c78134cc54dff016c83367912eb055637fa50cAlan Cox#define DBI_CB_TIME_OUT 0xFFFF 128289c78134cc54dff016c83367912eb055637fa50cAlan Cox 128389c78134cc54dff016c83367912eb055637fa50cAlan Cox#define GEN_FB_TIME_OUT 2000 128489c78134cc54dff016c83367912eb055637fa50cAlan Cox 128589c78134cc54dff016c83367912eb055637fa50cAlan Cox#define SKU_83 0x01 128689c78134cc54dff016c83367912eb055637fa50cAlan Cox#define SKU_100 0x02 128789c78134cc54dff016c83367912eb055637fa50cAlan Cox#define SKU_100L 0x04 128889c78134cc54dff016c83367912eb055637fa50cAlan Cox#define SKU_BYPASS 0x08 128989c78134cc54dff016c83367912eb055637fa50cAlan Cox 129089c78134cc54dff016c83367912eb055637fa50cAlan Cox/* Some handy macros for playing with bitfields. */ 129189c78134cc54dff016c83367912eb055637fa50cAlan Cox#define PSB_MASK(high, low) (((1<<((high)-(low)+1))-1)<<(low)) 129289c78134cc54dff016c83367912eb055637fa50cAlan Cox#define SET_FIELD(value, field) (((value) << field ## _SHIFT) & field ## _MASK) 129389c78134cc54dff016c83367912eb055637fa50cAlan Cox#define GET_FIELD(word, field) (((word) & field ## _MASK) >> field ## _SHIFT) 129489c78134cc54dff016c83367912eb055637fa50cAlan Cox 129589c78134cc54dff016c83367912eb055637fa50cAlan Cox#define _PIPE(pipe, a, b) ((a) + (pipe)*((b)-(a))) 129689c78134cc54dff016c83367912eb055637fa50cAlan Cox 129789c78134cc54dff016c83367912eb055637fa50cAlan Cox/* PCI config space */ 129889c78134cc54dff016c83367912eb055637fa50cAlan Cox 129989c78134cc54dff016c83367912eb055637fa50cAlan Cox#define SB_PCKT 0x02100 /* cedarview */ 130089c78134cc54dff016c83367912eb055637fa50cAlan Cox# define SB_OPCODE_MASK PSB_MASK(31, 16) 130189c78134cc54dff016c83367912eb055637fa50cAlan Cox# define SB_OPCODE_SHIFT 16 130289c78134cc54dff016c83367912eb055637fa50cAlan Cox# define SB_OPCODE_READ 0 130389c78134cc54dff016c83367912eb055637fa50cAlan Cox# define SB_OPCODE_WRITE 1 130489c78134cc54dff016c83367912eb055637fa50cAlan Cox# define SB_DEST_MASK PSB_MASK(15, 8) 130589c78134cc54dff016c83367912eb055637fa50cAlan Cox# define SB_DEST_SHIFT 8 130689c78134cc54dff016c83367912eb055637fa50cAlan Cox# define SB_DEST_DPLL 0x88 130789c78134cc54dff016c83367912eb055637fa50cAlan Cox# define SB_BYTE_ENABLE_MASK PSB_MASK(7, 4) 130889c78134cc54dff016c83367912eb055637fa50cAlan Cox# define SB_BYTE_ENABLE_SHIFT 4 130989c78134cc54dff016c83367912eb055637fa50cAlan Cox# define SB_BUSY (1 << 0) 131089c78134cc54dff016c83367912eb055637fa50cAlan Cox 131109016a11fc738e82ca1303e2332473b517bbd660Alan Cox#define DSPCLK_GATE_D 0x6200 131209016a11fc738e82ca1303e2332473b517bbd660Alan Cox# define VRHUNIT_CLOCK_GATE_DISABLE (1 << 28) /* Fixed value on CDV */ 131309016a11fc738e82ca1303e2332473b517bbd660Alan Cox# define DPOUNIT_CLOCK_GATE_DISABLE (1 << 11) 131409016a11fc738e82ca1303e2332473b517bbd660Alan Cox# define DPIOUNIT_CLOCK_GATE_DISABLE (1 << 6) 13159a9f5786fcccda3cc61eaa8f537690327eff6853Zhao Yakui# define DPUNIT_PIPEB_GATE_DISABLE (1 << 30) 13169a9f5786fcccda3cc61eaa8f537690327eff6853Zhao Yakui# define DPUNIT_PIPEA_GATE_DISABLE (1 << 25) 13179a9f5786fcccda3cc61eaa8f537690327eff6853Zhao Yakui# define DPCUNIT_CLOCK_GATE_DISABLE (1 << 24) 13189a9f5786fcccda3cc61eaa8f537690327eff6853Zhao Yakui# define DPLSUNIT_CLOCK_GATE_DISABLE (1 << 13) 131909016a11fc738e82ca1303e2332473b517bbd660Alan Cox 132009016a11fc738e82ca1303e2332473b517bbd660Alan Cox#define RAMCLK_GATE_D 0x6210 132189c78134cc54dff016c83367912eb055637fa50cAlan Cox 132289c78134cc54dff016c83367912eb055637fa50cAlan Cox/* 32-bit value read/written from the DPIO reg. */ 132389c78134cc54dff016c83367912eb055637fa50cAlan Cox#define SB_DATA 0x02104 /* cedarview */ 132489c78134cc54dff016c83367912eb055637fa50cAlan Cox/* 32-bit address of the DPIO reg to be read/written. */ 132589c78134cc54dff016c83367912eb055637fa50cAlan Cox#define SB_ADDR 0x02108 /* cedarview */ 132689c78134cc54dff016c83367912eb055637fa50cAlan Cox#define DPIO_CFG 0x02110 /* cedarview */ 132789c78134cc54dff016c83367912eb055637fa50cAlan Cox# define DPIO_MODE_SELECT_1 (1 << 3) 132889c78134cc54dff016c83367912eb055637fa50cAlan Cox# define DPIO_MODE_SELECT_0 (1 << 2) 132989c78134cc54dff016c83367912eb055637fa50cAlan Cox# define DPIO_SFR_BYPASS (1 << 1) 133089c78134cc54dff016c83367912eb055637fa50cAlan Cox/* reset is active low */ 133189c78134cc54dff016c83367912eb055637fa50cAlan Cox# define DPIO_CMN_RESET_N (1 << 0) 133289c78134cc54dff016c83367912eb055637fa50cAlan Cox 133389c78134cc54dff016c83367912eb055637fa50cAlan Cox/* Cedarview sideband registers */ 133489c78134cc54dff016c83367912eb055637fa50cAlan Cox#define _SB_M_A 0x8008 133589c78134cc54dff016c83367912eb055637fa50cAlan Cox#define _SB_M_B 0x8028 133689c78134cc54dff016c83367912eb055637fa50cAlan Cox#define SB_M(pipe) _PIPE(pipe, _SB_M_A, _SB_M_B) 133789c78134cc54dff016c83367912eb055637fa50cAlan Cox# define SB_M_DIVIDER_MASK (0xFF << 24) 133889c78134cc54dff016c83367912eb055637fa50cAlan Cox# define SB_M_DIVIDER_SHIFT 24 133989c78134cc54dff016c83367912eb055637fa50cAlan Cox 134089c78134cc54dff016c83367912eb055637fa50cAlan Cox#define _SB_N_VCO_A 0x8014 134189c78134cc54dff016c83367912eb055637fa50cAlan Cox#define _SB_N_VCO_B 0x8034 134289c78134cc54dff016c83367912eb055637fa50cAlan Cox#define SB_N_VCO(pipe) _PIPE(pipe, _SB_N_VCO_A, _SB_N_VCO_B) 134389c78134cc54dff016c83367912eb055637fa50cAlan Cox#define SB_N_VCO_SEL_MASK PSB_MASK(31, 30) 134489c78134cc54dff016c83367912eb055637fa50cAlan Cox#define SB_N_VCO_SEL_SHIFT 30 134589c78134cc54dff016c83367912eb055637fa50cAlan Cox#define SB_N_DIVIDER_MASK PSB_MASK(29, 26) 134689c78134cc54dff016c83367912eb055637fa50cAlan Cox#define SB_N_DIVIDER_SHIFT 26 134789c78134cc54dff016c83367912eb055637fa50cAlan Cox#define SB_N_CB_TUNE_MASK PSB_MASK(25, 24) 134889c78134cc54dff016c83367912eb055637fa50cAlan Cox#define SB_N_CB_TUNE_SHIFT 24 134989c78134cc54dff016c83367912eb055637fa50cAlan Cox 1350acd7ef927e06510fbfeec8d307f4726a156b2733Alan Cox/* the bit 14:13 is used to select between the different reference clock for Pipe A/B */ 1351acd7ef927e06510fbfeec8d307f4726a156b2733Alan Cox#define SB_REF_DPLLA 0x8010 1352acd7ef927e06510fbfeec8d307f4726a156b2733Alan Cox#define SB_REF_DPLLB 0x8030 1353acd7ef927e06510fbfeec8d307f4726a156b2733Alan Cox#define REF_CLK_MASK (0x3 << 13) 1354acd7ef927e06510fbfeec8d307f4726a156b2733Alan Cox#define REF_CLK_CORE (0 << 13) 1355acd7ef927e06510fbfeec8d307f4726a156b2733Alan Cox#define REF_CLK_DPLL (1 << 13) 1356acd7ef927e06510fbfeec8d307f4726a156b2733Alan Cox#define REF_CLK_DPLLA (2 << 13) 1357acd7ef927e06510fbfeec8d307f4726a156b2733Alan Cox/* For the DPLL B, it will use the reference clk from DPLL A when using (2 << 13) */ 1358acd7ef927e06510fbfeec8d307f4726a156b2733Alan Cox 135989c78134cc54dff016c83367912eb055637fa50cAlan Cox#define _SB_REF_A 0x8018 136089c78134cc54dff016c83367912eb055637fa50cAlan Cox#define _SB_REF_B 0x8038 136189c78134cc54dff016c83367912eb055637fa50cAlan Cox#define SB_REF_SFR(pipe) _PIPE(pipe, _SB_REF_A, _SB_REF_B) 136289c78134cc54dff016c83367912eb055637fa50cAlan Cox 136389c78134cc54dff016c83367912eb055637fa50cAlan Cox#define _SB_P_A 0x801c 136489c78134cc54dff016c83367912eb055637fa50cAlan Cox#define _SB_P_B 0x803c 136589c78134cc54dff016c83367912eb055637fa50cAlan Cox#define SB_P(pipe) _PIPE(pipe, _SB_P_A, _SB_P_B) 136689c78134cc54dff016c83367912eb055637fa50cAlan Cox#define SB_P2_DIVIDER_MASK PSB_MASK(31, 30) 136789c78134cc54dff016c83367912eb055637fa50cAlan Cox#define SB_P2_DIVIDER_SHIFT 30 136889c78134cc54dff016c83367912eb055637fa50cAlan Cox#define SB_P2_10 0 /* HDMI, DP, DAC */ 136989c78134cc54dff016c83367912eb055637fa50cAlan Cox#define SB_P2_5 1 /* DAC */ 137089c78134cc54dff016c83367912eb055637fa50cAlan Cox#define SB_P2_14 2 /* LVDS single */ 137189c78134cc54dff016c83367912eb055637fa50cAlan Cox#define SB_P2_7 3 /* LVDS double */ 137289c78134cc54dff016c83367912eb055637fa50cAlan Cox#define SB_P1_DIVIDER_MASK PSB_MASK(15, 12) 137389c78134cc54dff016c83367912eb055637fa50cAlan Cox#define SB_P1_DIVIDER_SHIFT 12 137489c78134cc54dff016c83367912eb055637fa50cAlan Cox 137589c78134cc54dff016c83367912eb055637fa50cAlan Cox#define PSB_LANE0 0x120 137689c78134cc54dff016c83367912eb055637fa50cAlan Cox#define PSB_LANE1 0x220 137789c78134cc54dff016c83367912eb055637fa50cAlan Cox#define PSB_LANE2 0x2320 137889c78134cc54dff016c83367912eb055637fa50cAlan Cox#define PSB_LANE3 0x2420 137989c78134cc54dff016c83367912eb055637fa50cAlan Cox 138089c78134cc54dff016c83367912eb055637fa50cAlan Cox#define LANE_PLL_MASK (0x7 << 20) 138189c78134cc54dff016c83367912eb055637fa50cAlan Cox#define LANE_PLL_ENABLE (0x3 << 20) 1382d235e64a4367ad3ff204309490c4325b4f89b25bAlan Cox#define LANE_PLL_PIPE(p) (((p) == 0) ? (1 << 21) : (0 << 21)) 138389c78134cc54dff016c83367912eb055637fa50cAlan Cox 13848695b612943561478fd22f28f45e5692e5d078dbAlan Cox#define DP_B 0x64100 13858695b612943561478fd22f28f45e5692e5d078dbAlan Cox#define DP_C 0x64200 13868695b612943561478fd22f28f45e5692e5d078dbAlan Cox 13878695b612943561478fd22f28f45e5692e5d078dbAlan Cox#define DP_PORT_EN (1 << 31) 13888695b612943561478fd22f28f45e5692e5d078dbAlan Cox#define DP_PIPEB_SELECT (1 << 30) 13898695b612943561478fd22f28f45e5692e5d078dbAlan Cox#define DP_PIPE_MASK (1 << 30) 13908695b612943561478fd22f28f45e5692e5d078dbAlan Cox 13918695b612943561478fd22f28f45e5692e5d078dbAlan Cox/* Link training mode - select a suitable mode for each stage */ 13928695b612943561478fd22f28f45e5692e5d078dbAlan Cox#define DP_LINK_TRAIN_PAT_1 (0 << 28) 13938695b612943561478fd22f28f45e5692e5d078dbAlan Cox#define DP_LINK_TRAIN_PAT_2 (1 << 28) 13948695b612943561478fd22f28f45e5692e5d078dbAlan Cox#define DP_LINK_TRAIN_PAT_IDLE (2 << 28) 13958695b612943561478fd22f28f45e5692e5d078dbAlan Cox#define DP_LINK_TRAIN_OFF (3 << 28) 13968695b612943561478fd22f28f45e5692e5d078dbAlan Cox#define DP_LINK_TRAIN_MASK (3 << 28) 13978695b612943561478fd22f28f45e5692e5d078dbAlan Cox#define DP_LINK_TRAIN_SHIFT 28 13988695b612943561478fd22f28f45e5692e5d078dbAlan Cox 13998695b612943561478fd22f28f45e5692e5d078dbAlan Cox/* Signal voltages. These are mostly controlled by the other end */ 14008695b612943561478fd22f28f45e5692e5d078dbAlan Cox#define DP_VOLTAGE_0_4 (0 << 25) 14018695b612943561478fd22f28f45e5692e5d078dbAlan Cox#define DP_VOLTAGE_0_6 (1 << 25) 14028695b612943561478fd22f28f45e5692e5d078dbAlan Cox#define DP_VOLTAGE_0_8 (2 << 25) 14038695b612943561478fd22f28f45e5692e5d078dbAlan Cox#define DP_VOLTAGE_1_2 (3 << 25) 14048695b612943561478fd22f28f45e5692e5d078dbAlan Cox#define DP_VOLTAGE_MASK (7 << 25) 14058695b612943561478fd22f28f45e5692e5d078dbAlan Cox#define DP_VOLTAGE_SHIFT 25 14068695b612943561478fd22f28f45e5692e5d078dbAlan Cox 14078695b612943561478fd22f28f45e5692e5d078dbAlan Cox/* Signal pre-emphasis levels, like voltages, the other end tells us what 14088695b612943561478fd22f28f45e5692e5d078dbAlan Cox * they want 14098695b612943561478fd22f28f45e5692e5d078dbAlan Cox */ 14108695b612943561478fd22f28f45e5692e5d078dbAlan Cox#define DP_PRE_EMPHASIS_0 (0 << 22) 14118695b612943561478fd22f28f45e5692e5d078dbAlan Cox#define DP_PRE_EMPHASIS_3_5 (1 << 22) 14128695b612943561478fd22f28f45e5692e5d078dbAlan Cox#define DP_PRE_EMPHASIS_6 (2 << 22) 14138695b612943561478fd22f28f45e5692e5d078dbAlan Cox#define DP_PRE_EMPHASIS_9_5 (3 << 22) 14148695b612943561478fd22f28f45e5692e5d078dbAlan Cox#define DP_PRE_EMPHASIS_MASK (7 << 22) 14158695b612943561478fd22f28f45e5692e5d078dbAlan Cox#define DP_PRE_EMPHASIS_SHIFT 22 14168695b612943561478fd22f28f45e5692e5d078dbAlan Cox 14178695b612943561478fd22f28f45e5692e5d078dbAlan Cox/* How many wires to use. I guess 3 was too hard */ 14188695b612943561478fd22f28f45e5692e5d078dbAlan Cox#define DP_PORT_WIDTH_1 (0 << 19) 14198695b612943561478fd22f28f45e5692e5d078dbAlan Cox#define DP_PORT_WIDTH_2 (1 << 19) 14208695b612943561478fd22f28f45e5692e5d078dbAlan Cox#define DP_PORT_WIDTH_4 (3 << 19) 14218695b612943561478fd22f28f45e5692e5d078dbAlan Cox#define DP_PORT_WIDTH_MASK (7 << 19) 14228695b612943561478fd22f28f45e5692e5d078dbAlan Cox 14238695b612943561478fd22f28f45e5692e5d078dbAlan Cox/* Mystic DPCD version 1.1 special mode */ 14248695b612943561478fd22f28f45e5692e5d078dbAlan Cox#define DP_ENHANCED_FRAMING (1 << 18) 14258695b612943561478fd22f28f45e5692e5d078dbAlan Cox 14268695b612943561478fd22f28f45e5692e5d078dbAlan Cox/** locked once port is enabled */ 14278695b612943561478fd22f28f45e5692e5d078dbAlan Cox#define DP_PORT_REVERSAL (1 << 15) 14288695b612943561478fd22f28f45e5692e5d078dbAlan Cox 14298695b612943561478fd22f28f45e5692e5d078dbAlan Cox/** sends the clock on lane 15 of the PEG for debug */ 14308695b612943561478fd22f28f45e5692e5d078dbAlan Cox#define DP_CLOCK_OUTPUT_ENABLE (1 << 13) 14318695b612943561478fd22f28f45e5692e5d078dbAlan Cox 14328695b612943561478fd22f28f45e5692e5d078dbAlan Cox#define DP_SCRAMBLING_DISABLE (1 << 12) 14338695b612943561478fd22f28f45e5692e5d078dbAlan Cox#define DP_SCRAMBLING_DISABLE_IRONLAKE (1 << 7) 14348695b612943561478fd22f28f45e5692e5d078dbAlan Cox 14358695b612943561478fd22f28f45e5692e5d078dbAlan Cox/** limit RGB values to avoid confusing TVs */ 14368695b612943561478fd22f28f45e5692e5d078dbAlan Cox#define DP_COLOR_RANGE_16_235 (1 << 8) 14378695b612943561478fd22f28f45e5692e5d078dbAlan Cox 14388695b612943561478fd22f28f45e5692e5d078dbAlan Cox/** Turn on the audio link */ 14398695b612943561478fd22f28f45e5692e5d078dbAlan Cox#define DP_AUDIO_OUTPUT_ENABLE (1 << 6) 14408695b612943561478fd22f28f45e5692e5d078dbAlan Cox 14418695b612943561478fd22f28f45e5692e5d078dbAlan Cox/** vs and hs sync polarity */ 14428695b612943561478fd22f28f45e5692e5d078dbAlan Cox#define DP_SYNC_VS_HIGH (1 << 4) 14438695b612943561478fd22f28f45e5692e5d078dbAlan Cox#define DP_SYNC_HS_HIGH (1 << 3) 14448695b612943561478fd22f28f45e5692e5d078dbAlan Cox 14458695b612943561478fd22f28f45e5692e5d078dbAlan Cox/** A fantasy */ 14468695b612943561478fd22f28f45e5692e5d078dbAlan Cox#define DP_DETECTED (1 << 2) 14478695b612943561478fd22f28f45e5692e5d078dbAlan Cox 14488695b612943561478fd22f28f45e5692e5d078dbAlan Cox/** The aux channel provides a way to talk to the 14498695b612943561478fd22f28f45e5692e5d078dbAlan Cox * signal sink for DDC etc. Max packet size supported 14508695b612943561478fd22f28f45e5692e5d078dbAlan Cox * is 20 bytes in each direction, hence the 5 fixed 14518695b612943561478fd22f28f45e5692e5d078dbAlan Cox * data registers 14528695b612943561478fd22f28f45e5692e5d078dbAlan Cox */ 14538695b612943561478fd22f28f45e5692e5d078dbAlan Cox#define DPB_AUX_CH_CTL 0x64110 14548695b612943561478fd22f28f45e5692e5d078dbAlan Cox#define DPB_AUX_CH_DATA1 0x64114 14558695b612943561478fd22f28f45e5692e5d078dbAlan Cox#define DPB_AUX_CH_DATA2 0x64118 14568695b612943561478fd22f28f45e5692e5d078dbAlan Cox#define DPB_AUX_CH_DATA3 0x6411c 14578695b612943561478fd22f28f45e5692e5d078dbAlan Cox#define DPB_AUX_CH_DATA4 0x64120 14588695b612943561478fd22f28f45e5692e5d078dbAlan Cox#define DPB_AUX_CH_DATA5 0x64124 14598695b612943561478fd22f28f45e5692e5d078dbAlan Cox 14608695b612943561478fd22f28f45e5692e5d078dbAlan Cox#define DPC_AUX_CH_CTL 0x64210 14618695b612943561478fd22f28f45e5692e5d078dbAlan Cox#define DPC_AUX_CH_DATA1 0x64214 14628695b612943561478fd22f28f45e5692e5d078dbAlan Cox#define DPC_AUX_CH_DATA2 0x64218 14638695b612943561478fd22f28f45e5692e5d078dbAlan Cox#define DPC_AUX_CH_DATA3 0x6421c 14648695b612943561478fd22f28f45e5692e5d078dbAlan Cox#define DPC_AUX_CH_DATA4 0x64220 14658695b612943561478fd22f28f45e5692e5d078dbAlan Cox#define DPC_AUX_CH_DATA5 0x64224 14668695b612943561478fd22f28f45e5692e5d078dbAlan Cox 14678695b612943561478fd22f28f45e5692e5d078dbAlan Cox#define DP_AUX_CH_CTL_SEND_BUSY (1 << 31) 14688695b612943561478fd22f28f45e5692e5d078dbAlan Cox#define DP_AUX_CH_CTL_DONE (1 << 30) 14698695b612943561478fd22f28f45e5692e5d078dbAlan Cox#define DP_AUX_CH_CTL_INTERRUPT (1 << 29) 14708695b612943561478fd22f28f45e5692e5d078dbAlan Cox#define DP_AUX_CH_CTL_TIME_OUT_ERROR (1 << 28) 14718695b612943561478fd22f28f45e5692e5d078dbAlan Cox#define DP_AUX_CH_CTL_TIME_OUT_400us (0 << 26) 14728695b612943561478fd22f28f45e5692e5d078dbAlan Cox#define DP_AUX_CH_CTL_TIME_OUT_600us (1 << 26) 14738695b612943561478fd22f28f45e5692e5d078dbAlan Cox#define DP_AUX_CH_CTL_TIME_OUT_800us (2 << 26) 14748695b612943561478fd22f28f45e5692e5d078dbAlan Cox#define DP_AUX_CH_CTL_TIME_OUT_1600us (3 << 26) 14758695b612943561478fd22f28f45e5692e5d078dbAlan Cox#define DP_AUX_CH_CTL_TIME_OUT_MASK (3 << 26) 14768695b612943561478fd22f28f45e5692e5d078dbAlan Cox#define DP_AUX_CH_CTL_RECEIVE_ERROR (1 << 25) 14778695b612943561478fd22f28f45e5692e5d078dbAlan Cox#define DP_AUX_CH_CTL_MESSAGE_SIZE_MASK (0x1f << 20) 14788695b612943561478fd22f28f45e5692e5d078dbAlan Cox#define DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT 20 14798695b612943561478fd22f28f45e5692e5d078dbAlan Cox#define DP_AUX_CH_CTL_PRECHARGE_2US_MASK (0xf << 16) 14808695b612943561478fd22f28f45e5692e5d078dbAlan Cox#define DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT 16 14818695b612943561478fd22f28f45e5692e5d078dbAlan Cox#define DP_AUX_CH_CTL_AUX_AKSV_SELECT (1 << 15) 14828695b612943561478fd22f28f45e5692e5d078dbAlan Cox#define DP_AUX_CH_CTL_MANCHESTER_TEST (1 << 14) 14838695b612943561478fd22f28f45e5692e5d078dbAlan Cox#define DP_AUX_CH_CTL_SYNC_TEST (1 << 13) 14848695b612943561478fd22f28f45e5692e5d078dbAlan Cox#define DP_AUX_CH_CTL_DEGLITCH_TEST (1 << 12) 14858695b612943561478fd22f28f45e5692e5d078dbAlan Cox#define DP_AUX_CH_CTL_PRECHARGE_TEST (1 << 11) 14868695b612943561478fd22f28f45e5692e5d078dbAlan Cox#define DP_AUX_CH_CTL_BIT_CLOCK_2X_MASK (0x7ff) 14878695b612943561478fd22f28f45e5692e5d078dbAlan Cox#define DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT 0 14888695b612943561478fd22f28f45e5692e5d078dbAlan Cox 14898695b612943561478fd22f28f45e5692e5d078dbAlan Cox/* 14908695b612943561478fd22f28f45e5692e5d078dbAlan Cox * Computing GMCH M and N values for the Display Port link 14918695b612943561478fd22f28f45e5692e5d078dbAlan Cox * 14928695b612943561478fd22f28f45e5692e5d078dbAlan Cox * GMCH M/N = dot clock * bytes per pixel / ls_clk * # of lanes 14938695b612943561478fd22f28f45e5692e5d078dbAlan Cox * 14948695b612943561478fd22f28f45e5692e5d078dbAlan Cox * ls_clk (we assume) is the DP link clock (1.62 or 2.7 GHz) 14958695b612943561478fd22f28f45e5692e5d078dbAlan Cox * 14968695b612943561478fd22f28f45e5692e5d078dbAlan Cox * The GMCH value is used internally 14978695b612943561478fd22f28f45e5692e5d078dbAlan Cox * 14988695b612943561478fd22f28f45e5692e5d078dbAlan Cox * bytes_per_pixel is the number of bytes coming out of the plane, 14998695b612943561478fd22f28f45e5692e5d078dbAlan Cox * which is after the LUTs, so we want the bytes for our color format. 15008695b612943561478fd22f28f45e5692e5d078dbAlan Cox * For our current usage, this is always 3, one byte for R, G and B. 15018695b612943561478fd22f28f45e5692e5d078dbAlan Cox */ 15028695b612943561478fd22f28f45e5692e5d078dbAlan Cox 15038695b612943561478fd22f28f45e5692e5d078dbAlan Cox#define _PIPEA_GMCH_DATA_M 0x70050 15048695b612943561478fd22f28f45e5692e5d078dbAlan Cox#define _PIPEB_GMCH_DATA_M 0x71050 15058695b612943561478fd22f28f45e5692e5d078dbAlan Cox 15068695b612943561478fd22f28f45e5692e5d078dbAlan Cox/* Transfer unit size for display port - 1, default is 0x3f (for TU size 64) */ 15078695b612943561478fd22f28f45e5692e5d078dbAlan Cox#define PIPE_GMCH_DATA_M_TU_SIZE_MASK (0x3f << 25) 15088695b612943561478fd22f28f45e5692e5d078dbAlan Cox#define PIPE_GMCH_DATA_M_TU_SIZE_SHIFT 25 15098695b612943561478fd22f28f45e5692e5d078dbAlan Cox 15108695b612943561478fd22f28f45e5692e5d078dbAlan Cox#define PIPE_GMCH_DATA_M_MASK (0xffffff) 15118695b612943561478fd22f28f45e5692e5d078dbAlan Cox 15128695b612943561478fd22f28f45e5692e5d078dbAlan Cox#define _PIPEA_GMCH_DATA_N 0x70054 15138695b612943561478fd22f28f45e5692e5d078dbAlan Cox#define _PIPEB_GMCH_DATA_N 0x71054 15148695b612943561478fd22f28f45e5692e5d078dbAlan Cox#define PIPE_GMCH_DATA_N_MASK (0xffffff) 15158695b612943561478fd22f28f45e5692e5d078dbAlan Cox 15168695b612943561478fd22f28f45e5692e5d078dbAlan Cox/* 15178695b612943561478fd22f28f45e5692e5d078dbAlan Cox * Computing Link M and N values for the Display Port link 15188695b612943561478fd22f28f45e5692e5d078dbAlan Cox * 15198695b612943561478fd22f28f45e5692e5d078dbAlan Cox * Link M / N = pixel_clock / ls_clk 15208695b612943561478fd22f28f45e5692e5d078dbAlan Cox * 15218695b612943561478fd22f28f45e5692e5d078dbAlan Cox * (the DP spec calls pixel_clock the 'strm_clk') 15228695b612943561478fd22f28f45e5692e5d078dbAlan Cox * 15238695b612943561478fd22f28f45e5692e5d078dbAlan Cox * The Link value is transmitted in the Main Stream 15248695b612943561478fd22f28f45e5692e5d078dbAlan Cox * Attributes and VB-ID. 15258695b612943561478fd22f28f45e5692e5d078dbAlan Cox */ 15268695b612943561478fd22f28f45e5692e5d078dbAlan Cox 15278695b612943561478fd22f28f45e5692e5d078dbAlan Cox#define _PIPEA_DP_LINK_M 0x70060 15288695b612943561478fd22f28f45e5692e5d078dbAlan Cox#define _PIPEB_DP_LINK_M 0x71060 15298695b612943561478fd22f28f45e5692e5d078dbAlan Cox#define PIPEA_DP_LINK_M_MASK (0xffffff) 15308695b612943561478fd22f28f45e5692e5d078dbAlan Cox 15318695b612943561478fd22f28f45e5692e5d078dbAlan Cox#define _PIPEA_DP_LINK_N 0x70064 15328695b612943561478fd22f28f45e5692e5d078dbAlan Cox#define _PIPEB_DP_LINK_N 0x71064 15338695b612943561478fd22f28f45e5692e5d078dbAlan Cox#define PIPEA_DP_LINK_N_MASK (0xffffff) 15348695b612943561478fd22f28f45e5692e5d078dbAlan Cox 15358695b612943561478fd22f28f45e5692e5d078dbAlan Cox#define PIPE_GMCH_DATA_M(pipe) _PIPE(pipe, _PIPEA_GMCH_DATA_M, _PIPEB_GMCH_DATA_M) 15368695b612943561478fd22f28f45e5692e5d078dbAlan Cox#define PIPE_GMCH_DATA_N(pipe) _PIPE(pipe, _PIPEA_GMCH_DATA_N, _PIPEB_GMCH_DATA_N) 15378695b612943561478fd22f28f45e5692e5d078dbAlan Cox#define PIPE_DP_LINK_M(pipe) _PIPE(pipe, _PIPEA_DP_LINK_M, _PIPEB_DP_LINK_M) 15388695b612943561478fd22f28f45e5692e5d078dbAlan Cox#define PIPE_DP_LINK_N(pipe) _PIPE(pipe, _PIPEA_DP_LINK_N, _PIPEB_DP_LINK_N) 153989c78134cc54dff016c83367912eb055637fa50cAlan Cox 1540d112a8163f83752361dd639a9a579ae5cc05c6cfZhao Yakui#define PIPE_BPC_MASK (7 << 5) 1541d112a8163f83752361dd639a9a579ae5cc05c6cfZhao Yakui#define PIPE_8BPC (0 << 5) 1542d112a8163f83752361dd639a9a579ae5cc05c6cfZhao Yakui#define PIPE_10BPC (1 << 5) 1543d112a8163f83752361dd639a9a579ae5cc05c6cfZhao Yakui#define PIPE_6BPC (2 << 5) 1544d112a8163f83752361dd639a9a579ae5cc05c6cfZhao Yakui 154589c78134cc54dff016c83367912eb055637fa50cAlan Cox#endif 1546