psb_intel_reg.h revision 89c78134cc54dff016c83367912eb055637fa50c
189c78134cc54dff016c83367912eb055637fa50cAlan Cox/* 289c78134cc54dff016c83367912eb055637fa50cAlan Cox * Copyright (c) 2009, Intel Corporation. 389c78134cc54dff016c83367912eb055637fa50cAlan Cox * 489c78134cc54dff016c83367912eb055637fa50cAlan Cox * This program is free software; you can redistribute it and/or modify it 589c78134cc54dff016c83367912eb055637fa50cAlan Cox * under the terms and conditions of the GNU General Public License, 689c78134cc54dff016c83367912eb055637fa50cAlan Cox * version 2, as published by the Free Software Foundation. 789c78134cc54dff016c83367912eb055637fa50cAlan Cox * 889c78134cc54dff016c83367912eb055637fa50cAlan Cox * This program is distributed in the hope it will be useful, but WITHOUT 989c78134cc54dff016c83367912eb055637fa50cAlan Cox * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 1089c78134cc54dff016c83367912eb055637fa50cAlan Cox * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 1189c78134cc54dff016c83367912eb055637fa50cAlan Cox * more details. 1289c78134cc54dff016c83367912eb055637fa50cAlan Cox * 1389c78134cc54dff016c83367912eb055637fa50cAlan Cox * You should have received a copy of the GNU General Public License along with 1489c78134cc54dff016c83367912eb055637fa50cAlan Cox * this program; if not, write to the Free Software Foundation, Inc., 1589c78134cc54dff016c83367912eb055637fa50cAlan Cox * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. 1689c78134cc54dff016c83367912eb055637fa50cAlan Cox */ 1789c78134cc54dff016c83367912eb055637fa50cAlan Cox#ifndef __PSB_INTEL_REG_H__ 1889c78134cc54dff016c83367912eb055637fa50cAlan Cox#define __PSB_INTEL_REG_H__ 1989c78134cc54dff016c83367912eb055637fa50cAlan Cox 2089c78134cc54dff016c83367912eb055637fa50cAlan Cox#define BLC_PWM_CTL 0x61254 2189c78134cc54dff016c83367912eb055637fa50cAlan Cox#define BLC_PWM_CTL2 0x61250 2289c78134cc54dff016c83367912eb055637fa50cAlan Cox#define BLC_PWM_CTL_C 0x62254 2389c78134cc54dff016c83367912eb055637fa50cAlan Cox#define BLC_PWM_CTL2_C 0x62250 2489c78134cc54dff016c83367912eb055637fa50cAlan Cox#define BACKLIGHT_MODULATION_FREQ_SHIFT (17) 2589c78134cc54dff016c83367912eb055637fa50cAlan Cox/* 2689c78134cc54dff016c83367912eb055637fa50cAlan Cox * This is the most significant 15 bits of the number of backlight cycles in a 2789c78134cc54dff016c83367912eb055637fa50cAlan Cox * complete cycle of the modulated backlight control. 2889c78134cc54dff016c83367912eb055637fa50cAlan Cox * 2989c78134cc54dff016c83367912eb055637fa50cAlan Cox * The actual value is this field multiplied by two. 3089c78134cc54dff016c83367912eb055637fa50cAlan Cox */ 3189c78134cc54dff016c83367912eb055637fa50cAlan Cox#define BACKLIGHT_MODULATION_FREQ_MASK (0x7fff << 17) 3289c78134cc54dff016c83367912eb055637fa50cAlan Cox#define BLM_LEGACY_MODE (1 << 16) 3389c78134cc54dff016c83367912eb055637fa50cAlan Cox/* 3489c78134cc54dff016c83367912eb055637fa50cAlan Cox * This is the number of cycles out of the backlight modulation cycle for which 3589c78134cc54dff016c83367912eb055637fa50cAlan Cox * the backlight is on. 3689c78134cc54dff016c83367912eb055637fa50cAlan Cox * 3789c78134cc54dff016c83367912eb055637fa50cAlan Cox * This field must be no greater than the number of cycles in the complete 3889c78134cc54dff016c83367912eb055637fa50cAlan Cox * backlight modulation cycle. 3989c78134cc54dff016c83367912eb055637fa50cAlan Cox */ 4089c78134cc54dff016c83367912eb055637fa50cAlan Cox#define BACKLIGHT_DUTY_CYCLE_SHIFT (0) 4189c78134cc54dff016c83367912eb055637fa50cAlan Cox#define BACKLIGHT_DUTY_CYCLE_MASK (0xffff) 4289c78134cc54dff016c83367912eb055637fa50cAlan Cox 4389c78134cc54dff016c83367912eb055637fa50cAlan Cox#define I915_GCFGC 0xf0 4489c78134cc54dff016c83367912eb055637fa50cAlan Cox#define I915_LOW_FREQUENCY_ENABLE (1 << 7) 4589c78134cc54dff016c83367912eb055637fa50cAlan Cox#define I915_DISPLAY_CLOCK_190_200_MHZ (0 << 4) 4689c78134cc54dff016c83367912eb055637fa50cAlan Cox#define I915_DISPLAY_CLOCK_333_MHZ (4 << 4) 4789c78134cc54dff016c83367912eb055637fa50cAlan Cox#define I915_DISPLAY_CLOCK_MASK (7 << 4) 4889c78134cc54dff016c83367912eb055637fa50cAlan Cox 4989c78134cc54dff016c83367912eb055637fa50cAlan Cox#define I855_HPLLCC 0xc0 5089c78134cc54dff016c83367912eb055637fa50cAlan Cox#define I855_CLOCK_CONTROL_MASK (3 << 0) 5189c78134cc54dff016c83367912eb055637fa50cAlan Cox#define I855_CLOCK_133_200 (0 << 0) 5289c78134cc54dff016c83367912eb055637fa50cAlan Cox#define I855_CLOCK_100_200 (1 << 0) 5389c78134cc54dff016c83367912eb055637fa50cAlan Cox#define I855_CLOCK_100_133 (2 << 0) 5489c78134cc54dff016c83367912eb055637fa50cAlan Cox#define I855_CLOCK_166_250 (3 << 0) 5589c78134cc54dff016c83367912eb055637fa50cAlan Cox 5689c78134cc54dff016c83367912eb055637fa50cAlan Cox/* I830 CRTC registers */ 5789c78134cc54dff016c83367912eb055637fa50cAlan Cox#define HTOTAL_A 0x60000 5889c78134cc54dff016c83367912eb055637fa50cAlan Cox#define HBLANK_A 0x60004 5989c78134cc54dff016c83367912eb055637fa50cAlan Cox#define HSYNC_A 0x60008 6089c78134cc54dff016c83367912eb055637fa50cAlan Cox#define VTOTAL_A 0x6000c 6189c78134cc54dff016c83367912eb055637fa50cAlan Cox#define VBLANK_A 0x60010 6289c78134cc54dff016c83367912eb055637fa50cAlan Cox#define VSYNC_A 0x60014 6389c78134cc54dff016c83367912eb055637fa50cAlan Cox#define PIPEASRC 0x6001c 6489c78134cc54dff016c83367912eb055637fa50cAlan Cox#define BCLRPAT_A 0x60020 6589c78134cc54dff016c83367912eb055637fa50cAlan Cox#define VSYNCSHIFT_A 0x60028 6689c78134cc54dff016c83367912eb055637fa50cAlan Cox 6789c78134cc54dff016c83367912eb055637fa50cAlan Cox#define HTOTAL_B 0x61000 6889c78134cc54dff016c83367912eb055637fa50cAlan Cox#define HBLANK_B 0x61004 6989c78134cc54dff016c83367912eb055637fa50cAlan Cox#define HSYNC_B 0x61008 7089c78134cc54dff016c83367912eb055637fa50cAlan Cox#define VTOTAL_B 0x6100c 7189c78134cc54dff016c83367912eb055637fa50cAlan Cox#define VBLANK_B 0x61010 7289c78134cc54dff016c83367912eb055637fa50cAlan Cox#define VSYNC_B 0x61014 7389c78134cc54dff016c83367912eb055637fa50cAlan Cox#define PIPEBSRC 0x6101c 7489c78134cc54dff016c83367912eb055637fa50cAlan Cox#define BCLRPAT_B 0x61020 7589c78134cc54dff016c83367912eb055637fa50cAlan Cox#define VSYNCSHIFT_B 0x61028 7689c78134cc54dff016c83367912eb055637fa50cAlan Cox 7789c78134cc54dff016c83367912eb055637fa50cAlan Cox#define HTOTAL_C 0x62000 7889c78134cc54dff016c83367912eb055637fa50cAlan Cox#define HBLANK_C 0x62004 7989c78134cc54dff016c83367912eb055637fa50cAlan Cox#define HSYNC_C 0x62008 8089c78134cc54dff016c83367912eb055637fa50cAlan Cox#define VTOTAL_C 0x6200c 8189c78134cc54dff016c83367912eb055637fa50cAlan Cox#define VBLANK_C 0x62010 8289c78134cc54dff016c83367912eb055637fa50cAlan Cox#define VSYNC_C 0x62014 8389c78134cc54dff016c83367912eb055637fa50cAlan Cox#define PIPECSRC 0x6201c 8489c78134cc54dff016c83367912eb055637fa50cAlan Cox#define BCLRPAT_C 0x62020 8589c78134cc54dff016c83367912eb055637fa50cAlan Cox#define VSYNCSHIFT_C 0x62028 8689c78134cc54dff016c83367912eb055637fa50cAlan Cox 8789c78134cc54dff016c83367912eb055637fa50cAlan Cox#define PP_STATUS 0x61200 8889c78134cc54dff016c83367912eb055637fa50cAlan Cox# define PP_ON (1 << 31) 8989c78134cc54dff016c83367912eb055637fa50cAlan Cox/* 9089c78134cc54dff016c83367912eb055637fa50cAlan Cox * Indicates that all dependencies of the panel are on: 9189c78134cc54dff016c83367912eb055637fa50cAlan Cox * 9289c78134cc54dff016c83367912eb055637fa50cAlan Cox * - PLL enabled 9389c78134cc54dff016c83367912eb055637fa50cAlan Cox * - pipe enabled 9489c78134cc54dff016c83367912eb055637fa50cAlan Cox * - LVDS/DVOB/DVOC on 9589c78134cc54dff016c83367912eb055637fa50cAlan Cox */ 9689c78134cc54dff016c83367912eb055637fa50cAlan Cox#define PP_READY (1 << 30) 9789c78134cc54dff016c83367912eb055637fa50cAlan Cox#define PP_SEQUENCE_NONE (0 << 28) 9889c78134cc54dff016c83367912eb055637fa50cAlan Cox#define PP_SEQUENCE_ON (1 << 28) 9989c78134cc54dff016c83367912eb055637fa50cAlan Cox#define PP_SEQUENCE_OFF (2 << 28) 10089c78134cc54dff016c83367912eb055637fa50cAlan Cox#define PP_SEQUENCE_MASK 0x30000000 10189c78134cc54dff016c83367912eb055637fa50cAlan Cox#define PP_CONTROL 0x61204 10289c78134cc54dff016c83367912eb055637fa50cAlan Cox#define POWER_TARGET_ON (1 << 0) 10389c78134cc54dff016c83367912eb055637fa50cAlan Cox 10489c78134cc54dff016c83367912eb055637fa50cAlan Cox#define LVDSPP_ON 0x61208 10589c78134cc54dff016c83367912eb055637fa50cAlan Cox#define LVDSPP_OFF 0x6120c 10689c78134cc54dff016c83367912eb055637fa50cAlan Cox#define PP_CYCLE 0x61210 10789c78134cc54dff016c83367912eb055637fa50cAlan Cox 10889c78134cc54dff016c83367912eb055637fa50cAlan Cox#define PFIT_CONTROL 0x61230 10989c78134cc54dff016c83367912eb055637fa50cAlan Cox#define PFIT_ENABLE (1 << 31) 11089c78134cc54dff016c83367912eb055637fa50cAlan Cox#define PFIT_PIPE_MASK (3 << 29) 11189c78134cc54dff016c83367912eb055637fa50cAlan Cox#define PFIT_PIPE_SHIFT 29 11289c78134cc54dff016c83367912eb055637fa50cAlan Cox#define PFIT_SCALING_MODE_PILLARBOX (1 << 27) 11389c78134cc54dff016c83367912eb055637fa50cAlan Cox#define PFIT_SCALING_MODE_LETTERBOX (3 << 26) 11489c78134cc54dff016c83367912eb055637fa50cAlan Cox#define VERT_INTERP_DISABLE (0 << 10) 11589c78134cc54dff016c83367912eb055637fa50cAlan Cox#define VERT_INTERP_BILINEAR (1 << 10) 11689c78134cc54dff016c83367912eb055637fa50cAlan Cox#define VERT_INTERP_MASK (3 << 10) 11789c78134cc54dff016c83367912eb055637fa50cAlan Cox#define VERT_AUTO_SCALE (1 << 9) 11889c78134cc54dff016c83367912eb055637fa50cAlan Cox#define HORIZ_INTERP_DISABLE (0 << 6) 11989c78134cc54dff016c83367912eb055637fa50cAlan Cox#define HORIZ_INTERP_BILINEAR (1 << 6) 12089c78134cc54dff016c83367912eb055637fa50cAlan Cox#define HORIZ_INTERP_MASK (3 << 6) 12189c78134cc54dff016c83367912eb055637fa50cAlan Cox#define HORIZ_AUTO_SCALE (1 << 5) 12289c78134cc54dff016c83367912eb055637fa50cAlan Cox#define PANEL_8TO6_DITHER_ENABLE (1 << 3) 12389c78134cc54dff016c83367912eb055637fa50cAlan Cox 12489c78134cc54dff016c83367912eb055637fa50cAlan Cox#define PFIT_PGM_RATIOS 0x61234 12589c78134cc54dff016c83367912eb055637fa50cAlan Cox#define PFIT_VERT_SCALE_MASK 0xfff00000 12689c78134cc54dff016c83367912eb055637fa50cAlan Cox#define PFIT_HORIZ_SCALE_MASK 0x0000fff0 12789c78134cc54dff016c83367912eb055637fa50cAlan Cox 12889c78134cc54dff016c83367912eb055637fa50cAlan Cox#define PFIT_AUTO_RATIOS 0x61238 12989c78134cc54dff016c83367912eb055637fa50cAlan Cox 13089c78134cc54dff016c83367912eb055637fa50cAlan Cox#define DPLL_A 0x06014 13189c78134cc54dff016c83367912eb055637fa50cAlan Cox#define DPLL_B 0x06018 13289c78134cc54dff016c83367912eb055637fa50cAlan Cox#define DPLL_VCO_ENABLE (1 << 31) 13389c78134cc54dff016c83367912eb055637fa50cAlan Cox#define DPLL_DVO_HIGH_SPEED (1 << 30) 13489c78134cc54dff016c83367912eb055637fa50cAlan Cox#define DPLL_SYNCLOCK_ENABLE (1 << 29) 13589c78134cc54dff016c83367912eb055637fa50cAlan Cox#define DPLL_VGA_MODE_DIS (1 << 28) 13689c78134cc54dff016c83367912eb055637fa50cAlan Cox#define DPLLB_MODE_DAC_SERIAL (1 << 26) /* i915 */ 13789c78134cc54dff016c83367912eb055637fa50cAlan Cox#define DPLLB_MODE_LVDS (2 << 26) /* i915 */ 13889c78134cc54dff016c83367912eb055637fa50cAlan Cox#define DPLL_MODE_MASK (3 << 26) 13989c78134cc54dff016c83367912eb055637fa50cAlan Cox#define DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 (0 << 24) /* i915 */ 14089c78134cc54dff016c83367912eb055637fa50cAlan Cox#define DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 (1 << 24) /* i915 */ 14189c78134cc54dff016c83367912eb055637fa50cAlan Cox#define DPLLB_LVDS_P2_CLOCK_DIV_14 (0 << 24) /* i915 */ 14289c78134cc54dff016c83367912eb055637fa50cAlan Cox#define DPLLB_LVDS_P2_CLOCK_DIV_7 (1 << 24) /* i915 */ 14389c78134cc54dff016c83367912eb055637fa50cAlan Cox#define DPLL_P2_CLOCK_DIV_MASK 0x03000000 /* i915 */ 14489c78134cc54dff016c83367912eb055637fa50cAlan Cox#define DPLL_FPA01_P1_POST_DIV_MASK 0x00ff0000 /* i915 */ 14589c78134cc54dff016c83367912eb055637fa50cAlan Cox#define DPLL_LOCK (1 << 15) /* CDV */ 14689c78134cc54dff016c83367912eb055637fa50cAlan Cox 14789c78134cc54dff016c83367912eb055637fa50cAlan Cox/* 14889c78134cc54dff016c83367912eb055637fa50cAlan Cox * The i830 generation, in DAC/serial mode, defines p1 as two plus this 14989c78134cc54dff016c83367912eb055637fa50cAlan Cox * bitfield, or just 2 if PLL_P1_DIVIDE_BY_TWO is set. 15089c78134cc54dff016c83367912eb055637fa50cAlan Cox */ 15189c78134cc54dff016c83367912eb055637fa50cAlan Cox# define DPLL_FPA01_P1_POST_DIV_MASK_I830 0x001f0000 15289c78134cc54dff016c83367912eb055637fa50cAlan Cox/* 15389c78134cc54dff016c83367912eb055637fa50cAlan Cox * The i830 generation, in LVDS mode, defines P1 as the bit number set within 15489c78134cc54dff016c83367912eb055637fa50cAlan Cox * this field (only one bit may be set). 15589c78134cc54dff016c83367912eb055637fa50cAlan Cox */ 15689c78134cc54dff016c83367912eb055637fa50cAlan Cox#define DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS 0x003f0000 15789c78134cc54dff016c83367912eb055637fa50cAlan Cox#define DPLL_FPA01_P1_POST_DIV_SHIFT 16 15889c78134cc54dff016c83367912eb055637fa50cAlan Cox#define PLL_P2_DIVIDE_BY_4 (1 << 23) /* i830, required 15989c78134cc54dff016c83367912eb055637fa50cAlan Cox * in DVO non-gang */ 16089c78134cc54dff016c83367912eb055637fa50cAlan Cox# define PLL_P1_DIVIDE_BY_TWO (1 << 21) /* i830 */ 16189c78134cc54dff016c83367912eb055637fa50cAlan Cox#define PLL_REF_INPUT_DREFCLK (0 << 13) 16289c78134cc54dff016c83367912eb055637fa50cAlan Cox#define PLL_REF_INPUT_TVCLKINA (1 << 13) /* i830 */ 16389c78134cc54dff016c83367912eb055637fa50cAlan Cox#define PLL_REF_INPUT_TVCLKINBC (2 << 13) /* SDVO 16489c78134cc54dff016c83367912eb055637fa50cAlan Cox * TVCLKIN */ 16589c78134cc54dff016c83367912eb055637fa50cAlan Cox#define PLLB_REF_INPUT_SPREADSPECTRUMIN (3 << 13) 16689c78134cc54dff016c83367912eb055637fa50cAlan Cox#define PLL_REF_INPUT_MASK (3 << 13) 16789c78134cc54dff016c83367912eb055637fa50cAlan Cox#define PLL_LOAD_PULSE_PHASE_SHIFT 9 16889c78134cc54dff016c83367912eb055637fa50cAlan Cox/* 16989c78134cc54dff016c83367912eb055637fa50cAlan Cox * Parallel to Serial Load Pulse phase selection. 17089c78134cc54dff016c83367912eb055637fa50cAlan Cox * Selects the phase for the 10X DPLL clock for the PCIe 17189c78134cc54dff016c83367912eb055637fa50cAlan Cox * digital display port. The range is 4 to 13; 10 or more 17289c78134cc54dff016c83367912eb055637fa50cAlan Cox * is just a flip delay. The default is 6 17389c78134cc54dff016c83367912eb055637fa50cAlan Cox */ 17489c78134cc54dff016c83367912eb055637fa50cAlan Cox#define PLL_LOAD_PULSE_PHASE_MASK (0xf << PLL_LOAD_PULSE_PHASE_SHIFT) 17589c78134cc54dff016c83367912eb055637fa50cAlan Cox#define DISPLAY_RATE_SELECT_FPA1 (1 << 8) 17689c78134cc54dff016c83367912eb055637fa50cAlan Cox 17789c78134cc54dff016c83367912eb055637fa50cAlan Cox/* 17889c78134cc54dff016c83367912eb055637fa50cAlan Cox * SDVO multiplier for 945G/GM. Not used on 965. 17989c78134cc54dff016c83367912eb055637fa50cAlan Cox * 18089c78134cc54dff016c83367912eb055637fa50cAlan Cox * DPLL_MD_UDI_MULTIPLIER_MASK 18189c78134cc54dff016c83367912eb055637fa50cAlan Cox */ 18289c78134cc54dff016c83367912eb055637fa50cAlan Cox#define SDVO_MULTIPLIER_MASK 0x000000ff 18389c78134cc54dff016c83367912eb055637fa50cAlan Cox#define SDVO_MULTIPLIER_SHIFT_HIRES 4 18489c78134cc54dff016c83367912eb055637fa50cAlan Cox#define SDVO_MULTIPLIER_SHIFT_VGA 0 18589c78134cc54dff016c83367912eb055637fa50cAlan Cox 18689c78134cc54dff016c83367912eb055637fa50cAlan Cox/* 18789c78134cc54dff016c83367912eb055637fa50cAlan Cox * PLL_MD 18889c78134cc54dff016c83367912eb055637fa50cAlan Cox */ 18989c78134cc54dff016c83367912eb055637fa50cAlan Cox/* Pipe A SDVO/UDI clock multiplier/divider register for G965. */ 19089c78134cc54dff016c83367912eb055637fa50cAlan Cox#define DPLL_A_MD 0x0601c 19189c78134cc54dff016c83367912eb055637fa50cAlan Cox/* Pipe B SDVO/UDI clock multiplier/divider register for G965. */ 19289c78134cc54dff016c83367912eb055637fa50cAlan Cox#define DPLL_B_MD 0x06020 19389c78134cc54dff016c83367912eb055637fa50cAlan Cox/* 19489c78134cc54dff016c83367912eb055637fa50cAlan Cox * UDI pixel divider, controlling how many pixels are stuffed into a packet. 19589c78134cc54dff016c83367912eb055637fa50cAlan Cox * 19689c78134cc54dff016c83367912eb055637fa50cAlan Cox * Value is pixels minus 1. Must be set to 1 pixel for SDVO. 19789c78134cc54dff016c83367912eb055637fa50cAlan Cox */ 19889c78134cc54dff016c83367912eb055637fa50cAlan Cox#define DPLL_MD_UDI_DIVIDER_MASK 0x3f000000 19989c78134cc54dff016c83367912eb055637fa50cAlan Cox#define DPLL_MD_UDI_DIVIDER_SHIFT 24 20089c78134cc54dff016c83367912eb055637fa50cAlan Cox/* UDI pixel divider for VGA, same as DPLL_MD_UDI_DIVIDER_MASK. */ 20189c78134cc54dff016c83367912eb055637fa50cAlan Cox#define DPLL_MD_VGA_UDI_DIVIDER_MASK 0x003f0000 20289c78134cc54dff016c83367912eb055637fa50cAlan Cox#define DPLL_MD_VGA_UDI_DIVIDER_SHIFT 16 20389c78134cc54dff016c83367912eb055637fa50cAlan Cox/* 20489c78134cc54dff016c83367912eb055637fa50cAlan Cox * SDVO/UDI pixel multiplier. 20589c78134cc54dff016c83367912eb055637fa50cAlan Cox * 20689c78134cc54dff016c83367912eb055637fa50cAlan Cox * SDVO requires that the bus clock rate be between 1 and 2 Ghz, and the bus 20789c78134cc54dff016c83367912eb055637fa50cAlan Cox * clock rate is 10 times the DPLL clock. At low resolution/refresh rate 20889c78134cc54dff016c83367912eb055637fa50cAlan Cox * modes, the bus rate would be below the limits, so SDVO allows for stuffing 20989c78134cc54dff016c83367912eb055637fa50cAlan Cox * dummy bytes in the datastream at an increased clock rate, with both sides of 21089c78134cc54dff016c83367912eb055637fa50cAlan Cox * the link knowing how many bytes are fill. 21189c78134cc54dff016c83367912eb055637fa50cAlan Cox * 21289c78134cc54dff016c83367912eb055637fa50cAlan Cox * So, for a mode with a dotclock of 65Mhz, we would want to double the clock 21389c78134cc54dff016c83367912eb055637fa50cAlan Cox * rate to 130Mhz to get a bus rate of 1.30Ghz. The DPLL clock rate would be 21489c78134cc54dff016c83367912eb055637fa50cAlan Cox * set to 130Mhz, and the SDVO multiplier set to 2x in this register and 21589c78134cc54dff016c83367912eb055637fa50cAlan Cox * through an SDVO command. 21689c78134cc54dff016c83367912eb055637fa50cAlan Cox * 21789c78134cc54dff016c83367912eb055637fa50cAlan Cox * This register field has values of multiplication factor minus 1, with 21889c78134cc54dff016c83367912eb055637fa50cAlan Cox * a maximum multiplier of 5 for SDVO. 21989c78134cc54dff016c83367912eb055637fa50cAlan Cox */ 22089c78134cc54dff016c83367912eb055637fa50cAlan Cox#define DPLL_MD_UDI_MULTIPLIER_MASK 0x00003f00 22189c78134cc54dff016c83367912eb055637fa50cAlan Cox#define DPLL_MD_UDI_MULTIPLIER_SHIFT 8 22289c78134cc54dff016c83367912eb055637fa50cAlan Cox/* 22389c78134cc54dff016c83367912eb055637fa50cAlan Cox * SDVO/UDI pixel multiplier for VGA, same as DPLL_MD_UDI_MULTIPLIER_MASK. 22489c78134cc54dff016c83367912eb055637fa50cAlan Cox * This best be set to the default value (3) or the CRT won't work. No, 22589c78134cc54dff016c83367912eb055637fa50cAlan Cox * I don't entirely understand what this does... 22689c78134cc54dff016c83367912eb055637fa50cAlan Cox */ 22789c78134cc54dff016c83367912eb055637fa50cAlan Cox#define DPLL_MD_VGA_UDI_MULTIPLIER_MASK 0x0000003f 22889c78134cc54dff016c83367912eb055637fa50cAlan Cox#define DPLL_MD_VGA_UDI_MULTIPLIER_SHIFT 0 22989c78134cc54dff016c83367912eb055637fa50cAlan Cox 23089c78134cc54dff016c83367912eb055637fa50cAlan Cox#define DPLL_TEST 0x606c 23189c78134cc54dff016c83367912eb055637fa50cAlan Cox#define DPLLB_TEST_SDVO_DIV_1 (0 << 22) 23289c78134cc54dff016c83367912eb055637fa50cAlan Cox#define DPLLB_TEST_SDVO_DIV_2 (1 << 22) 23389c78134cc54dff016c83367912eb055637fa50cAlan Cox#define DPLLB_TEST_SDVO_DIV_4 (2 << 22) 23489c78134cc54dff016c83367912eb055637fa50cAlan Cox#define DPLLB_TEST_SDVO_DIV_MASK (3 << 22) 23589c78134cc54dff016c83367912eb055637fa50cAlan Cox#define DPLLB_TEST_N_BYPASS (1 << 19) 23689c78134cc54dff016c83367912eb055637fa50cAlan Cox#define DPLLB_TEST_M_BYPASS (1 << 18) 23789c78134cc54dff016c83367912eb055637fa50cAlan Cox#define DPLLB_INPUT_BUFFER_ENABLE (1 << 16) 23889c78134cc54dff016c83367912eb055637fa50cAlan Cox#define DPLLA_TEST_N_BYPASS (1 << 3) 23989c78134cc54dff016c83367912eb055637fa50cAlan Cox#define DPLLA_TEST_M_BYPASS (1 << 2) 24089c78134cc54dff016c83367912eb055637fa50cAlan Cox#define DPLLA_INPUT_BUFFER_ENABLE (1 << 0) 24189c78134cc54dff016c83367912eb055637fa50cAlan Cox 24289c78134cc54dff016c83367912eb055637fa50cAlan Cox#define ADPA 0x61100 24389c78134cc54dff016c83367912eb055637fa50cAlan Cox#define ADPA_DAC_ENABLE (1 << 31) 24489c78134cc54dff016c83367912eb055637fa50cAlan Cox#define ADPA_DAC_DISABLE 0 24589c78134cc54dff016c83367912eb055637fa50cAlan Cox#define ADPA_PIPE_SELECT_MASK (1 << 30) 24689c78134cc54dff016c83367912eb055637fa50cAlan Cox#define ADPA_PIPE_A_SELECT 0 24789c78134cc54dff016c83367912eb055637fa50cAlan Cox#define ADPA_PIPE_B_SELECT (1 << 30) 24889c78134cc54dff016c83367912eb055637fa50cAlan Cox#define ADPA_USE_VGA_HVPOLARITY (1 << 15) 24989c78134cc54dff016c83367912eb055637fa50cAlan Cox#define ADPA_SETS_HVPOLARITY 0 25089c78134cc54dff016c83367912eb055637fa50cAlan Cox#define ADPA_VSYNC_CNTL_DISABLE (1 << 11) 25189c78134cc54dff016c83367912eb055637fa50cAlan Cox#define ADPA_VSYNC_CNTL_ENABLE 0 25289c78134cc54dff016c83367912eb055637fa50cAlan Cox#define ADPA_HSYNC_CNTL_DISABLE (1 << 10) 25389c78134cc54dff016c83367912eb055637fa50cAlan Cox#define ADPA_HSYNC_CNTL_ENABLE 0 25489c78134cc54dff016c83367912eb055637fa50cAlan Cox#define ADPA_VSYNC_ACTIVE_HIGH (1 << 4) 25589c78134cc54dff016c83367912eb055637fa50cAlan Cox#define ADPA_VSYNC_ACTIVE_LOW 0 25689c78134cc54dff016c83367912eb055637fa50cAlan Cox#define ADPA_HSYNC_ACTIVE_HIGH (1 << 3) 25789c78134cc54dff016c83367912eb055637fa50cAlan Cox#define ADPA_HSYNC_ACTIVE_LOW 0 25889c78134cc54dff016c83367912eb055637fa50cAlan Cox 25989c78134cc54dff016c83367912eb055637fa50cAlan Cox#define FPA0 0x06040 26089c78134cc54dff016c83367912eb055637fa50cAlan Cox#define FPA1 0x06044 26189c78134cc54dff016c83367912eb055637fa50cAlan Cox#define FPB0 0x06048 26289c78134cc54dff016c83367912eb055637fa50cAlan Cox#define FPB1 0x0604c 26389c78134cc54dff016c83367912eb055637fa50cAlan Cox#define FP_N_DIV_MASK 0x003f0000 26489c78134cc54dff016c83367912eb055637fa50cAlan Cox#define FP_N_DIV_SHIFT 16 26589c78134cc54dff016c83367912eb055637fa50cAlan Cox#define FP_M1_DIV_MASK 0x00003f00 26689c78134cc54dff016c83367912eb055637fa50cAlan Cox#define FP_M1_DIV_SHIFT 8 26789c78134cc54dff016c83367912eb055637fa50cAlan Cox#define FP_M2_DIV_MASK 0x0000003f 26889c78134cc54dff016c83367912eb055637fa50cAlan Cox#define FP_M2_DIV_SHIFT 0 26989c78134cc54dff016c83367912eb055637fa50cAlan Cox 27089c78134cc54dff016c83367912eb055637fa50cAlan Cox#define PORT_HOTPLUG_EN 0x61110 27189c78134cc54dff016c83367912eb055637fa50cAlan Cox#define SDVOB_HOTPLUG_INT_EN (1 << 26) 27289c78134cc54dff016c83367912eb055637fa50cAlan Cox#define SDVOC_HOTPLUG_INT_EN (1 << 25) 27389c78134cc54dff016c83367912eb055637fa50cAlan Cox#define TV_HOTPLUG_INT_EN (1 << 18) 27489c78134cc54dff016c83367912eb055637fa50cAlan Cox#define CRT_HOTPLUG_INT_EN (1 << 9) 27589c78134cc54dff016c83367912eb055637fa50cAlan Cox#define CRT_HOTPLUG_FORCE_DETECT (1 << 3) 27689c78134cc54dff016c83367912eb055637fa50cAlan Cox/* CDV.. */ 27789c78134cc54dff016c83367912eb055637fa50cAlan Cox#define CRT_HOTPLUG_ACTIVATION_PERIOD_64 (1 << 8) 27889c78134cc54dff016c83367912eb055637fa50cAlan Cox#define CRT_HOTPLUG_DAC_ON_TIME_2M (0 << 7) 27989c78134cc54dff016c83367912eb055637fa50cAlan Cox#define CRT_HOTPLUG_DAC_ON_TIME_4M (1 << 7) 28089c78134cc54dff016c83367912eb055637fa50cAlan Cox#define CRT_HOTPLUG_VOLTAGE_COMPARE_40 (0 << 5) 28189c78134cc54dff016c83367912eb055637fa50cAlan Cox#define CRT_HOTPLUG_VOLTAGE_COMPARE_50 (1 << 5) 28289c78134cc54dff016c83367912eb055637fa50cAlan Cox#define CRT_HOTPLUG_VOLTAGE_COMPARE_60 (2 << 5) 28389c78134cc54dff016c83367912eb055637fa50cAlan Cox#define CRT_HOTPLUG_VOLTAGE_COMPARE_70 (3 << 5) 28489c78134cc54dff016c83367912eb055637fa50cAlan Cox#define CRT_HOTPLUG_VOLTAGE_COMPARE_MASK (3 << 5) 28589c78134cc54dff016c83367912eb055637fa50cAlan Cox#define CRT_HOTPLUG_DETECT_DELAY_1G (0 << 4) 28689c78134cc54dff016c83367912eb055637fa50cAlan Cox#define CRT_HOTPLUG_DETECT_DELAY_2G (1 << 4) 28789c78134cc54dff016c83367912eb055637fa50cAlan Cox#define CRT_HOTPLUG_DETECT_VOLTAGE_325MV (0 << 2) 28889c78134cc54dff016c83367912eb055637fa50cAlan Cox#define CRT_HOTPLUG_DETECT_VOLTAGE_475MV (1 << 2) 28989c78134cc54dff016c83367912eb055637fa50cAlan Cox#define CRT_HOTPLUG_DETECT_MASK 0x000000F8 29089c78134cc54dff016c83367912eb055637fa50cAlan Cox 29189c78134cc54dff016c83367912eb055637fa50cAlan Cox#define PORT_HOTPLUG_STAT 0x61114 29289c78134cc54dff016c83367912eb055637fa50cAlan Cox#define CRT_HOTPLUG_INT_STATUS (1 << 11) 29389c78134cc54dff016c83367912eb055637fa50cAlan Cox#define TV_HOTPLUG_INT_STATUS (1 << 10) 29489c78134cc54dff016c83367912eb055637fa50cAlan Cox#define CRT_HOTPLUG_MONITOR_MASK (3 << 8) 29589c78134cc54dff016c83367912eb055637fa50cAlan Cox#define CRT_HOTPLUG_MONITOR_COLOR (3 << 8) 29689c78134cc54dff016c83367912eb055637fa50cAlan Cox#define CRT_HOTPLUG_MONITOR_MONO (2 << 8) 29789c78134cc54dff016c83367912eb055637fa50cAlan Cox#define CRT_HOTPLUG_MONITOR_NONE (0 << 8) 29889c78134cc54dff016c83367912eb055637fa50cAlan Cox#define SDVOC_HOTPLUG_INT_STATUS (1 << 7) 29989c78134cc54dff016c83367912eb055637fa50cAlan Cox#define SDVOB_HOTPLUG_INT_STATUS (1 << 6) 30089c78134cc54dff016c83367912eb055637fa50cAlan Cox 30189c78134cc54dff016c83367912eb055637fa50cAlan Cox#define SDVOB 0x61140 30289c78134cc54dff016c83367912eb055637fa50cAlan Cox#define SDVOC 0x61160 30389c78134cc54dff016c83367912eb055637fa50cAlan Cox#define SDVO_ENABLE (1 << 31) 30489c78134cc54dff016c83367912eb055637fa50cAlan Cox#define SDVO_PIPE_B_SELECT (1 << 30) 30589c78134cc54dff016c83367912eb055637fa50cAlan Cox#define SDVO_STALL_SELECT (1 << 29) 30689c78134cc54dff016c83367912eb055637fa50cAlan Cox#define SDVO_INTERRUPT_ENABLE (1 << 26) 30789c78134cc54dff016c83367912eb055637fa50cAlan Cox 30889c78134cc54dff016c83367912eb055637fa50cAlan Cox/** 30989c78134cc54dff016c83367912eb055637fa50cAlan Cox * 915G/GM SDVO pixel multiplier. 31089c78134cc54dff016c83367912eb055637fa50cAlan Cox * 31189c78134cc54dff016c83367912eb055637fa50cAlan Cox * Programmed value is multiplier - 1, up to 5x. 31289c78134cc54dff016c83367912eb055637fa50cAlan Cox * 31389c78134cc54dff016c83367912eb055637fa50cAlan Cox * DPLL_MD_UDI_MULTIPLIER_MASK 31489c78134cc54dff016c83367912eb055637fa50cAlan Cox */ 31589c78134cc54dff016c83367912eb055637fa50cAlan Cox#define SDVO_PORT_MULTIPLY_MASK (7 << 23) 31689c78134cc54dff016c83367912eb055637fa50cAlan Cox#define SDVO_PORT_MULTIPLY_SHIFT 23 31789c78134cc54dff016c83367912eb055637fa50cAlan Cox#define SDVO_PHASE_SELECT_MASK (15 << 19) 31889c78134cc54dff016c83367912eb055637fa50cAlan Cox#define SDVO_PHASE_SELECT_DEFAULT (6 << 19) 31989c78134cc54dff016c83367912eb055637fa50cAlan Cox#define SDVO_CLOCK_OUTPUT_INVERT (1 << 18) 32089c78134cc54dff016c83367912eb055637fa50cAlan Cox#define SDVOC_GANG_MODE (1 << 16) 32189c78134cc54dff016c83367912eb055637fa50cAlan Cox#define SDVO_BORDER_ENABLE (1 << 7) 32289c78134cc54dff016c83367912eb055637fa50cAlan Cox#define SDVOB_PCIE_CONCURRENCY (1 << 3) 32389c78134cc54dff016c83367912eb055637fa50cAlan Cox#define SDVO_DETECTED (1 << 2) 32489c78134cc54dff016c83367912eb055637fa50cAlan Cox/* Bits to be preserved when writing */ 32589c78134cc54dff016c83367912eb055637fa50cAlan Cox#define SDVOB_PRESERVE_MASK ((1 << 17) | (1 << 16) | (1 << 14)) 32689c78134cc54dff016c83367912eb055637fa50cAlan Cox#define SDVOC_PRESERVE_MASK (1 << 17) 32789c78134cc54dff016c83367912eb055637fa50cAlan Cox 32889c78134cc54dff016c83367912eb055637fa50cAlan Cox/* 32989c78134cc54dff016c83367912eb055637fa50cAlan Cox * This register controls the LVDS output enable, pipe selection, and data 33089c78134cc54dff016c83367912eb055637fa50cAlan Cox * format selection. 33189c78134cc54dff016c83367912eb055637fa50cAlan Cox * 33289c78134cc54dff016c83367912eb055637fa50cAlan Cox * All of the clock/data pairs are force powered down by power sequencing. 33389c78134cc54dff016c83367912eb055637fa50cAlan Cox */ 33489c78134cc54dff016c83367912eb055637fa50cAlan Cox#define LVDS 0x61180 33589c78134cc54dff016c83367912eb055637fa50cAlan Cox/* 33689c78134cc54dff016c83367912eb055637fa50cAlan Cox * Enables the LVDS port. This bit must be set before DPLLs are enabled, as 33789c78134cc54dff016c83367912eb055637fa50cAlan Cox * the DPLL semantics change when the LVDS is assigned to that pipe. 33889c78134cc54dff016c83367912eb055637fa50cAlan Cox */ 33989c78134cc54dff016c83367912eb055637fa50cAlan Cox#define LVDS_PORT_EN (1 << 31) 34089c78134cc54dff016c83367912eb055637fa50cAlan Cox/* Selects pipe B for LVDS data. Must be set on pre-965. */ 34189c78134cc54dff016c83367912eb055637fa50cAlan Cox#define LVDS_PIPEB_SELECT (1 << 30) 34289c78134cc54dff016c83367912eb055637fa50cAlan Cox 34389c78134cc54dff016c83367912eb055637fa50cAlan Cox/* Turns on border drawing to allow centered display. */ 34489c78134cc54dff016c83367912eb055637fa50cAlan Cox#define LVDS_BORDER_EN (1 << 15) 34589c78134cc54dff016c83367912eb055637fa50cAlan Cox 34689c78134cc54dff016c83367912eb055637fa50cAlan Cox/* 34789c78134cc54dff016c83367912eb055637fa50cAlan Cox * Enables the A0-A2 data pairs and CLKA, containing 18 bits of color data per 34889c78134cc54dff016c83367912eb055637fa50cAlan Cox * pixel. 34989c78134cc54dff016c83367912eb055637fa50cAlan Cox */ 35089c78134cc54dff016c83367912eb055637fa50cAlan Cox#define LVDS_A0A2_CLKA_POWER_MASK (3 << 8) 35189c78134cc54dff016c83367912eb055637fa50cAlan Cox#define LVDS_A0A2_CLKA_POWER_DOWN (0 << 8) 35289c78134cc54dff016c83367912eb055637fa50cAlan Cox#define LVDS_A0A2_CLKA_POWER_UP (3 << 8) 35389c78134cc54dff016c83367912eb055637fa50cAlan Cox/* 35489c78134cc54dff016c83367912eb055637fa50cAlan Cox * Controls the A3 data pair, which contains the additional LSBs for 24 bit 35589c78134cc54dff016c83367912eb055637fa50cAlan Cox * mode. Only enabled if LVDS_A0A2_CLKA_POWER_UP also indicates it should be 35689c78134cc54dff016c83367912eb055637fa50cAlan Cox * on. 35789c78134cc54dff016c83367912eb055637fa50cAlan Cox */ 35889c78134cc54dff016c83367912eb055637fa50cAlan Cox#define LVDS_A3_POWER_MASK (3 << 6) 35989c78134cc54dff016c83367912eb055637fa50cAlan Cox#define LVDS_A3_POWER_DOWN (0 << 6) 36089c78134cc54dff016c83367912eb055637fa50cAlan Cox#define LVDS_A3_POWER_UP (3 << 6) 36189c78134cc54dff016c83367912eb055637fa50cAlan Cox/* 36289c78134cc54dff016c83367912eb055637fa50cAlan Cox * Controls the CLKB pair. This should only be set when LVDS_B0B3_POWER_UP 36389c78134cc54dff016c83367912eb055637fa50cAlan Cox * is set. 36489c78134cc54dff016c83367912eb055637fa50cAlan Cox */ 36589c78134cc54dff016c83367912eb055637fa50cAlan Cox#define LVDS_CLKB_POWER_MASK (3 << 4) 36689c78134cc54dff016c83367912eb055637fa50cAlan Cox#define LVDS_CLKB_POWER_DOWN (0 << 4) 36789c78134cc54dff016c83367912eb055637fa50cAlan Cox#define LVDS_CLKB_POWER_UP (3 << 4) 36889c78134cc54dff016c83367912eb055637fa50cAlan Cox/* 36989c78134cc54dff016c83367912eb055637fa50cAlan Cox * Controls the B0-B3 data pairs. This must be set to match the DPLL p2 37089c78134cc54dff016c83367912eb055637fa50cAlan Cox * setting for whether we are in dual-channel mode. The B3 pair will 37189c78134cc54dff016c83367912eb055637fa50cAlan Cox * additionally only be powered up when LVDS_A3_POWER_UP is set. 37289c78134cc54dff016c83367912eb055637fa50cAlan Cox */ 37389c78134cc54dff016c83367912eb055637fa50cAlan Cox#define LVDS_B0B3_POWER_MASK (3 << 2) 37489c78134cc54dff016c83367912eb055637fa50cAlan Cox#define LVDS_B0B3_POWER_DOWN (0 << 2) 37589c78134cc54dff016c83367912eb055637fa50cAlan Cox#define LVDS_B0B3_POWER_UP (3 << 2) 37689c78134cc54dff016c83367912eb055637fa50cAlan Cox 37789c78134cc54dff016c83367912eb055637fa50cAlan Cox#define PIPEACONF 0x70008 37889c78134cc54dff016c83367912eb055637fa50cAlan Cox#define PIPEACONF_ENABLE (1 << 31) 37989c78134cc54dff016c83367912eb055637fa50cAlan Cox#define PIPEACONF_DISABLE 0 38089c78134cc54dff016c83367912eb055637fa50cAlan Cox#define PIPEACONF_DOUBLE_WIDE (1 << 30) 38189c78134cc54dff016c83367912eb055637fa50cAlan Cox#define PIPECONF_ACTIVE (1 << 30) 38289c78134cc54dff016c83367912eb055637fa50cAlan Cox#define I965_PIPECONF_ACTIVE (1 << 30) 38389c78134cc54dff016c83367912eb055637fa50cAlan Cox#define PIPECONF_DSIPLL_LOCK (1 << 29) 38489c78134cc54dff016c83367912eb055637fa50cAlan Cox#define PIPEACONF_SINGLE_WIDE 0 38589c78134cc54dff016c83367912eb055637fa50cAlan Cox#define PIPEACONF_PIPE_UNLOCKED 0 38689c78134cc54dff016c83367912eb055637fa50cAlan Cox#define PIPEACONF_DSR (1 << 26) 38789c78134cc54dff016c83367912eb055637fa50cAlan Cox#define PIPEACONF_PIPE_LOCKED (1 << 25) 38889c78134cc54dff016c83367912eb055637fa50cAlan Cox#define PIPEACONF_PALETTE 0 38989c78134cc54dff016c83367912eb055637fa50cAlan Cox#define PIPECONF_FORCE_BORDER (1 << 25) 39089c78134cc54dff016c83367912eb055637fa50cAlan Cox#define PIPEACONF_GAMMA (1 << 24) 39189c78134cc54dff016c83367912eb055637fa50cAlan Cox#define PIPECONF_PROGRESSIVE (0 << 21) 39289c78134cc54dff016c83367912eb055637fa50cAlan Cox#define PIPECONF_INTERLACE_W_FIELD_INDICATION (6 << 21) 39389c78134cc54dff016c83367912eb055637fa50cAlan Cox#define PIPECONF_INTERLACE_FIELD_0_ONLY (7 << 21) 39489c78134cc54dff016c83367912eb055637fa50cAlan Cox#define PIPECONF_PLANE_OFF (1 << 19) 39589c78134cc54dff016c83367912eb055637fa50cAlan Cox#define PIPECONF_CURSOR_OFF (1 << 18) 39689c78134cc54dff016c83367912eb055637fa50cAlan Cox 39789c78134cc54dff016c83367912eb055637fa50cAlan Cox#define PIPEBCONF 0x71008 39889c78134cc54dff016c83367912eb055637fa50cAlan Cox#define PIPEBCONF_ENABLE (1 << 31) 39989c78134cc54dff016c83367912eb055637fa50cAlan Cox#define PIPEBCONF_DISABLE 0 40089c78134cc54dff016c83367912eb055637fa50cAlan Cox#define PIPEBCONF_DOUBLE_WIDE (1 << 30) 40189c78134cc54dff016c83367912eb055637fa50cAlan Cox#define PIPEBCONF_DISABLE 0 40289c78134cc54dff016c83367912eb055637fa50cAlan Cox#define PIPEBCONF_GAMMA (1 << 24) 40389c78134cc54dff016c83367912eb055637fa50cAlan Cox#define PIPEBCONF_PALETTE 0 40489c78134cc54dff016c83367912eb055637fa50cAlan Cox 40589c78134cc54dff016c83367912eb055637fa50cAlan Cox#define PIPECCONF 0x72008 40689c78134cc54dff016c83367912eb055637fa50cAlan Cox 40789c78134cc54dff016c83367912eb055637fa50cAlan Cox#define PIPEBGCMAXRED 0x71010 40889c78134cc54dff016c83367912eb055637fa50cAlan Cox#define PIPEBGCMAXGREEN 0x71014 40989c78134cc54dff016c83367912eb055637fa50cAlan Cox#define PIPEBGCMAXBLUE 0x71018 41089c78134cc54dff016c83367912eb055637fa50cAlan Cox 41189c78134cc54dff016c83367912eb055637fa50cAlan Cox#define PIPEASTAT 0x70024 41289c78134cc54dff016c83367912eb055637fa50cAlan Cox#define PIPEBSTAT 0x71024 41389c78134cc54dff016c83367912eb055637fa50cAlan Cox#define PIPECSTAT 0x72024 41489c78134cc54dff016c83367912eb055637fa50cAlan Cox#define PIPE_VBLANK_INTERRUPT_STATUS (1UL << 1) 41589c78134cc54dff016c83367912eb055637fa50cAlan Cox#define PIPE_START_VBLANK_INTERRUPT_STATUS (1UL << 2) 41689c78134cc54dff016c83367912eb055637fa50cAlan Cox#define PIPE_VBLANK_CLEAR (1 << 1) 41789c78134cc54dff016c83367912eb055637fa50cAlan Cox#define PIPE_VBLANK_STATUS (1 << 1) 41889c78134cc54dff016c83367912eb055637fa50cAlan Cox#define PIPE_TE_STATUS (1UL << 6) 41989c78134cc54dff016c83367912eb055637fa50cAlan Cox#define PIPE_DPST_EVENT_STATUS (1UL << 7) 42089c78134cc54dff016c83367912eb055637fa50cAlan Cox#define PIPE_VSYNC_CLEAR (1UL << 9) 42189c78134cc54dff016c83367912eb055637fa50cAlan Cox#define PIPE_VSYNC_STATUS (1UL << 9) 42289c78134cc54dff016c83367912eb055637fa50cAlan Cox#define PIPE_HDMI_AUDIO_UNDERRUN_STATUS (1UL << 10) 42389c78134cc54dff016c83367912eb055637fa50cAlan Cox#define PIPE_HDMI_AUDIO_BUFFER_DONE_STATUS (1UL << 11) 42489c78134cc54dff016c83367912eb055637fa50cAlan Cox#define PIPE_VBLANK_INTERRUPT_ENABLE (1UL << 17) 42589c78134cc54dff016c83367912eb055637fa50cAlan Cox#define PIPE_START_VBLANK_INTERRUPT_ENABLE (1UL << 18) 42689c78134cc54dff016c83367912eb055637fa50cAlan Cox#define PIPE_TE_ENABLE (1UL << 22) 42789c78134cc54dff016c83367912eb055637fa50cAlan Cox#define PIPE_DPST_EVENT_ENABLE (1UL << 23) 42889c78134cc54dff016c83367912eb055637fa50cAlan Cox#define PIPE_VSYNC_ENABL (1UL << 25) 42989c78134cc54dff016c83367912eb055637fa50cAlan Cox#define PIPE_HDMI_AUDIO_UNDERRUN (1UL << 26) 43089c78134cc54dff016c83367912eb055637fa50cAlan Cox#define PIPE_HDMI_AUDIO_BUFFER_DONE (1UL << 27) 43189c78134cc54dff016c83367912eb055637fa50cAlan Cox#define PIPE_HDMI_AUDIO_INT_MASK (PIPE_HDMI_AUDIO_UNDERRUN | \ 43289c78134cc54dff016c83367912eb055637fa50cAlan Cox PIPE_HDMI_AUDIO_BUFFER_DONE) 43389c78134cc54dff016c83367912eb055637fa50cAlan Cox#define PIPE_EVENT_MASK ((1 << 29)|(1 << 28)|(1 << 27)|(1 << 26)|(1 << 24)|(1 << 23)|(1 << 22)|(1 << 21)|(1 << 20)|(1 << 16)) 43489c78134cc54dff016c83367912eb055637fa50cAlan Cox#define PIPE_VBLANK_MASK ((1 << 25)|(1 << 24)|(1 << 18)|(1 << 17)) 43589c78134cc54dff016c83367912eb055637fa50cAlan Cox#define HISTOGRAM_INT_CONTROL 0x61268 43689c78134cc54dff016c83367912eb055637fa50cAlan Cox#define HISTOGRAM_BIN_DATA 0X61264 43789c78134cc54dff016c83367912eb055637fa50cAlan Cox#define HISTOGRAM_LOGIC_CONTROL 0x61260 43889c78134cc54dff016c83367912eb055637fa50cAlan Cox#define PWM_CONTROL_LOGIC 0x61250 43989c78134cc54dff016c83367912eb055637fa50cAlan Cox#define PIPE_HOTPLUG_INTERRUPT_STATUS (1UL << 10) 44089c78134cc54dff016c83367912eb055637fa50cAlan Cox#define HISTOGRAM_INTERRUPT_ENABLE (1UL << 31) 44189c78134cc54dff016c83367912eb055637fa50cAlan Cox#define HISTOGRAM_LOGIC_ENABLE (1UL << 31) 44289c78134cc54dff016c83367912eb055637fa50cAlan Cox#define PWM_LOGIC_ENABLE (1UL << 31) 44389c78134cc54dff016c83367912eb055637fa50cAlan Cox#define PWM_PHASEIN_ENABLE (1UL << 25) 44489c78134cc54dff016c83367912eb055637fa50cAlan Cox#define PWM_PHASEIN_INT_ENABLE (1UL << 24) 44589c78134cc54dff016c83367912eb055637fa50cAlan Cox#define PWM_PHASEIN_VB_COUNT 0x00001f00 44689c78134cc54dff016c83367912eb055637fa50cAlan Cox#define PWM_PHASEIN_INC 0x0000001f 44789c78134cc54dff016c83367912eb055637fa50cAlan Cox#define HISTOGRAM_INT_CTRL_CLEAR (1UL << 30) 44889c78134cc54dff016c83367912eb055637fa50cAlan Cox#define DPST_YUV_LUMA_MODE 0 44989c78134cc54dff016c83367912eb055637fa50cAlan Cox 45089c78134cc54dff016c83367912eb055637fa50cAlan Coxstruct dpst_ie_histogram_control { 45189c78134cc54dff016c83367912eb055637fa50cAlan Cox union { 45289c78134cc54dff016c83367912eb055637fa50cAlan Cox uint32_t data; 45389c78134cc54dff016c83367912eb055637fa50cAlan Cox struct { 45489c78134cc54dff016c83367912eb055637fa50cAlan Cox uint32_t bin_reg_index:7; 45589c78134cc54dff016c83367912eb055637fa50cAlan Cox uint32_t reserved:4; 45689c78134cc54dff016c83367912eb055637fa50cAlan Cox uint32_t bin_reg_func_select:1; 45789c78134cc54dff016c83367912eb055637fa50cAlan Cox uint32_t sync_to_phase_in:1; 45889c78134cc54dff016c83367912eb055637fa50cAlan Cox uint32_t alt_enhancement_mode:2; 45989c78134cc54dff016c83367912eb055637fa50cAlan Cox uint32_t reserved1:1; 46089c78134cc54dff016c83367912eb055637fa50cAlan Cox uint32_t sync_to_phase_in_count:8; 46189c78134cc54dff016c83367912eb055637fa50cAlan Cox uint32_t histogram_mode_select:1; 46289c78134cc54dff016c83367912eb055637fa50cAlan Cox uint32_t reserved2:4; 46389c78134cc54dff016c83367912eb055637fa50cAlan Cox uint32_t ie_pipe_assignment:1; 46489c78134cc54dff016c83367912eb055637fa50cAlan Cox uint32_t ie_mode_table_enabled:1; 46589c78134cc54dff016c83367912eb055637fa50cAlan Cox uint32_t ie_histogram_enable:1; 46689c78134cc54dff016c83367912eb055637fa50cAlan Cox }; 46789c78134cc54dff016c83367912eb055637fa50cAlan Cox }; 46889c78134cc54dff016c83367912eb055637fa50cAlan Cox}; 46989c78134cc54dff016c83367912eb055637fa50cAlan Cox 47089c78134cc54dff016c83367912eb055637fa50cAlan Coxstruct dpst_guardband { 47189c78134cc54dff016c83367912eb055637fa50cAlan Cox union { 47289c78134cc54dff016c83367912eb055637fa50cAlan Cox uint32_t data; 47389c78134cc54dff016c83367912eb055637fa50cAlan Cox struct { 47489c78134cc54dff016c83367912eb055637fa50cAlan Cox uint32_t guardband:22; 47589c78134cc54dff016c83367912eb055637fa50cAlan Cox uint32_t guardband_interrupt_delay:8; 47689c78134cc54dff016c83367912eb055637fa50cAlan Cox uint32_t interrupt_status:1; 47789c78134cc54dff016c83367912eb055637fa50cAlan Cox uint32_t interrupt_enable:1; 47889c78134cc54dff016c83367912eb055637fa50cAlan Cox }; 47989c78134cc54dff016c83367912eb055637fa50cAlan Cox }; 48089c78134cc54dff016c83367912eb055637fa50cAlan Cox}; 48189c78134cc54dff016c83367912eb055637fa50cAlan Cox 48289c78134cc54dff016c83367912eb055637fa50cAlan Cox#define PIPEAFRAMEHIGH 0x70040 48389c78134cc54dff016c83367912eb055637fa50cAlan Cox#define PIPEAFRAMEPIXEL 0x70044 48489c78134cc54dff016c83367912eb055637fa50cAlan Cox#define PIPEBFRAMEHIGH 0x71040 48589c78134cc54dff016c83367912eb055637fa50cAlan Cox#define PIPEBFRAMEPIXEL 0x71044 48689c78134cc54dff016c83367912eb055637fa50cAlan Cox#define PIPECFRAMEHIGH 0x72040 48789c78134cc54dff016c83367912eb055637fa50cAlan Cox#define PIPECFRAMEPIXEL 0x72044 48889c78134cc54dff016c83367912eb055637fa50cAlan Cox#define PIPE_FRAME_HIGH_MASK 0x0000ffff 48989c78134cc54dff016c83367912eb055637fa50cAlan Cox#define PIPE_FRAME_HIGH_SHIFT 0 49089c78134cc54dff016c83367912eb055637fa50cAlan Cox#define PIPE_FRAME_LOW_MASK 0xff000000 49189c78134cc54dff016c83367912eb055637fa50cAlan Cox#define PIPE_FRAME_LOW_SHIFT 24 49289c78134cc54dff016c83367912eb055637fa50cAlan Cox#define PIPE_PIXEL_MASK 0x00ffffff 49389c78134cc54dff016c83367912eb055637fa50cAlan Cox#define PIPE_PIXEL_SHIFT 0 49489c78134cc54dff016c83367912eb055637fa50cAlan Cox 49589c78134cc54dff016c83367912eb055637fa50cAlan Cox#define DSPARB 0x70030 49689c78134cc54dff016c83367912eb055637fa50cAlan Cox#define DSPFW1 0x70034 49789c78134cc54dff016c83367912eb055637fa50cAlan Cox#define DSPFW2 0x70038 49889c78134cc54dff016c83367912eb055637fa50cAlan Cox#define DSPFW3 0x7003c 49989c78134cc54dff016c83367912eb055637fa50cAlan Cox#define DSPFW4 0x70050 50089c78134cc54dff016c83367912eb055637fa50cAlan Cox#define DSPFW5 0x70054 50189c78134cc54dff016c83367912eb055637fa50cAlan Cox#define DSPFW6 0x70058 50289c78134cc54dff016c83367912eb055637fa50cAlan Cox#define DSPCHICKENBIT 0x70400 50389c78134cc54dff016c83367912eb055637fa50cAlan Cox#define DSPACNTR 0x70180 50489c78134cc54dff016c83367912eb055637fa50cAlan Cox#define DSPBCNTR 0x71180 50589c78134cc54dff016c83367912eb055637fa50cAlan Cox#define DSPCCNTR 0x72180 50689c78134cc54dff016c83367912eb055637fa50cAlan Cox#define DISPLAY_PLANE_ENABLE (1 << 31) 50789c78134cc54dff016c83367912eb055637fa50cAlan Cox#define DISPLAY_PLANE_DISABLE 0 50889c78134cc54dff016c83367912eb055637fa50cAlan Cox#define DISPPLANE_GAMMA_ENABLE (1 << 30) 50989c78134cc54dff016c83367912eb055637fa50cAlan Cox#define DISPPLANE_GAMMA_DISABLE 0 51089c78134cc54dff016c83367912eb055637fa50cAlan Cox#define DISPPLANE_PIXFORMAT_MASK (0xf << 26) 51189c78134cc54dff016c83367912eb055637fa50cAlan Cox#define DISPPLANE_8BPP (0x2 << 26) 51289c78134cc54dff016c83367912eb055637fa50cAlan Cox#define DISPPLANE_15_16BPP (0x4 << 26) 51389c78134cc54dff016c83367912eb055637fa50cAlan Cox#define DISPPLANE_16BPP (0x5 << 26) 51489c78134cc54dff016c83367912eb055637fa50cAlan Cox#define DISPPLANE_32BPP_NO_ALPHA (0x6 << 26) 51589c78134cc54dff016c83367912eb055637fa50cAlan Cox#define DISPPLANE_32BPP (0x7 << 26) 51689c78134cc54dff016c83367912eb055637fa50cAlan Cox#define DISPPLANE_STEREO_ENABLE (1 << 25) 51789c78134cc54dff016c83367912eb055637fa50cAlan Cox#define DISPPLANE_STEREO_DISABLE 0 51889c78134cc54dff016c83367912eb055637fa50cAlan Cox#define DISPPLANE_SEL_PIPE_MASK (1 << 24) 51989c78134cc54dff016c83367912eb055637fa50cAlan Cox#define DISPPLANE_SEL_PIPE_POS 24 52089c78134cc54dff016c83367912eb055637fa50cAlan Cox#define DISPPLANE_SEL_PIPE_A 0 52189c78134cc54dff016c83367912eb055637fa50cAlan Cox#define DISPPLANE_SEL_PIPE_B (1 << 24) 52289c78134cc54dff016c83367912eb055637fa50cAlan Cox#define DISPPLANE_SRC_KEY_ENABLE (1 << 22) 52389c78134cc54dff016c83367912eb055637fa50cAlan Cox#define DISPPLANE_SRC_KEY_DISABLE 0 52489c78134cc54dff016c83367912eb055637fa50cAlan Cox#define DISPPLANE_LINE_DOUBLE (1 << 20) 52589c78134cc54dff016c83367912eb055637fa50cAlan Cox#define DISPPLANE_NO_LINE_DOUBLE 0 52689c78134cc54dff016c83367912eb055637fa50cAlan Cox#define DISPPLANE_STEREO_POLARITY_FIRST 0 52789c78134cc54dff016c83367912eb055637fa50cAlan Cox#define DISPPLANE_STEREO_POLARITY_SECOND (1 << 18) 52889c78134cc54dff016c83367912eb055637fa50cAlan Cox/* plane B only */ 52989c78134cc54dff016c83367912eb055637fa50cAlan Cox#define DISPPLANE_ALPHA_TRANS_ENABLE (1 << 15) 53089c78134cc54dff016c83367912eb055637fa50cAlan Cox#define DISPPLANE_ALPHA_TRANS_DISABLE 0 53189c78134cc54dff016c83367912eb055637fa50cAlan Cox#define DISPPLANE_SPRITE_ABOVE_DISPLAYA 0 53289c78134cc54dff016c83367912eb055637fa50cAlan Cox#define DISPPLANE_SPRITE_ABOVE_OVERLAY (1) 53389c78134cc54dff016c83367912eb055637fa50cAlan Cox#define DISPPLANE_BOTTOM (4) 53489c78134cc54dff016c83367912eb055637fa50cAlan Cox 53589c78134cc54dff016c83367912eb055637fa50cAlan Cox#define DSPABASE 0x70184 53689c78134cc54dff016c83367912eb055637fa50cAlan Cox#define DSPALINOFF 0x70184 53789c78134cc54dff016c83367912eb055637fa50cAlan Cox#define DSPASTRIDE 0x70188 53889c78134cc54dff016c83367912eb055637fa50cAlan Cox 53989c78134cc54dff016c83367912eb055637fa50cAlan Cox#define DSPBBASE 0x71184 54089c78134cc54dff016c83367912eb055637fa50cAlan Cox#define DSPBLINOFF 0X71184 54189c78134cc54dff016c83367912eb055637fa50cAlan Cox#define DSPBADDR DSPBBASE 54289c78134cc54dff016c83367912eb055637fa50cAlan Cox#define DSPBSTRIDE 0x71188 54389c78134cc54dff016c83367912eb055637fa50cAlan Cox 54489c78134cc54dff016c83367912eb055637fa50cAlan Cox#define DSPCBASE 0x72184 54589c78134cc54dff016c83367912eb055637fa50cAlan Cox#define DSPCLINOFF 0x72184 54689c78134cc54dff016c83367912eb055637fa50cAlan Cox#define DSPCSTRIDE 0x72188 54789c78134cc54dff016c83367912eb055637fa50cAlan Cox 54889c78134cc54dff016c83367912eb055637fa50cAlan Cox#define DSPAKEYVAL 0x70194 54989c78134cc54dff016c83367912eb055637fa50cAlan Cox#define DSPAKEYMASK 0x70198 55089c78134cc54dff016c83367912eb055637fa50cAlan Cox 55189c78134cc54dff016c83367912eb055637fa50cAlan Cox#define DSPAPOS 0x7018C /* reserved */ 55289c78134cc54dff016c83367912eb055637fa50cAlan Cox#define DSPASIZE 0x70190 55389c78134cc54dff016c83367912eb055637fa50cAlan Cox#define DSPBPOS 0x7118C 55489c78134cc54dff016c83367912eb055637fa50cAlan Cox#define DSPBSIZE 0x71190 55589c78134cc54dff016c83367912eb055637fa50cAlan Cox#define DSPCPOS 0x7218C 55689c78134cc54dff016c83367912eb055637fa50cAlan Cox#define DSPCSIZE 0x72190 55789c78134cc54dff016c83367912eb055637fa50cAlan Cox 55889c78134cc54dff016c83367912eb055637fa50cAlan Cox#define DSPASURF 0x7019C 55989c78134cc54dff016c83367912eb055637fa50cAlan Cox#define DSPATILEOFF 0x701A4 56089c78134cc54dff016c83367912eb055637fa50cAlan Cox 56189c78134cc54dff016c83367912eb055637fa50cAlan Cox#define DSPBSURF 0x7119C 56289c78134cc54dff016c83367912eb055637fa50cAlan Cox#define DSPBTILEOFF 0x711A4 56389c78134cc54dff016c83367912eb055637fa50cAlan Cox 56489c78134cc54dff016c83367912eb055637fa50cAlan Cox#define DSPCSURF 0x7219C 56589c78134cc54dff016c83367912eb055637fa50cAlan Cox#define DSPCTILEOFF 0x721A4 56689c78134cc54dff016c83367912eb055637fa50cAlan Cox#define DSPCKEYMAXVAL 0x721A0 56789c78134cc54dff016c83367912eb055637fa50cAlan Cox#define DSPCKEYMINVAL 0x72194 56889c78134cc54dff016c83367912eb055637fa50cAlan Cox#define DSPCKEYMSK 0x72198 56989c78134cc54dff016c83367912eb055637fa50cAlan Cox 57089c78134cc54dff016c83367912eb055637fa50cAlan Cox#define VGACNTRL 0x71400 57189c78134cc54dff016c83367912eb055637fa50cAlan Cox#define VGA_DISP_DISABLE (1 << 31) 57289c78134cc54dff016c83367912eb055637fa50cAlan Cox#define VGA_2X_MODE (1 << 30) 57389c78134cc54dff016c83367912eb055637fa50cAlan Cox#define VGA_PIPE_B_SELECT (1 << 29) 57489c78134cc54dff016c83367912eb055637fa50cAlan Cox 57589c78134cc54dff016c83367912eb055637fa50cAlan Cox/* 57689c78134cc54dff016c83367912eb055637fa50cAlan Cox * Overlay registers 57789c78134cc54dff016c83367912eb055637fa50cAlan Cox */ 57889c78134cc54dff016c83367912eb055637fa50cAlan Cox#define OV_C_OFFSET 0x08000 57989c78134cc54dff016c83367912eb055637fa50cAlan Cox#define OV_OVADD 0x30000 58089c78134cc54dff016c83367912eb055637fa50cAlan Cox#define OV_DOVASTA 0x30008 58189c78134cc54dff016c83367912eb055637fa50cAlan Cox# define OV_PIPE_SELECT ((1 << 6)|(1 << 7)) 58289c78134cc54dff016c83367912eb055637fa50cAlan Cox# define OV_PIPE_SELECT_POS 6 58389c78134cc54dff016c83367912eb055637fa50cAlan Cox# define OV_PIPE_A 0 58489c78134cc54dff016c83367912eb055637fa50cAlan Cox# define OV_PIPE_C 1 58589c78134cc54dff016c83367912eb055637fa50cAlan Cox#define OV_OGAMC5 0x30010 58689c78134cc54dff016c83367912eb055637fa50cAlan Cox#define OV_OGAMC4 0x30014 58789c78134cc54dff016c83367912eb055637fa50cAlan Cox#define OV_OGAMC3 0x30018 58889c78134cc54dff016c83367912eb055637fa50cAlan Cox#define OV_OGAMC2 0x3001C 58989c78134cc54dff016c83367912eb055637fa50cAlan Cox#define OV_OGAMC1 0x30020 59089c78134cc54dff016c83367912eb055637fa50cAlan Cox#define OV_OGAMC0 0x30024 59189c78134cc54dff016c83367912eb055637fa50cAlan Cox#define OVC_OVADD 0x38000 59289c78134cc54dff016c83367912eb055637fa50cAlan Cox#define OVC_DOVCSTA 0x38008 59389c78134cc54dff016c83367912eb055637fa50cAlan Cox#define OVC_OGAMC5 0x38010 59489c78134cc54dff016c83367912eb055637fa50cAlan Cox#define OVC_OGAMC4 0x38014 59589c78134cc54dff016c83367912eb055637fa50cAlan Cox#define OVC_OGAMC3 0x38018 59689c78134cc54dff016c83367912eb055637fa50cAlan Cox#define OVC_OGAMC2 0x3801C 59789c78134cc54dff016c83367912eb055637fa50cAlan Cox#define OVC_OGAMC1 0x38020 59889c78134cc54dff016c83367912eb055637fa50cAlan Cox#define OVC_OGAMC0 0x38024 59989c78134cc54dff016c83367912eb055637fa50cAlan Cox 60089c78134cc54dff016c83367912eb055637fa50cAlan Cox/* 60189c78134cc54dff016c83367912eb055637fa50cAlan Cox * Some BIOS scratch area registers. The 845 (and 830?) store the amount 60289c78134cc54dff016c83367912eb055637fa50cAlan Cox * of video memory available to the BIOS in SWF1. 60389c78134cc54dff016c83367912eb055637fa50cAlan Cox */ 60489c78134cc54dff016c83367912eb055637fa50cAlan Cox#define SWF0 0x71410 60589c78134cc54dff016c83367912eb055637fa50cAlan Cox#define SWF1 0x71414 60689c78134cc54dff016c83367912eb055637fa50cAlan Cox#define SWF2 0x71418 60789c78134cc54dff016c83367912eb055637fa50cAlan Cox#define SWF3 0x7141c 60889c78134cc54dff016c83367912eb055637fa50cAlan Cox#define SWF4 0x71420 60989c78134cc54dff016c83367912eb055637fa50cAlan Cox#define SWF5 0x71424 61089c78134cc54dff016c83367912eb055637fa50cAlan Cox#define SWF6 0x71428 61189c78134cc54dff016c83367912eb055637fa50cAlan Cox 61289c78134cc54dff016c83367912eb055637fa50cAlan Cox/* 61389c78134cc54dff016c83367912eb055637fa50cAlan Cox * 855 scratch registers. 61489c78134cc54dff016c83367912eb055637fa50cAlan Cox */ 61589c78134cc54dff016c83367912eb055637fa50cAlan Cox#define SWF00 0x70410 61689c78134cc54dff016c83367912eb055637fa50cAlan Cox#define SWF01 0x70414 61789c78134cc54dff016c83367912eb055637fa50cAlan Cox#define SWF02 0x70418 61889c78134cc54dff016c83367912eb055637fa50cAlan Cox#define SWF03 0x7041c 61989c78134cc54dff016c83367912eb055637fa50cAlan Cox#define SWF04 0x70420 62089c78134cc54dff016c83367912eb055637fa50cAlan Cox#define SWF05 0x70424 62189c78134cc54dff016c83367912eb055637fa50cAlan Cox#define SWF06 0x70428 62289c78134cc54dff016c83367912eb055637fa50cAlan Cox 62389c78134cc54dff016c83367912eb055637fa50cAlan Cox#define SWF10 SWF0 62489c78134cc54dff016c83367912eb055637fa50cAlan Cox#define SWF11 SWF1 62589c78134cc54dff016c83367912eb055637fa50cAlan Cox#define SWF12 SWF2 62689c78134cc54dff016c83367912eb055637fa50cAlan Cox#define SWF13 SWF3 62789c78134cc54dff016c83367912eb055637fa50cAlan Cox#define SWF14 SWF4 62889c78134cc54dff016c83367912eb055637fa50cAlan Cox#define SWF15 SWF5 62989c78134cc54dff016c83367912eb055637fa50cAlan Cox#define SWF16 SWF6 63089c78134cc54dff016c83367912eb055637fa50cAlan Cox 63189c78134cc54dff016c83367912eb055637fa50cAlan Cox#define SWF30 0x72414 63289c78134cc54dff016c83367912eb055637fa50cAlan Cox#define SWF31 0x72418 63389c78134cc54dff016c83367912eb055637fa50cAlan Cox#define SWF32 0x7241c 63489c78134cc54dff016c83367912eb055637fa50cAlan Cox 63589c78134cc54dff016c83367912eb055637fa50cAlan Cox 63689c78134cc54dff016c83367912eb055637fa50cAlan Cox/* 63789c78134cc54dff016c83367912eb055637fa50cAlan Cox * Palette registers 63889c78134cc54dff016c83367912eb055637fa50cAlan Cox */ 63989c78134cc54dff016c83367912eb055637fa50cAlan Cox#define PALETTE_A 0x0a000 64089c78134cc54dff016c83367912eb055637fa50cAlan Cox#define PALETTE_B 0x0a800 64189c78134cc54dff016c83367912eb055637fa50cAlan Cox#define PALETTE_C 0x0ac00 64289c78134cc54dff016c83367912eb055637fa50cAlan Cox 64389c78134cc54dff016c83367912eb055637fa50cAlan Cox/* Cursor A & B regs */ 64489c78134cc54dff016c83367912eb055637fa50cAlan Cox#define CURACNTR 0x70080 64589c78134cc54dff016c83367912eb055637fa50cAlan Cox#define CURSOR_MODE_DISABLE 0x00 64689c78134cc54dff016c83367912eb055637fa50cAlan Cox#define CURSOR_MODE_64_32B_AX 0x07 64789c78134cc54dff016c83367912eb055637fa50cAlan Cox#define CURSOR_MODE_64_ARGB_AX ((1 << 5) | CURSOR_MODE_64_32B_AX) 64889c78134cc54dff016c83367912eb055637fa50cAlan Cox#define MCURSOR_GAMMA_ENABLE (1 << 26) 64989c78134cc54dff016c83367912eb055637fa50cAlan Cox#define CURABASE 0x70084 65089c78134cc54dff016c83367912eb055637fa50cAlan Cox#define CURAPOS 0x70088 65189c78134cc54dff016c83367912eb055637fa50cAlan Cox#define CURSOR_POS_MASK 0x007FF 65289c78134cc54dff016c83367912eb055637fa50cAlan Cox#define CURSOR_POS_SIGN 0x8000 65389c78134cc54dff016c83367912eb055637fa50cAlan Cox#define CURSOR_X_SHIFT 0 65489c78134cc54dff016c83367912eb055637fa50cAlan Cox#define CURSOR_Y_SHIFT 16 65589c78134cc54dff016c83367912eb055637fa50cAlan Cox#define CURBCNTR 0x700c0 65689c78134cc54dff016c83367912eb055637fa50cAlan Cox#define CURBBASE 0x700c4 65789c78134cc54dff016c83367912eb055637fa50cAlan Cox#define CURBPOS 0x700c8 65889c78134cc54dff016c83367912eb055637fa50cAlan Cox#define CURCCNTR 0x700e0 65989c78134cc54dff016c83367912eb055637fa50cAlan Cox#define CURCBASE 0x700e4 66089c78134cc54dff016c83367912eb055637fa50cAlan Cox#define CURCPOS 0x700e8 66189c78134cc54dff016c83367912eb055637fa50cAlan Cox 66289c78134cc54dff016c83367912eb055637fa50cAlan Cox/* 66389c78134cc54dff016c83367912eb055637fa50cAlan Cox * Interrupt Registers 66489c78134cc54dff016c83367912eb055637fa50cAlan Cox */ 66589c78134cc54dff016c83367912eb055637fa50cAlan Cox#define IER 0x020a0 66689c78134cc54dff016c83367912eb055637fa50cAlan Cox#define IIR 0x020a4 66789c78134cc54dff016c83367912eb055637fa50cAlan Cox#define IMR 0x020a8 66889c78134cc54dff016c83367912eb055637fa50cAlan Cox#define ISR 0x020ac 66989c78134cc54dff016c83367912eb055637fa50cAlan Cox 67089c78134cc54dff016c83367912eb055637fa50cAlan Cox/* 67189c78134cc54dff016c83367912eb055637fa50cAlan Cox * MOORESTOWN delta registers 67289c78134cc54dff016c83367912eb055637fa50cAlan Cox */ 67389c78134cc54dff016c83367912eb055637fa50cAlan Cox#define MRST_DPLL_A 0x0f014 67489c78134cc54dff016c83367912eb055637fa50cAlan Cox#define MDFLD_DPLL_B 0x0f018 67589c78134cc54dff016c83367912eb055637fa50cAlan Cox#define MDFLD_INPUT_REF_SEL (1 << 14) 67689c78134cc54dff016c83367912eb055637fa50cAlan Cox#define MDFLD_VCO_SEL (1 << 16) 67789c78134cc54dff016c83367912eb055637fa50cAlan Cox#define DPLLA_MODE_LVDS (2 << 26) /* mrst */ 67889c78134cc54dff016c83367912eb055637fa50cAlan Cox#define MDFLD_PLL_LATCHEN (1 << 28) 67989c78134cc54dff016c83367912eb055637fa50cAlan Cox#define MDFLD_PWR_GATE_EN (1 << 30) 68089c78134cc54dff016c83367912eb055637fa50cAlan Cox#define MDFLD_P1_MASK (0x1FF << 17) 68189c78134cc54dff016c83367912eb055637fa50cAlan Cox#define MRST_FPA0 0x0f040 68289c78134cc54dff016c83367912eb055637fa50cAlan Cox#define MRST_FPA1 0x0f044 68389c78134cc54dff016c83367912eb055637fa50cAlan Cox#define MDFLD_DPLL_DIV0 0x0f048 68489c78134cc54dff016c83367912eb055637fa50cAlan Cox#define MDFLD_DPLL_DIV1 0x0f04c 68589c78134cc54dff016c83367912eb055637fa50cAlan Cox#define MRST_PERF_MODE 0x020f4 68689c78134cc54dff016c83367912eb055637fa50cAlan Cox 68789c78134cc54dff016c83367912eb055637fa50cAlan Cox/* 68889c78134cc54dff016c83367912eb055637fa50cAlan Cox * MEDFIELD HDMI registers 68989c78134cc54dff016c83367912eb055637fa50cAlan Cox */ 69089c78134cc54dff016c83367912eb055637fa50cAlan Cox#define HDMIPHYMISCCTL 0x61134 69189c78134cc54dff016c83367912eb055637fa50cAlan Cox#define HDMI_PHY_POWER_DOWN 0x7f 69289c78134cc54dff016c83367912eb055637fa50cAlan Cox#define HDMIB_CONTROL 0x61140 69389c78134cc54dff016c83367912eb055637fa50cAlan Cox#define HDMIB_PORT_EN (1 << 31) 69489c78134cc54dff016c83367912eb055637fa50cAlan Cox#define HDMIB_PIPE_B_SELECT (1 << 30) 69589c78134cc54dff016c83367912eb055637fa50cAlan Cox#define HDMIB_NULL_PACKET (1 << 9) 69689c78134cc54dff016c83367912eb055637fa50cAlan Cox#define HDMIB_HDCP_PORT (1 << 5) 69789c78134cc54dff016c83367912eb055637fa50cAlan Cox 69889c78134cc54dff016c83367912eb055637fa50cAlan Cox/* #define LVDS 0x61180 */ 69989c78134cc54dff016c83367912eb055637fa50cAlan Cox#define MRST_PANEL_8TO6_DITHER_ENABLE (1 << 25) 70089c78134cc54dff016c83367912eb055637fa50cAlan Cox#define MRST_PANEL_24_DOT_1_FORMAT (1 << 24) 70189c78134cc54dff016c83367912eb055637fa50cAlan Cox#define LVDS_A3_POWER_UP_0_OUTPUT (1 << 6) 70289c78134cc54dff016c83367912eb055637fa50cAlan Cox 70389c78134cc54dff016c83367912eb055637fa50cAlan Cox#define MIPI 0x61190 70489c78134cc54dff016c83367912eb055637fa50cAlan Cox#define MIPI_C 0x62190 70589c78134cc54dff016c83367912eb055637fa50cAlan Cox#define MIPI_PORT_EN (1 << 31) 70689c78134cc54dff016c83367912eb055637fa50cAlan Cox/* Turns on border drawing to allow centered display. */ 70789c78134cc54dff016c83367912eb055637fa50cAlan Cox#define SEL_FLOPPED_HSTX (1 << 23) 70889c78134cc54dff016c83367912eb055637fa50cAlan Cox#define PASS_FROM_SPHY_TO_AFE (1 << 16) 70989c78134cc54dff016c83367912eb055637fa50cAlan Cox#define MIPI_BORDER_EN (1 << 15) 71089c78134cc54dff016c83367912eb055637fa50cAlan Cox#define MIPIA_3LANE_MIPIC_1LANE 0x1 71189c78134cc54dff016c83367912eb055637fa50cAlan Cox#define MIPIA_2LANE_MIPIC_2LANE 0x2 71289c78134cc54dff016c83367912eb055637fa50cAlan Cox#define TE_TRIGGER_DSI_PROTOCOL (1 << 2) 71389c78134cc54dff016c83367912eb055637fa50cAlan Cox#define TE_TRIGGER_GPIO_PIN (1 << 3) 71489c78134cc54dff016c83367912eb055637fa50cAlan Cox#define MIPI_TE_COUNT 0x61194 71589c78134cc54dff016c83367912eb055637fa50cAlan Cox 71689c78134cc54dff016c83367912eb055637fa50cAlan Cox/* #define PP_CONTROL 0x61204 */ 71789c78134cc54dff016c83367912eb055637fa50cAlan Cox#define POWER_DOWN_ON_RESET (1 << 1) 71889c78134cc54dff016c83367912eb055637fa50cAlan Cox 71989c78134cc54dff016c83367912eb055637fa50cAlan Cox/* #define PFIT_CONTROL 0x61230 */ 72089c78134cc54dff016c83367912eb055637fa50cAlan Cox#define PFIT_PIPE_SELECT (3 << 29) 72189c78134cc54dff016c83367912eb055637fa50cAlan Cox#define PFIT_PIPE_SELECT_SHIFT (29) 72289c78134cc54dff016c83367912eb055637fa50cAlan Cox 72389c78134cc54dff016c83367912eb055637fa50cAlan Cox/* #define BLC_PWM_CTL 0x61254 */ 72489c78134cc54dff016c83367912eb055637fa50cAlan Cox#define MRST_BACKLIGHT_MODULATION_FREQ_SHIFT (16) 72589c78134cc54dff016c83367912eb055637fa50cAlan Cox#define MRST_BACKLIGHT_MODULATION_FREQ_MASK (0xffff << 16) 72689c78134cc54dff016c83367912eb055637fa50cAlan Cox 72789c78134cc54dff016c83367912eb055637fa50cAlan Cox/* #define PIPEACONF 0x70008 */ 72889c78134cc54dff016c83367912eb055637fa50cAlan Cox#define PIPEACONF_PIPE_STATE (1 << 30) 72989c78134cc54dff016c83367912eb055637fa50cAlan Cox/* #define DSPACNTR 0x70180 */ 73089c78134cc54dff016c83367912eb055637fa50cAlan Cox 73189c78134cc54dff016c83367912eb055637fa50cAlan Cox#define MRST_DSPABASE 0x7019c 73289c78134cc54dff016c83367912eb055637fa50cAlan Cox#define MRST_DSPBBASE 0x7119c 73389c78134cc54dff016c83367912eb055637fa50cAlan Cox#define MDFLD_DSPCBASE 0x7219c 73489c78134cc54dff016c83367912eb055637fa50cAlan Cox 73589c78134cc54dff016c83367912eb055637fa50cAlan Cox/* 73689c78134cc54dff016c83367912eb055637fa50cAlan Cox * Moorestown registers. 73789c78134cc54dff016c83367912eb055637fa50cAlan Cox */ 73889c78134cc54dff016c83367912eb055637fa50cAlan Cox 73989c78134cc54dff016c83367912eb055637fa50cAlan Cox/* 74089c78134cc54dff016c83367912eb055637fa50cAlan Cox * MIPI IP registers 74189c78134cc54dff016c83367912eb055637fa50cAlan Cox */ 74289c78134cc54dff016c83367912eb055637fa50cAlan Cox#define MIPIC_REG_OFFSET 0x800 74389c78134cc54dff016c83367912eb055637fa50cAlan Cox 74489c78134cc54dff016c83367912eb055637fa50cAlan Cox#define DEVICE_READY_REG 0xb000 74589c78134cc54dff016c83367912eb055637fa50cAlan Cox#define LP_OUTPUT_HOLD (1 << 16) 74689c78134cc54dff016c83367912eb055637fa50cAlan Cox#define EXIT_ULPS_DEV_READY 0x3 74789c78134cc54dff016c83367912eb055637fa50cAlan Cox#define LP_OUTPUT_HOLD_RELEASE 0x810000 74889c78134cc54dff016c83367912eb055637fa50cAlan Cox# define ENTERING_ULPS (2 << 1) 74989c78134cc54dff016c83367912eb055637fa50cAlan Cox# define EXITING_ULPS (1 << 1) 75089c78134cc54dff016c83367912eb055637fa50cAlan Cox# define ULPS_MASK (3 << 1) 75189c78134cc54dff016c83367912eb055637fa50cAlan Cox# define BUS_POSSESSION (1 << 3) 75289c78134cc54dff016c83367912eb055637fa50cAlan Cox#define INTR_STAT_REG 0xb004 75389c78134cc54dff016c83367912eb055637fa50cAlan Cox#define RX_SOT_ERROR (1 << 0) 75489c78134cc54dff016c83367912eb055637fa50cAlan Cox#define RX_SOT_SYNC_ERROR (1 << 1) 75589c78134cc54dff016c83367912eb055637fa50cAlan Cox#define RX_ESCAPE_MODE_ENTRY_ERROR (1 << 3) 75689c78134cc54dff016c83367912eb055637fa50cAlan Cox#define RX_LP_TX_SYNC_ERROR (1 << 4) 75789c78134cc54dff016c83367912eb055637fa50cAlan Cox#define RX_HS_RECEIVE_TIMEOUT_ERROR (1 << 5) 75889c78134cc54dff016c83367912eb055637fa50cAlan Cox#define RX_FALSE_CONTROL_ERROR (1 << 6) 75989c78134cc54dff016c83367912eb055637fa50cAlan Cox#define RX_ECC_SINGLE_BIT_ERROR (1 << 7) 76089c78134cc54dff016c83367912eb055637fa50cAlan Cox#define RX_ECC_MULTI_BIT_ERROR (1 << 8) 76189c78134cc54dff016c83367912eb055637fa50cAlan Cox#define RX_CHECKSUM_ERROR (1 << 9) 76289c78134cc54dff016c83367912eb055637fa50cAlan Cox#define RX_DSI_DATA_TYPE_NOT_RECOGNIZED (1 << 10) 76389c78134cc54dff016c83367912eb055637fa50cAlan Cox#define RX_DSI_VC_ID_INVALID (1 << 11) 76489c78134cc54dff016c83367912eb055637fa50cAlan Cox#define TX_FALSE_CONTROL_ERROR (1 << 12) 76589c78134cc54dff016c83367912eb055637fa50cAlan Cox#define TX_ECC_SINGLE_BIT_ERROR (1 << 13) 76689c78134cc54dff016c83367912eb055637fa50cAlan Cox#define TX_ECC_MULTI_BIT_ERROR (1 << 14) 76789c78134cc54dff016c83367912eb055637fa50cAlan Cox#define TX_CHECKSUM_ERROR (1 << 15) 76889c78134cc54dff016c83367912eb055637fa50cAlan Cox#define TX_DSI_DATA_TYPE_NOT_RECOGNIZED (1 << 16) 76989c78134cc54dff016c83367912eb055637fa50cAlan Cox#define TX_DSI_VC_ID_INVALID (1 << 17) 77089c78134cc54dff016c83367912eb055637fa50cAlan Cox#define HIGH_CONTENTION (1 << 18) 77189c78134cc54dff016c83367912eb055637fa50cAlan Cox#define LOW_CONTENTION (1 << 19) 77289c78134cc54dff016c83367912eb055637fa50cAlan Cox#define DPI_FIFO_UNDER_RUN (1 << 20) 77389c78134cc54dff016c83367912eb055637fa50cAlan Cox#define HS_TX_TIMEOUT (1 << 21) 77489c78134cc54dff016c83367912eb055637fa50cAlan Cox#define LP_RX_TIMEOUT (1 << 22) 77589c78134cc54dff016c83367912eb055637fa50cAlan Cox#define TURN_AROUND_ACK_TIMEOUT (1 << 23) 77689c78134cc54dff016c83367912eb055637fa50cAlan Cox#define ACK_WITH_NO_ERROR (1 << 24) 77789c78134cc54dff016c83367912eb055637fa50cAlan Cox#define HS_GENERIC_WR_FIFO_FULL (1 << 27) 77889c78134cc54dff016c83367912eb055637fa50cAlan Cox#define LP_GENERIC_WR_FIFO_FULL (1 << 28) 77989c78134cc54dff016c83367912eb055637fa50cAlan Cox#define SPL_PKT_SENT (1 << 30) 78089c78134cc54dff016c83367912eb055637fa50cAlan Cox#define INTR_EN_REG 0xb008 78189c78134cc54dff016c83367912eb055637fa50cAlan Cox#define DSI_FUNC_PRG_REG 0xb00c 78289c78134cc54dff016c83367912eb055637fa50cAlan Cox#define DPI_CHANNEL_NUMBER_POS 0x03 78389c78134cc54dff016c83367912eb055637fa50cAlan Cox#define DBI_CHANNEL_NUMBER_POS 0x05 78489c78134cc54dff016c83367912eb055637fa50cAlan Cox#define FMT_DPI_POS 0x07 78589c78134cc54dff016c83367912eb055637fa50cAlan Cox#define FMT_DBI_POS 0x0A 78689c78134cc54dff016c83367912eb055637fa50cAlan Cox#define DBI_DATA_WIDTH_POS 0x0D 78789c78134cc54dff016c83367912eb055637fa50cAlan Cox 78889c78134cc54dff016c83367912eb055637fa50cAlan Cox/* DPI PIXEL FORMATS */ 78989c78134cc54dff016c83367912eb055637fa50cAlan Cox#define RGB_565_FMT 0x01 /* RGB 565 FORMAT */ 79089c78134cc54dff016c83367912eb055637fa50cAlan Cox#define RGB_666_FMT 0x02 /* RGB 666 FORMAT */ 79189c78134cc54dff016c83367912eb055637fa50cAlan Cox#define LRGB_666_FMT 0x03 /* RGB LOOSELY PACKED 79289c78134cc54dff016c83367912eb055637fa50cAlan Cox * 666 FORMAT 79389c78134cc54dff016c83367912eb055637fa50cAlan Cox */ 79489c78134cc54dff016c83367912eb055637fa50cAlan Cox#define RGB_888_FMT 0x04 /* RGB 888 FORMAT */ 79589c78134cc54dff016c83367912eb055637fa50cAlan Cox#define VIRTUAL_CHANNEL_NUMBER_0 0x00 /* Virtual channel 0 */ 79689c78134cc54dff016c83367912eb055637fa50cAlan Cox#define VIRTUAL_CHANNEL_NUMBER_1 0x01 /* Virtual channel 1 */ 79789c78134cc54dff016c83367912eb055637fa50cAlan Cox#define VIRTUAL_CHANNEL_NUMBER_2 0x02 /* Virtual channel 2 */ 79889c78134cc54dff016c83367912eb055637fa50cAlan Cox#define VIRTUAL_CHANNEL_NUMBER_3 0x03 /* Virtual channel 3 */ 79989c78134cc54dff016c83367912eb055637fa50cAlan Cox 80089c78134cc54dff016c83367912eb055637fa50cAlan Cox#define DBI_NOT_SUPPORTED 0x00 /* command mode 80189c78134cc54dff016c83367912eb055637fa50cAlan Cox * is not supported 80289c78134cc54dff016c83367912eb055637fa50cAlan Cox */ 80389c78134cc54dff016c83367912eb055637fa50cAlan Cox#define DBI_DATA_WIDTH_16BIT 0x01 /* 16 bit data */ 80489c78134cc54dff016c83367912eb055637fa50cAlan Cox#define DBI_DATA_WIDTH_9BIT 0x02 /* 9 bit data */ 80589c78134cc54dff016c83367912eb055637fa50cAlan Cox#define DBI_DATA_WIDTH_8BIT 0x03 /* 8 bit data */ 80689c78134cc54dff016c83367912eb055637fa50cAlan Cox#define DBI_DATA_WIDTH_OPT1 0x04 /* option 1 */ 80789c78134cc54dff016c83367912eb055637fa50cAlan Cox#define DBI_DATA_WIDTH_OPT2 0x05 /* option 2 */ 80889c78134cc54dff016c83367912eb055637fa50cAlan Cox 80989c78134cc54dff016c83367912eb055637fa50cAlan Cox#define HS_TX_TIMEOUT_REG 0xb010 81089c78134cc54dff016c83367912eb055637fa50cAlan Cox#define LP_RX_TIMEOUT_REG 0xb014 81189c78134cc54dff016c83367912eb055637fa50cAlan Cox#define TURN_AROUND_TIMEOUT_REG 0xb018 81289c78134cc54dff016c83367912eb055637fa50cAlan Cox#define DEVICE_RESET_REG 0xb01C 81389c78134cc54dff016c83367912eb055637fa50cAlan Cox#define DPI_RESOLUTION_REG 0xb020 81489c78134cc54dff016c83367912eb055637fa50cAlan Cox#define RES_V_POS 0x10 81589c78134cc54dff016c83367912eb055637fa50cAlan Cox#define DBI_RESOLUTION_REG 0xb024 /* Reserved for MDFLD */ 81689c78134cc54dff016c83367912eb055637fa50cAlan Cox#define HORIZ_SYNC_PAD_COUNT_REG 0xb028 81789c78134cc54dff016c83367912eb055637fa50cAlan Cox#define HORIZ_BACK_PORCH_COUNT_REG 0xb02C 81889c78134cc54dff016c83367912eb055637fa50cAlan Cox#define HORIZ_FRONT_PORCH_COUNT_REG 0xb030 81989c78134cc54dff016c83367912eb055637fa50cAlan Cox#define HORIZ_ACTIVE_AREA_COUNT_REG 0xb034 82089c78134cc54dff016c83367912eb055637fa50cAlan Cox#define VERT_SYNC_PAD_COUNT_REG 0xb038 82189c78134cc54dff016c83367912eb055637fa50cAlan Cox#define VERT_BACK_PORCH_COUNT_REG 0xb03c 82289c78134cc54dff016c83367912eb055637fa50cAlan Cox#define VERT_FRONT_PORCH_COUNT_REG 0xb040 82389c78134cc54dff016c83367912eb055637fa50cAlan Cox#define HIGH_LOW_SWITCH_COUNT_REG 0xb044 82489c78134cc54dff016c83367912eb055637fa50cAlan Cox#define DPI_CONTROL_REG 0xb048 82589c78134cc54dff016c83367912eb055637fa50cAlan Cox#define DPI_SHUT_DOWN (1 << 0) 82689c78134cc54dff016c83367912eb055637fa50cAlan Cox#define DPI_TURN_ON (1 << 1) 82789c78134cc54dff016c83367912eb055637fa50cAlan Cox#define DPI_COLOR_MODE_ON (1 << 2) 82889c78134cc54dff016c83367912eb055637fa50cAlan Cox#define DPI_COLOR_MODE_OFF (1 << 3) 82989c78134cc54dff016c83367912eb055637fa50cAlan Cox#define DPI_BACK_LIGHT_ON (1 << 4) 83089c78134cc54dff016c83367912eb055637fa50cAlan Cox#define DPI_BACK_LIGHT_OFF (1 << 5) 83189c78134cc54dff016c83367912eb055637fa50cAlan Cox#define DPI_LP (1 << 6) 83289c78134cc54dff016c83367912eb055637fa50cAlan Cox#define DPI_DATA_REG 0xb04c 83389c78134cc54dff016c83367912eb055637fa50cAlan Cox#define DPI_BACK_LIGHT_ON_DATA 0x07 83489c78134cc54dff016c83367912eb055637fa50cAlan Cox#define DPI_BACK_LIGHT_OFF_DATA 0x17 83589c78134cc54dff016c83367912eb055637fa50cAlan Cox#define INIT_COUNT_REG 0xb050 83689c78134cc54dff016c83367912eb055637fa50cAlan Cox#define MAX_RET_PAK_REG 0xb054 83789c78134cc54dff016c83367912eb055637fa50cAlan Cox#define VIDEO_FMT_REG 0xb058 83889c78134cc54dff016c83367912eb055637fa50cAlan Cox#define COMPLETE_LAST_PCKT (1 << 2) 83989c78134cc54dff016c83367912eb055637fa50cAlan Cox#define EOT_DISABLE_REG 0xb05c 84089c78134cc54dff016c83367912eb055637fa50cAlan Cox#define ENABLE_CLOCK_STOPPING (1 << 1) 84189c78134cc54dff016c83367912eb055637fa50cAlan Cox#define LP_BYTECLK_REG 0xb060 84289c78134cc54dff016c83367912eb055637fa50cAlan Cox#define LP_GEN_DATA_REG 0xb064 84389c78134cc54dff016c83367912eb055637fa50cAlan Cox#define HS_GEN_DATA_REG 0xb068 84489c78134cc54dff016c83367912eb055637fa50cAlan Cox#define LP_GEN_CTRL_REG 0xb06C 84589c78134cc54dff016c83367912eb055637fa50cAlan Cox#define HS_GEN_CTRL_REG 0xb070 84689c78134cc54dff016c83367912eb055637fa50cAlan Cox#define DCS_CHANNEL_NUMBER_POS 0x6 84789c78134cc54dff016c83367912eb055637fa50cAlan Cox#define MCS_COMMANDS_POS 0x8 84889c78134cc54dff016c83367912eb055637fa50cAlan Cox#define WORD_COUNTS_POS 0x8 84989c78134cc54dff016c83367912eb055637fa50cAlan Cox#define MCS_PARAMETER_POS 0x10 85089c78134cc54dff016c83367912eb055637fa50cAlan Cox#define GEN_FIFO_STAT_REG 0xb074 85189c78134cc54dff016c83367912eb055637fa50cAlan Cox#define HS_DATA_FIFO_FULL (1 << 0) 85289c78134cc54dff016c83367912eb055637fa50cAlan Cox#define HS_DATA_FIFO_HALF_EMPTY (1 << 1) 85389c78134cc54dff016c83367912eb055637fa50cAlan Cox#define HS_DATA_FIFO_EMPTY (1 << 2) 85489c78134cc54dff016c83367912eb055637fa50cAlan Cox#define LP_DATA_FIFO_FULL (1 << 8) 85589c78134cc54dff016c83367912eb055637fa50cAlan Cox#define LP_DATA_FIFO_HALF_EMPTY (1 << 9) 85689c78134cc54dff016c83367912eb055637fa50cAlan Cox#define LP_DATA_FIFO_EMPTY (1 << 10) 85789c78134cc54dff016c83367912eb055637fa50cAlan Cox#define HS_CTRL_FIFO_FULL (1 << 16) 85889c78134cc54dff016c83367912eb055637fa50cAlan Cox#define HS_CTRL_FIFO_HALF_EMPTY (1 << 17) 85989c78134cc54dff016c83367912eb055637fa50cAlan Cox#define HS_CTRL_FIFO_EMPTY (1 << 18) 86089c78134cc54dff016c83367912eb055637fa50cAlan Cox#define LP_CTRL_FIFO_FULL (1 << 24) 86189c78134cc54dff016c83367912eb055637fa50cAlan Cox#define LP_CTRL_FIFO_HALF_EMPTY (1 << 25) 86289c78134cc54dff016c83367912eb055637fa50cAlan Cox#define LP_CTRL_FIFO_EMPTY (1 << 26) 86389c78134cc54dff016c83367912eb055637fa50cAlan Cox#define DBI_FIFO_EMPTY (1 << 27) 86489c78134cc54dff016c83367912eb055637fa50cAlan Cox#define DPI_FIFO_EMPTY (1 << 28) 86589c78134cc54dff016c83367912eb055637fa50cAlan Cox#define HS_LS_DBI_ENABLE_REG 0xb078 86689c78134cc54dff016c83367912eb055637fa50cAlan Cox#define TXCLKESC_REG 0xb07c 86789c78134cc54dff016c83367912eb055637fa50cAlan Cox#define DPHY_PARAM_REG 0xb080 86889c78134cc54dff016c83367912eb055637fa50cAlan Cox#define DBI_BW_CTRL_REG 0xb084 86989c78134cc54dff016c83367912eb055637fa50cAlan Cox#define CLK_LANE_SWT_REG 0xb088 87089c78134cc54dff016c83367912eb055637fa50cAlan Cox 87189c78134cc54dff016c83367912eb055637fa50cAlan Cox/* 87289c78134cc54dff016c83367912eb055637fa50cAlan Cox * MIPI Adapter registers 87389c78134cc54dff016c83367912eb055637fa50cAlan Cox */ 87489c78134cc54dff016c83367912eb055637fa50cAlan Cox#define MIPI_CONTROL_REG 0xb104 87589c78134cc54dff016c83367912eb055637fa50cAlan Cox#define MIPI_2X_CLOCK_BITS ((1 << 0) | (1 << 1)) 87689c78134cc54dff016c83367912eb055637fa50cAlan Cox#define MIPI_DATA_ADDRESS_REG 0xb108 87789c78134cc54dff016c83367912eb055637fa50cAlan Cox#define MIPI_DATA_LENGTH_REG 0xb10C 87889c78134cc54dff016c83367912eb055637fa50cAlan Cox#define MIPI_COMMAND_ADDRESS_REG 0xb110 87989c78134cc54dff016c83367912eb055637fa50cAlan Cox#define MIPI_COMMAND_LENGTH_REG 0xb114 88089c78134cc54dff016c83367912eb055637fa50cAlan Cox#define MIPI_READ_DATA_RETURN_REG0 0xb118 88189c78134cc54dff016c83367912eb055637fa50cAlan Cox#define MIPI_READ_DATA_RETURN_REG1 0xb11C 88289c78134cc54dff016c83367912eb055637fa50cAlan Cox#define MIPI_READ_DATA_RETURN_REG2 0xb120 88389c78134cc54dff016c83367912eb055637fa50cAlan Cox#define MIPI_READ_DATA_RETURN_REG3 0xb124 88489c78134cc54dff016c83367912eb055637fa50cAlan Cox#define MIPI_READ_DATA_RETURN_REG4 0xb128 88589c78134cc54dff016c83367912eb055637fa50cAlan Cox#define MIPI_READ_DATA_RETURN_REG5 0xb12C 88689c78134cc54dff016c83367912eb055637fa50cAlan Cox#define MIPI_READ_DATA_RETURN_REG6 0xb130 88789c78134cc54dff016c83367912eb055637fa50cAlan Cox#define MIPI_READ_DATA_RETURN_REG7 0xb134 88889c78134cc54dff016c83367912eb055637fa50cAlan Cox#define MIPI_READ_DATA_VALID_REG 0xb138 88989c78134cc54dff016c83367912eb055637fa50cAlan Cox 89089c78134cc54dff016c83367912eb055637fa50cAlan Cox/* DBI COMMANDS */ 89189c78134cc54dff016c83367912eb055637fa50cAlan Cox#define soft_reset 0x01 89289c78134cc54dff016c83367912eb055637fa50cAlan Cox/* 89389c78134cc54dff016c83367912eb055637fa50cAlan Cox * The display module performs a software reset. 89489c78134cc54dff016c83367912eb055637fa50cAlan Cox * Registers are written with their SW Reset default values. 89589c78134cc54dff016c83367912eb055637fa50cAlan Cox */ 89689c78134cc54dff016c83367912eb055637fa50cAlan Cox#define get_power_mode 0x0a 89789c78134cc54dff016c83367912eb055637fa50cAlan Cox/* 89889c78134cc54dff016c83367912eb055637fa50cAlan Cox * The display module returns the current power mode 89989c78134cc54dff016c83367912eb055637fa50cAlan Cox */ 90089c78134cc54dff016c83367912eb055637fa50cAlan Cox#define get_address_mode 0x0b 90189c78134cc54dff016c83367912eb055637fa50cAlan Cox/* 90289c78134cc54dff016c83367912eb055637fa50cAlan Cox * The display module returns the current status. 90389c78134cc54dff016c83367912eb055637fa50cAlan Cox */ 90489c78134cc54dff016c83367912eb055637fa50cAlan Cox#define get_pixel_format 0x0c 90589c78134cc54dff016c83367912eb055637fa50cAlan Cox/* 90689c78134cc54dff016c83367912eb055637fa50cAlan Cox * This command gets the pixel format for the RGB image data 90789c78134cc54dff016c83367912eb055637fa50cAlan Cox * used by the interface. 90889c78134cc54dff016c83367912eb055637fa50cAlan Cox */ 90989c78134cc54dff016c83367912eb055637fa50cAlan Cox#define get_display_mode 0x0d 91089c78134cc54dff016c83367912eb055637fa50cAlan Cox/* 91189c78134cc54dff016c83367912eb055637fa50cAlan Cox * The display module returns the Display Image Mode status. 91289c78134cc54dff016c83367912eb055637fa50cAlan Cox */ 91389c78134cc54dff016c83367912eb055637fa50cAlan Cox#define get_signal_mode 0x0e 91489c78134cc54dff016c83367912eb055637fa50cAlan Cox/* 91589c78134cc54dff016c83367912eb055637fa50cAlan Cox * The display module returns the Display Signal Mode. 91689c78134cc54dff016c83367912eb055637fa50cAlan Cox */ 91789c78134cc54dff016c83367912eb055637fa50cAlan Cox#define get_diagnostic_result 0x0f 91889c78134cc54dff016c83367912eb055637fa50cAlan Cox/* 91989c78134cc54dff016c83367912eb055637fa50cAlan Cox * The display module returns the self-diagnostic results following 92089c78134cc54dff016c83367912eb055637fa50cAlan Cox * a Sleep Out command. 92189c78134cc54dff016c83367912eb055637fa50cAlan Cox */ 92289c78134cc54dff016c83367912eb055637fa50cAlan Cox#define enter_sleep_mode 0x10 92389c78134cc54dff016c83367912eb055637fa50cAlan Cox/* 92489c78134cc54dff016c83367912eb055637fa50cAlan Cox * This command causes the display module to enter the Sleep mode. 92589c78134cc54dff016c83367912eb055637fa50cAlan Cox * In this mode, all unnecessary blocks inside the display module are 92689c78134cc54dff016c83367912eb055637fa50cAlan Cox * disabled except interface communication. This is the lowest power 92789c78134cc54dff016c83367912eb055637fa50cAlan Cox * mode the display module supports. 92889c78134cc54dff016c83367912eb055637fa50cAlan Cox */ 92989c78134cc54dff016c83367912eb055637fa50cAlan Cox#define exit_sleep_mode 0x11 93089c78134cc54dff016c83367912eb055637fa50cAlan Cox/* 93189c78134cc54dff016c83367912eb055637fa50cAlan Cox * This command causes the display module to exit Sleep mode. 93289c78134cc54dff016c83367912eb055637fa50cAlan Cox * All blocks inside the display module are enabled. 93389c78134cc54dff016c83367912eb055637fa50cAlan Cox */ 93489c78134cc54dff016c83367912eb055637fa50cAlan Cox#define enter_partial_mode 0x12 93589c78134cc54dff016c83367912eb055637fa50cAlan Cox/* 93689c78134cc54dff016c83367912eb055637fa50cAlan Cox * This command causes the display module to enter the Partial Display 93789c78134cc54dff016c83367912eb055637fa50cAlan Cox * Mode. The Partial Display Mode window is described by the 93889c78134cc54dff016c83367912eb055637fa50cAlan Cox * set_partial_area command. 93989c78134cc54dff016c83367912eb055637fa50cAlan Cox */ 94089c78134cc54dff016c83367912eb055637fa50cAlan Cox#define enter_normal_mode 0x13 94189c78134cc54dff016c83367912eb055637fa50cAlan Cox/* 94289c78134cc54dff016c83367912eb055637fa50cAlan Cox * This command causes the display module to enter the Normal mode. 94389c78134cc54dff016c83367912eb055637fa50cAlan Cox * Normal Mode is defined as Partial Display mode and Scroll mode are off 94489c78134cc54dff016c83367912eb055637fa50cAlan Cox */ 94589c78134cc54dff016c83367912eb055637fa50cAlan Cox#define exit_invert_mode 0x20 94689c78134cc54dff016c83367912eb055637fa50cAlan Cox/* 94789c78134cc54dff016c83367912eb055637fa50cAlan Cox * This command causes the display module to stop inverting the image 94889c78134cc54dff016c83367912eb055637fa50cAlan Cox * data on the display device. The frame memory contents remain unchanged. 94989c78134cc54dff016c83367912eb055637fa50cAlan Cox * No status bits are changed. 95089c78134cc54dff016c83367912eb055637fa50cAlan Cox */ 95189c78134cc54dff016c83367912eb055637fa50cAlan Cox#define enter_invert_mode 0x21 95289c78134cc54dff016c83367912eb055637fa50cAlan Cox/* 95389c78134cc54dff016c83367912eb055637fa50cAlan Cox * This command causes the display module to invert the image data only on 95489c78134cc54dff016c83367912eb055637fa50cAlan Cox * the display device. The frame memory contents remain unchanged. 95589c78134cc54dff016c83367912eb055637fa50cAlan Cox * No status bits are changed. 95689c78134cc54dff016c83367912eb055637fa50cAlan Cox */ 95789c78134cc54dff016c83367912eb055637fa50cAlan Cox#define set_gamma_curve 0x26 95889c78134cc54dff016c83367912eb055637fa50cAlan Cox/* 95989c78134cc54dff016c83367912eb055637fa50cAlan Cox * This command selects the desired gamma curve for the display device. 96089c78134cc54dff016c83367912eb055637fa50cAlan Cox * Four fixed gamma curves are defined in section DCS spec. 96189c78134cc54dff016c83367912eb055637fa50cAlan Cox */ 96289c78134cc54dff016c83367912eb055637fa50cAlan Cox#define set_display_off 0x28 96389c78134cc54dff016c83367912eb055637fa50cAlan Cox/* ************************************************************************* *\ 96489c78134cc54dff016c83367912eb055637fa50cAlan CoxThis command causes the display module to stop displaying the image data 96589c78134cc54dff016c83367912eb055637fa50cAlan Coxon the display device. The frame memory contents remain unchanged. 96689c78134cc54dff016c83367912eb055637fa50cAlan CoxNo status bits are changed. 96789c78134cc54dff016c83367912eb055637fa50cAlan Cox\* ************************************************************************* */ 96889c78134cc54dff016c83367912eb055637fa50cAlan Cox#define set_display_on 0x29 96989c78134cc54dff016c83367912eb055637fa50cAlan Cox/* ************************************************************************* *\ 97089c78134cc54dff016c83367912eb055637fa50cAlan CoxThis command causes the display module to start displaying the image data 97189c78134cc54dff016c83367912eb055637fa50cAlan Coxon the display device. The frame memory contents remain unchanged. 97289c78134cc54dff016c83367912eb055637fa50cAlan CoxNo status bits are changed. 97389c78134cc54dff016c83367912eb055637fa50cAlan Cox\* ************************************************************************* */ 97489c78134cc54dff016c83367912eb055637fa50cAlan Cox#define set_column_address 0x2a 97589c78134cc54dff016c83367912eb055637fa50cAlan Cox/* 97689c78134cc54dff016c83367912eb055637fa50cAlan Cox * This command defines the column extent of the frame memory accessed by 97789c78134cc54dff016c83367912eb055637fa50cAlan Cox * the hostprocessor with the read_memory_continue and 97889c78134cc54dff016c83367912eb055637fa50cAlan Cox * write_memory_continue commands. 97989c78134cc54dff016c83367912eb055637fa50cAlan Cox * No status bits are changed. 98089c78134cc54dff016c83367912eb055637fa50cAlan Cox */ 98189c78134cc54dff016c83367912eb055637fa50cAlan Cox#define set_page_addr 0x2b 98289c78134cc54dff016c83367912eb055637fa50cAlan Cox/* 98389c78134cc54dff016c83367912eb055637fa50cAlan Cox * This command defines the page extent of the frame memory accessed by 98489c78134cc54dff016c83367912eb055637fa50cAlan Cox * the host processor with the write_memory_continue and 98589c78134cc54dff016c83367912eb055637fa50cAlan Cox * read_memory_continue command. 98689c78134cc54dff016c83367912eb055637fa50cAlan Cox * No status bits are changed. 98789c78134cc54dff016c83367912eb055637fa50cAlan Cox */ 98889c78134cc54dff016c83367912eb055637fa50cAlan Cox#define write_mem_start 0x2c 98989c78134cc54dff016c83367912eb055637fa50cAlan Cox/* 99089c78134cc54dff016c83367912eb055637fa50cAlan Cox * This command transfers image data from the host processor to the 99189c78134cc54dff016c83367912eb055637fa50cAlan Cox * display modules frame memory starting at the pixel location specified 99289c78134cc54dff016c83367912eb055637fa50cAlan Cox * by preceding set_column_address and set_page_address commands. 99389c78134cc54dff016c83367912eb055637fa50cAlan Cox */ 99489c78134cc54dff016c83367912eb055637fa50cAlan Cox#define set_partial_area 0x30 99589c78134cc54dff016c83367912eb055637fa50cAlan Cox/* 99689c78134cc54dff016c83367912eb055637fa50cAlan Cox * This command defines the Partial Display mode s display area. 99789c78134cc54dff016c83367912eb055637fa50cAlan Cox * There are two parameters associated with this command, the first 99889c78134cc54dff016c83367912eb055637fa50cAlan Cox * defines the Start Row (SR) and the second the End Row (ER). SR and ER 99989c78134cc54dff016c83367912eb055637fa50cAlan Cox * refer to the Frame Memory Line Pointer. 100089c78134cc54dff016c83367912eb055637fa50cAlan Cox */ 100189c78134cc54dff016c83367912eb055637fa50cAlan Cox#define set_scroll_area 0x33 100289c78134cc54dff016c83367912eb055637fa50cAlan Cox/* 100389c78134cc54dff016c83367912eb055637fa50cAlan Cox * This command defines the display modules Vertical Scrolling Area. 100489c78134cc54dff016c83367912eb055637fa50cAlan Cox */ 100589c78134cc54dff016c83367912eb055637fa50cAlan Cox#define set_tear_off 0x34 100689c78134cc54dff016c83367912eb055637fa50cAlan Cox/* 100789c78134cc54dff016c83367912eb055637fa50cAlan Cox * This command turns off the display modules Tearing Effect output 100889c78134cc54dff016c83367912eb055637fa50cAlan Cox * signal on the TE signal line. 100989c78134cc54dff016c83367912eb055637fa50cAlan Cox */ 101089c78134cc54dff016c83367912eb055637fa50cAlan Cox#define set_tear_on 0x35 101189c78134cc54dff016c83367912eb055637fa50cAlan Cox/* 101289c78134cc54dff016c83367912eb055637fa50cAlan Cox * This command turns on the display modules Tearing Effect output signal 101389c78134cc54dff016c83367912eb055637fa50cAlan Cox * on the TE signal line. 101489c78134cc54dff016c83367912eb055637fa50cAlan Cox */ 101589c78134cc54dff016c83367912eb055637fa50cAlan Cox#define set_address_mode 0x36 101689c78134cc54dff016c83367912eb055637fa50cAlan Cox/* 101789c78134cc54dff016c83367912eb055637fa50cAlan Cox * This command sets the data order for transfers from the host processor 101889c78134cc54dff016c83367912eb055637fa50cAlan Cox * to display modules frame memory,bits B[7:5] and B3, and from the 101989c78134cc54dff016c83367912eb055637fa50cAlan Cox * display modules frame memory to the display device, bits B[2:0] and B4. 102089c78134cc54dff016c83367912eb055637fa50cAlan Cox */ 102189c78134cc54dff016c83367912eb055637fa50cAlan Cox#define set_scroll_start 0x37 102289c78134cc54dff016c83367912eb055637fa50cAlan Cox/* 102389c78134cc54dff016c83367912eb055637fa50cAlan Cox * This command sets the start of the vertical scrolling area in the frame 102489c78134cc54dff016c83367912eb055637fa50cAlan Cox * memory. The vertical scrolling area is fully defined when this command 102589c78134cc54dff016c83367912eb055637fa50cAlan Cox * is used with the set_scroll_area command The set_scroll_start command 102689c78134cc54dff016c83367912eb055637fa50cAlan Cox * has one parameter, the Vertical Scroll Pointer. The VSP defines the 102789c78134cc54dff016c83367912eb055637fa50cAlan Cox * line in the frame memory that is written to the display device as the 102889c78134cc54dff016c83367912eb055637fa50cAlan Cox * first line of the vertical scroll area. 102989c78134cc54dff016c83367912eb055637fa50cAlan Cox */ 103089c78134cc54dff016c83367912eb055637fa50cAlan Cox#define exit_idle_mode 0x38 103189c78134cc54dff016c83367912eb055637fa50cAlan Cox/* 103289c78134cc54dff016c83367912eb055637fa50cAlan Cox * This command causes the display module to exit Idle mode. 103389c78134cc54dff016c83367912eb055637fa50cAlan Cox */ 103489c78134cc54dff016c83367912eb055637fa50cAlan Cox#define enter_idle_mode 0x39 103589c78134cc54dff016c83367912eb055637fa50cAlan Cox/* 103689c78134cc54dff016c83367912eb055637fa50cAlan Cox * This command causes the display module to enter Idle Mode. 103789c78134cc54dff016c83367912eb055637fa50cAlan Cox * In Idle Mode, color expression is reduced. Colors are shown on the 103889c78134cc54dff016c83367912eb055637fa50cAlan Cox * display device using the MSB of each of the R, G and B color 103989c78134cc54dff016c83367912eb055637fa50cAlan Cox * components in the frame memory 104089c78134cc54dff016c83367912eb055637fa50cAlan Cox */ 104189c78134cc54dff016c83367912eb055637fa50cAlan Cox#define set_pixel_format 0x3a 104289c78134cc54dff016c83367912eb055637fa50cAlan Cox/* 104389c78134cc54dff016c83367912eb055637fa50cAlan Cox * This command sets the pixel format for the RGB image data used by the 104489c78134cc54dff016c83367912eb055637fa50cAlan Cox * interface. 104589c78134cc54dff016c83367912eb055637fa50cAlan Cox * Bits D[6:4] DPI Pixel Format Definition 104689c78134cc54dff016c83367912eb055637fa50cAlan Cox * Bits D[2:0] DBI Pixel Format Definition 104789c78134cc54dff016c83367912eb055637fa50cAlan Cox * Bits D7 and D3 are not used. 104889c78134cc54dff016c83367912eb055637fa50cAlan Cox */ 104989c78134cc54dff016c83367912eb055637fa50cAlan Cox#define DCS_PIXEL_FORMAT_3bpp 0x1 105089c78134cc54dff016c83367912eb055637fa50cAlan Cox#define DCS_PIXEL_FORMAT_8bpp 0x2 105189c78134cc54dff016c83367912eb055637fa50cAlan Cox#define DCS_PIXEL_FORMAT_12bpp 0x3 105289c78134cc54dff016c83367912eb055637fa50cAlan Cox#define DCS_PIXEL_FORMAT_16bpp 0x5 105389c78134cc54dff016c83367912eb055637fa50cAlan Cox#define DCS_PIXEL_FORMAT_18bpp 0x6 105489c78134cc54dff016c83367912eb055637fa50cAlan Cox#define DCS_PIXEL_FORMAT_24bpp 0x7 105589c78134cc54dff016c83367912eb055637fa50cAlan Cox 105689c78134cc54dff016c83367912eb055637fa50cAlan Cox#define write_mem_cont 0x3c 105789c78134cc54dff016c83367912eb055637fa50cAlan Cox 105889c78134cc54dff016c83367912eb055637fa50cAlan Cox/* 105989c78134cc54dff016c83367912eb055637fa50cAlan Cox * This command transfers image data from the host processor to the 106089c78134cc54dff016c83367912eb055637fa50cAlan Cox * display module's frame memory continuing from the pixel location 106189c78134cc54dff016c83367912eb055637fa50cAlan Cox * following the previous write_memory_continue or write_memory_start 106289c78134cc54dff016c83367912eb055637fa50cAlan Cox * command. 106389c78134cc54dff016c83367912eb055637fa50cAlan Cox */ 106489c78134cc54dff016c83367912eb055637fa50cAlan Cox#define set_tear_scanline 0x44 106589c78134cc54dff016c83367912eb055637fa50cAlan Cox/* 106689c78134cc54dff016c83367912eb055637fa50cAlan Cox * This command turns on the display modules Tearing Effect output signal 106789c78134cc54dff016c83367912eb055637fa50cAlan Cox * on the TE signal line when the display module reaches line N. 106889c78134cc54dff016c83367912eb055637fa50cAlan Cox */ 106989c78134cc54dff016c83367912eb055637fa50cAlan Cox#define get_scanline 0x45 107089c78134cc54dff016c83367912eb055637fa50cAlan Cox/* 107189c78134cc54dff016c83367912eb055637fa50cAlan Cox * The display module returns the current scanline, N, used to update the 107289c78134cc54dff016c83367912eb055637fa50cAlan Cox * display device. The total number of scanlines on a display device is 107389c78134cc54dff016c83367912eb055637fa50cAlan Cox * defined as VSYNC + VBP + VACT + VFP.The first scanline is defined as 107489c78134cc54dff016c83367912eb055637fa50cAlan Cox * the first line of V Sync and is denoted as Line 0. 107589c78134cc54dff016c83367912eb055637fa50cAlan Cox * When in Sleep Mode, the value returned by get_scanline is undefined. 107689c78134cc54dff016c83367912eb055637fa50cAlan Cox */ 107789c78134cc54dff016c83367912eb055637fa50cAlan Cox 107889c78134cc54dff016c83367912eb055637fa50cAlan Cox/* MCS or Generic COMMANDS */ 107989c78134cc54dff016c83367912eb055637fa50cAlan Cox/* MCS/generic data type */ 108089c78134cc54dff016c83367912eb055637fa50cAlan Cox#define GEN_SHORT_WRITE_0 0x03 /* generic short write, no parameters */ 108189c78134cc54dff016c83367912eb055637fa50cAlan Cox#define GEN_SHORT_WRITE_1 0x13 /* generic short write, 1 parameters */ 108289c78134cc54dff016c83367912eb055637fa50cAlan Cox#define GEN_SHORT_WRITE_2 0x23 /* generic short write, 2 parameters */ 108389c78134cc54dff016c83367912eb055637fa50cAlan Cox#define GEN_READ_0 0x04 /* generic read, no parameters */ 108489c78134cc54dff016c83367912eb055637fa50cAlan Cox#define GEN_READ_1 0x14 /* generic read, 1 parameters */ 108589c78134cc54dff016c83367912eb055637fa50cAlan Cox#define GEN_READ_2 0x24 /* generic read, 2 parameters */ 108689c78134cc54dff016c83367912eb055637fa50cAlan Cox#define GEN_LONG_WRITE 0x29 /* generic long write */ 108789c78134cc54dff016c83367912eb055637fa50cAlan Cox#define MCS_SHORT_WRITE_0 0x05 /* MCS short write, no parameters */ 108889c78134cc54dff016c83367912eb055637fa50cAlan Cox#define MCS_SHORT_WRITE_1 0x15 /* MCS short write, 1 parameters */ 108989c78134cc54dff016c83367912eb055637fa50cAlan Cox#define MCS_READ 0x06 /* MCS read, no parameters */ 109089c78134cc54dff016c83367912eb055637fa50cAlan Cox#define MCS_LONG_WRITE 0x39 /* MCS long write */ 109189c78134cc54dff016c83367912eb055637fa50cAlan Cox/* MCS/generic commands */ 109289c78134cc54dff016c83367912eb055637fa50cAlan Cox/* TPO MCS */ 109389c78134cc54dff016c83367912eb055637fa50cAlan Cox#define write_display_profile 0x50 109489c78134cc54dff016c83367912eb055637fa50cAlan Cox#define write_display_brightness 0x51 109589c78134cc54dff016c83367912eb055637fa50cAlan Cox#define write_ctrl_display 0x53 109689c78134cc54dff016c83367912eb055637fa50cAlan Cox#define write_ctrl_cabc 0x55 109789c78134cc54dff016c83367912eb055637fa50cAlan Cox #define UI_IMAGE 0x01 109889c78134cc54dff016c83367912eb055637fa50cAlan Cox #define STILL_IMAGE 0x02 109989c78134cc54dff016c83367912eb055637fa50cAlan Cox #define MOVING_IMAGE 0x03 110089c78134cc54dff016c83367912eb055637fa50cAlan Cox#define write_hysteresis 0x57 110189c78134cc54dff016c83367912eb055637fa50cAlan Cox#define write_gamma_setting 0x58 110289c78134cc54dff016c83367912eb055637fa50cAlan Cox#define write_cabc_min_bright 0x5e 110389c78134cc54dff016c83367912eb055637fa50cAlan Cox#define write_kbbc_profile 0x60 110489c78134cc54dff016c83367912eb055637fa50cAlan Cox/* TMD MCS */ 110589c78134cc54dff016c83367912eb055637fa50cAlan Cox#define tmd_write_display_brightness 0x8c 110689c78134cc54dff016c83367912eb055637fa50cAlan Cox 110789c78134cc54dff016c83367912eb055637fa50cAlan Cox/* 110889c78134cc54dff016c83367912eb055637fa50cAlan Cox * This command is used to control ambient light, panel backlight 110989c78134cc54dff016c83367912eb055637fa50cAlan Cox * brightness and gamma settings. 111089c78134cc54dff016c83367912eb055637fa50cAlan Cox */ 111189c78134cc54dff016c83367912eb055637fa50cAlan Cox#define BRIGHT_CNTL_BLOCK_ON (1 << 5) 111289c78134cc54dff016c83367912eb055637fa50cAlan Cox#define AMBIENT_LIGHT_SENSE_ON (1 << 4) 111389c78134cc54dff016c83367912eb055637fa50cAlan Cox#define DISPLAY_DIMMING_ON (1 << 3) 111489c78134cc54dff016c83367912eb055637fa50cAlan Cox#define BACKLIGHT_ON (1 << 2) 111589c78134cc54dff016c83367912eb055637fa50cAlan Cox#define DISPLAY_BRIGHTNESS_AUTO (1 << 1) 111689c78134cc54dff016c83367912eb055637fa50cAlan Cox#define GAMMA_AUTO (1 << 0) 111789c78134cc54dff016c83367912eb055637fa50cAlan Cox 111889c78134cc54dff016c83367912eb055637fa50cAlan Cox/* DCS Interface Pixel Formats */ 111989c78134cc54dff016c83367912eb055637fa50cAlan Cox#define DCS_PIXEL_FORMAT_3BPP 0x1 112089c78134cc54dff016c83367912eb055637fa50cAlan Cox#define DCS_PIXEL_FORMAT_8BPP 0x2 112189c78134cc54dff016c83367912eb055637fa50cAlan Cox#define DCS_PIXEL_FORMAT_12BPP 0x3 112289c78134cc54dff016c83367912eb055637fa50cAlan Cox#define DCS_PIXEL_FORMAT_16BPP 0x5 112389c78134cc54dff016c83367912eb055637fa50cAlan Cox#define DCS_PIXEL_FORMAT_18BPP 0x6 112489c78134cc54dff016c83367912eb055637fa50cAlan Cox#define DCS_PIXEL_FORMAT_24BPP 0x7 112589c78134cc54dff016c83367912eb055637fa50cAlan Cox/* ONE PARAMETER READ DATA */ 112689c78134cc54dff016c83367912eb055637fa50cAlan Cox#define addr_mode_data 0xfc 112789c78134cc54dff016c83367912eb055637fa50cAlan Cox#define diag_res_data 0x00 112889c78134cc54dff016c83367912eb055637fa50cAlan Cox#define disp_mode_data 0x23 112989c78134cc54dff016c83367912eb055637fa50cAlan Cox#define pxl_fmt_data 0x77 113089c78134cc54dff016c83367912eb055637fa50cAlan Cox#define pwr_mode_data 0x74 113189c78134cc54dff016c83367912eb055637fa50cAlan Cox#define sig_mode_data 0x00 113289c78134cc54dff016c83367912eb055637fa50cAlan Cox/* TWO PARAMETERS READ DATA */ 113389c78134cc54dff016c83367912eb055637fa50cAlan Cox#define scanline_data1 0xff 113489c78134cc54dff016c83367912eb055637fa50cAlan Cox#define scanline_data2 0xff 113589c78134cc54dff016c83367912eb055637fa50cAlan Cox#define NON_BURST_MODE_SYNC_PULSE 0x01 /* Non Burst Mode 113689c78134cc54dff016c83367912eb055637fa50cAlan Cox * with Sync Pulse 113789c78134cc54dff016c83367912eb055637fa50cAlan Cox */ 113889c78134cc54dff016c83367912eb055637fa50cAlan Cox#define NON_BURST_MODE_SYNC_EVENTS 0x02 /* Non Burst Mode 113989c78134cc54dff016c83367912eb055637fa50cAlan Cox * with Sync events 114089c78134cc54dff016c83367912eb055637fa50cAlan Cox */ 114189c78134cc54dff016c83367912eb055637fa50cAlan Cox#define BURST_MODE 0x03 /* Burst Mode */ 114289c78134cc54dff016c83367912eb055637fa50cAlan Cox#define DBI_COMMAND_BUFFER_SIZE 0x240 /* 0x32 */ /* 0x120 */ 114389c78134cc54dff016c83367912eb055637fa50cAlan Cox /* Allocate at least 114489c78134cc54dff016c83367912eb055637fa50cAlan Cox * 0x100 Byte with 32 114589c78134cc54dff016c83367912eb055637fa50cAlan Cox * byte alignment 114689c78134cc54dff016c83367912eb055637fa50cAlan Cox */ 114789c78134cc54dff016c83367912eb055637fa50cAlan Cox#define DBI_DATA_BUFFER_SIZE 0x120 /* Allocate at least 114889c78134cc54dff016c83367912eb055637fa50cAlan Cox * 0x100 Byte with 32 114989c78134cc54dff016c83367912eb055637fa50cAlan Cox * byte alignment 115089c78134cc54dff016c83367912eb055637fa50cAlan Cox */ 115189c78134cc54dff016c83367912eb055637fa50cAlan Cox#define DBI_CB_TIME_OUT 0xFFFF 115289c78134cc54dff016c83367912eb055637fa50cAlan Cox 115389c78134cc54dff016c83367912eb055637fa50cAlan Cox#define GEN_FB_TIME_OUT 2000 115489c78134cc54dff016c83367912eb055637fa50cAlan Cox 115589c78134cc54dff016c83367912eb055637fa50cAlan Cox#define SKU_83 0x01 115689c78134cc54dff016c83367912eb055637fa50cAlan Cox#define SKU_100 0x02 115789c78134cc54dff016c83367912eb055637fa50cAlan Cox#define SKU_100L 0x04 115889c78134cc54dff016c83367912eb055637fa50cAlan Cox#define SKU_BYPASS 0x08 115989c78134cc54dff016c83367912eb055637fa50cAlan Cox 116089c78134cc54dff016c83367912eb055637fa50cAlan Cox/* Some handy macros for playing with bitfields. */ 116189c78134cc54dff016c83367912eb055637fa50cAlan Cox#define PSB_MASK(high, low) (((1<<((high)-(low)+1))-1)<<(low)) 116289c78134cc54dff016c83367912eb055637fa50cAlan Cox#define SET_FIELD(value, field) (((value) << field ## _SHIFT) & field ## _MASK) 116389c78134cc54dff016c83367912eb055637fa50cAlan Cox#define GET_FIELD(word, field) (((word) & field ## _MASK) >> field ## _SHIFT) 116489c78134cc54dff016c83367912eb055637fa50cAlan Cox 116589c78134cc54dff016c83367912eb055637fa50cAlan Cox#define _PIPE(pipe, a, b) ((a) + (pipe)*((b)-(a))) 116689c78134cc54dff016c83367912eb055637fa50cAlan Cox 116789c78134cc54dff016c83367912eb055637fa50cAlan Cox/* PCI config space */ 116889c78134cc54dff016c83367912eb055637fa50cAlan Cox 116989c78134cc54dff016c83367912eb055637fa50cAlan Cox#define SB_PCKT 0x02100 /* cedarview */ 117089c78134cc54dff016c83367912eb055637fa50cAlan Cox# define SB_OPCODE_MASK PSB_MASK(31, 16) 117189c78134cc54dff016c83367912eb055637fa50cAlan Cox# define SB_OPCODE_SHIFT 16 117289c78134cc54dff016c83367912eb055637fa50cAlan Cox# define SB_OPCODE_READ 0 117389c78134cc54dff016c83367912eb055637fa50cAlan Cox# define SB_OPCODE_WRITE 1 117489c78134cc54dff016c83367912eb055637fa50cAlan Cox# define SB_DEST_MASK PSB_MASK(15, 8) 117589c78134cc54dff016c83367912eb055637fa50cAlan Cox# define SB_DEST_SHIFT 8 117689c78134cc54dff016c83367912eb055637fa50cAlan Cox# define SB_DEST_DPLL 0x88 117789c78134cc54dff016c83367912eb055637fa50cAlan Cox# define SB_BYTE_ENABLE_MASK PSB_MASK(7, 4) 117889c78134cc54dff016c83367912eb055637fa50cAlan Cox# define SB_BYTE_ENABLE_SHIFT 4 117989c78134cc54dff016c83367912eb055637fa50cAlan Cox# define SB_BUSY (1 << 0) 118089c78134cc54dff016c83367912eb055637fa50cAlan Cox 118189c78134cc54dff016c83367912eb055637fa50cAlan Cox 118289c78134cc54dff016c83367912eb055637fa50cAlan Cox/* 32-bit value read/written from the DPIO reg. */ 118389c78134cc54dff016c83367912eb055637fa50cAlan Cox#define SB_DATA 0x02104 /* cedarview */ 118489c78134cc54dff016c83367912eb055637fa50cAlan Cox/* 32-bit address of the DPIO reg to be read/written. */ 118589c78134cc54dff016c83367912eb055637fa50cAlan Cox#define SB_ADDR 0x02108 /* cedarview */ 118689c78134cc54dff016c83367912eb055637fa50cAlan Cox#define DPIO_CFG 0x02110 /* cedarview */ 118789c78134cc54dff016c83367912eb055637fa50cAlan Cox# define DPIO_MODE_SELECT_1 (1 << 3) 118889c78134cc54dff016c83367912eb055637fa50cAlan Cox# define DPIO_MODE_SELECT_0 (1 << 2) 118989c78134cc54dff016c83367912eb055637fa50cAlan Cox# define DPIO_SFR_BYPASS (1 << 1) 119089c78134cc54dff016c83367912eb055637fa50cAlan Cox/* reset is active low */ 119189c78134cc54dff016c83367912eb055637fa50cAlan Cox# define DPIO_CMN_RESET_N (1 << 0) 119289c78134cc54dff016c83367912eb055637fa50cAlan Cox 119389c78134cc54dff016c83367912eb055637fa50cAlan Cox/* Cedarview sideband registers */ 119489c78134cc54dff016c83367912eb055637fa50cAlan Cox#define _SB_M_A 0x8008 119589c78134cc54dff016c83367912eb055637fa50cAlan Cox#define _SB_M_B 0x8028 119689c78134cc54dff016c83367912eb055637fa50cAlan Cox#define SB_M(pipe) _PIPE(pipe, _SB_M_A, _SB_M_B) 119789c78134cc54dff016c83367912eb055637fa50cAlan Cox# define SB_M_DIVIDER_MASK (0xFF << 24) 119889c78134cc54dff016c83367912eb055637fa50cAlan Cox# define SB_M_DIVIDER_SHIFT 24 119989c78134cc54dff016c83367912eb055637fa50cAlan Cox 120089c78134cc54dff016c83367912eb055637fa50cAlan Cox#define _SB_N_VCO_A 0x8014 120189c78134cc54dff016c83367912eb055637fa50cAlan Cox#define _SB_N_VCO_B 0x8034 120289c78134cc54dff016c83367912eb055637fa50cAlan Cox#define SB_N_VCO(pipe) _PIPE(pipe, _SB_N_VCO_A, _SB_N_VCO_B) 120389c78134cc54dff016c83367912eb055637fa50cAlan Cox#define SB_N_VCO_SEL_MASK PSB_MASK(31, 30) 120489c78134cc54dff016c83367912eb055637fa50cAlan Cox#define SB_N_VCO_SEL_SHIFT 30 120589c78134cc54dff016c83367912eb055637fa50cAlan Cox#define SB_N_DIVIDER_MASK PSB_MASK(29, 26) 120689c78134cc54dff016c83367912eb055637fa50cAlan Cox#define SB_N_DIVIDER_SHIFT 26 120789c78134cc54dff016c83367912eb055637fa50cAlan Cox#define SB_N_CB_TUNE_MASK PSB_MASK(25, 24) 120889c78134cc54dff016c83367912eb055637fa50cAlan Cox#define SB_N_CB_TUNE_SHIFT 24 120989c78134cc54dff016c83367912eb055637fa50cAlan Cox 121089c78134cc54dff016c83367912eb055637fa50cAlan Cox#define _SB_REF_A 0x8018 121189c78134cc54dff016c83367912eb055637fa50cAlan Cox#define _SB_REF_B 0x8038 121289c78134cc54dff016c83367912eb055637fa50cAlan Cox#define SB_REF_SFR(pipe) _PIPE(pipe, _SB_REF_A, _SB_REF_B) 121389c78134cc54dff016c83367912eb055637fa50cAlan Cox 121489c78134cc54dff016c83367912eb055637fa50cAlan Cox#define _SB_P_A 0x801c 121589c78134cc54dff016c83367912eb055637fa50cAlan Cox#define _SB_P_B 0x803c 121689c78134cc54dff016c83367912eb055637fa50cAlan Cox#define SB_P(pipe) _PIPE(pipe, _SB_P_A, _SB_P_B) 121789c78134cc54dff016c83367912eb055637fa50cAlan Cox#define SB_P2_DIVIDER_MASK PSB_MASK(31, 30) 121889c78134cc54dff016c83367912eb055637fa50cAlan Cox#define SB_P2_DIVIDER_SHIFT 30 121989c78134cc54dff016c83367912eb055637fa50cAlan Cox#define SB_P2_10 0 /* HDMI, DP, DAC */ 122089c78134cc54dff016c83367912eb055637fa50cAlan Cox#define SB_P2_5 1 /* DAC */ 122189c78134cc54dff016c83367912eb055637fa50cAlan Cox#define SB_P2_14 2 /* LVDS single */ 122289c78134cc54dff016c83367912eb055637fa50cAlan Cox#define SB_P2_7 3 /* LVDS double */ 122389c78134cc54dff016c83367912eb055637fa50cAlan Cox#define SB_P1_DIVIDER_MASK PSB_MASK(15, 12) 122489c78134cc54dff016c83367912eb055637fa50cAlan Cox#define SB_P1_DIVIDER_SHIFT 12 122589c78134cc54dff016c83367912eb055637fa50cAlan Cox 122689c78134cc54dff016c83367912eb055637fa50cAlan Cox#define PSB_LANE0 0x120 122789c78134cc54dff016c83367912eb055637fa50cAlan Cox#define PSB_LANE1 0x220 122889c78134cc54dff016c83367912eb055637fa50cAlan Cox#define PSB_LANE2 0x2320 122989c78134cc54dff016c83367912eb055637fa50cAlan Cox#define PSB_LANE3 0x2420 123089c78134cc54dff016c83367912eb055637fa50cAlan Cox 123189c78134cc54dff016c83367912eb055637fa50cAlan Cox#define LANE_PLL_MASK (0x7 << 20) 123289c78134cc54dff016c83367912eb055637fa50cAlan Cox#define LANE_PLL_ENABLE (0x3 << 20) 123389c78134cc54dff016c83367912eb055637fa50cAlan Cox 123489c78134cc54dff016c83367912eb055637fa50cAlan Cox 123589c78134cc54dff016c83367912eb055637fa50cAlan Cox#endif 1236