tda998x_drv.c revision 179f1aa407b466c06a94f9e54abc948d1e1146e7
1e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark/* 2e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark * Copyright (C) 2012 Texas Instruments 3e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark * Author: Rob Clark <robdclark@gmail.com> 4e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark * 5e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark * This program is free software; you can redistribute it and/or modify it 6e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark * under the terms of the GNU General Public License version 2 as published by 7e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark * the Free Software Foundation. 8e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark * 9e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark * This program is distributed in the hope that it will be useful, but WITHOUT 10e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark * more details. 13e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark * 14e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark * You should have received a copy of the GNU General Public License along with 15e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark * this program. If not, see <http://www.gnu.org/licenses/>. 16e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark */ 17e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 18e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 19e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 20e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark#include <linux/module.h> 21e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 22e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark#include <drm/drmP.h> 23e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark#include <drm/drm_crtc_helper.h> 24e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark#include <drm/drm_encoder_slave.h> 25e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark#include <drm/drm_edid.h> 26c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King#include <drm/i2c/tda998x.h> 27e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 28e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark#define DBG(fmt, ...) DRM_DEBUG(fmt"\n", ##__VA_ARGS__) 29e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 30e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clarkstruct tda998x_priv { 31e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark struct i2c_client *cec; 32e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark uint16_t rev; 33e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark uint8_t current_page; 34e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark int dpms; 35c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King bool is_hdmi_sink; 365e74c22cd1e0f9e49573fe580de47e198ee04975Russell King u8 vip_cntrl_0; 375e74c22cd1e0f9e49573fe580de47e198ee04975Russell King u8 vip_cntrl_1; 385e74c22cd1e0f9e49573fe580de47e198ee04975Russell King u8 vip_cntrl_2; 39c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King struct tda998x_encoder_params params; 40e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark}; 41e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 42e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark#define to_tda998x_priv(x) ((struct tda998x_priv *)to_encoder_slave(x)->slave_priv) 43e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 44e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark/* The TDA9988 series of devices use a paged register scheme.. to simplify 45e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark * things we encode the page # in upper bits of the register #. To read/ 46e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark * write a given register, we need to make sure CURPAGE register is set 47e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark * appropriately. Which implies reads/writes are not atomic. Fun! 48e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark */ 49e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 50e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark#define REG(page, addr) (((page) << 8) | (addr)) 51e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark#define REG2ADDR(reg) ((reg) & 0xff) 52e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark#define REG2PAGE(reg) (((reg) >> 8) & 0xff) 53e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 54e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark#define REG_CURPAGE 0xff /* write */ 55e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 56e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 57e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark/* Page 00h: General Control */ 58e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark#define REG_VERSION_LSB REG(0x00, 0x00) /* read */ 59e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark#define REG_MAIN_CNTRL0 REG(0x00, 0x01) /* read/write */ 60e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark# define MAIN_CNTRL0_SR (1 << 0) 61e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark# define MAIN_CNTRL0_DECS (1 << 1) 62e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark# define MAIN_CNTRL0_DEHS (1 << 2) 63e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark# define MAIN_CNTRL0_CECS (1 << 3) 64e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark# define MAIN_CNTRL0_CEHS (1 << 4) 65e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark# define MAIN_CNTRL0_SCALER (1 << 7) 66e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark#define REG_VERSION_MSB REG(0x00, 0x02) /* read */ 67e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark#define REG_SOFTRESET REG(0x00, 0x0a) /* write */ 68e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark# define SOFTRESET_AUDIO (1 << 0) 69e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark# define SOFTRESET_I2C_MASTER (1 << 1) 70e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark#define REG_DDC_DISABLE REG(0x00, 0x0b) /* read/write */ 71e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark#define REG_CCLK_ON REG(0x00, 0x0c) /* read/write */ 72e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark#define REG_I2C_MASTER REG(0x00, 0x0d) /* read/write */ 73e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark# define I2C_MASTER_DIS_MM (1 << 0) 74e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark# define I2C_MASTER_DIS_FILT (1 << 1) 75e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark# define I2C_MASTER_APP_STRT_LAT (1 << 2) 76c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King#define REG_FEAT_POWERDOWN REG(0x00, 0x0e) /* read/write */ 77c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King# define FEAT_POWERDOWN_SPDIF (1 << 3) 78e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark#define REG_INT_FLAGS_0 REG(0x00, 0x0f) /* read/write */ 79e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark#define REG_INT_FLAGS_1 REG(0x00, 0x10) /* read/write */ 80e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark#define REG_INT_FLAGS_2 REG(0x00, 0x11) /* read/write */ 81e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark# define INT_FLAGS_2_EDID_BLK_RD (1 << 1) 82c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King#define REG_ENA_ACLK REG(0x00, 0x16) /* read/write */ 83e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark#define REG_ENA_VP_0 REG(0x00, 0x18) /* read/write */ 84e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark#define REG_ENA_VP_1 REG(0x00, 0x19) /* read/write */ 85e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark#define REG_ENA_VP_2 REG(0x00, 0x1a) /* read/write */ 86e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark#define REG_ENA_AP REG(0x00, 0x1e) /* read/write */ 87e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark#define REG_VIP_CNTRL_0 REG(0x00, 0x20) /* write */ 88e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark# define VIP_CNTRL_0_MIRR_A (1 << 7) 89e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark# define VIP_CNTRL_0_SWAP_A(x) (((x) & 7) << 4) 90e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark# define VIP_CNTRL_0_MIRR_B (1 << 3) 91e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark# define VIP_CNTRL_0_SWAP_B(x) (((x) & 7) << 0) 92e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark#define REG_VIP_CNTRL_1 REG(0x00, 0x21) /* write */ 93e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark# define VIP_CNTRL_1_MIRR_C (1 << 7) 94e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark# define VIP_CNTRL_1_SWAP_C(x) (((x) & 7) << 4) 95e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark# define VIP_CNTRL_1_MIRR_D (1 << 3) 96e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark# define VIP_CNTRL_1_SWAP_D(x) (((x) & 7) << 0) 97e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark#define REG_VIP_CNTRL_2 REG(0x00, 0x22) /* write */ 98e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark# define VIP_CNTRL_2_MIRR_E (1 << 7) 99e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark# define VIP_CNTRL_2_SWAP_E(x) (((x) & 7) << 4) 100e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark# define VIP_CNTRL_2_MIRR_F (1 << 3) 101e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark# define VIP_CNTRL_2_SWAP_F(x) (((x) & 7) << 0) 102e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark#define REG_VIP_CNTRL_3 REG(0x00, 0x23) /* write */ 103e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark# define VIP_CNTRL_3_X_TGL (1 << 0) 104e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark# define VIP_CNTRL_3_H_TGL (1 << 1) 105e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark# define VIP_CNTRL_3_V_TGL (1 << 2) 106e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark# define VIP_CNTRL_3_EMB (1 << 3) 107e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark# define VIP_CNTRL_3_SYNC_DE (1 << 4) 108e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark# define VIP_CNTRL_3_SYNC_HS (1 << 5) 109e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark# define VIP_CNTRL_3_DE_INT (1 << 6) 110e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark# define VIP_CNTRL_3_EDGE (1 << 7) 111e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark#define REG_VIP_CNTRL_4 REG(0x00, 0x24) /* write */ 112e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark# define VIP_CNTRL_4_BLC(x) (((x) & 3) << 0) 113e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark# define VIP_CNTRL_4_BLANKIT(x) (((x) & 3) << 2) 114e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark# define VIP_CNTRL_4_CCIR656 (1 << 4) 115e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark# define VIP_CNTRL_4_656_ALT (1 << 5) 116e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark# define VIP_CNTRL_4_TST_656 (1 << 6) 117e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark# define VIP_CNTRL_4_TST_PAT (1 << 7) 118e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark#define REG_VIP_CNTRL_5 REG(0x00, 0x25) /* write */ 119e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark# define VIP_CNTRL_5_CKCASE (1 << 0) 120e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark# define VIP_CNTRL_5_SP_CNT(x) (((x) & 3) << 1) 121c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King#define REG_MUX_AP REG(0x00, 0x26) /* read/write */ 122bcb2481df01a9aee7a09b20d43194011edd35754Russell King#define REG_MUX_VP_VIP_OUT REG(0x00, 0x27) /* read/write */ 123e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark#define REG_MAT_CONTRL REG(0x00, 0x80) /* write */ 124e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark# define MAT_CONTRL_MAT_SC(x) (((x) & 3) << 0) 125e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark# define MAT_CONTRL_MAT_BP (1 << 2) 126e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark#define REG_VIDFORMAT REG(0x00, 0xa0) /* write */ 127e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark#define REG_REFPIX_MSB REG(0x00, 0xa1) /* write */ 128e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark#define REG_REFPIX_LSB REG(0x00, 0xa2) /* write */ 129e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark#define REG_REFLINE_MSB REG(0x00, 0xa3) /* write */ 130e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark#define REG_REFLINE_LSB REG(0x00, 0xa4) /* write */ 131e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark#define REG_NPIX_MSB REG(0x00, 0xa5) /* write */ 132e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark#define REG_NPIX_LSB REG(0x00, 0xa6) /* write */ 133e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark#define REG_NLINE_MSB REG(0x00, 0xa7) /* write */ 134e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark#define REG_NLINE_LSB REG(0x00, 0xa8) /* write */ 135e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark#define REG_VS_LINE_STRT_1_MSB REG(0x00, 0xa9) /* write */ 136e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark#define REG_VS_LINE_STRT_1_LSB REG(0x00, 0xaa) /* write */ 137e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark#define REG_VS_PIX_STRT_1_MSB REG(0x00, 0xab) /* write */ 138e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark#define REG_VS_PIX_STRT_1_LSB REG(0x00, 0xac) /* write */ 139e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark#define REG_VS_LINE_END_1_MSB REG(0x00, 0xad) /* write */ 140e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark#define REG_VS_LINE_END_1_LSB REG(0x00, 0xae) /* write */ 141e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark#define REG_VS_PIX_END_1_MSB REG(0x00, 0xaf) /* write */ 142e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark#define REG_VS_PIX_END_1_LSB REG(0x00, 0xb0) /* write */ 143088d61d1fdfde56850c157138a6dc08880c1853dSebastian Hesselbarth#define REG_VS_LINE_STRT_2_MSB REG(0x00, 0xb1) /* write */ 144088d61d1fdfde56850c157138a6dc08880c1853dSebastian Hesselbarth#define REG_VS_LINE_STRT_2_LSB REG(0x00, 0xb2) /* write */ 145e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark#define REG_VS_PIX_STRT_2_MSB REG(0x00, 0xb3) /* write */ 146e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark#define REG_VS_PIX_STRT_2_LSB REG(0x00, 0xb4) /* write */ 147088d61d1fdfde56850c157138a6dc08880c1853dSebastian Hesselbarth#define REG_VS_LINE_END_2_MSB REG(0x00, 0xb5) /* write */ 148088d61d1fdfde56850c157138a6dc08880c1853dSebastian Hesselbarth#define REG_VS_LINE_END_2_LSB REG(0x00, 0xb6) /* write */ 149e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark#define REG_VS_PIX_END_2_MSB REG(0x00, 0xb7) /* write */ 150e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark#define REG_VS_PIX_END_2_LSB REG(0x00, 0xb8) /* write */ 151e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark#define REG_HS_PIX_START_MSB REG(0x00, 0xb9) /* write */ 152e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark#define REG_HS_PIX_START_LSB REG(0x00, 0xba) /* write */ 153e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark#define REG_HS_PIX_STOP_MSB REG(0x00, 0xbb) /* write */ 154e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark#define REG_HS_PIX_STOP_LSB REG(0x00, 0xbc) /* write */ 155e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark#define REG_VWIN_START_1_MSB REG(0x00, 0xbd) /* write */ 156e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark#define REG_VWIN_START_1_LSB REG(0x00, 0xbe) /* write */ 157e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark#define REG_VWIN_END_1_MSB REG(0x00, 0xbf) /* write */ 158e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark#define REG_VWIN_END_1_LSB REG(0x00, 0xc0) /* write */ 159088d61d1fdfde56850c157138a6dc08880c1853dSebastian Hesselbarth#define REG_VWIN_START_2_MSB REG(0x00, 0xc1) /* write */ 160088d61d1fdfde56850c157138a6dc08880c1853dSebastian Hesselbarth#define REG_VWIN_START_2_LSB REG(0x00, 0xc2) /* write */ 161088d61d1fdfde56850c157138a6dc08880c1853dSebastian Hesselbarth#define REG_VWIN_END_2_MSB REG(0x00, 0xc3) /* write */ 162088d61d1fdfde56850c157138a6dc08880c1853dSebastian Hesselbarth#define REG_VWIN_END_2_LSB REG(0x00, 0xc4) /* write */ 163e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark#define REG_DE_START_MSB REG(0x00, 0xc5) /* write */ 164e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark#define REG_DE_START_LSB REG(0x00, 0xc6) /* write */ 165e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark#define REG_DE_STOP_MSB REG(0x00, 0xc7) /* write */ 166e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark#define REG_DE_STOP_LSB REG(0x00, 0xc8) /* write */ 167e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark#define REG_TBG_CNTRL_0 REG(0x00, 0xca) /* write */ 168088d61d1fdfde56850c157138a6dc08880c1853dSebastian Hesselbarth# define TBG_CNTRL_0_TOP_TGL (1 << 0) 169088d61d1fdfde56850c157138a6dc08880c1853dSebastian Hesselbarth# define TBG_CNTRL_0_TOP_SEL (1 << 1) 170088d61d1fdfde56850c157138a6dc08880c1853dSebastian Hesselbarth# define TBG_CNTRL_0_DE_EXT (1 << 2) 171088d61d1fdfde56850c157138a6dc08880c1853dSebastian Hesselbarth# define TBG_CNTRL_0_TOP_EXT (1 << 3) 172e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark# define TBG_CNTRL_0_FRAME_DIS (1 << 5) 173e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark# define TBG_CNTRL_0_SYNC_MTHD (1 << 6) 174e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark# define TBG_CNTRL_0_SYNC_ONCE (1 << 7) 175e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark#define REG_TBG_CNTRL_1 REG(0x00, 0xcb) /* write */ 176088d61d1fdfde56850c157138a6dc08880c1853dSebastian Hesselbarth# define TBG_CNTRL_1_H_TGL (1 << 0) 177088d61d1fdfde56850c157138a6dc08880c1853dSebastian Hesselbarth# define TBG_CNTRL_1_V_TGL (1 << 1) 178088d61d1fdfde56850c157138a6dc08880c1853dSebastian Hesselbarth# define TBG_CNTRL_1_TGL_EN (1 << 2) 179088d61d1fdfde56850c157138a6dc08880c1853dSebastian Hesselbarth# define TBG_CNTRL_1_X_EXT (1 << 3) 180088d61d1fdfde56850c157138a6dc08880c1853dSebastian Hesselbarth# define TBG_CNTRL_1_H_EXT (1 << 4) 181088d61d1fdfde56850c157138a6dc08880c1853dSebastian Hesselbarth# define TBG_CNTRL_1_V_EXT (1 << 5) 182e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark# define TBG_CNTRL_1_DWIN_DIS (1 << 6) 183e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark#define REG_ENABLE_SPACE REG(0x00, 0xd6) /* write */ 184e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark#define REG_HVF_CNTRL_0 REG(0x00, 0xe4) /* write */ 185e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark# define HVF_CNTRL_0_SM (1 << 7) 186e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark# define HVF_CNTRL_0_RWB (1 << 6) 187e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark# define HVF_CNTRL_0_PREFIL(x) (((x) & 3) << 2) 188e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark# define HVF_CNTRL_0_INTPOL(x) (((x) & 3) << 0) 189e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark#define REG_HVF_CNTRL_1 REG(0x00, 0xe5) /* write */ 190e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark# define HVF_CNTRL_1_FOR (1 << 0) 191e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark# define HVF_CNTRL_1_YUVBLK (1 << 1) 192e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark# define HVF_CNTRL_1_VQR(x) (((x) & 3) << 2) 193e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark# define HVF_CNTRL_1_PAD(x) (((x) & 3) << 4) 194e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark# define HVF_CNTRL_1_SEMI_PLANAR (1 << 6) 195e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark#define REG_RPT_CNTRL REG(0x00, 0xf0) /* write */ 196c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King#define REG_I2S_FORMAT REG(0x00, 0xfc) /* read/write */ 197c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King# define I2S_FORMAT(x) (((x) & 3) << 0) 198c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King#define REG_AIP_CLKSEL REG(0x00, 0xfd) /* write */ 199c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King# define AIP_CLKSEL_FS(x) (((x) & 3) << 0) 200c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King# define AIP_CLKSEL_CLK_POL(x) (((x) & 1) << 2) 201c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King# define AIP_CLKSEL_AIP(x) (((x) & 7) << 3) 202e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 203e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 204e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark/* Page 02h: PLL settings */ 205e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark#define REG_PLL_SERIAL_1 REG(0x02, 0x00) /* read/write */ 206e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark# define PLL_SERIAL_1_SRL_FDN (1 << 0) 207e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark# define PLL_SERIAL_1_SRL_IZ(x) (((x) & 3) << 1) 208e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark# define PLL_SERIAL_1_SRL_MAN_IZ (1 << 6) 209e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark#define REG_PLL_SERIAL_2 REG(0x02, 0x01) /* read/write */ 210e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark# define PLL_SERIAL_2_SRL_NOSC(x) (((x) & 3) << 0) 211e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark# define PLL_SERIAL_2_SRL_PR(x) (((x) & 0xf) << 4) 212e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark#define REG_PLL_SERIAL_3 REG(0x02, 0x02) /* read/write */ 213e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark# define PLL_SERIAL_3_SRL_CCIR (1 << 0) 214e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark# define PLL_SERIAL_3_SRL_DE (1 << 2) 215e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark# define PLL_SERIAL_3_SRL_PXIN_SEL (1 << 4) 216e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark#define REG_SERIALIZER REG(0x02, 0x03) /* read/write */ 217e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark#define REG_BUFFER_OUT REG(0x02, 0x04) /* read/write */ 218e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark#define REG_PLL_SCG1 REG(0x02, 0x05) /* read/write */ 219e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark#define REG_PLL_SCG2 REG(0x02, 0x06) /* read/write */ 220e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark#define REG_PLL_SCGN1 REG(0x02, 0x07) /* read/write */ 221e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark#define REG_PLL_SCGN2 REG(0x02, 0x08) /* read/write */ 222e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark#define REG_PLL_SCGR1 REG(0x02, 0x09) /* read/write */ 223e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark#define REG_PLL_SCGR2 REG(0x02, 0x0a) /* read/write */ 224e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark#define REG_AUDIO_DIV REG(0x02, 0x0e) /* read/write */ 225c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King# define AUDIO_DIV_SERCLK_1 0 226c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King# define AUDIO_DIV_SERCLK_2 1 227c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King# define AUDIO_DIV_SERCLK_4 2 228c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King# define AUDIO_DIV_SERCLK_8 3 229c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King# define AUDIO_DIV_SERCLK_16 4 230c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King# define AUDIO_DIV_SERCLK_32 5 231e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark#define REG_SEL_CLK REG(0x02, 0x11) /* read/write */ 232e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark# define SEL_CLK_SEL_CLK1 (1 << 0) 233e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark# define SEL_CLK_SEL_VRF_CLK(x) (((x) & 3) << 1) 234e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark# define SEL_CLK_ENA_SC_CLK (1 << 3) 235e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark#define REG_ANA_GENERAL REG(0x02, 0x12) /* read/write */ 236e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 237e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 238e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark/* Page 09h: EDID Control */ 239e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark#define REG_EDID_DATA_0 REG(0x09, 0x00) /* read */ 240e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark/* next 127 successive registers are the EDID block */ 241e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark#define REG_EDID_CTRL REG(0x09, 0xfa) /* read/write */ 242e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark#define REG_DDC_ADDR REG(0x09, 0xfb) /* read/write */ 243e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark#define REG_DDC_OFFS REG(0x09, 0xfc) /* read/write */ 244e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark#define REG_DDC_SEGM_ADDR REG(0x09, 0xfd) /* read/write */ 245e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark#define REG_DDC_SEGM REG(0x09, 0xfe) /* read/write */ 246e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 247e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 248e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark/* Page 10h: information frames and packets */ 249c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King#define REG_IF1_HB0 REG(0x10, 0x20) /* read/write */ 250c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King#define REG_IF2_HB0 REG(0x10, 0x40) /* read/write */ 251c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King#define REG_IF3_HB0 REG(0x10, 0x60) /* read/write */ 252c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King#define REG_IF4_HB0 REG(0x10, 0x80) /* read/write */ 253c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King#define REG_IF5_HB0 REG(0x10, 0xa0) /* read/write */ 254e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 255e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 256e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark/* Page 11h: audio settings and content info packets */ 257e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark#define REG_AIP_CNTRL_0 REG(0x11, 0x00) /* read/write */ 258e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark# define AIP_CNTRL_0_RST_FIFO (1 << 0) 259e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark# define AIP_CNTRL_0_SWAP (1 << 1) 260e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark# define AIP_CNTRL_0_LAYOUT (1 << 2) 261e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark# define AIP_CNTRL_0_ACR_MAN (1 << 5) 262e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark# define AIP_CNTRL_0_RST_CTS (1 << 6) 263c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King#define REG_CA_I2S REG(0x11, 0x01) /* read/write */ 264c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King# define CA_I2S_CA_I2S(x) (((x) & 31) << 0) 265c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King# define CA_I2S_HBR_CHSTAT (1 << 6) 266c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King#define REG_LATENCY_RD REG(0x11, 0x04) /* read/write */ 267c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King#define REG_ACR_CTS_0 REG(0x11, 0x05) /* read/write */ 268c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King#define REG_ACR_CTS_1 REG(0x11, 0x06) /* read/write */ 269c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King#define REG_ACR_CTS_2 REG(0x11, 0x07) /* read/write */ 270c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King#define REG_ACR_N_0 REG(0x11, 0x08) /* read/write */ 271c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King#define REG_ACR_N_1 REG(0x11, 0x09) /* read/write */ 272c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King#define REG_ACR_N_2 REG(0x11, 0x0a) /* read/write */ 273c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King#define REG_CTS_N REG(0x11, 0x0c) /* read/write */ 274c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King# define CTS_N_K(x) (((x) & 7) << 0) 275c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King# define CTS_N_M(x) (((x) & 3) << 4) 276e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark#define REG_ENC_CNTRL REG(0x11, 0x0d) /* read/write */ 277e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark# define ENC_CNTRL_RST_ENC (1 << 0) 278e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark# define ENC_CNTRL_RST_SEL (1 << 1) 279e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark# define ENC_CNTRL_CTL_CODE(x) (((x) & 3) << 2) 280c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King#define REG_DIP_FLAGS REG(0x11, 0x0e) /* read/write */ 281c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King# define DIP_FLAGS_ACR (1 << 0) 282c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King# define DIP_FLAGS_GC (1 << 1) 283c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King#define REG_DIP_IF_FLAGS REG(0x11, 0x0f) /* read/write */ 284c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King# define DIP_IF_FLAGS_IF1 (1 << 1) 285c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King# define DIP_IF_FLAGS_IF2 (1 << 2) 286c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King# define DIP_IF_FLAGS_IF3 (1 << 3) 287c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King# define DIP_IF_FLAGS_IF4 (1 << 4) 288c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King# define DIP_IF_FLAGS_IF5 (1 << 5) 289c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King#define REG_CH_STAT_B(x) REG(0x11, 0x14 + (x)) /* read/write */ 290e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 291e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 292e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark/* Page 12h: HDCP and OTP */ 293e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark#define REG_TX3 REG(0x12, 0x9a) /* read/write */ 294063b472fbb44ac562797a630ac3516720f588140Russell King#define REG_TX4 REG(0x12, 0x9b) /* read/write */ 295063b472fbb44ac562797a630ac3516720f588140Russell King# define TX4_PD_RAM (1 << 1) 296e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark#define REG_TX33 REG(0x12, 0xb8) /* read/write */ 297e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark# define TX33_HDMI (1 << 1) 298e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 299e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 300e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark/* Page 13h: Gamut related metadata packets */ 301e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 302e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 303e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 304e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark/* CEC registers: (not paged) 305e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark */ 306e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark#define REG_CEC_FRO_IM_CLK_CTRL 0xfb /* read/write */ 307e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark# define CEC_FRO_IM_CLK_CTRL_GHOST_DIS (1 << 7) 308e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark# define CEC_FRO_IM_CLK_CTRL_ENA_OTP (1 << 6) 309e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark# define CEC_FRO_IM_CLK_CTRL_IMCLK_SEL (1 << 1) 310e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark# define CEC_FRO_IM_CLK_CTRL_FRO_DIV (1 << 0) 311e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark#define REG_CEC_RXSHPDLEV 0xfe /* read */ 312e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark# define CEC_RXSHPDLEV_RXSENS (1 << 0) 313e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark# define CEC_RXSHPDLEV_HPD (1 << 1) 314e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 315e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark#define REG_CEC_ENAMODS 0xff /* read/write */ 316e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark# define CEC_ENAMODS_DIS_FRO (1 << 6) 317e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark# define CEC_ENAMODS_DIS_CCLK (1 << 5) 318e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark# define CEC_ENAMODS_EN_RXSENS (1 << 2) 319e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark# define CEC_ENAMODS_EN_HDMI (1 << 1) 320e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark# define CEC_ENAMODS_EN_CEC (1 << 0) 321e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 322e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 323e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark/* Device versions: */ 324e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark#define TDA9989N2 0x0101 325e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark#define TDA19989 0x0201 326e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark#define TDA19989N2 0x0202 327e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark#define TDA19988 0x0301 328e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 329e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clarkstatic void 330e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clarkcec_write(struct drm_encoder *encoder, uint16_t addr, uint8_t val) 331e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark{ 332e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark struct i2c_client *client = to_tda998x_priv(encoder)->cec; 333e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark uint8_t buf[] = {addr, val}; 334e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark int ret; 335e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 336e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark ret = i2c_master_send(client, buf, ARRAY_SIZE(buf)); 337e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark if (ret < 0) 338e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark dev_err(&client->dev, "Error %d writing to cec:0x%x\n", ret, addr); 339e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark} 340e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 341e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clarkstatic uint8_t 342e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clarkcec_read(struct drm_encoder *encoder, uint8_t addr) 343e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark{ 344e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark struct i2c_client *client = to_tda998x_priv(encoder)->cec; 345e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark uint8_t val; 346e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark int ret; 347e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 348e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark ret = i2c_master_send(client, &addr, sizeof(addr)); 349e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark if (ret < 0) 350e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark goto fail; 351e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 352e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark ret = i2c_master_recv(client, &val, sizeof(val)); 353e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark if (ret < 0) 354e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark goto fail; 355e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 356e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark return val; 357e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 358e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clarkfail: 359e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark dev_err(&client->dev, "Error %d reading from cec:0x%x\n", ret, addr); 360e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark return 0; 361e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark} 362e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 363e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clarkstatic void 364e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clarkset_page(struct drm_encoder *encoder, uint16_t reg) 365e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark{ 366e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark struct tda998x_priv *priv = to_tda998x_priv(encoder); 367e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 368e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark if (REG2PAGE(reg) != priv->current_page) { 369e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark struct i2c_client *client = drm_i2c_encoder_get_client(encoder); 370e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark uint8_t buf[] = { 371e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark REG_CURPAGE, REG2PAGE(reg) 372e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark }; 373e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark int ret = i2c_master_send(client, buf, sizeof(buf)); 374e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark if (ret < 0) 375e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark dev_err(&client->dev, "Error %d writing to REG_CURPAGE\n", ret); 376e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 377e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark priv->current_page = REG2PAGE(reg); 378e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark } 379e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark} 380e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 381e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clarkstatic int 382e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clarkreg_read_range(struct drm_encoder *encoder, uint16_t reg, char *buf, int cnt) 383e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark{ 384e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark struct i2c_client *client = drm_i2c_encoder_get_client(encoder); 385e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark uint8_t addr = REG2ADDR(reg); 386e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark int ret; 387e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 388e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark set_page(encoder, reg); 389e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 390e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark ret = i2c_master_send(client, &addr, sizeof(addr)); 391e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark if (ret < 0) 392e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark goto fail; 393e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 394e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark ret = i2c_master_recv(client, buf, cnt); 395e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark if (ret < 0) 396e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark goto fail; 397e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 398e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark return ret; 399e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 400e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clarkfail: 401e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark dev_err(&client->dev, "Error %d reading from 0x%x\n", ret, reg); 402e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark return ret; 403e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark} 404e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 405c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell Kingstatic void 406c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell Kingreg_write_range(struct drm_encoder *encoder, uint16_t reg, uint8_t *p, int cnt) 407c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King{ 408c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King struct i2c_client *client = drm_i2c_encoder_get_client(encoder); 409c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King uint8_t buf[cnt+1]; 410c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King int ret; 411c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King 412c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King buf[0] = REG2ADDR(reg); 413c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King memcpy(&buf[1], p, cnt); 414c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King 415c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King set_page(encoder, reg); 416c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King 417c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King ret = i2c_master_send(client, buf, cnt + 1); 418c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King if (ret < 0) 419c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King dev_err(&client->dev, "Error %d writing to 0x%x\n", ret, reg); 420c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King} 421c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King 422e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clarkstatic uint8_t 423e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clarkreg_read(struct drm_encoder *encoder, uint16_t reg) 424e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark{ 425e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark uint8_t val = 0; 426e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark reg_read_range(encoder, reg, &val, sizeof(val)); 427e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark return val; 428e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark} 429e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 430e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clarkstatic void 431e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clarkreg_write(struct drm_encoder *encoder, uint16_t reg, uint8_t val) 432e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark{ 433e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark struct i2c_client *client = drm_i2c_encoder_get_client(encoder); 434e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark uint8_t buf[] = {REG2ADDR(reg), val}; 435e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark int ret; 436e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 437e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark set_page(encoder, reg); 438e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 439e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark ret = i2c_master_send(client, buf, ARRAY_SIZE(buf)); 440e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark if (ret < 0) 441e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark dev_err(&client->dev, "Error %d writing to 0x%x\n", ret, reg); 442e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark} 443e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 444e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clarkstatic void 445e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clarkreg_write16(struct drm_encoder *encoder, uint16_t reg, uint16_t val) 446e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark{ 447e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark struct i2c_client *client = drm_i2c_encoder_get_client(encoder); 448e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark uint8_t buf[] = {REG2ADDR(reg), val >> 8, val}; 449e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark int ret; 450e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 451e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark set_page(encoder, reg); 452e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 453e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark ret = i2c_master_send(client, buf, ARRAY_SIZE(buf)); 454e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark if (ret < 0) 455e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark dev_err(&client->dev, "Error %d writing to 0x%x\n", ret, reg); 456e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark} 457e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 458e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clarkstatic void 459e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clarkreg_set(struct drm_encoder *encoder, uint16_t reg, uint8_t val) 460e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark{ 461e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark reg_write(encoder, reg, reg_read(encoder, reg) | val); 462e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark} 463e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 464e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clarkstatic void 465e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clarkreg_clear(struct drm_encoder *encoder, uint16_t reg, uint8_t val) 466e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark{ 467e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark reg_write(encoder, reg, reg_read(encoder, reg) & ~val); 468e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark} 469e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 470e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clarkstatic void 471e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clarktda998x_reset(struct drm_encoder *encoder) 472e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark{ 473e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark /* reset audio and i2c master: */ 474e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark reg_set(encoder, REG_SOFTRESET, SOFTRESET_AUDIO | SOFTRESET_I2C_MASTER); 475e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark msleep(50); 476e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark reg_clear(encoder, REG_SOFTRESET, SOFTRESET_AUDIO | SOFTRESET_I2C_MASTER); 477e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark msleep(50); 478e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 479e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark /* reset transmitter: */ 480e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark reg_set(encoder, REG_MAIN_CNTRL0, MAIN_CNTRL0_SR); 481e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark reg_clear(encoder, REG_MAIN_CNTRL0, MAIN_CNTRL0_SR); 482e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 483e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark /* PLL registers common configuration */ 484e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark reg_write(encoder, REG_PLL_SERIAL_1, 0x00); 485e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark reg_write(encoder, REG_PLL_SERIAL_2, PLL_SERIAL_2_SRL_NOSC(1)); 486e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark reg_write(encoder, REG_PLL_SERIAL_3, 0x00); 487e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark reg_write(encoder, REG_SERIALIZER, 0x00); 488e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark reg_write(encoder, REG_BUFFER_OUT, 0x00); 489e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark reg_write(encoder, REG_PLL_SCG1, 0x00); 490c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King reg_write(encoder, REG_AUDIO_DIV, AUDIO_DIV_SERCLK_8); 491e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark reg_write(encoder, REG_SEL_CLK, SEL_CLK_SEL_CLK1 | SEL_CLK_ENA_SC_CLK); 492e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark reg_write(encoder, REG_PLL_SCGN1, 0xfa); 493e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark reg_write(encoder, REG_PLL_SCGN2, 0x00); 494e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark reg_write(encoder, REG_PLL_SCGR1, 0x5b); 495e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark reg_write(encoder, REG_PLL_SCGR2, 0x00); 496e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark reg_write(encoder, REG_PLL_SCG2, 0x10); 497bcb2481df01a9aee7a09b20d43194011edd35754Russell King 498bcb2481df01a9aee7a09b20d43194011edd35754Russell King /* Write the default value MUX register */ 499bcb2481df01a9aee7a09b20d43194011edd35754Russell King reg_write(encoder, REG_MUX_VP_VIP_OUT, 0x24); 500e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark} 501e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 502c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell Kingstatic uint8_t tda998x_cksum(uint8_t *buf, size_t bytes) 503c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King{ 504c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King uint8_t sum = 0; 505c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King 506c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King while (bytes--) 507c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King sum += *buf++; 508c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King return (255 - sum) + 1; 509c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King} 510c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King 511c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King#define HB(x) (x) 512c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King#define PB(x) (HB(2) + 1 + (x)) 513c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King 514c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell Kingstatic void 515c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell Kingtda998x_write_if(struct drm_encoder *encoder, uint8_t bit, uint16_t addr, 516c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King uint8_t *buf, size_t size) 517c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King{ 518c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King buf[PB(0)] = tda998x_cksum(buf, size); 519c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King 520c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King reg_clear(encoder, REG_DIP_IF_FLAGS, bit); 521c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King reg_write_range(encoder, addr, buf, size); 522c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King reg_set(encoder, REG_DIP_IF_FLAGS, bit); 523c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King} 524c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King 525c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell Kingstatic void 526c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell Kingtda998x_write_aif(struct drm_encoder *encoder, struct tda998x_encoder_params *p) 527c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King{ 528c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King uint8_t buf[PB(5) + 1]; 529c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King 530c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King buf[HB(0)] = 0x84; 531c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King buf[HB(1)] = 0x01; 532c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King buf[HB(2)] = 10; 533c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King buf[PB(0)] = 0; 534c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King buf[PB(1)] = p->audio_frame[1] & 0x07; /* CC */ 535c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King buf[PB(2)] = p->audio_frame[2] & 0x1c; /* SF */ 536c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King buf[PB(4)] = p->audio_frame[4]; 537c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King buf[PB(5)] = p->audio_frame[5] & 0xf8; /* DM_INH + LSV */ 538c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King 539c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King tda998x_write_if(encoder, DIP_IF_FLAGS_IF4, REG_IF4_HB0, buf, 540c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King sizeof(buf)); 541c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King} 542c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King 543c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell Kingstatic void 544c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell Kingtda998x_write_avi(struct drm_encoder *encoder, struct drm_display_mode *mode) 545c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King{ 546c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King uint8_t buf[PB(13) + 1]; 547c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King 548c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King memset(buf, 0, sizeof(buf)); 549c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King buf[HB(0)] = 0x82; 550c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King buf[HB(1)] = 0x02; 551c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King buf[HB(2)] = 13; 552c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King buf[PB(4)] = drm_match_cea_mode(mode); 553c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King 554c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King tda998x_write_if(encoder, DIP_IF_FLAGS_IF2, REG_IF2_HB0, buf, 555c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King sizeof(buf)); 556c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King} 557c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King 558c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell Kingstatic void tda998x_audio_mute(struct drm_encoder *encoder, bool on) 559c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King{ 560c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King if (on) { 561c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King reg_set(encoder, REG_SOFTRESET, SOFTRESET_AUDIO); 562c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King reg_clear(encoder, REG_SOFTRESET, SOFTRESET_AUDIO); 563c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King reg_set(encoder, REG_AIP_CNTRL_0, AIP_CNTRL_0_RST_FIFO); 564c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King } else { 565c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King reg_clear(encoder, REG_AIP_CNTRL_0, AIP_CNTRL_0_RST_FIFO); 566c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King } 567c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King} 568c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King 569c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell Kingstatic void 570c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell Kingtda998x_configure_audio(struct drm_encoder *encoder, 571c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King struct drm_display_mode *mode, struct tda998x_encoder_params *p) 572c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King{ 573c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King uint8_t buf[6], clksel_aip, clksel_fs, ca_i2s, cts_n, adiv; 574c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King uint32_t n; 575c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King 576c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King /* Enable audio ports */ 577c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King reg_write(encoder, REG_ENA_AP, p->audio_cfg); 578c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King reg_write(encoder, REG_ENA_ACLK, p->audio_clk_cfg); 579c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King 580c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King /* Set audio input source */ 581c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King switch (p->audio_format) { 582c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King case AFMT_SPDIF: 583c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King reg_write(encoder, REG_MUX_AP, 0x40); 584c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King clksel_aip = AIP_CLKSEL_AIP(0); 585c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King /* FS64SPDIF */ 586c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King clksel_fs = AIP_CLKSEL_FS(2); 587c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King cts_n = CTS_N_M(3) | CTS_N_K(3); 588c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King ca_i2s = 0; 589c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King break; 590c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King 591c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King case AFMT_I2S: 592c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King reg_write(encoder, REG_MUX_AP, 0x64); 593c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King clksel_aip = AIP_CLKSEL_AIP(1); 594c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King /* ACLK */ 595c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King clksel_fs = AIP_CLKSEL_FS(0); 596c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King cts_n = CTS_N_M(3) | CTS_N_K(3); 597c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King ca_i2s = CA_I2S_CA_I2S(0); 598c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King break; 599c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King } 600c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King 601c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King reg_write(encoder, REG_AIP_CLKSEL, clksel_aip); 602c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King reg_clear(encoder, REG_AIP_CNTRL_0, AIP_CNTRL_0_LAYOUT); 603c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King 604c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King /* Enable automatic CTS generation */ 605c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King reg_clear(encoder, REG_AIP_CNTRL_0, AIP_CNTRL_0_ACR_MAN); 606c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King reg_write(encoder, REG_CTS_N, cts_n); 607c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King 608c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King /* 609c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King * Audio input somehow depends on HDMI line rate which is 610c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King * related to pixclk. Testing showed that modes with pixclk 611c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King * >100MHz need a larger divider while <40MHz need the default. 612c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King * There is no detailed info in the datasheet, so we just 613c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King * assume 100MHz requires larger divider. 614c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King */ 615c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King if (mode->clock > 100000) 616c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King adiv = AUDIO_DIV_SERCLK_16; 617c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King else 618c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King adiv = AUDIO_DIV_SERCLK_8; 619c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King reg_write(encoder, REG_AUDIO_DIV, adiv); 620c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King 621c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King /* 622c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King * This is the approximate value of N, which happens to be 623c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King * the recommended values for non-coherent clocks. 624c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King */ 625c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King n = 128 * p->audio_sample_rate / 1000; 626c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King 627c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King /* Write the CTS and N values */ 628c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King buf[0] = 0x44; 629c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King buf[1] = 0x42; 630c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King buf[2] = 0x01; 631c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King buf[3] = n; 632c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King buf[4] = n >> 8; 633c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King buf[5] = n >> 16; 634c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King reg_write_range(encoder, REG_ACR_CTS_0, buf, 6); 635c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King 636c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King /* Set CTS clock reference */ 637c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King reg_write(encoder, REG_AIP_CLKSEL, clksel_aip | clksel_fs); 638c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King 639c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King /* Reset CTS generator */ 640c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King reg_set(encoder, REG_AIP_CNTRL_0, AIP_CNTRL_0_RST_CTS); 641c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King reg_clear(encoder, REG_AIP_CNTRL_0, AIP_CNTRL_0_RST_CTS); 642c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King 643c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King /* Write the channel status */ 644c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King buf[0] = 0x04; 645c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King buf[1] = 0x00; 646c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King buf[2] = 0x00; 647c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King buf[3] = 0xf1; 648c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King reg_write_range(encoder, REG_CH_STAT_B(0), buf, 4); 649c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King 650c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King tda998x_audio_mute(encoder, true); 651c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King mdelay(20); 652c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King tda998x_audio_mute(encoder, false); 653c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King 654c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King /* Write the audio information packet */ 655c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King tda998x_write_aif(encoder, p); 656c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King} 657c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King 658e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark/* DRM encoder functions */ 659e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 660e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clarkstatic void 661e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clarktda998x_encoder_set_config(struct drm_encoder *encoder, void *params) 662e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark{ 663c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King struct tda998x_priv *priv = to_tda998x_priv(encoder); 664c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King struct tda998x_encoder_params *p = params; 665c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King 666c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King priv->vip_cntrl_0 = VIP_CNTRL_0_SWAP_A(p->swap_a) | 667c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King (p->mirr_a ? VIP_CNTRL_0_MIRR_A : 0) | 668c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King VIP_CNTRL_0_SWAP_B(p->swap_b) | 669c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King (p->mirr_b ? VIP_CNTRL_0_MIRR_B : 0); 670c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King priv->vip_cntrl_1 = VIP_CNTRL_1_SWAP_C(p->swap_c) | 671c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King (p->mirr_c ? VIP_CNTRL_1_MIRR_C : 0) | 672c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King VIP_CNTRL_1_SWAP_D(p->swap_d) | 673c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King (p->mirr_d ? VIP_CNTRL_1_MIRR_D : 0); 674c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King priv->vip_cntrl_2 = VIP_CNTRL_2_SWAP_E(p->swap_e) | 675c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King (p->mirr_e ? VIP_CNTRL_2_MIRR_E : 0) | 676c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King VIP_CNTRL_2_SWAP_F(p->swap_f) | 677c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King (p->mirr_f ? VIP_CNTRL_2_MIRR_F : 0); 678c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King 679c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King priv->params = *p; 680e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark} 681e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 682e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clarkstatic void 683e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clarktda998x_encoder_dpms(struct drm_encoder *encoder, int mode) 684e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark{ 685e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark struct tda998x_priv *priv = to_tda998x_priv(encoder); 686e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 687e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark /* we only care about on or off: */ 688e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark if (mode != DRM_MODE_DPMS_ON) 689e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark mode = DRM_MODE_DPMS_OFF; 690e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 691e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark if (mode == priv->dpms) 692e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark return; 693e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 694e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark switch (mode) { 695e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark case DRM_MODE_DPMS_ON: 696c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King /* enable video ports, audio will be enabled later */ 697e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark reg_write(encoder, REG_ENA_VP_0, 0xff); 698e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark reg_write(encoder, REG_ENA_VP_1, 0xff); 699e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark reg_write(encoder, REG_ENA_VP_2, 0xff); 700e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark /* set muxing after enabling ports: */ 7015e74c22cd1e0f9e49573fe580de47e198ee04975Russell King reg_write(encoder, REG_VIP_CNTRL_0, priv->vip_cntrl_0); 7025e74c22cd1e0f9e49573fe580de47e198ee04975Russell King reg_write(encoder, REG_VIP_CNTRL_1, priv->vip_cntrl_1); 7035e74c22cd1e0f9e49573fe580de47e198ee04975Russell King reg_write(encoder, REG_VIP_CNTRL_2, priv->vip_cntrl_2); 704e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark break; 705e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark case DRM_MODE_DPMS_OFF: 706e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark /* disable audio and video ports */ 707e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark reg_write(encoder, REG_ENA_AP, 0x00); 708e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark reg_write(encoder, REG_ENA_VP_0, 0x00); 709e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark reg_write(encoder, REG_ENA_VP_1, 0x00); 710e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark reg_write(encoder, REG_ENA_VP_2, 0x00); 711e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark break; 712e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark } 713e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 714e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark priv->dpms = mode; 715e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark} 716e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 717e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clarkstatic void 718e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clarktda998x_encoder_save(struct drm_encoder *encoder) 719e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark{ 720e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark DBG(""); 721e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark} 722e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 723e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clarkstatic void 724e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clarktda998x_encoder_restore(struct drm_encoder *encoder) 725e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark{ 726e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark DBG(""); 727e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark} 728e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 729e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clarkstatic bool 730e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clarktda998x_encoder_mode_fixup(struct drm_encoder *encoder, 731e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark const struct drm_display_mode *mode, 732e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark struct drm_display_mode *adjusted_mode) 733e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark{ 734e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark return true; 735e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark} 736e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 737e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clarkstatic int 738e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clarktda998x_encoder_mode_valid(struct drm_encoder *encoder, 739e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark struct drm_display_mode *mode) 740e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark{ 741e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark return MODE_OK; 742e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark} 743e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 744e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clarkstatic void 745e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clarktda998x_encoder_mode_set(struct drm_encoder *encoder, 746e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark struct drm_display_mode *mode, 747e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark struct drm_display_mode *adjusted_mode) 748e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark{ 749e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark struct tda998x_priv *priv = to_tda998x_priv(encoder); 750088d61d1fdfde56850c157138a6dc08880c1853dSebastian Hesselbarth uint16_t ref_pix, ref_line, n_pix, n_line; 751088d61d1fdfde56850c157138a6dc08880c1853dSebastian Hesselbarth uint16_t hs_pix_s, hs_pix_e; 752088d61d1fdfde56850c157138a6dc08880c1853dSebastian Hesselbarth uint16_t vs1_pix_s, vs1_pix_e, vs1_line_s, vs1_line_e; 753088d61d1fdfde56850c157138a6dc08880c1853dSebastian Hesselbarth uint16_t vs2_pix_s, vs2_pix_e, vs2_line_s, vs2_line_e; 754088d61d1fdfde56850c157138a6dc08880c1853dSebastian Hesselbarth uint16_t vwin1_line_s, vwin1_line_e; 755088d61d1fdfde56850c157138a6dc08880c1853dSebastian Hesselbarth uint16_t vwin2_line_s, vwin2_line_e; 756088d61d1fdfde56850c157138a6dc08880c1853dSebastian Hesselbarth uint16_t de_pix_s, de_pix_e; 757e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark uint8_t reg, div, rep; 758e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 759088d61d1fdfde56850c157138a6dc08880c1853dSebastian Hesselbarth /* 760088d61d1fdfde56850c157138a6dc08880c1853dSebastian Hesselbarth * Internally TDA998x is using ITU-R BT.656 style sync but 761088d61d1fdfde56850c157138a6dc08880c1853dSebastian Hesselbarth * we get VESA style sync. TDA998x is using a reference pixel 762088d61d1fdfde56850c157138a6dc08880c1853dSebastian Hesselbarth * relative to ITU to sync to the input frame and for output 763088d61d1fdfde56850c157138a6dc08880c1853dSebastian Hesselbarth * sync generation. Currently, we are using reference detection 764088d61d1fdfde56850c157138a6dc08880c1853dSebastian Hesselbarth * from HS/VS, i.e. REFPIX/REFLINE denote frame start sync point 765088d61d1fdfde56850c157138a6dc08880c1853dSebastian Hesselbarth * which is position of rising VS with coincident rising HS. 766088d61d1fdfde56850c157138a6dc08880c1853dSebastian Hesselbarth * 767088d61d1fdfde56850c157138a6dc08880c1853dSebastian Hesselbarth * Now there is some issues to take care of: 768088d61d1fdfde56850c157138a6dc08880c1853dSebastian Hesselbarth * - HDMI data islands require sync-before-active 769088d61d1fdfde56850c157138a6dc08880c1853dSebastian Hesselbarth * - TDA998x register values must be > 0 to be enabled 770088d61d1fdfde56850c157138a6dc08880c1853dSebastian Hesselbarth * - REFLINE needs an additional offset of +1 771088d61d1fdfde56850c157138a6dc08880c1853dSebastian Hesselbarth * - REFPIX needs an addtional offset of +1 for UYUV and +3 for RGB 772088d61d1fdfde56850c157138a6dc08880c1853dSebastian Hesselbarth * 773088d61d1fdfde56850c157138a6dc08880c1853dSebastian Hesselbarth * So we add +1 to all horizontal and vertical register values, 774088d61d1fdfde56850c157138a6dc08880c1853dSebastian Hesselbarth * plus an additional +3 for REFPIX as we are using RGB input only. 775e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark */ 776088d61d1fdfde56850c157138a6dc08880c1853dSebastian Hesselbarth n_pix = mode->htotal; 777088d61d1fdfde56850c157138a6dc08880c1853dSebastian Hesselbarth n_line = mode->vtotal; 778088d61d1fdfde56850c157138a6dc08880c1853dSebastian Hesselbarth 779088d61d1fdfde56850c157138a6dc08880c1853dSebastian Hesselbarth hs_pix_e = mode->hsync_end - mode->hdisplay; 780088d61d1fdfde56850c157138a6dc08880c1853dSebastian Hesselbarth hs_pix_s = mode->hsync_start - mode->hdisplay; 781088d61d1fdfde56850c157138a6dc08880c1853dSebastian Hesselbarth de_pix_e = mode->htotal; 782088d61d1fdfde56850c157138a6dc08880c1853dSebastian Hesselbarth de_pix_s = mode->htotal - mode->hdisplay; 783088d61d1fdfde56850c157138a6dc08880c1853dSebastian Hesselbarth ref_pix = 3 + hs_pix_s; 784088d61d1fdfde56850c157138a6dc08880c1853dSebastian Hesselbarth 785179f1aa407b466c06a94f9e54abc948d1e1146e7Sebastian Hesselbarth /* 786179f1aa407b466c06a94f9e54abc948d1e1146e7Sebastian Hesselbarth * Attached LCD controllers may generate broken sync. Allow 787179f1aa407b466c06a94f9e54abc948d1e1146e7Sebastian Hesselbarth * those to adjust the position of the rising VS edge by adding 788179f1aa407b466c06a94f9e54abc948d1e1146e7Sebastian Hesselbarth * HSKEW to ref_pix. 789179f1aa407b466c06a94f9e54abc948d1e1146e7Sebastian Hesselbarth */ 790179f1aa407b466c06a94f9e54abc948d1e1146e7Sebastian Hesselbarth if (adjusted_mode->flags & DRM_MODE_FLAG_HSKEW) 791179f1aa407b466c06a94f9e54abc948d1e1146e7Sebastian Hesselbarth ref_pix += adjusted_mode->hskew; 792179f1aa407b466c06a94f9e54abc948d1e1146e7Sebastian Hesselbarth 793088d61d1fdfde56850c157138a6dc08880c1853dSebastian Hesselbarth if ((mode->flags & DRM_MODE_FLAG_INTERLACE) == 0) { 794088d61d1fdfde56850c157138a6dc08880c1853dSebastian Hesselbarth ref_line = 1 + mode->vsync_start - mode->vdisplay; 795088d61d1fdfde56850c157138a6dc08880c1853dSebastian Hesselbarth vwin1_line_s = mode->vtotal - mode->vdisplay - 1; 796088d61d1fdfde56850c157138a6dc08880c1853dSebastian Hesselbarth vwin1_line_e = vwin1_line_s + mode->vdisplay; 797088d61d1fdfde56850c157138a6dc08880c1853dSebastian Hesselbarth vs1_pix_s = vs1_pix_e = hs_pix_s; 798088d61d1fdfde56850c157138a6dc08880c1853dSebastian Hesselbarth vs1_line_s = mode->vsync_start - mode->vdisplay; 799088d61d1fdfde56850c157138a6dc08880c1853dSebastian Hesselbarth vs1_line_e = vs1_line_s + 800088d61d1fdfde56850c157138a6dc08880c1853dSebastian Hesselbarth mode->vsync_end - mode->vsync_start; 801088d61d1fdfde56850c157138a6dc08880c1853dSebastian Hesselbarth vwin2_line_s = vwin2_line_e = 0; 802088d61d1fdfde56850c157138a6dc08880c1853dSebastian Hesselbarth vs2_pix_s = vs2_pix_e = 0; 803088d61d1fdfde56850c157138a6dc08880c1853dSebastian Hesselbarth vs2_line_s = vs2_line_e = 0; 804088d61d1fdfde56850c157138a6dc08880c1853dSebastian Hesselbarth } else { 805088d61d1fdfde56850c157138a6dc08880c1853dSebastian Hesselbarth ref_line = 1 + (mode->vsync_start - mode->vdisplay)/2; 806088d61d1fdfde56850c157138a6dc08880c1853dSebastian Hesselbarth vwin1_line_s = (mode->vtotal - mode->vdisplay)/2; 807088d61d1fdfde56850c157138a6dc08880c1853dSebastian Hesselbarth vwin1_line_e = vwin1_line_s + mode->vdisplay/2; 808088d61d1fdfde56850c157138a6dc08880c1853dSebastian Hesselbarth vs1_pix_s = vs1_pix_e = hs_pix_s; 809088d61d1fdfde56850c157138a6dc08880c1853dSebastian Hesselbarth vs1_line_s = (mode->vsync_start - mode->vdisplay)/2; 810088d61d1fdfde56850c157138a6dc08880c1853dSebastian Hesselbarth vs1_line_e = vs1_line_s + 811088d61d1fdfde56850c157138a6dc08880c1853dSebastian Hesselbarth (mode->vsync_end - mode->vsync_start)/2; 812088d61d1fdfde56850c157138a6dc08880c1853dSebastian Hesselbarth vwin2_line_s = vwin1_line_s + mode->vtotal/2; 813088d61d1fdfde56850c157138a6dc08880c1853dSebastian Hesselbarth vwin2_line_e = vwin2_line_s + mode->vdisplay/2; 814088d61d1fdfde56850c157138a6dc08880c1853dSebastian Hesselbarth vs2_pix_s = vs2_pix_e = hs_pix_s + mode->htotal/2; 815088d61d1fdfde56850c157138a6dc08880c1853dSebastian Hesselbarth vs2_line_s = vs1_line_s + mode->vtotal/2 ; 816088d61d1fdfde56850c157138a6dc08880c1853dSebastian Hesselbarth vs2_line_e = vs2_line_s + 817088d61d1fdfde56850c157138a6dc08880c1853dSebastian Hesselbarth (mode->vsync_end - mode->vsync_start)/2; 818088d61d1fdfde56850c157138a6dc08880c1853dSebastian Hesselbarth } 819e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 820e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark div = 148500 / mode->clock; 821e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 822e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark /* mute the audio FIFO: */ 823e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark reg_set(encoder, REG_AIP_CNTRL_0, AIP_CNTRL_0_RST_FIFO); 824e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 825e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark /* set HDMI HDCP mode off: */ 826e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark reg_set(encoder, REG_TBG_CNTRL_1, TBG_CNTRL_1_DWIN_DIS); 827e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark reg_clear(encoder, REG_TX33, TX33_HDMI); 828e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 829e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark reg_write(encoder, REG_ENC_CNTRL, ENC_CNTRL_CTL_CODE(0)); 830e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark /* no pre-filter or interpolator: */ 831e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark reg_write(encoder, REG_HVF_CNTRL_0, HVF_CNTRL_0_PREFIL(0) | 832e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark HVF_CNTRL_0_INTPOL(0)); 833e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark reg_write(encoder, REG_VIP_CNTRL_5, VIP_CNTRL_5_SP_CNT(0)); 834e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark reg_write(encoder, REG_VIP_CNTRL_4, VIP_CNTRL_4_BLANKIT(0) | 835e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark VIP_CNTRL_4_BLC(0)); 836e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark reg_clear(encoder, REG_PLL_SERIAL_3, PLL_SERIAL_3_SRL_CCIR); 837e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 838e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark reg_clear(encoder, REG_PLL_SERIAL_1, PLL_SERIAL_1_SRL_MAN_IZ); 839e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark reg_clear(encoder, REG_PLL_SERIAL_3, PLL_SERIAL_3_SRL_DE); 840e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark reg_write(encoder, REG_SERIALIZER, 0); 841e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark reg_write(encoder, REG_HVF_CNTRL_1, HVF_CNTRL_1_VQR(0)); 842e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 843e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark /* TODO enable pixel repeat for pixel rates less than 25Msamp/s */ 844e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark rep = 0; 845e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark reg_write(encoder, REG_RPT_CNTRL, 0); 846e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark reg_write(encoder, REG_SEL_CLK, SEL_CLK_SEL_VRF_CLK(0) | 847e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark SEL_CLK_SEL_CLK1 | SEL_CLK_ENA_SC_CLK); 848e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 849e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark reg_write(encoder, REG_PLL_SERIAL_2, PLL_SERIAL_2_SRL_NOSC(div) | 850e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark PLL_SERIAL_2_SRL_PR(rep)); 851e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 852e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark /* set color matrix bypass flag: */ 853e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark reg_set(encoder, REG_MAT_CONTRL, MAT_CONTRL_MAT_BP); 854e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 855e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark /* set BIAS tmds value: */ 856e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark reg_write(encoder, REG_ANA_GENERAL, 0x09); 857e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 858e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark reg_clear(encoder, REG_TBG_CNTRL_0, TBG_CNTRL_0_SYNC_MTHD); 859e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 860088d61d1fdfde56850c157138a6dc08880c1853dSebastian Hesselbarth /* 861088d61d1fdfde56850c157138a6dc08880c1853dSebastian Hesselbarth * Sync on rising HSYNC/VSYNC 862088d61d1fdfde56850c157138a6dc08880c1853dSebastian Hesselbarth */ 863e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark reg_write(encoder, REG_VIP_CNTRL_3, 0); 864e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark reg_set(encoder, REG_VIP_CNTRL_3, VIP_CNTRL_3_SYNC_HS); 865088d61d1fdfde56850c157138a6dc08880c1853dSebastian Hesselbarth 866088d61d1fdfde56850c157138a6dc08880c1853dSebastian Hesselbarth /* 867088d61d1fdfde56850c157138a6dc08880c1853dSebastian Hesselbarth * TDA19988 requires high-active sync at input stage, 868088d61d1fdfde56850c157138a6dc08880c1853dSebastian Hesselbarth * so invert low-active sync provided by master encoder here 869088d61d1fdfde56850c157138a6dc08880c1853dSebastian Hesselbarth */ 870088d61d1fdfde56850c157138a6dc08880c1853dSebastian Hesselbarth if (mode->flags & DRM_MODE_FLAG_NHSYNC) 871088d61d1fdfde56850c157138a6dc08880c1853dSebastian Hesselbarth reg_set(encoder, REG_VIP_CNTRL_3, VIP_CNTRL_3_H_TGL); 872e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark if (mode->flags & DRM_MODE_FLAG_NVSYNC) 873e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark reg_set(encoder, REG_VIP_CNTRL_3, VIP_CNTRL_3_V_TGL); 874e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 875088d61d1fdfde56850c157138a6dc08880c1853dSebastian Hesselbarth /* 876088d61d1fdfde56850c157138a6dc08880c1853dSebastian Hesselbarth * Always generate sync polarity relative to input sync and 877088d61d1fdfde56850c157138a6dc08880c1853dSebastian Hesselbarth * revert input stage toggled sync at output stage 878088d61d1fdfde56850c157138a6dc08880c1853dSebastian Hesselbarth */ 879088d61d1fdfde56850c157138a6dc08880c1853dSebastian Hesselbarth reg = TBG_CNTRL_1_TGL_EN; 880e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark if (mode->flags & DRM_MODE_FLAG_NHSYNC) 881088d61d1fdfde56850c157138a6dc08880c1853dSebastian Hesselbarth reg |= TBG_CNTRL_1_H_TGL; 882088d61d1fdfde56850c157138a6dc08880c1853dSebastian Hesselbarth if (mode->flags & DRM_MODE_FLAG_NVSYNC) 883088d61d1fdfde56850c157138a6dc08880c1853dSebastian Hesselbarth reg |= TBG_CNTRL_1_V_TGL; 884088d61d1fdfde56850c157138a6dc08880c1853dSebastian Hesselbarth reg_write(encoder, REG_TBG_CNTRL_1, reg); 885e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 886e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark reg_write(encoder, REG_VIDFORMAT, 0x00); 887088d61d1fdfde56850c157138a6dc08880c1853dSebastian Hesselbarth reg_write16(encoder, REG_REFPIX_MSB, ref_pix); 888088d61d1fdfde56850c157138a6dc08880c1853dSebastian Hesselbarth reg_write16(encoder, REG_REFLINE_MSB, ref_line); 889088d61d1fdfde56850c157138a6dc08880c1853dSebastian Hesselbarth reg_write16(encoder, REG_NPIX_MSB, n_pix); 890088d61d1fdfde56850c157138a6dc08880c1853dSebastian Hesselbarth reg_write16(encoder, REG_NLINE_MSB, n_line); 891088d61d1fdfde56850c157138a6dc08880c1853dSebastian Hesselbarth reg_write16(encoder, REG_VS_LINE_STRT_1_MSB, vs1_line_s); 892088d61d1fdfde56850c157138a6dc08880c1853dSebastian Hesselbarth reg_write16(encoder, REG_VS_PIX_STRT_1_MSB, vs1_pix_s); 893088d61d1fdfde56850c157138a6dc08880c1853dSebastian Hesselbarth reg_write16(encoder, REG_VS_LINE_END_1_MSB, vs1_line_e); 894088d61d1fdfde56850c157138a6dc08880c1853dSebastian Hesselbarth reg_write16(encoder, REG_VS_PIX_END_1_MSB, vs1_pix_e); 895088d61d1fdfde56850c157138a6dc08880c1853dSebastian Hesselbarth reg_write16(encoder, REG_VS_LINE_STRT_2_MSB, vs2_line_s); 896088d61d1fdfde56850c157138a6dc08880c1853dSebastian Hesselbarth reg_write16(encoder, REG_VS_PIX_STRT_2_MSB, vs2_pix_s); 897088d61d1fdfde56850c157138a6dc08880c1853dSebastian Hesselbarth reg_write16(encoder, REG_VS_LINE_END_2_MSB, vs2_line_e); 898088d61d1fdfde56850c157138a6dc08880c1853dSebastian Hesselbarth reg_write16(encoder, REG_VS_PIX_END_2_MSB, vs2_pix_e); 899088d61d1fdfde56850c157138a6dc08880c1853dSebastian Hesselbarth reg_write16(encoder, REG_HS_PIX_START_MSB, hs_pix_s); 900088d61d1fdfde56850c157138a6dc08880c1853dSebastian Hesselbarth reg_write16(encoder, REG_HS_PIX_STOP_MSB, hs_pix_e); 901088d61d1fdfde56850c157138a6dc08880c1853dSebastian Hesselbarth reg_write16(encoder, REG_VWIN_START_1_MSB, vwin1_line_s); 902088d61d1fdfde56850c157138a6dc08880c1853dSebastian Hesselbarth reg_write16(encoder, REG_VWIN_END_1_MSB, vwin1_line_e); 903088d61d1fdfde56850c157138a6dc08880c1853dSebastian Hesselbarth reg_write16(encoder, REG_VWIN_START_2_MSB, vwin2_line_s); 904088d61d1fdfde56850c157138a6dc08880c1853dSebastian Hesselbarth reg_write16(encoder, REG_VWIN_END_2_MSB, vwin2_line_e); 905088d61d1fdfde56850c157138a6dc08880c1853dSebastian Hesselbarth reg_write16(encoder, REG_DE_START_MSB, de_pix_s); 906088d61d1fdfde56850c157138a6dc08880c1853dSebastian Hesselbarth reg_write16(encoder, REG_DE_STOP_MSB, de_pix_e); 907e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 908e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark if (priv->rev == TDA19988) { 909e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark /* let incoming pixels fill the active space (if any) */ 910e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark reg_write(encoder, REG_ENABLE_SPACE, 0x01); 911e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark } 912e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 913e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark /* must be last register set: */ 914e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark reg_clear(encoder, REG_TBG_CNTRL_0, TBG_CNTRL_0_SYNC_ONCE); 915c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King 916c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King /* Only setup the info frames if the sink is HDMI */ 917c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King if (priv->is_hdmi_sink) { 918c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King /* We need to turn HDMI HDCP stuff on to get audio through */ 919c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King reg_clear(encoder, REG_TBG_CNTRL_1, TBG_CNTRL_1_DWIN_DIS); 920c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King reg_write(encoder, REG_ENC_CNTRL, ENC_CNTRL_CTL_CODE(1)); 921c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King reg_set(encoder, REG_TX33, TX33_HDMI); 922c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King 923c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King tda998x_write_avi(encoder, adjusted_mode); 924c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King 925c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King if (priv->params.audio_cfg) 926c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King tda998x_configure_audio(encoder, adjusted_mode, 927c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King &priv->params); 928c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King } 929e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark} 930e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 931e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clarkstatic enum drm_connector_status 932e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clarktda998x_encoder_detect(struct drm_encoder *encoder, 933e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark struct drm_connector *connector) 934e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark{ 935e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark uint8_t val = cec_read(encoder, REG_CEC_RXSHPDLEV); 936e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark return (val & CEC_RXSHPDLEV_HPD) ? connector_status_connected : 937e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark connector_status_disconnected; 938e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark} 939e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 940e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clarkstatic int 941e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clarkread_edid_block(struct drm_encoder *encoder, uint8_t *buf, int blk) 942e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark{ 943e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark uint8_t offset, segptr; 944e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark int ret, i; 945e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 946e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark /* enable EDID read irq: */ 947e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark reg_set(encoder, REG_INT_FLAGS_2, INT_FLAGS_2_EDID_BLK_RD); 948e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 949e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark offset = (blk & 1) ? 128 : 0; 950e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark segptr = blk / 2; 951e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 952e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark reg_write(encoder, REG_DDC_ADDR, 0xa0); 953e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark reg_write(encoder, REG_DDC_OFFS, offset); 954e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark reg_write(encoder, REG_DDC_SEGM_ADDR, 0x60); 955e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark reg_write(encoder, REG_DDC_SEGM, segptr); 956e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 957e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark /* enable reading EDID: */ 958e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark reg_write(encoder, REG_EDID_CTRL, 0x1); 959e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 960e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark /* flag must be cleared by sw: */ 961e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark reg_write(encoder, REG_EDID_CTRL, 0x0); 962e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 963e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark /* wait for block read to complete: */ 964e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark for (i = 100; i > 0; i--) { 965e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark uint8_t val = reg_read(encoder, REG_INT_FLAGS_2); 966e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark if (val & INT_FLAGS_2_EDID_BLK_RD) 967e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark break; 968e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark msleep(1); 969e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark } 970e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 971e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark if (i == 0) 972e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark return -ETIMEDOUT; 973e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 974e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark ret = reg_read_range(encoder, REG_EDID_DATA_0, buf, EDID_LENGTH); 975e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark if (ret != EDID_LENGTH) { 976e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark dev_err(encoder->dev->dev, "failed to read edid block %d: %d", 977e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark blk, ret); 978e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark return ret; 979e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark } 980e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 981e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark reg_clear(encoder, REG_INT_FLAGS_2, INT_FLAGS_2_EDID_BLK_RD); 982e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 983e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark return 0; 984e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark} 985e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 986e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clarkstatic uint8_t * 987e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clarkdo_get_edid(struct drm_encoder *encoder) 988e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark{ 989063b472fbb44ac562797a630ac3516720f588140Russell King struct tda998x_priv *priv = to_tda998x_priv(encoder); 990e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark int j = 0, valid_extensions = 0; 991e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark uint8_t *block, *new; 992e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark bool print_bad_edid = drm_debug & DRM_UT_KMS; 993e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 994e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark if ((block = kmalloc(EDID_LENGTH, GFP_KERNEL)) == NULL) 995e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark return NULL; 996e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 997063b472fbb44ac562797a630ac3516720f588140Russell King if (priv->rev == TDA19988) 998063b472fbb44ac562797a630ac3516720f588140Russell King reg_clear(encoder, REG_TX4, TX4_PD_RAM); 999063b472fbb44ac562797a630ac3516720f588140Russell King 1000e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark /* base block fetch */ 1001e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark if (read_edid_block(encoder, block, 0)) 1002e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark goto fail; 1003e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 1004e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark if (!drm_edid_block_valid(block, 0, print_bad_edid)) 1005e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark goto fail; 1006e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 1007e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark /* if there's no extensions, we're done */ 1008e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark if (block[0x7e] == 0) 1009063b472fbb44ac562797a630ac3516720f588140Russell King goto done; 1010e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 1011e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark new = krealloc(block, (block[0x7e] + 1) * EDID_LENGTH, GFP_KERNEL); 1012e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark if (!new) 1013e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark goto fail; 1014e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark block = new; 1015e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 1016e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark for (j = 1; j <= block[0x7e]; j++) { 1017e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark uint8_t *ext_block = block + (valid_extensions + 1) * EDID_LENGTH; 1018e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark if (read_edid_block(encoder, ext_block, j)) 1019e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark goto fail; 1020e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 1021e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark if (!drm_edid_block_valid(ext_block, j, print_bad_edid)) 1022e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark goto fail; 1023e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 1024e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark valid_extensions++; 1025e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark } 1026e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 1027e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark if (valid_extensions != block[0x7e]) { 1028e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark block[EDID_LENGTH-1] += block[0x7e] - valid_extensions; 1029e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark block[0x7e] = valid_extensions; 1030e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark new = krealloc(block, (valid_extensions + 1) * EDID_LENGTH, GFP_KERNEL); 1031e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark if (!new) 1032e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark goto fail; 1033e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark block = new; 1034e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark } 1035e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 1036063b472fbb44ac562797a630ac3516720f588140Russell Kingdone: 1037063b472fbb44ac562797a630ac3516720f588140Russell King if (priv->rev == TDA19988) 1038063b472fbb44ac562797a630ac3516720f588140Russell King reg_set(encoder, REG_TX4, TX4_PD_RAM); 1039063b472fbb44ac562797a630ac3516720f588140Russell King 1040e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark return block; 1041e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 1042e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clarkfail: 1043063b472fbb44ac562797a630ac3516720f588140Russell King if (priv->rev == TDA19988) 1044063b472fbb44ac562797a630ac3516720f588140Russell King reg_set(encoder, REG_TX4, TX4_PD_RAM); 1045e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark dev_warn(encoder->dev->dev, "failed to read EDID\n"); 1046e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark kfree(block); 1047e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark return NULL; 1048e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark} 1049e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 1050e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clarkstatic int 1051e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clarktda998x_encoder_get_modes(struct drm_encoder *encoder, 1052e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark struct drm_connector *connector) 1053e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark{ 1054c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King struct tda998x_priv *priv = to_tda998x_priv(encoder); 1055e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark struct edid *edid = (struct edid *)do_get_edid(encoder); 1056e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark int n = 0; 1057e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 1058e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark if (edid) { 1059e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark drm_mode_connector_update_edid_property(connector, edid); 1060e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark n = drm_add_edid_modes(connector, edid); 1061c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King priv->is_hdmi_sink = drm_detect_hdmi_monitor(edid); 1062e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark kfree(edid); 1063e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark } 1064e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 1065e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark return n; 1066e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark} 1067e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 1068e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clarkstatic int 1069e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clarktda998x_encoder_create_resources(struct drm_encoder *encoder, 1070e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark struct drm_connector *connector) 1071e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark{ 1072e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark DBG(""); 1073e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark return 0; 1074e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark} 1075e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 1076e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clarkstatic int 1077e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clarktda998x_encoder_set_property(struct drm_encoder *encoder, 1078e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark struct drm_connector *connector, 1079e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark struct drm_property *property, 1080e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark uint64_t val) 1081e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark{ 1082e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark DBG(""); 1083e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark return 0; 1084e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark} 1085e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 1086e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clarkstatic void 1087e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clarktda998x_encoder_destroy(struct drm_encoder *encoder) 1088e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark{ 1089e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark struct tda998x_priv *priv = to_tda998x_priv(encoder); 1090e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark drm_i2c_encoder_destroy(encoder); 1091e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark kfree(priv); 1092e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark} 1093e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 1094e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clarkstatic struct drm_encoder_slave_funcs tda998x_encoder_funcs = { 1095e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark .set_config = tda998x_encoder_set_config, 1096e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark .destroy = tda998x_encoder_destroy, 1097e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark .dpms = tda998x_encoder_dpms, 1098e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark .save = tda998x_encoder_save, 1099e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark .restore = tda998x_encoder_restore, 1100e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark .mode_fixup = tda998x_encoder_mode_fixup, 1101e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark .mode_valid = tda998x_encoder_mode_valid, 1102e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark .mode_set = tda998x_encoder_mode_set, 1103e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark .detect = tda998x_encoder_detect, 1104e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark .get_modes = tda998x_encoder_get_modes, 1105e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark .create_resources = tda998x_encoder_create_resources, 1106e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark .set_property = tda998x_encoder_set_property, 1107e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark}; 1108e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 1109e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark/* I2C driver functions */ 1110e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 1111e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clarkstatic int 1112e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clarktda998x_probe(struct i2c_client *client, const struct i2c_device_id *id) 1113e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark{ 1114e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark return 0; 1115e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark} 1116e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 1117e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clarkstatic int 1118e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clarktda998x_remove(struct i2c_client *client) 1119e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark{ 1120e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark return 0; 1121e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark} 1122e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 1123e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clarkstatic int 1124e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clarktda998x_encoder_init(struct i2c_client *client, 1125e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark struct drm_device *dev, 1126e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark struct drm_encoder_slave *encoder_slave) 1127e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark{ 1128e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark struct drm_encoder *encoder = &encoder_slave->base; 1129e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark struct tda998x_priv *priv; 1130e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 1131e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark priv = kzalloc(sizeof(*priv), GFP_KERNEL); 1132e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark if (!priv) 1133e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark return -ENOMEM; 1134e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 11355e74c22cd1e0f9e49573fe580de47e198ee04975Russell King priv->vip_cntrl_0 = VIP_CNTRL_0_SWAP_A(2) | VIP_CNTRL_0_SWAP_B(3); 11365e74c22cd1e0f9e49573fe580de47e198ee04975Russell King priv->vip_cntrl_1 = VIP_CNTRL_1_SWAP_C(0) | VIP_CNTRL_1_SWAP_D(1); 11375e74c22cd1e0f9e49573fe580de47e198ee04975Russell King priv->vip_cntrl_2 = VIP_CNTRL_2_SWAP_E(4) | VIP_CNTRL_2_SWAP_F(5); 11385e74c22cd1e0f9e49573fe580de47e198ee04975Russell King 1139e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark priv->current_page = 0; 1140e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark priv->cec = i2c_new_dummy(client->adapter, 0x34); 1141e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark priv->dpms = DRM_MODE_DPMS_OFF; 1142e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 1143e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark encoder_slave->slave_priv = priv; 1144e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark encoder_slave->slave_funcs = &tda998x_encoder_funcs; 1145e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 1146e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark /* wake up the device: */ 1147e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark cec_write(encoder, REG_CEC_ENAMODS, 1148e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark CEC_ENAMODS_EN_RXSENS | CEC_ENAMODS_EN_HDMI); 1149e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 1150e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark tda998x_reset(encoder); 1151e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 1152e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark /* read version: */ 1153e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark priv->rev = reg_read(encoder, REG_VERSION_LSB) | 1154e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark reg_read(encoder, REG_VERSION_MSB) << 8; 1155e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 1156e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark /* mask off feature bits: */ 1157e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark priv->rev &= ~0x30; /* not-hdcp and not-scalar bit */ 1158e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 1159e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark switch (priv->rev) { 1160e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark case TDA9989N2: dev_info(dev->dev, "found TDA9989 n2"); break; 1161e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark case TDA19989: dev_info(dev->dev, "found TDA19989"); break; 1162e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark case TDA19989N2: dev_info(dev->dev, "found TDA19989 n2"); break; 1163e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark case TDA19988: dev_info(dev->dev, "found TDA19988"); break; 1164e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark default: 1165e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark DBG("found unsupported device: %04x", priv->rev); 1166e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark goto fail; 1167e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark } 1168e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 1169e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark /* after reset, enable DDC: */ 1170e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark reg_write(encoder, REG_DDC_DISABLE, 0x00); 1171e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 1172e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark /* set clock on DDC channel: */ 1173e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark reg_write(encoder, REG_TX3, 39); 1174e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 1175e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark /* if necessary, disable multi-master: */ 1176e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark if (priv->rev == TDA19989) 1177e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark reg_set(encoder, REG_I2C_MASTER, I2C_MASTER_DIS_MM); 1178e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 1179e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark cec_write(encoder, REG_CEC_FRO_IM_CLK_CTRL, 1180e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark CEC_FRO_IM_CLK_CTRL_GHOST_DIS | CEC_FRO_IM_CLK_CTRL_IMCLK_SEL); 1181e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 1182e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark return 0; 1183e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 1184e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clarkfail: 1185e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark /* if encoder_init fails, the encoder slave is never registered, 1186e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark * so cleanup here: 1187e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark */ 1188e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark if (priv->cec) 1189e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark i2c_unregister_device(priv->cec); 1190e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark kfree(priv); 1191e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark encoder_slave->slave_priv = NULL; 1192e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark encoder_slave->slave_funcs = NULL; 1193e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark return -ENXIO; 1194e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark} 1195e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 1196e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clarkstatic struct i2c_device_id tda998x_ids[] = { 1197e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark { "tda998x", 0 }, 1198e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark { } 1199e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark}; 1200e7792ce2da5ded80861db787ace9b57ecf7bc96cRob ClarkMODULE_DEVICE_TABLE(i2c, tda998x_ids); 1201e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 1202e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clarkstatic struct drm_i2c_encoder_driver tda998x_driver = { 1203e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark .i2c_driver = { 1204e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark .probe = tda998x_probe, 1205e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark .remove = tda998x_remove, 1206e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark .driver = { 1207e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark .name = "tda998x", 1208e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark }, 1209e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark .id_table = tda998x_ids, 1210e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark }, 1211e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark .encoder_init = tda998x_encoder_init, 1212e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark}; 1213e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 1214e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark/* Module initialization */ 1215e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 1216e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clarkstatic int __init 1217e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clarktda998x_init(void) 1218e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark{ 1219e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark DBG(""); 1220e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark return drm_i2c_encoder_register(THIS_MODULE, &tda998x_driver); 1221e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark} 1222e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 1223e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clarkstatic void __exit 1224e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clarktda998x_exit(void) 1225e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark{ 1226e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark DBG(""); 1227e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark drm_i2c_encoder_unregister(&tda998x_driver); 1228e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark} 1229e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 1230e7792ce2da5ded80861db787ace9b57ecf7bc96cRob ClarkMODULE_AUTHOR("Rob Clark <robdclark@gmail.com"); 1231e7792ce2da5ded80861db787ace9b57ecf7bc96cRob ClarkMODULE_DESCRIPTION("NXP Semiconductors TDA998X HDMI Encoder"); 1232e7792ce2da5ded80861db787ace9b57ecf7bc96cRob ClarkMODULE_LICENSE("GPL"); 1233e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 1234e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clarkmodule_init(tda998x_init); 1235e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clarkmodule_exit(tda998x_exit); 1236