tda998x_drv.c revision c4c11dd160a8cc98f402c4e12f94b1572e822ffd
1e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark/* 2e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark * Copyright (C) 2012 Texas Instruments 3e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark * Author: Rob Clark <robdclark@gmail.com> 4e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark * 5e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark * This program is free software; you can redistribute it and/or modify it 6e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark * under the terms of the GNU General Public License version 2 as published by 7e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark * the Free Software Foundation. 8e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark * 9e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark * This program is distributed in the hope that it will be useful, but WITHOUT 10e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark * more details. 13e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark * 14e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark * You should have received a copy of the GNU General Public License along with 15e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark * this program. If not, see <http://www.gnu.org/licenses/>. 16e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark */ 17e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 18e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 19e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 20e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark#include <linux/module.h> 21e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 22e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark#include <drm/drmP.h> 23e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark#include <drm/drm_crtc_helper.h> 24e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark#include <drm/drm_encoder_slave.h> 25e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark#include <drm/drm_edid.h> 26c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King#include <drm/i2c/tda998x.h> 27e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 28e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark#define DBG(fmt, ...) DRM_DEBUG(fmt"\n", ##__VA_ARGS__) 29e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 30e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clarkstruct tda998x_priv { 31e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark struct i2c_client *cec; 32e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark uint16_t rev; 33e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark uint8_t current_page; 34e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark int dpms; 35c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King bool is_hdmi_sink; 365e74c22cd1e0f9e49573fe580de47e198ee04975Russell King u8 vip_cntrl_0; 375e74c22cd1e0f9e49573fe580de47e198ee04975Russell King u8 vip_cntrl_1; 385e74c22cd1e0f9e49573fe580de47e198ee04975Russell King u8 vip_cntrl_2; 39c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King struct tda998x_encoder_params params; 40e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark}; 41e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 42e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark#define to_tda998x_priv(x) ((struct tda998x_priv *)to_encoder_slave(x)->slave_priv) 43e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 44e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark/* The TDA9988 series of devices use a paged register scheme.. to simplify 45e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark * things we encode the page # in upper bits of the register #. To read/ 46e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark * write a given register, we need to make sure CURPAGE register is set 47e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark * appropriately. Which implies reads/writes are not atomic. Fun! 48e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark */ 49e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 50e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark#define REG(page, addr) (((page) << 8) | (addr)) 51e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark#define REG2ADDR(reg) ((reg) & 0xff) 52e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark#define REG2PAGE(reg) (((reg) >> 8) & 0xff) 53e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 54e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark#define REG_CURPAGE 0xff /* write */ 55e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 56e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 57e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark/* Page 00h: General Control */ 58e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark#define REG_VERSION_LSB REG(0x00, 0x00) /* read */ 59e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark#define REG_MAIN_CNTRL0 REG(0x00, 0x01) /* read/write */ 60e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark# define MAIN_CNTRL0_SR (1 << 0) 61e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark# define MAIN_CNTRL0_DECS (1 << 1) 62e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark# define MAIN_CNTRL0_DEHS (1 << 2) 63e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark# define MAIN_CNTRL0_CECS (1 << 3) 64e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark# define MAIN_CNTRL0_CEHS (1 << 4) 65e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark# define MAIN_CNTRL0_SCALER (1 << 7) 66e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark#define REG_VERSION_MSB REG(0x00, 0x02) /* read */ 67e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark#define REG_SOFTRESET REG(0x00, 0x0a) /* write */ 68e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark# define SOFTRESET_AUDIO (1 << 0) 69e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark# define SOFTRESET_I2C_MASTER (1 << 1) 70e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark#define REG_DDC_DISABLE REG(0x00, 0x0b) /* read/write */ 71e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark#define REG_CCLK_ON REG(0x00, 0x0c) /* read/write */ 72e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark#define REG_I2C_MASTER REG(0x00, 0x0d) /* read/write */ 73e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark# define I2C_MASTER_DIS_MM (1 << 0) 74e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark# define I2C_MASTER_DIS_FILT (1 << 1) 75e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark# define I2C_MASTER_APP_STRT_LAT (1 << 2) 76c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King#define REG_FEAT_POWERDOWN REG(0x00, 0x0e) /* read/write */ 77c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King# define FEAT_POWERDOWN_SPDIF (1 << 3) 78e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark#define REG_INT_FLAGS_0 REG(0x00, 0x0f) /* read/write */ 79e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark#define REG_INT_FLAGS_1 REG(0x00, 0x10) /* read/write */ 80e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark#define REG_INT_FLAGS_2 REG(0x00, 0x11) /* read/write */ 81e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark# define INT_FLAGS_2_EDID_BLK_RD (1 << 1) 82c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King#define REG_ENA_ACLK REG(0x00, 0x16) /* read/write */ 83e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark#define REG_ENA_VP_0 REG(0x00, 0x18) /* read/write */ 84e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark#define REG_ENA_VP_1 REG(0x00, 0x19) /* read/write */ 85e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark#define REG_ENA_VP_2 REG(0x00, 0x1a) /* read/write */ 86e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark#define REG_ENA_AP REG(0x00, 0x1e) /* read/write */ 87e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark#define REG_VIP_CNTRL_0 REG(0x00, 0x20) /* write */ 88e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark# define VIP_CNTRL_0_MIRR_A (1 << 7) 89e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark# define VIP_CNTRL_0_SWAP_A(x) (((x) & 7) << 4) 90e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark# define VIP_CNTRL_0_MIRR_B (1 << 3) 91e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark# define VIP_CNTRL_0_SWAP_B(x) (((x) & 7) << 0) 92e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark#define REG_VIP_CNTRL_1 REG(0x00, 0x21) /* write */ 93e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark# define VIP_CNTRL_1_MIRR_C (1 << 7) 94e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark# define VIP_CNTRL_1_SWAP_C(x) (((x) & 7) << 4) 95e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark# define VIP_CNTRL_1_MIRR_D (1 << 3) 96e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark# define VIP_CNTRL_1_SWAP_D(x) (((x) & 7) << 0) 97e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark#define REG_VIP_CNTRL_2 REG(0x00, 0x22) /* write */ 98e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark# define VIP_CNTRL_2_MIRR_E (1 << 7) 99e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark# define VIP_CNTRL_2_SWAP_E(x) (((x) & 7) << 4) 100e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark# define VIP_CNTRL_2_MIRR_F (1 << 3) 101e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark# define VIP_CNTRL_2_SWAP_F(x) (((x) & 7) << 0) 102e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark#define REG_VIP_CNTRL_3 REG(0x00, 0x23) /* write */ 103e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark# define VIP_CNTRL_3_X_TGL (1 << 0) 104e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark# define VIP_CNTRL_3_H_TGL (1 << 1) 105e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark# define VIP_CNTRL_3_V_TGL (1 << 2) 106e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark# define VIP_CNTRL_3_EMB (1 << 3) 107e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark# define VIP_CNTRL_3_SYNC_DE (1 << 4) 108e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark# define VIP_CNTRL_3_SYNC_HS (1 << 5) 109e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark# define VIP_CNTRL_3_DE_INT (1 << 6) 110e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark# define VIP_CNTRL_3_EDGE (1 << 7) 111e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark#define REG_VIP_CNTRL_4 REG(0x00, 0x24) /* write */ 112e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark# define VIP_CNTRL_4_BLC(x) (((x) & 3) << 0) 113e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark# define VIP_CNTRL_4_BLANKIT(x) (((x) & 3) << 2) 114e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark# define VIP_CNTRL_4_CCIR656 (1 << 4) 115e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark# define VIP_CNTRL_4_656_ALT (1 << 5) 116e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark# define VIP_CNTRL_4_TST_656 (1 << 6) 117e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark# define VIP_CNTRL_4_TST_PAT (1 << 7) 118e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark#define REG_VIP_CNTRL_5 REG(0x00, 0x25) /* write */ 119e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark# define VIP_CNTRL_5_CKCASE (1 << 0) 120e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark# define VIP_CNTRL_5_SP_CNT(x) (((x) & 3) << 1) 121c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King#define REG_MUX_AP REG(0x00, 0x26) /* read/write */ 122bcb2481df01a9aee7a09b20d43194011edd35754Russell King#define REG_MUX_VP_VIP_OUT REG(0x00, 0x27) /* read/write */ 123e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark#define REG_MAT_CONTRL REG(0x00, 0x80) /* write */ 124e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark# define MAT_CONTRL_MAT_SC(x) (((x) & 3) << 0) 125e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark# define MAT_CONTRL_MAT_BP (1 << 2) 126e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark#define REG_VIDFORMAT REG(0x00, 0xa0) /* write */ 127e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark#define REG_REFPIX_MSB REG(0x00, 0xa1) /* write */ 128e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark#define REG_REFPIX_LSB REG(0x00, 0xa2) /* write */ 129e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark#define REG_REFLINE_MSB REG(0x00, 0xa3) /* write */ 130e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark#define REG_REFLINE_LSB REG(0x00, 0xa4) /* write */ 131e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark#define REG_NPIX_MSB REG(0x00, 0xa5) /* write */ 132e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark#define REG_NPIX_LSB REG(0x00, 0xa6) /* write */ 133e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark#define REG_NLINE_MSB REG(0x00, 0xa7) /* write */ 134e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark#define REG_NLINE_LSB REG(0x00, 0xa8) /* write */ 135e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark#define REG_VS_LINE_STRT_1_MSB REG(0x00, 0xa9) /* write */ 136e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark#define REG_VS_LINE_STRT_1_LSB REG(0x00, 0xaa) /* write */ 137e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark#define REG_VS_PIX_STRT_1_MSB REG(0x00, 0xab) /* write */ 138e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark#define REG_VS_PIX_STRT_1_LSB REG(0x00, 0xac) /* write */ 139e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark#define REG_VS_LINE_END_1_MSB REG(0x00, 0xad) /* write */ 140e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark#define REG_VS_LINE_END_1_LSB REG(0x00, 0xae) /* write */ 141e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark#define REG_VS_PIX_END_1_MSB REG(0x00, 0xaf) /* write */ 142e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark#define REG_VS_PIX_END_1_LSB REG(0x00, 0xb0) /* write */ 143e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark#define REG_VS_PIX_STRT_2_MSB REG(0x00, 0xb3) /* write */ 144e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark#define REG_VS_PIX_STRT_2_LSB REG(0x00, 0xb4) /* write */ 145e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark#define REG_VS_PIX_END_2_MSB REG(0x00, 0xb7) /* write */ 146e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark#define REG_VS_PIX_END_2_LSB REG(0x00, 0xb8) /* write */ 147e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark#define REG_HS_PIX_START_MSB REG(0x00, 0xb9) /* write */ 148e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark#define REG_HS_PIX_START_LSB REG(0x00, 0xba) /* write */ 149e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark#define REG_HS_PIX_STOP_MSB REG(0x00, 0xbb) /* write */ 150e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark#define REG_HS_PIX_STOP_LSB REG(0x00, 0xbc) /* write */ 151e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark#define REG_VWIN_START_1_MSB REG(0x00, 0xbd) /* write */ 152e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark#define REG_VWIN_START_1_LSB REG(0x00, 0xbe) /* write */ 153e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark#define REG_VWIN_END_1_MSB REG(0x00, 0xbf) /* write */ 154e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark#define REG_VWIN_END_1_LSB REG(0x00, 0xc0) /* write */ 155e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark#define REG_DE_START_MSB REG(0x00, 0xc5) /* write */ 156e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark#define REG_DE_START_LSB REG(0x00, 0xc6) /* write */ 157e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark#define REG_DE_STOP_MSB REG(0x00, 0xc7) /* write */ 158e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark#define REG_DE_STOP_LSB REG(0x00, 0xc8) /* write */ 159e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark#define REG_TBG_CNTRL_0 REG(0x00, 0xca) /* write */ 160e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark# define TBG_CNTRL_0_FRAME_DIS (1 << 5) 161e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark# define TBG_CNTRL_0_SYNC_MTHD (1 << 6) 162e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark# define TBG_CNTRL_0_SYNC_ONCE (1 << 7) 163e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark#define REG_TBG_CNTRL_1 REG(0x00, 0xcb) /* write */ 164e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark# define TBG_CNTRL_1_VH_TGL_0 (1 << 0) 165e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark# define TBG_CNTRL_1_VH_TGL_1 (1 << 1) 166e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark# define TBG_CNTRL_1_VH_TGL_2 (1 << 2) 167e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark# define TBG_CNTRL_1_VHX_EXT_DE (1 << 3) 168e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark# define TBG_CNTRL_1_VHX_EXT_HS (1 << 4) 169e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark# define TBG_CNTRL_1_VHX_EXT_VS (1 << 5) 170e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark# define TBG_CNTRL_1_DWIN_DIS (1 << 6) 171e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark#define REG_ENABLE_SPACE REG(0x00, 0xd6) /* write */ 172e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark#define REG_HVF_CNTRL_0 REG(0x00, 0xe4) /* write */ 173e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark# define HVF_CNTRL_0_SM (1 << 7) 174e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark# define HVF_CNTRL_0_RWB (1 << 6) 175e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark# define HVF_CNTRL_0_PREFIL(x) (((x) & 3) << 2) 176e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark# define HVF_CNTRL_0_INTPOL(x) (((x) & 3) << 0) 177e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark#define REG_HVF_CNTRL_1 REG(0x00, 0xe5) /* write */ 178e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark# define HVF_CNTRL_1_FOR (1 << 0) 179e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark# define HVF_CNTRL_1_YUVBLK (1 << 1) 180e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark# define HVF_CNTRL_1_VQR(x) (((x) & 3) << 2) 181e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark# define HVF_CNTRL_1_PAD(x) (((x) & 3) << 4) 182e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark# define HVF_CNTRL_1_SEMI_PLANAR (1 << 6) 183e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark#define REG_RPT_CNTRL REG(0x00, 0xf0) /* write */ 184c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King#define REG_I2S_FORMAT REG(0x00, 0xfc) /* read/write */ 185c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King# define I2S_FORMAT(x) (((x) & 3) << 0) 186c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King#define REG_AIP_CLKSEL REG(0x00, 0xfd) /* write */ 187c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King# define AIP_CLKSEL_FS(x) (((x) & 3) << 0) 188c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King# define AIP_CLKSEL_CLK_POL(x) (((x) & 1) << 2) 189c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King# define AIP_CLKSEL_AIP(x) (((x) & 7) << 3) 190e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 191e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 192e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark/* Page 02h: PLL settings */ 193e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark#define REG_PLL_SERIAL_1 REG(0x02, 0x00) /* read/write */ 194e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark# define PLL_SERIAL_1_SRL_FDN (1 << 0) 195e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark# define PLL_SERIAL_1_SRL_IZ(x) (((x) & 3) << 1) 196e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark# define PLL_SERIAL_1_SRL_MAN_IZ (1 << 6) 197e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark#define REG_PLL_SERIAL_2 REG(0x02, 0x01) /* read/write */ 198e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark# define PLL_SERIAL_2_SRL_NOSC(x) (((x) & 3) << 0) 199e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark# define PLL_SERIAL_2_SRL_PR(x) (((x) & 0xf) << 4) 200e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark#define REG_PLL_SERIAL_3 REG(0x02, 0x02) /* read/write */ 201e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark# define PLL_SERIAL_3_SRL_CCIR (1 << 0) 202e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark# define PLL_SERIAL_3_SRL_DE (1 << 2) 203e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark# define PLL_SERIAL_3_SRL_PXIN_SEL (1 << 4) 204e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark#define REG_SERIALIZER REG(0x02, 0x03) /* read/write */ 205e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark#define REG_BUFFER_OUT REG(0x02, 0x04) /* read/write */ 206e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark#define REG_PLL_SCG1 REG(0x02, 0x05) /* read/write */ 207e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark#define REG_PLL_SCG2 REG(0x02, 0x06) /* read/write */ 208e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark#define REG_PLL_SCGN1 REG(0x02, 0x07) /* read/write */ 209e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark#define REG_PLL_SCGN2 REG(0x02, 0x08) /* read/write */ 210e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark#define REG_PLL_SCGR1 REG(0x02, 0x09) /* read/write */ 211e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark#define REG_PLL_SCGR2 REG(0x02, 0x0a) /* read/write */ 212e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark#define REG_AUDIO_DIV REG(0x02, 0x0e) /* read/write */ 213c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King# define AUDIO_DIV_SERCLK_1 0 214c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King# define AUDIO_DIV_SERCLK_2 1 215c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King# define AUDIO_DIV_SERCLK_4 2 216c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King# define AUDIO_DIV_SERCLK_8 3 217c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King# define AUDIO_DIV_SERCLK_16 4 218c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King# define AUDIO_DIV_SERCLK_32 5 219e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark#define REG_SEL_CLK REG(0x02, 0x11) /* read/write */ 220e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark# define SEL_CLK_SEL_CLK1 (1 << 0) 221e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark# define SEL_CLK_SEL_VRF_CLK(x) (((x) & 3) << 1) 222e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark# define SEL_CLK_ENA_SC_CLK (1 << 3) 223e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark#define REG_ANA_GENERAL REG(0x02, 0x12) /* read/write */ 224e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 225e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 226e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark/* Page 09h: EDID Control */ 227e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark#define REG_EDID_DATA_0 REG(0x09, 0x00) /* read */ 228e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark/* next 127 successive registers are the EDID block */ 229e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark#define REG_EDID_CTRL REG(0x09, 0xfa) /* read/write */ 230e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark#define REG_DDC_ADDR REG(0x09, 0xfb) /* read/write */ 231e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark#define REG_DDC_OFFS REG(0x09, 0xfc) /* read/write */ 232e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark#define REG_DDC_SEGM_ADDR REG(0x09, 0xfd) /* read/write */ 233e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark#define REG_DDC_SEGM REG(0x09, 0xfe) /* read/write */ 234e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 235e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 236e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark/* Page 10h: information frames and packets */ 237c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King#define REG_IF1_HB0 REG(0x10, 0x20) /* read/write */ 238c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King#define REG_IF2_HB0 REG(0x10, 0x40) /* read/write */ 239c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King#define REG_IF3_HB0 REG(0x10, 0x60) /* read/write */ 240c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King#define REG_IF4_HB0 REG(0x10, 0x80) /* read/write */ 241c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King#define REG_IF5_HB0 REG(0x10, 0xa0) /* read/write */ 242e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 243e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 244e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark/* Page 11h: audio settings and content info packets */ 245e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark#define REG_AIP_CNTRL_0 REG(0x11, 0x00) /* read/write */ 246e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark# define AIP_CNTRL_0_RST_FIFO (1 << 0) 247e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark# define AIP_CNTRL_0_SWAP (1 << 1) 248e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark# define AIP_CNTRL_0_LAYOUT (1 << 2) 249e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark# define AIP_CNTRL_0_ACR_MAN (1 << 5) 250e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark# define AIP_CNTRL_0_RST_CTS (1 << 6) 251c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King#define REG_CA_I2S REG(0x11, 0x01) /* read/write */ 252c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King# define CA_I2S_CA_I2S(x) (((x) & 31) << 0) 253c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King# define CA_I2S_HBR_CHSTAT (1 << 6) 254c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King#define REG_LATENCY_RD REG(0x11, 0x04) /* read/write */ 255c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King#define REG_ACR_CTS_0 REG(0x11, 0x05) /* read/write */ 256c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King#define REG_ACR_CTS_1 REG(0x11, 0x06) /* read/write */ 257c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King#define REG_ACR_CTS_2 REG(0x11, 0x07) /* read/write */ 258c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King#define REG_ACR_N_0 REG(0x11, 0x08) /* read/write */ 259c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King#define REG_ACR_N_1 REG(0x11, 0x09) /* read/write */ 260c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King#define REG_ACR_N_2 REG(0x11, 0x0a) /* read/write */ 261c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King#define REG_CTS_N REG(0x11, 0x0c) /* read/write */ 262c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King# define CTS_N_K(x) (((x) & 7) << 0) 263c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King# define CTS_N_M(x) (((x) & 3) << 4) 264e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark#define REG_ENC_CNTRL REG(0x11, 0x0d) /* read/write */ 265e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark# define ENC_CNTRL_RST_ENC (1 << 0) 266e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark# define ENC_CNTRL_RST_SEL (1 << 1) 267e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark# define ENC_CNTRL_CTL_CODE(x) (((x) & 3) << 2) 268c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King#define REG_DIP_FLAGS REG(0x11, 0x0e) /* read/write */ 269c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King# define DIP_FLAGS_ACR (1 << 0) 270c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King# define DIP_FLAGS_GC (1 << 1) 271c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King#define REG_DIP_IF_FLAGS REG(0x11, 0x0f) /* read/write */ 272c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King# define DIP_IF_FLAGS_IF1 (1 << 1) 273c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King# define DIP_IF_FLAGS_IF2 (1 << 2) 274c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King# define DIP_IF_FLAGS_IF3 (1 << 3) 275c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King# define DIP_IF_FLAGS_IF4 (1 << 4) 276c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King# define DIP_IF_FLAGS_IF5 (1 << 5) 277c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King#define REG_CH_STAT_B(x) REG(0x11, 0x14 + (x)) /* read/write */ 278e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 279e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 280e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark/* Page 12h: HDCP and OTP */ 281e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark#define REG_TX3 REG(0x12, 0x9a) /* read/write */ 282063b472fbb44ac562797a630ac3516720f588140Russell King#define REG_TX4 REG(0x12, 0x9b) /* read/write */ 283063b472fbb44ac562797a630ac3516720f588140Russell King# define TX4_PD_RAM (1 << 1) 284e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark#define REG_TX33 REG(0x12, 0xb8) /* read/write */ 285e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark# define TX33_HDMI (1 << 1) 286e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 287e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 288e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark/* Page 13h: Gamut related metadata packets */ 289e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 290e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 291e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 292e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark/* CEC registers: (not paged) 293e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark */ 294e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark#define REG_CEC_FRO_IM_CLK_CTRL 0xfb /* read/write */ 295e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark# define CEC_FRO_IM_CLK_CTRL_GHOST_DIS (1 << 7) 296e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark# define CEC_FRO_IM_CLK_CTRL_ENA_OTP (1 << 6) 297e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark# define CEC_FRO_IM_CLK_CTRL_IMCLK_SEL (1 << 1) 298e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark# define CEC_FRO_IM_CLK_CTRL_FRO_DIV (1 << 0) 299e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark#define REG_CEC_RXSHPDLEV 0xfe /* read */ 300e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark# define CEC_RXSHPDLEV_RXSENS (1 << 0) 301e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark# define CEC_RXSHPDLEV_HPD (1 << 1) 302e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 303e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark#define REG_CEC_ENAMODS 0xff /* read/write */ 304e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark# define CEC_ENAMODS_DIS_FRO (1 << 6) 305e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark# define CEC_ENAMODS_DIS_CCLK (1 << 5) 306e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark# define CEC_ENAMODS_EN_RXSENS (1 << 2) 307e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark# define CEC_ENAMODS_EN_HDMI (1 << 1) 308e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark# define CEC_ENAMODS_EN_CEC (1 << 0) 309e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 310e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 311e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark/* Device versions: */ 312e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark#define TDA9989N2 0x0101 313e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark#define TDA19989 0x0201 314e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark#define TDA19989N2 0x0202 315e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark#define TDA19988 0x0301 316e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 317e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clarkstatic void 318e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clarkcec_write(struct drm_encoder *encoder, uint16_t addr, uint8_t val) 319e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark{ 320e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark struct i2c_client *client = to_tda998x_priv(encoder)->cec; 321e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark uint8_t buf[] = {addr, val}; 322e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark int ret; 323e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 324e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark ret = i2c_master_send(client, buf, ARRAY_SIZE(buf)); 325e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark if (ret < 0) 326e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark dev_err(&client->dev, "Error %d writing to cec:0x%x\n", ret, addr); 327e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark} 328e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 329e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clarkstatic uint8_t 330e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clarkcec_read(struct drm_encoder *encoder, uint8_t addr) 331e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark{ 332e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark struct i2c_client *client = to_tda998x_priv(encoder)->cec; 333e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark uint8_t val; 334e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark int ret; 335e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 336e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark ret = i2c_master_send(client, &addr, sizeof(addr)); 337e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark if (ret < 0) 338e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark goto fail; 339e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 340e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark ret = i2c_master_recv(client, &val, sizeof(val)); 341e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark if (ret < 0) 342e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark goto fail; 343e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 344e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark return val; 345e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 346e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clarkfail: 347e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark dev_err(&client->dev, "Error %d reading from cec:0x%x\n", ret, addr); 348e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark return 0; 349e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark} 350e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 351e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clarkstatic void 352e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clarkset_page(struct drm_encoder *encoder, uint16_t reg) 353e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark{ 354e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark struct tda998x_priv *priv = to_tda998x_priv(encoder); 355e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 356e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark if (REG2PAGE(reg) != priv->current_page) { 357e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark struct i2c_client *client = drm_i2c_encoder_get_client(encoder); 358e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark uint8_t buf[] = { 359e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark REG_CURPAGE, REG2PAGE(reg) 360e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark }; 361e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark int ret = i2c_master_send(client, buf, sizeof(buf)); 362e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark if (ret < 0) 363e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark dev_err(&client->dev, "Error %d writing to REG_CURPAGE\n", ret); 364e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 365e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark priv->current_page = REG2PAGE(reg); 366e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark } 367e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark} 368e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 369e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clarkstatic int 370e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clarkreg_read_range(struct drm_encoder *encoder, uint16_t reg, char *buf, int cnt) 371e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark{ 372e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark struct i2c_client *client = drm_i2c_encoder_get_client(encoder); 373e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark uint8_t addr = REG2ADDR(reg); 374e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark int ret; 375e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 376e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark set_page(encoder, reg); 377e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 378e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark ret = i2c_master_send(client, &addr, sizeof(addr)); 379e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark if (ret < 0) 380e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark goto fail; 381e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 382e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark ret = i2c_master_recv(client, buf, cnt); 383e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark if (ret < 0) 384e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark goto fail; 385e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 386e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark return ret; 387e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 388e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clarkfail: 389e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark dev_err(&client->dev, "Error %d reading from 0x%x\n", ret, reg); 390e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark return ret; 391e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark} 392e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 393c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell Kingstatic void 394c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell Kingreg_write_range(struct drm_encoder *encoder, uint16_t reg, uint8_t *p, int cnt) 395c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King{ 396c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King struct i2c_client *client = drm_i2c_encoder_get_client(encoder); 397c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King uint8_t buf[cnt+1]; 398c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King int ret; 399c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King 400c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King buf[0] = REG2ADDR(reg); 401c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King memcpy(&buf[1], p, cnt); 402c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King 403c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King set_page(encoder, reg); 404c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King 405c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King ret = i2c_master_send(client, buf, cnt + 1); 406c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King if (ret < 0) 407c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King dev_err(&client->dev, "Error %d writing to 0x%x\n", ret, reg); 408c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King} 409c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King 410e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clarkstatic uint8_t 411e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clarkreg_read(struct drm_encoder *encoder, uint16_t reg) 412e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark{ 413e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark uint8_t val = 0; 414e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark reg_read_range(encoder, reg, &val, sizeof(val)); 415e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark return val; 416e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark} 417e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 418e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clarkstatic void 419e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clarkreg_write(struct drm_encoder *encoder, uint16_t reg, uint8_t val) 420e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark{ 421e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark struct i2c_client *client = drm_i2c_encoder_get_client(encoder); 422e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark uint8_t buf[] = {REG2ADDR(reg), val}; 423e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark int ret; 424e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 425e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark set_page(encoder, reg); 426e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 427e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark ret = i2c_master_send(client, buf, ARRAY_SIZE(buf)); 428e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark if (ret < 0) 429e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark dev_err(&client->dev, "Error %d writing to 0x%x\n", ret, reg); 430e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark} 431e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 432e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clarkstatic void 433e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clarkreg_write16(struct drm_encoder *encoder, uint16_t reg, uint16_t val) 434e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark{ 435e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark struct i2c_client *client = drm_i2c_encoder_get_client(encoder); 436e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark uint8_t buf[] = {REG2ADDR(reg), val >> 8, val}; 437e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark int ret; 438e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 439e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark set_page(encoder, reg); 440e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 441e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark ret = i2c_master_send(client, buf, ARRAY_SIZE(buf)); 442e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark if (ret < 0) 443e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark dev_err(&client->dev, "Error %d writing to 0x%x\n", ret, reg); 444e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark} 445e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 446e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clarkstatic void 447e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clarkreg_set(struct drm_encoder *encoder, uint16_t reg, uint8_t val) 448e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark{ 449e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark reg_write(encoder, reg, reg_read(encoder, reg) | val); 450e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark} 451e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 452e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clarkstatic void 453e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clarkreg_clear(struct drm_encoder *encoder, uint16_t reg, uint8_t val) 454e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark{ 455e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark reg_write(encoder, reg, reg_read(encoder, reg) & ~val); 456e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark} 457e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 458e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clarkstatic void 459e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clarktda998x_reset(struct drm_encoder *encoder) 460e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark{ 461e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark /* reset audio and i2c master: */ 462e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark reg_set(encoder, REG_SOFTRESET, SOFTRESET_AUDIO | SOFTRESET_I2C_MASTER); 463e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark msleep(50); 464e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark reg_clear(encoder, REG_SOFTRESET, SOFTRESET_AUDIO | SOFTRESET_I2C_MASTER); 465e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark msleep(50); 466e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 467e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark /* reset transmitter: */ 468e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark reg_set(encoder, REG_MAIN_CNTRL0, MAIN_CNTRL0_SR); 469e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark reg_clear(encoder, REG_MAIN_CNTRL0, MAIN_CNTRL0_SR); 470e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 471e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark /* PLL registers common configuration */ 472e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark reg_write(encoder, REG_PLL_SERIAL_1, 0x00); 473e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark reg_write(encoder, REG_PLL_SERIAL_2, PLL_SERIAL_2_SRL_NOSC(1)); 474e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark reg_write(encoder, REG_PLL_SERIAL_3, 0x00); 475e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark reg_write(encoder, REG_SERIALIZER, 0x00); 476e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark reg_write(encoder, REG_BUFFER_OUT, 0x00); 477e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark reg_write(encoder, REG_PLL_SCG1, 0x00); 478c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King reg_write(encoder, REG_AUDIO_DIV, AUDIO_DIV_SERCLK_8); 479e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark reg_write(encoder, REG_SEL_CLK, SEL_CLK_SEL_CLK1 | SEL_CLK_ENA_SC_CLK); 480e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark reg_write(encoder, REG_PLL_SCGN1, 0xfa); 481e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark reg_write(encoder, REG_PLL_SCGN2, 0x00); 482e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark reg_write(encoder, REG_PLL_SCGR1, 0x5b); 483e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark reg_write(encoder, REG_PLL_SCGR2, 0x00); 484e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark reg_write(encoder, REG_PLL_SCG2, 0x10); 485bcb2481df01a9aee7a09b20d43194011edd35754Russell King 486bcb2481df01a9aee7a09b20d43194011edd35754Russell King /* Write the default value MUX register */ 487bcb2481df01a9aee7a09b20d43194011edd35754Russell King reg_write(encoder, REG_MUX_VP_VIP_OUT, 0x24); 488e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark} 489e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 490c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell Kingstatic uint8_t tda998x_cksum(uint8_t *buf, size_t bytes) 491c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King{ 492c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King uint8_t sum = 0; 493c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King 494c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King while (bytes--) 495c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King sum += *buf++; 496c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King return (255 - sum) + 1; 497c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King} 498c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King 499c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King#define HB(x) (x) 500c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King#define PB(x) (HB(2) + 1 + (x)) 501c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King 502c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell Kingstatic void 503c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell Kingtda998x_write_if(struct drm_encoder *encoder, uint8_t bit, uint16_t addr, 504c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King uint8_t *buf, size_t size) 505c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King{ 506c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King buf[PB(0)] = tda998x_cksum(buf, size); 507c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King 508c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King reg_clear(encoder, REG_DIP_IF_FLAGS, bit); 509c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King reg_write_range(encoder, addr, buf, size); 510c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King reg_set(encoder, REG_DIP_IF_FLAGS, bit); 511c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King} 512c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King 513c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell Kingstatic void 514c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell Kingtda998x_write_aif(struct drm_encoder *encoder, struct tda998x_encoder_params *p) 515c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King{ 516c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King uint8_t buf[PB(5) + 1]; 517c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King 518c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King buf[HB(0)] = 0x84; 519c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King buf[HB(1)] = 0x01; 520c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King buf[HB(2)] = 10; 521c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King buf[PB(0)] = 0; 522c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King buf[PB(1)] = p->audio_frame[1] & 0x07; /* CC */ 523c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King buf[PB(2)] = p->audio_frame[2] & 0x1c; /* SF */ 524c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King buf[PB(4)] = p->audio_frame[4]; 525c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King buf[PB(5)] = p->audio_frame[5] & 0xf8; /* DM_INH + LSV */ 526c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King 527c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King tda998x_write_if(encoder, DIP_IF_FLAGS_IF4, REG_IF4_HB0, buf, 528c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King sizeof(buf)); 529c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King} 530c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King 531c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell Kingstatic void 532c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell Kingtda998x_write_avi(struct drm_encoder *encoder, struct drm_display_mode *mode) 533c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King{ 534c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King uint8_t buf[PB(13) + 1]; 535c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King 536c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King memset(buf, 0, sizeof(buf)); 537c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King buf[HB(0)] = 0x82; 538c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King buf[HB(1)] = 0x02; 539c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King buf[HB(2)] = 13; 540c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King buf[PB(4)] = drm_match_cea_mode(mode); 541c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King 542c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King tda998x_write_if(encoder, DIP_IF_FLAGS_IF2, REG_IF2_HB0, buf, 543c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King sizeof(buf)); 544c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King} 545c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King 546c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell Kingstatic void tda998x_audio_mute(struct drm_encoder *encoder, bool on) 547c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King{ 548c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King if (on) { 549c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King reg_set(encoder, REG_SOFTRESET, SOFTRESET_AUDIO); 550c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King reg_clear(encoder, REG_SOFTRESET, SOFTRESET_AUDIO); 551c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King reg_set(encoder, REG_AIP_CNTRL_0, AIP_CNTRL_0_RST_FIFO); 552c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King } else { 553c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King reg_clear(encoder, REG_AIP_CNTRL_0, AIP_CNTRL_0_RST_FIFO); 554c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King } 555c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King} 556c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King 557c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell Kingstatic void 558c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell Kingtda998x_configure_audio(struct drm_encoder *encoder, 559c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King struct drm_display_mode *mode, struct tda998x_encoder_params *p) 560c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King{ 561c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King uint8_t buf[6], clksel_aip, clksel_fs, ca_i2s, cts_n, adiv; 562c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King uint32_t n; 563c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King 564c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King /* Enable audio ports */ 565c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King reg_write(encoder, REG_ENA_AP, p->audio_cfg); 566c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King reg_write(encoder, REG_ENA_ACLK, p->audio_clk_cfg); 567c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King 568c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King /* Set audio input source */ 569c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King switch (p->audio_format) { 570c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King case AFMT_SPDIF: 571c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King reg_write(encoder, REG_MUX_AP, 0x40); 572c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King clksel_aip = AIP_CLKSEL_AIP(0); 573c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King /* FS64SPDIF */ 574c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King clksel_fs = AIP_CLKSEL_FS(2); 575c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King cts_n = CTS_N_M(3) | CTS_N_K(3); 576c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King ca_i2s = 0; 577c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King break; 578c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King 579c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King case AFMT_I2S: 580c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King reg_write(encoder, REG_MUX_AP, 0x64); 581c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King clksel_aip = AIP_CLKSEL_AIP(1); 582c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King /* ACLK */ 583c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King clksel_fs = AIP_CLKSEL_FS(0); 584c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King cts_n = CTS_N_M(3) | CTS_N_K(3); 585c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King ca_i2s = CA_I2S_CA_I2S(0); 586c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King break; 587c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King } 588c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King 589c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King reg_write(encoder, REG_AIP_CLKSEL, clksel_aip); 590c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King reg_clear(encoder, REG_AIP_CNTRL_0, AIP_CNTRL_0_LAYOUT); 591c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King 592c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King /* Enable automatic CTS generation */ 593c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King reg_clear(encoder, REG_AIP_CNTRL_0, AIP_CNTRL_0_ACR_MAN); 594c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King reg_write(encoder, REG_CTS_N, cts_n); 595c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King 596c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King /* 597c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King * Audio input somehow depends on HDMI line rate which is 598c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King * related to pixclk. Testing showed that modes with pixclk 599c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King * >100MHz need a larger divider while <40MHz need the default. 600c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King * There is no detailed info in the datasheet, so we just 601c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King * assume 100MHz requires larger divider. 602c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King */ 603c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King if (mode->clock > 100000) 604c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King adiv = AUDIO_DIV_SERCLK_16; 605c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King else 606c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King adiv = AUDIO_DIV_SERCLK_8; 607c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King reg_write(encoder, REG_AUDIO_DIV, adiv); 608c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King 609c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King /* 610c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King * This is the approximate value of N, which happens to be 611c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King * the recommended values for non-coherent clocks. 612c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King */ 613c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King n = 128 * p->audio_sample_rate / 1000; 614c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King 615c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King /* Write the CTS and N values */ 616c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King buf[0] = 0x44; 617c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King buf[1] = 0x42; 618c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King buf[2] = 0x01; 619c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King buf[3] = n; 620c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King buf[4] = n >> 8; 621c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King buf[5] = n >> 16; 622c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King reg_write_range(encoder, REG_ACR_CTS_0, buf, 6); 623c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King 624c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King /* Set CTS clock reference */ 625c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King reg_write(encoder, REG_AIP_CLKSEL, clksel_aip | clksel_fs); 626c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King 627c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King /* Reset CTS generator */ 628c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King reg_set(encoder, REG_AIP_CNTRL_0, AIP_CNTRL_0_RST_CTS); 629c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King reg_clear(encoder, REG_AIP_CNTRL_0, AIP_CNTRL_0_RST_CTS); 630c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King 631c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King /* Write the channel status */ 632c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King buf[0] = 0x04; 633c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King buf[1] = 0x00; 634c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King buf[2] = 0x00; 635c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King buf[3] = 0xf1; 636c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King reg_write_range(encoder, REG_CH_STAT_B(0), buf, 4); 637c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King 638c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King tda998x_audio_mute(encoder, true); 639c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King mdelay(20); 640c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King tda998x_audio_mute(encoder, false); 641c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King 642c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King /* Write the audio information packet */ 643c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King tda998x_write_aif(encoder, p); 644c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King} 645c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King 646e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark/* DRM encoder functions */ 647e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 648e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clarkstatic void 649e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clarktda998x_encoder_set_config(struct drm_encoder *encoder, void *params) 650e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark{ 651c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King struct tda998x_priv *priv = to_tda998x_priv(encoder); 652c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King struct tda998x_encoder_params *p = params; 653c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King 654c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King priv->vip_cntrl_0 = VIP_CNTRL_0_SWAP_A(p->swap_a) | 655c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King (p->mirr_a ? VIP_CNTRL_0_MIRR_A : 0) | 656c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King VIP_CNTRL_0_SWAP_B(p->swap_b) | 657c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King (p->mirr_b ? VIP_CNTRL_0_MIRR_B : 0); 658c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King priv->vip_cntrl_1 = VIP_CNTRL_1_SWAP_C(p->swap_c) | 659c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King (p->mirr_c ? VIP_CNTRL_1_MIRR_C : 0) | 660c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King VIP_CNTRL_1_SWAP_D(p->swap_d) | 661c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King (p->mirr_d ? VIP_CNTRL_1_MIRR_D : 0); 662c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King priv->vip_cntrl_2 = VIP_CNTRL_2_SWAP_E(p->swap_e) | 663c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King (p->mirr_e ? VIP_CNTRL_2_MIRR_E : 0) | 664c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King VIP_CNTRL_2_SWAP_F(p->swap_f) | 665c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King (p->mirr_f ? VIP_CNTRL_2_MIRR_F : 0); 666c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King 667c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King priv->params = *p; 668e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark} 669e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 670e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clarkstatic void 671e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clarktda998x_encoder_dpms(struct drm_encoder *encoder, int mode) 672e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark{ 673e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark struct tda998x_priv *priv = to_tda998x_priv(encoder); 674e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 675e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark /* we only care about on or off: */ 676e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark if (mode != DRM_MODE_DPMS_ON) 677e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark mode = DRM_MODE_DPMS_OFF; 678e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 679e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark if (mode == priv->dpms) 680e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark return; 681e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 682e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark switch (mode) { 683e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark case DRM_MODE_DPMS_ON: 684c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King /* enable video ports, audio will be enabled later */ 685e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark reg_write(encoder, REG_ENA_VP_0, 0xff); 686e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark reg_write(encoder, REG_ENA_VP_1, 0xff); 687e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark reg_write(encoder, REG_ENA_VP_2, 0xff); 688e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark /* set muxing after enabling ports: */ 6895e74c22cd1e0f9e49573fe580de47e198ee04975Russell King reg_write(encoder, REG_VIP_CNTRL_0, priv->vip_cntrl_0); 6905e74c22cd1e0f9e49573fe580de47e198ee04975Russell King reg_write(encoder, REG_VIP_CNTRL_1, priv->vip_cntrl_1); 6915e74c22cd1e0f9e49573fe580de47e198ee04975Russell King reg_write(encoder, REG_VIP_CNTRL_2, priv->vip_cntrl_2); 692e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark break; 693e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark case DRM_MODE_DPMS_OFF: 694e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark /* disable audio and video ports */ 695e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark reg_write(encoder, REG_ENA_AP, 0x00); 696e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark reg_write(encoder, REG_ENA_VP_0, 0x00); 697e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark reg_write(encoder, REG_ENA_VP_1, 0x00); 698e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark reg_write(encoder, REG_ENA_VP_2, 0x00); 699e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark break; 700e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark } 701e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 702e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark priv->dpms = mode; 703e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark} 704e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 705e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clarkstatic void 706e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clarktda998x_encoder_save(struct drm_encoder *encoder) 707e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark{ 708e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark DBG(""); 709e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark} 710e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 711e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clarkstatic void 712e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clarktda998x_encoder_restore(struct drm_encoder *encoder) 713e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark{ 714e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark DBG(""); 715e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark} 716e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 717e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clarkstatic bool 718e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clarktda998x_encoder_mode_fixup(struct drm_encoder *encoder, 719e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark const struct drm_display_mode *mode, 720e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark struct drm_display_mode *adjusted_mode) 721e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark{ 722e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark return true; 723e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark} 724e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 725e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clarkstatic int 726e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clarktda998x_encoder_mode_valid(struct drm_encoder *encoder, 727e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark struct drm_display_mode *mode) 728e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark{ 729e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark return MODE_OK; 730e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark} 731e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 732e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clarkstatic void 733e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clarktda998x_encoder_mode_set(struct drm_encoder *encoder, 734e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark struct drm_display_mode *mode, 735e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark struct drm_display_mode *adjusted_mode) 736e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark{ 737e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark struct tda998x_priv *priv = to_tda998x_priv(encoder); 738e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark uint16_t hs_start, hs_end, line_start, line_end; 739e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark uint16_t vwin_start, vwin_end, de_start, de_end; 740e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark uint16_t ref_pix, ref_line, pix_start2; 741e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark uint8_t reg, div, rep; 742e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 743e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark hs_start = mode->hsync_start - mode->hdisplay; 744e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark hs_end = mode->hsync_end - mode->hdisplay; 745e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark line_start = 1; 746e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark line_end = 1 + mode->vsync_end - mode->vsync_start; 747e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark vwin_start = mode->vtotal - mode->vsync_start; 748e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark vwin_end = vwin_start + mode->vdisplay; 749e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark de_start = mode->htotal - mode->hdisplay; 750e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark de_end = mode->htotal; 751e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 752e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark pix_start2 = 0; 753e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark if (mode->flags & DRM_MODE_FLAG_INTERLACE) 754e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark pix_start2 = (mode->htotal / 2) + hs_start; 755e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 756e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark /* TODO how is this value calculated? It is 2 for all common 757e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark * formats in the tables in out of tree nxp driver (assuming 758e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark * I've properly deciphered their byzantine table system) 759e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark */ 760e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark ref_line = 2; 761e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 762e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark /* this might changes for other color formats from the CRTC: */ 763e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark ref_pix = 3 + hs_start; 764e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 765e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark div = 148500 / mode->clock; 766e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 767e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark DBG("clock=%d, div=%u", mode->clock, div); 768e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark DBG("hs_start=%u, hs_end=%u, line_start=%u, line_end=%u", 769e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark hs_start, hs_end, line_start, line_end); 770e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark DBG("vwin_start=%u, vwin_end=%u, de_start=%u, de_end=%u", 771e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark vwin_start, vwin_end, de_start, de_end); 772e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark DBG("ref_line=%u, ref_pix=%u, pix_start2=%u", 773e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark ref_line, ref_pix, pix_start2); 774e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 775e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark /* mute the audio FIFO: */ 776e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark reg_set(encoder, REG_AIP_CNTRL_0, AIP_CNTRL_0_RST_FIFO); 777e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 778e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark /* set HDMI HDCP mode off: */ 779e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark reg_set(encoder, REG_TBG_CNTRL_1, TBG_CNTRL_1_DWIN_DIS); 780e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark reg_clear(encoder, REG_TX33, TX33_HDMI); 781e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 782e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark reg_write(encoder, REG_ENC_CNTRL, ENC_CNTRL_CTL_CODE(0)); 783e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark /* no pre-filter or interpolator: */ 784e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark reg_write(encoder, REG_HVF_CNTRL_0, HVF_CNTRL_0_PREFIL(0) | 785e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark HVF_CNTRL_0_INTPOL(0)); 786e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark reg_write(encoder, REG_VIP_CNTRL_5, VIP_CNTRL_5_SP_CNT(0)); 787e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark reg_write(encoder, REG_VIP_CNTRL_4, VIP_CNTRL_4_BLANKIT(0) | 788e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark VIP_CNTRL_4_BLC(0)); 789e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark reg_clear(encoder, REG_PLL_SERIAL_3, PLL_SERIAL_3_SRL_CCIR); 790e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 791e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark reg_clear(encoder, REG_PLL_SERIAL_1, PLL_SERIAL_1_SRL_MAN_IZ); 792e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark reg_clear(encoder, REG_PLL_SERIAL_3, PLL_SERIAL_3_SRL_DE); 793e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark reg_write(encoder, REG_SERIALIZER, 0); 794e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark reg_write(encoder, REG_HVF_CNTRL_1, HVF_CNTRL_1_VQR(0)); 795e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 796e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark /* TODO enable pixel repeat for pixel rates less than 25Msamp/s */ 797e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark rep = 0; 798e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark reg_write(encoder, REG_RPT_CNTRL, 0); 799e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark reg_write(encoder, REG_SEL_CLK, SEL_CLK_SEL_VRF_CLK(0) | 800e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark SEL_CLK_SEL_CLK1 | SEL_CLK_ENA_SC_CLK); 801e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 802e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark reg_write(encoder, REG_PLL_SERIAL_2, PLL_SERIAL_2_SRL_NOSC(div) | 803e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark PLL_SERIAL_2_SRL_PR(rep)); 804e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 805e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark reg_write16(encoder, REG_VS_PIX_STRT_2_MSB, pix_start2); 806e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark reg_write16(encoder, REG_VS_PIX_END_2_MSB, pix_start2); 807e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 808e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark /* set color matrix bypass flag: */ 809e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark reg_set(encoder, REG_MAT_CONTRL, MAT_CONTRL_MAT_BP); 810e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 811e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark /* set BIAS tmds value: */ 812e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark reg_write(encoder, REG_ANA_GENERAL, 0x09); 813e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 814e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark reg_clear(encoder, REG_TBG_CNTRL_0, TBG_CNTRL_0_SYNC_MTHD); 815e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 816e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark reg_write(encoder, REG_VIP_CNTRL_3, 0); 817e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark reg_set(encoder, REG_VIP_CNTRL_3, VIP_CNTRL_3_SYNC_HS); 818e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark if (mode->flags & DRM_MODE_FLAG_NVSYNC) 819e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark reg_set(encoder, REG_VIP_CNTRL_3, VIP_CNTRL_3_V_TGL); 820e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 821e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark if (mode->flags & DRM_MODE_FLAG_NHSYNC) 822e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark reg_set(encoder, REG_VIP_CNTRL_3, VIP_CNTRL_3_H_TGL); 823e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 824e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark reg_write(encoder, REG_VIDFORMAT, 0x00); 82520c17675fea9ddf94b8249a67fb95fd26e732bafRussell King reg_write16(encoder, REG_NPIX_MSB, mode->htotal); 82620c17675fea9ddf94b8249a67fb95fd26e732bafRussell King reg_write16(encoder, REG_NLINE_MSB, mode->vtotal); 827e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark reg_write16(encoder, REG_VS_LINE_STRT_1_MSB, line_start); 828e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark reg_write16(encoder, REG_VS_LINE_END_1_MSB, line_end); 829e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark reg_write16(encoder, REG_VS_PIX_STRT_1_MSB, hs_start); 830e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark reg_write16(encoder, REG_VS_PIX_END_1_MSB, hs_start); 831e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark reg_write16(encoder, REG_HS_PIX_START_MSB, hs_start); 832e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark reg_write16(encoder, REG_HS_PIX_STOP_MSB, hs_end); 833e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark reg_write16(encoder, REG_VWIN_START_1_MSB, vwin_start); 834e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark reg_write16(encoder, REG_VWIN_END_1_MSB, vwin_end); 835e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark reg_write16(encoder, REG_DE_START_MSB, de_start); 836e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark reg_write16(encoder, REG_DE_STOP_MSB, de_end); 837e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 838e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark if (priv->rev == TDA19988) { 839e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark /* let incoming pixels fill the active space (if any) */ 840e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark reg_write(encoder, REG_ENABLE_SPACE, 0x01); 841e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark } 842e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 843e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark reg_write16(encoder, REG_REFPIX_MSB, ref_pix); 844e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark reg_write16(encoder, REG_REFLINE_MSB, ref_line); 845e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 846c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King reg = TBG_CNTRL_1_DWIN_DIS | /* HDCP off */ 847e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark TBG_CNTRL_1_VH_TGL_2; 848c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King /* 849c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King * It is questionable whether this is correct - the nxp driver 850c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King * does not set VH_TGL_2 and the below for all display modes. 851c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King */ 852e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark if (mode->flags & (DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC)) 853e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark reg |= TBG_CNTRL_1_VH_TGL_0; 854e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark reg_set(encoder, REG_TBG_CNTRL_1, reg); 855e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 856e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark /* must be last register set: */ 857e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark reg_clear(encoder, REG_TBG_CNTRL_0, TBG_CNTRL_0_SYNC_ONCE); 858c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King 859c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King /* Only setup the info frames if the sink is HDMI */ 860c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King if (priv->is_hdmi_sink) { 861c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King /* We need to turn HDMI HDCP stuff on to get audio through */ 862c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King reg_clear(encoder, REG_TBG_CNTRL_1, TBG_CNTRL_1_DWIN_DIS); 863c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King reg_write(encoder, REG_ENC_CNTRL, ENC_CNTRL_CTL_CODE(1)); 864c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King reg_set(encoder, REG_TX33, TX33_HDMI); 865c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King 866c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King tda998x_write_avi(encoder, adjusted_mode); 867c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King 868c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King if (priv->params.audio_cfg) 869c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King tda998x_configure_audio(encoder, adjusted_mode, 870c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King &priv->params); 871c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King } 872e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark} 873e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 874e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clarkstatic enum drm_connector_status 875e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clarktda998x_encoder_detect(struct drm_encoder *encoder, 876e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark struct drm_connector *connector) 877e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark{ 878e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark uint8_t val = cec_read(encoder, REG_CEC_RXSHPDLEV); 879e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark return (val & CEC_RXSHPDLEV_HPD) ? connector_status_connected : 880e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark connector_status_disconnected; 881e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark} 882e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 883e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clarkstatic int 884e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clarkread_edid_block(struct drm_encoder *encoder, uint8_t *buf, int blk) 885e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark{ 886e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark uint8_t offset, segptr; 887e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark int ret, i; 888e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 889e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark /* enable EDID read irq: */ 890e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark reg_set(encoder, REG_INT_FLAGS_2, INT_FLAGS_2_EDID_BLK_RD); 891e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 892e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark offset = (blk & 1) ? 128 : 0; 893e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark segptr = blk / 2; 894e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 895e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark reg_write(encoder, REG_DDC_ADDR, 0xa0); 896e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark reg_write(encoder, REG_DDC_OFFS, offset); 897e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark reg_write(encoder, REG_DDC_SEGM_ADDR, 0x60); 898e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark reg_write(encoder, REG_DDC_SEGM, segptr); 899e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 900e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark /* enable reading EDID: */ 901e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark reg_write(encoder, REG_EDID_CTRL, 0x1); 902e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 903e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark /* flag must be cleared by sw: */ 904e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark reg_write(encoder, REG_EDID_CTRL, 0x0); 905e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 906e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark /* wait for block read to complete: */ 907e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark for (i = 100; i > 0; i--) { 908e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark uint8_t val = reg_read(encoder, REG_INT_FLAGS_2); 909e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark if (val & INT_FLAGS_2_EDID_BLK_RD) 910e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark break; 911e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark msleep(1); 912e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark } 913e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 914e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark if (i == 0) 915e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark return -ETIMEDOUT; 916e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 917e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark ret = reg_read_range(encoder, REG_EDID_DATA_0, buf, EDID_LENGTH); 918e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark if (ret != EDID_LENGTH) { 919e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark dev_err(encoder->dev->dev, "failed to read edid block %d: %d", 920e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark blk, ret); 921e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark return ret; 922e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark } 923e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 924e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark reg_clear(encoder, REG_INT_FLAGS_2, INT_FLAGS_2_EDID_BLK_RD); 925e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 926e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark return 0; 927e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark} 928e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 929e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clarkstatic uint8_t * 930e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clarkdo_get_edid(struct drm_encoder *encoder) 931e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark{ 932063b472fbb44ac562797a630ac3516720f588140Russell King struct tda998x_priv *priv = to_tda998x_priv(encoder); 933e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark int j = 0, valid_extensions = 0; 934e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark uint8_t *block, *new; 935e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark bool print_bad_edid = drm_debug & DRM_UT_KMS; 936e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 937e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark if ((block = kmalloc(EDID_LENGTH, GFP_KERNEL)) == NULL) 938e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark return NULL; 939e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 940063b472fbb44ac562797a630ac3516720f588140Russell King if (priv->rev == TDA19988) 941063b472fbb44ac562797a630ac3516720f588140Russell King reg_clear(encoder, REG_TX4, TX4_PD_RAM); 942063b472fbb44ac562797a630ac3516720f588140Russell King 943e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark /* base block fetch */ 944e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark if (read_edid_block(encoder, block, 0)) 945e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark goto fail; 946e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 947e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark if (!drm_edid_block_valid(block, 0, print_bad_edid)) 948e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark goto fail; 949e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 950e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark /* if there's no extensions, we're done */ 951e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark if (block[0x7e] == 0) 952063b472fbb44ac562797a630ac3516720f588140Russell King goto done; 953e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 954e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark new = krealloc(block, (block[0x7e] + 1) * EDID_LENGTH, GFP_KERNEL); 955e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark if (!new) 956e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark goto fail; 957e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark block = new; 958e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 959e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark for (j = 1; j <= block[0x7e]; j++) { 960e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark uint8_t *ext_block = block + (valid_extensions + 1) * EDID_LENGTH; 961e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark if (read_edid_block(encoder, ext_block, j)) 962e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark goto fail; 963e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 964e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark if (!drm_edid_block_valid(ext_block, j, print_bad_edid)) 965e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark goto fail; 966e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 967e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark valid_extensions++; 968e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark } 969e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 970e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark if (valid_extensions != block[0x7e]) { 971e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark block[EDID_LENGTH-1] += block[0x7e] - valid_extensions; 972e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark block[0x7e] = valid_extensions; 973e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark new = krealloc(block, (valid_extensions + 1) * EDID_LENGTH, GFP_KERNEL); 974e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark if (!new) 975e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark goto fail; 976e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark block = new; 977e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark } 978e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 979063b472fbb44ac562797a630ac3516720f588140Russell Kingdone: 980063b472fbb44ac562797a630ac3516720f588140Russell King if (priv->rev == TDA19988) 981063b472fbb44ac562797a630ac3516720f588140Russell King reg_set(encoder, REG_TX4, TX4_PD_RAM); 982063b472fbb44ac562797a630ac3516720f588140Russell King 983e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark return block; 984e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 985e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clarkfail: 986063b472fbb44ac562797a630ac3516720f588140Russell King if (priv->rev == TDA19988) 987063b472fbb44ac562797a630ac3516720f588140Russell King reg_set(encoder, REG_TX4, TX4_PD_RAM); 988e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark dev_warn(encoder->dev->dev, "failed to read EDID\n"); 989e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark kfree(block); 990e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark return NULL; 991e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark} 992e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 993e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clarkstatic int 994e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clarktda998x_encoder_get_modes(struct drm_encoder *encoder, 995e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark struct drm_connector *connector) 996e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark{ 997c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King struct tda998x_priv *priv = to_tda998x_priv(encoder); 998e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark struct edid *edid = (struct edid *)do_get_edid(encoder); 999e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark int n = 0; 1000e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 1001e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark if (edid) { 1002e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark drm_mode_connector_update_edid_property(connector, edid); 1003e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark n = drm_add_edid_modes(connector, edid); 1004c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King priv->is_hdmi_sink = drm_detect_hdmi_monitor(edid); 1005e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark kfree(edid); 1006e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark } 1007e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 1008e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark return n; 1009e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark} 1010e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 1011e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clarkstatic int 1012e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clarktda998x_encoder_create_resources(struct drm_encoder *encoder, 1013e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark struct drm_connector *connector) 1014e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark{ 1015e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark DBG(""); 1016e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark return 0; 1017e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark} 1018e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 1019e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clarkstatic int 1020e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clarktda998x_encoder_set_property(struct drm_encoder *encoder, 1021e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark struct drm_connector *connector, 1022e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark struct drm_property *property, 1023e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark uint64_t val) 1024e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark{ 1025e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark DBG(""); 1026e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark return 0; 1027e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark} 1028e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 1029e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clarkstatic void 1030e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clarktda998x_encoder_destroy(struct drm_encoder *encoder) 1031e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark{ 1032e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark struct tda998x_priv *priv = to_tda998x_priv(encoder); 1033e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark drm_i2c_encoder_destroy(encoder); 1034e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark kfree(priv); 1035e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark} 1036e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 1037e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clarkstatic struct drm_encoder_slave_funcs tda998x_encoder_funcs = { 1038e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark .set_config = tda998x_encoder_set_config, 1039e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark .destroy = tda998x_encoder_destroy, 1040e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark .dpms = tda998x_encoder_dpms, 1041e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark .save = tda998x_encoder_save, 1042e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark .restore = tda998x_encoder_restore, 1043e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark .mode_fixup = tda998x_encoder_mode_fixup, 1044e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark .mode_valid = tda998x_encoder_mode_valid, 1045e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark .mode_set = tda998x_encoder_mode_set, 1046e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark .detect = tda998x_encoder_detect, 1047e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark .get_modes = tda998x_encoder_get_modes, 1048e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark .create_resources = tda998x_encoder_create_resources, 1049e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark .set_property = tda998x_encoder_set_property, 1050e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark}; 1051e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 1052e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark/* I2C driver functions */ 1053e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 1054e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clarkstatic int 1055e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clarktda998x_probe(struct i2c_client *client, const struct i2c_device_id *id) 1056e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark{ 1057e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark return 0; 1058e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark} 1059e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 1060e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clarkstatic int 1061e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clarktda998x_remove(struct i2c_client *client) 1062e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark{ 1063e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark return 0; 1064e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark} 1065e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 1066e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clarkstatic int 1067e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clarktda998x_encoder_init(struct i2c_client *client, 1068e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark struct drm_device *dev, 1069e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark struct drm_encoder_slave *encoder_slave) 1070e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark{ 1071e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark struct drm_encoder *encoder = &encoder_slave->base; 1072e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark struct tda998x_priv *priv; 1073e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 1074e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark priv = kzalloc(sizeof(*priv), GFP_KERNEL); 1075e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark if (!priv) 1076e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark return -ENOMEM; 1077e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 10785e74c22cd1e0f9e49573fe580de47e198ee04975Russell King priv->vip_cntrl_0 = VIP_CNTRL_0_SWAP_A(2) | VIP_CNTRL_0_SWAP_B(3); 10795e74c22cd1e0f9e49573fe580de47e198ee04975Russell King priv->vip_cntrl_1 = VIP_CNTRL_1_SWAP_C(0) | VIP_CNTRL_1_SWAP_D(1); 10805e74c22cd1e0f9e49573fe580de47e198ee04975Russell King priv->vip_cntrl_2 = VIP_CNTRL_2_SWAP_E(4) | VIP_CNTRL_2_SWAP_F(5); 10815e74c22cd1e0f9e49573fe580de47e198ee04975Russell King 1082e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark priv->current_page = 0; 1083e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark priv->cec = i2c_new_dummy(client->adapter, 0x34); 1084e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark priv->dpms = DRM_MODE_DPMS_OFF; 1085e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 1086e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark encoder_slave->slave_priv = priv; 1087e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark encoder_slave->slave_funcs = &tda998x_encoder_funcs; 1088e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 1089e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark /* wake up the device: */ 1090e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark cec_write(encoder, REG_CEC_ENAMODS, 1091e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark CEC_ENAMODS_EN_RXSENS | CEC_ENAMODS_EN_HDMI); 1092e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 1093e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark tda998x_reset(encoder); 1094e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 1095e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark /* read version: */ 1096e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark priv->rev = reg_read(encoder, REG_VERSION_LSB) | 1097e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark reg_read(encoder, REG_VERSION_MSB) << 8; 1098e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 1099e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark /* mask off feature bits: */ 1100e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark priv->rev &= ~0x30; /* not-hdcp and not-scalar bit */ 1101e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 1102e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark switch (priv->rev) { 1103e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark case TDA9989N2: dev_info(dev->dev, "found TDA9989 n2"); break; 1104e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark case TDA19989: dev_info(dev->dev, "found TDA19989"); break; 1105e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark case TDA19989N2: dev_info(dev->dev, "found TDA19989 n2"); break; 1106e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark case TDA19988: dev_info(dev->dev, "found TDA19988"); break; 1107e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark default: 1108e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark DBG("found unsupported device: %04x", priv->rev); 1109e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark goto fail; 1110e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark } 1111e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 1112e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark /* after reset, enable DDC: */ 1113e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark reg_write(encoder, REG_DDC_DISABLE, 0x00); 1114e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 1115e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark /* set clock on DDC channel: */ 1116e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark reg_write(encoder, REG_TX3, 39); 1117e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 1118e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark /* if necessary, disable multi-master: */ 1119e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark if (priv->rev == TDA19989) 1120e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark reg_set(encoder, REG_I2C_MASTER, I2C_MASTER_DIS_MM); 1121e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 1122e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark cec_write(encoder, REG_CEC_FRO_IM_CLK_CTRL, 1123e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark CEC_FRO_IM_CLK_CTRL_GHOST_DIS | CEC_FRO_IM_CLK_CTRL_IMCLK_SEL); 1124e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 1125e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark return 0; 1126e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 1127e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clarkfail: 1128e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark /* if encoder_init fails, the encoder slave is never registered, 1129e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark * so cleanup here: 1130e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark */ 1131e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark if (priv->cec) 1132e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark i2c_unregister_device(priv->cec); 1133e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark kfree(priv); 1134e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark encoder_slave->slave_priv = NULL; 1135e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark encoder_slave->slave_funcs = NULL; 1136e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark return -ENXIO; 1137e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark} 1138e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 1139e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clarkstatic struct i2c_device_id tda998x_ids[] = { 1140e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark { "tda998x", 0 }, 1141e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark { } 1142e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark}; 1143e7792ce2da5ded80861db787ace9b57ecf7bc96cRob ClarkMODULE_DEVICE_TABLE(i2c, tda998x_ids); 1144e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 1145e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clarkstatic struct drm_i2c_encoder_driver tda998x_driver = { 1146e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark .i2c_driver = { 1147e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark .probe = tda998x_probe, 1148e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark .remove = tda998x_remove, 1149e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark .driver = { 1150e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark .name = "tda998x", 1151e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark }, 1152e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark .id_table = tda998x_ids, 1153e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark }, 1154e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark .encoder_init = tda998x_encoder_init, 1155e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark}; 1156e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 1157e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark/* Module initialization */ 1158e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 1159e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clarkstatic int __init 1160e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clarktda998x_init(void) 1161e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark{ 1162e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark DBG(""); 1163e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark return drm_i2c_encoder_register(THIS_MODULE, &tda998x_driver); 1164e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark} 1165e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 1166e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clarkstatic void __exit 1167e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clarktda998x_exit(void) 1168e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark{ 1169e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark DBG(""); 1170e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark drm_i2c_encoder_unregister(&tda998x_driver); 1171e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark} 1172e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 1173e7792ce2da5ded80861db787ace9b57ecf7bc96cRob ClarkMODULE_AUTHOR("Rob Clark <robdclark@gmail.com"); 1174e7792ce2da5ded80861db787ace9b57ecf7bc96cRob ClarkMODULE_DESCRIPTION("NXP Semiconductors TDA998X HDMI Encoder"); 1175e7792ce2da5ded80861db787ace9b57ecf7bc96cRob ClarkMODULE_LICENSE("GPL"); 1176e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 1177e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clarkmodule_init(tda998x_init); 1178e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clarkmodule_exit(tda998x_exit); 1179