tda998x_drv.c revision fb7544d7732f780df989fabf31c5852be953daad
1e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark/* 2e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark * Copyright (C) 2012 Texas Instruments 3e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark * Author: Rob Clark <robdclark@gmail.com> 4e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark * 5e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark * This program is free software; you can redistribute it and/or modify it 6e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark * under the terms of the GNU General Public License version 2 as published by 7e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark * the Free Software Foundation. 8e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark * 9e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark * This program is distributed in the hope that it will be useful, but WITHOUT 10e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark * more details. 13e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark * 14e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark * You should have received a copy of the GNU General Public License along with 15e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark * this program. If not, see <http://www.gnu.org/licenses/>. 16e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark */ 17e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 18e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 19e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 20893c3e538dc338509b0c1121173355e8cfa34ff0Russell King#include <linux/hdmi.h> 21e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark#include <linux/module.h> 22f0b33b282c17337276504d6a700d0f558f1a6891Jean-Francois Moine#include <sound/asoundef.h> 23e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 24e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark#include <drm/drmP.h> 25e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark#include <drm/drm_crtc_helper.h> 26e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark#include <drm/drm_encoder_slave.h> 27e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark#include <drm/drm_edid.h> 28c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King#include <drm/i2c/tda998x.h> 29e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 30e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark#define DBG(fmt, ...) DRM_DEBUG(fmt"\n", ##__VA_ARGS__) 31e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 32e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clarkstruct tda998x_priv { 33e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark struct i2c_client *cec; 342f7f730a4f0fd3376dda9266203f29ceccd0a67fJean-Francois Moine struct i2c_client *hdmi; 35e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark uint16_t rev; 36e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark uint8_t current_page; 37e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark int dpms; 38c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King bool is_hdmi_sink; 395e74c22cd1e0f9e49573fe580de47e198ee04975Russell King u8 vip_cntrl_0; 405e74c22cd1e0f9e49573fe580de47e198ee04975Russell King u8 vip_cntrl_1; 415e74c22cd1e0f9e49573fe580de47e198ee04975Russell King u8 vip_cntrl_2; 42c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King struct tda998x_encoder_params params; 43e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark}; 44e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 45e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark#define to_tda998x_priv(x) ((struct tda998x_priv *)to_encoder_slave(x)->slave_priv) 46e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 47e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark/* The TDA9988 series of devices use a paged register scheme.. to simplify 48e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark * things we encode the page # in upper bits of the register #. To read/ 49e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark * write a given register, we need to make sure CURPAGE register is set 50e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark * appropriately. Which implies reads/writes are not atomic. Fun! 51e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark */ 52e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 53e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark#define REG(page, addr) (((page) << 8) | (addr)) 54e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark#define REG2ADDR(reg) ((reg) & 0xff) 55e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark#define REG2PAGE(reg) (((reg) >> 8) & 0xff) 56e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 57e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark#define REG_CURPAGE 0xff /* write */ 58e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 59e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 60e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark/* Page 00h: General Control */ 61e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark#define REG_VERSION_LSB REG(0x00, 0x00) /* read */ 62e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark#define REG_MAIN_CNTRL0 REG(0x00, 0x01) /* read/write */ 63e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark# define MAIN_CNTRL0_SR (1 << 0) 64e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark# define MAIN_CNTRL0_DECS (1 << 1) 65e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark# define MAIN_CNTRL0_DEHS (1 << 2) 66e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark# define MAIN_CNTRL0_CECS (1 << 3) 67e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark# define MAIN_CNTRL0_CEHS (1 << 4) 68e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark# define MAIN_CNTRL0_SCALER (1 << 7) 69e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark#define REG_VERSION_MSB REG(0x00, 0x02) /* read */ 70e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark#define REG_SOFTRESET REG(0x00, 0x0a) /* write */ 71e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark# define SOFTRESET_AUDIO (1 << 0) 72e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark# define SOFTRESET_I2C_MASTER (1 << 1) 73e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark#define REG_DDC_DISABLE REG(0x00, 0x0b) /* read/write */ 74e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark#define REG_CCLK_ON REG(0x00, 0x0c) /* read/write */ 75e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark#define REG_I2C_MASTER REG(0x00, 0x0d) /* read/write */ 76e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark# define I2C_MASTER_DIS_MM (1 << 0) 77e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark# define I2C_MASTER_DIS_FILT (1 << 1) 78e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark# define I2C_MASTER_APP_STRT_LAT (1 << 2) 79c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King#define REG_FEAT_POWERDOWN REG(0x00, 0x0e) /* read/write */ 80c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King# define FEAT_POWERDOWN_SPDIF (1 << 3) 81e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark#define REG_INT_FLAGS_0 REG(0x00, 0x0f) /* read/write */ 82e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark#define REG_INT_FLAGS_1 REG(0x00, 0x10) /* read/write */ 83e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark#define REG_INT_FLAGS_2 REG(0x00, 0x11) /* read/write */ 84e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark# define INT_FLAGS_2_EDID_BLK_RD (1 << 1) 85c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King#define REG_ENA_ACLK REG(0x00, 0x16) /* read/write */ 86e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark#define REG_ENA_VP_0 REG(0x00, 0x18) /* read/write */ 87e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark#define REG_ENA_VP_1 REG(0x00, 0x19) /* read/write */ 88e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark#define REG_ENA_VP_2 REG(0x00, 0x1a) /* read/write */ 89e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark#define REG_ENA_AP REG(0x00, 0x1e) /* read/write */ 90e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark#define REG_VIP_CNTRL_0 REG(0x00, 0x20) /* write */ 91e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark# define VIP_CNTRL_0_MIRR_A (1 << 7) 92e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark# define VIP_CNTRL_0_SWAP_A(x) (((x) & 7) << 4) 93e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark# define VIP_CNTRL_0_MIRR_B (1 << 3) 94e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark# define VIP_CNTRL_0_SWAP_B(x) (((x) & 7) << 0) 95e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark#define REG_VIP_CNTRL_1 REG(0x00, 0x21) /* write */ 96e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark# define VIP_CNTRL_1_MIRR_C (1 << 7) 97e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark# define VIP_CNTRL_1_SWAP_C(x) (((x) & 7) << 4) 98e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark# define VIP_CNTRL_1_MIRR_D (1 << 3) 99e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark# define VIP_CNTRL_1_SWAP_D(x) (((x) & 7) << 0) 100e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark#define REG_VIP_CNTRL_2 REG(0x00, 0x22) /* write */ 101e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark# define VIP_CNTRL_2_MIRR_E (1 << 7) 102e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark# define VIP_CNTRL_2_SWAP_E(x) (((x) & 7) << 4) 103e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark# define VIP_CNTRL_2_MIRR_F (1 << 3) 104e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark# define VIP_CNTRL_2_SWAP_F(x) (((x) & 7) << 0) 105e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark#define REG_VIP_CNTRL_3 REG(0x00, 0x23) /* write */ 106e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark# define VIP_CNTRL_3_X_TGL (1 << 0) 107e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark# define VIP_CNTRL_3_H_TGL (1 << 1) 108e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark# define VIP_CNTRL_3_V_TGL (1 << 2) 109e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark# define VIP_CNTRL_3_EMB (1 << 3) 110e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark# define VIP_CNTRL_3_SYNC_DE (1 << 4) 111e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark# define VIP_CNTRL_3_SYNC_HS (1 << 5) 112e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark# define VIP_CNTRL_3_DE_INT (1 << 6) 113e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark# define VIP_CNTRL_3_EDGE (1 << 7) 114e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark#define REG_VIP_CNTRL_4 REG(0x00, 0x24) /* write */ 115e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark# define VIP_CNTRL_4_BLC(x) (((x) & 3) << 0) 116e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark# define VIP_CNTRL_4_BLANKIT(x) (((x) & 3) << 2) 117e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark# define VIP_CNTRL_4_CCIR656 (1 << 4) 118e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark# define VIP_CNTRL_4_656_ALT (1 << 5) 119e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark# define VIP_CNTRL_4_TST_656 (1 << 6) 120e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark# define VIP_CNTRL_4_TST_PAT (1 << 7) 121e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark#define REG_VIP_CNTRL_5 REG(0x00, 0x25) /* write */ 122e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark# define VIP_CNTRL_5_CKCASE (1 << 0) 123e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark# define VIP_CNTRL_5_SP_CNT(x) (((x) & 3) << 1) 124c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King#define REG_MUX_AP REG(0x00, 0x26) /* read/write */ 125bcb2481df01a9aee7a09b20d43194011edd35754Russell King#define REG_MUX_VP_VIP_OUT REG(0x00, 0x27) /* read/write */ 126e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark#define REG_MAT_CONTRL REG(0x00, 0x80) /* write */ 127e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark# define MAT_CONTRL_MAT_SC(x) (((x) & 3) << 0) 128e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark# define MAT_CONTRL_MAT_BP (1 << 2) 129e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark#define REG_VIDFORMAT REG(0x00, 0xa0) /* write */ 130e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark#define REG_REFPIX_MSB REG(0x00, 0xa1) /* write */ 131e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark#define REG_REFPIX_LSB REG(0x00, 0xa2) /* write */ 132e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark#define REG_REFLINE_MSB REG(0x00, 0xa3) /* write */ 133e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark#define REG_REFLINE_LSB REG(0x00, 0xa4) /* write */ 134e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark#define REG_NPIX_MSB REG(0x00, 0xa5) /* write */ 135e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark#define REG_NPIX_LSB REG(0x00, 0xa6) /* write */ 136e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark#define REG_NLINE_MSB REG(0x00, 0xa7) /* write */ 137e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark#define REG_NLINE_LSB REG(0x00, 0xa8) /* write */ 138e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark#define REG_VS_LINE_STRT_1_MSB REG(0x00, 0xa9) /* write */ 139e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark#define REG_VS_LINE_STRT_1_LSB REG(0x00, 0xaa) /* write */ 140e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark#define REG_VS_PIX_STRT_1_MSB REG(0x00, 0xab) /* write */ 141e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark#define REG_VS_PIX_STRT_1_LSB REG(0x00, 0xac) /* write */ 142e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark#define REG_VS_LINE_END_1_MSB REG(0x00, 0xad) /* write */ 143e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark#define REG_VS_LINE_END_1_LSB REG(0x00, 0xae) /* write */ 144e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark#define REG_VS_PIX_END_1_MSB REG(0x00, 0xaf) /* write */ 145e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark#define REG_VS_PIX_END_1_LSB REG(0x00, 0xb0) /* write */ 146088d61d1fdfde56850c157138a6dc08880c1853dSebastian Hesselbarth#define REG_VS_LINE_STRT_2_MSB REG(0x00, 0xb1) /* write */ 147088d61d1fdfde56850c157138a6dc08880c1853dSebastian Hesselbarth#define REG_VS_LINE_STRT_2_LSB REG(0x00, 0xb2) /* write */ 148e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark#define REG_VS_PIX_STRT_2_MSB REG(0x00, 0xb3) /* write */ 149e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark#define REG_VS_PIX_STRT_2_LSB REG(0x00, 0xb4) /* write */ 150088d61d1fdfde56850c157138a6dc08880c1853dSebastian Hesselbarth#define REG_VS_LINE_END_2_MSB REG(0x00, 0xb5) /* write */ 151088d61d1fdfde56850c157138a6dc08880c1853dSebastian Hesselbarth#define REG_VS_LINE_END_2_LSB REG(0x00, 0xb6) /* write */ 152e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark#define REG_VS_PIX_END_2_MSB REG(0x00, 0xb7) /* write */ 153e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark#define REG_VS_PIX_END_2_LSB REG(0x00, 0xb8) /* write */ 154e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark#define REG_HS_PIX_START_MSB REG(0x00, 0xb9) /* write */ 155e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark#define REG_HS_PIX_START_LSB REG(0x00, 0xba) /* write */ 156e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark#define REG_HS_PIX_STOP_MSB REG(0x00, 0xbb) /* write */ 157e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark#define REG_HS_PIX_STOP_LSB REG(0x00, 0xbc) /* write */ 158e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark#define REG_VWIN_START_1_MSB REG(0x00, 0xbd) /* write */ 159e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark#define REG_VWIN_START_1_LSB REG(0x00, 0xbe) /* write */ 160e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark#define REG_VWIN_END_1_MSB REG(0x00, 0xbf) /* write */ 161e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark#define REG_VWIN_END_1_LSB REG(0x00, 0xc0) /* write */ 162088d61d1fdfde56850c157138a6dc08880c1853dSebastian Hesselbarth#define REG_VWIN_START_2_MSB REG(0x00, 0xc1) /* write */ 163088d61d1fdfde56850c157138a6dc08880c1853dSebastian Hesselbarth#define REG_VWIN_START_2_LSB REG(0x00, 0xc2) /* write */ 164088d61d1fdfde56850c157138a6dc08880c1853dSebastian Hesselbarth#define REG_VWIN_END_2_MSB REG(0x00, 0xc3) /* write */ 165088d61d1fdfde56850c157138a6dc08880c1853dSebastian Hesselbarth#define REG_VWIN_END_2_LSB REG(0x00, 0xc4) /* write */ 166e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark#define REG_DE_START_MSB REG(0x00, 0xc5) /* write */ 167e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark#define REG_DE_START_LSB REG(0x00, 0xc6) /* write */ 168e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark#define REG_DE_STOP_MSB REG(0x00, 0xc7) /* write */ 169e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark#define REG_DE_STOP_LSB REG(0x00, 0xc8) /* write */ 170e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark#define REG_TBG_CNTRL_0 REG(0x00, 0xca) /* write */ 171088d61d1fdfde56850c157138a6dc08880c1853dSebastian Hesselbarth# define TBG_CNTRL_0_TOP_TGL (1 << 0) 172088d61d1fdfde56850c157138a6dc08880c1853dSebastian Hesselbarth# define TBG_CNTRL_0_TOP_SEL (1 << 1) 173088d61d1fdfde56850c157138a6dc08880c1853dSebastian Hesselbarth# define TBG_CNTRL_0_DE_EXT (1 << 2) 174088d61d1fdfde56850c157138a6dc08880c1853dSebastian Hesselbarth# define TBG_CNTRL_0_TOP_EXT (1 << 3) 175e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark# define TBG_CNTRL_0_FRAME_DIS (1 << 5) 176e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark# define TBG_CNTRL_0_SYNC_MTHD (1 << 6) 177e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark# define TBG_CNTRL_0_SYNC_ONCE (1 << 7) 178e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark#define REG_TBG_CNTRL_1 REG(0x00, 0xcb) /* write */ 179088d61d1fdfde56850c157138a6dc08880c1853dSebastian Hesselbarth# define TBG_CNTRL_1_H_TGL (1 << 0) 180088d61d1fdfde56850c157138a6dc08880c1853dSebastian Hesselbarth# define TBG_CNTRL_1_V_TGL (1 << 1) 181088d61d1fdfde56850c157138a6dc08880c1853dSebastian Hesselbarth# define TBG_CNTRL_1_TGL_EN (1 << 2) 182088d61d1fdfde56850c157138a6dc08880c1853dSebastian Hesselbarth# define TBG_CNTRL_1_X_EXT (1 << 3) 183088d61d1fdfde56850c157138a6dc08880c1853dSebastian Hesselbarth# define TBG_CNTRL_1_H_EXT (1 << 4) 184088d61d1fdfde56850c157138a6dc08880c1853dSebastian Hesselbarth# define TBG_CNTRL_1_V_EXT (1 << 5) 185e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark# define TBG_CNTRL_1_DWIN_DIS (1 << 6) 186e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark#define REG_ENABLE_SPACE REG(0x00, 0xd6) /* write */ 187e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark#define REG_HVF_CNTRL_0 REG(0x00, 0xe4) /* write */ 188e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark# define HVF_CNTRL_0_SM (1 << 7) 189e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark# define HVF_CNTRL_0_RWB (1 << 6) 190e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark# define HVF_CNTRL_0_PREFIL(x) (((x) & 3) << 2) 191e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark# define HVF_CNTRL_0_INTPOL(x) (((x) & 3) << 0) 192e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark#define REG_HVF_CNTRL_1 REG(0x00, 0xe5) /* write */ 193e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark# define HVF_CNTRL_1_FOR (1 << 0) 194e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark# define HVF_CNTRL_1_YUVBLK (1 << 1) 195e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark# define HVF_CNTRL_1_VQR(x) (((x) & 3) << 2) 196e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark# define HVF_CNTRL_1_PAD(x) (((x) & 3) << 4) 197e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark# define HVF_CNTRL_1_SEMI_PLANAR (1 << 6) 198e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark#define REG_RPT_CNTRL REG(0x00, 0xf0) /* write */ 199c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King#define REG_I2S_FORMAT REG(0x00, 0xfc) /* read/write */ 200c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King# define I2S_FORMAT(x) (((x) & 3) << 0) 201c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King#define REG_AIP_CLKSEL REG(0x00, 0xfd) /* write */ 202c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King# define AIP_CLKSEL_FS(x) (((x) & 3) << 0) 203c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King# define AIP_CLKSEL_CLK_POL(x) (((x) & 1) << 2) 204c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King# define AIP_CLKSEL_AIP(x) (((x) & 7) << 3) 205e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 206e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 207e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark/* Page 02h: PLL settings */ 208e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark#define REG_PLL_SERIAL_1 REG(0x02, 0x00) /* read/write */ 209e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark# define PLL_SERIAL_1_SRL_FDN (1 << 0) 210e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark# define PLL_SERIAL_1_SRL_IZ(x) (((x) & 3) << 1) 211e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark# define PLL_SERIAL_1_SRL_MAN_IZ (1 << 6) 212e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark#define REG_PLL_SERIAL_2 REG(0x02, 0x01) /* read/write */ 2133ae471f73a1d581e078b5b06d08d7b82833a093fJean-Francois Moine# define PLL_SERIAL_2_SRL_NOSC(x) ((x) << 0) 214e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark# define PLL_SERIAL_2_SRL_PR(x) (((x) & 0xf) << 4) 215e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark#define REG_PLL_SERIAL_3 REG(0x02, 0x02) /* read/write */ 216e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark# define PLL_SERIAL_3_SRL_CCIR (1 << 0) 217e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark# define PLL_SERIAL_3_SRL_DE (1 << 2) 218e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark# define PLL_SERIAL_3_SRL_PXIN_SEL (1 << 4) 219e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark#define REG_SERIALIZER REG(0x02, 0x03) /* read/write */ 220e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark#define REG_BUFFER_OUT REG(0x02, 0x04) /* read/write */ 221e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark#define REG_PLL_SCG1 REG(0x02, 0x05) /* read/write */ 222e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark#define REG_PLL_SCG2 REG(0x02, 0x06) /* read/write */ 223e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark#define REG_PLL_SCGN1 REG(0x02, 0x07) /* read/write */ 224e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark#define REG_PLL_SCGN2 REG(0x02, 0x08) /* read/write */ 225e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark#define REG_PLL_SCGR1 REG(0x02, 0x09) /* read/write */ 226e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark#define REG_PLL_SCGR2 REG(0x02, 0x0a) /* read/write */ 227e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark#define REG_AUDIO_DIV REG(0x02, 0x0e) /* read/write */ 228c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King# define AUDIO_DIV_SERCLK_1 0 229c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King# define AUDIO_DIV_SERCLK_2 1 230c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King# define AUDIO_DIV_SERCLK_4 2 231c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King# define AUDIO_DIV_SERCLK_8 3 232c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King# define AUDIO_DIV_SERCLK_16 4 233c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King# define AUDIO_DIV_SERCLK_32 5 234e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark#define REG_SEL_CLK REG(0x02, 0x11) /* read/write */ 235e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark# define SEL_CLK_SEL_CLK1 (1 << 0) 236e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark# define SEL_CLK_SEL_VRF_CLK(x) (((x) & 3) << 1) 237e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark# define SEL_CLK_ENA_SC_CLK (1 << 3) 238e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark#define REG_ANA_GENERAL REG(0x02, 0x12) /* read/write */ 239e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 240e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 241e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark/* Page 09h: EDID Control */ 242e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark#define REG_EDID_DATA_0 REG(0x09, 0x00) /* read */ 243e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark/* next 127 successive registers are the EDID block */ 244e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark#define REG_EDID_CTRL REG(0x09, 0xfa) /* read/write */ 245e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark#define REG_DDC_ADDR REG(0x09, 0xfb) /* read/write */ 246e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark#define REG_DDC_OFFS REG(0x09, 0xfc) /* read/write */ 247e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark#define REG_DDC_SEGM_ADDR REG(0x09, 0xfd) /* read/write */ 248e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark#define REG_DDC_SEGM REG(0x09, 0xfe) /* read/write */ 249e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 250e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 251e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark/* Page 10h: information frames and packets */ 252c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King#define REG_IF1_HB0 REG(0x10, 0x20) /* read/write */ 253c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King#define REG_IF2_HB0 REG(0x10, 0x40) /* read/write */ 254c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King#define REG_IF3_HB0 REG(0x10, 0x60) /* read/write */ 255c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King#define REG_IF4_HB0 REG(0x10, 0x80) /* read/write */ 256c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King#define REG_IF5_HB0 REG(0x10, 0xa0) /* read/write */ 257e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 258e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 259e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark/* Page 11h: audio settings and content info packets */ 260e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark#define REG_AIP_CNTRL_0 REG(0x11, 0x00) /* read/write */ 261e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark# define AIP_CNTRL_0_RST_FIFO (1 << 0) 262e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark# define AIP_CNTRL_0_SWAP (1 << 1) 263e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark# define AIP_CNTRL_0_LAYOUT (1 << 2) 264e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark# define AIP_CNTRL_0_ACR_MAN (1 << 5) 265e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark# define AIP_CNTRL_0_RST_CTS (1 << 6) 266c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King#define REG_CA_I2S REG(0x11, 0x01) /* read/write */ 267c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King# define CA_I2S_CA_I2S(x) (((x) & 31) << 0) 268c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King# define CA_I2S_HBR_CHSTAT (1 << 6) 269c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King#define REG_LATENCY_RD REG(0x11, 0x04) /* read/write */ 270c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King#define REG_ACR_CTS_0 REG(0x11, 0x05) /* read/write */ 271c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King#define REG_ACR_CTS_1 REG(0x11, 0x06) /* read/write */ 272c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King#define REG_ACR_CTS_2 REG(0x11, 0x07) /* read/write */ 273c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King#define REG_ACR_N_0 REG(0x11, 0x08) /* read/write */ 274c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King#define REG_ACR_N_1 REG(0x11, 0x09) /* read/write */ 275c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King#define REG_ACR_N_2 REG(0x11, 0x0a) /* read/write */ 276c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King#define REG_CTS_N REG(0x11, 0x0c) /* read/write */ 277c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King# define CTS_N_K(x) (((x) & 7) << 0) 278c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King# define CTS_N_M(x) (((x) & 3) << 4) 279e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark#define REG_ENC_CNTRL REG(0x11, 0x0d) /* read/write */ 280e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark# define ENC_CNTRL_RST_ENC (1 << 0) 281e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark# define ENC_CNTRL_RST_SEL (1 << 1) 282e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark# define ENC_CNTRL_CTL_CODE(x) (((x) & 3) << 2) 283c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King#define REG_DIP_FLAGS REG(0x11, 0x0e) /* read/write */ 284c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King# define DIP_FLAGS_ACR (1 << 0) 285c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King# define DIP_FLAGS_GC (1 << 1) 286c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King#define REG_DIP_IF_FLAGS REG(0x11, 0x0f) /* read/write */ 287c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King# define DIP_IF_FLAGS_IF1 (1 << 1) 288c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King# define DIP_IF_FLAGS_IF2 (1 << 2) 289c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King# define DIP_IF_FLAGS_IF3 (1 << 3) 290c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King# define DIP_IF_FLAGS_IF4 (1 << 4) 291c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King# define DIP_IF_FLAGS_IF5 (1 << 5) 292c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King#define REG_CH_STAT_B(x) REG(0x11, 0x14 + (x)) /* read/write */ 293e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 294e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 295e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark/* Page 12h: HDCP and OTP */ 296e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark#define REG_TX3 REG(0x12, 0x9a) /* read/write */ 297063b472fbb44ac562797a630ac3516720f588140Russell King#define REG_TX4 REG(0x12, 0x9b) /* read/write */ 298063b472fbb44ac562797a630ac3516720f588140Russell King# define TX4_PD_RAM (1 << 1) 299e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark#define REG_TX33 REG(0x12, 0xb8) /* read/write */ 300e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark# define TX33_HDMI (1 << 1) 301e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 302e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 303e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark/* Page 13h: Gamut related metadata packets */ 304e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 305e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 306e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 307e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark/* CEC registers: (not paged) 308e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark */ 309e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark#define REG_CEC_FRO_IM_CLK_CTRL 0xfb /* read/write */ 310e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark# define CEC_FRO_IM_CLK_CTRL_GHOST_DIS (1 << 7) 311e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark# define CEC_FRO_IM_CLK_CTRL_ENA_OTP (1 << 6) 312e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark# define CEC_FRO_IM_CLK_CTRL_IMCLK_SEL (1 << 1) 313e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark# define CEC_FRO_IM_CLK_CTRL_FRO_DIV (1 << 0) 314e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark#define REG_CEC_RXSHPDLEV 0xfe /* read */ 315e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark# define CEC_RXSHPDLEV_RXSENS (1 << 0) 316e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark# define CEC_RXSHPDLEV_HPD (1 << 1) 317e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 318e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark#define REG_CEC_ENAMODS 0xff /* read/write */ 319e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark# define CEC_ENAMODS_DIS_FRO (1 << 6) 320e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark# define CEC_ENAMODS_DIS_CCLK (1 << 5) 321e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark# define CEC_ENAMODS_EN_RXSENS (1 << 2) 322e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark# define CEC_ENAMODS_EN_HDMI (1 << 1) 323e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark# define CEC_ENAMODS_EN_CEC (1 << 0) 324e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 325e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 326e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark/* Device versions: */ 327e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark#define TDA9989N2 0x0101 328e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark#define TDA19989 0x0201 329e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark#define TDA19989N2 0x0202 330e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark#define TDA19988 0x0301 331e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 332e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clarkstatic void 3332f7f730a4f0fd3376dda9266203f29ceccd0a67fJean-Francois Moinecec_write(struct tda998x_priv *priv, uint16_t addr, uint8_t val) 334e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark{ 3352f7f730a4f0fd3376dda9266203f29ceccd0a67fJean-Francois Moine struct i2c_client *client = priv->cec; 336e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark uint8_t buf[] = {addr, val}; 337e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark int ret; 338e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 339e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark ret = i2c_master_send(client, buf, ARRAY_SIZE(buf)); 340e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark if (ret < 0) 341e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark dev_err(&client->dev, "Error %d writing to cec:0x%x\n", ret, addr); 342e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark} 343e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 344e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clarkstatic uint8_t 3452f7f730a4f0fd3376dda9266203f29ceccd0a67fJean-Francois Moinecec_read(struct tda998x_priv *priv, uint8_t addr) 346e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark{ 3472f7f730a4f0fd3376dda9266203f29ceccd0a67fJean-Francois Moine struct i2c_client *client = priv->cec; 348e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark uint8_t val; 349e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark int ret; 350e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 351e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark ret = i2c_master_send(client, &addr, sizeof(addr)); 352e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark if (ret < 0) 353e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark goto fail; 354e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 355e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark ret = i2c_master_recv(client, &val, sizeof(val)); 356e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark if (ret < 0) 357e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark goto fail; 358e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 359e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark return val; 360e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 361e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clarkfail: 362e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark dev_err(&client->dev, "Error %d reading from cec:0x%x\n", ret, addr); 363e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark return 0; 364e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark} 365e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 3667d2eadc9b9d4eacc6aa8cc0cb33e05b5a6d30256Jean-Francois Moinestatic int 3672f7f730a4f0fd3376dda9266203f29ceccd0a67fJean-Francois Moineset_page(struct tda998x_priv *priv, uint16_t reg) 368e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark{ 369e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark if (REG2PAGE(reg) != priv->current_page) { 3702f7f730a4f0fd3376dda9266203f29ceccd0a67fJean-Francois Moine struct i2c_client *client = priv->hdmi; 371e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark uint8_t buf[] = { 372e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark REG_CURPAGE, REG2PAGE(reg) 373e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark }; 374e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark int ret = i2c_master_send(client, buf, sizeof(buf)); 3757d2eadc9b9d4eacc6aa8cc0cb33e05b5a6d30256Jean-Francois Moine if (ret < 0) { 376e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark dev_err(&client->dev, "Error %d writing to REG_CURPAGE\n", ret); 3777d2eadc9b9d4eacc6aa8cc0cb33e05b5a6d30256Jean-Francois Moine return ret; 3787d2eadc9b9d4eacc6aa8cc0cb33e05b5a6d30256Jean-Francois Moine } 379e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 380e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark priv->current_page = REG2PAGE(reg); 381e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark } 3827d2eadc9b9d4eacc6aa8cc0cb33e05b5a6d30256Jean-Francois Moine return 0; 383e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark} 384e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 385e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clarkstatic int 3862f7f730a4f0fd3376dda9266203f29ceccd0a67fJean-Francois Moinereg_read_range(struct tda998x_priv *priv, uint16_t reg, char *buf, int cnt) 387e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark{ 3882f7f730a4f0fd3376dda9266203f29ceccd0a67fJean-Francois Moine struct i2c_client *client = priv->hdmi; 389e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark uint8_t addr = REG2ADDR(reg); 390e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark int ret; 391e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 3927d2eadc9b9d4eacc6aa8cc0cb33e05b5a6d30256Jean-Francois Moine ret = set_page(priv, reg); 3937d2eadc9b9d4eacc6aa8cc0cb33e05b5a6d30256Jean-Francois Moine if (ret < 0) 3947d2eadc9b9d4eacc6aa8cc0cb33e05b5a6d30256Jean-Francois Moine return ret; 395e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 396e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark ret = i2c_master_send(client, &addr, sizeof(addr)); 397e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark if (ret < 0) 398e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark goto fail; 399e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 400e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark ret = i2c_master_recv(client, buf, cnt); 401e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark if (ret < 0) 402e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark goto fail; 403e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 404e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark return ret; 405e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 406e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clarkfail: 407e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark dev_err(&client->dev, "Error %d reading from 0x%x\n", ret, reg); 408e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark return ret; 409e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark} 410e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 411c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell Kingstatic void 4122f7f730a4f0fd3376dda9266203f29ceccd0a67fJean-Francois Moinereg_write_range(struct tda998x_priv *priv, uint16_t reg, uint8_t *p, int cnt) 413c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King{ 4142f7f730a4f0fd3376dda9266203f29ceccd0a67fJean-Francois Moine struct i2c_client *client = priv->hdmi; 415c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King uint8_t buf[cnt+1]; 416c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King int ret; 417c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King 418c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King buf[0] = REG2ADDR(reg); 419c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King memcpy(&buf[1], p, cnt); 420c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King 4217d2eadc9b9d4eacc6aa8cc0cb33e05b5a6d30256Jean-Francois Moine ret = set_page(priv, reg); 4227d2eadc9b9d4eacc6aa8cc0cb33e05b5a6d30256Jean-Francois Moine if (ret < 0) 4237d2eadc9b9d4eacc6aa8cc0cb33e05b5a6d30256Jean-Francois Moine return; 424c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King 425c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King ret = i2c_master_send(client, buf, cnt + 1); 426c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King if (ret < 0) 427c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King dev_err(&client->dev, "Error %d writing to 0x%x\n", ret, reg); 428c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King} 429c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King 4307d2eadc9b9d4eacc6aa8cc0cb33e05b5a6d30256Jean-Francois Moinestatic int 4312f7f730a4f0fd3376dda9266203f29ceccd0a67fJean-Francois Moinereg_read(struct tda998x_priv *priv, uint16_t reg) 432e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark{ 433e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark uint8_t val = 0; 4347d2eadc9b9d4eacc6aa8cc0cb33e05b5a6d30256Jean-Francois Moine int ret; 4357d2eadc9b9d4eacc6aa8cc0cb33e05b5a6d30256Jean-Francois Moine 4367d2eadc9b9d4eacc6aa8cc0cb33e05b5a6d30256Jean-Francois Moine ret = reg_read_range(priv, reg, &val, sizeof(val)); 4377d2eadc9b9d4eacc6aa8cc0cb33e05b5a6d30256Jean-Francois Moine if (ret < 0) 4387d2eadc9b9d4eacc6aa8cc0cb33e05b5a6d30256Jean-Francois Moine return ret; 439e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark return val; 440e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark} 441e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 442e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clarkstatic void 4432f7f730a4f0fd3376dda9266203f29ceccd0a67fJean-Francois Moinereg_write(struct tda998x_priv *priv, uint16_t reg, uint8_t val) 444e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark{ 4452f7f730a4f0fd3376dda9266203f29ceccd0a67fJean-Francois Moine struct i2c_client *client = priv->hdmi; 446e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark uint8_t buf[] = {REG2ADDR(reg), val}; 447e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark int ret; 448e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 4497d2eadc9b9d4eacc6aa8cc0cb33e05b5a6d30256Jean-Francois Moine ret = set_page(priv, reg); 4507d2eadc9b9d4eacc6aa8cc0cb33e05b5a6d30256Jean-Francois Moine if (ret < 0) 4517d2eadc9b9d4eacc6aa8cc0cb33e05b5a6d30256Jean-Francois Moine return; 452e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 453e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark ret = i2c_master_send(client, buf, ARRAY_SIZE(buf)); 454e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark if (ret < 0) 455e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark dev_err(&client->dev, "Error %d writing to 0x%x\n", ret, reg); 456e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark} 457e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 458e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clarkstatic void 4592f7f730a4f0fd3376dda9266203f29ceccd0a67fJean-Francois Moinereg_write16(struct tda998x_priv *priv, uint16_t reg, uint16_t val) 460e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark{ 4612f7f730a4f0fd3376dda9266203f29ceccd0a67fJean-Francois Moine struct i2c_client *client = priv->hdmi; 462e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark uint8_t buf[] = {REG2ADDR(reg), val >> 8, val}; 463e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark int ret; 464e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 4657d2eadc9b9d4eacc6aa8cc0cb33e05b5a6d30256Jean-Francois Moine ret = set_page(priv, reg); 4667d2eadc9b9d4eacc6aa8cc0cb33e05b5a6d30256Jean-Francois Moine if (ret < 0) 4677d2eadc9b9d4eacc6aa8cc0cb33e05b5a6d30256Jean-Francois Moine return; 468e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 469e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark ret = i2c_master_send(client, buf, ARRAY_SIZE(buf)); 470e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark if (ret < 0) 471e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark dev_err(&client->dev, "Error %d writing to 0x%x\n", ret, reg); 472e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark} 473e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 474e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clarkstatic void 4752f7f730a4f0fd3376dda9266203f29ceccd0a67fJean-Francois Moinereg_set(struct tda998x_priv *priv, uint16_t reg, uint8_t val) 476e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark{ 4777d2eadc9b9d4eacc6aa8cc0cb33e05b5a6d30256Jean-Francois Moine int old_val; 4787d2eadc9b9d4eacc6aa8cc0cb33e05b5a6d30256Jean-Francois Moine 4797d2eadc9b9d4eacc6aa8cc0cb33e05b5a6d30256Jean-Francois Moine old_val = reg_read(priv, reg); 4807d2eadc9b9d4eacc6aa8cc0cb33e05b5a6d30256Jean-Francois Moine if (old_val >= 0) 4817d2eadc9b9d4eacc6aa8cc0cb33e05b5a6d30256Jean-Francois Moine reg_write(priv, reg, old_val | val); 482e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark} 483e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 484e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clarkstatic void 4852f7f730a4f0fd3376dda9266203f29ceccd0a67fJean-Francois Moinereg_clear(struct tda998x_priv *priv, uint16_t reg, uint8_t val) 486e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark{ 4877d2eadc9b9d4eacc6aa8cc0cb33e05b5a6d30256Jean-Francois Moine int old_val; 4887d2eadc9b9d4eacc6aa8cc0cb33e05b5a6d30256Jean-Francois Moine 4897d2eadc9b9d4eacc6aa8cc0cb33e05b5a6d30256Jean-Francois Moine old_val = reg_read(priv, reg); 4907d2eadc9b9d4eacc6aa8cc0cb33e05b5a6d30256Jean-Francois Moine if (old_val >= 0) 4917d2eadc9b9d4eacc6aa8cc0cb33e05b5a6d30256Jean-Francois Moine reg_write(priv, reg, old_val & ~val); 492e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark} 493e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 494e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clarkstatic void 4952f7f730a4f0fd3376dda9266203f29ceccd0a67fJean-Francois Moinetda998x_reset(struct tda998x_priv *priv) 496e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark{ 497e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark /* reset audio and i2c master: */ 4982f7f730a4f0fd3376dda9266203f29ceccd0a67fJean-Francois Moine reg_set(priv, REG_SOFTRESET, SOFTRESET_AUDIO | SOFTRESET_I2C_MASTER); 499e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark msleep(50); 5002f7f730a4f0fd3376dda9266203f29ceccd0a67fJean-Francois Moine reg_clear(priv, REG_SOFTRESET, SOFTRESET_AUDIO | SOFTRESET_I2C_MASTER); 501e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark msleep(50); 502e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 503e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark /* reset transmitter: */ 5042f7f730a4f0fd3376dda9266203f29ceccd0a67fJean-Francois Moine reg_set(priv, REG_MAIN_CNTRL0, MAIN_CNTRL0_SR); 5052f7f730a4f0fd3376dda9266203f29ceccd0a67fJean-Francois Moine reg_clear(priv, REG_MAIN_CNTRL0, MAIN_CNTRL0_SR); 506e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 507e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark /* PLL registers common configuration */ 5082f7f730a4f0fd3376dda9266203f29ceccd0a67fJean-Francois Moine reg_write(priv, REG_PLL_SERIAL_1, 0x00); 5092f7f730a4f0fd3376dda9266203f29ceccd0a67fJean-Francois Moine reg_write(priv, REG_PLL_SERIAL_2, PLL_SERIAL_2_SRL_NOSC(1)); 5102f7f730a4f0fd3376dda9266203f29ceccd0a67fJean-Francois Moine reg_write(priv, REG_PLL_SERIAL_3, 0x00); 5112f7f730a4f0fd3376dda9266203f29ceccd0a67fJean-Francois Moine reg_write(priv, REG_SERIALIZER, 0x00); 5122f7f730a4f0fd3376dda9266203f29ceccd0a67fJean-Francois Moine reg_write(priv, REG_BUFFER_OUT, 0x00); 5132f7f730a4f0fd3376dda9266203f29ceccd0a67fJean-Francois Moine reg_write(priv, REG_PLL_SCG1, 0x00); 5142f7f730a4f0fd3376dda9266203f29ceccd0a67fJean-Francois Moine reg_write(priv, REG_AUDIO_DIV, AUDIO_DIV_SERCLK_8); 5152f7f730a4f0fd3376dda9266203f29ceccd0a67fJean-Francois Moine reg_write(priv, REG_SEL_CLK, SEL_CLK_SEL_CLK1 | SEL_CLK_ENA_SC_CLK); 5162f7f730a4f0fd3376dda9266203f29ceccd0a67fJean-Francois Moine reg_write(priv, REG_PLL_SCGN1, 0xfa); 5172f7f730a4f0fd3376dda9266203f29ceccd0a67fJean-Francois Moine reg_write(priv, REG_PLL_SCGN2, 0x00); 5182f7f730a4f0fd3376dda9266203f29ceccd0a67fJean-Francois Moine reg_write(priv, REG_PLL_SCGR1, 0x5b); 5192f7f730a4f0fd3376dda9266203f29ceccd0a67fJean-Francois Moine reg_write(priv, REG_PLL_SCGR2, 0x00); 5202f7f730a4f0fd3376dda9266203f29ceccd0a67fJean-Francois Moine reg_write(priv, REG_PLL_SCG2, 0x10); 521bcb2481df01a9aee7a09b20d43194011edd35754Russell King 522bcb2481df01a9aee7a09b20d43194011edd35754Russell King /* Write the default value MUX register */ 5232f7f730a4f0fd3376dda9266203f29ceccd0a67fJean-Francois Moine reg_write(priv, REG_MUX_VP_VIP_OUT, 0x24); 524e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark} 525e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 526c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell Kingstatic uint8_t tda998x_cksum(uint8_t *buf, size_t bytes) 527c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King{ 528c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King uint8_t sum = 0; 529c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King 530c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King while (bytes--) 531c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King sum += *buf++; 532c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King return (255 - sum) + 1; 533c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King} 534c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King 535c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King#define HB(x) (x) 536c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King#define PB(x) (HB(2) + 1 + (x)) 537c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King 538c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell Kingstatic void 5392f7f730a4f0fd3376dda9266203f29ceccd0a67fJean-Francois Moinetda998x_write_if(struct tda998x_priv *priv, uint8_t bit, uint16_t addr, 540c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King uint8_t *buf, size_t size) 541c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King{ 542c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King buf[PB(0)] = tda998x_cksum(buf, size); 543c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King 5442f7f730a4f0fd3376dda9266203f29ceccd0a67fJean-Francois Moine reg_clear(priv, REG_DIP_IF_FLAGS, bit); 5452f7f730a4f0fd3376dda9266203f29ceccd0a67fJean-Francois Moine reg_write_range(priv, addr, buf, size); 5462f7f730a4f0fd3376dda9266203f29ceccd0a67fJean-Francois Moine reg_set(priv, REG_DIP_IF_FLAGS, bit); 547c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King} 548c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King 549c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell Kingstatic void 5502f7f730a4f0fd3376dda9266203f29ceccd0a67fJean-Francois Moinetda998x_write_aif(struct tda998x_priv *priv, struct tda998x_encoder_params *p) 551c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King{ 5529e541466eed411cb5462fa9e6181c4d409e7e2efJean-Francois Moine u8 buf[PB(HDMI_AUDIO_INFOFRAME_SIZE) + 1]; 553c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King 5547288ca07b638db485abec5752bd6b1faed1c33efJean-Francois Moine memset(buf, 0, sizeof(buf)); 5559e541466eed411cb5462fa9e6181c4d409e7e2efJean-Francois Moine buf[HB(0)] = HDMI_INFOFRAME_TYPE_AUDIO; 556c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King buf[HB(1)] = 0x01; 5579e541466eed411cb5462fa9e6181c4d409e7e2efJean-Francois Moine buf[HB(2)] = HDMI_AUDIO_INFOFRAME_SIZE; 558c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King buf[PB(1)] = p->audio_frame[1] & 0x07; /* CC */ 559c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King buf[PB(2)] = p->audio_frame[2] & 0x1c; /* SF */ 560c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King buf[PB(4)] = p->audio_frame[4]; 561c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King buf[PB(5)] = p->audio_frame[5] & 0xf8; /* DM_INH + LSV */ 562c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King 5632f7f730a4f0fd3376dda9266203f29ceccd0a67fJean-Francois Moine tda998x_write_if(priv, DIP_IF_FLAGS_IF4, REG_IF4_HB0, buf, 564c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King sizeof(buf)); 565c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King} 566c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King 567c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell Kingstatic void 5682f7f730a4f0fd3376dda9266203f29ceccd0a67fJean-Francois Moinetda998x_write_avi(struct tda998x_priv *priv, struct drm_display_mode *mode) 569c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King{ 5709e541466eed411cb5462fa9e6181c4d409e7e2efJean-Francois Moine u8 buf[PB(HDMI_AVI_INFOFRAME_SIZE) + 1]; 571c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King 572c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King memset(buf, 0, sizeof(buf)); 5739e541466eed411cb5462fa9e6181c4d409e7e2efJean-Francois Moine buf[HB(0)] = HDMI_INFOFRAME_TYPE_AVI; 574c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King buf[HB(1)] = 0x02; 5759e541466eed411cb5462fa9e6181c4d409e7e2efJean-Francois Moine buf[HB(2)] = HDMI_AVI_INFOFRAME_SIZE; 576893c3e538dc338509b0c1121173355e8cfa34ff0Russell King buf[PB(1)] = HDMI_SCAN_MODE_UNDERSCAN; 577bdf6345b3262d0ddbc6405fbc0fedd2941bec08eJean-Francois Moine buf[PB(2)] = HDMI_ACTIVE_ASPECT_PICTURE; 578893c3e538dc338509b0c1121173355e8cfa34ff0Russell King buf[PB(3)] = HDMI_QUANTIZATION_RANGE_FULL << 2; 579c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King buf[PB(4)] = drm_match_cea_mode(mode); 580c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King 5812f7f730a4f0fd3376dda9266203f29ceccd0a67fJean-Francois Moine tda998x_write_if(priv, DIP_IF_FLAGS_IF2, REG_IF2_HB0, buf, 582c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King sizeof(buf)); 583c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King} 584c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King 5852f7f730a4f0fd3376dda9266203f29ceccd0a67fJean-Francois Moinestatic void tda998x_audio_mute(struct tda998x_priv *priv, bool on) 586c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King{ 587c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King if (on) { 5882f7f730a4f0fd3376dda9266203f29ceccd0a67fJean-Francois Moine reg_set(priv, REG_SOFTRESET, SOFTRESET_AUDIO); 5892f7f730a4f0fd3376dda9266203f29ceccd0a67fJean-Francois Moine reg_clear(priv, REG_SOFTRESET, SOFTRESET_AUDIO); 5902f7f730a4f0fd3376dda9266203f29ceccd0a67fJean-Francois Moine reg_set(priv, REG_AIP_CNTRL_0, AIP_CNTRL_0_RST_FIFO); 591c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King } else { 5922f7f730a4f0fd3376dda9266203f29ceccd0a67fJean-Francois Moine reg_clear(priv, REG_AIP_CNTRL_0, AIP_CNTRL_0_RST_FIFO); 593c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King } 594c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King} 595c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King 596c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell Kingstatic void 5972f7f730a4f0fd3376dda9266203f29ceccd0a67fJean-Francois Moinetda998x_configure_audio(struct tda998x_priv *priv, 598c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King struct drm_display_mode *mode, struct tda998x_encoder_params *p) 599c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King{ 600c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King uint8_t buf[6], clksel_aip, clksel_fs, ca_i2s, cts_n, adiv; 601c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King uint32_t n; 602c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King 603c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King /* Enable audio ports */ 6042f7f730a4f0fd3376dda9266203f29ceccd0a67fJean-Francois Moine reg_write(priv, REG_ENA_AP, p->audio_cfg); 6052f7f730a4f0fd3376dda9266203f29ceccd0a67fJean-Francois Moine reg_write(priv, REG_ENA_ACLK, p->audio_clk_cfg); 606c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King 607c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King /* Set audio input source */ 608c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King switch (p->audio_format) { 609c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King case AFMT_SPDIF: 6102f7f730a4f0fd3376dda9266203f29ceccd0a67fJean-Francois Moine reg_write(priv, REG_MUX_AP, 0x40); 611c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King clksel_aip = AIP_CLKSEL_AIP(0); 612c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King /* FS64SPDIF */ 613c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King clksel_fs = AIP_CLKSEL_FS(2); 614c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King cts_n = CTS_N_M(3) | CTS_N_K(3); 615c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King ca_i2s = 0; 616c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King break; 617c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King 618c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King case AFMT_I2S: 6192f7f730a4f0fd3376dda9266203f29ceccd0a67fJean-Francois Moine reg_write(priv, REG_MUX_AP, 0x64); 620c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King clksel_aip = AIP_CLKSEL_AIP(1); 621c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King /* ACLK */ 622c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King clksel_fs = AIP_CLKSEL_FS(0); 623c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King cts_n = CTS_N_M(3) | CTS_N_K(3); 624c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King ca_i2s = CA_I2S_CA_I2S(0); 625c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King break; 6263b28802e37bb1ca1cab584f679c42e72a7e384f8David Herrmann 6273b28802e37bb1ca1cab584f679c42e72a7e384f8David Herrmann default: 6283b28802e37bb1ca1cab584f679c42e72a7e384f8David Herrmann BUG(); 6293b28802e37bb1ca1cab584f679c42e72a7e384f8David Herrmann return; 630c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King } 631c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King 6322f7f730a4f0fd3376dda9266203f29ceccd0a67fJean-Francois Moine reg_write(priv, REG_AIP_CLKSEL, clksel_aip); 6332f7f730a4f0fd3376dda9266203f29ceccd0a67fJean-Francois Moine reg_clear(priv, REG_AIP_CNTRL_0, AIP_CNTRL_0_LAYOUT); 634c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King 635c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King /* Enable automatic CTS generation */ 6362f7f730a4f0fd3376dda9266203f29ceccd0a67fJean-Francois Moine reg_clear(priv, REG_AIP_CNTRL_0, AIP_CNTRL_0_ACR_MAN); 6372f7f730a4f0fd3376dda9266203f29ceccd0a67fJean-Francois Moine reg_write(priv, REG_CTS_N, cts_n); 638c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King 639c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King /* 640c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King * Audio input somehow depends on HDMI line rate which is 641c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King * related to pixclk. Testing showed that modes with pixclk 642c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King * >100MHz need a larger divider while <40MHz need the default. 643c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King * There is no detailed info in the datasheet, so we just 644c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King * assume 100MHz requires larger divider. 645c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King */ 646c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King if (mode->clock > 100000) 647c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King adiv = AUDIO_DIV_SERCLK_16; 648c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King else 649c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King adiv = AUDIO_DIV_SERCLK_8; 6502f7f730a4f0fd3376dda9266203f29ceccd0a67fJean-Francois Moine reg_write(priv, REG_AUDIO_DIV, adiv); 651c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King 652c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King /* 653c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King * This is the approximate value of N, which happens to be 654c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King * the recommended values for non-coherent clocks. 655c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King */ 656c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King n = 128 * p->audio_sample_rate / 1000; 657c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King 658c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King /* Write the CTS and N values */ 659c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King buf[0] = 0x44; 660c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King buf[1] = 0x42; 661c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King buf[2] = 0x01; 662c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King buf[3] = n; 663c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King buf[4] = n >> 8; 664c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King buf[5] = n >> 16; 6652f7f730a4f0fd3376dda9266203f29ceccd0a67fJean-Francois Moine reg_write_range(priv, REG_ACR_CTS_0, buf, 6); 666c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King 667c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King /* Set CTS clock reference */ 6682f7f730a4f0fd3376dda9266203f29ceccd0a67fJean-Francois Moine reg_write(priv, REG_AIP_CLKSEL, clksel_aip | clksel_fs); 669c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King 670c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King /* Reset CTS generator */ 6712f7f730a4f0fd3376dda9266203f29ceccd0a67fJean-Francois Moine reg_set(priv, REG_AIP_CNTRL_0, AIP_CNTRL_0_RST_CTS); 6722f7f730a4f0fd3376dda9266203f29ceccd0a67fJean-Francois Moine reg_clear(priv, REG_AIP_CNTRL_0, AIP_CNTRL_0_RST_CTS); 673c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King 674c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King /* Write the channel status */ 675f0b33b282c17337276504d6a700d0f558f1a6891Jean-Francois Moine buf[0] = IEC958_AES0_CON_NOT_COPYRIGHT; 676c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King buf[1] = 0x00; 677f0b33b282c17337276504d6a700d0f558f1a6891Jean-Francois Moine buf[2] = IEC958_AES3_CON_FS_NOTID; 678f0b33b282c17337276504d6a700d0f558f1a6891Jean-Francois Moine buf[3] = IEC958_AES4_CON_ORIGFS_NOTID | 679f0b33b282c17337276504d6a700d0f558f1a6891Jean-Francois Moine IEC958_AES4_CON_MAX_WORDLEN_24; 6802f7f730a4f0fd3376dda9266203f29ceccd0a67fJean-Francois Moine reg_write_range(priv, REG_CH_STAT_B(0), buf, 4); 681c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King 6822f7f730a4f0fd3376dda9266203f29ceccd0a67fJean-Francois Moine tda998x_audio_mute(priv, true); 683c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King mdelay(20); 6842f7f730a4f0fd3376dda9266203f29ceccd0a67fJean-Francois Moine tda998x_audio_mute(priv, false); 685c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King 686c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King /* Write the audio information packet */ 6872f7f730a4f0fd3376dda9266203f29ceccd0a67fJean-Francois Moine tda998x_write_aif(priv, p); 688c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King} 689c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King 690e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark/* DRM encoder functions */ 691e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 692e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clarkstatic void 693e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clarktda998x_encoder_set_config(struct drm_encoder *encoder, void *params) 694e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark{ 695c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King struct tda998x_priv *priv = to_tda998x_priv(encoder); 696c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King struct tda998x_encoder_params *p = params; 697c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King 698c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King priv->vip_cntrl_0 = VIP_CNTRL_0_SWAP_A(p->swap_a) | 699c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King (p->mirr_a ? VIP_CNTRL_0_MIRR_A : 0) | 700c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King VIP_CNTRL_0_SWAP_B(p->swap_b) | 701c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King (p->mirr_b ? VIP_CNTRL_0_MIRR_B : 0); 702c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King priv->vip_cntrl_1 = VIP_CNTRL_1_SWAP_C(p->swap_c) | 703c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King (p->mirr_c ? VIP_CNTRL_1_MIRR_C : 0) | 704c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King VIP_CNTRL_1_SWAP_D(p->swap_d) | 705c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King (p->mirr_d ? VIP_CNTRL_1_MIRR_D : 0); 706c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King priv->vip_cntrl_2 = VIP_CNTRL_2_SWAP_E(p->swap_e) | 707c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King (p->mirr_e ? VIP_CNTRL_2_MIRR_E : 0) | 708c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King VIP_CNTRL_2_SWAP_F(p->swap_f) | 709c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King (p->mirr_f ? VIP_CNTRL_2_MIRR_F : 0); 710c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King 711c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King priv->params = *p; 712e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark} 713e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 714e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clarkstatic void 715e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clarktda998x_encoder_dpms(struct drm_encoder *encoder, int mode) 716e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark{ 717e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark struct tda998x_priv *priv = to_tda998x_priv(encoder); 718e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 719e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark /* we only care about on or off: */ 720e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark if (mode != DRM_MODE_DPMS_ON) 721e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark mode = DRM_MODE_DPMS_OFF; 722e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 723e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark if (mode == priv->dpms) 724e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark return; 725e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 726e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark switch (mode) { 727e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark case DRM_MODE_DPMS_ON: 728c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King /* enable video ports, audio will be enabled later */ 7292f7f730a4f0fd3376dda9266203f29ceccd0a67fJean-Francois Moine reg_write(priv, REG_ENA_VP_0, 0xff); 7302f7f730a4f0fd3376dda9266203f29ceccd0a67fJean-Francois Moine reg_write(priv, REG_ENA_VP_1, 0xff); 7312f7f730a4f0fd3376dda9266203f29ceccd0a67fJean-Francois Moine reg_write(priv, REG_ENA_VP_2, 0xff); 732e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark /* set muxing after enabling ports: */ 7332f7f730a4f0fd3376dda9266203f29ceccd0a67fJean-Francois Moine reg_write(priv, REG_VIP_CNTRL_0, priv->vip_cntrl_0); 7342f7f730a4f0fd3376dda9266203f29ceccd0a67fJean-Francois Moine reg_write(priv, REG_VIP_CNTRL_1, priv->vip_cntrl_1); 7352f7f730a4f0fd3376dda9266203f29ceccd0a67fJean-Francois Moine reg_write(priv, REG_VIP_CNTRL_2, priv->vip_cntrl_2); 736e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark break; 737e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark case DRM_MODE_DPMS_OFF: 738db6aaf4d55f95dcb6b162c3a59b56eb1e85ccdfeRussell King /* disable video ports */ 7392f7f730a4f0fd3376dda9266203f29ceccd0a67fJean-Francois Moine reg_write(priv, REG_ENA_VP_0, 0x00); 7402f7f730a4f0fd3376dda9266203f29ceccd0a67fJean-Francois Moine reg_write(priv, REG_ENA_VP_1, 0x00); 7412f7f730a4f0fd3376dda9266203f29ceccd0a67fJean-Francois Moine reg_write(priv, REG_ENA_VP_2, 0x00); 742e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark break; 743e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark } 744e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 745e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark priv->dpms = mode; 746e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark} 747e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 748e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clarkstatic void 749e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clarktda998x_encoder_save(struct drm_encoder *encoder) 750e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark{ 751e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark DBG(""); 752e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark} 753e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 754e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clarkstatic void 755e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clarktda998x_encoder_restore(struct drm_encoder *encoder) 756e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark{ 757e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark DBG(""); 758e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark} 759e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 760e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clarkstatic bool 761e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clarktda998x_encoder_mode_fixup(struct drm_encoder *encoder, 762e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark const struct drm_display_mode *mode, 763e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark struct drm_display_mode *adjusted_mode) 764e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark{ 765e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark return true; 766e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark} 767e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 768e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clarkstatic int 769e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clarktda998x_encoder_mode_valid(struct drm_encoder *encoder, 770e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark struct drm_display_mode *mode) 771e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark{ 772e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark return MODE_OK; 773e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark} 774e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 775e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clarkstatic void 776e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clarktda998x_encoder_mode_set(struct drm_encoder *encoder, 777e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark struct drm_display_mode *mode, 778e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark struct drm_display_mode *adjusted_mode) 779e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark{ 780e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark struct tda998x_priv *priv = to_tda998x_priv(encoder); 781088d61d1fdfde56850c157138a6dc08880c1853dSebastian Hesselbarth uint16_t ref_pix, ref_line, n_pix, n_line; 782088d61d1fdfde56850c157138a6dc08880c1853dSebastian Hesselbarth uint16_t hs_pix_s, hs_pix_e; 783088d61d1fdfde56850c157138a6dc08880c1853dSebastian Hesselbarth uint16_t vs1_pix_s, vs1_pix_e, vs1_line_s, vs1_line_e; 784088d61d1fdfde56850c157138a6dc08880c1853dSebastian Hesselbarth uint16_t vs2_pix_s, vs2_pix_e, vs2_line_s, vs2_line_e; 785088d61d1fdfde56850c157138a6dc08880c1853dSebastian Hesselbarth uint16_t vwin1_line_s, vwin1_line_e; 786088d61d1fdfde56850c157138a6dc08880c1853dSebastian Hesselbarth uint16_t vwin2_line_s, vwin2_line_e; 787088d61d1fdfde56850c157138a6dc08880c1853dSebastian Hesselbarth uint16_t de_pix_s, de_pix_e; 788e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark uint8_t reg, div, rep; 789e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 790088d61d1fdfde56850c157138a6dc08880c1853dSebastian Hesselbarth /* 791088d61d1fdfde56850c157138a6dc08880c1853dSebastian Hesselbarth * Internally TDA998x is using ITU-R BT.656 style sync but 792088d61d1fdfde56850c157138a6dc08880c1853dSebastian Hesselbarth * we get VESA style sync. TDA998x is using a reference pixel 793088d61d1fdfde56850c157138a6dc08880c1853dSebastian Hesselbarth * relative to ITU to sync to the input frame and for output 794088d61d1fdfde56850c157138a6dc08880c1853dSebastian Hesselbarth * sync generation. Currently, we are using reference detection 795088d61d1fdfde56850c157138a6dc08880c1853dSebastian Hesselbarth * from HS/VS, i.e. REFPIX/REFLINE denote frame start sync point 796088d61d1fdfde56850c157138a6dc08880c1853dSebastian Hesselbarth * which is position of rising VS with coincident rising HS. 797088d61d1fdfde56850c157138a6dc08880c1853dSebastian Hesselbarth * 798088d61d1fdfde56850c157138a6dc08880c1853dSebastian Hesselbarth * Now there is some issues to take care of: 799088d61d1fdfde56850c157138a6dc08880c1853dSebastian Hesselbarth * - HDMI data islands require sync-before-active 800088d61d1fdfde56850c157138a6dc08880c1853dSebastian Hesselbarth * - TDA998x register values must be > 0 to be enabled 801088d61d1fdfde56850c157138a6dc08880c1853dSebastian Hesselbarth * - REFLINE needs an additional offset of +1 802088d61d1fdfde56850c157138a6dc08880c1853dSebastian Hesselbarth * - REFPIX needs an addtional offset of +1 for UYUV and +3 for RGB 803088d61d1fdfde56850c157138a6dc08880c1853dSebastian Hesselbarth * 804088d61d1fdfde56850c157138a6dc08880c1853dSebastian Hesselbarth * So we add +1 to all horizontal and vertical register values, 805088d61d1fdfde56850c157138a6dc08880c1853dSebastian Hesselbarth * plus an additional +3 for REFPIX as we are using RGB input only. 806e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark */ 807088d61d1fdfde56850c157138a6dc08880c1853dSebastian Hesselbarth n_pix = mode->htotal; 808088d61d1fdfde56850c157138a6dc08880c1853dSebastian Hesselbarth n_line = mode->vtotal; 809088d61d1fdfde56850c157138a6dc08880c1853dSebastian Hesselbarth 810088d61d1fdfde56850c157138a6dc08880c1853dSebastian Hesselbarth hs_pix_e = mode->hsync_end - mode->hdisplay; 811088d61d1fdfde56850c157138a6dc08880c1853dSebastian Hesselbarth hs_pix_s = mode->hsync_start - mode->hdisplay; 812088d61d1fdfde56850c157138a6dc08880c1853dSebastian Hesselbarth de_pix_e = mode->htotal; 813088d61d1fdfde56850c157138a6dc08880c1853dSebastian Hesselbarth de_pix_s = mode->htotal - mode->hdisplay; 814088d61d1fdfde56850c157138a6dc08880c1853dSebastian Hesselbarth ref_pix = 3 + hs_pix_s; 815088d61d1fdfde56850c157138a6dc08880c1853dSebastian Hesselbarth 816179f1aa407b466c06a94f9e54abc948d1e1146e7Sebastian Hesselbarth /* 817179f1aa407b466c06a94f9e54abc948d1e1146e7Sebastian Hesselbarth * Attached LCD controllers may generate broken sync. Allow 818179f1aa407b466c06a94f9e54abc948d1e1146e7Sebastian Hesselbarth * those to adjust the position of the rising VS edge by adding 819179f1aa407b466c06a94f9e54abc948d1e1146e7Sebastian Hesselbarth * HSKEW to ref_pix. 820179f1aa407b466c06a94f9e54abc948d1e1146e7Sebastian Hesselbarth */ 821179f1aa407b466c06a94f9e54abc948d1e1146e7Sebastian Hesselbarth if (adjusted_mode->flags & DRM_MODE_FLAG_HSKEW) 822179f1aa407b466c06a94f9e54abc948d1e1146e7Sebastian Hesselbarth ref_pix += adjusted_mode->hskew; 823179f1aa407b466c06a94f9e54abc948d1e1146e7Sebastian Hesselbarth 824088d61d1fdfde56850c157138a6dc08880c1853dSebastian Hesselbarth if ((mode->flags & DRM_MODE_FLAG_INTERLACE) == 0) { 825088d61d1fdfde56850c157138a6dc08880c1853dSebastian Hesselbarth ref_line = 1 + mode->vsync_start - mode->vdisplay; 826088d61d1fdfde56850c157138a6dc08880c1853dSebastian Hesselbarth vwin1_line_s = mode->vtotal - mode->vdisplay - 1; 827088d61d1fdfde56850c157138a6dc08880c1853dSebastian Hesselbarth vwin1_line_e = vwin1_line_s + mode->vdisplay; 828088d61d1fdfde56850c157138a6dc08880c1853dSebastian Hesselbarth vs1_pix_s = vs1_pix_e = hs_pix_s; 829088d61d1fdfde56850c157138a6dc08880c1853dSebastian Hesselbarth vs1_line_s = mode->vsync_start - mode->vdisplay; 830088d61d1fdfde56850c157138a6dc08880c1853dSebastian Hesselbarth vs1_line_e = vs1_line_s + 831088d61d1fdfde56850c157138a6dc08880c1853dSebastian Hesselbarth mode->vsync_end - mode->vsync_start; 832088d61d1fdfde56850c157138a6dc08880c1853dSebastian Hesselbarth vwin2_line_s = vwin2_line_e = 0; 833088d61d1fdfde56850c157138a6dc08880c1853dSebastian Hesselbarth vs2_pix_s = vs2_pix_e = 0; 834088d61d1fdfde56850c157138a6dc08880c1853dSebastian Hesselbarth vs2_line_s = vs2_line_e = 0; 835088d61d1fdfde56850c157138a6dc08880c1853dSebastian Hesselbarth } else { 836088d61d1fdfde56850c157138a6dc08880c1853dSebastian Hesselbarth ref_line = 1 + (mode->vsync_start - mode->vdisplay)/2; 837088d61d1fdfde56850c157138a6dc08880c1853dSebastian Hesselbarth vwin1_line_s = (mode->vtotal - mode->vdisplay)/2; 838088d61d1fdfde56850c157138a6dc08880c1853dSebastian Hesselbarth vwin1_line_e = vwin1_line_s + mode->vdisplay/2; 839088d61d1fdfde56850c157138a6dc08880c1853dSebastian Hesselbarth vs1_pix_s = vs1_pix_e = hs_pix_s; 840088d61d1fdfde56850c157138a6dc08880c1853dSebastian Hesselbarth vs1_line_s = (mode->vsync_start - mode->vdisplay)/2; 841088d61d1fdfde56850c157138a6dc08880c1853dSebastian Hesselbarth vs1_line_e = vs1_line_s + 842088d61d1fdfde56850c157138a6dc08880c1853dSebastian Hesselbarth (mode->vsync_end - mode->vsync_start)/2; 843088d61d1fdfde56850c157138a6dc08880c1853dSebastian Hesselbarth vwin2_line_s = vwin1_line_s + mode->vtotal/2; 844088d61d1fdfde56850c157138a6dc08880c1853dSebastian Hesselbarth vwin2_line_e = vwin2_line_s + mode->vdisplay/2; 845088d61d1fdfde56850c157138a6dc08880c1853dSebastian Hesselbarth vs2_pix_s = vs2_pix_e = hs_pix_s + mode->htotal/2; 846088d61d1fdfde56850c157138a6dc08880c1853dSebastian Hesselbarth vs2_line_s = vs1_line_s + mode->vtotal/2 ; 847088d61d1fdfde56850c157138a6dc08880c1853dSebastian Hesselbarth vs2_line_e = vs2_line_s + 848088d61d1fdfde56850c157138a6dc08880c1853dSebastian Hesselbarth (mode->vsync_end - mode->vsync_start)/2; 849088d61d1fdfde56850c157138a6dc08880c1853dSebastian Hesselbarth } 850e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 851e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark div = 148500 / mode->clock; 8523ae471f73a1d581e078b5b06d08d7b82833a093fJean-Francois Moine if (div != 0) { 8533ae471f73a1d581e078b5b06d08d7b82833a093fJean-Francois Moine div--; 8543ae471f73a1d581e078b5b06d08d7b82833a093fJean-Francois Moine if (div > 3) 8553ae471f73a1d581e078b5b06d08d7b82833a093fJean-Francois Moine div = 3; 8563ae471f73a1d581e078b5b06d08d7b82833a093fJean-Francois Moine } 857e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 858e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark /* mute the audio FIFO: */ 8592f7f730a4f0fd3376dda9266203f29ceccd0a67fJean-Francois Moine reg_set(priv, REG_AIP_CNTRL_0, AIP_CNTRL_0_RST_FIFO); 860e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 861e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark /* set HDMI HDCP mode off: */ 8622f7f730a4f0fd3376dda9266203f29ceccd0a67fJean-Francois Moine reg_set(priv, REG_TBG_CNTRL_1, TBG_CNTRL_1_DWIN_DIS); 8632f7f730a4f0fd3376dda9266203f29ceccd0a67fJean-Francois Moine reg_clear(priv, REG_TX33, TX33_HDMI); 8642f7f730a4f0fd3376dda9266203f29ceccd0a67fJean-Francois Moine reg_write(priv, REG_ENC_CNTRL, ENC_CNTRL_CTL_CODE(0)); 865e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 866e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark /* no pre-filter or interpolator: */ 8672f7f730a4f0fd3376dda9266203f29ceccd0a67fJean-Francois Moine reg_write(priv, REG_HVF_CNTRL_0, HVF_CNTRL_0_PREFIL(0) | 868e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark HVF_CNTRL_0_INTPOL(0)); 8692f7f730a4f0fd3376dda9266203f29ceccd0a67fJean-Francois Moine reg_write(priv, REG_VIP_CNTRL_5, VIP_CNTRL_5_SP_CNT(0)); 8702f7f730a4f0fd3376dda9266203f29ceccd0a67fJean-Francois Moine reg_write(priv, REG_VIP_CNTRL_4, VIP_CNTRL_4_BLANKIT(0) | 871e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark VIP_CNTRL_4_BLC(0)); 8722f7f730a4f0fd3376dda9266203f29ceccd0a67fJean-Francois Moine reg_clear(priv, REG_PLL_SERIAL_3, PLL_SERIAL_3_SRL_CCIR); 873e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 8742f7f730a4f0fd3376dda9266203f29ceccd0a67fJean-Francois Moine reg_clear(priv, REG_PLL_SERIAL_1, PLL_SERIAL_1_SRL_MAN_IZ); 8752f7f730a4f0fd3376dda9266203f29ceccd0a67fJean-Francois Moine reg_clear(priv, REG_PLL_SERIAL_3, PLL_SERIAL_3_SRL_DE); 8762f7f730a4f0fd3376dda9266203f29ceccd0a67fJean-Francois Moine reg_write(priv, REG_SERIALIZER, 0); 8772f7f730a4f0fd3376dda9266203f29ceccd0a67fJean-Francois Moine reg_write(priv, REG_HVF_CNTRL_1, HVF_CNTRL_1_VQR(0)); 878e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 879e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark /* TODO enable pixel repeat for pixel rates less than 25Msamp/s */ 880e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark rep = 0; 8812f7f730a4f0fd3376dda9266203f29ceccd0a67fJean-Francois Moine reg_write(priv, REG_RPT_CNTRL, 0); 8822f7f730a4f0fd3376dda9266203f29ceccd0a67fJean-Francois Moine reg_write(priv, REG_SEL_CLK, SEL_CLK_SEL_VRF_CLK(0) | 883e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark SEL_CLK_SEL_CLK1 | SEL_CLK_ENA_SC_CLK); 884e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 8852f7f730a4f0fd3376dda9266203f29ceccd0a67fJean-Francois Moine reg_write(priv, REG_PLL_SERIAL_2, PLL_SERIAL_2_SRL_NOSC(div) | 886e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark PLL_SERIAL_2_SRL_PR(rep)); 887e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 888e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark /* set color matrix bypass flag: */ 8892f7f730a4f0fd3376dda9266203f29ceccd0a67fJean-Francois Moine reg_set(priv, REG_MAT_CONTRL, MAT_CONTRL_MAT_BP); 890e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 891e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark /* set BIAS tmds value: */ 8922f7f730a4f0fd3376dda9266203f29ceccd0a67fJean-Francois Moine reg_write(priv, REG_ANA_GENERAL, 0x09); 893e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 8942f7f730a4f0fd3376dda9266203f29ceccd0a67fJean-Francois Moine reg_clear(priv, REG_TBG_CNTRL_0, TBG_CNTRL_0_SYNC_MTHD); 895e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 896088d61d1fdfde56850c157138a6dc08880c1853dSebastian Hesselbarth /* 897088d61d1fdfde56850c157138a6dc08880c1853dSebastian Hesselbarth * Sync on rising HSYNC/VSYNC 898088d61d1fdfde56850c157138a6dc08880c1853dSebastian Hesselbarth */ 8992f7f730a4f0fd3376dda9266203f29ceccd0a67fJean-Francois Moine reg_write(priv, REG_VIP_CNTRL_3, 0); 9002f7f730a4f0fd3376dda9266203f29ceccd0a67fJean-Francois Moine reg_set(priv, REG_VIP_CNTRL_3, VIP_CNTRL_3_SYNC_HS); 901088d61d1fdfde56850c157138a6dc08880c1853dSebastian Hesselbarth 902088d61d1fdfde56850c157138a6dc08880c1853dSebastian Hesselbarth /* 903088d61d1fdfde56850c157138a6dc08880c1853dSebastian Hesselbarth * TDA19988 requires high-active sync at input stage, 904088d61d1fdfde56850c157138a6dc08880c1853dSebastian Hesselbarth * so invert low-active sync provided by master encoder here 905088d61d1fdfde56850c157138a6dc08880c1853dSebastian Hesselbarth */ 906088d61d1fdfde56850c157138a6dc08880c1853dSebastian Hesselbarth if (mode->flags & DRM_MODE_FLAG_NHSYNC) 9072f7f730a4f0fd3376dda9266203f29ceccd0a67fJean-Francois Moine reg_set(priv, REG_VIP_CNTRL_3, VIP_CNTRL_3_H_TGL); 908e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark if (mode->flags & DRM_MODE_FLAG_NVSYNC) 9092f7f730a4f0fd3376dda9266203f29ceccd0a67fJean-Francois Moine reg_set(priv, REG_VIP_CNTRL_3, VIP_CNTRL_3_V_TGL); 910e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 911088d61d1fdfde56850c157138a6dc08880c1853dSebastian Hesselbarth /* 912088d61d1fdfde56850c157138a6dc08880c1853dSebastian Hesselbarth * Always generate sync polarity relative to input sync and 913088d61d1fdfde56850c157138a6dc08880c1853dSebastian Hesselbarth * revert input stage toggled sync at output stage 914088d61d1fdfde56850c157138a6dc08880c1853dSebastian Hesselbarth */ 915088d61d1fdfde56850c157138a6dc08880c1853dSebastian Hesselbarth reg = TBG_CNTRL_1_TGL_EN; 916e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark if (mode->flags & DRM_MODE_FLAG_NHSYNC) 917088d61d1fdfde56850c157138a6dc08880c1853dSebastian Hesselbarth reg |= TBG_CNTRL_1_H_TGL; 918088d61d1fdfde56850c157138a6dc08880c1853dSebastian Hesselbarth if (mode->flags & DRM_MODE_FLAG_NVSYNC) 919088d61d1fdfde56850c157138a6dc08880c1853dSebastian Hesselbarth reg |= TBG_CNTRL_1_V_TGL; 9202f7f730a4f0fd3376dda9266203f29ceccd0a67fJean-Francois Moine reg_write(priv, REG_TBG_CNTRL_1, reg); 9212f7f730a4f0fd3376dda9266203f29ceccd0a67fJean-Francois Moine 9222f7f730a4f0fd3376dda9266203f29ceccd0a67fJean-Francois Moine reg_write(priv, REG_VIDFORMAT, 0x00); 9232f7f730a4f0fd3376dda9266203f29ceccd0a67fJean-Francois Moine reg_write16(priv, REG_REFPIX_MSB, ref_pix); 9242f7f730a4f0fd3376dda9266203f29ceccd0a67fJean-Francois Moine reg_write16(priv, REG_REFLINE_MSB, ref_line); 9252f7f730a4f0fd3376dda9266203f29ceccd0a67fJean-Francois Moine reg_write16(priv, REG_NPIX_MSB, n_pix); 9262f7f730a4f0fd3376dda9266203f29ceccd0a67fJean-Francois Moine reg_write16(priv, REG_NLINE_MSB, n_line); 9272f7f730a4f0fd3376dda9266203f29ceccd0a67fJean-Francois Moine reg_write16(priv, REG_VS_LINE_STRT_1_MSB, vs1_line_s); 9282f7f730a4f0fd3376dda9266203f29ceccd0a67fJean-Francois Moine reg_write16(priv, REG_VS_PIX_STRT_1_MSB, vs1_pix_s); 9292f7f730a4f0fd3376dda9266203f29ceccd0a67fJean-Francois Moine reg_write16(priv, REG_VS_LINE_END_1_MSB, vs1_line_e); 9302f7f730a4f0fd3376dda9266203f29ceccd0a67fJean-Francois Moine reg_write16(priv, REG_VS_PIX_END_1_MSB, vs1_pix_e); 9312f7f730a4f0fd3376dda9266203f29ceccd0a67fJean-Francois Moine reg_write16(priv, REG_VS_LINE_STRT_2_MSB, vs2_line_s); 9322f7f730a4f0fd3376dda9266203f29ceccd0a67fJean-Francois Moine reg_write16(priv, REG_VS_PIX_STRT_2_MSB, vs2_pix_s); 9332f7f730a4f0fd3376dda9266203f29ceccd0a67fJean-Francois Moine reg_write16(priv, REG_VS_LINE_END_2_MSB, vs2_line_e); 9342f7f730a4f0fd3376dda9266203f29ceccd0a67fJean-Francois Moine reg_write16(priv, REG_VS_PIX_END_2_MSB, vs2_pix_e); 9352f7f730a4f0fd3376dda9266203f29ceccd0a67fJean-Francois Moine reg_write16(priv, REG_HS_PIX_START_MSB, hs_pix_s); 9362f7f730a4f0fd3376dda9266203f29ceccd0a67fJean-Francois Moine reg_write16(priv, REG_HS_PIX_STOP_MSB, hs_pix_e); 9372f7f730a4f0fd3376dda9266203f29ceccd0a67fJean-Francois Moine reg_write16(priv, REG_VWIN_START_1_MSB, vwin1_line_s); 9382f7f730a4f0fd3376dda9266203f29ceccd0a67fJean-Francois Moine reg_write16(priv, REG_VWIN_END_1_MSB, vwin1_line_e); 9392f7f730a4f0fd3376dda9266203f29ceccd0a67fJean-Francois Moine reg_write16(priv, REG_VWIN_START_2_MSB, vwin2_line_s); 9402f7f730a4f0fd3376dda9266203f29ceccd0a67fJean-Francois Moine reg_write16(priv, REG_VWIN_END_2_MSB, vwin2_line_e); 9412f7f730a4f0fd3376dda9266203f29ceccd0a67fJean-Francois Moine reg_write16(priv, REG_DE_START_MSB, de_pix_s); 9422f7f730a4f0fd3376dda9266203f29ceccd0a67fJean-Francois Moine reg_write16(priv, REG_DE_STOP_MSB, de_pix_e); 943e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 944e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark if (priv->rev == TDA19988) { 945e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark /* let incoming pixels fill the active space (if any) */ 9462f7f730a4f0fd3376dda9266203f29ceccd0a67fJean-Francois Moine reg_write(priv, REG_ENABLE_SPACE, 0x00); 947e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark } 948e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 949e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark /* must be last register set: */ 9502f7f730a4f0fd3376dda9266203f29ceccd0a67fJean-Francois Moine reg_clear(priv, REG_TBG_CNTRL_0, TBG_CNTRL_0_SYNC_ONCE); 951c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King 952c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King /* Only setup the info frames if the sink is HDMI */ 953c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King if (priv->is_hdmi_sink) { 954c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King /* We need to turn HDMI HDCP stuff on to get audio through */ 9552f7f730a4f0fd3376dda9266203f29ceccd0a67fJean-Francois Moine reg_clear(priv, REG_TBG_CNTRL_1, TBG_CNTRL_1_DWIN_DIS); 9562f7f730a4f0fd3376dda9266203f29ceccd0a67fJean-Francois Moine reg_write(priv, REG_ENC_CNTRL, ENC_CNTRL_CTL_CODE(1)); 9572f7f730a4f0fd3376dda9266203f29ceccd0a67fJean-Francois Moine reg_set(priv, REG_TX33, TX33_HDMI); 958c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King 9592f7f730a4f0fd3376dda9266203f29ceccd0a67fJean-Francois Moine tda998x_write_avi(priv, adjusted_mode); 960c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King 961c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King if (priv->params.audio_cfg) 9622f7f730a4f0fd3376dda9266203f29ceccd0a67fJean-Francois Moine tda998x_configure_audio(priv, adjusted_mode, 963c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King &priv->params); 964c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King } 965e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark} 966e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 967e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clarkstatic enum drm_connector_status 968e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clarktda998x_encoder_detect(struct drm_encoder *encoder, 969e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark struct drm_connector *connector) 970e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark{ 9712f7f730a4f0fd3376dda9266203f29ceccd0a67fJean-Francois Moine struct tda998x_priv *priv = to_tda998x_priv(encoder); 9722f7f730a4f0fd3376dda9266203f29ceccd0a67fJean-Francois Moine uint8_t val = cec_read(priv, REG_CEC_RXSHPDLEV); 9732f7f730a4f0fd3376dda9266203f29ceccd0a67fJean-Francois Moine 974e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark return (val & CEC_RXSHPDLEV_HPD) ? connector_status_connected : 975e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark connector_status_disconnected; 976e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark} 977e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 978e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clarkstatic int 979e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clarkread_edid_block(struct drm_encoder *encoder, uint8_t *buf, int blk) 980e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark{ 9812f7f730a4f0fd3376dda9266203f29ceccd0a67fJean-Francois Moine struct tda998x_priv *priv = to_tda998x_priv(encoder); 982e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark uint8_t offset, segptr; 983e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark int ret, i; 984e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 985e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark /* enable EDID read irq: */ 9862f7f730a4f0fd3376dda9266203f29ceccd0a67fJean-Francois Moine reg_set(priv, REG_INT_FLAGS_2, INT_FLAGS_2_EDID_BLK_RD); 987e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 988e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark offset = (blk & 1) ? 128 : 0; 989e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark segptr = blk / 2; 990e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 9912f7f730a4f0fd3376dda9266203f29ceccd0a67fJean-Francois Moine reg_write(priv, REG_DDC_ADDR, 0xa0); 9922f7f730a4f0fd3376dda9266203f29ceccd0a67fJean-Francois Moine reg_write(priv, REG_DDC_OFFS, offset); 9932f7f730a4f0fd3376dda9266203f29ceccd0a67fJean-Francois Moine reg_write(priv, REG_DDC_SEGM_ADDR, 0x60); 9942f7f730a4f0fd3376dda9266203f29ceccd0a67fJean-Francois Moine reg_write(priv, REG_DDC_SEGM, segptr); 995e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 996e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark /* enable reading EDID: */ 9972f7f730a4f0fd3376dda9266203f29ceccd0a67fJean-Francois Moine reg_write(priv, REG_EDID_CTRL, 0x1); 998e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 999e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark /* flag must be cleared by sw: */ 10002f7f730a4f0fd3376dda9266203f29ceccd0a67fJean-Francois Moine reg_write(priv, REG_EDID_CTRL, 0x0); 1001e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 1002e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark /* wait for block read to complete: */ 1003e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark for (i = 100; i > 0; i--) { 10047d2eadc9b9d4eacc6aa8cc0cb33e05b5a6d30256Jean-Francois Moine ret = reg_read(priv, REG_INT_FLAGS_2); 10057d2eadc9b9d4eacc6aa8cc0cb33e05b5a6d30256Jean-Francois Moine if (ret < 0) 10067d2eadc9b9d4eacc6aa8cc0cb33e05b5a6d30256Jean-Francois Moine return ret; 10077d2eadc9b9d4eacc6aa8cc0cb33e05b5a6d30256Jean-Francois Moine if (ret & INT_FLAGS_2_EDID_BLK_RD) 1008e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark break; 1009e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark msleep(1); 1010e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark } 1011e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 1012e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark if (i == 0) 1013e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark return -ETIMEDOUT; 1014e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 10152f7f730a4f0fd3376dda9266203f29ceccd0a67fJean-Francois Moine ret = reg_read_range(priv, REG_EDID_DATA_0, buf, EDID_LENGTH); 1016e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark if (ret != EDID_LENGTH) { 1017e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark dev_err(encoder->dev->dev, "failed to read edid block %d: %d", 1018e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark blk, ret); 1019e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark return ret; 1020e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark } 1021e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 10222f7f730a4f0fd3376dda9266203f29ceccd0a67fJean-Francois Moine reg_clear(priv, REG_INT_FLAGS_2, INT_FLAGS_2_EDID_BLK_RD); 1023e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 1024e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark return 0; 1025e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark} 1026e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 1027e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clarkstatic uint8_t * 1028e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clarkdo_get_edid(struct drm_encoder *encoder) 1029e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark{ 1030063b472fbb44ac562797a630ac3516720f588140Russell King struct tda998x_priv *priv = to_tda998x_priv(encoder); 1031e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark int j = 0, valid_extensions = 0; 1032e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark uint8_t *block, *new; 1033e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark bool print_bad_edid = drm_debug & DRM_UT_KMS; 1034e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 1035e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark if ((block = kmalloc(EDID_LENGTH, GFP_KERNEL)) == NULL) 1036e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark return NULL; 1037e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 1038063b472fbb44ac562797a630ac3516720f588140Russell King if (priv->rev == TDA19988) 10392f7f730a4f0fd3376dda9266203f29ceccd0a67fJean-Francois Moine reg_clear(priv, REG_TX4, TX4_PD_RAM); 1040063b472fbb44ac562797a630ac3516720f588140Russell King 1041e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark /* base block fetch */ 1042e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark if (read_edid_block(encoder, block, 0)) 1043e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark goto fail; 1044e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 1045e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark if (!drm_edid_block_valid(block, 0, print_bad_edid)) 1046e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark goto fail; 1047e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 1048e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark /* if there's no extensions, we're done */ 1049e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark if (block[0x7e] == 0) 1050063b472fbb44ac562797a630ac3516720f588140Russell King goto done; 1051e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 1052e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark new = krealloc(block, (block[0x7e] + 1) * EDID_LENGTH, GFP_KERNEL); 1053e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark if (!new) 1054e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark goto fail; 1055e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark block = new; 1056e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 1057e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark for (j = 1; j <= block[0x7e]; j++) { 1058e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark uint8_t *ext_block = block + (valid_extensions + 1) * EDID_LENGTH; 1059e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark if (read_edid_block(encoder, ext_block, j)) 1060e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark goto fail; 1061e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 1062e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark if (!drm_edid_block_valid(ext_block, j, print_bad_edid)) 1063e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark goto fail; 1064e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 1065e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark valid_extensions++; 1066e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark } 1067e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 1068e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark if (valid_extensions != block[0x7e]) { 1069e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark block[EDID_LENGTH-1] += block[0x7e] - valid_extensions; 1070e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark block[0x7e] = valid_extensions; 1071e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark new = krealloc(block, (valid_extensions + 1) * EDID_LENGTH, GFP_KERNEL); 1072e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark if (!new) 1073e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark goto fail; 1074e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark block = new; 1075e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark } 1076e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 1077063b472fbb44ac562797a630ac3516720f588140Russell Kingdone: 1078063b472fbb44ac562797a630ac3516720f588140Russell King if (priv->rev == TDA19988) 10792f7f730a4f0fd3376dda9266203f29ceccd0a67fJean-Francois Moine reg_set(priv, REG_TX4, TX4_PD_RAM); 1080063b472fbb44ac562797a630ac3516720f588140Russell King 1081e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark return block; 1082e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 1083e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clarkfail: 1084063b472fbb44ac562797a630ac3516720f588140Russell King if (priv->rev == TDA19988) 10852f7f730a4f0fd3376dda9266203f29ceccd0a67fJean-Francois Moine reg_set(priv, REG_TX4, TX4_PD_RAM); 1086e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark dev_warn(encoder->dev->dev, "failed to read EDID\n"); 1087e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark kfree(block); 1088e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark return NULL; 1089e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark} 1090e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 1091e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clarkstatic int 1092e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clarktda998x_encoder_get_modes(struct drm_encoder *encoder, 1093e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark struct drm_connector *connector) 1094e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark{ 1095c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King struct tda998x_priv *priv = to_tda998x_priv(encoder); 1096e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark struct edid *edid = (struct edid *)do_get_edid(encoder); 1097e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark int n = 0; 1098e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 1099e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark if (edid) { 1100e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark drm_mode_connector_update_edid_property(connector, edid); 1101e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark n = drm_add_edid_modes(connector, edid); 1102c4c11dd160a8cc98f402c4e12f94b1572e822ffdRussell King priv->is_hdmi_sink = drm_detect_hdmi_monitor(edid); 1103e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark kfree(edid); 1104e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark } 1105e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 1106e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark return n; 1107e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark} 1108e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 1109e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clarkstatic int 1110e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clarktda998x_encoder_create_resources(struct drm_encoder *encoder, 1111e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark struct drm_connector *connector) 1112e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark{ 1113e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark DBG(""); 1114e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark return 0; 1115e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark} 1116e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 1117e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clarkstatic int 1118e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clarktda998x_encoder_set_property(struct drm_encoder *encoder, 1119e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark struct drm_connector *connector, 1120e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark struct drm_property *property, 1121e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark uint64_t val) 1122e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark{ 1123e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark DBG(""); 1124e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark return 0; 1125e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark} 1126e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 1127e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clarkstatic void 1128e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clarktda998x_encoder_destroy(struct drm_encoder *encoder) 1129e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark{ 1130e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark struct tda998x_priv *priv = to_tda998x_priv(encoder); 1131e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark drm_i2c_encoder_destroy(encoder); 1132fc275a74eb816c12d4fc226344e734872ed0b2f9Jean-Francois Moine if (priv->cec) 1133fc275a74eb816c12d4fc226344e734872ed0b2f9Jean-Francois Moine i2c_unregister_device(priv->cec); 1134e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark kfree(priv); 1135e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark} 1136e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 1137e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clarkstatic struct drm_encoder_slave_funcs tda998x_encoder_funcs = { 1138e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark .set_config = tda998x_encoder_set_config, 1139e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark .destroy = tda998x_encoder_destroy, 1140e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark .dpms = tda998x_encoder_dpms, 1141e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark .save = tda998x_encoder_save, 1142e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark .restore = tda998x_encoder_restore, 1143e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark .mode_fixup = tda998x_encoder_mode_fixup, 1144e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark .mode_valid = tda998x_encoder_mode_valid, 1145e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark .mode_set = tda998x_encoder_mode_set, 1146e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark .detect = tda998x_encoder_detect, 1147e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark .get_modes = tda998x_encoder_get_modes, 1148e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark .create_resources = tda998x_encoder_create_resources, 1149e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark .set_property = tda998x_encoder_set_property, 1150e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark}; 1151e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 1152e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark/* I2C driver functions */ 1153e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 1154e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clarkstatic int 1155e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clarktda998x_probe(struct i2c_client *client, const struct i2c_device_id *id) 1156e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark{ 1157e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark return 0; 1158e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark} 1159e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 1160e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clarkstatic int 1161e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clarktda998x_remove(struct i2c_client *client) 1162e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark{ 1163e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark return 0; 1164e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark} 1165e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 1166e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clarkstatic int 1167e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clarktda998x_encoder_init(struct i2c_client *client, 1168e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark struct drm_device *dev, 1169e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark struct drm_encoder_slave *encoder_slave) 1170e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark{ 1171e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark struct tda998x_priv *priv; 1172fb7544d7732f780df989fabf31c5852be953daadRussell King int rev_lo, rev_hi, ret; 1173e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 1174e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark priv = kzalloc(sizeof(*priv), GFP_KERNEL); 1175e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark if (!priv) 1176e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark return -ENOMEM; 1177e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 11785e74c22cd1e0f9e49573fe580de47e198ee04975Russell King priv->vip_cntrl_0 = VIP_CNTRL_0_SWAP_A(2) | VIP_CNTRL_0_SWAP_B(3); 11795e74c22cd1e0f9e49573fe580de47e198ee04975Russell King priv->vip_cntrl_1 = VIP_CNTRL_1_SWAP_C(0) | VIP_CNTRL_1_SWAP_D(1); 11805e74c22cd1e0f9e49573fe580de47e198ee04975Russell King priv->vip_cntrl_2 = VIP_CNTRL_2_SWAP_E(4) | VIP_CNTRL_2_SWAP_F(5); 11815e74c22cd1e0f9e49573fe580de47e198ee04975Russell King 11822eb4c7b1e7f275fe833aabe0a251b8e3f767fb08Jean-Francois Moine priv->current_page = 0xff; 11832f7f730a4f0fd3376dda9266203f29ceccd0a67fJean-Francois Moine priv->hdmi = client; 1184e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark priv->cec = i2c_new_dummy(client->adapter, 0x34); 118571c68c4fc9bdcd6e46107a0f40b50a523f3b4fe0Dave Jones if (!priv->cec) { 118671c68c4fc9bdcd6e46107a0f40b50a523f3b4fe0Dave Jones kfree(priv); 11876ae668cc19e8b18df28cd67b3448d9abd79284a4Jean-Francois Moine return -ENODEV; 118871c68c4fc9bdcd6e46107a0f40b50a523f3b4fe0Dave Jones } 1189e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark priv->dpms = DRM_MODE_DPMS_OFF; 1190e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 1191e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark encoder_slave->slave_priv = priv; 1192e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark encoder_slave->slave_funcs = &tda998x_encoder_funcs; 1193e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 1194e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark /* wake up the device: */ 11952f7f730a4f0fd3376dda9266203f29ceccd0a67fJean-Francois Moine cec_write(priv, REG_CEC_ENAMODS, 1196e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark CEC_ENAMODS_EN_RXSENS | CEC_ENAMODS_EN_HDMI); 1197e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 11982f7f730a4f0fd3376dda9266203f29ceccd0a67fJean-Francois Moine tda998x_reset(priv); 1199e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 1200e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark /* read version: */ 1201fb7544d7732f780df989fabf31c5852be953daadRussell King rev_lo = reg_read(priv, REG_VERSION_LSB); 1202fb7544d7732f780df989fabf31c5852be953daadRussell King rev_hi = reg_read(priv, REG_VERSION_MSB); 1203fb7544d7732f780df989fabf31c5852be953daadRussell King if (rev_lo < 0 || rev_hi < 0) { 1204fb7544d7732f780df989fabf31c5852be953daadRussell King ret = rev_lo < 0 ? rev_lo : rev_hi; 12057d2eadc9b9d4eacc6aa8cc0cb33e05b5a6d30256Jean-Francois Moine goto fail; 1206fb7544d7732f780df989fabf31c5852be953daadRussell King } 1207fb7544d7732f780df989fabf31c5852be953daadRussell King 1208fb7544d7732f780df989fabf31c5852be953daadRussell King priv->rev = rev_lo | rev_hi << 8; 1209e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 1210e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark /* mask off feature bits: */ 1211e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark priv->rev &= ~0x30; /* not-hdcp and not-scalar bit */ 1212e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 1213e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark switch (priv->rev) { 1214e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark case TDA9989N2: dev_info(dev->dev, "found TDA9989 n2"); break; 1215e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark case TDA19989: dev_info(dev->dev, "found TDA19989"); break; 1216e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark case TDA19989N2: dev_info(dev->dev, "found TDA19989 n2"); break; 1217e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark case TDA19988: dev_info(dev->dev, "found TDA19988"); break; 1218e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark default: 1219e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark DBG("found unsupported device: %04x", priv->rev); 1220e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark goto fail; 1221e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark } 1222e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 1223e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark /* after reset, enable DDC: */ 12242f7f730a4f0fd3376dda9266203f29ceccd0a67fJean-Francois Moine reg_write(priv, REG_DDC_DISABLE, 0x00); 1225e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 1226e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark /* set clock on DDC channel: */ 12272f7f730a4f0fd3376dda9266203f29ceccd0a67fJean-Francois Moine reg_write(priv, REG_TX3, 39); 1228e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 1229e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark /* if necessary, disable multi-master: */ 1230e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark if (priv->rev == TDA19989) 12312f7f730a4f0fd3376dda9266203f29ceccd0a67fJean-Francois Moine reg_set(priv, REG_I2C_MASTER, I2C_MASTER_DIS_MM); 1232e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 12332f7f730a4f0fd3376dda9266203f29ceccd0a67fJean-Francois Moine cec_write(priv, REG_CEC_FRO_IM_CLK_CTRL, 1234e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark CEC_FRO_IM_CLK_CTRL_GHOST_DIS | CEC_FRO_IM_CLK_CTRL_IMCLK_SEL); 1235e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 1236e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark return 0; 1237e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 1238e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clarkfail: 1239e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark /* if encoder_init fails, the encoder slave is never registered, 1240e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark * so cleanup here: 1241e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark */ 1242e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark if (priv->cec) 1243e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark i2c_unregister_device(priv->cec); 1244e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark kfree(priv); 1245e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark encoder_slave->slave_priv = NULL; 1246e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark encoder_slave->slave_funcs = NULL; 1247e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark return -ENXIO; 1248e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark} 1249e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 1250e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clarkstatic struct i2c_device_id tda998x_ids[] = { 1251e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark { "tda998x", 0 }, 1252e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark { } 1253e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark}; 1254e7792ce2da5ded80861db787ace9b57ecf7bc96cRob ClarkMODULE_DEVICE_TABLE(i2c, tda998x_ids); 1255e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 1256e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clarkstatic struct drm_i2c_encoder_driver tda998x_driver = { 1257e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark .i2c_driver = { 1258e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark .probe = tda998x_probe, 1259e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark .remove = tda998x_remove, 1260e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark .driver = { 1261e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark .name = "tda998x", 1262e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark }, 1263e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark .id_table = tda998x_ids, 1264e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark }, 1265e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark .encoder_init = tda998x_encoder_init, 1266e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark}; 1267e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 1268e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark/* Module initialization */ 1269e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 1270e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clarkstatic int __init 1271e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clarktda998x_init(void) 1272e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark{ 1273e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark DBG(""); 1274e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark return drm_i2c_encoder_register(THIS_MODULE, &tda998x_driver); 1275e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark} 1276e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 1277e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clarkstatic void __exit 1278e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clarktda998x_exit(void) 1279e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark{ 1280e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark DBG(""); 1281e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark drm_i2c_encoder_unregister(&tda998x_driver); 1282e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark} 1283e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 1284e7792ce2da5ded80861db787ace9b57ecf7bc96cRob ClarkMODULE_AUTHOR("Rob Clark <robdclark@gmail.com"); 1285e7792ce2da5ded80861db787ace9b57ecf7bc96cRob ClarkMODULE_DESCRIPTION("NXP Semiconductors TDA998X HDMI Encoder"); 1286e7792ce2da5ded80861db787ace9b57ecf7bc96cRob ClarkMODULE_LICENSE("GPL"); 1287e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clark 1288e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clarkmodule_init(tda998x_init); 1289e7792ce2da5ded80861db787ace9b57ecf7bc96cRob Clarkmodule_exit(tda998x_exit); 1290