tda998x_drv.c revision 85c988bb26a3da46c04284bc43f93d732986547b
1/* 2 * Copyright (C) 2012 Texas Instruments 3 * Author: Rob Clark <robdclark@gmail.com> 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of the GNU General Public License version 2 as published by 7 * the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 * 14 * You should have received a copy of the GNU General Public License along with 15 * this program. If not, see <http://www.gnu.org/licenses/>. 16 */ 17 18 19 20#include <linux/hdmi.h> 21#include <linux/module.h> 22#include <linux/irq.h> 23#include <sound/asoundef.h> 24 25#include <drm/drmP.h> 26#include <drm/drm_crtc_helper.h> 27#include <drm/drm_encoder_slave.h> 28#include <drm/drm_edid.h> 29#include <drm/i2c/tda998x.h> 30 31#define DBG(fmt, ...) DRM_DEBUG(fmt"\n", ##__VA_ARGS__) 32 33struct tda998x_priv { 34 struct i2c_client *cec; 35 struct i2c_client *hdmi; 36 uint16_t rev; 37 uint8_t current_page; 38 int dpms; 39 bool is_hdmi_sink; 40 u8 vip_cntrl_0; 41 u8 vip_cntrl_1; 42 u8 vip_cntrl_2; 43 struct tda998x_encoder_params params; 44 45 wait_queue_head_t wq_edid; 46 volatile int wq_edid_wait; 47 struct drm_encoder *encoder; 48}; 49 50#define to_tda998x_priv(x) ((struct tda998x_priv *)to_encoder_slave(x)->slave_priv) 51 52/* The TDA9988 series of devices use a paged register scheme.. to simplify 53 * things we encode the page # in upper bits of the register #. To read/ 54 * write a given register, we need to make sure CURPAGE register is set 55 * appropriately. Which implies reads/writes are not atomic. Fun! 56 */ 57 58#define REG(page, addr) (((page) << 8) | (addr)) 59#define REG2ADDR(reg) ((reg) & 0xff) 60#define REG2PAGE(reg) (((reg) >> 8) & 0xff) 61 62#define REG_CURPAGE 0xff /* write */ 63 64 65/* Page 00h: General Control */ 66#define REG_VERSION_LSB REG(0x00, 0x00) /* read */ 67#define REG_MAIN_CNTRL0 REG(0x00, 0x01) /* read/write */ 68# define MAIN_CNTRL0_SR (1 << 0) 69# define MAIN_CNTRL0_DECS (1 << 1) 70# define MAIN_CNTRL0_DEHS (1 << 2) 71# define MAIN_CNTRL0_CECS (1 << 3) 72# define MAIN_CNTRL0_CEHS (1 << 4) 73# define MAIN_CNTRL0_SCALER (1 << 7) 74#define REG_VERSION_MSB REG(0x00, 0x02) /* read */ 75#define REG_SOFTRESET REG(0x00, 0x0a) /* write */ 76# define SOFTRESET_AUDIO (1 << 0) 77# define SOFTRESET_I2C_MASTER (1 << 1) 78#define REG_DDC_DISABLE REG(0x00, 0x0b) /* read/write */ 79#define REG_CCLK_ON REG(0x00, 0x0c) /* read/write */ 80#define REG_I2C_MASTER REG(0x00, 0x0d) /* read/write */ 81# define I2C_MASTER_DIS_MM (1 << 0) 82# define I2C_MASTER_DIS_FILT (1 << 1) 83# define I2C_MASTER_APP_STRT_LAT (1 << 2) 84#define REG_FEAT_POWERDOWN REG(0x00, 0x0e) /* read/write */ 85# define FEAT_POWERDOWN_SPDIF (1 << 3) 86#define REG_INT_FLAGS_0 REG(0x00, 0x0f) /* read/write */ 87#define REG_INT_FLAGS_1 REG(0x00, 0x10) /* read/write */ 88#define REG_INT_FLAGS_2 REG(0x00, 0x11) /* read/write */ 89# define INT_FLAGS_2_EDID_BLK_RD (1 << 1) 90#define REG_ENA_ACLK REG(0x00, 0x16) /* read/write */ 91#define REG_ENA_VP_0 REG(0x00, 0x18) /* read/write */ 92#define REG_ENA_VP_1 REG(0x00, 0x19) /* read/write */ 93#define REG_ENA_VP_2 REG(0x00, 0x1a) /* read/write */ 94#define REG_ENA_AP REG(0x00, 0x1e) /* read/write */ 95#define REG_VIP_CNTRL_0 REG(0x00, 0x20) /* write */ 96# define VIP_CNTRL_0_MIRR_A (1 << 7) 97# define VIP_CNTRL_0_SWAP_A(x) (((x) & 7) << 4) 98# define VIP_CNTRL_0_MIRR_B (1 << 3) 99# define VIP_CNTRL_0_SWAP_B(x) (((x) & 7) << 0) 100#define REG_VIP_CNTRL_1 REG(0x00, 0x21) /* write */ 101# define VIP_CNTRL_1_MIRR_C (1 << 7) 102# define VIP_CNTRL_1_SWAP_C(x) (((x) & 7) << 4) 103# define VIP_CNTRL_1_MIRR_D (1 << 3) 104# define VIP_CNTRL_1_SWAP_D(x) (((x) & 7) << 0) 105#define REG_VIP_CNTRL_2 REG(0x00, 0x22) /* write */ 106# define VIP_CNTRL_2_MIRR_E (1 << 7) 107# define VIP_CNTRL_2_SWAP_E(x) (((x) & 7) << 4) 108# define VIP_CNTRL_2_MIRR_F (1 << 3) 109# define VIP_CNTRL_2_SWAP_F(x) (((x) & 7) << 0) 110#define REG_VIP_CNTRL_3 REG(0x00, 0x23) /* write */ 111# define VIP_CNTRL_3_X_TGL (1 << 0) 112# define VIP_CNTRL_3_H_TGL (1 << 1) 113# define VIP_CNTRL_3_V_TGL (1 << 2) 114# define VIP_CNTRL_3_EMB (1 << 3) 115# define VIP_CNTRL_3_SYNC_DE (1 << 4) 116# define VIP_CNTRL_3_SYNC_HS (1 << 5) 117# define VIP_CNTRL_3_DE_INT (1 << 6) 118# define VIP_CNTRL_3_EDGE (1 << 7) 119#define REG_VIP_CNTRL_4 REG(0x00, 0x24) /* write */ 120# define VIP_CNTRL_4_BLC(x) (((x) & 3) << 0) 121# define VIP_CNTRL_4_BLANKIT(x) (((x) & 3) << 2) 122# define VIP_CNTRL_4_CCIR656 (1 << 4) 123# define VIP_CNTRL_4_656_ALT (1 << 5) 124# define VIP_CNTRL_4_TST_656 (1 << 6) 125# define VIP_CNTRL_4_TST_PAT (1 << 7) 126#define REG_VIP_CNTRL_5 REG(0x00, 0x25) /* write */ 127# define VIP_CNTRL_5_CKCASE (1 << 0) 128# define VIP_CNTRL_5_SP_CNT(x) (((x) & 3) << 1) 129#define REG_MUX_AP REG(0x00, 0x26) /* read/write */ 130# define MUX_AP_SELECT_I2S 0x64 131# define MUX_AP_SELECT_SPDIF 0x40 132#define REG_MUX_VP_VIP_OUT REG(0x00, 0x27) /* read/write */ 133#define REG_MAT_CONTRL REG(0x00, 0x80) /* write */ 134# define MAT_CONTRL_MAT_SC(x) (((x) & 3) << 0) 135# define MAT_CONTRL_MAT_BP (1 << 2) 136#define REG_VIDFORMAT REG(0x00, 0xa0) /* write */ 137#define REG_REFPIX_MSB REG(0x00, 0xa1) /* write */ 138#define REG_REFPIX_LSB REG(0x00, 0xa2) /* write */ 139#define REG_REFLINE_MSB REG(0x00, 0xa3) /* write */ 140#define REG_REFLINE_LSB REG(0x00, 0xa4) /* write */ 141#define REG_NPIX_MSB REG(0x00, 0xa5) /* write */ 142#define REG_NPIX_LSB REG(0x00, 0xa6) /* write */ 143#define REG_NLINE_MSB REG(0x00, 0xa7) /* write */ 144#define REG_NLINE_LSB REG(0x00, 0xa8) /* write */ 145#define REG_VS_LINE_STRT_1_MSB REG(0x00, 0xa9) /* write */ 146#define REG_VS_LINE_STRT_1_LSB REG(0x00, 0xaa) /* write */ 147#define REG_VS_PIX_STRT_1_MSB REG(0x00, 0xab) /* write */ 148#define REG_VS_PIX_STRT_1_LSB REG(0x00, 0xac) /* write */ 149#define REG_VS_LINE_END_1_MSB REG(0x00, 0xad) /* write */ 150#define REG_VS_LINE_END_1_LSB REG(0x00, 0xae) /* write */ 151#define REG_VS_PIX_END_1_MSB REG(0x00, 0xaf) /* write */ 152#define REG_VS_PIX_END_1_LSB REG(0x00, 0xb0) /* write */ 153#define REG_VS_LINE_STRT_2_MSB REG(0x00, 0xb1) /* write */ 154#define REG_VS_LINE_STRT_2_LSB REG(0x00, 0xb2) /* write */ 155#define REG_VS_PIX_STRT_2_MSB REG(0x00, 0xb3) /* write */ 156#define REG_VS_PIX_STRT_2_LSB REG(0x00, 0xb4) /* write */ 157#define REG_VS_LINE_END_2_MSB REG(0x00, 0xb5) /* write */ 158#define REG_VS_LINE_END_2_LSB REG(0x00, 0xb6) /* write */ 159#define REG_VS_PIX_END_2_MSB REG(0x00, 0xb7) /* write */ 160#define REG_VS_PIX_END_2_LSB REG(0x00, 0xb8) /* write */ 161#define REG_HS_PIX_START_MSB REG(0x00, 0xb9) /* write */ 162#define REG_HS_PIX_START_LSB REG(0x00, 0xba) /* write */ 163#define REG_HS_PIX_STOP_MSB REG(0x00, 0xbb) /* write */ 164#define REG_HS_PIX_STOP_LSB REG(0x00, 0xbc) /* write */ 165#define REG_VWIN_START_1_MSB REG(0x00, 0xbd) /* write */ 166#define REG_VWIN_START_1_LSB REG(0x00, 0xbe) /* write */ 167#define REG_VWIN_END_1_MSB REG(0x00, 0xbf) /* write */ 168#define REG_VWIN_END_1_LSB REG(0x00, 0xc0) /* write */ 169#define REG_VWIN_START_2_MSB REG(0x00, 0xc1) /* write */ 170#define REG_VWIN_START_2_LSB REG(0x00, 0xc2) /* write */ 171#define REG_VWIN_END_2_MSB REG(0x00, 0xc3) /* write */ 172#define REG_VWIN_END_2_LSB REG(0x00, 0xc4) /* write */ 173#define REG_DE_START_MSB REG(0x00, 0xc5) /* write */ 174#define REG_DE_START_LSB REG(0x00, 0xc6) /* write */ 175#define REG_DE_STOP_MSB REG(0x00, 0xc7) /* write */ 176#define REG_DE_STOP_LSB REG(0x00, 0xc8) /* write */ 177#define REG_TBG_CNTRL_0 REG(0x00, 0xca) /* write */ 178# define TBG_CNTRL_0_TOP_TGL (1 << 0) 179# define TBG_CNTRL_0_TOP_SEL (1 << 1) 180# define TBG_CNTRL_0_DE_EXT (1 << 2) 181# define TBG_CNTRL_0_TOP_EXT (1 << 3) 182# define TBG_CNTRL_0_FRAME_DIS (1 << 5) 183# define TBG_CNTRL_0_SYNC_MTHD (1 << 6) 184# define TBG_CNTRL_0_SYNC_ONCE (1 << 7) 185#define REG_TBG_CNTRL_1 REG(0x00, 0xcb) /* write */ 186# define TBG_CNTRL_1_H_TGL (1 << 0) 187# define TBG_CNTRL_1_V_TGL (1 << 1) 188# define TBG_CNTRL_1_TGL_EN (1 << 2) 189# define TBG_CNTRL_1_X_EXT (1 << 3) 190# define TBG_CNTRL_1_H_EXT (1 << 4) 191# define TBG_CNTRL_1_V_EXT (1 << 5) 192# define TBG_CNTRL_1_DWIN_DIS (1 << 6) 193#define REG_ENABLE_SPACE REG(0x00, 0xd6) /* write */ 194#define REG_HVF_CNTRL_0 REG(0x00, 0xe4) /* write */ 195# define HVF_CNTRL_0_SM (1 << 7) 196# define HVF_CNTRL_0_RWB (1 << 6) 197# define HVF_CNTRL_0_PREFIL(x) (((x) & 3) << 2) 198# define HVF_CNTRL_0_INTPOL(x) (((x) & 3) << 0) 199#define REG_HVF_CNTRL_1 REG(0x00, 0xe5) /* write */ 200# define HVF_CNTRL_1_FOR (1 << 0) 201# define HVF_CNTRL_1_YUVBLK (1 << 1) 202# define HVF_CNTRL_1_VQR(x) (((x) & 3) << 2) 203# define HVF_CNTRL_1_PAD(x) (((x) & 3) << 4) 204# define HVF_CNTRL_1_SEMI_PLANAR (1 << 6) 205#define REG_RPT_CNTRL REG(0x00, 0xf0) /* write */ 206#define REG_I2S_FORMAT REG(0x00, 0xfc) /* read/write */ 207# define I2S_FORMAT(x) (((x) & 3) << 0) 208#define REG_AIP_CLKSEL REG(0x00, 0xfd) /* write */ 209# define AIP_CLKSEL_AIP_SPDIF (0 << 3) 210# define AIP_CLKSEL_AIP_I2S (1 << 3) 211# define AIP_CLKSEL_FS_ACLK (0 << 0) 212# define AIP_CLKSEL_FS_MCLK (1 << 0) 213# define AIP_CLKSEL_FS_FS64SPDIF (2 << 0) 214 215/* Page 02h: PLL settings */ 216#define REG_PLL_SERIAL_1 REG(0x02, 0x00) /* read/write */ 217# define PLL_SERIAL_1_SRL_FDN (1 << 0) 218# define PLL_SERIAL_1_SRL_IZ(x) (((x) & 3) << 1) 219# define PLL_SERIAL_1_SRL_MAN_IZ (1 << 6) 220#define REG_PLL_SERIAL_2 REG(0x02, 0x01) /* read/write */ 221# define PLL_SERIAL_2_SRL_NOSC(x) ((x) << 0) 222# define PLL_SERIAL_2_SRL_PR(x) (((x) & 0xf) << 4) 223#define REG_PLL_SERIAL_3 REG(0x02, 0x02) /* read/write */ 224# define PLL_SERIAL_3_SRL_CCIR (1 << 0) 225# define PLL_SERIAL_3_SRL_DE (1 << 2) 226# define PLL_SERIAL_3_SRL_PXIN_SEL (1 << 4) 227#define REG_SERIALIZER REG(0x02, 0x03) /* read/write */ 228#define REG_BUFFER_OUT REG(0x02, 0x04) /* read/write */ 229#define REG_PLL_SCG1 REG(0x02, 0x05) /* read/write */ 230#define REG_PLL_SCG2 REG(0x02, 0x06) /* read/write */ 231#define REG_PLL_SCGN1 REG(0x02, 0x07) /* read/write */ 232#define REG_PLL_SCGN2 REG(0x02, 0x08) /* read/write */ 233#define REG_PLL_SCGR1 REG(0x02, 0x09) /* read/write */ 234#define REG_PLL_SCGR2 REG(0x02, 0x0a) /* read/write */ 235#define REG_AUDIO_DIV REG(0x02, 0x0e) /* read/write */ 236# define AUDIO_DIV_SERCLK_1 0 237# define AUDIO_DIV_SERCLK_2 1 238# define AUDIO_DIV_SERCLK_4 2 239# define AUDIO_DIV_SERCLK_8 3 240# define AUDIO_DIV_SERCLK_16 4 241# define AUDIO_DIV_SERCLK_32 5 242#define REG_SEL_CLK REG(0x02, 0x11) /* read/write */ 243# define SEL_CLK_SEL_CLK1 (1 << 0) 244# define SEL_CLK_SEL_VRF_CLK(x) (((x) & 3) << 1) 245# define SEL_CLK_ENA_SC_CLK (1 << 3) 246#define REG_ANA_GENERAL REG(0x02, 0x12) /* read/write */ 247 248 249/* Page 09h: EDID Control */ 250#define REG_EDID_DATA_0 REG(0x09, 0x00) /* read */ 251/* next 127 successive registers are the EDID block */ 252#define REG_EDID_CTRL REG(0x09, 0xfa) /* read/write */ 253#define REG_DDC_ADDR REG(0x09, 0xfb) /* read/write */ 254#define REG_DDC_OFFS REG(0x09, 0xfc) /* read/write */ 255#define REG_DDC_SEGM_ADDR REG(0x09, 0xfd) /* read/write */ 256#define REG_DDC_SEGM REG(0x09, 0xfe) /* read/write */ 257 258 259/* Page 10h: information frames and packets */ 260#define REG_IF1_HB0 REG(0x10, 0x20) /* read/write */ 261#define REG_IF2_HB0 REG(0x10, 0x40) /* read/write */ 262#define REG_IF3_HB0 REG(0x10, 0x60) /* read/write */ 263#define REG_IF4_HB0 REG(0x10, 0x80) /* read/write */ 264#define REG_IF5_HB0 REG(0x10, 0xa0) /* read/write */ 265 266 267/* Page 11h: audio settings and content info packets */ 268#define REG_AIP_CNTRL_0 REG(0x11, 0x00) /* read/write */ 269# define AIP_CNTRL_0_RST_FIFO (1 << 0) 270# define AIP_CNTRL_0_SWAP (1 << 1) 271# define AIP_CNTRL_0_LAYOUT (1 << 2) 272# define AIP_CNTRL_0_ACR_MAN (1 << 5) 273# define AIP_CNTRL_0_RST_CTS (1 << 6) 274#define REG_CA_I2S REG(0x11, 0x01) /* read/write */ 275# define CA_I2S_CA_I2S(x) (((x) & 31) << 0) 276# define CA_I2S_HBR_CHSTAT (1 << 6) 277#define REG_LATENCY_RD REG(0x11, 0x04) /* read/write */ 278#define REG_ACR_CTS_0 REG(0x11, 0x05) /* read/write */ 279#define REG_ACR_CTS_1 REG(0x11, 0x06) /* read/write */ 280#define REG_ACR_CTS_2 REG(0x11, 0x07) /* read/write */ 281#define REG_ACR_N_0 REG(0x11, 0x08) /* read/write */ 282#define REG_ACR_N_1 REG(0x11, 0x09) /* read/write */ 283#define REG_ACR_N_2 REG(0x11, 0x0a) /* read/write */ 284#define REG_CTS_N REG(0x11, 0x0c) /* read/write */ 285# define CTS_N_K(x) (((x) & 7) << 0) 286# define CTS_N_M(x) (((x) & 3) << 4) 287#define REG_ENC_CNTRL REG(0x11, 0x0d) /* read/write */ 288# define ENC_CNTRL_RST_ENC (1 << 0) 289# define ENC_CNTRL_RST_SEL (1 << 1) 290# define ENC_CNTRL_CTL_CODE(x) (((x) & 3) << 2) 291#define REG_DIP_FLAGS REG(0x11, 0x0e) /* read/write */ 292# define DIP_FLAGS_ACR (1 << 0) 293# define DIP_FLAGS_GC (1 << 1) 294#define REG_DIP_IF_FLAGS REG(0x11, 0x0f) /* read/write */ 295# define DIP_IF_FLAGS_IF1 (1 << 1) 296# define DIP_IF_FLAGS_IF2 (1 << 2) 297# define DIP_IF_FLAGS_IF3 (1 << 3) 298# define DIP_IF_FLAGS_IF4 (1 << 4) 299# define DIP_IF_FLAGS_IF5 (1 << 5) 300#define REG_CH_STAT_B(x) REG(0x11, 0x14 + (x)) /* read/write */ 301 302 303/* Page 12h: HDCP and OTP */ 304#define REG_TX3 REG(0x12, 0x9a) /* read/write */ 305#define REG_TX4 REG(0x12, 0x9b) /* read/write */ 306# define TX4_PD_RAM (1 << 1) 307#define REG_TX33 REG(0x12, 0xb8) /* read/write */ 308# define TX33_HDMI (1 << 1) 309 310 311/* Page 13h: Gamut related metadata packets */ 312 313 314 315/* CEC registers: (not paged) 316 */ 317#define REG_CEC_INTSTATUS 0xee /* read */ 318# define CEC_INTSTATUS_CEC (1 << 0) 319# define CEC_INTSTATUS_HDMI (1 << 1) 320#define REG_CEC_FRO_IM_CLK_CTRL 0xfb /* read/write */ 321# define CEC_FRO_IM_CLK_CTRL_GHOST_DIS (1 << 7) 322# define CEC_FRO_IM_CLK_CTRL_ENA_OTP (1 << 6) 323# define CEC_FRO_IM_CLK_CTRL_IMCLK_SEL (1 << 1) 324# define CEC_FRO_IM_CLK_CTRL_FRO_DIV (1 << 0) 325#define REG_CEC_RXSHPDINTENA 0xfc /* read/write */ 326#define REG_CEC_RXSHPDINT 0xfd /* read */ 327#define REG_CEC_RXSHPDLEV 0xfe /* read */ 328# define CEC_RXSHPDLEV_RXSENS (1 << 0) 329# define CEC_RXSHPDLEV_HPD (1 << 1) 330 331#define REG_CEC_ENAMODS 0xff /* read/write */ 332# define CEC_ENAMODS_DIS_FRO (1 << 6) 333# define CEC_ENAMODS_DIS_CCLK (1 << 5) 334# define CEC_ENAMODS_EN_RXSENS (1 << 2) 335# define CEC_ENAMODS_EN_HDMI (1 << 1) 336# define CEC_ENAMODS_EN_CEC (1 << 0) 337 338 339/* Device versions: */ 340#define TDA9989N2 0x0101 341#define TDA19989 0x0201 342#define TDA19989N2 0x0202 343#define TDA19988 0x0301 344 345static void 346cec_write(struct tda998x_priv *priv, uint16_t addr, uint8_t val) 347{ 348 struct i2c_client *client = priv->cec; 349 uint8_t buf[] = {addr, val}; 350 int ret; 351 352 ret = i2c_master_send(client, buf, sizeof(buf)); 353 if (ret < 0) 354 dev_err(&client->dev, "Error %d writing to cec:0x%x\n", ret, addr); 355} 356 357static uint8_t 358cec_read(struct tda998x_priv *priv, uint8_t addr) 359{ 360 struct i2c_client *client = priv->cec; 361 uint8_t val; 362 int ret; 363 364 ret = i2c_master_send(client, &addr, sizeof(addr)); 365 if (ret < 0) 366 goto fail; 367 368 ret = i2c_master_recv(client, &val, sizeof(val)); 369 if (ret < 0) 370 goto fail; 371 372 return val; 373 374fail: 375 dev_err(&client->dev, "Error %d reading from cec:0x%x\n", ret, addr); 376 return 0; 377} 378 379static int 380set_page(struct tda998x_priv *priv, uint16_t reg) 381{ 382 if (REG2PAGE(reg) != priv->current_page) { 383 struct i2c_client *client = priv->hdmi; 384 uint8_t buf[] = { 385 REG_CURPAGE, REG2PAGE(reg) 386 }; 387 int ret = i2c_master_send(client, buf, sizeof(buf)); 388 if (ret < 0) { 389 dev_err(&client->dev, "setpage %04x err %d\n", 390 reg, ret); 391 return ret; 392 } 393 394 priv->current_page = REG2PAGE(reg); 395 } 396 return 0; 397} 398 399static int 400reg_read_range(struct tda998x_priv *priv, uint16_t reg, char *buf, int cnt) 401{ 402 struct i2c_client *client = priv->hdmi; 403 uint8_t addr = REG2ADDR(reg); 404 int ret; 405 406 ret = set_page(priv, reg); 407 if (ret < 0) 408 return ret; 409 410 ret = i2c_master_send(client, &addr, sizeof(addr)); 411 if (ret < 0) 412 goto fail; 413 414 ret = i2c_master_recv(client, buf, cnt); 415 if (ret < 0) 416 goto fail; 417 418 return ret; 419 420fail: 421 dev_err(&client->dev, "Error %d reading from 0x%x\n", ret, reg); 422 return ret; 423} 424 425static void 426reg_write_range(struct tda998x_priv *priv, uint16_t reg, uint8_t *p, int cnt) 427{ 428 struct i2c_client *client = priv->hdmi; 429 uint8_t buf[cnt+1]; 430 int ret; 431 432 buf[0] = REG2ADDR(reg); 433 memcpy(&buf[1], p, cnt); 434 435 ret = set_page(priv, reg); 436 if (ret < 0) 437 return; 438 439 ret = i2c_master_send(client, buf, cnt + 1); 440 if (ret < 0) 441 dev_err(&client->dev, "Error %d writing to 0x%x\n", ret, reg); 442} 443 444static int 445reg_read(struct tda998x_priv *priv, uint16_t reg) 446{ 447 uint8_t val = 0; 448 int ret; 449 450 ret = reg_read_range(priv, reg, &val, sizeof(val)); 451 if (ret < 0) 452 return ret; 453 return val; 454} 455 456static void 457reg_write(struct tda998x_priv *priv, uint16_t reg, uint8_t val) 458{ 459 struct i2c_client *client = priv->hdmi; 460 uint8_t buf[] = {REG2ADDR(reg), val}; 461 int ret; 462 463 ret = set_page(priv, reg); 464 if (ret < 0) 465 return; 466 467 ret = i2c_master_send(client, buf, sizeof(buf)); 468 if (ret < 0) 469 dev_err(&client->dev, "Error %d writing to 0x%x\n", ret, reg); 470} 471 472static void 473reg_write16(struct tda998x_priv *priv, uint16_t reg, uint16_t val) 474{ 475 struct i2c_client *client = priv->hdmi; 476 uint8_t buf[] = {REG2ADDR(reg), val >> 8, val}; 477 int ret; 478 479 ret = set_page(priv, reg); 480 if (ret < 0) 481 return; 482 483 ret = i2c_master_send(client, buf, sizeof(buf)); 484 if (ret < 0) 485 dev_err(&client->dev, "Error %d writing to 0x%x\n", ret, reg); 486} 487 488static void 489reg_set(struct tda998x_priv *priv, uint16_t reg, uint8_t val) 490{ 491 int old_val; 492 493 old_val = reg_read(priv, reg); 494 if (old_val >= 0) 495 reg_write(priv, reg, old_val | val); 496} 497 498static void 499reg_clear(struct tda998x_priv *priv, uint16_t reg, uint8_t val) 500{ 501 int old_val; 502 503 old_val = reg_read(priv, reg); 504 if (old_val >= 0) 505 reg_write(priv, reg, old_val & ~val); 506} 507 508static void 509tda998x_reset(struct tda998x_priv *priv) 510{ 511 /* reset audio and i2c master: */ 512 reg_write(priv, REG_SOFTRESET, SOFTRESET_AUDIO | SOFTRESET_I2C_MASTER); 513 msleep(50); 514 reg_write(priv, REG_SOFTRESET, 0); 515 msleep(50); 516 517 /* reset transmitter: */ 518 reg_set(priv, REG_MAIN_CNTRL0, MAIN_CNTRL0_SR); 519 reg_clear(priv, REG_MAIN_CNTRL0, MAIN_CNTRL0_SR); 520 521 /* PLL registers common configuration */ 522 reg_write(priv, REG_PLL_SERIAL_1, 0x00); 523 reg_write(priv, REG_PLL_SERIAL_2, PLL_SERIAL_2_SRL_NOSC(1)); 524 reg_write(priv, REG_PLL_SERIAL_3, 0x00); 525 reg_write(priv, REG_SERIALIZER, 0x00); 526 reg_write(priv, REG_BUFFER_OUT, 0x00); 527 reg_write(priv, REG_PLL_SCG1, 0x00); 528 reg_write(priv, REG_AUDIO_DIV, AUDIO_DIV_SERCLK_8); 529 reg_write(priv, REG_SEL_CLK, SEL_CLK_SEL_CLK1 | SEL_CLK_ENA_SC_CLK); 530 reg_write(priv, REG_PLL_SCGN1, 0xfa); 531 reg_write(priv, REG_PLL_SCGN2, 0x00); 532 reg_write(priv, REG_PLL_SCGR1, 0x5b); 533 reg_write(priv, REG_PLL_SCGR2, 0x00); 534 reg_write(priv, REG_PLL_SCG2, 0x10); 535 536 /* Write the default value MUX register */ 537 reg_write(priv, REG_MUX_VP_VIP_OUT, 0x24); 538} 539 540/* 541 * only 2 interrupts may occur: screen plug/unplug and EDID read 542 */ 543static irqreturn_t tda998x_irq_thread(int irq, void *data) 544{ 545 struct tda998x_priv *priv = data; 546 u8 sta, cec, lvl, flag0, flag1, flag2; 547 548 if (!priv) 549 return IRQ_HANDLED; 550 sta = cec_read(priv, REG_CEC_INTSTATUS); 551 cec = cec_read(priv, REG_CEC_RXSHPDINT); 552 lvl = cec_read(priv, REG_CEC_RXSHPDLEV); 553 flag0 = reg_read(priv, REG_INT_FLAGS_0); 554 flag1 = reg_read(priv, REG_INT_FLAGS_1); 555 flag2 = reg_read(priv, REG_INT_FLAGS_2); 556 DRM_DEBUG_DRIVER( 557 "tda irq sta %02x cec %02x lvl %02x f0 %02x f1 %02x f2 %02x\n", 558 sta, cec, lvl, flag0, flag1, flag2); 559 if ((flag2 & INT_FLAGS_2_EDID_BLK_RD) && priv->wq_edid_wait) { 560 priv->wq_edid_wait = 0; 561 wake_up(&priv->wq_edid); 562 } else if (cec != 0) { /* HPD change */ 563 if (priv->encoder && priv->encoder->dev) 564 drm_helper_hpd_irq_event(priv->encoder->dev); 565 } 566 return IRQ_HANDLED; 567} 568 569static uint8_t tda998x_cksum(uint8_t *buf, size_t bytes) 570{ 571 uint8_t sum = 0; 572 573 while (bytes--) 574 sum += *buf++; 575 return (255 - sum) + 1; 576} 577 578#define HB(x) (x) 579#define PB(x) (HB(2) + 1 + (x)) 580 581static void 582tda998x_write_if(struct tda998x_priv *priv, uint8_t bit, uint16_t addr, 583 uint8_t *buf, size_t size) 584{ 585 buf[PB(0)] = tda998x_cksum(buf, size); 586 587 reg_clear(priv, REG_DIP_IF_FLAGS, bit); 588 reg_write_range(priv, addr, buf, size); 589 reg_set(priv, REG_DIP_IF_FLAGS, bit); 590} 591 592static void 593tda998x_write_aif(struct tda998x_priv *priv, struct tda998x_encoder_params *p) 594{ 595 u8 buf[PB(HDMI_AUDIO_INFOFRAME_SIZE) + 1]; 596 597 memset(buf, 0, sizeof(buf)); 598 buf[HB(0)] = HDMI_INFOFRAME_TYPE_AUDIO; 599 buf[HB(1)] = 0x01; 600 buf[HB(2)] = HDMI_AUDIO_INFOFRAME_SIZE; 601 buf[PB(1)] = p->audio_frame[1] & 0x07; /* CC */ 602 buf[PB(2)] = p->audio_frame[2] & 0x1c; /* SF */ 603 buf[PB(4)] = p->audio_frame[4]; 604 buf[PB(5)] = p->audio_frame[5] & 0xf8; /* DM_INH + LSV */ 605 606 tda998x_write_if(priv, DIP_IF_FLAGS_IF4, REG_IF4_HB0, buf, 607 sizeof(buf)); 608} 609 610static void 611tda998x_write_avi(struct tda998x_priv *priv, struct drm_display_mode *mode) 612{ 613 u8 buf[PB(HDMI_AVI_INFOFRAME_SIZE) + 1]; 614 615 memset(buf, 0, sizeof(buf)); 616 buf[HB(0)] = HDMI_INFOFRAME_TYPE_AVI; 617 buf[HB(1)] = 0x02; 618 buf[HB(2)] = HDMI_AVI_INFOFRAME_SIZE; 619 buf[PB(1)] = HDMI_SCAN_MODE_UNDERSCAN; 620 buf[PB(2)] = HDMI_ACTIVE_ASPECT_PICTURE; 621 buf[PB(3)] = HDMI_QUANTIZATION_RANGE_FULL << 2; 622 buf[PB(4)] = drm_match_cea_mode(mode); 623 624 tda998x_write_if(priv, DIP_IF_FLAGS_IF2, REG_IF2_HB0, buf, 625 sizeof(buf)); 626} 627 628static void tda998x_audio_mute(struct tda998x_priv *priv, bool on) 629{ 630 if (on) { 631 reg_set(priv, REG_SOFTRESET, SOFTRESET_AUDIO); 632 reg_clear(priv, REG_SOFTRESET, SOFTRESET_AUDIO); 633 reg_set(priv, REG_AIP_CNTRL_0, AIP_CNTRL_0_RST_FIFO); 634 } else { 635 reg_clear(priv, REG_AIP_CNTRL_0, AIP_CNTRL_0_RST_FIFO); 636 } 637} 638 639static void 640tda998x_configure_audio(struct tda998x_priv *priv, 641 struct drm_display_mode *mode, struct tda998x_encoder_params *p) 642{ 643 uint8_t buf[6], clksel_aip, clksel_fs, cts_n, adiv; 644 uint32_t n; 645 646 /* Enable audio ports */ 647 reg_write(priv, REG_ENA_AP, p->audio_cfg); 648 reg_write(priv, REG_ENA_ACLK, p->audio_clk_cfg); 649 650 /* Set audio input source */ 651 switch (p->audio_format) { 652 case AFMT_SPDIF: 653 reg_write(priv, REG_MUX_AP, MUX_AP_SELECT_SPDIF); 654 clksel_aip = AIP_CLKSEL_AIP_SPDIF; 655 clksel_fs = AIP_CLKSEL_FS_FS64SPDIF; 656 cts_n = CTS_N_M(3) | CTS_N_K(3); 657 break; 658 659 case AFMT_I2S: 660 reg_write(priv, REG_MUX_AP, MUX_AP_SELECT_I2S); 661 clksel_aip = AIP_CLKSEL_AIP_I2S; 662 clksel_fs = AIP_CLKSEL_FS_ACLK; 663 cts_n = CTS_N_M(3) | CTS_N_K(3); 664 break; 665 666 default: 667 BUG(); 668 return; 669 } 670 671 reg_write(priv, REG_AIP_CLKSEL, clksel_aip); 672 reg_clear(priv, REG_AIP_CNTRL_0, AIP_CNTRL_0_LAYOUT); 673 674 /* Enable automatic CTS generation */ 675 reg_clear(priv, REG_AIP_CNTRL_0, AIP_CNTRL_0_ACR_MAN); 676 reg_write(priv, REG_CTS_N, cts_n); 677 678 /* 679 * Audio input somehow depends on HDMI line rate which is 680 * related to pixclk. Testing showed that modes with pixclk 681 * >100MHz need a larger divider while <40MHz need the default. 682 * There is no detailed info in the datasheet, so we just 683 * assume 100MHz requires larger divider. 684 */ 685 if (mode->clock > 100000) 686 adiv = AUDIO_DIV_SERCLK_16; 687 else 688 adiv = AUDIO_DIV_SERCLK_8; 689 reg_write(priv, REG_AUDIO_DIV, adiv); 690 691 /* 692 * This is the approximate value of N, which happens to be 693 * the recommended values for non-coherent clocks. 694 */ 695 n = 128 * p->audio_sample_rate / 1000; 696 697 /* Write the CTS and N values */ 698 buf[0] = 0x44; 699 buf[1] = 0x42; 700 buf[2] = 0x01; 701 buf[3] = n; 702 buf[4] = n >> 8; 703 buf[5] = n >> 16; 704 reg_write_range(priv, REG_ACR_CTS_0, buf, 6); 705 706 /* Set CTS clock reference */ 707 reg_write(priv, REG_AIP_CLKSEL, clksel_aip | clksel_fs); 708 709 /* Reset CTS generator */ 710 reg_set(priv, REG_AIP_CNTRL_0, AIP_CNTRL_0_RST_CTS); 711 reg_clear(priv, REG_AIP_CNTRL_0, AIP_CNTRL_0_RST_CTS); 712 713 /* Write the channel status */ 714 buf[0] = IEC958_AES0_CON_NOT_COPYRIGHT; 715 buf[1] = 0x00; 716 buf[2] = IEC958_AES3_CON_FS_NOTID; 717 buf[3] = IEC958_AES4_CON_ORIGFS_NOTID | 718 IEC958_AES4_CON_MAX_WORDLEN_24; 719 reg_write_range(priv, REG_CH_STAT_B(0), buf, 4); 720 721 tda998x_audio_mute(priv, true); 722 msleep(20); 723 tda998x_audio_mute(priv, false); 724 725 /* Write the audio information packet */ 726 tda998x_write_aif(priv, p); 727} 728 729/* DRM encoder functions */ 730 731static void 732tda998x_encoder_set_config(struct drm_encoder *encoder, void *params) 733{ 734 struct tda998x_priv *priv = to_tda998x_priv(encoder); 735 struct tda998x_encoder_params *p = params; 736 737 priv->vip_cntrl_0 = VIP_CNTRL_0_SWAP_A(p->swap_a) | 738 (p->mirr_a ? VIP_CNTRL_0_MIRR_A : 0) | 739 VIP_CNTRL_0_SWAP_B(p->swap_b) | 740 (p->mirr_b ? VIP_CNTRL_0_MIRR_B : 0); 741 priv->vip_cntrl_1 = VIP_CNTRL_1_SWAP_C(p->swap_c) | 742 (p->mirr_c ? VIP_CNTRL_1_MIRR_C : 0) | 743 VIP_CNTRL_1_SWAP_D(p->swap_d) | 744 (p->mirr_d ? VIP_CNTRL_1_MIRR_D : 0); 745 priv->vip_cntrl_2 = VIP_CNTRL_2_SWAP_E(p->swap_e) | 746 (p->mirr_e ? VIP_CNTRL_2_MIRR_E : 0) | 747 VIP_CNTRL_2_SWAP_F(p->swap_f) | 748 (p->mirr_f ? VIP_CNTRL_2_MIRR_F : 0); 749 750 priv->params = *p; 751} 752 753static void 754tda998x_encoder_dpms(struct drm_encoder *encoder, int mode) 755{ 756 struct tda998x_priv *priv = to_tda998x_priv(encoder); 757 758 /* we only care about on or off: */ 759 if (mode != DRM_MODE_DPMS_ON) 760 mode = DRM_MODE_DPMS_OFF; 761 762 if (mode == priv->dpms) 763 return; 764 765 switch (mode) { 766 case DRM_MODE_DPMS_ON: 767 /* enable video ports, audio will be enabled later */ 768 reg_write(priv, REG_ENA_VP_0, 0xff); 769 reg_write(priv, REG_ENA_VP_1, 0xff); 770 reg_write(priv, REG_ENA_VP_2, 0xff); 771 /* set muxing after enabling ports: */ 772 reg_write(priv, REG_VIP_CNTRL_0, priv->vip_cntrl_0); 773 reg_write(priv, REG_VIP_CNTRL_1, priv->vip_cntrl_1); 774 reg_write(priv, REG_VIP_CNTRL_2, priv->vip_cntrl_2); 775 break; 776 case DRM_MODE_DPMS_OFF: 777 /* disable video ports */ 778 reg_write(priv, REG_ENA_VP_0, 0x00); 779 reg_write(priv, REG_ENA_VP_1, 0x00); 780 reg_write(priv, REG_ENA_VP_2, 0x00); 781 break; 782 } 783 784 priv->dpms = mode; 785} 786 787static void 788tda998x_encoder_save(struct drm_encoder *encoder) 789{ 790 DBG(""); 791} 792 793static void 794tda998x_encoder_restore(struct drm_encoder *encoder) 795{ 796 DBG(""); 797} 798 799static bool 800tda998x_encoder_mode_fixup(struct drm_encoder *encoder, 801 const struct drm_display_mode *mode, 802 struct drm_display_mode *adjusted_mode) 803{ 804 return true; 805} 806 807static int 808tda998x_encoder_mode_valid(struct drm_encoder *encoder, 809 struct drm_display_mode *mode) 810{ 811 return MODE_OK; 812} 813 814static void 815tda998x_encoder_mode_set(struct drm_encoder *encoder, 816 struct drm_display_mode *mode, 817 struct drm_display_mode *adjusted_mode) 818{ 819 struct tda998x_priv *priv = to_tda998x_priv(encoder); 820 uint16_t ref_pix, ref_line, n_pix, n_line; 821 uint16_t hs_pix_s, hs_pix_e; 822 uint16_t vs1_pix_s, vs1_pix_e, vs1_line_s, vs1_line_e; 823 uint16_t vs2_pix_s, vs2_pix_e, vs2_line_s, vs2_line_e; 824 uint16_t vwin1_line_s, vwin1_line_e; 825 uint16_t vwin2_line_s, vwin2_line_e; 826 uint16_t de_pix_s, de_pix_e; 827 uint8_t reg, div, rep; 828 829 /* 830 * Internally TDA998x is using ITU-R BT.656 style sync but 831 * we get VESA style sync. TDA998x is using a reference pixel 832 * relative to ITU to sync to the input frame and for output 833 * sync generation. Currently, we are using reference detection 834 * from HS/VS, i.e. REFPIX/REFLINE denote frame start sync point 835 * which is position of rising VS with coincident rising HS. 836 * 837 * Now there is some issues to take care of: 838 * - HDMI data islands require sync-before-active 839 * - TDA998x register values must be > 0 to be enabled 840 * - REFLINE needs an additional offset of +1 841 * - REFPIX needs an addtional offset of +1 for UYUV and +3 for RGB 842 * 843 * So we add +1 to all horizontal and vertical register values, 844 * plus an additional +3 for REFPIX as we are using RGB input only. 845 */ 846 n_pix = mode->htotal; 847 n_line = mode->vtotal; 848 849 hs_pix_e = mode->hsync_end - mode->hdisplay; 850 hs_pix_s = mode->hsync_start - mode->hdisplay; 851 de_pix_e = mode->htotal; 852 de_pix_s = mode->htotal - mode->hdisplay; 853 ref_pix = 3 + hs_pix_s; 854 855 /* 856 * Attached LCD controllers may generate broken sync. Allow 857 * those to adjust the position of the rising VS edge by adding 858 * HSKEW to ref_pix. 859 */ 860 if (adjusted_mode->flags & DRM_MODE_FLAG_HSKEW) 861 ref_pix += adjusted_mode->hskew; 862 863 if ((mode->flags & DRM_MODE_FLAG_INTERLACE) == 0) { 864 ref_line = 1 + mode->vsync_start - mode->vdisplay; 865 vwin1_line_s = mode->vtotal - mode->vdisplay - 1; 866 vwin1_line_e = vwin1_line_s + mode->vdisplay; 867 vs1_pix_s = vs1_pix_e = hs_pix_s; 868 vs1_line_s = mode->vsync_start - mode->vdisplay; 869 vs1_line_e = vs1_line_s + 870 mode->vsync_end - mode->vsync_start; 871 vwin2_line_s = vwin2_line_e = 0; 872 vs2_pix_s = vs2_pix_e = 0; 873 vs2_line_s = vs2_line_e = 0; 874 } else { 875 ref_line = 1 + (mode->vsync_start - mode->vdisplay)/2; 876 vwin1_line_s = (mode->vtotal - mode->vdisplay)/2; 877 vwin1_line_e = vwin1_line_s + mode->vdisplay/2; 878 vs1_pix_s = vs1_pix_e = hs_pix_s; 879 vs1_line_s = (mode->vsync_start - mode->vdisplay)/2; 880 vs1_line_e = vs1_line_s + 881 (mode->vsync_end - mode->vsync_start)/2; 882 vwin2_line_s = vwin1_line_s + mode->vtotal/2; 883 vwin2_line_e = vwin2_line_s + mode->vdisplay/2; 884 vs2_pix_s = vs2_pix_e = hs_pix_s + mode->htotal/2; 885 vs2_line_s = vs1_line_s + mode->vtotal/2 ; 886 vs2_line_e = vs2_line_s + 887 (mode->vsync_end - mode->vsync_start)/2; 888 } 889 890 div = 148500 / mode->clock; 891 if (div != 0) { 892 div--; 893 if (div > 3) 894 div = 3; 895 } 896 897 /* mute the audio FIFO: */ 898 reg_set(priv, REG_AIP_CNTRL_0, AIP_CNTRL_0_RST_FIFO); 899 900 /* set HDMI HDCP mode off: */ 901 reg_write(priv, REG_TBG_CNTRL_1, TBG_CNTRL_1_DWIN_DIS); 902 reg_clear(priv, REG_TX33, TX33_HDMI); 903 reg_write(priv, REG_ENC_CNTRL, ENC_CNTRL_CTL_CODE(0)); 904 905 /* no pre-filter or interpolator: */ 906 reg_write(priv, REG_HVF_CNTRL_0, HVF_CNTRL_0_PREFIL(0) | 907 HVF_CNTRL_0_INTPOL(0)); 908 reg_write(priv, REG_VIP_CNTRL_5, VIP_CNTRL_5_SP_CNT(0)); 909 reg_write(priv, REG_VIP_CNTRL_4, VIP_CNTRL_4_BLANKIT(0) | 910 VIP_CNTRL_4_BLC(0)); 911 reg_clear(priv, REG_PLL_SERIAL_3, PLL_SERIAL_3_SRL_CCIR); 912 913 reg_clear(priv, REG_PLL_SERIAL_1, PLL_SERIAL_1_SRL_MAN_IZ); 914 reg_clear(priv, REG_PLL_SERIAL_3, PLL_SERIAL_3_SRL_DE); 915 reg_write(priv, REG_SERIALIZER, 0); 916 reg_write(priv, REG_HVF_CNTRL_1, HVF_CNTRL_1_VQR(0)); 917 918 /* TODO enable pixel repeat for pixel rates less than 25Msamp/s */ 919 rep = 0; 920 reg_write(priv, REG_RPT_CNTRL, 0); 921 reg_write(priv, REG_SEL_CLK, SEL_CLK_SEL_VRF_CLK(0) | 922 SEL_CLK_SEL_CLK1 | SEL_CLK_ENA_SC_CLK); 923 924 reg_write(priv, REG_PLL_SERIAL_2, PLL_SERIAL_2_SRL_NOSC(div) | 925 PLL_SERIAL_2_SRL_PR(rep)); 926 927 /* set color matrix bypass flag: */ 928 reg_write(priv, REG_MAT_CONTRL, MAT_CONTRL_MAT_BP | 929 MAT_CONTRL_MAT_SC(1)); 930 931 /* set BIAS tmds value: */ 932 reg_write(priv, REG_ANA_GENERAL, 0x09); 933 934 reg_write(priv, REG_TBG_CNTRL_0, 0); 935 936 /* 937 * Sync on rising HSYNC/VSYNC 938 */ 939 reg = VIP_CNTRL_3_SYNC_HS; 940 941 /* 942 * TDA19988 requires high-active sync at input stage, 943 * so invert low-active sync provided by master encoder here 944 */ 945 if (mode->flags & DRM_MODE_FLAG_NHSYNC) 946 reg |= VIP_CNTRL_3_H_TGL; 947 if (mode->flags & DRM_MODE_FLAG_NVSYNC) 948 reg |= VIP_CNTRL_3_V_TGL; 949 reg_write(priv, REG_VIP_CNTRL_3, reg); 950 951 reg_write(priv, REG_VIDFORMAT, 0x00); 952 reg_write16(priv, REG_REFPIX_MSB, ref_pix); 953 reg_write16(priv, REG_REFLINE_MSB, ref_line); 954 reg_write16(priv, REG_NPIX_MSB, n_pix); 955 reg_write16(priv, REG_NLINE_MSB, n_line); 956 reg_write16(priv, REG_VS_LINE_STRT_1_MSB, vs1_line_s); 957 reg_write16(priv, REG_VS_PIX_STRT_1_MSB, vs1_pix_s); 958 reg_write16(priv, REG_VS_LINE_END_1_MSB, vs1_line_e); 959 reg_write16(priv, REG_VS_PIX_END_1_MSB, vs1_pix_e); 960 reg_write16(priv, REG_VS_LINE_STRT_2_MSB, vs2_line_s); 961 reg_write16(priv, REG_VS_PIX_STRT_2_MSB, vs2_pix_s); 962 reg_write16(priv, REG_VS_LINE_END_2_MSB, vs2_line_e); 963 reg_write16(priv, REG_VS_PIX_END_2_MSB, vs2_pix_e); 964 reg_write16(priv, REG_HS_PIX_START_MSB, hs_pix_s); 965 reg_write16(priv, REG_HS_PIX_STOP_MSB, hs_pix_e); 966 reg_write16(priv, REG_VWIN_START_1_MSB, vwin1_line_s); 967 reg_write16(priv, REG_VWIN_END_1_MSB, vwin1_line_e); 968 reg_write16(priv, REG_VWIN_START_2_MSB, vwin2_line_s); 969 reg_write16(priv, REG_VWIN_END_2_MSB, vwin2_line_e); 970 reg_write16(priv, REG_DE_START_MSB, de_pix_s); 971 reg_write16(priv, REG_DE_STOP_MSB, de_pix_e); 972 973 if (priv->rev == TDA19988) { 974 /* let incoming pixels fill the active space (if any) */ 975 reg_write(priv, REG_ENABLE_SPACE, 0x00); 976 } 977 978 /* 979 * Always generate sync polarity relative to input sync and 980 * revert input stage toggled sync at output stage 981 */ 982 reg = TBG_CNTRL_1_DWIN_DIS | TBG_CNTRL_1_TGL_EN; 983 if (mode->flags & DRM_MODE_FLAG_NHSYNC) 984 reg |= TBG_CNTRL_1_H_TGL; 985 if (mode->flags & DRM_MODE_FLAG_NVSYNC) 986 reg |= TBG_CNTRL_1_V_TGL; 987 reg_write(priv, REG_TBG_CNTRL_1, reg); 988 989 /* must be last register set: */ 990 reg_write(priv, REG_TBG_CNTRL_0, 0); 991 992 /* Only setup the info frames if the sink is HDMI */ 993 if (priv->is_hdmi_sink) { 994 /* We need to turn HDMI HDCP stuff on to get audio through */ 995 reg &= ~TBG_CNTRL_1_DWIN_DIS; 996 reg_write(priv, REG_TBG_CNTRL_1, reg); 997 reg_write(priv, REG_ENC_CNTRL, ENC_CNTRL_CTL_CODE(1)); 998 reg_set(priv, REG_TX33, TX33_HDMI); 999 1000 tda998x_write_avi(priv, adjusted_mode); 1001 1002 if (priv->params.audio_cfg) 1003 tda998x_configure_audio(priv, adjusted_mode, 1004 &priv->params); 1005 } 1006} 1007 1008static enum drm_connector_status 1009tda998x_encoder_detect(struct drm_encoder *encoder, 1010 struct drm_connector *connector) 1011{ 1012 struct tda998x_priv *priv = to_tda998x_priv(encoder); 1013 uint8_t val = cec_read(priv, REG_CEC_RXSHPDLEV); 1014 1015 return (val & CEC_RXSHPDLEV_HPD) ? connector_status_connected : 1016 connector_status_disconnected; 1017} 1018 1019static int 1020read_edid_block(struct drm_encoder *encoder, uint8_t *buf, int blk) 1021{ 1022 struct tda998x_priv *priv = to_tda998x_priv(encoder); 1023 uint8_t offset, segptr; 1024 int ret, i; 1025 1026 offset = (blk & 1) ? 128 : 0; 1027 segptr = blk / 2; 1028 1029 reg_write(priv, REG_DDC_ADDR, 0xa0); 1030 reg_write(priv, REG_DDC_OFFS, offset); 1031 reg_write(priv, REG_DDC_SEGM_ADDR, 0x60); 1032 reg_write(priv, REG_DDC_SEGM, segptr); 1033 1034 /* enable reading EDID: */ 1035 priv->wq_edid_wait = 1; 1036 reg_write(priv, REG_EDID_CTRL, 0x1); 1037 1038 /* flag must be cleared by sw: */ 1039 reg_write(priv, REG_EDID_CTRL, 0x0); 1040 1041 /* wait for block read to complete: */ 1042 if (priv->hdmi->irq) { 1043 i = wait_event_timeout(priv->wq_edid, 1044 !priv->wq_edid_wait, 1045 msecs_to_jiffies(100)); 1046 if (i < 0) { 1047 dev_err(encoder->dev->dev, "read edid wait err %d\n", i); 1048 return i; 1049 } 1050 } else { 1051 for (i = 10; i > 0; i--) { 1052 msleep(10); 1053 ret = reg_read(priv, REG_INT_FLAGS_2); 1054 if (ret < 0) 1055 return ret; 1056 if (ret & INT_FLAGS_2_EDID_BLK_RD) 1057 break; 1058 } 1059 } 1060 1061 if (i == 0) { 1062 dev_err(encoder->dev->dev, "read edid timeout\n"); 1063 return -ETIMEDOUT; 1064 } 1065 1066 ret = reg_read_range(priv, REG_EDID_DATA_0, buf, EDID_LENGTH); 1067 if (ret != EDID_LENGTH) { 1068 dev_err(encoder->dev->dev, "failed to read edid block %d: %d\n", 1069 blk, ret); 1070 return ret; 1071 } 1072 1073 return 0; 1074} 1075 1076static uint8_t * 1077do_get_edid(struct drm_encoder *encoder) 1078{ 1079 struct tda998x_priv *priv = to_tda998x_priv(encoder); 1080 int j, valid_extensions = 0; 1081 uint8_t *block, *new; 1082 bool print_bad_edid = drm_debug & DRM_UT_KMS; 1083 1084 if ((block = kmalloc(EDID_LENGTH, GFP_KERNEL)) == NULL) 1085 return NULL; 1086 1087 if (priv->rev == TDA19988) 1088 reg_clear(priv, REG_TX4, TX4_PD_RAM); 1089 1090 /* base block fetch */ 1091 if (read_edid_block(encoder, block, 0)) 1092 goto fail; 1093 1094 if (!drm_edid_block_valid(block, 0, print_bad_edid)) 1095 goto fail; 1096 1097 /* if there's no extensions, we're done */ 1098 if (block[0x7e] == 0) 1099 goto done; 1100 1101 new = krealloc(block, (block[0x7e] + 1) * EDID_LENGTH, GFP_KERNEL); 1102 if (!new) 1103 goto fail; 1104 block = new; 1105 1106 for (j = 1; j <= block[0x7e]; j++) { 1107 uint8_t *ext_block = block + (valid_extensions + 1) * EDID_LENGTH; 1108 if (read_edid_block(encoder, ext_block, j)) 1109 goto fail; 1110 1111 if (!drm_edid_block_valid(ext_block, j, print_bad_edid)) 1112 goto fail; 1113 1114 valid_extensions++; 1115 } 1116 1117 if (valid_extensions != block[0x7e]) { 1118 block[EDID_LENGTH-1] += block[0x7e] - valid_extensions; 1119 block[0x7e] = valid_extensions; 1120 new = krealloc(block, (valid_extensions + 1) * EDID_LENGTH, GFP_KERNEL); 1121 if (!new) 1122 goto fail; 1123 block = new; 1124 } 1125 1126done: 1127 if (priv->rev == TDA19988) 1128 reg_set(priv, REG_TX4, TX4_PD_RAM); 1129 1130 return block; 1131 1132fail: 1133 if (priv->rev == TDA19988) 1134 reg_set(priv, REG_TX4, TX4_PD_RAM); 1135 dev_warn(encoder->dev->dev, "failed to read EDID\n"); 1136 kfree(block); 1137 return NULL; 1138} 1139 1140static int 1141tda998x_encoder_get_modes(struct drm_encoder *encoder, 1142 struct drm_connector *connector) 1143{ 1144 struct tda998x_priv *priv = to_tda998x_priv(encoder); 1145 struct edid *edid = (struct edid *)do_get_edid(encoder); 1146 int n = 0; 1147 1148 if (edid) { 1149 drm_mode_connector_update_edid_property(connector, edid); 1150 n = drm_add_edid_modes(connector, edid); 1151 priv->is_hdmi_sink = drm_detect_hdmi_monitor(edid); 1152 kfree(edid); 1153 } 1154 1155 return n; 1156} 1157 1158static int 1159tda998x_encoder_create_resources(struct drm_encoder *encoder, 1160 struct drm_connector *connector) 1161{ 1162 struct tda998x_priv *priv = to_tda998x_priv(encoder); 1163 1164 if (priv->hdmi->irq) 1165 connector->polled = DRM_CONNECTOR_POLL_HPD; 1166 else 1167 connector->polled = DRM_CONNECTOR_POLL_CONNECT | 1168 DRM_CONNECTOR_POLL_DISCONNECT; 1169 return 0; 1170} 1171 1172static int 1173tda998x_encoder_set_property(struct drm_encoder *encoder, 1174 struct drm_connector *connector, 1175 struct drm_property *property, 1176 uint64_t val) 1177{ 1178 DBG(""); 1179 return 0; 1180} 1181 1182static void 1183tda998x_encoder_destroy(struct drm_encoder *encoder) 1184{ 1185 struct tda998x_priv *priv = to_tda998x_priv(encoder); 1186 drm_i2c_encoder_destroy(encoder); 1187 1188 /* disable all IRQs and free the IRQ handler */ 1189 cec_write(priv, REG_CEC_RXSHPDINTENA, 0); 1190 reg_clear(priv, REG_INT_FLAGS_2, INT_FLAGS_2_EDID_BLK_RD); 1191 if (priv->hdmi->irq) 1192 free_irq(priv->hdmi->irq, priv); 1193 1194 if (priv->cec) 1195 i2c_unregister_device(priv->cec); 1196 kfree(priv); 1197} 1198 1199static struct drm_encoder_slave_funcs tda998x_encoder_funcs = { 1200 .set_config = tda998x_encoder_set_config, 1201 .destroy = tda998x_encoder_destroy, 1202 .dpms = tda998x_encoder_dpms, 1203 .save = tda998x_encoder_save, 1204 .restore = tda998x_encoder_restore, 1205 .mode_fixup = tda998x_encoder_mode_fixup, 1206 .mode_valid = tda998x_encoder_mode_valid, 1207 .mode_set = tda998x_encoder_mode_set, 1208 .detect = tda998x_encoder_detect, 1209 .get_modes = tda998x_encoder_get_modes, 1210 .create_resources = tda998x_encoder_create_resources, 1211 .set_property = tda998x_encoder_set_property, 1212}; 1213 1214/* I2C driver functions */ 1215 1216static int 1217tda998x_probe(struct i2c_client *client, const struct i2c_device_id *id) 1218{ 1219 return 0; 1220} 1221 1222static int 1223tda998x_remove(struct i2c_client *client) 1224{ 1225 return 0; 1226} 1227 1228static int 1229tda998x_encoder_init(struct i2c_client *client, 1230 struct drm_device *dev, 1231 struct drm_encoder_slave *encoder_slave) 1232{ 1233 struct tda998x_priv *priv; 1234 struct device_node *np = client->dev.of_node; 1235 u32 video; 1236 int rev_lo, rev_hi, ret; 1237 1238 priv = kzalloc(sizeof(*priv), GFP_KERNEL); 1239 if (!priv) 1240 return -ENOMEM; 1241 1242 priv->vip_cntrl_0 = VIP_CNTRL_0_SWAP_A(2) | VIP_CNTRL_0_SWAP_B(3); 1243 priv->vip_cntrl_1 = VIP_CNTRL_1_SWAP_C(0) | VIP_CNTRL_1_SWAP_D(1); 1244 priv->vip_cntrl_2 = VIP_CNTRL_2_SWAP_E(4) | VIP_CNTRL_2_SWAP_F(5); 1245 1246 priv->current_page = 0xff; 1247 priv->hdmi = client; 1248 priv->cec = i2c_new_dummy(client->adapter, 0x34); 1249 if (!priv->cec) { 1250 kfree(priv); 1251 return -ENODEV; 1252 } 1253 1254 priv->encoder = &encoder_slave->base; 1255 priv->dpms = DRM_MODE_DPMS_OFF; 1256 1257 encoder_slave->slave_priv = priv; 1258 encoder_slave->slave_funcs = &tda998x_encoder_funcs; 1259 1260 /* wake up the device: */ 1261 cec_write(priv, REG_CEC_ENAMODS, 1262 CEC_ENAMODS_EN_RXSENS | CEC_ENAMODS_EN_HDMI); 1263 1264 tda998x_reset(priv); 1265 1266 /* read version: */ 1267 rev_lo = reg_read(priv, REG_VERSION_LSB); 1268 rev_hi = reg_read(priv, REG_VERSION_MSB); 1269 if (rev_lo < 0 || rev_hi < 0) { 1270 ret = rev_lo < 0 ? rev_lo : rev_hi; 1271 goto fail; 1272 } 1273 1274 priv->rev = rev_lo | rev_hi << 8; 1275 1276 /* mask off feature bits: */ 1277 priv->rev &= ~0x30; /* not-hdcp and not-scalar bit */ 1278 1279 switch (priv->rev) { 1280 case TDA9989N2: 1281 dev_info(&client->dev, "found TDA9989 n2"); 1282 break; 1283 case TDA19989: 1284 dev_info(&client->dev, "found TDA19989"); 1285 break; 1286 case TDA19989N2: 1287 dev_info(&client->dev, "found TDA19989 n2"); 1288 break; 1289 case TDA19988: 1290 dev_info(&client->dev, "found TDA19988"); 1291 break; 1292 default: 1293 dev_err(&client->dev, "found unsupported device: %04x\n", 1294 priv->rev); 1295 goto fail; 1296 } 1297 1298 /* after reset, enable DDC: */ 1299 reg_write(priv, REG_DDC_DISABLE, 0x00); 1300 1301 /* set clock on DDC channel: */ 1302 reg_write(priv, REG_TX3, 39); 1303 1304 /* if necessary, disable multi-master: */ 1305 if (priv->rev == TDA19989) 1306 reg_set(priv, REG_I2C_MASTER, I2C_MASTER_DIS_MM); 1307 1308 cec_write(priv, REG_CEC_FRO_IM_CLK_CTRL, 1309 CEC_FRO_IM_CLK_CTRL_GHOST_DIS | CEC_FRO_IM_CLK_CTRL_IMCLK_SEL); 1310 1311 /* initialize the optional IRQ */ 1312 if (client->irq) { 1313 int irqf_trigger; 1314 1315 /* init read EDID waitqueue */ 1316 init_waitqueue_head(&priv->wq_edid); 1317 1318 /* clear pending interrupts */ 1319 reg_read(priv, REG_INT_FLAGS_0); 1320 reg_read(priv, REG_INT_FLAGS_1); 1321 reg_read(priv, REG_INT_FLAGS_2); 1322 1323 irqf_trigger = 1324 irqd_get_trigger_type(irq_get_irq_data(client->irq)); 1325 ret = request_threaded_irq(client->irq, NULL, 1326 tda998x_irq_thread, 1327 irqf_trigger | IRQF_ONESHOT, 1328 "tda998x", priv); 1329 if (ret) { 1330 dev_err(&client->dev, 1331 "failed to request IRQ#%u: %d\n", 1332 client->irq, ret); 1333 goto fail; 1334 } 1335 1336 /* enable HPD irq */ 1337 cec_write(priv, REG_CEC_RXSHPDINTENA, CEC_RXSHPDLEV_HPD); 1338 } 1339 1340 /* enable EDID read irq: */ 1341 reg_set(priv, REG_INT_FLAGS_2, INT_FLAGS_2_EDID_BLK_RD); 1342 1343 if (!np) 1344 return 0; /* non-DT */ 1345 1346 /* get the optional video properties */ 1347 ret = of_property_read_u32(np, "video-ports", &video); 1348 if (ret == 0) { 1349 priv->vip_cntrl_0 = video >> 16; 1350 priv->vip_cntrl_1 = video >> 8; 1351 priv->vip_cntrl_2 = video; 1352 } 1353 1354 return 0; 1355 1356fail: 1357 /* if encoder_init fails, the encoder slave is never registered, 1358 * so cleanup here: 1359 */ 1360 if (priv->cec) 1361 i2c_unregister_device(priv->cec); 1362 kfree(priv); 1363 encoder_slave->slave_priv = NULL; 1364 encoder_slave->slave_funcs = NULL; 1365 return -ENXIO; 1366} 1367 1368#ifdef CONFIG_OF 1369static const struct of_device_id tda998x_dt_ids[] = { 1370 { .compatible = "nxp,tda998x", }, 1371 { } 1372}; 1373MODULE_DEVICE_TABLE(of, tda998x_dt_ids); 1374#endif 1375 1376static struct i2c_device_id tda998x_ids[] = { 1377 { "tda998x", 0 }, 1378 { } 1379}; 1380MODULE_DEVICE_TABLE(i2c, tda998x_ids); 1381 1382static struct drm_i2c_encoder_driver tda998x_driver = { 1383 .i2c_driver = { 1384 .probe = tda998x_probe, 1385 .remove = tda998x_remove, 1386 .driver = { 1387 .name = "tda998x", 1388 .of_match_table = of_match_ptr(tda998x_dt_ids), 1389 }, 1390 .id_table = tda998x_ids, 1391 }, 1392 .encoder_init = tda998x_encoder_init, 1393}; 1394 1395/* Module initialization */ 1396 1397static int __init 1398tda998x_init(void) 1399{ 1400 DBG(""); 1401 return drm_i2c_encoder_register(THIS_MODULE, &tda998x_driver); 1402} 1403 1404static void __exit 1405tda998x_exit(void) 1406{ 1407 DBG(""); 1408 drm_i2c_encoder_unregister(&tda998x_driver); 1409} 1410 1411MODULE_AUTHOR("Rob Clark <robdclark@gmail.com"); 1412MODULE_DESCRIPTION("NXP Semiconductors TDA998X HDMI Encoder"); 1413MODULE_LICENSE("GPL"); 1414 1415module_init(tda998x_init); 1416module_exit(tda998x_exit); 1417