tda998x_drv.c revision bdf6345b3262d0ddbc6405fbc0fedd2941bec08e
1/* 2 * Copyright (C) 2012 Texas Instruments 3 * Author: Rob Clark <robdclark@gmail.com> 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of the GNU General Public License version 2 as published by 7 * the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 * 14 * You should have received a copy of the GNU General Public License along with 15 * this program. If not, see <http://www.gnu.org/licenses/>. 16 */ 17 18 19 20#include <linux/hdmi.h> 21#include <linux/module.h> 22 23#include <drm/drmP.h> 24#include <drm/drm_crtc_helper.h> 25#include <drm/drm_encoder_slave.h> 26#include <drm/drm_edid.h> 27#include <drm/i2c/tda998x.h> 28 29#define DBG(fmt, ...) DRM_DEBUG(fmt"\n", ##__VA_ARGS__) 30 31struct tda998x_priv { 32 struct i2c_client *cec; 33 uint16_t rev; 34 uint8_t current_page; 35 int dpms; 36 bool is_hdmi_sink; 37 u8 vip_cntrl_0; 38 u8 vip_cntrl_1; 39 u8 vip_cntrl_2; 40 struct tda998x_encoder_params params; 41}; 42 43#define to_tda998x_priv(x) ((struct tda998x_priv *)to_encoder_slave(x)->slave_priv) 44 45/* The TDA9988 series of devices use a paged register scheme.. to simplify 46 * things we encode the page # in upper bits of the register #. To read/ 47 * write a given register, we need to make sure CURPAGE register is set 48 * appropriately. Which implies reads/writes are not atomic. Fun! 49 */ 50 51#define REG(page, addr) (((page) << 8) | (addr)) 52#define REG2ADDR(reg) ((reg) & 0xff) 53#define REG2PAGE(reg) (((reg) >> 8) & 0xff) 54 55#define REG_CURPAGE 0xff /* write */ 56 57 58/* Page 00h: General Control */ 59#define REG_VERSION_LSB REG(0x00, 0x00) /* read */ 60#define REG_MAIN_CNTRL0 REG(0x00, 0x01) /* read/write */ 61# define MAIN_CNTRL0_SR (1 << 0) 62# define MAIN_CNTRL0_DECS (1 << 1) 63# define MAIN_CNTRL0_DEHS (1 << 2) 64# define MAIN_CNTRL0_CECS (1 << 3) 65# define MAIN_CNTRL0_CEHS (1 << 4) 66# define MAIN_CNTRL0_SCALER (1 << 7) 67#define REG_VERSION_MSB REG(0x00, 0x02) /* read */ 68#define REG_SOFTRESET REG(0x00, 0x0a) /* write */ 69# define SOFTRESET_AUDIO (1 << 0) 70# define SOFTRESET_I2C_MASTER (1 << 1) 71#define REG_DDC_DISABLE REG(0x00, 0x0b) /* read/write */ 72#define REG_CCLK_ON REG(0x00, 0x0c) /* read/write */ 73#define REG_I2C_MASTER REG(0x00, 0x0d) /* read/write */ 74# define I2C_MASTER_DIS_MM (1 << 0) 75# define I2C_MASTER_DIS_FILT (1 << 1) 76# define I2C_MASTER_APP_STRT_LAT (1 << 2) 77#define REG_FEAT_POWERDOWN REG(0x00, 0x0e) /* read/write */ 78# define FEAT_POWERDOWN_SPDIF (1 << 3) 79#define REG_INT_FLAGS_0 REG(0x00, 0x0f) /* read/write */ 80#define REG_INT_FLAGS_1 REG(0x00, 0x10) /* read/write */ 81#define REG_INT_FLAGS_2 REG(0x00, 0x11) /* read/write */ 82# define INT_FLAGS_2_EDID_BLK_RD (1 << 1) 83#define REG_ENA_ACLK REG(0x00, 0x16) /* read/write */ 84#define REG_ENA_VP_0 REG(0x00, 0x18) /* read/write */ 85#define REG_ENA_VP_1 REG(0x00, 0x19) /* read/write */ 86#define REG_ENA_VP_2 REG(0x00, 0x1a) /* read/write */ 87#define REG_ENA_AP REG(0x00, 0x1e) /* read/write */ 88#define REG_VIP_CNTRL_0 REG(0x00, 0x20) /* write */ 89# define VIP_CNTRL_0_MIRR_A (1 << 7) 90# define VIP_CNTRL_0_SWAP_A(x) (((x) & 7) << 4) 91# define VIP_CNTRL_0_MIRR_B (1 << 3) 92# define VIP_CNTRL_0_SWAP_B(x) (((x) & 7) << 0) 93#define REG_VIP_CNTRL_1 REG(0x00, 0x21) /* write */ 94# define VIP_CNTRL_1_MIRR_C (1 << 7) 95# define VIP_CNTRL_1_SWAP_C(x) (((x) & 7) << 4) 96# define VIP_CNTRL_1_MIRR_D (1 << 3) 97# define VIP_CNTRL_1_SWAP_D(x) (((x) & 7) << 0) 98#define REG_VIP_CNTRL_2 REG(0x00, 0x22) /* write */ 99# define VIP_CNTRL_2_MIRR_E (1 << 7) 100# define VIP_CNTRL_2_SWAP_E(x) (((x) & 7) << 4) 101# define VIP_CNTRL_2_MIRR_F (1 << 3) 102# define VIP_CNTRL_2_SWAP_F(x) (((x) & 7) << 0) 103#define REG_VIP_CNTRL_3 REG(0x00, 0x23) /* write */ 104# define VIP_CNTRL_3_X_TGL (1 << 0) 105# define VIP_CNTRL_3_H_TGL (1 << 1) 106# define VIP_CNTRL_3_V_TGL (1 << 2) 107# define VIP_CNTRL_3_EMB (1 << 3) 108# define VIP_CNTRL_3_SYNC_DE (1 << 4) 109# define VIP_CNTRL_3_SYNC_HS (1 << 5) 110# define VIP_CNTRL_3_DE_INT (1 << 6) 111# define VIP_CNTRL_3_EDGE (1 << 7) 112#define REG_VIP_CNTRL_4 REG(0x00, 0x24) /* write */ 113# define VIP_CNTRL_4_BLC(x) (((x) & 3) << 0) 114# define VIP_CNTRL_4_BLANKIT(x) (((x) & 3) << 2) 115# define VIP_CNTRL_4_CCIR656 (1 << 4) 116# define VIP_CNTRL_4_656_ALT (1 << 5) 117# define VIP_CNTRL_4_TST_656 (1 << 6) 118# define VIP_CNTRL_4_TST_PAT (1 << 7) 119#define REG_VIP_CNTRL_5 REG(0x00, 0x25) /* write */ 120# define VIP_CNTRL_5_CKCASE (1 << 0) 121# define VIP_CNTRL_5_SP_CNT(x) (((x) & 3) << 1) 122#define REG_MUX_AP REG(0x00, 0x26) /* read/write */ 123#define REG_MUX_VP_VIP_OUT REG(0x00, 0x27) /* read/write */ 124#define REG_MAT_CONTRL REG(0x00, 0x80) /* write */ 125# define MAT_CONTRL_MAT_SC(x) (((x) & 3) << 0) 126# define MAT_CONTRL_MAT_BP (1 << 2) 127#define REG_VIDFORMAT REG(0x00, 0xa0) /* write */ 128#define REG_REFPIX_MSB REG(0x00, 0xa1) /* write */ 129#define REG_REFPIX_LSB REG(0x00, 0xa2) /* write */ 130#define REG_REFLINE_MSB REG(0x00, 0xa3) /* write */ 131#define REG_REFLINE_LSB REG(0x00, 0xa4) /* write */ 132#define REG_NPIX_MSB REG(0x00, 0xa5) /* write */ 133#define REG_NPIX_LSB REG(0x00, 0xa6) /* write */ 134#define REG_NLINE_MSB REG(0x00, 0xa7) /* write */ 135#define REG_NLINE_LSB REG(0x00, 0xa8) /* write */ 136#define REG_VS_LINE_STRT_1_MSB REG(0x00, 0xa9) /* write */ 137#define REG_VS_LINE_STRT_1_LSB REG(0x00, 0xaa) /* write */ 138#define REG_VS_PIX_STRT_1_MSB REG(0x00, 0xab) /* write */ 139#define REG_VS_PIX_STRT_1_LSB REG(0x00, 0xac) /* write */ 140#define REG_VS_LINE_END_1_MSB REG(0x00, 0xad) /* write */ 141#define REG_VS_LINE_END_1_LSB REG(0x00, 0xae) /* write */ 142#define REG_VS_PIX_END_1_MSB REG(0x00, 0xaf) /* write */ 143#define REG_VS_PIX_END_1_LSB REG(0x00, 0xb0) /* write */ 144#define REG_VS_LINE_STRT_2_MSB REG(0x00, 0xb1) /* write */ 145#define REG_VS_LINE_STRT_2_LSB REG(0x00, 0xb2) /* write */ 146#define REG_VS_PIX_STRT_2_MSB REG(0x00, 0xb3) /* write */ 147#define REG_VS_PIX_STRT_2_LSB REG(0x00, 0xb4) /* write */ 148#define REG_VS_LINE_END_2_MSB REG(0x00, 0xb5) /* write */ 149#define REG_VS_LINE_END_2_LSB REG(0x00, 0xb6) /* write */ 150#define REG_VS_PIX_END_2_MSB REG(0x00, 0xb7) /* write */ 151#define REG_VS_PIX_END_2_LSB REG(0x00, 0xb8) /* write */ 152#define REG_HS_PIX_START_MSB REG(0x00, 0xb9) /* write */ 153#define REG_HS_PIX_START_LSB REG(0x00, 0xba) /* write */ 154#define REG_HS_PIX_STOP_MSB REG(0x00, 0xbb) /* write */ 155#define REG_HS_PIX_STOP_LSB REG(0x00, 0xbc) /* write */ 156#define REG_VWIN_START_1_MSB REG(0x00, 0xbd) /* write */ 157#define REG_VWIN_START_1_LSB REG(0x00, 0xbe) /* write */ 158#define REG_VWIN_END_1_MSB REG(0x00, 0xbf) /* write */ 159#define REG_VWIN_END_1_LSB REG(0x00, 0xc0) /* write */ 160#define REG_VWIN_START_2_MSB REG(0x00, 0xc1) /* write */ 161#define REG_VWIN_START_2_LSB REG(0x00, 0xc2) /* write */ 162#define REG_VWIN_END_2_MSB REG(0x00, 0xc3) /* write */ 163#define REG_VWIN_END_2_LSB REG(0x00, 0xc4) /* write */ 164#define REG_DE_START_MSB REG(0x00, 0xc5) /* write */ 165#define REG_DE_START_LSB REG(0x00, 0xc6) /* write */ 166#define REG_DE_STOP_MSB REG(0x00, 0xc7) /* write */ 167#define REG_DE_STOP_LSB REG(0x00, 0xc8) /* write */ 168#define REG_TBG_CNTRL_0 REG(0x00, 0xca) /* write */ 169# define TBG_CNTRL_0_TOP_TGL (1 << 0) 170# define TBG_CNTRL_0_TOP_SEL (1 << 1) 171# define TBG_CNTRL_0_DE_EXT (1 << 2) 172# define TBG_CNTRL_0_TOP_EXT (1 << 3) 173# define TBG_CNTRL_0_FRAME_DIS (1 << 5) 174# define TBG_CNTRL_0_SYNC_MTHD (1 << 6) 175# define TBG_CNTRL_0_SYNC_ONCE (1 << 7) 176#define REG_TBG_CNTRL_1 REG(0x00, 0xcb) /* write */ 177# define TBG_CNTRL_1_H_TGL (1 << 0) 178# define TBG_CNTRL_1_V_TGL (1 << 1) 179# define TBG_CNTRL_1_TGL_EN (1 << 2) 180# define TBG_CNTRL_1_X_EXT (1 << 3) 181# define TBG_CNTRL_1_H_EXT (1 << 4) 182# define TBG_CNTRL_1_V_EXT (1 << 5) 183# define TBG_CNTRL_1_DWIN_DIS (1 << 6) 184#define REG_ENABLE_SPACE REG(0x00, 0xd6) /* write */ 185#define REG_HVF_CNTRL_0 REG(0x00, 0xe4) /* write */ 186# define HVF_CNTRL_0_SM (1 << 7) 187# define HVF_CNTRL_0_RWB (1 << 6) 188# define HVF_CNTRL_0_PREFIL(x) (((x) & 3) << 2) 189# define HVF_CNTRL_0_INTPOL(x) (((x) & 3) << 0) 190#define REG_HVF_CNTRL_1 REG(0x00, 0xe5) /* write */ 191# define HVF_CNTRL_1_FOR (1 << 0) 192# define HVF_CNTRL_1_YUVBLK (1 << 1) 193# define HVF_CNTRL_1_VQR(x) (((x) & 3) << 2) 194# define HVF_CNTRL_1_PAD(x) (((x) & 3) << 4) 195# define HVF_CNTRL_1_SEMI_PLANAR (1 << 6) 196#define REG_RPT_CNTRL REG(0x00, 0xf0) /* write */ 197#define REG_I2S_FORMAT REG(0x00, 0xfc) /* read/write */ 198# define I2S_FORMAT(x) (((x) & 3) << 0) 199#define REG_AIP_CLKSEL REG(0x00, 0xfd) /* write */ 200# define AIP_CLKSEL_FS(x) (((x) & 3) << 0) 201# define AIP_CLKSEL_CLK_POL(x) (((x) & 1) << 2) 202# define AIP_CLKSEL_AIP(x) (((x) & 7) << 3) 203 204 205/* Page 02h: PLL settings */ 206#define REG_PLL_SERIAL_1 REG(0x02, 0x00) /* read/write */ 207# define PLL_SERIAL_1_SRL_FDN (1 << 0) 208# define PLL_SERIAL_1_SRL_IZ(x) (((x) & 3) << 1) 209# define PLL_SERIAL_1_SRL_MAN_IZ (1 << 6) 210#define REG_PLL_SERIAL_2 REG(0x02, 0x01) /* read/write */ 211# define PLL_SERIAL_2_SRL_NOSC(x) ((x) << 0) 212# define PLL_SERIAL_2_SRL_PR(x) (((x) & 0xf) << 4) 213#define REG_PLL_SERIAL_3 REG(0x02, 0x02) /* read/write */ 214# define PLL_SERIAL_3_SRL_CCIR (1 << 0) 215# define PLL_SERIAL_3_SRL_DE (1 << 2) 216# define PLL_SERIAL_3_SRL_PXIN_SEL (1 << 4) 217#define REG_SERIALIZER REG(0x02, 0x03) /* read/write */ 218#define REG_BUFFER_OUT REG(0x02, 0x04) /* read/write */ 219#define REG_PLL_SCG1 REG(0x02, 0x05) /* read/write */ 220#define REG_PLL_SCG2 REG(0x02, 0x06) /* read/write */ 221#define REG_PLL_SCGN1 REG(0x02, 0x07) /* read/write */ 222#define REG_PLL_SCGN2 REG(0x02, 0x08) /* read/write */ 223#define REG_PLL_SCGR1 REG(0x02, 0x09) /* read/write */ 224#define REG_PLL_SCGR2 REG(0x02, 0x0a) /* read/write */ 225#define REG_AUDIO_DIV REG(0x02, 0x0e) /* read/write */ 226# define AUDIO_DIV_SERCLK_1 0 227# define AUDIO_DIV_SERCLK_2 1 228# define AUDIO_DIV_SERCLK_4 2 229# define AUDIO_DIV_SERCLK_8 3 230# define AUDIO_DIV_SERCLK_16 4 231# define AUDIO_DIV_SERCLK_32 5 232#define REG_SEL_CLK REG(0x02, 0x11) /* read/write */ 233# define SEL_CLK_SEL_CLK1 (1 << 0) 234# define SEL_CLK_SEL_VRF_CLK(x) (((x) & 3) << 1) 235# define SEL_CLK_ENA_SC_CLK (1 << 3) 236#define REG_ANA_GENERAL REG(0x02, 0x12) /* read/write */ 237 238 239/* Page 09h: EDID Control */ 240#define REG_EDID_DATA_0 REG(0x09, 0x00) /* read */ 241/* next 127 successive registers are the EDID block */ 242#define REG_EDID_CTRL REG(0x09, 0xfa) /* read/write */ 243#define REG_DDC_ADDR REG(0x09, 0xfb) /* read/write */ 244#define REG_DDC_OFFS REG(0x09, 0xfc) /* read/write */ 245#define REG_DDC_SEGM_ADDR REG(0x09, 0xfd) /* read/write */ 246#define REG_DDC_SEGM REG(0x09, 0xfe) /* read/write */ 247 248 249/* Page 10h: information frames and packets */ 250#define REG_IF1_HB0 REG(0x10, 0x20) /* read/write */ 251#define REG_IF2_HB0 REG(0x10, 0x40) /* read/write */ 252#define REG_IF3_HB0 REG(0x10, 0x60) /* read/write */ 253#define REG_IF4_HB0 REG(0x10, 0x80) /* read/write */ 254#define REG_IF5_HB0 REG(0x10, 0xa0) /* read/write */ 255 256 257/* Page 11h: audio settings and content info packets */ 258#define REG_AIP_CNTRL_0 REG(0x11, 0x00) /* read/write */ 259# define AIP_CNTRL_0_RST_FIFO (1 << 0) 260# define AIP_CNTRL_0_SWAP (1 << 1) 261# define AIP_CNTRL_0_LAYOUT (1 << 2) 262# define AIP_CNTRL_0_ACR_MAN (1 << 5) 263# define AIP_CNTRL_0_RST_CTS (1 << 6) 264#define REG_CA_I2S REG(0x11, 0x01) /* read/write */ 265# define CA_I2S_CA_I2S(x) (((x) & 31) << 0) 266# define CA_I2S_HBR_CHSTAT (1 << 6) 267#define REG_LATENCY_RD REG(0x11, 0x04) /* read/write */ 268#define REG_ACR_CTS_0 REG(0x11, 0x05) /* read/write */ 269#define REG_ACR_CTS_1 REG(0x11, 0x06) /* read/write */ 270#define REG_ACR_CTS_2 REG(0x11, 0x07) /* read/write */ 271#define REG_ACR_N_0 REG(0x11, 0x08) /* read/write */ 272#define REG_ACR_N_1 REG(0x11, 0x09) /* read/write */ 273#define REG_ACR_N_2 REG(0x11, 0x0a) /* read/write */ 274#define REG_CTS_N REG(0x11, 0x0c) /* read/write */ 275# define CTS_N_K(x) (((x) & 7) << 0) 276# define CTS_N_M(x) (((x) & 3) << 4) 277#define REG_ENC_CNTRL REG(0x11, 0x0d) /* read/write */ 278# define ENC_CNTRL_RST_ENC (1 << 0) 279# define ENC_CNTRL_RST_SEL (1 << 1) 280# define ENC_CNTRL_CTL_CODE(x) (((x) & 3) << 2) 281#define REG_DIP_FLAGS REG(0x11, 0x0e) /* read/write */ 282# define DIP_FLAGS_ACR (1 << 0) 283# define DIP_FLAGS_GC (1 << 1) 284#define REG_DIP_IF_FLAGS REG(0x11, 0x0f) /* read/write */ 285# define DIP_IF_FLAGS_IF1 (1 << 1) 286# define DIP_IF_FLAGS_IF2 (1 << 2) 287# define DIP_IF_FLAGS_IF3 (1 << 3) 288# define DIP_IF_FLAGS_IF4 (1 << 4) 289# define DIP_IF_FLAGS_IF5 (1 << 5) 290#define REG_CH_STAT_B(x) REG(0x11, 0x14 + (x)) /* read/write */ 291 292 293/* Page 12h: HDCP and OTP */ 294#define REG_TX3 REG(0x12, 0x9a) /* read/write */ 295#define REG_TX4 REG(0x12, 0x9b) /* read/write */ 296# define TX4_PD_RAM (1 << 1) 297#define REG_TX33 REG(0x12, 0xb8) /* read/write */ 298# define TX33_HDMI (1 << 1) 299 300 301/* Page 13h: Gamut related metadata packets */ 302 303 304 305/* CEC registers: (not paged) 306 */ 307#define REG_CEC_FRO_IM_CLK_CTRL 0xfb /* read/write */ 308# define CEC_FRO_IM_CLK_CTRL_GHOST_DIS (1 << 7) 309# define CEC_FRO_IM_CLK_CTRL_ENA_OTP (1 << 6) 310# define CEC_FRO_IM_CLK_CTRL_IMCLK_SEL (1 << 1) 311# define CEC_FRO_IM_CLK_CTRL_FRO_DIV (1 << 0) 312#define REG_CEC_RXSHPDLEV 0xfe /* read */ 313# define CEC_RXSHPDLEV_RXSENS (1 << 0) 314# define CEC_RXSHPDLEV_HPD (1 << 1) 315 316#define REG_CEC_ENAMODS 0xff /* read/write */ 317# define CEC_ENAMODS_DIS_FRO (1 << 6) 318# define CEC_ENAMODS_DIS_CCLK (1 << 5) 319# define CEC_ENAMODS_EN_RXSENS (1 << 2) 320# define CEC_ENAMODS_EN_HDMI (1 << 1) 321# define CEC_ENAMODS_EN_CEC (1 << 0) 322 323 324/* Device versions: */ 325#define TDA9989N2 0x0101 326#define TDA19989 0x0201 327#define TDA19989N2 0x0202 328#define TDA19988 0x0301 329 330static void 331cec_write(struct drm_encoder *encoder, uint16_t addr, uint8_t val) 332{ 333 struct i2c_client *client = to_tda998x_priv(encoder)->cec; 334 uint8_t buf[] = {addr, val}; 335 int ret; 336 337 ret = i2c_master_send(client, buf, ARRAY_SIZE(buf)); 338 if (ret < 0) 339 dev_err(&client->dev, "Error %d writing to cec:0x%x\n", ret, addr); 340} 341 342static uint8_t 343cec_read(struct drm_encoder *encoder, uint8_t addr) 344{ 345 struct i2c_client *client = to_tda998x_priv(encoder)->cec; 346 uint8_t val; 347 int ret; 348 349 ret = i2c_master_send(client, &addr, sizeof(addr)); 350 if (ret < 0) 351 goto fail; 352 353 ret = i2c_master_recv(client, &val, sizeof(val)); 354 if (ret < 0) 355 goto fail; 356 357 return val; 358 359fail: 360 dev_err(&client->dev, "Error %d reading from cec:0x%x\n", ret, addr); 361 return 0; 362} 363 364static void 365set_page(struct drm_encoder *encoder, uint16_t reg) 366{ 367 struct tda998x_priv *priv = to_tda998x_priv(encoder); 368 369 if (REG2PAGE(reg) != priv->current_page) { 370 struct i2c_client *client = drm_i2c_encoder_get_client(encoder); 371 uint8_t buf[] = { 372 REG_CURPAGE, REG2PAGE(reg) 373 }; 374 int ret = i2c_master_send(client, buf, sizeof(buf)); 375 if (ret < 0) 376 dev_err(&client->dev, "Error %d writing to REG_CURPAGE\n", ret); 377 378 priv->current_page = REG2PAGE(reg); 379 } 380} 381 382static int 383reg_read_range(struct drm_encoder *encoder, uint16_t reg, char *buf, int cnt) 384{ 385 struct i2c_client *client = drm_i2c_encoder_get_client(encoder); 386 uint8_t addr = REG2ADDR(reg); 387 int ret; 388 389 set_page(encoder, reg); 390 391 ret = i2c_master_send(client, &addr, sizeof(addr)); 392 if (ret < 0) 393 goto fail; 394 395 ret = i2c_master_recv(client, buf, cnt); 396 if (ret < 0) 397 goto fail; 398 399 return ret; 400 401fail: 402 dev_err(&client->dev, "Error %d reading from 0x%x\n", ret, reg); 403 return ret; 404} 405 406static void 407reg_write_range(struct drm_encoder *encoder, uint16_t reg, uint8_t *p, int cnt) 408{ 409 struct i2c_client *client = drm_i2c_encoder_get_client(encoder); 410 uint8_t buf[cnt+1]; 411 int ret; 412 413 buf[0] = REG2ADDR(reg); 414 memcpy(&buf[1], p, cnt); 415 416 set_page(encoder, reg); 417 418 ret = i2c_master_send(client, buf, cnt + 1); 419 if (ret < 0) 420 dev_err(&client->dev, "Error %d writing to 0x%x\n", ret, reg); 421} 422 423static uint8_t 424reg_read(struct drm_encoder *encoder, uint16_t reg) 425{ 426 uint8_t val = 0; 427 reg_read_range(encoder, reg, &val, sizeof(val)); 428 return val; 429} 430 431static void 432reg_write(struct drm_encoder *encoder, uint16_t reg, uint8_t val) 433{ 434 struct i2c_client *client = drm_i2c_encoder_get_client(encoder); 435 uint8_t buf[] = {REG2ADDR(reg), val}; 436 int ret; 437 438 set_page(encoder, reg); 439 440 ret = i2c_master_send(client, buf, ARRAY_SIZE(buf)); 441 if (ret < 0) 442 dev_err(&client->dev, "Error %d writing to 0x%x\n", ret, reg); 443} 444 445static void 446reg_write16(struct drm_encoder *encoder, uint16_t reg, uint16_t val) 447{ 448 struct i2c_client *client = drm_i2c_encoder_get_client(encoder); 449 uint8_t buf[] = {REG2ADDR(reg), val >> 8, val}; 450 int ret; 451 452 set_page(encoder, reg); 453 454 ret = i2c_master_send(client, buf, ARRAY_SIZE(buf)); 455 if (ret < 0) 456 dev_err(&client->dev, "Error %d writing to 0x%x\n", ret, reg); 457} 458 459static void 460reg_set(struct drm_encoder *encoder, uint16_t reg, uint8_t val) 461{ 462 reg_write(encoder, reg, reg_read(encoder, reg) | val); 463} 464 465static void 466reg_clear(struct drm_encoder *encoder, uint16_t reg, uint8_t val) 467{ 468 reg_write(encoder, reg, reg_read(encoder, reg) & ~val); 469} 470 471static void 472tda998x_reset(struct drm_encoder *encoder) 473{ 474 /* reset audio and i2c master: */ 475 reg_set(encoder, REG_SOFTRESET, SOFTRESET_AUDIO | SOFTRESET_I2C_MASTER); 476 msleep(50); 477 reg_clear(encoder, REG_SOFTRESET, SOFTRESET_AUDIO | SOFTRESET_I2C_MASTER); 478 msleep(50); 479 480 /* reset transmitter: */ 481 reg_set(encoder, REG_MAIN_CNTRL0, MAIN_CNTRL0_SR); 482 reg_clear(encoder, REG_MAIN_CNTRL0, MAIN_CNTRL0_SR); 483 484 /* PLL registers common configuration */ 485 reg_write(encoder, REG_PLL_SERIAL_1, 0x00); 486 reg_write(encoder, REG_PLL_SERIAL_2, PLL_SERIAL_2_SRL_NOSC(1)); 487 reg_write(encoder, REG_PLL_SERIAL_3, 0x00); 488 reg_write(encoder, REG_SERIALIZER, 0x00); 489 reg_write(encoder, REG_BUFFER_OUT, 0x00); 490 reg_write(encoder, REG_PLL_SCG1, 0x00); 491 reg_write(encoder, REG_AUDIO_DIV, AUDIO_DIV_SERCLK_8); 492 reg_write(encoder, REG_SEL_CLK, SEL_CLK_SEL_CLK1 | SEL_CLK_ENA_SC_CLK); 493 reg_write(encoder, REG_PLL_SCGN1, 0xfa); 494 reg_write(encoder, REG_PLL_SCGN2, 0x00); 495 reg_write(encoder, REG_PLL_SCGR1, 0x5b); 496 reg_write(encoder, REG_PLL_SCGR2, 0x00); 497 reg_write(encoder, REG_PLL_SCG2, 0x10); 498 499 /* Write the default value MUX register */ 500 reg_write(encoder, REG_MUX_VP_VIP_OUT, 0x24); 501} 502 503static uint8_t tda998x_cksum(uint8_t *buf, size_t bytes) 504{ 505 uint8_t sum = 0; 506 507 while (bytes--) 508 sum += *buf++; 509 return (255 - sum) + 1; 510} 511 512#define HB(x) (x) 513#define PB(x) (HB(2) + 1 + (x)) 514 515static void 516tda998x_write_if(struct drm_encoder *encoder, uint8_t bit, uint16_t addr, 517 uint8_t *buf, size_t size) 518{ 519 buf[PB(0)] = tda998x_cksum(buf, size); 520 521 reg_clear(encoder, REG_DIP_IF_FLAGS, bit); 522 reg_write_range(encoder, addr, buf, size); 523 reg_set(encoder, REG_DIP_IF_FLAGS, bit); 524} 525 526static void 527tda998x_write_aif(struct drm_encoder *encoder, struct tda998x_encoder_params *p) 528{ 529 u8 buf[PB(HDMI_AUDIO_INFOFRAME_SIZE) + 1]; 530 531 memset(buf, 0, sizeof(buf)); 532 buf[HB(0)] = HDMI_INFOFRAME_TYPE_AUDIO; 533 buf[HB(1)] = 0x01; 534 buf[HB(2)] = HDMI_AUDIO_INFOFRAME_SIZE; 535 buf[PB(1)] = p->audio_frame[1] & 0x07; /* CC */ 536 buf[PB(2)] = p->audio_frame[2] & 0x1c; /* SF */ 537 buf[PB(4)] = p->audio_frame[4]; 538 buf[PB(5)] = p->audio_frame[5] & 0xf8; /* DM_INH + LSV */ 539 540 tda998x_write_if(encoder, DIP_IF_FLAGS_IF4, REG_IF4_HB0, buf, 541 sizeof(buf)); 542} 543 544static void 545tda998x_write_avi(struct drm_encoder *encoder, struct drm_display_mode *mode) 546{ 547 u8 buf[PB(HDMI_AVI_INFOFRAME_SIZE) + 1]; 548 549 memset(buf, 0, sizeof(buf)); 550 buf[HB(0)] = HDMI_INFOFRAME_TYPE_AVI; 551 buf[HB(1)] = 0x02; 552 buf[HB(2)] = HDMI_AVI_INFOFRAME_SIZE; 553 buf[PB(1)] = HDMI_SCAN_MODE_UNDERSCAN; 554 buf[PB(2)] = HDMI_ACTIVE_ASPECT_PICTURE; 555 buf[PB(3)] = HDMI_QUANTIZATION_RANGE_FULL << 2; 556 buf[PB(4)] = drm_match_cea_mode(mode); 557 558 tda998x_write_if(encoder, DIP_IF_FLAGS_IF2, REG_IF2_HB0, buf, 559 sizeof(buf)); 560} 561 562static void tda998x_audio_mute(struct drm_encoder *encoder, bool on) 563{ 564 if (on) { 565 reg_set(encoder, REG_SOFTRESET, SOFTRESET_AUDIO); 566 reg_clear(encoder, REG_SOFTRESET, SOFTRESET_AUDIO); 567 reg_set(encoder, REG_AIP_CNTRL_0, AIP_CNTRL_0_RST_FIFO); 568 } else { 569 reg_clear(encoder, REG_AIP_CNTRL_0, AIP_CNTRL_0_RST_FIFO); 570 } 571} 572 573static void 574tda998x_configure_audio(struct drm_encoder *encoder, 575 struct drm_display_mode *mode, struct tda998x_encoder_params *p) 576{ 577 uint8_t buf[6], clksel_aip, clksel_fs, ca_i2s, cts_n, adiv; 578 uint32_t n; 579 580 /* Enable audio ports */ 581 reg_write(encoder, REG_ENA_AP, p->audio_cfg); 582 reg_write(encoder, REG_ENA_ACLK, p->audio_clk_cfg); 583 584 /* Set audio input source */ 585 switch (p->audio_format) { 586 case AFMT_SPDIF: 587 reg_write(encoder, REG_MUX_AP, 0x40); 588 clksel_aip = AIP_CLKSEL_AIP(0); 589 /* FS64SPDIF */ 590 clksel_fs = AIP_CLKSEL_FS(2); 591 cts_n = CTS_N_M(3) | CTS_N_K(3); 592 ca_i2s = 0; 593 break; 594 595 case AFMT_I2S: 596 reg_write(encoder, REG_MUX_AP, 0x64); 597 clksel_aip = AIP_CLKSEL_AIP(1); 598 /* ACLK */ 599 clksel_fs = AIP_CLKSEL_FS(0); 600 cts_n = CTS_N_M(3) | CTS_N_K(3); 601 ca_i2s = CA_I2S_CA_I2S(0); 602 break; 603 604 default: 605 BUG(); 606 return; 607 } 608 609 reg_write(encoder, REG_AIP_CLKSEL, clksel_aip); 610 reg_clear(encoder, REG_AIP_CNTRL_0, AIP_CNTRL_0_LAYOUT); 611 612 /* Enable automatic CTS generation */ 613 reg_clear(encoder, REG_AIP_CNTRL_0, AIP_CNTRL_0_ACR_MAN); 614 reg_write(encoder, REG_CTS_N, cts_n); 615 616 /* 617 * Audio input somehow depends on HDMI line rate which is 618 * related to pixclk. Testing showed that modes with pixclk 619 * >100MHz need a larger divider while <40MHz need the default. 620 * There is no detailed info in the datasheet, so we just 621 * assume 100MHz requires larger divider. 622 */ 623 if (mode->clock > 100000) 624 adiv = AUDIO_DIV_SERCLK_16; 625 else 626 adiv = AUDIO_DIV_SERCLK_8; 627 reg_write(encoder, REG_AUDIO_DIV, adiv); 628 629 /* 630 * This is the approximate value of N, which happens to be 631 * the recommended values for non-coherent clocks. 632 */ 633 n = 128 * p->audio_sample_rate / 1000; 634 635 /* Write the CTS and N values */ 636 buf[0] = 0x44; 637 buf[1] = 0x42; 638 buf[2] = 0x01; 639 buf[3] = n; 640 buf[4] = n >> 8; 641 buf[5] = n >> 16; 642 reg_write_range(encoder, REG_ACR_CTS_0, buf, 6); 643 644 /* Set CTS clock reference */ 645 reg_write(encoder, REG_AIP_CLKSEL, clksel_aip | clksel_fs); 646 647 /* Reset CTS generator */ 648 reg_set(encoder, REG_AIP_CNTRL_0, AIP_CNTRL_0_RST_CTS); 649 reg_clear(encoder, REG_AIP_CNTRL_0, AIP_CNTRL_0_RST_CTS); 650 651 /* Write the channel status */ 652 buf[0] = 0x04; 653 buf[1] = 0x00; 654 buf[2] = 0x00; 655 buf[3] = 0xf1; 656 reg_write_range(encoder, REG_CH_STAT_B(0), buf, 4); 657 658 tda998x_audio_mute(encoder, true); 659 mdelay(20); 660 tda998x_audio_mute(encoder, false); 661 662 /* Write the audio information packet */ 663 tda998x_write_aif(encoder, p); 664} 665 666/* DRM encoder functions */ 667 668static void 669tda998x_encoder_set_config(struct drm_encoder *encoder, void *params) 670{ 671 struct tda998x_priv *priv = to_tda998x_priv(encoder); 672 struct tda998x_encoder_params *p = params; 673 674 priv->vip_cntrl_0 = VIP_CNTRL_0_SWAP_A(p->swap_a) | 675 (p->mirr_a ? VIP_CNTRL_0_MIRR_A : 0) | 676 VIP_CNTRL_0_SWAP_B(p->swap_b) | 677 (p->mirr_b ? VIP_CNTRL_0_MIRR_B : 0); 678 priv->vip_cntrl_1 = VIP_CNTRL_1_SWAP_C(p->swap_c) | 679 (p->mirr_c ? VIP_CNTRL_1_MIRR_C : 0) | 680 VIP_CNTRL_1_SWAP_D(p->swap_d) | 681 (p->mirr_d ? VIP_CNTRL_1_MIRR_D : 0); 682 priv->vip_cntrl_2 = VIP_CNTRL_2_SWAP_E(p->swap_e) | 683 (p->mirr_e ? VIP_CNTRL_2_MIRR_E : 0) | 684 VIP_CNTRL_2_SWAP_F(p->swap_f) | 685 (p->mirr_f ? VIP_CNTRL_2_MIRR_F : 0); 686 687 priv->params = *p; 688} 689 690static void 691tda998x_encoder_dpms(struct drm_encoder *encoder, int mode) 692{ 693 struct tda998x_priv *priv = to_tda998x_priv(encoder); 694 695 /* we only care about on or off: */ 696 if (mode != DRM_MODE_DPMS_ON) 697 mode = DRM_MODE_DPMS_OFF; 698 699 if (mode == priv->dpms) 700 return; 701 702 switch (mode) { 703 case DRM_MODE_DPMS_ON: 704 /* enable video ports, audio will be enabled later */ 705 reg_write(encoder, REG_ENA_VP_0, 0xff); 706 reg_write(encoder, REG_ENA_VP_1, 0xff); 707 reg_write(encoder, REG_ENA_VP_2, 0xff); 708 /* set muxing after enabling ports: */ 709 reg_write(encoder, REG_VIP_CNTRL_0, priv->vip_cntrl_0); 710 reg_write(encoder, REG_VIP_CNTRL_1, priv->vip_cntrl_1); 711 reg_write(encoder, REG_VIP_CNTRL_2, priv->vip_cntrl_2); 712 break; 713 case DRM_MODE_DPMS_OFF: 714 /* disable video ports */ 715 reg_write(encoder, REG_ENA_VP_0, 0x00); 716 reg_write(encoder, REG_ENA_VP_1, 0x00); 717 reg_write(encoder, REG_ENA_VP_2, 0x00); 718 break; 719 } 720 721 priv->dpms = mode; 722} 723 724static void 725tda998x_encoder_save(struct drm_encoder *encoder) 726{ 727 DBG(""); 728} 729 730static void 731tda998x_encoder_restore(struct drm_encoder *encoder) 732{ 733 DBG(""); 734} 735 736static bool 737tda998x_encoder_mode_fixup(struct drm_encoder *encoder, 738 const struct drm_display_mode *mode, 739 struct drm_display_mode *adjusted_mode) 740{ 741 return true; 742} 743 744static int 745tda998x_encoder_mode_valid(struct drm_encoder *encoder, 746 struct drm_display_mode *mode) 747{ 748 return MODE_OK; 749} 750 751static void 752tda998x_encoder_mode_set(struct drm_encoder *encoder, 753 struct drm_display_mode *mode, 754 struct drm_display_mode *adjusted_mode) 755{ 756 struct tda998x_priv *priv = to_tda998x_priv(encoder); 757 uint16_t ref_pix, ref_line, n_pix, n_line; 758 uint16_t hs_pix_s, hs_pix_e; 759 uint16_t vs1_pix_s, vs1_pix_e, vs1_line_s, vs1_line_e; 760 uint16_t vs2_pix_s, vs2_pix_e, vs2_line_s, vs2_line_e; 761 uint16_t vwin1_line_s, vwin1_line_e; 762 uint16_t vwin2_line_s, vwin2_line_e; 763 uint16_t de_pix_s, de_pix_e; 764 uint8_t reg, div, rep; 765 766 /* 767 * Internally TDA998x is using ITU-R BT.656 style sync but 768 * we get VESA style sync. TDA998x is using a reference pixel 769 * relative to ITU to sync to the input frame and for output 770 * sync generation. Currently, we are using reference detection 771 * from HS/VS, i.e. REFPIX/REFLINE denote frame start sync point 772 * which is position of rising VS with coincident rising HS. 773 * 774 * Now there is some issues to take care of: 775 * - HDMI data islands require sync-before-active 776 * - TDA998x register values must be > 0 to be enabled 777 * - REFLINE needs an additional offset of +1 778 * - REFPIX needs an addtional offset of +1 for UYUV and +3 for RGB 779 * 780 * So we add +1 to all horizontal and vertical register values, 781 * plus an additional +3 for REFPIX as we are using RGB input only. 782 */ 783 n_pix = mode->htotal; 784 n_line = mode->vtotal; 785 786 hs_pix_e = mode->hsync_end - mode->hdisplay; 787 hs_pix_s = mode->hsync_start - mode->hdisplay; 788 de_pix_e = mode->htotal; 789 de_pix_s = mode->htotal - mode->hdisplay; 790 ref_pix = 3 + hs_pix_s; 791 792 /* 793 * Attached LCD controllers may generate broken sync. Allow 794 * those to adjust the position of the rising VS edge by adding 795 * HSKEW to ref_pix. 796 */ 797 if (adjusted_mode->flags & DRM_MODE_FLAG_HSKEW) 798 ref_pix += adjusted_mode->hskew; 799 800 if ((mode->flags & DRM_MODE_FLAG_INTERLACE) == 0) { 801 ref_line = 1 + mode->vsync_start - mode->vdisplay; 802 vwin1_line_s = mode->vtotal - mode->vdisplay - 1; 803 vwin1_line_e = vwin1_line_s + mode->vdisplay; 804 vs1_pix_s = vs1_pix_e = hs_pix_s; 805 vs1_line_s = mode->vsync_start - mode->vdisplay; 806 vs1_line_e = vs1_line_s + 807 mode->vsync_end - mode->vsync_start; 808 vwin2_line_s = vwin2_line_e = 0; 809 vs2_pix_s = vs2_pix_e = 0; 810 vs2_line_s = vs2_line_e = 0; 811 } else { 812 ref_line = 1 + (mode->vsync_start - mode->vdisplay)/2; 813 vwin1_line_s = (mode->vtotal - mode->vdisplay)/2; 814 vwin1_line_e = vwin1_line_s + mode->vdisplay/2; 815 vs1_pix_s = vs1_pix_e = hs_pix_s; 816 vs1_line_s = (mode->vsync_start - mode->vdisplay)/2; 817 vs1_line_e = vs1_line_s + 818 (mode->vsync_end - mode->vsync_start)/2; 819 vwin2_line_s = vwin1_line_s + mode->vtotal/2; 820 vwin2_line_e = vwin2_line_s + mode->vdisplay/2; 821 vs2_pix_s = vs2_pix_e = hs_pix_s + mode->htotal/2; 822 vs2_line_s = vs1_line_s + mode->vtotal/2 ; 823 vs2_line_e = vs2_line_s + 824 (mode->vsync_end - mode->vsync_start)/2; 825 } 826 827 div = 148500 / mode->clock; 828 if (div != 0) { 829 div--; 830 if (div > 3) 831 div = 3; 832 } 833 834 /* mute the audio FIFO: */ 835 reg_set(encoder, REG_AIP_CNTRL_0, AIP_CNTRL_0_RST_FIFO); 836 837 /* set HDMI HDCP mode off: */ 838 reg_set(encoder, REG_TBG_CNTRL_1, TBG_CNTRL_1_DWIN_DIS); 839 reg_clear(encoder, REG_TX33, TX33_HDMI); 840 841 reg_write(encoder, REG_ENC_CNTRL, ENC_CNTRL_CTL_CODE(0)); 842 /* no pre-filter or interpolator: */ 843 reg_write(encoder, REG_HVF_CNTRL_0, HVF_CNTRL_0_PREFIL(0) | 844 HVF_CNTRL_0_INTPOL(0)); 845 reg_write(encoder, REG_VIP_CNTRL_5, VIP_CNTRL_5_SP_CNT(0)); 846 reg_write(encoder, REG_VIP_CNTRL_4, VIP_CNTRL_4_BLANKIT(0) | 847 VIP_CNTRL_4_BLC(0)); 848 reg_clear(encoder, REG_PLL_SERIAL_3, PLL_SERIAL_3_SRL_CCIR); 849 850 reg_clear(encoder, REG_PLL_SERIAL_1, PLL_SERIAL_1_SRL_MAN_IZ); 851 reg_clear(encoder, REG_PLL_SERIAL_3, PLL_SERIAL_3_SRL_DE); 852 reg_write(encoder, REG_SERIALIZER, 0); 853 reg_write(encoder, REG_HVF_CNTRL_1, HVF_CNTRL_1_VQR(0)); 854 855 /* TODO enable pixel repeat for pixel rates less than 25Msamp/s */ 856 rep = 0; 857 reg_write(encoder, REG_RPT_CNTRL, 0); 858 reg_write(encoder, REG_SEL_CLK, SEL_CLK_SEL_VRF_CLK(0) | 859 SEL_CLK_SEL_CLK1 | SEL_CLK_ENA_SC_CLK); 860 861 reg_write(encoder, REG_PLL_SERIAL_2, PLL_SERIAL_2_SRL_NOSC(div) | 862 PLL_SERIAL_2_SRL_PR(rep)); 863 864 /* set color matrix bypass flag: */ 865 reg_set(encoder, REG_MAT_CONTRL, MAT_CONTRL_MAT_BP); 866 867 /* set BIAS tmds value: */ 868 reg_write(encoder, REG_ANA_GENERAL, 0x09); 869 870 reg_clear(encoder, REG_TBG_CNTRL_0, TBG_CNTRL_0_SYNC_MTHD); 871 872 /* 873 * Sync on rising HSYNC/VSYNC 874 */ 875 reg_write(encoder, REG_VIP_CNTRL_3, 0); 876 reg_set(encoder, REG_VIP_CNTRL_3, VIP_CNTRL_3_SYNC_HS); 877 878 /* 879 * TDA19988 requires high-active sync at input stage, 880 * so invert low-active sync provided by master encoder here 881 */ 882 if (mode->flags & DRM_MODE_FLAG_NHSYNC) 883 reg_set(encoder, REG_VIP_CNTRL_3, VIP_CNTRL_3_H_TGL); 884 if (mode->flags & DRM_MODE_FLAG_NVSYNC) 885 reg_set(encoder, REG_VIP_CNTRL_3, VIP_CNTRL_3_V_TGL); 886 887 /* 888 * Always generate sync polarity relative to input sync and 889 * revert input stage toggled sync at output stage 890 */ 891 reg = TBG_CNTRL_1_TGL_EN; 892 if (mode->flags & DRM_MODE_FLAG_NHSYNC) 893 reg |= TBG_CNTRL_1_H_TGL; 894 if (mode->flags & DRM_MODE_FLAG_NVSYNC) 895 reg |= TBG_CNTRL_1_V_TGL; 896 reg_write(encoder, REG_TBG_CNTRL_1, reg); 897 898 reg_write(encoder, REG_VIDFORMAT, 0x00); 899 reg_write16(encoder, REG_REFPIX_MSB, ref_pix); 900 reg_write16(encoder, REG_REFLINE_MSB, ref_line); 901 reg_write16(encoder, REG_NPIX_MSB, n_pix); 902 reg_write16(encoder, REG_NLINE_MSB, n_line); 903 reg_write16(encoder, REG_VS_LINE_STRT_1_MSB, vs1_line_s); 904 reg_write16(encoder, REG_VS_PIX_STRT_1_MSB, vs1_pix_s); 905 reg_write16(encoder, REG_VS_LINE_END_1_MSB, vs1_line_e); 906 reg_write16(encoder, REG_VS_PIX_END_1_MSB, vs1_pix_e); 907 reg_write16(encoder, REG_VS_LINE_STRT_2_MSB, vs2_line_s); 908 reg_write16(encoder, REG_VS_PIX_STRT_2_MSB, vs2_pix_s); 909 reg_write16(encoder, REG_VS_LINE_END_2_MSB, vs2_line_e); 910 reg_write16(encoder, REG_VS_PIX_END_2_MSB, vs2_pix_e); 911 reg_write16(encoder, REG_HS_PIX_START_MSB, hs_pix_s); 912 reg_write16(encoder, REG_HS_PIX_STOP_MSB, hs_pix_e); 913 reg_write16(encoder, REG_VWIN_START_1_MSB, vwin1_line_s); 914 reg_write16(encoder, REG_VWIN_END_1_MSB, vwin1_line_e); 915 reg_write16(encoder, REG_VWIN_START_2_MSB, vwin2_line_s); 916 reg_write16(encoder, REG_VWIN_END_2_MSB, vwin2_line_e); 917 reg_write16(encoder, REG_DE_START_MSB, de_pix_s); 918 reg_write16(encoder, REG_DE_STOP_MSB, de_pix_e); 919 920 if (priv->rev == TDA19988) { 921 /* let incoming pixels fill the active space (if any) */ 922 reg_write(encoder, REG_ENABLE_SPACE, 0x00); 923 } 924 925 /* must be last register set: */ 926 reg_clear(encoder, REG_TBG_CNTRL_0, TBG_CNTRL_0_SYNC_ONCE); 927 928 /* Only setup the info frames if the sink is HDMI */ 929 if (priv->is_hdmi_sink) { 930 /* We need to turn HDMI HDCP stuff on to get audio through */ 931 reg_clear(encoder, REG_TBG_CNTRL_1, TBG_CNTRL_1_DWIN_DIS); 932 reg_write(encoder, REG_ENC_CNTRL, ENC_CNTRL_CTL_CODE(1)); 933 reg_set(encoder, REG_TX33, TX33_HDMI); 934 935 tda998x_write_avi(encoder, adjusted_mode); 936 937 if (priv->params.audio_cfg) 938 tda998x_configure_audio(encoder, adjusted_mode, 939 &priv->params); 940 } 941} 942 943static enum drm_connector_status 944tda998x_encoder_detect(struct drm_encoder *encoder, 945 struct drm_connector *connector) 946{ 947 uint8_t val = cec_read(encoder, REG_CEC_RXSHPDLEV); 948 return (val & CEC_RXSHPDLEV_HPD) ? connector_status_connected : 949 connector_status_disconnected; 950} 951 952static int 953read_edid_block(struct drm_encoder *encoder, uint8_t *buf, int blk) 954{ 955 uint8_t offset, segptr; 956 int ret, i; 957 958 /* enable EDID read irq: */ 959 reg_set(encoder, REG_INT_FLAGS_2, INT_FLAGS_2_EDID_BLK_RD); 960 961 offset = (blk & 1) ? 128 : 0; 962 segptr = blk / 2; 963 964 reg_write(encoder, REG_DDC_ADDR, 0xa0); 965 reg_write(encoder, REG_DDC_OFFS, offset); 966 reg_write(encoder, REG_DDC_SEGM_ADDR, 0x60); 967 reg_write(encoder, REG_DDC_SEGM, segptr); 968 969 /* enable reading EDID: */ 970 reg_write(encoder, REG_EDID_CTRL, 0x1); 971 972 /* flag must be cleared by sw: */ 973 reg_write(encoder, REG_EDID_CTRL, 0x0); 974 975 /* wait for block read to complete: */ 976 for (i = 100; i > 0; i--) { 977 uint8_t val = reg_read(encoder, REG_INT_FLAGS_2); 978 if (val & INT_FLAGS_2_EDID_BLK_RD) 979 break; 980 msleep(1); 981 } 982 983 if (i == 0) 984 return -ETIMEDOUT; 985 986 ret = reg_read_range(encoder, REG_EDID_DATA_0, buf, EDID_LENGTH); 987 if (ret != EDID_LENGTH) { 988 dev_err(encoder->dev->dev, "failed to read edid block %d: %d", 989 blk, ret); 990 return ret; 991 } 992 993 reg_clear(encoder, REG_INT_FLAGS_2, INT_FLAGS_2_EDID_BLK_RD); 994 995 return 0; 996} 997 998static uint8_t * 999do_get_edid(struct drm_encoder *encoder) 1000{ 1001 struct tda998x_priv *priv = to_tda998x_priv(encoder); 1002 int j = 0, valid_extensions = 0; 1003 uint8_t *block, *new; 1004 bool print_bad_edid = drm_debug & DRM_UT_KMS; 1005 1006 if ((block = kmalloc(EDID_LENGTH, GFP_KERNEL)) == NULL) 1007 return NULL; 1008 1009 if (priv->rev == TDA19988) 1010 reg_clear(encoder, REG_TX4, TX4_PD_RAM); 1011 1012 /* base block fetch */ 1013 if (read_edid_block(encoder, block, 0)) 1014 goto fail; 1015 1016 if (!drm_edid_block_valid(block, 0, print_bad_edid)) 1017 goto fail; 1018 1019 /* if there's no extensions, we're done */ 1020 if (block[0x7e] == 0) 1021 goto done; 1022 1023 new = krealloc(block, (block[0x7e] + 1) * EDID_LENGTH, GFP_KERNEL); 1024 if (!new) 1025 goto fail; 1026 block = new; 1027 1028 for (j = 1; j <= block[0x7e]; j++) { 1029 uint8_t *ext_block = block + (valid_extensions + 1) * EDID_LENGTH; 1030 if (read_edid_block(encoder, ext_block, j)) 1031 goto fail; 1032 1033 if (!drm_edid_block_valid(ext_block, j, print_bad_edid)) 1034 goto fail; 1035 1036 valid_extensions++; 1037 } 1038 1039 if (valid_extensions != block[0x7e]) { 1040 block[EDID_LENGTH-1] += block[0x7e] - valid_extensions; 1041 block[0x7e] = valid_extensions; 1042 new = krealloc(block, (valid_extensions + 1) * EDID_LENGTH, GFP_KERNEL); 1043 if (!new) 1044 goto fail; 1045 block = new; 1046 } 1047 1048done: 1049 if (priv->rev == TDA19988) 1050 reg_set(encoder, REG_TX4, TX4_PD_RAM); 1051 1052 return block; 1053 1054fail: 1055 if (priv->rev == TDA19988) 1056 reg_set(encoder, REG_TX4, TX4_PD_RAM); 1057 dev_warn(encoder->dev->dev, "failed to read EDID\n"); 1058 kfree(block); 1059 return NULL; 1060} 1061 1062static int 1063tda998x_encoder_get_modes(struct drm_encoder *encoder, 1064 struct drm_connector *connector) 1065{ 1066 struct tda998x_priv *priv = to_tda998x_priv(encoder); 1067 struct edid *edid = (struct edid *)do_get_edid(encoder); 1068 int n = 0; 1069 1070 if (edid) { 1071 drm_mode_connector_update_edid_property(connector, edid); 1072 n = drm_add_edid_modes(connector, edid); 1073 priv->is_hdmi_sink = drm_detect_hdmi_monitor(edid); 1074 kfree(edid); 1075 } 1076 1077 return n; 1078} 1079 1080static int 1081tda998x_encoder_create_resources(struct drm_encoder *encoder, 1082 struct drm_connector *connector) 1083{ 1084 DBG(""); 1085 return 0; 1086} 1087 1088static int 1089tda998x_encoder_set_property(struct drm_encoder *encoder, 1090 struct drm_connector *connector, 1091 struct drm_property *property, 1092 uint64_t val) 1093{ 1094 DBG(""); 1095 return 0; 1096} 1097 1098static void 1099tda998x_encoder_destroy(struct drm_encoder *encoder) 1100{ 1101 struct tda998x_priv *priv = to_tda998x_priv(encoder); 1102 drm_i2c_encoder_destroy(encoder); 1103 if (priv->cec) 1104 i2c_unregister_device(priv->cec); 1105 kfree(priv); 1106} 1107 1108static struct drm_encoder_slave_funcs tda998x_encoder_funcs = { 1109 .set_config = tda998x_encoder_set_config, 1110 .destroy = tda998x_encoder_destroy, 1111 .dpms = tda998x_encoder_dpms, 1112 .save = tda998x_encoder_save, 1113 .restore = tda998x_encoder_restore, 1114 .mode_fixup = tda998x_encoder_mode_fixup, 1115 .mode_valid = tda998x_encoder_mode_valid, 1116 .mode_set = tda998x_encoder_mode_set, 1117 .detect = tda998x_encoder_detect, 1118 .get_modes = tda998x_encoder_get_modes, 1119 .create_resources = tda998x_encoder_create_resources, 1120 .set_property = tda998x_encoder_set_property, 1121}; 1122 1123/* I2C driver functions */ 1124 1125static int 1126tda998x_probe(struct i2c_client *client, const struct i2c_device_id *id) 1127{ 1128 return 0; 1129} 1130 1131static int 1132tda998x_remove(struct i2c_client *client) 1133{ 1134 return 0; 1135} 1136 1137static int 1138tda998x_encoder_init(struct i2c_client *client, 1139 struct drm_device *dev, 1140 struct drm_encoder_slave *encoder_slave) 1141{ 1142 struct drm_encoder *encoder = &encoder_slave->base; 1143 struct tda998x_priv *priv; 1144 1145 priv = kzalloc(sizeof(*priv), GFP_KERNEL); 1146 if (!priv) 1147 return -ENOMEM; 1148 1149 priv->vip_cntrl_0 = VIP_CNTRL_0_SWAP_A(2) | VIP_CNTRL_0_SWAP_B(3); 1150 priv->vip_cntrl_1 = VIP_CNTRL_1_SWAP_C(0) | VIP_CNTRL_1_SWAP_D(1); 1151 priv->vip_cntrl_2 = VIP_CNTRL_2_SWAP_E(4) | VIP_CNTRL_2_SWAP_F(5); 1152 1153 priv->current_page = 0xff; 1154 priv->cec = i2c_new_dummy(client->adapter, 0x34); 1155 if (!priv->cec) { 1156 kfree(priv); 1157 return -ENODEV; 1158 } 1159 priv->dpms = DRM_MODE_DPMS_OFF; 1160 1161 encoder_slave->slave_priv = priv; 1162 encoder_slave->slave_funcs = &tda998x_encoder_funcs; 1163 1164 /* wake up the device: */ 1165 cec_write(encoder, REG_CEC_ENAMODS, 1166 CEC_ENAMODS_EN_RXSENS | CEC_ENAMODS_EN_HDMI); 1167 1168 tda998x_reset(encoder); 1169 1170 /* read version: */ 1171 priv->rev = reg_read(encoder, REG_VERSION_LSB) | 1172 reg_read(encoder, REG_VERSION_MSB) << 8; 1173 1174 /* mask off feature bits: */ 1175 priv->rev &= ~0x30; /* not-hdcp and not-scalar bit */ 1176 1177 switch (priv->rev) { 1178 case TDA9989N2: dev_info(dev->dev, "found TDA9989 n2"); break; 1179 case TDA19989: dev_info(dev->dev, "found TDA19989"); break; 1180 case TDA19989N2: dev_info(dev->dev, "found TDA19989 n2"); break; 1181 case TDA19988: dev_info(dev->dev, "found TDA19988"); break; 1182 default: 1183 DBG("found unsupported device: %04x", priv->rev); 1184 goto fail; 1185 } 1186 1187 /* after reset, enable DDC: */ 1188 reg_write(encoder, REG_DDC_DISABLE, 0x00); 1189 1190 /* set clock on DDC channel: */ 1191 reg_write(encoder, REG_TX3, 39); 1192 1193 /* if necessary, disable multi-master: */ 1194 if (priv->rev == TDA19989) 1195 reg_set(encoder, REG_I2C_MASTER, I2C_MASTER_DIS_MM); 1196 1197 cec_write(encoder, REG_CEC_FRO_IM_CLK_CTRL, 1198 CEC_FRO_IM_CLK_CTRL_GHOST_DIS | CEC_FRO_IM_CLK_CTRL_IMCLK_SEL); 1199 1200 return 0; 1201 1202fail: 1203 /* if encoder_init fails, the encoder slave is never registered, 1204 * so cleanup here: 1205 */ 1206 if (priv->cec) 1207 i2c_unregister_device(priv->cec); 1208 kfree(priv); 1209 encoder_slave->slave_priv = NULL; 1210 encoder_slave->slave_funcs = NULL; 1211 return -ENXIO; 1212} 1213 1214static struct i2c_device_id tda998x_ids[] = { 1215 { "tda998x", 0 }, 1216 { } 1217}; 1218MODULE_DEVICE_TABLE(i2c, tda998x_ids); 1219 1220static struct drm_i2c_encoder_driver tda998x_driver = { 1221 .i2c_driver = { 1222 .probe = tda998x_probe, 1223 .remove = tda998x_remove, 1224 .driver = { 1225 .name = "tda998x", 1226 }, 1227 .id_table = tda998x_ids, 1228 }, 1229 .encoder_init = tda998x_encoder_init, 1230}; 1231 1232/* Module initialization */ 1233 1234static int __init 1235tda998x_init(void) 1236{ 1237 DBG(""); 1238 return drm_i2c_encoder_register(THIS_MODULE, &tda998x_driver); 1239} 1240 1241static void __exit 1242tda998x_exit(void) 1243{ 1244 DBG(""); 1245 drm_i2c_encoder_unregister(&tda998x_driver); 1246} 1247 1248MODULE_AUTHOR("Rob Clark <robdclark@gmail.com"); 1249MODULE_DESCRIPTION("NXP Semiconductors TDA998X HDMI Encoder"); 1250MODULE_LICENSE("GPL"); 1251 1252module_init(tda998x_init); 1253module_exit(tda998x_exit); 1254