1/* Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. 2 * All Rights Reserved. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the 6 * "Software"), to deal in the Software without restriction, including 7 * without limitation the rights to use, copy, modify, merge, publish, 8 * distribute, sub license, and/or sell copies of the Software, and to 9 * permit persons to whom the Software is furnished to do so, subject to 10 * the following conditions: 11 * 12 * The above copyright notice and this permission notice (including the 13 * next paragraph) shall be included in all copies or substantial portions 14 * of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 17 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 18 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. 19 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR 20 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 21 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 22 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 23 */ 24 25#ifndef _I915_REG_H_ 26#define _I915_REG_H_ 27 28#define _PIPE(pipe, a, b) ((a) + (pipe)*((b)-(a))) 29#define _TRANSCODER(tran, a, b) ((a) + (tran)*((b)-(a))) 30 31#define _PORT(port, a, b) ((a) + (port)*((b)-(a))) 32#define _PIPE3(pipe, a, b, c) ((pipe) == PIPE_A ? (a) : \ 33 (pipe) == PIPE_B ? (b) : (c)) 34 35#define _MASKED_BIT_ENABLE(a) (((a) << 16) | (a)) 36#define _MASKED_BIT_DISABLE(a) ((a) << 16) 37 38/* PCI config space */ 39 40#define HPLLCC 0xc0 /* 855 only */ 41#define GC_CLOCK_CONTROL_MASK (0xf << 0) 42#define GC_CLOCK_133_200 (0 << 0) 43#define GC_CLOCK_100_200 (1 << 0) 44#define GC_CLOCK_100_133 (2 << 0) 45#define GC_CLOCK_166_250 (3 << 0) 46#define GCFGC2 0xda 47#define GCFGC 0xf0 /* 915+ only */ 48#define GC_LOW_FREQUENCY_ENABLE (1 << 7) 49#define GC_DISPLAY_CLOCK_190_200_MHZ (0 << 4) 50#define GC_DISPLAY_CLOCK_333_MHZ (4 << 4) 51#define GC_DISPLAY_CLOCK_267_MHZ_PNV (0 << 4) 52#define GC_DISPLAY_CLOCK_333_MHZ_PNV (1 << 4) 53#define GC_DISPLAY_CLOCK_444_MHZ_PNV (2 << 4) 54#define GC_DISPLAY_CLOCK_200_MHZ_PNV (5 << 4) 55#define GC_DISPLAY_CLOCK_133_MHZ_PNV (6 << 4) 56#define GC_DISPLAY_CLOCK_167_MHZ_PNV (7 << 4) 57#define GC_DISPLAY_CLOCK_MASK (7 << 4) 58#define GM45_GC_RENDER_CLOCK_MASK (0xf << 0) 59#define GM45_GC_RENDER_CLOCK_266_MHZ (8 << 0) 60#define GM45_GC_RENDER_CLOCK_320_MHZ (9 << 0) 61#define GM45_GC_RENDER_CLOCK_400_MHZ (0xb << 0) 62#define GM45_GC_RENDER_CLOCK_533_MHZ (0xc << 0) 63#define I965_GC_RENDER_CLOCK_MASK (0xf << 0) 64#define I965_GC_RENDER_CLOCK_267_MHZ (2 << 0) 65#define I965_GC_RENDER_CLOCK_333_MHZ (3 << 0) 66#define I965_GC_RENDER_CLOCK_444_MHZ (4 << 0) 67#define I965_GC_RENDER_CLOCK_533_MHZ (5 << 0) 68#define I945_GC_RENDER_CLOCK_MASK (7 << 0) 69#define I945_GC_RENDER_CLOCK_166_MHZ (0 << 0) 70#define I945_GC_RENDER_CLOCK_200_MHZ (1 << 0) 71#define I945_GC_RENDER_CLOCK_250_MHZ (3 << 0) 72#define I945_GC_RENDER_CLOCK_400_MHZ (5 << 0) 73#define I915_GC_RENDER_CLOCK_MASK (7 << 0) 74#define I915_GC_RENDER_CLOCK_166_MHZ (0 << 0) 75#define I915_GC_RENDER_CLOCK_200_MHZ (1 << 0) 76#define I915_GC_RENDER_CLOCK_333_MHZ (4 << 0) 77#define PCI_LBPC 0xf4 /* legacy/combination backlight modes, also called LBB */ 78 79 80/* Graphics reset regs */ 81#define I965_GDRST 0xc0 /* PCI config register */ 82#define GRDOM_FULL (0<<2) 83#define GRDOM_RENDER (1<<2) 84#define GRDOM_MEDIA (3<<2) 85#define GRDOM_MASK (3<<2) 86#define GRDOM_RESET_ENABLE (1<<0) 87 88#define ILK_GDSR 0x2ca4 /* MCHBAR offset */ 89#define ILK_GRDOM_FULL (0<<1) 90#define ILK_GRDOM_RENDER (1<<1) 91#define ILK_GRDOM_MEDIA (3<<1) 92#define ILK_GRDOM_MASK (3<<1) 93#define ILK_GRDOM_RESET_ENABLE (1<<0) 94 95#define GEN6_MBCUNIT_SNPCR 0x900c /* for LLC config */ 96#define GEN6_MBC_SNPCR_SHIFT 21 97#define GEN6_MBC_SNPCR_MASK (3<<21) 98#define GEN6_MBC_SNPCR_MAX (0<<21) 99#define GEN6_MBC_SNPCR_MED (1<<21) 100#define GEN6_MBC_SNPCR_LOW (2<<21) 101#define GEN6_MBC_SNPCR_MIN (3<<21) /* only 1/16th of the cache is shared */ 102 103#define VLV_G3DCTL 0x9024 104#define VLV_GSCKGCTL 0x9028 105 106#define GEN6_MBCTL 0x0907c 107#define GEN6_MBCTL_ENABLE_BOOT_FETCH (1 << 4) 108#define GEN6_MBCTL_CTX_FETCH_NEEDED (1 << 3) 109#define GEN6_MBCTL_BME_UPDATE_ENABLE (1 << 2) 110#define GEN6_MBCTL_MAE_UPDATE_ENABLE (1 << 1) 111#define GEN6_MBCTL_BOOT_FETCH_MECH (1 << 0) 112 113#define GEN6_GDRST 0x941c 114#define GEN6_GRDOM_FULL (1 << 0) 115#define GEN6_GRDOM_RENDER (1 << 1) 116#define GEN6_GRDOM_MEDIA (1 << 2) 117#define GEN6_GRDOM_BLT (1 << 3) 118 119#define RING_PP_DIR_BASE(ring) ((ring)->mmio_base+0x228) 120#define RING_PP_DIR_BASE_READ(ring) ((ring)->mmio_base+0x518) 121#define RING_PP_DIR_DCLV(ring) ((ring)->mmio_base+0x220) 122#define PP_DIR_DCLV_2G 0xffffffff 123 124#define GEN8_RING_PDP_UDW(ring, n) ((ring)->mmio_base+0x270 + ((n) * 8 + 4)) 125#define GEN8_RING_PDP_LDW(ring, n) ((ring)->mmio_base+0x270 + (n) * 8) 126 127#define GAM_ECOCHK 0x4090 128#define ECOCHK_SNB_BIT (1<<10) 129#define HSW_ECOCHK_ARB_PRIO_SOL (1<<6) 130#define ECOCHK_PPGTT_CACHE64B (0x3<<3) 131#define ECOCHK_PPGTT_CACHE4B (0x0<<3) 132#define ECOCHK_PPGTT_GFDT_IVB (0x1<<4) 133#define ECOCHK_PPGTT_LLC_IVB (0x1<<3) 134#define ECOCHK_PPGTT_UC_HSW (0x1<<3) 135#define ECOCHK_PPGTT_WT_HSW (0x2<<3) 136#define ECOCHK_PPGTT_WB_HSW (0x3<<3) 137 138#define GAC_ECO_BITS 0x14090 139#define ECOBITS_SNB_BIT (1<<13) 140#define ECOBITS_PPGTT_CACHE64B (3<<8) 141#define ECOBITS_PPGTT_CACHE4B (0<<8) 142 143#define GAB_CTL 0x24000 144#define GAB_CTL_CONT_AFTER_PAGEFAULT (1<<8) 145 146#define GEN7_BIOS_RESERVED 0x1082C0 147#define GEN7_BIOS_RESERVED_1M (0 << 5) 148#define GEN7_BIOS_RESERVED_256K (1 << 5) 149#define GEN8_BIOS_RESERVED_SHIFT 7 150#define GEN7_BIOS_RESERVED_MASK 0x1 151#define GEN8_BIOS_RESERVED_MASK 0x3 152 153 154/* VGA stuff */ 155 156#define VGA_ST01_MDA 0x3ba 157#define VGA_ST01_CGA 0x3da 158 159#define VGA_MSR_WRITE 0x3c2 160#define VGA_MSR_READ 0x3cc 161#define VGA_MSR_MEM_EN (1<<1) 162#define VGA_MSR_CGA_MODE (1<<0) 163 164#define VGA_SR_INDEX 0x3c4 165#define SR01 1 166#define VGA_SR_DATA 0x3c5 167 168#define VGA_AR_INDEX 0x3c0 169#define VGA_AR_VID_EN (1<<5) 170#define VGA_AR_DATA_WRITE 0x3c0 171#define VGA_AR_DATA_READ 0x3c1 172 173#define VGA_GR_INDEX 0x3ce 174#define VGA_GR_DATA 0x3cf 175/* GR05 */ 176#define VGA_GR_MEM_READ_MODE_SHIFT 3 177#define VGA_GR_MEM_READ_MODE_PLANE 1 178/* GR06 */ 179#define VGA_GR_MEM_MODE_MASK 0xc 180#define VGA_GR_MEM_MODE_SHIFT 2 181#define VGA_GR_MEM_A0000_AFFFF 0 182#define VGA_GR_MEM_A0000_BFFFF 1 183#define VGA_GR_MEM_B0000_B7FFF 2 184#define VGA_GR_MEM_B0000_BFFFF 3 185 186#define VGA_DACMASK 0x3c6 187#define VGA_DACRX 0x3c7 188#define VGA_DACWX 0x3c8 189#define VGA_DACDATA 0x3c9 190 191#define VGA_CR_INDEX_MDA 0x3b4 192#define VGA_CR_DATA_MDA 0x3b5 193#define VGA_CR_INDEX_CGA 0x3d4 194#define VGA_CR_DATA_CGA 0x3d5 195 196/* 197 * Instruction field definitions used by the command parser 198 */ 199#define INSTR_CLIENT_SHIFT 29 200#define INSTR_CLIENT_MASK 0xE0000000 201#define INSTR_MI_CLIENT 0x0 202#define INSTR_BC_CLIENT 0x2 203#define INSTR_RC_CLIENT 0x3 204#define INSTR_SUBCLIENT_SHIFT 27 205#define INSTR_SUBCLIENT_MASK 0x18000000 206#define INSTR_MEDIA_SUBCLIENT 0x2 207 208/* 209 * Memory interface instructions used by the kernel 210 */ 211#define MI_INSTR(opcode, flags) (((opcode) << 23) | (flags)) 212/* Many MI commands use bit 22 of the header dword for GGTT vs PPGTT */ 213#define MI_GLOBAL_GTT (1<<22) 214 215#define MI_NOOP MI_INSTR(0, 0) 216#define MI_USER_INTERRUPT MI_INSTR(0x02, 0) 217#define MI_WAIT_FOR_EVENT MI_INSTR(0x03, 0) 218#define MI_WAIT_FOR_OVERLAY_FLIP (1<<16) 219#define MI_WAIT_FOR_PLANE_B_FLIP (1<<6) 220#define MI_WAIT_FOR_PLANE_A_FLIP (1<<2) 221#define MI_WAIT_FOR_PLANE_A_SCANLINES (1<<1) 222#define MI_FLUSH MI_INSTR(0x04, 0) 223#define MI_READ_FLUSH (1 << 0) 224#define MI_EXE_FLUSH (1 << 1) 225#define MI_NO_WRITE_FLUSH (1 << 2) 226#define MI_SCENE_COUNT (1 << 3) /* just increment scene count */ 227#define MI_END_SCENE (1 << 4) /* flush binner and incr scene count */ 228#define MI_INVALIDATE_ISP (1 << 5) /* invalidate indirect state pointers */ 229#define MI_REPORT_HEAD MI_INSTR(0x07, 0) 230#define MI_ARB_ON_OFF MI_INSTR(0x08, 0) 231#define MI_ARB_ENABLE (1<<0) 232#define MI_ARB_DISABLE (0<<0) 233#define MI_BATCH_BUFFER_END MI_INSTR(0x0a, 0) 234#define MI_SUSPEND_FLUSH MI_INSTR(0x0b, 0) 235#define MI_SUSPEND_FLUSH_EN (1<<0) 236#define MI_OVERLAY_FLIP MI_INSTR(0x11, 0) 237#define MI_OVERLAY_CONTINUE (0x0<<21) 238#define MI_OVERLAY_ON (0x1<<21) 239#define MI_OVERLAY_OFF (0x2<<21) 240#define MI_LOAD_SCAN_LINES_INCL MI_INSTR(0x12, 0) 241#define MI_DISPLAY_FLIP MI_INSTR(0x14, 2) 242#define MI_DISPLAY_FLIP_I915 MI_INSTR(0x14, 1) 243#define MI_DISPLAY_FLIP_PLANE(n) ((n) << 20) 244/* IVB has funny definitions for which plane to flip. */ 245#define MI_DISPLAY_FLIP_IVB_PLANE_A (0 << 19) 246#define MI_DISPLAY_FLIP_IVB_PLANE_B (1 << 19) 247#define MI_DISPLAY_FLIP_IVB_SPRITE_A (2 << 19) 248#define MI_DISPLAY_FLIP_IVB_SPRITE_B (3 << 19) 249#define MI_DISPLAY_FLIP_IVB_PLANE_C (4 << 19) 250#define MI_DISPLAY_FLIP_IVB_SPRITE_C (5 << 19) 251#define MI_SEMAPHORE_MBOX MI_INSTR(0x16, 1) /* gen6, gen7 */ 252#define MI_SEMAPHORE_GLOBAL_GTT (1<<22) 253#define MI_SEMAPHORE_UPDATE (1<<21) 254#define MI_SEMAPHORE_COMPARE (1<<20) 255#define MI_SEMAPHORE_REGISTER (1<<18) 256#define MI_SEMAPHORE_SYNC_VR (0<<16) /* RCS wait for VCS (RVSYNC) */ 257#define MI_SEMAPHORE_SYNC_VER (1<<16) /* RCS wait for VECS (RVESYNC) */ 258#define MI_SEMAPHORE_SYNC_BR (2<<16) /* RCS wait for BCS (RBSYNC) */ 259#define MI_SEMAPHORE_SYNC_BV (0<<16) /* VCS wait for BCS (VBSYNC) */ 260#define MI_SEMAPHORE_SYNC_VEV (1<<16) /* VCS wait for VECS (VVESYNC) */ 261#define MI_SEMAPHORE_SYNC_RV (2<<16) /* VCS wait for RCS (VRSYNC) */ 262#define MI_SEMAPHORE_SYNC_RB (0<<16) /* BCS wait for RCS (BRSYNC) */ 263#define MI_SEMAPHORE_SYNC_VEB (1<<16) /* BCS wait for VECS (BVESYNC) */ 264#define MI_SEMAPHORE_SYNC_VB (2<<16) /* BCS wait for VCS (BVSYNC) */ 265#define MI_SEMAPHORE_SYNC_BVE (0<<16) /* VECS wait for BCS (VEBSYNC) */ 266#define MI_SEMAPHORE_SYNC_VVE (1<<16) /* VECS wait for VCS (VEVSYNC) */ 267#define MI_SEMAPHORE_SYNC_RVE (2<<16) /* VECS wait for RCS (VERSYNC) */ 268#define MI_SEMAPHORE_SYNC_INVALID (3<<16) 269#define MI_SEMAPHORE_SYNC_MASK (3<<16) 270#define MI_SET_CONTEXT MI_INSTR(0x18, 0) 271#define MI_MM_SPACE_GTT (1<<8) 272#define MI_MM_SPACE_PHYSICAL (0<<8) 273#define MI_SAVE_EXT_STATE_EN (1<<3) 274#define MI_RESTORE_EXT_STATE_EN (1<<2) 275#define MI_FORCE_RESTORE (1<<1) 276#define MI_RESTORE_INHIBIT (1<<0) 277#define MI_SEMAPHORE_SIGNAL MI_INSTR(0x1b, 0) /* GEN8+ */ 278#define MI_SEMAPHORE_TARGET(engine) ((engine)<<15) 279#define MI_SEMAPHORE_WAIT MI_INSTR(0x1c, 2) /* GEN8+ */ 280#define MI_SEMAPHORE_POLL (1<<15) 281#define MI_SEMAPHORE_SAD_GTE_SDD (1<<12) 282#define MI_STORE_DWORD_IMM MI_INSTR(0x20, 1) 283#define MI_STORE_DWORD_IMM_GEN8 MI_INSTR(0x20, 2) 284#define MI_MEM_VIRTUAL (1 << 22) /* 965+ only */ 285#define MI_STORE_DWORD_INDEX MI_INSTR(0x21, 1) 286#define MI_STORE_DWORD_INDEX_SHIFT 2 287/* Official intel docs are somewhat sloppy concerning MI_LOAD_REGISTER_IMM: 288 * - Always issue a MI_NOOP _before_ the MI_LOAD_REGISTER_IMM - otherwise hw 289 * simply ignores the register load under certain conditions. 290 * - One can actually load arbitrary many arbitrary registers: Simply issue x 291 * address/value pairs. Don't overdue it, though, x <= 2^4 must hold! 292 */ 293#define MI_LOAD_REGISTER_IMM(x) MI_INSTR(0x22, 2*(x)-1) 294#define MI_LRI_FORCE_POSTED (1<<12) 295#define MI_STORE_REGISTER_MEM(x) MI_INSTR(0x24, 2*(x)-1) 296#define MI_STORE_REGISTER_MEM_GEN8(x) MI_INSTR(0x24, 3*(x)-1) 297#define MI_SRM_LRM_GLOBAL_GTT (1<<22) 298#define MI_FLUSH_DW MI_INSTR(0x26, 1) /* for GEN6 */ 299#define MI_FLUSH_DW_STORE_INDEX (1<<21) 300#define MI_INVALIDATE_TLB (1<<18) 301#define MI_FLUSH_DW_OP_STOREDW (1<<14) 302#define MI_FLUSH_DW_OP_MASK (3<<14) 303#define MI_FLUSH_DW_NOTIFY (1<<8) 304#define MI_INVALIDATE_BSD (1<<7) 305#define MI_FLUSH_DW_USE_GTT (1<<2) 306#define MI_FLUSH_DW_USE_PPGTT (0<<2) 307#define MI_BATCH_BUFFER MI_INSTR(0x30, 1) 308#define MI_BATCH_NON_SECURE (1) 309/* for snb/ivb/vlv this also means "batch in ppgtt" when ppgtt is enabled. */ 310#define MI_BATCH_NON_SECURE_I965 (1<<8) 311#define MI_BATCH_PPGTT_HSW (1<<8) 312#define MI_BATCH_NON_SECURE_HSW (1<<13) 313#define MI_BATCH_BUFFER_START MI_INSTR(0x31, 0) 314#define MI_BATCH_GTT (2<<6) /* aliased with (1<<7) on gen4 */ 315#define MI_BATCH_BUFFER_START_GEN8 MI_INSTR(0x31, 1) 316 317 318#define MI_PREDICATE_RESULT_2 (0x2214) 319#define LOWER_SLICE_ENABLED (1<<0) 320#define LOWER_SLICE_DISABLED (0<<0) 321 322/* 323 * 3D instructions used by the kernel 324 */ 325#define GFX_INSTR(opcode, flags) ((0x3 << 29) | ((opcode) << 24) | (flags)) 326 327#define GFX_OP_RASTER_RULES ((0x3<<29)|(0x7<<24)) 328#define GFX_OP_SCISSOR ((0x3<<29)|(0x1c<<24)|(0x10<<19)) 329#define SC_UPDATE_SCISSOR (0x1<<1) 330#define SC_ENABLE_MASK (0x1<<0) 331#define SC_ENABLE (0x1<<0) 332#define GFX_OP_LOAD_INDIRECT ((0x3<<29)|(0x1d<<24)|(0x7<<16)) 333#define GFX_OP_SCISSOR_INFO ((0x3<<29)|(0x1d<<24)|(0x81<<16)|(0x1)) 334#define SCI_YMIN_MASK (0xffff<<16) 335#define SCI_XMIN_MASK (0xffff<<0) 336#define SCI_YMAX_MASK (0xffff<<16) 337#define SCI_XMAX_MASK (0xffff<<0) 338#define GFX_OP_SCISSOR_ENABLE ((0x3<<29)|(0x1c<<24)|(0x10<<19)) 339#define GFX_OP_SCISSOR_RECT ((0x3<<29)|(0x1d<<24)|(0x81<<16)|1) 340#define GFX_OP_COLOR_FACTOR ((0x3<<29)|(0x1d<<24)|(0x1<<16)|0x0) 341#define GFX_OP_STIPPLE ((0x3<<29)|(0x1d<<24)|(0x83<<16)) 342#define GFX_OP_MAP_INFO ((0x3<<29)|(0x1d<<24)|0x4) 343#define GFX_OP_DESTBUFFER_VARS ((0x3<<29)|(0x1d<<24)|(0x85<<16)|0x0) 344#define GFX_OP_DESTBUFFER_INFO ((0x3<<29)|(0x1d<<24)|(0x8e<<16)|1) 345#define GFX_OP_DRAWRECT_INFO ((0x3<<29)|(0x1d<<24)|(0x80<<16)|(0x3)) 346#define GFX_OP_DRAWRECT_INFO_I965 ((0x7900<<16)|0x2) 347 348#define COLOR_BLT_CMD (2<<29 | 0x40<<22 | (5-2)) 349#define SRC_COPY_BLT_CMD ((2<<29)|(0x43<<22)|4) 350#define XY_SRC_COPY_BLT_CMD ((2<<29)|(0x53<<22)|6) 351#define XY_MONO_SRC_COPY_IMM_BLT ((2<<29)|(0x71<<22)|5) 352#define BLT_WRITE_A (2<<20) 353#define BLT_WRITE_RGB (1<<20) 354#define BLT_WRITE_RGBA (BLT_WRITE_RGB | BLT_WRITE_A) 355#define BLT_DEPTH_8 (0<<24) 356#define BLT_DEPTH_16_565 (1<<24) 357#define BLT_DEPTH_16_1555 (2<<24) 358#define BLT_DEPTH_32 (3<<24) 359#define BLT_ROP_SRC_COPY (0xcc<<16) 360#define BLT_ROP_COLOR_COPY (0xf0<<16) 361#define XY_SRC_COPY_BLT_SRC_TILED (1<<15) /* 965+ only */ 362#define XY_SRC_COPY_BLT_DST_TILED (1<<11) /* 965+ only */ 363#define CMD_OP_DISPLAYBUFFER_INFO ((0x0<<29)|(0x14<<23)|2) 364#define ASYNC_FLIP (1<<22) 365#define DISPLAY_PLANE_A (0<<20) 366#define DISPLAY_PLANE_B (1<<20) 367#define GFX_OP_PIPE_CONTROL(len) ((0x3<<29)|(0x3<<27)|(0x2<<24)|(len-2)) 368#define PIPE_CONTROL_GLOBAL_GTT_IVB (1<<24) /* gen7+ */ 369#define PIPE_CONTROL_MMIO_WRITE (1<<23) 370#define PIPE_CONTROL_STORE_DATA_INDEX (1<<21) 371#define PIPE_CONTROL_CS_STALL (1<<20) 372#define PIPE_CONTROL_TLB_INVALIDATE (1<<18) 373#define PIPE_CONTROL_QW_WRITE (1<<14) 374#define PIPE_CONTROL_POST_SYNC_OP_MASK (3<<14) 375#define PIPE_CONTROL_DEPTH_STALL (1<<13) 376#define PIPE_CONTROL_WRITE_FLUSH (1<<12) 377#define PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH (1<<12) /* gen6+ */ 378#define PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE (1<<11) /* MBZ on Ironlake */ 379#define PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE (1<<10) /* GM45+ only */ 380#define PIPE_CONTROL_INDIRECT_STATE_DISABLE (1<<9) 381#define PIPE_CONTROL_NOTIFY (1<<8) 382#define PIPE_CONTROL_FLUSH_ENABLE (1<<7) /* gen7+ */ 383#define PIPE_CONTROL_VF_CACHE_INVALIDATE (1<<4) 384#define PIPE_CONTROL_CONST_CACHE_INVALIDATE (1<<3) 385#define PIPE_CONTROL_STATE_CACHE_INVALIDATE (1<<2) 386#define PIPE_CONTROL_STALL_AT_SCOREBOARD (1<<1) 387#define PIPE_CONTROL_DEPTH_CACHE_FLUSH (1<<0) 388#define PIPE_CONTROL_GLOBAL_GTT (1<<2) /* in addr dword */ 389 390/* 391 * Commands used only by the command parser 392 */ 393#define MI_SET_PREDICATE MI_INSTR(0x01, 0) 394#define MI_ARB_CHECK MI_INSTR(0x05, 0) 395#define MI_RS_CONTROL MI_INSTR(0x06, 0) 396#define MI_URB_ATOMIC_ALLOC MI_INSTR(0x09, 0) 397#define MI_PREDICATE MI_INSTR(0x0C, 0) 398#define MI_RS_CONTEXT MI_INSTR(0x0F, 0) 399#define MI_TOPOLOGY_FILTER MI_INSTR(0x0D, 0) 400#define MI_LOAD_SCAN_LINES_EXCL MI_INSTR(0x13, 0) 401#define MI_URB_CLEAR MI_INSTR(0x19, 0) 402#define MI_UPDATE_GTT MI_INSTR(0x23, 0) 403#define MI_CLFLUSH MI_INSTR(0x27, 0) 404#define MI_REPORT_PERF_COUNT MI_INSTR(0x28, 0) 405#define MI_REPORT_PERF_COUNT_GGTT (1<<0) 406#define MI_LOAD_REGISTER_MEM MI_INSTR(0x29, 0) 407#define MI_LOAD_REGISTER_REG MI_INSTR(0x2A, 0) 408#define MI_RS_STORE_DATA_IMM MI_INSTR(0x2B, 0) 409#define MI_LOAD_URB_MEM MI_INSTR(0x2C, 0) 410#define MI_STORE_URB_MEM MI_INSTR(0x2D, 0) 411#define MI_CONDITIONAL_BATCH_BUFFER_END MI_INSTR(0x36, 0) 412 413#define PIPELINE_SELECT ((0x3<<29)|(0x1<<27)|(0x1<<24)|(0x4<<16)) 414#define GFX_OP_3DSTATE_VF_STATISTICS ((0x3<<29)|(0x1<<27)|(0x0<<24)|(0xB<<16)) 415#define MEDIA_VFE_STATE ((0x3<<29)|(0x2<<27)|(0x0<<24)|(0x0<<16)) 416#define MEDIA_VFE_STATE_MMIO_ACCESS_MASK (0x18) 417#define GPGPU_OBJECT ((0x3<<29)|(0x2<<27)|(0x1<<24)|(0x4<<16)) 418#define GPGPU_WALKER ((0x3<<29)|(0x2<<27)|(0x1<<24)|(0x5<<16)) 419#define GFX_OP_3DSTATE_DX9_CONSTANTF_VS \ 420 ((0x3<<29)|(0x3<<27)|(0x0<<24)|(0x39<<16)) 421#define GFX_OP_3DSTATE_DX9_CONSTANTF_PS \ 422 ((0x3<<29)|(0x3<<27)|(0x0<<24)|(0x3A<<16)) 423#define GFX_OP_3DSTATE_SO_DECL_LIST \ 424 ((0x3<<29)|(0x3<<27)|(0x1<<24)|(0x17<<16)) 425 426#define GFX_OP_3DSTATE_BINDING_TABLE_EDIT_VS \ 427 ((0x3<<29)|(0x3<<27)|(0x0<<24)|(0x43<<16)) 428#define GFX_OP_3DSTATE_BINDING_TABLE_EDIT_GS \ 429 ((0x3<<29)|(0x3<<27)|(0x0<<24)|(0x44<<16)) 430#define GFX_OP_3DSTATE_BINDING_TABLE_EDIT_HS \ 431 ((0x3<<29)|(0x3<<27)|(0x0<<24)|(0x45<<16)) 432#define GFX_OP_3DSTATE_BINDING_TABLE_EDIT_DS \ 433 ((0x3<<29)|(0x3<<27)|(0x0<<24)|(0x46<<16)) 434#define GFX_OP_3DSTATE_BINDING_TABLE_EDIT_PS \ 435 ((0x3<<29)|(0x3<<27)|(0x0<<24)|(0x47<<16)) 436 437#define MFX_WAIT ((0x3<<29)|(0x1<<27)|(0x0<<16)) 438 439#define COLOR_BLT ((0x2<<29)|(0x40<<22)) 440#define SRC_COPY_BLT ((0x2<<29)|(0x43<<22)) 441 442/* 443 * Registers used only by the command parser 444 */ 445#define BCS_SWCTRL 0x22200 446 447#define HS_INVOCATION_COUNT 0x2300 448#define DS_INVOCATION_COUNT 0x2308 449#define IA_VERTICES_COUNT 0x2310 450#define IA_PRIMITIVES_COUNT 0x2318 451#define VS_INVOCATION_COUNT 0x2320 452#define GS_INVOCATION_COUNT 0x2328 453#define GS_PRIMITIVES_COUNT 0x2330 454#define CL_INVOCATION_COUNT 0x2338 455#define CL_PRIMITIVES_COUNT 0x2340 456#define PS_INVOCATION_COUNT 0x2348 457#define PS_DEPTH_COUNT 0x2350 458 459/* There are the 4 64-bit counter registers, one for each stream output */ 460#define GEN7_SO_NUM_PRIMS_WRITTEN(n) (0x5200 + (n) * 8) 461 462#define GEN7_SO_PRIM_STORAGE_NEEDED(n) (0x5240 + (n) * 8) 463 464#define GEN7_3DPRIM_END_OFFSET 0x2420 465#define GEN7_3DPRIM_START_VERTEX 0x2430 466#define GEN7_3DPRIM_VERTEX_COUNT 0x2434 467#define GEN7_3DPRIM_INSTANCE_COUNT 0x2438 468#define GEN7_3DPRIM_START_INSTANCE 0x243C 469#define GEN7_3DPRIM_BASE_VERTEX 0x2440 470 471#define OACONTROL 0x2360 472 473#define _GEN7_PIPEA_DE_LOAD_SL 0x70068 474#define _GEN7_PIPEB_DE_LOAD_SL 0x71068 475#define GEN7_PIPE_DE_LOAD_SL(pipe) _PIPE(pipe, \ 476 _GEN7_PIPEA_DE_LOAD_SL, \ 477 _GEN7_PIPEB_DE_LOAD_SL) 478 479/* 480 * Reset registers 481 */ 482#define DEBUG_RESET_I830 0x6070 483#define DEBUG_RESET_FULL (1<<7) 484#define DEBUG_RESET_RENDER (1<<8) 485#define DEBUG_RESET_DISPLAY (1<<9) 486 487/* 488 * IOSF sideband 489 */ 490#define VLV_IOSF_DOORBELL_REQ (VLV_DISPLAY_BASE + 0x2100) 491#define IOSF_DEVFN_SHIFT 24 492#define IOSF_OPCODE_SHIFT 16 493#define IOSF_PORT_SHIFT 8 494#define IOSF_BYTE_ENABLES_SHIFT 4 495#define IOSF_BAR_SHIFT 1 496#define IOSF_SB_BUSY (1<<0) 497#define IOSF_PORT_BUNIT 0x3 498#define IOSF_PORT_PUNIT 0x4 499#define IOSF_PORT_NC 0x11 500#define IOSF_PORT_DPIO 0x12 501#define IOSF_PORT_DPIO_2 0x1a 502#define IOSF_PORT_GPIO_NC 0x13 503#define IOSF_PORT_CCK 0x14 504#define IOSF_PORT_CCU 0xA9 505#define IOSF_PORT_GPS_CORE 0x48 506#define IOSF_PORT_FLISDSI 0x1B 507#define VLV_IOSF_DATA (VLV_DISPLAY_BASE + 0x2104) 508#define VLV_IOSF_ADDR (VLV_DISPLAY_BASE + 0x2108) 509 510/* See configdb bunit SB addr map */ 511#define BUNIT_REG_BISOC 0x11 512 513#define PUNIT_REG_DSPFREQ 0x36 514#define DSPFREQSTAT_SHIFT_CHV 24 515#define DSPFREQSTAT_MASK_CHV (0x1f << DSPFREQSTAT_SHIFT_CHV) 516#define DSPFREQGUAR_SHIFT_CHV 8 517#define DSPFREQGUAR_MASK_CHV (0x1f << DSPFREQGUAR_SHIFT_CHV) 518#define DSPFREQSTAT_SHIFT 30 519#define DSPFREQSTAT_MASK (0x3 << DSPFREQSTAT_SHIFT) 520#define DSPFREQGUAR_SHIFT 14 521#define DSPFREQGUAR_MASK (0x3 << DSPFREQGUAR_SHIFT) 522#define _DP_SSC(val, pipe) ((val) << (2 * (pipe))) 523#define DP_SSC_MASK(pipe) _DP_SSC(0x3, (pipe)) 524#define DP_SSC_PWR_ON(pipe) _DP_SSC(0x0, (pipe)) 525#define DP_SSC_CLK_GATE(pipe) _DP_SSC(0x1, (pipe)) 526#define DP_SSC_RESET(pipe) _DP_SSC(0x2, (pipe)) 527#define DP_SSC_PWR_GATE(pipe) _DP_SSC(0x3, (pipe)) 528#define _DP_SSS(val, pipe) ((val) << (2 * (pipe) + 16)) 529#define DP_SSS_MASK(pipe) _DP_SSS(0x3, (pipe)) 530#define DP_SSS_PWR_ON(pipe) _DP_SSS(0x0, (pipe)) 531#define DP_SSS_CLK_GATE(pipe) _DP_SSS(0x1, (pipe)) 532#define DP_SSS_RESET(pipe) _DP_SSS(0x2, (pipe)) 533#define DP_SSS_PWR_GATE(pipe) _DP_SSS(0x3, (pipe)) 534 535/* See the PUNIT HAS v0.8 for the below bits */ 536enum punit_power_well { 537 PUNIT_POWER_WELL_RENDER = 0, 538 PUNIT_POWER_WELL_MEDIA = 1, 539 PUNIT_POWER_WELL_DISP2D = 3, 540 PUNIT_POWER_WELL_DPIO_CMN_BC = 5, 541 PUNIT_POWER_WELL_DPIO_TX_B_LANES_01 = 6, 542 PUNIT_POWER_WELL_DPIO_TX_B_LANES_23 = 7, 543 PUNIT_POWER_WELL_DPIO_TX_C_LANES_01 = 8, 544 PUNIT_POWER_WELL_DPIO_TX_C_LANES_23 = 9, 545 PUNIT_POWER_WELL_DPIO_RX0 = 10, 546 PUNIT_POWER_WELL_DPIO_RX1 = 11, 547 PUNIT_POWER_WELL_DPIO_CMN_D = 12, 548 /* FIXME: guesswork below */ 549 PUNIT_POWER_WELL_DPIO_TX_D_LANES_01 = 13, 550 PUNIT_POWER_WELL_DPIO_TX_D_LANES_23 = 14, 551 PUNIT_POWER_WELL_DPIO_RX2 = 15, 552 553 PUNIT_POWER_WELL_NUM, 554}; 555 556#define PUNIT_REG_PWRGT_CTRL 0x60 557#define PUNIT_REG_PWRGT_STATUS 0x61 558#define PUNIT_PWRGT_MASK(power_well) (3 << ((power_well) * 2)) 559#define PUNIT_PWRGT_PWR_ON(power_well) (0 << ((power_well) * 2)) 560#define PUNIT_PWRGT_CLK_GATE(power_well) (1 << ((power_well) * 2)) 561#define PUNIT_PWRGT_RESET(power_well) (2 << ((power_well) * 2)) 562#define PUNIT_PWRGT_PWR_GATE(power_well) (3 << ((power_well) * 2)) 563 564#define PUNIT_REG_GPU_LFM 0xd3 565#define PUNIT_REG_GPU_FREQ_REQ 0xd4 566#define PUNIT_REG_GPU_FREQ_STS 0xd8 567#define GENFREQSTATUS (1<<0) 568#define PUNIT_REG_MEDIA_TURBO_FREQ_REQ 0xdc 569#define PUNIT_REG_CZ_TIMESTAMP 0xce 570 571#define PUNIT_FUSE_BUS2 0xf6 /* bits 47:40 */ 572#define PUNIT_FUSE_BUS1 0xf5 /* bits 55:48 */ 573 574#define PUNIT_GPU_STATUS_REG 0xdb 575#define PUNIT_GPU_STATUS_MAX_FREQ_SHIFT 16 576#define PUNIT_GPU_STATUS_MAX_FREQ_MASK 0xff 577#define PUNIT_GPU_STATIS_GFX_MIN_FREQ_SHIFT 8 578#define PUNIT_GPU_STATUS_GFX_MIN_FREQ_MASK 0xff 579 580#define PUNIT_GPU_DUTYCYCLE_REG 0xdf 581#define PUNIT_GPU_DUTYCYCLE_RPE_FREQ_SHIFT 8 582#define PUNIT_GPU_DUTYCYCLE_RPE_FREQ_MASK 0xff 583 584#define IOSF_NC_FB_GFX_FREQ_FUSE 0x1c 585#define FB_GFX_MAX_FREQ_FUSE_SHIFT 3 586#define FB_GFX_MAX_FREQ_FUSE_MASK 0x000007f8 587#define FB_GFX_FGUARANTEED_FREQ_FUSE_SHIFT 11 588#define FB_GFX_FGUARANTEED_FREQ_FUSE_MASK 0x0007f800 589#define IOSF_NC_FB_GFX_FMAX_FUSE_HI 0x34 590#define FB_FMAX_VMIN_FREQ_HI_MASK 0x00000007 591#define IOSF_NC_FB_GFX_FMAX_FUSE_LO 0x30 592#define FB_FMAX_VMIN_FREQ_LO_SHIFT 27 593#define FB_FMAX_VMIN_FREQ_LO_MASK 0xf8000000 594 595#define VLV_CZ_CLOCK_TO_MILLI_SEC 100000 596#define VLV_RP_UP_EI_THRESHOLD 90 597#define VLV_RP_DOWN_EI_THRESHOLD 70 598#define VLV_INT_COUNT_FOR_DOWN_EI 5 599 600/* vlv2 north clock has */ 601#define CCK_FUSE_REG 0x8 602#define CCK_FUSE_HPLL_FREQ_MASK 0x3 603#define CCK_REG_DSI_PLL_FUSE 0x44 604#define CCK_REG_DSI_PLL_CONTROL 0x48 605#define DSI_PLL_VCO_EN (1 << 31) 606#define DSI_PLL_LDO_GATE (1 << 30) 607#define DSI_PLL_P1_POST_DIV_SHIFT 17 608#define DSI_PLL_P1_POST_DIV_MASK (0x1ff << 17) 609#define DSI_PLL_P2_MUX_DSI0_DIV2 (1 << 13) 610#define DSI_PLL_P3_MUX_DSI1_DIV2 (1 << 12) 611#define DSI_PLL_MUX_MASK (3 << 9) 612#define DSI_PLL_MUX_DSI0_DSIPLL (0 << 10) 613#define DSI_PLL_MUX_DSI0_CCK (1 << 10) 614#define DSI_PLL_MUX_DSI1_DSIPLL (0 << 9) 615#define DSI_PLL_MUX_DSI1_CCK (1 << 9) 616#define DSI_PLL_CLK_GATE_MASK (0xf << 5) 617#define DSI_PLL_CLK_GATE_DSI0_DSIPLL (1 << 8) 618#define DSI_PLL_CLK_GATE_DSI1_DSIPLL (1 << 7) 619#define DSI_PLL_CLK_GATE_DSI0_CCK (1 << 6) 620#define DSI_PLL_CLK_GATE_DSI1_CCK (1 << 5) 621#define DSI_PLL_LOCK (1 << 0) 622#define CCK_REG_DSI_PLL_DIVIDER 0x4c 623#define DSI_PLL_LFSR (1 << 31) 624#define DSI_PLL_FRACTION_EN (1 << 30) 625#define DSI_PLL_FRAC_COUNTER_SHIFT 27 626#define DSI_PLL_FRAC_COUNTER_MASK (7 << 27) 627#define DSI_PLL_USYNC_CNT_SHIFT 18 628#define DSI_PLL_USYNC_CNT_MASK (0x1ff << 18) 629#define DSI_PLL_N1_DIV_SHIFT 16 630#define DSI_PLL_N1_DIV_MASK (3 << 16) 631#define DSI_PLL_M1_DIV_SHIFT 0 632#define DSI_PLL_M1_DIV_MASK (0x1ff << 0) 633#define CCK_DISPLAY_CLOCK_CONTROL 0x6b 634#define DISPLAY_TRUNK_FORCE_ON (1 << 17) 635#define DISPLAY_TRUNK_FORCE_OFF (1 << 16) 636#define DISPLAY_FREQUENCY_STATUS (0x1f << 8) 637#define DISPLAY_FREQUENCY_STATUS_SHIFT 8 638#define DISPLAY_FREQUENCY_VALUES (0x1f << 0) 639 640/** 641 * DOC: DPIO 642 * 643 * VLV and CHV have slightly peculiar display PHYs for driving DP/HDMI 644 * ports. DPIO is the name given to such a display PHY. These PHYs 645 * don't follow the standard programming model using direct MMIO 646 * registers, and instead their registers must be accessed trough IOSF 647 * sideband. VLV has one such PHY for driving ports B and C, and CHV 648 * adds another PHY for driving port D. Each PHY responds to specific 649 * IOSF-SB port. 650 * 651 * Each display PHY is made up of one or two channels. Each channel 652 * houses a common lane part which contains the PLL and other common 653 * logic. CH0 common lane also contains the IOSF-SB logic for the 654 * Common Register Interface (CRI) ie. the DPIO registers. CRI clock 655 * must be running when any DPIO registers are accessed. 656 * 657 * In addition to having their own registers, the PHYs are also 658 * controlled through some dedicated signals from the display 659 * controller. These include PLL reference clock enable, PLL enable, 660 * and CRI clock selection, for example. 661 * 662 * Eeach channel also has two splines (also called data lanes), and 663 * each spline is made up of one Physical Access Coding Sub-Layer 664 * (PCS) block and two TX lanes. So each channel has two PCS blocks 665 * and four TX lanes. The TX lanes are used as DP lanes or TMDS 666 * data/clock pairs depending on the output type. 667 * 668 * Additionally the PHY also contains an AUX lane with AUX blocks 669 * for each channel. This is used for DP AUX communication, but 670 * this fact isn't really relevant for the driver since AUX is 671 * controlled from the display controller side. No DPIO registers 672 * need to be accessed during AUX communication, 673 * 674 * Generally the common lane corresponds to the pipe and 675 * the spline (PCS/TX) correponds to the port. 676 * 677 * For dual channel PHY (VLV/CHV): 678 * 679 * pipe A == CMN/PLL/REF CH0 680 * 681 * pipe B == CMN/PLL/REF CH1 682 * 683 * port B == PCS/TX CH0 684 * 685 * port C == PCS/TX CH1 686 * 687 * This is especially important when we cross the streams 688 * ie. drive port B with pipe B, or port C with pipe A. 689 * 690 * For single channel PHY (CHV): 691 * 692 * pipe C == CMN/PLL/REF CH0 693 * 694 * port D == PCS/TX CH0 695 * 696 * Note: digital port B is DDI0, digital port C is DDI1, 697 * digital port D is DDI2 698 */ 699/* 700 * Dual channel PHY (VLV/CHV) 701 * --------------------------------- 702 * | CH0 | CH1 | 703 * | CMN/PLL/REF | CMN/PLL/REF | 704 * |---------------|---------------| Display PHY 705 * | PCS01 | PCS23 | PCS01 | PCS23 | 706 * |-------|-------|-------|-------| 707 * |TX0|TX1|TX2|TX3|TX0|TX1|TX2|TX3| 708 * --------------------------------- 709 * | DDI0 | DDI1 | DP/HDMI ports 710 * --------------------------------- 711 * 712 * Single channel PHY (CHV) 713 * ----------------- 714 * | CH0 | 715 * | CMN/PLL/REF | 716 * |---------------| Display PHY 717 * | PCS01 | PCS23 | 718 * |-------|-------| 719 * |TX0|TX1|TX2|TX3| 720 * ----------------- 721 * | DDI2 | DP/HDMI port 722 * ----------------- 723 */ 724#define DPIO_DEVFN 0 725 726#define DPIO_CTL (VLV_DISPLAY_BASE + 0x2110) 727#define DPIO_MODSEL1 (1<<3) /* if ref clk b == 27 */ 728#define DPIO_MODSEL0 (1<<2) /* if ref clk a == 27 */ 729#define DPIO_SFR_BYPASS (1<<1) 730#define DPIO_CMNRST (1<<0) 731 732#define DPIO_PHY(pipe) ((pipe) >> 1) 733#define DPIO_PHY_IOSF_PORT(phy) (dev_priv->dpio_phy_iosf_port[phy]) 734 735/* 736 * Per pipe/PLL DPIO regs 737 */ 738#define _VLV_PLL_DW3_CH0 0x800c 739#define DPIO_POST_DIV_SHIFT (28) /* 3 bits */ 740#define DPIO_POST_DIV_DAC 0 741#define DPIO_POST_DIV_HDMIDP 1 /* DAC 225-400M rate */ 742#define DPIO_POST_DIV_LVDS1 2 743#define DPIO_POST_DIV_LVDS2 3 744#define DPIO_K_SHIFT (24) /* 4 bits */ 745#define DPIO_P1_SHIFT (21) /* 3 bits */ 746#define DPIO_P2_SHIFT (16) /* 5 bits */ 747#define DPIO_N_SHIFT (12) /* 4 bits */ 748#define DPIO_ENABLE_CALIBRATION (1<<11) 749#define DPIO_M1DIV_SHIFT (8) /* 3 bits */ 750#define DPIO_M2DIV_MASK 0xff 751#define _VLV_PLL_DW3_CH1 0x802c 752#define VLV_PLL_DW3(ch) _PIPE(ch, _VLV_PLL_DW3_CH0, _VLV_PLL_DW3_CH1) 753 754#define _VLV_PLL_DW5_CH0 0x8014 755#define DPIO_REFSEL_OVERRIDE 27 756#define DPIO_PLL_MODESEL_SHIFT 24 /* 3 bits */ 757#define DPIO_BIAS_CURRENT_CTL_SHIFT 21 /* 3 bits, always 0x7 */ 758#define DPIO_PLL_REFCLK_SEL_SHIFT 16 /* 2 bits */ 759#define DPIO_PLL_REFCLK_SEL_MASK 3 760#define DPIO_DRIVER_CTL_SHIFT 12 /* always set to 0x8 */ 761#define DPIO_CLK_BIAS_CTL_SHIFT 8 /* always set to 0x5 */ 762#define _VLV_PLL_DW5_CH1 0x8034 763#define VLV_PLL_DW5(ch) _PIPE(ch, _VLV_PLL_DW5_CH0, _VLV_PLL_DW5_CH1) 764 765#define _VLV_PLL_DW7_CH0 0x801c 766#define _VLV_PLL_DW7_CH1 0x803c 767#define VLV_PLL_DW7(ch) _PIPE(ch, _VLV_PLL_DW7_CH0, _VLV_PLL_DW7_CH1) 768 769#define _VLV_PLL_DW8_CH0 0x8040 770#define _VLV_PLL_DW8_CH1 0x8060 771#define VLV_PLL_DW8(ch) _PIPE(ch, _VLV_PLL_DW8_CH0, _VLV_PLL_DW8_CH1) 772 773#define VLV_PLL_DW9_BCAST 0xc044 774#define _VLV_PLL_DW9_CH0 0x8044 775#define _VLV_PLL_DW9_CH1 0x8064 776#define VLV_PLL_DW9(ch) _PIPE(ch, _VLV_PLL_DW9_CH0, _VLV_PLL_DW9_CH1) 777 778#define _VLV_PLL_DW10_CH0 0x8048 779#define _VLV_PLL_DW10_CH1 0x8068 780#define VLV_PLL_DW10(ch) _PIPE(ch, _VLV_PLL_DW10_CH0, _VLV_PLL_DW10_CH1) 781 782#define _VLV_PLL_DW11_CH0 0x804c 783#define _VLV_PLL_DW11_CH1 0x806c 784#define VLV_PLL_DW11(ch) _PIPE(ch, _VLV_PLL_DW11_CH0, _VLV_PLL_DW11_CH1) 785 786/* Spec for ref block start counts at DW10 */ 787#define VLV_REF_DW13 0x80ac 788 789#define VLV_CMN_DW0 0x8100 790 791/* 792 * Per DDI channel DPIO regs 793 */ 794 795#define _VLV_PCS_DW0_CH0 0x8200 796#define _VLV_PCS_DW0_CH1 0x8400 797#define DPIO_PCS_TX_LANE2_RESET (1<<16) 798#define DPIO_PCS_TX_LANE1_RESET (1<<7) 799#define VLV_PCS_DW0(ch) _PORT(ch, _VLV_PCS_DW0_CH0, _VLV_PCS_DW0_CH1) 800 801#define _VLV_PCS01_DW0_CH0 0x200 802#define _VLV_PCS23_DW0_CH0 0x400 803#define _VLV_PCS01_DW0_CH1 0x2600 804#define _VLV_PCS23_DW0_CH1 0x2800 805#define VLV_PCS01_DW0(ch) _PORT(ch, _VLV_PCS01_DW0_CH0, _VLV_PCS01_DW0_CH1) 806#define VLV_PCS23_DW0(ch) _PORT(ch, _VLV_PCS23_DW0_CH0, _VLV_PCS23_DW0_CH1) 807 808#define _VLV_PCS_DW1_CH0 0x8204 809#define _VLV_PCS_DW1_CH1 0x8404 810#define CHV_PCS_REQ_SOFTRESET_EN (1<<23) 811#define DPIO_PCS_CLK_CRI_RXEB_EIOS_EN (1<<22) 812#define DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN (1<<21) 813#define DPIO_PCS_CLK_DATAWIDTH_SHIFT (6) 814#define DPIO_PCS_CLK_SOFT_RESET (1<<5) 815#define VLV_PCS_DW1(ch) _PORT(ch, _VLV_PCS_DW1_CH0, _VLV_PCS_DW1_CH1) 816 817#define _VLV_PCS01_DW1_CH0 0x204 818#define _VLV_PCS23_DW1_CH0 0x404 819#define _VLV_PCS01_DW1_CH1 0x2604 820#define _VLV_PCS23_DW1_CH1 0x2804 821#define VLV_PCS01_DW1(ch) _PORT(ch, _VLV_PCS01_DW1_CH0, _VLV_PCS01_DW1_CH1) 822#define VLV_PCS23_DW1(ch) _PORT(ch, _VLV_PCS23_DW1_CH0, _VLV_PCS23_DW1_CH1) 823 824#define _VLV_PCS_DW8_CH0 0x8220 825#define _VLV_PCS_DW8_CH1 0x8420 826#define CHV_PCS_USEDCLKCHANNEL_OVRRIDE (1 << 20) 827#define CHV_PCS_USEDCLKCHANNEL (1 << 21) 828#define VLV_PCS_DW8(ch) _PORT(ch, _VLV_PCS_DW8_CH0, _VLV_PCS_DW8_CH1) 829 830#define _VLV_PCS01_DW8_CH0 0x0220 831#define _VLV_PCS23_DW8_CH0 0x0420 832#define _VLV_PCS01_DW8_CH1 0x2620 833#define _VLV_PCS23_DW8_CH1 0x2820 834#define VLV_PCS01_DW8(port) _PORT(port, _VLV_PCS01_DW8_CH0, _VLV_PCS01_DW8_CH1) 835#define VLV_PCS23_DW8(port) _PORT(port, _VLV_PCS23_DW8_CH0, _VLV_PCS23_DW8_CH1) 836 837#define _VLV_PCS_DW9_CH0 0x8224 838#define _VLV_PCS_DW9_CH1 0x8424 839#define VLV_PCS_DW9(ch) _PORT(ch, _VLV_PCS_DW9_CH0, _VLV_PCS_DW9_CH1) 840 841#define _CHV_PCS_DW10_CH0 0x8228 842#define _CHV_PCS_DW10_CH1 0x8428 843#define DPIO_PCS_SWING_CALC_TX0_TX2 (1<<30) 844#define DPIO_PCS_SWING_CALC_TX1_TX3 (1<<31) 845#define CHV_PCS_DW10(ch) _PORT(ch, _CHV_PCS_DW10_CH0, _CHV_PCS_DW10_CH1) 846 847#define _VLV_PCS01_DW10_CH0 0x0228 848#define _VLV_PCS23_DW10_CH0 0x0428 849#define _VLV_PCS01_DW10_CH1 0x2628 850#define _VLV_PCS23_DW10_CH1 0x2828 851#define VLV_PCS01_DW10(port) _PORT(port, _VLV_PCS01_DW10_CH0, _VLV_PCS01_DW10_CH1) 852#define VLV_PCS23_DW10(port) _PORT(port, _VLV_PCS23_DW10_CH0, _VLV_PCS23_DW10_CH1) 853 854#define _VLV_PCS_DW11_CH0 0x822c 855#define _VLV_PCS_DW11_CH1 0x842c 856#define VLV_PCS_DW11(ch) _PORT(ch, _VLV_PCS_DW11_CH0, _VLV_PCS_DW11_CH1) 857 858#define _VLV_PCS_DW12_CH0 0x8230 859#define _VLV_PCS_DW12_CH1 0x8430 860#define VLV_PCS_DW12(ch) _PORT(ch, _VLV_PCS_DW12_CH0, _VLV_PCS_DW12_CH1) 861 862#define _VLV_PCS_DW14_CH0 0x8238 863#define _VLV_PCS_DW14_CH1 0x8438 864#define VLV_PCS_DW14(ch) _PORT(ch, _VLV_PCS_DW14_CH0, _VLV_PCS_DW14_CH1) 865 866#define _VLV_PCS_DW23_CH0 0x825c 867#define _VLV_PCS_DW23_CH1 0x845c 868#define VLV_PCS_DW23(ch) _PORT(ch, _VLV_PCS_DW23_CH0, _VLV_PCS_DW23_CH1) 869 870#define _VLV_TX_DW2_CH0 0x8288 871#define _VLV_TX_DW2_CH1 0x8488 872#define DPIO_SWING_MARGIN000_SHIFT 16 873#define DPIO_SWING_MARGIN000_MASK (0xff << DPIO_SWING_MARGIN000_SHIFT) 874#define DPIO_UNIQ_TRANS_SCALE_SHIFT 8 875#define VLV_TX_DW2(ch) _PORT(ch, _VLV_TX_DW2_CH0, _VLV_TX_DW2_CH1) 876 877#define _VLV_TX_DW3_CH0 0x828c 878#define _VLV_TX_DW3_CH1 0x848c 879/* The following bit for CHV phy */ 880#define DPIO_TX_UNIQ_TRANS_SCALE_EN (1<<27) 881#define DPIO_SWING_MARGIN101_SHIFT 16 882#define DPIO_SWING_MARGIN101_MASK (0xff << DPIO_SWING_MARGIN101_SHIFT) 883#define VLV_TX_DW3(ch) _PORT(ch, _VLV_TX_DW3_CH0, _VLV_TX_DW3_CH1) 884 885#define _VLV_TX_DW4_CH0 0x8290 886#define _VLV_TX_DW4_CH1 0x8490 887#define DPIO_SWING_DEEMPH9P5_SHIFT 24 888#define DPIO_SWING_DEEMPH9P5_MASK (0xff << DPIO_SWING_DEEMPH9P5_SHIFT) 889#define DPIO_SWING_DEEMPH6P0_SHIFT 16 890#define DPIO_SWING_DEEMPH6P0_MASK (0xff << DPIO_SWING_DEEMPH6P0_SHIFT) 891#define VLV_TX_DW4(ch) _PORT(ch, _VLV_TX_DW4_CH0, _VLV_TX_DW4_CH1) 892 893#define _VLV_TX3_DW4_CH0 0x690 894#define _VLV_TX3_DW4_CH1 0x2a90 895#define VLV_TX3_DW4(ch) _PORT(ch, _VLV_TX3_DW4_CH0, _VLV_TX3_DW4_CH1) 896 897#define _VLV_TX_DW5_CH0 0x8294 898#define _VLV_TX_DW5_CH1 0x8494 899#define DPIO_TX_OCALINIT_EN (1<<31) 900#define VLV_TX_DW5(ch) _PORT(ch, _VLV_TX_DW5_CH0, _VLV_TX_DW5_CH1) 901 902#define _VLV_TX_DW11_CH0 0x82ac 903#define _VLV_TX_DW11_CH1 0x84ac 904#define VLV_TX_DW11(ch) _PORT(ch, _VLV_TX_DW11_CH0, _VLV_TX_DW11_CH1) 905 906#define _VLV_TX_DW14_CH0 0x82b8 907#define _VLV_TX_DW14_CH1 0x84b8 908#define VLV_TX_DW14(ch) _PORT(ch, _VLV_TX_DW14_CH0, _VLV_TX_DW14_CH1) 909 910/* CHV dpPhy registers */ 911#define _CHV_PLL_DW0_CH0 0x8000 912#define _CHV_PLL_DW0_CH1 0x8180 913#define CHV_PLL_DW0(ch) _PIPE(ch, _CHV_PLL_DW0_CH0, _CHV_PLL_DW0_CH1) 914 915#define _CHV_PLL_DW1_CH0 0x8004 916#define _CHV_PLL_DW1_CH1 0x8184 917#define DPIO_CHV_N_DIV_SHIFT 8 918#define DPIO_CHV_M1_DIV_BY_2 (0 << 0) 919#define CHV_PLL_DW1(ch) _PIPE(ch, _CHV_PLL_DW1_CH0, _CHV_PLL_DW1_CH1) 920 921#define _CHV_PLL_DW2_CH0 0x8008 922#define _CHV_PLL_DW2_CH1 0x8188 923#define CHV_PLL_DW2(ch) _PIPE(ch, _CHV_PLL_DW2_CH0, _CHV_PLL_DW2_CH1) 924 925#define _CHV_PLL_DW3_CH0 0x800c 926#define _CHV_PLL_DW3_CH1 0x818c 927#define DPIO_CHV_FRAC_DIV_EN (1 << 16) 928#define DPIO_CHV_FIRST_MOD (0 << 8) 929#define DPIO_CHV_SECOND_MOD (1 << 8) 930#define DPIO_CHV_FEEDFWD_GAIN_SHIFT 0 931#define CHV_PLL_DW3(ch) _PIPE(ch, _CHV_PLL_DW3_CH0, _CHV_PLL_DW3_CH1) 932 933#define _CHV_PLL_DW6_CH0 0x8018 934#define _CHV_PLL_DW6_CH1 0x8198 935#define DPIO_CHV_GAIN_CTRL_SHIFT 16 936#define DPIO_CHV_INT_COEFF_SHIFT 8 937#define DPIO_CHV_PROP_COEFF_SHIFT 0 938#define CHV_PLL_DW6(ch) _PIPE(ch, _CHV_PLL_DW6_CH0, _CHV_PLL_DW6_CH1) 939 940#define _CHV_CMN_DW5_CH0 0x8114 941#define CHV_BUFRIGHTENA1_DISABLE (0 << 20) 942#define CHV_BUFRIGHTENA1_NORMAL (1 << 20) 943#define CHV_BUFRIGHTENA1_FORCE (3 << 20) 944#define CHV_BUFRIGHTENA1_MASK (3 << 20) 945#define CHV_BUFLEFTENA1_DISABLE (0 << 22) 946#define CHV_BUFLEFTENA1_NORMAL (1 << 22) 947#define CHV_BUFLEFTENA1_FORCE (3 << 22) 948#define CHV_BUFLEFTENA1_MASK (3 << 22) 949 950#define _CHV_CMN_DW13_CH0 0x8134 951#define _CHV_CMN_DW0_CH1 0x8080 952#define DPIO_CHV_S1_DIV_SHIFT 21 953#define DPIO_CHV_P1_DIV_SHIFT 13 /* 3 bits */ 954#define DPIO_CHV_P2_DIV_SHIFT 8 /* 5 bits */ 955#define DPIO_CHV_K_DIV_SHIFT 4 956#define DPIO_PLL_FREQLOCK (1 << 1) 957#define DPIO_PLL_LOCK (1 << 0) 958#define CHV_CMN_DW13(ch) _PIPE(ch, _CHV_CMN_DW13_CH0, _CHV_CMN_DW0_CH1) 959 960#define _CHV_CMN_DW14_CH0 0x8138 961#define _CHV_CMN_DW1_CH1 0x8084 962#define DPIO_AFC_RECAL (1 << 14) 963#define DPIO_DCLKP_EN (1 << 13) 964#define CHV_BUFLEFTENA2_DISABLE (0 << 17) /* CL2 DW1 only */ 965#define CHV_BUFLEFTENA2_NORMAL (1 << 17) /* CL2 DW1 only */ 966#define CHV_BUFLEFTENA2_FORCE (3 << 17) /* CL2 DW1 only */ 967#define CHV_BUFLEFTENA2_MASK (3 << 17) /* CL2 DW1 only */ 968#define CHV_BUFRIGHTENA2_DISABLE (0 << 19) /* CL2 DW1 only */ 969#define CHV_BUFRIGHTENA2_NORMAL (1 << 19) /* CL2 DW1 only */ 970#define CHV_BUFRIGHTENA2_FORCE (3 << 19) /* CL2 DW1 only */ 971#define CHV_BUFRIGHTENA2_MASK (3 << 19) /* CL2 DW1 only */ 972#define CHV_CMN_DW14(ch) _PIPE(ch, _CHV_CMN_DW14_CH0, _CHV_CMN_DW1_CH1) 973 974#define _CHV_CMN_DW19_CH0 0x814c 975#define _CHV_CMN_DW6_CH1 0x8098 976#define CHV_CMN_USEDCLKCHANNEL (1 << 13) 977#define CHV_CMN_DW19(ch) _PIPE(ch, _CHV_CMN_DW19_CH0, _CHV_CMN_DW6_CH1) 978 979#define CHV_CMN_DW30 0x8178 980#define DPIO_LRC_BYPASS (1 << 3) 981 982#define _TXLANE(ch, lane, offset) ((ch ? 0x2400 : 0) + \ 983 (lane) * 0x200 + (offset)) 984 985#define CHV_TX_DW0(ch, lane) _TXLANE(ch, lane, 0x80) 986#define CHV_TX_DW1(ch, lane) _TXLANE(ch, lane, 0x84) 987#define CHV_TX_DW2(ch, lane) _TXLANE(ch, lane, 0x88) 988#define CHV_TX_DW3(ch, lane) _TXLANE(ch, lane, 0x8c) 989#define CHV_TX_DW4(ch, lane) _TXLANE(ch, lane, 0x90) 990#define CHV_TX_DW5(ch, lane) _TXLANE(ch, lane, 0x94) 991#define CHV_TX_DW6(ch, lane) _TXLANE(ch, lane, 0x98) 992#define CHV_TX_DW7(ch, lane) _TXLANE(ch, lane, 0x9c) 993#define CHV_TX_DW8(ch, lane) _TXLANE(ch, lane, 0xa0) 994#define CHV_TX_DW9(ch, lane) _TXLANE(ch, lane, 0xa4) 995#define CHV_TX_DW10(ch, lane) _TXLANE(ch, lane, 0xa8) 996#define CHV_TX_DW11(ch, lane) _TXLANE(ch, lane, 0xac) 997#define DPIO_FRC_LATENCY_SHFIT 8 998#define CHV_TX_DW14(ch, lane) _TXLANE(ch, lane, 0xb8) 999#define DPIO_UPAR_SHIFT 30 1000/* 1001 * Fence registers 1002 */ 1003#define FENCE_REG_830_0 0x2000 1004#define FENCE_REG_945_8 0x3000 1005#define I830_FENCE_START_MASK 0x07f80000 1006#define I830_FENCE_TILING_Y_SHIFT 12 1007#define I830_FENCE_SIZE_BITS(size) ((ffs((size) >> 19) - 1) << 8) 1008#define I830_FENCE_PITCH_SHIFT 4 1009#define I830_FENCE_REG_VALID (1<<0) 1010#define I915_FENCE_MAX_PITCH_VAL 4 1011#define I830_FENCE_MAX_PITCH_VAL 6 1012#define I830_FENCE_MAX_SIZE_VAL (1<<8) 1013 1014#define I915_FENCE_START_MASK 0x0ff00000 1015#define I915_FENCE_SIZE_BITS(size) ((ffs((size) >> 20) - 1) << 8) 1016 1017#define FENCE_REG_965_0 0x03000 1018#define I965_FENCE_PITCH_SHIFT 2 1019#define I965_FENCE_TILING_Y_SHIFT 1 1020#define I965_FENCE_REG_VALID (1<<0) 1021#define I965_FENCE_MAX_PITCH_VAL 0x0400 1022 1023#define FENCE_REG_SANDYBRIDGE_0 0x100000 1024#define SANDYBRIDGE_FENCE_PITCH_SHIFT 32 1025#define GEN7_FENCE_MAX_PITCH_VAL 0x0800 1026 1027 1028/* control register for cpu gtt access */ 1029#define TILECTL 0x101000 1030#define TILECTL_SWZCTL (1 << 0) 1031#define TILECTL_TLB_PREFETCH_DIS (1 << 2) 1032#define TILECTL_BACKSNOOP_DIS (1 << 3) 1033 1034/* 1035 * Instruction and interrupt control regs 1036 */ 1037#define PGTBL_CTL 0x02020 1038#define PGTBL_ADDRESS_LO_MASK 0xfffff000 /* bits [31:12] */ 1039#define PGTBL_ADDRESS_HI_MASK 0x000000f0 /* bits [35:32] (gen4) */ 1040#define PGTBL_ER 0x02024 1041#define PRB0_BASE (0x2030-0x30) 1042#define PRB1_BASE (0x2040-0x30) /* 830,gen3 */ 1043#define PRB2_BASE (0x2050-0x30) /* gen3 */ 1044#define SRB0_BASE (0x2100-0x30) /* gen2 */ 1045#define SRB1_BASE (0x2110-0x30) /* gen2 */ 1046#define SRB2_BASE (0x2120-0x30) /* 830 */ 1047#define SRB3_BASE (0x2130-0x30) /* 830 */ 1048#define RENDER_RING_BASE 0x02000 1049#define BSD_RING_BASE 0x04000 1050#define GEN6_BSD_RING_BASE 0x12000 1051#define GEN8_BSD2_RING_BASE 0x1c000 1052#define VEBOX_RING_BASE 0x1a000 1053#define BLT_RING_BASE 0x22000 1054#define RING_TAIL(base) ((base)+0x30) 1055#define RING_HEAD(base) ((base)+0x34) 1056#define RING_START(base) ((base)+0x38) 1057#define RING_CTL(base) ((base)+0x3c) 1058#define RING_SYNC_0(base) ((base)+0x40) 1059#define RING_SYNC_1(base) ((base)+0x44) 1060#define RING_SYNC_2(base) ((base)+0x48) 1061#define GEN6_RVSYNC (RING_SYNC_0(RENDER_RING_BASE)) 1062#define GEN6_RBSYNC (RING_SYNC_1(RENDER_RING_BASE)) 1063#define GEN6_RVESYNC (RING_SYNC_2(RENDER_RING_BASE)) 1064#define GEN6_VBSYNC (RING_SYNC_0(GEN6_BSD_RING_BASE)) 1065#define GEN6_VRSYNC (RING_SYNC_1(GEN6_BSD_RING_BASE)) 1066#define GEN6_VVESYNC (RING_SYNC_2(GEN6_BSD_RING_BASE)) 1067#define GEN6_BRSYNC (RING_SYNC_0(BLT_RING_BASE)) 1068#define GEN6_BVSYNC (RING_SYNC_1(BLT_RING_BASE)) 1069#define GEN6_BVESYNC (RING_SYNC_2(BLT_RING_BASE)) 1070#define GEN6_VEBSYNC (RING_SYNC_0(VEBOX_RING_BASE)) 1071#define GEN6_VERSYNC (RING_SYNC_1(VEBOX_RING_BASE)) 1072#define GEN6_VEVSYNC (RING_SYNC_2(VEBOX_RING_BASE)) 1073#define GEN6_NOSYNC 0 1074#define RING_MAX_IDLE(base) ((base)+0x54) 1075#define RING_HWS_PGA(base) ((base)+0x80) 1076#define RING_HWS_PGA_GEN6(base) ((base)+0x2080) 1077 1078#define GEN7_WR_WATERMARK 0x4028 1079#define GEN7_GFX_PRIO_CTRL 0x402C 1080#define ARB_MODE 0x4030 1081#define ARB_MODE_SWIZZLE_SNB (1<<4) 1082#define ARB_MODE_SWIZZLE_IVB (1<<5) 1083#define GEN7_GFX_PEND_TLB0 0x4034 1084#define GEN7_GFX_PEND_TLB1 0x4038 1085/* L3, CVS, ZTLB, RCC, CASC LRA min, max values */ 1086#define GEN7_LRA_LIMITS_BASE 0x403C 1087#define GEN7_LRA_LIMITS_REG_NUM 13 1088#define GEN7_MEDIA_MAX_REQ_COUNT 0x4070 1089#define GEN7_GFX_MAX_REQ_COUNT 0x4074 1090 1091#define GAMTARBMODE 0x04a08 1092#define ARB_MODE_BWGTLB_DISABLE (1<<9) 1093#define ARB_MODE_SWIZZLE_BDW (1<<1) 1094#define RENDER_HWS_PGA_GEN7 (0x04080) 1095#define RING_FAULT_REG(ring) (0x4094 + 0x100*(ring)->id) 1096#define RING_FAULT_GTTSEL_MASK (1<<11) 1097#define RING_FAULT_SRCID(x) ((x >> 3) & 0xff) 1098#define RING_FAULT_FAULT_TYPE(x) ((x >> 1) & 0x3) 1099#define RING_FAULT_VALID (1<<0) 1100#define DONE_REG 0x40b0 1101#define GEN8_PRIVATE_PAT 0x40e0 1102#define BSD_HWS_PGA_GEN7 (0x04180) 1103#define BLT_HWS_PGA_GEN7 (0x04280) 1104#define VEBOX_HWS_PGA_GEN7 (0x04380) 1105#define RING_ACTHD(base) ((base)+0x74) 1106#define RING_ACTHD_UDW(base) ((base)+0x5c) 1107#define RING_NOPID(base) ((base)+0x94) 1108#define RING_IMR(base) ((base)+0xa8) 1109#define RING_HWSTAM(base) ((base)+0x98) 1110#define RING_TIMESTAMP(base) ((base)+0x358) 1111#define TAIL_ADDR 0x001FFFF8 1112#define HEAD_WRAP_COUNT 0xFFE00000 1113#define HEAD_WRAP_ONE 0x00200000 1114#define HEAD_ADDR 0x001FFFFC 1115#define RING_NR_PAGES 0x001FF000 1116#define RING_REPORT_MASK 0x00000006 1117#define RING_REPORT_64K 0x00000002 1118#define RING_REPORT_128K 0x00000004 1119#define RING_NO_REPORT 0x00000000 1120#define RING_VALID_MASK 0x00000001 1121#define RING_VALID 0x00000001 1122#define RING_INVALID 0x00000000 1123#define RING_WAIT_I8XX (1<<0) /* gen2, PRBx_HEAD */ 1124#define RING_WAIT (1<<11) /* gen3+, PRBx_CTL */ 1125#define RING_WAIT_SEMAPHORE (1<<10) /* gen6+ */ 1126 1127#define GEN7_TLB_RD_ADDR 0x4700 1128 1129#if 0 1130#define PRB0_TAIL 0x02030 1131#define PRB0_HEAD 0x02034 1132#define PRB0_START 0x02038 1133#define PRB0_CTL 0x0203c 1134#define PRB1_TAIL 0x02040 /* 915+ only */ 1135#define PRB1_HEAD 0x02044 /* 915+ only */ 1136#define PRB1_START 0x02048 /* 915+ only */ 1137#define PRB1_CTL 0x0204c /* 915+ only */ 1138#endif 1139#define IPEIR_I965 0x02064 1140#define IPEHR_I965 0x02068 1141#define INSTDONE_I965 0x0206c 1142#define GEN7_INSTDONE_1 0x0206c 1143#define GEN7_SC_INSTDONE 0x07100 1144#define GEN7_SAMPLER_INSTDONE 0x0e160 1145#define GEN7_ROW_INSTDONE 0x0e164 1146#define I915_NUM_INSTDONE_REG 4 1147#define RING_IPEIR(base) ((base)+0x64) 1148#define RING_IPEHR(base) ((base)+0x68) 1149#define RING_INSTDONE(base) ((base)+0x6c) 1150#define RING_INSTPS(base) ((base)+0x70) 1151#define RING_DMA_FADD(base) ((base)+0x78) 1152#define RING_DMA_FADD_UDW(base) ((base)+0x60) /* gen8+ */ 1153#define RING_INSTPM(base) ((base)+0xc0) 1154#define RING_MI_MODE(base) ((base)+0x9c) 1155#define INSTPS 0x02070 /* 965+ only */ 1156#define INSTDONE1 0x0207c /* 965+ only */ 1157#define ACTHD_I965 0x02074 1158#define HWS_PGA 0x02080 1159#define HWS_ADDRESS_MASK 0xfffff000 1160#define HWS_START_ADDRESS_SHIFT 4 1161#define PWRCTXA 0x2088 /* 965GM+ only */ 1162#define PWRCTX_EN (1<<0) 1163#define IPEIR 0x02088 1164#define IPEHR 0x0208c 1165#define INSTDONE 0x02090 1166#define NOPID 0x02094 1167#define HWSTAM 0x02098 1168#define DMA_FADD_I8XX 0x020d0 1169#define RING_BBSTATE(base) ((base)+0x110) 1170#define RING_BBADDR(base) ((base)+0x140) 1171#define RING_BBADDR_UDW(base) ((base)+0x168) /* gen8+ */ 1172 1173#define ERROR_GEN6 0x040a0 1174#define GEN7_ERR_INT 0x44040 1175#define ERR_INT_POISON (1<<31) 1176#define ERR_INT_MMIO_UNCLAIMED (1<<13) 1177#define ERR_INT_PIPE_CRC_DONE_C (1<<8) 1178#define ERR_INT_FIFO_UNDERRUN_C (1<<6) 1179#define ERR_INT_PIPE_CRC_DONE_B (1<<5) 1180#define ERR_INT_FIFO_UNDERRUN_B (1<<3) 1181#define ERR_INT_PIPE_CRC_DONE_A (1<<2) 1182#define ERR_INT_PIPE_CRC_DONE(pipe) (1<<(2 + pipe*3)) 1183#define ERR_INT_FIFO_UNDERRUN_A (1<<0) 1184#define ERR_INT_FIFO_UNDERRUN(pipe) (1<<(pipe*3)) 1185 1186#define FPGA_DBG 0x42300 1187#define FPGA_DBG_RM_NOCLAIM (1<<31) 1188 1189#define DERRMR 0x44050 1190/* Note that HBLANK events are reserved on bdw+ */ 1191#define DERRMR_PIPEA_SCANLINE (1<<0) 1192#define DERRMR_PIPEA_PRI_FLIP_DONE (1<<1) 1193#define DERRMR_PIPEA_SPR_FLIP_DONE (1<<2) 1194#define DERRMR_PIPEA_VBLANK (1<<3) 1195#define DERRMR_PIPEA_HBLANK (1<<5) 1196#define DERRMR_PIPEB_SCANLINE (1<<8) 1197#define DERRMR_PIPEB_PRI_FLIP_DONE (1<<9) 1198#define DERRMR_PIPEB_SPR_FLIP_DONE (1<<10) 1199#define DERRMR_PIPEB_VBLANK (1<<11) 1200#define DERRMR_PIPEB_HBLANK (1<<13) 1201/* Note that PIPEC is not a simple translation of PIPEA/PIPEB */ 1202#define DERRMR_PIPEC_SCANLINE (1<<14) 1203#define DERRMR_PIPEC_PRI_FLIP_DONE (1<<15) 1204#define DERRMR_PIPEC_SPR_FLIP_DONE (1<<20) 1205#define DERRMR_PIPEC_VBLANK (1<<21) 1206#define DERRMR_PIPEC_HBLANK (1<<22) 1207 1208 1209/* GM45+ chicken bits -- debug workaround bits that may be required 1210 * for various sorts of correct behavior. The top 16 bits of each are 1211 * the enables for writing to the corresponding low bit. 1212 */ 1213#define _3D_CHICKEN 0x02084 1214#define _3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB (1 << 10) 1215#define _3D_CHICKEN2 0x0208c 1216/* Disables pipelining of read flushes past the SF-WIZ interface. 1217 * Required on all Ironlake steppings according to the B-Spec, but the 1218 * particular danger of not doing so is not specified. 1219 */ 1220# define _3D_CHICKEN2_WM_READ_PIPELINED (1 << 14) 1221#define _3D_CHICKEN3 0x02090 1222#define _3D_CHICKEN_SF_DISABLE_OBJEND_CULL (1 << 10) 1223#define _3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL (1 << 5) 1224#define _3D_CHICKEN_SDE_LIMIT_FIFO_POLY_DEPTH(x) ((x)<<1) /* gen8+ */ 1225#define _3D_CHICKEN3_SF_DISABLE_PIPELINED_ATTR_FETCH (1 << 1) /* gen6 */ 1226 1227#define MI_MODE 0x0209c 1228# define VS_TIMER_DISPATCH (1 << 6) 1229# define MI_FLUSH_ENABLE (1 << 12) 1230# define ASYNC_FLIP_PERF_DISABLE (1 << 14) 1231# define MODE_IDLE (1 << 9) 1232# define STOP_RING (1 << 8) 1233 1234#define GEN6_GT_MODE 0x20d0 1235#define GEN7_GT_MODE 0x7008 1236#define GEN6_WIZ_HASHING(hi, lo) (((hi) << 9) | ((lo) << 7)) 1237#define GEN6_WIZ_HASHING_8x8 GEN6_WIZ_HASHING(0, 0) 1238#define GEN6_WIZ_HASHING_8x4 GEN6_WIZ_HASHING(0, 1) 1239#define GEN6_WIZ_HASHING_16x4 GEN6_WIZ_HASHING(1, 0) 1240#define GEN6_WIZ_HASHING_MASK (GEN6_WIZ_HASHING(1, 1) << 16) 1241#define GEN6_TD_FOUR_ROW_DISPATCH_DISABLE (1 << 5) 1242 1243#define GFX_MODE 0x02520 1244#define GFX_MODE_GEN7 0x0229c 1245#define RING_MODE_GEN7(ring) ((ring)->mmio_base+0x29c) 1246#define GFX_RUN_LIST_ENABLE (1<<15) 1247#define GFX_TLB_INVALIDATE_EXPLICIT (1<<13) 1248#define GFX_SURFACE_FAULT_ENABLE (1<<12) 1249#define GFX_REPLAY_MODE (1<<11) 1250#define GFX_PSMI_GRANULARITY (1<<10) 1251#define GFX_PPGTT_ENABLE (1<<9) 1252 1253#define VLV_DISPLAY_BASE 0x180000 1254#define VLV_MIPI_BASE VLV_DISPLAY_BASE 1255 1256#define VLV_GU_CTL0 (VLV_DISPLAY_BASE + 0x2030) 1257#define VLV_GU_CTL1 (VLV_DISPLAY_BASE + 0x2034) 1258#define SCPD0 0x0209c /* 915+ only */ 1259#define IER 0x020a0 1260#define IIR 0x020a4 1261#define IMR 0x020a8 1262#define ISR 0x020ac 1263#define VLV_GUNIT_CLOCK_GATE (VLV_DISPLAY_BASE + 0x2060) 1264#define GINT_DIS (1<<22) 1265#define GCFG_DIS (1<<8) 1266#define VLV_GUNIT_CLOCK_GATE2 (VLV_DISPLAY_BASE + 0x2064) 1267#define VLV_IIR_RW (VLV_DISPLAY_BASE + 0x2084) 1268#define VLV_IER (VLV_DISPLAY_BASE + 0x20a0) 1269#define VLV_IIR (VLV_DISPLAY_BASE + 0x20a4) 1270#define VLV_IMR (VLV_DISPLAY_BASE + 0x20a8) 1271#define VLV_ISR (VLV_DISPLAY_BASE + 0x20ac) 1272#define VLV_PCBR (VLV_DISPLAY_BASE + 0x2120) 1273#define VLV_PCBR_ADDR_SHIFT 12 1274 1275#define DISPLAY_PLANE_FLIP_PENDING(plane) (1<<(11-(plane))) /* A and B only */ 1276#define EIR 0x020b0 1277#define EMR 0x020b4 1278#define ESR 0x020b8 1279#define GM45_ERROR_PAGE_TABLE (1<<5) 1280#define GM45_ERROR_MEM_PRIV (1<<4) 1281#define I915_ERROR_PAGE_TABLE (1<<4) 1282#define GM45_ERROR_CP_PRIV (1<<3) 1283#define I915_ERROR_MEMORY_REFRESH (1<<1) 1284#define I915_ERROR_INSTRUCTION (1<<0) 1285#define INSTPM 0x020c0 1286#define INSTPM_SELF_EN (1<<12) /* 915GM only */ 1287#define INSTPM_AGPBUSY_INT_EN (1<<11) /* gen3: when disabled, pending interrupts 1288 will not assert AGPBUSY# and will only 1289 be delivered when out of C3. */ 1290#define INSTPM_FORCE_ORDERING (1<<7) /* GEN6+ */ 1291#define INSTPM_TLB_INVALIDATE (1<<9) 1292#define INSTPM_SYNC_FLUSH (1<<5) 1293#define ACTHD 0x020c8 1294#define MEM_MODE 0x020cc 1295#define MEM_DISPLAY_B_TRICKLE_FEED_DISABLE (1<<3) /* 830 only */ 1296#define MEM_DISPLAY_A_TRICKLE_FEED_DISABLE (1<<2) /* 830/845 only */ 1297#define MEM_DISPLAY_TRICKLE_FEED_DISABLE (1<<2) /* 85x only */ 1298#define FW_BLC 0x020d8 1299#define FW_BLC2 0x020dc 1300#define FW_BLC_SELF 0x020e0 /* 915+ only */ 1301#define FW_BLC_SELF_EN_MASK (1<<31) 1302#define FW_BLC_SELF_FIFO_MASK (1<<16) /* 945 only */ 1303#define FW_BLC_SELF_EN (1<<15) /* 945 only */ 1304#define MM_BURST_LENGTH 0x00700000 1305#define MM_FIFO_WATERMARK 0x0001F000 1306#define LM_BURST_LENGTH 0x00000700 1307#define LM_FIFO_WATERMARK 0x0000001F 1308#define MI_ARB_STATE 0x020e4 /* 915+ only */ 1309 1310/* Make render/texture TLB fetches lower priorty than associated data 1311 * fetches. This is not turned on by default 1312 */ 1313#define MI_ARB_RENDER_TLB_LOW_PRIORITY (1 << 15) 1314 1315/* Isoch request wait on GTT enable (Display A/B/C streams). 1316 * Make isoch requests stall on the TLB update. May cause 1317 * display underruns (test mode only) 1318 */ 1319#define MI_ARB_ISOCH_WAIT_GTT (1 << 14) 1320 1321/* Block grant count for isoch requests when block count is 1322 * set to a finite value. 1323 */ 1324#define MI_ARB_BLOCK_GRANT_MASK (3 << 12) 1325#define MI_ARB_BLOCK_GRANT_8 (0 << 12) /* for 3 display planes */ 1326#define MI_ARB_BLOCK_GRANT_4 (1 << 12) /* for 2 display planes */ 1327#define MI_ARB_BLOCK_GRANT_2 (2 << 12) /* for 1 display plane */ 1328#define MI_ARB_BLOCK_GRANT_0 (3 << 12) /* don't use */ 1329 1330/* Enable render writes to complete in C2/C3/C4 power states. 1331 * If this isn't enabled, render writes are prevented in low 1332 * power states. That seems bad to me. 1333 */ 1334#define MI_ARB_C3_LP_WRITE_ENABLE (1 << 11) 1335 1336/* This acknowledges an async flip immediately instead 1337 * of waiting for 2TLB fetches. 1338 */ 1339#define MI_ARB_ASYNC_FLIP_ACK_IMMEDIATE (1 << 10) 1340 1341/* Enables non-sequential data reads through arbiter 1342 */ 1343#define MI_ARB_DUAL_DATA_PHASE_DISABLE (1 << 9) 1344 1345/* Disable FSB snooping of cacheable write cycles from binner/render 1346 * command stream 1347 */ 1348#define MI_ARB_CACHE_SNOOP_DISABLE (1 << 8) 1349 1350/* Arbiter time slice for non-isoch streams */ 1351#define MI_ARB_TIME_SLICE_MASK (7 << 5) 1352#define MI_ARB_TIME_SLICE_1 (0 << 5) 1353#define MI_ARB_TIME_SLICE_2 (1 << 5) 1354#define MI_ARB_TIME_SLICE_4 (2 << 5) 1355#define MI_ARB_TIME_SLICE_6 (3 << 5) 1356#define MI_ARB_TIME_SLICE_8 (4 << 5) 1357#define MI_ARB_TIME_SLICE_10 (5 << 5) 1358#define MI_ARB_TIME_SLICE_14 (6 << 5) 1359#define MI_ARB_TIME_SLICE_16 (7 << 5) 1360 1361/* Low priority grace period page size */ 1362#define MI_ARB_LOW_PRIORITY_GRACE_4KB (0 << 4) /* default */ 1363#define MI_ARB_LOW_PRIORITY_GRACE_8KB (1 << 4) 1364 1365/* Disable display A/B trickle feed */ 1366#define MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE (1 << 2) 1367 1368/* Set display plane priority */ 1369#define MI_ARB_DISPLAY_PRIORITY_A_B (0 << 0) /* display A > display B */ 1370#define MI_ARB_DISPLAY_PRIORITY_B_A (1 << 0) /* display B > display A */ 1371 1372#define MI_STATE 0x020e4 /* gen2 only */ 1373#define MI_AGPBUSY_INT_EN (1 << 1) /* 85x only */ 1374#define MI_AGPBUSY_830_MODE (1 << 0) /* 85x only */ 1375 1376#define CACHE_MODE_0 0x02120 /* 915+ only */ 1377#define CM0_PIPELINED_RENDER_FLUSH_DISABLE (1<<8) 1378#define CM0_IZ_OPT_DISABLE (1<<6) 1379#define CM0_ZR_OPT_DISABLE (1<<5) 1380#define CM0_STC_EVICT_DISABLE_LRA_SNB (1<<5) 1381#define CM0_DEPTH_EVICT_DISABLE (1<<4) 1382#define CM0_COLOR_EVICT_DISABLE (1<<3) 1383#define CM0_DEPTH_WRITE_DISABLE (1<<1) 1384#define CM0_RC_OP_FLUSH_DISABLE (1<<0) 1385#define GFX_FLSH_CNTL 0x02170 /* 915+ only */ 1386#define GFX_FLSH_CNTL_GEN6 0x101008 1387#define GFX_FLSH_CNTL_EN (1<<0) 1388#define ECOSKPD 0x021d0 1389#define ECO_GATING_CX_ONLY (1<<3) 1390#define ECO_FLIP_DONE (1<<0) 1391 1392#define CACHE_MODE_0_GEN7 0x7000 /* IVB+ */ 1393#define RC_OP_FLUSH_ENABLE (1<<0) 1394#define HIZ_RAW_STALL_OPT_DISABLE (1<<2) 1395#define CACHE_MODE_1 0x7004 /* IVB+ */ 1396#define PIXEL_SUBSPAN_COLLECT_OPT_DISABLE (1<<6) 1397#define GEN8_4x4_STC_OPTIMIZATION_DISABLE (1<<6) 1398 1399#define GEN6_BLITTER_ECOSKPD 0x221d0 1400#define GEN6_BLITTER_LOCK_SHIFT 16 1401#define GEN6_BLITTER_FBC_NOTIFY (1<<3) 1402 1403#define GEN6_RC_SLEEP_PSMI_CONTROL 0x2050 1404#define GEN8_RC_SEMA_IDLE_MSG_DISABLE (1 << 12) 1405#define GEN8_FF_DOP_CLOCK_GATE_DISABLE (1<<10) 1406 1407#define GEN6_BSD_SLEEP_PSMI_CONTROL 0x12050 1408#define GEN6_BSD_SLEEP_MSG_DISABLE (1 << 0) 1409#define GEN6_BSD_SLEEP_FLUSH_DISABLE (1 << 2) 1410#define GEN6_BSD_SLEEP_INDICATOR (1 << 3) 1411#define GEN6_BSD_GO_INDICATOR (1 << 4) 1412 1413/* On modern GEN architectures interrupt control consists of two sets 1414 * of registers. The first set pertains to the ring generating the 1415 * interrupt. The second control is for the functional block generating the 1416 * interrupt. These are PM, GT, DE, etc. 1417 * 1418 * Luckily *knocks on wood* all the ring interrupt bits match up with the 1419 * GT interrupt bits, so we don't need to duplicate the defines. 1420 * 1421 * These defines should cover us well from SNB->HSW with minor exceptions 1422 * it can also work on ILK. 1423 */ 1424#define GT_BLT_FLUSHDW_NOTIFY_INTERRUPT (1 << 26) 1425#define GT_BLT_CS_ERROR_INTERRUPT (1 << 25) 1426#define GT_BLT_USER_INTERRUPT (1 << 22) 1427#define GT_BSD_CS_ERROR_INTERRUPT (1 << 15) 1428#define GT_BSD_USER_INTERRUPT (1 << 12) 1429#define GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1 (1 << 11) /* hsw+; rsvd on snb, ivb, vlv */ 1430#define GT_CONTEXT_SWITCH_INTERRUPT (1 << 8) 1431#define GT_RENDER_L3_PARITY_ERROR_INTERRUPT (1 << 5) /* !snb */ 1432#define GT_RENDER_PIPECTL_NOTIFY_INTERRUPT (1 << 4) 1433#define GT_RENDER_CS_MASTER_ERROR_INTERRUPT (1 << 3) 1434#define GT_RENDER_SYNC_STATUS_INTERRUPT (1 << 2) 1435#define GT_RENDER_DEBUG_INTERRUPT (1 << 1) 1436#define GT_RENDER_USER_INTERRUPT (1 << 0) 1437 1438#define PM_VEBOX_CS_ERROR_INTERRUPT (1 << 12) /* hsw+ */ 1439#define PM_VEBOX_USER_INTERRUPT (1 << 10) /* hsw+ */ 1440 1441#define GT_PARITY_ERROR(dev) \ 1442 (GT_RENDER_L3_PARITY_ERROR_INTERRUPT | \ 1443 (IS_HASWELL(dev) ? GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1 : 0)) 1444 1445/* These are all the "old" interrupts */ 1446#define ILK_BSD_USER_INTERRUPT (1<<5) 1447 1448#define I915_PM_INTERRUPT (1<<31) 1449#define I915_ISP_INTERRUPT (1<<22) 1450#define I915_LPE_PIPE_B_INTERRUPT (1<<21) 1451#define I915_LPE_PIPE_A_INTERRUPT (1<<20) 1452#define I915_MIPIB_INTERRUPT (1<<19) 1453#define I915_MIPIA_INTERRUPT (1<<18) 1454#define I915_PIPE_CONTROL_NOTIFY_INTERRUPT (1<<18) 1455#define I915_DISPLAY_PORT_INTERRUPT (1<<17) 1456#define I915_DISPLAY_PIPE_C_HBLANK_INTERRUPT (1<<16) 1457#define I915_MASTER_ERROR_INTERRUPT (1<<15) 1458#define I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT (1<<15) 1459#define I915_DISPLAY_PIPE_B_HBLANK_INTERRUPT (1<<14) 1460#define I915_GMCH_THERMAL_SENSOR_EVENT_INTERRUPT (1<<14) /* p-state */ 1461#define I915_DISPLAY_PIPE_A_HBLANK_INTERRUPT (1<<13) 1462#define I915_HWB_OOM_INTERRUPT (1<<13) 1463#define I915_LPE_PIPE_C_INTERRUPT (1<<12) 1464#define I915_SYNC_STATUS_INTERRUPT (1<<12) 1465#define I915_MISC_INTERRUPT (1<<11) 1466#define I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT (1<<11) 1467#define I915_DISPLAY_PIPE_C_VBLANK_INTERRUPT (1<<10) 1468#define I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT (1<<10) 1469#define I915_DISPLAY_PIPE_C_EVENT_INTERRUPT (1<<9) 1470#define I915_OVERLAY_PLANE_FLIP_PENDING_INTERRUPT (1<<9) 1471#define I915_DISPLAY_PIPE_C_DPBM_INTERRUPT (1<<8) 1472#define I915_DISPLAY_PLANE_C_FLIP_PENDING_INTERRUPT (1<<8) 1473#define I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT (1<<7) 1474#define I915_DISPLAY_PIPE_A_EVENT_INTERRUPT (1<<6) 1475#define I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT (1<<5) 1476#define I915_DISPLAY_PIPE_B_EVENT_INTERRUPT (1<<4) 1477#define I915_DISPLAY_PIPE_A_DPBM_INTERRUPT (1<<3) 1478#define I915_DISPLAY_PIPE_B_DPBM_INTERRUPT (1<<2) 1479#define I915_DEBUG_INTERRUPT (1<<2) 1480#define I915_WINVALID_INTERRUPT (1<<1) 1481#define I915_USER_INTERRUPT (1<<1) 1482#define I915_ASLE_INTERRUPT (1<<0) 1483#define I915_BSD_USER_INTERRUPT (1<<25) 1484 1485#define GEN6_BSD_RNCID 0x12198 1486 1487#define GEN7_FF_THREAD_MODE 0x20a0 1488#define GEN7_FF_SCHED_MASK 0x0077070 1489#define GEN8_FF_DS_REF_CNT_FFME (1 << 19) 1490#define GEN7_FF_TS_SCHED_HS1 (0x5<<16) 1491#define GEN7_FF_TS_SCHED_HS0 (0x3<<16) 1492#define GEN7_FF_TS_SCHED_LOAD_BALANCE (0x1<<16) 1493#define GEN7_FF_TS_SCHED_HW (0x0<<16) /* Default */ 1494#define GEN7_FF_VS_REF_CNT_FFME (1 << 15) 1495#define GEN7_FF_VS_SCHED_HS1 (0x5<<12) 1496#define GEN7_FF_VS_SCHED_HS0 (0x3<<12) 1497#define GEN7_FF_VS_SCHED_LOAD_BALANCE (0x1<<12) /* Default */ 1498#define GEN7_FF_VS_SCHED_HW (0x0<<12) 1499#define GEN7_FF_DS_SCHED_HS1 (0x5<<4) 1500#define GEN7_FF_DS_SCHED_HS0 (0x3<<4) 1501#define GEN7_FF_DS_SCHED_LOAD_BALANCE (0x1<<4) /* Default */ 1502#define GEN7_FF_DS_SCHED_HW (0x0<<4) 1503 1504/* 1505 * Framebuffer compression (915+ only) 1506 */ 1507 1508#define FBC_CFB_BASE 0x03200 /* 4k page aligned */ 1509#define FBC_LL_BASE 0x03204 /* 4k page aligned */ 1510#define FBC_CONTROL 0x03208 1511#define FBC_CTL_EN (1<<31) 1512#define FBC_CTL_PERIODIC (1<<30) 1513#define FBC_CTL_INTERVAL_SHIFT (16) 1514#define FBC_CTL_UNCOMPRESSIBLE (1<<14) 1515#define FBC_CTL_C3_IDLE (1<<13) 1516#define FBC_CTL_STRIDE_SHIFT (5) 1517#define FBC_CTL_FENCENO_SHIFT (0) 1518#define FBC_COMMAND 0x0320c 1519#define FBC_CMD_COMPRESS (1<<0) 1520#define FBC_STATUS 0x03210 1521#define FBC_STAT_COMPRESSING (1<<31) 1522#define FBC_STAT_COMPRESSED (1<<30) 1523#define FBC_STAT_MODIFIED (1<<29) 1524#define FBC_STAT_CURRENT_LINE_SHIFT (0) 1525#define FBC_CONTROL2 0x03214 1526#define FBC_CTL_FENCE_DBL (0<<4) 1527#define FBC_CTL_IDLE_IMM (0<<2) 1528#define FBC_CTL_IDLE_FULL (1<<2) 1529#define FBC_CTL_IDLE_LINE (2<<2) 1530#define FBC_CTL_IDLE_DEBUG (3<<2) 1531#define FBC_CTL_CPU_FENCE (1<<1) 1532#define FBC_CTL_PLANE(plane) ((plane)<<0) 1533#define FBC_FENCE_OFF 0x03218 /* BSpec typo has 321Bh */ 1534#define FBC_TAG 0x03300 1535 1536#define FBC_LL_SIZE (1536) 1537 1538/* Framebuffer compression for GM45+ */ 1539#define DPFC_CB_BASE 0x3200 1540#define DPFC_CONTROL 0x3208 1541#define DPFC_CTL_EN (1<<31) 1542#define DPFC_CTL_PLANE(plane) ((plane)<<30) 1543#define IVB_DPFC_CTL_PLANE(plane) ((plane)<<29) 1544#define DPFC_CTL_FENCE_EN (1<<29) 1545#define IVB_DPFC_CTL_FENCE_EN (1<<28) 1546#define DPFC_CTL_PERSISTENT_MODE (1<<25) 1547#define DPFC_SR_EN (1<<10) 1548#define DPFC_CTL_LIMIT_1X (0<<6) 1549#define DPFC_CTL_LIMIT_2X (1<<6) 1550#define DPFC_CTL_LIMIT_4X (2<<6) 1551#define DPFC_RECOMP_CTL 0x320c 1552#define DPFC_RECOMP_STALL_EN (1<<27) 1553#define DPFC_RECOMP_STALL_WM_SHIFT (16) 1554#define DPFC_RECOMP_STALL_WM_MASK (0x07ff0000) 1555#define DPFC_RECOMP_TIMER_COUNT_SHIFT (0) 1556#define DPFC_RECOMP_TIMER_COUNT_MASK (0x0000003f) 1557#define DPFC_STATUS 0x3210 1558#define DPFC_INVAL_SEG_SHIFT (16) 1559#define DPFC_INVAL_SEG_MASK (0x07ff0000) 1560#define DPFC_COMP_SEG_SHIFT (0) 1561#define DPFC_COMP_SEG_MASK (0x000003ff) 1562#define DPFC_STATUS2 0x3214 1563#define DPFC_FENCE_YOFF 0x3218 1564#define DPFC_CHICKEN 0x3224 1565#define DPFC_HT_MODIFY (1<<31) 1566 1567/* Framebuffer compression for Ironlake */ 1568#define ILK_DPFC_CB_BASE 0x43200 1569#define ILK_DPFC_CONTROL 0x43208 1570#define FBC_CTL_FALSE_COLOR (1<<10) 1571/* The bit 28-8 is reserved */ 1572#define DPFC_RESERVED (0x1FFFFF00) 1573#define ILK_DPFC_RECOMP_CTL 0x4320c 1574#define ILK_DPFC_STATUS 0x43210 1575#define ILK_DPFC_FENCE_YOFF 0x43218 1576#define ILK_DPFC_CHICKEN 0x43224 1577#define ILK_FBC_RT_BASE 0x2128 1578#define ILK_FBC_RT_VALID (1<<0) 1579#define SNB_FBC_FRONT_BUFFER (1<<1) 1580 1581#define ILK_DISPLAY_CHICKEN1 0x42000 1582#define ILK_FBCQ_DIS (1<<22) 1583#define ILK_PABSTRETCH_DIS (1<<21) 1584 1585 1586/* 1587 * Framebuffer compression for Sandybridge 1588 * 1589 * The following two registers are of type GTTMMADR 1590 */ 1591#define SNB_DPFC_CTL_SA 0x100100 1592#define SNB_CPU_FENCE_ENABLE (1<<29) 1593#define DPFC_CPU_FENCE_OFFSET 0x100104 1594 1595/* Framebuffer compression for Ivybridge */ 1596#define IVB_FBC_RT_BASE 0x7020 1597 1598#define IPS_CTL 0x43408 1599#define IPS_ENABLE (1 << 31) 1600 1601#define MSG_FBC_REND_STATE 0x50380 1602#define FBC_REND_NUKE (1<<2) 1603#define FBC_REND_CACHE_CLEAN (1<<1) 1604 1605/* 1606 * GPIO regs 1607 */ 1608#define GPIOA 0x5010 1609#define GPIOB 0x5014 1610#define GPIOC 0x5018 1611#define GPIOD 0x501c 1612#define GPIOE 0x5020 1613#define GPIOF 0x5024 1614#define GPIOG 0x5028 1615#define GPIOH 0x502c 1616# define GPIO_CLOCK_DIR_MASK (1 << 0) 1617# define GPIO_CLOCK_DIR_IN (0 << 1) 1618# define GPIO_CLOCK_DIR_OUT (1 << 1) 1619# define GPIO_CLOCK_VAL_MASK (1 << 2) 1620# define GPIO_CLOCK_VAL_OUT (1 << 3) 1621# define GPIO_CLOCK_VAL_IN (1 << 4) 1622# define GPIO_CLOCK_PULLUP_DISABLE (1 << 5) 1623# define GPIO_DATA_DIR_MASK (1 << 8) 1624# define GPIO_DATA_DIR_IN (0 << 9) 1625# define GPIO_DATA_DIR_OUT (1 << 9) 1626# define GPIO_DATA_VAL_MASK (1 << 10) 1627# define GPIO_DATA_VAL_OUT (1 << 11) 1628# define GPIO_DATA_VAL_IN (1 << 12) 1629# define GPIO_DATA_PULLUP_DISABLE (1 << 13) 1630 1631#define GMBUS0 0x5100 /* clock/port select */ 1632#define GMBUS_RATE_100KHZ (0<<8) 1633#define GMBUS_RATE_50KHZ (1<<8) 1634#define GMBUS_RATE_400KHZ (2<<8) /* reserved on Pineview */ 1635#define GMBUS_RATE_1MHZ (3<<8) /* reserved on Pineview */ 1636#define GMBUS_HOLD_EXT (1<<7) /* 300ns hold time, rsvd on Pineview */ 1637#define GMBUS_PORT_DISABLED 0 1638#define GMBUS_PORT_SSC 1 1639#define GMBUS_PORT_VGADDC 2 1640#define GMBUS_PORT_PANEL 3 1641#define GMBUS_PORT_DPD_CHV 3 /* HDMID_CHV */ 1642#define GMBUS_PORT_DPC 4 /* HDMIC */ 1643#define GMBUS_PORT_DPB 5 /* SDVO, HDMIB */ 1644#define GMBUS_PORT_DPD 6 /* HDMID */ 1645#define GMBUS_PORT_RESERVED 7 /* 7 reserved */ 1646#define GMBUS_NUM_PORTS (GMBUS_PORT_DPD - GMBUS_PORT_SSC + 1) 1647#define GMBUS1 0x5104 /* command/status */ 1648#define GMBUS_SW_CLR_INT (1<<31) 1649#define GMBUS_SW_RDY (1<<30) 1650#define GMBUS_ENT (1<<29) /* enable timeout */ 1651#define GMBUS_CYCLE_NONE (0<<25) 1652#define GMBUS_CYCLE_WAIT (1<<25) 1653#define GMBUS_CYCLE_INDEX (2<<25) 1654#define GMBUS_CYCLE_STOP (4<<25) 1655#define GMBUS_BYTE_COUNT_SHIFT 16 1656#define GMBUS_SLAVE_INDEX_SHIFT 8 1657#define GMBUS_SLAVE_ADDR_SHIFT 1 1658#define GMBUS_SLAVE_READ (1<<0) 1659#define GMBUS_SLAVE_WRITE (0<<0) 1660#define GMBUS2 0x5108 /* status */ 1661#define GMBUS_INUSE (1<<15) 1662#define GMBUS_HW_WAIT_PHASE (1<<14) 1663#define GMBUS_STALL_TIMEOUT (1<<13) 1664#define GMBUS_INT (1<<12) 1665#define GMBUS_HW_RDY (1<<11) 1666#define GMBUS_SATOER (1<<10) 1667#define GMBUS_ACTIVE (1<<9) 1668#define GMBUS3 0x510c /* data buffer bytes 3-0 */ 1669#define GMBUS4 0x5110 /* interrupt mask (Pineview+) */ 1670#define GMBUS_SLAVE_TIMEOUT_EN (1<<4) 1671#define GMBUS_NAK_EN (1<<3) 1672#define GMBUS_IDLE_EN (1<<2) 1673#define GMBUS_HW_WAIT_EN (1<<1) 1674#define GMBUS_HW_RDY_EN (1<<0) 1675#define GMBUS5 0x5120 /* byte index */ 1676#define GMBUS_2BYTE_INDEX_EN (1<<31) 1677 1678/* 1679 * Clock control & power management 1680 */ 1681#define _DPLL_A (dev_priv->info.display_mmio_offset + 0x6014) 1682#define _DPLL_B (dev_priv->info.display_mmio_offset + 0x6018) 1683#define _CHV_DPLL_C (dev_priv->info.display_mmio_offset + 0x6030) 1684#define DPLL(pipe) _PIPE3((pipe), _DPLL_A, _DPLL_B, _CHV_DPLL_C) 1685 1686#define VGA0 0x6000 1687#define VGA1 0x6004 1688#define VGA_PD 0x6010 1689#define VGA0_PD_P2_DIV_4 (1 << 7) 1690#define VGA0_PD_P1_DIV_2 (1 << 5) 1691#define VGA0_PD_P1_SHIFT 0 1692#define VGA0_PD_P1_MASK (0x1f << 0) 1693#define VGA1_PD_P2_DIV_4 (1 << 15) 1694#define VGA1_PD_P1_DIV_2 (1 << 13) 1695#define VGA1_PD_P1_SHIFT 8 1696#define VGA1_PD_P1_MASK (0x1f << 8) 1697#define DPLL_VCO_ENABLE (1 << 31) 1698#define DPLL_SDVO_HIGH_SPEED (1 << 30) 1699#define DPLL_DVO_2X_MODE (1 << 30) 1700#define DPLL_EXT_BUFFER_ENABLE_VLV (1 << 30) 1701#define DPLL_SYNCLOCK_ENABLE (1 << 29) 1702#define DPLL_REFA_CLK_ENABLE_VLV (1 << 29) 1703#define DPLL_VGA_MODE_DIS (1 << 28) 1704#define DPLLB_MODE_DAC_SERIAL (1 << 26) /* i915 */ 1705#define DPLLB_MODE_LVDS (2 << 26) /* i915 */ 1706#define DPLL_MODE_MASK (3 << 26) 1707#define DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 (0 << 24) /* i915 */ 1708#define DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 (1 << 24) /* i915 */ 1709#define DPLLB_LVDS_P2_CLOCK_DIV_14 (0 << 24) /* i915 */ 1710#define DPLLB_LVDS_P2_CLOCK_DIV_7 (1 << 24) /* i915 */ 1711#define DPLL_P2_CLOCK_DIV_MASK 0x03000000 /* i915 */ 1712#define DPLL_FPA01_P1_POST_DIV_MASK 0x00ff0000 /* i915 */ 1713#define DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW 0x00ff8000 /* Pineview */ 1714#define DPLL_LOCK_VLV (1<<15) 1715#define DPLL_INTEGRATED_CRI_CLK_VLV (1<<14) 1716#define DPLL_INTEGRATED_CLOCK_VLV (1<<13) 1717#define DPLL_SSC_REF_CLOCK_CHV (1<<13) 1718#define DPLL_PORTC_READY_MASK (0xf << 4) 1719#define DPLL_PORTB_READY_MASK (0xf) 1720 1721#define DPLL_FPA01_P1_POST_DIV_MASK_I830 0x001f0000 1722 1723/* Additional CHV pll/phy registers */ 1724#define DPIO_PHY_STATUS (VLV_DISPLAY_BASE + 0x6240) 1725#define DPLL_PORTD_READY_MASK (0xf) 1726#define DISPLAY_PHY_CONTROL (VLV_DISPLAY_BASE + 0x60100) 1727#define PHY_COM_LANE_RESET_DEASSERT(phy) (1 << (phy)) 1728#define DISPLAY_PHY_STATUS (VLV_DISPLAY_BASE + 0x60104) 1729#define PHY_POWERGOOD(phy) (((phy) == DPIO_PHY0) ? (1<<31) : (1<<30)) 1730 1731/* 1732 * The i830 generation, in LVDS mode, defines P1 as the bit number set within 1733 * this field (only one bit may be set). 1734 */ 1735#define DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS 0x003f0000 1736#define DPLL_FPA01_P1_POST_DIV_SHIFT 16 1737#define DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW 15 1738/* i830, required in DVO non-gang */ 1739#define PLL_P2_DIVIDE_BY_4 (1 << 23) 1740#define PLL_P1_DIVIDE_BY_TWO (1 << 21) /* i830 */ 1741#define PLL_REF_INPUT_DREFCLK (0 << 13) 1742#define PLL_REF_INPUT_TVCLKINA (1 << 13) /* i830 */ 1743#define PLL_REF_INPUT_TVCLKINBC (2 << 13) /* SDVO TVCLKIN */ 1744#define PLLB_REF_INPUT_SPREADSPECTRUMIN (3 << 13) 1745#define PLL_REF_INPUT_MASK (3 << 13) 1746#define PLL_LOAD_PULSE_PHASE_SHIFT 9 1747/* Ironlake */ 1748# define PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT 9 1749# define PLL_REF_SDVO_HDMI_MULTIPLIER_MASK (7 << 9) 1750# define PLL_REF_SDVO_HDMI_MULTIPLIER(x) (((x)-1) << 9) 1751# define DPLL_FPA1_P1_POST_DIV_SHIFT 0 1752# define DPLL_FPA1_P1_POST_DIV_MASK 0xff 1753 1754/* 1755 * Parallel to Serial Load Pulse phase selection. 1756 * Selects the phase for the 10X DPLL clock for the PCIe 1757 * digital display port. The range is 4 to 13; 10 or more 1758 * is just a flip delay. The default is 6 1759 */ 1760#define PLL_LOAD_PULSE_PHASE_MASK (0xf << PLL_LOAD_PULSE_PHASE_SHIFT) 1761#define DISPLAY_RATE_SELECT_FPA1 (1 << 8) 1762/* 1763 * SDVO multiplier for 945G/GM. Not used on 965. 1764 */ 1765#define SDVO_MULTIPLIER_MASK 0x000000ff 1766#define SDVO_MULTIPLIER_SHIFT_HIRES 4 1767#define SDVO_MULTIPLIER_SHIFT_VGA 0 1768 1769#define _DPLL_A_MD (dev_priv->info.display_mmio_offset + 0x601c) 1770#define _DPLL_B_MD (dev_priv->info.display_mmio_offset + 0x6020) 1771#define _CHV_DPLL_C_MD (dev_priv->info.display_mmio_offset + 0x603c) 1772#define DPLL_MD(pipe) _PIPE3((pipe), _DPLL_A_MD, _DPLL_B_MD, _CHV_DPLL_C_MD) 1773 1774/* 1775 * UDI pixel divider, controlling how many pixels are stuffed into a packet. 1776 * 1777 * Value is pixels minus 1. Must be set to 1 pixel for SDVO. 1778 */ 1779#define DPLL_MD_UDI_DIVIDER_MASK 0x3f000000 1780#define DPLL_MD_UDI_DIVIDER_SHIFT 24 1781/* UDI pixel divider for VGA, same as DPLL_MD_UDI_DIVIDER_MASK. */ 1782#define DPLL_MD_VGA_UDI_DIVIDER_MASK 0x003f0000 1783#define DPLL_MD_VGA_UDI_DIVIDER_SHIFT 16 1784/* 1785 * SDVO/UDI pixel multiplier. 1786 * 1787 * SDVO requires that the bus clock rate be between 1 and 2 Ghz, and the bus 1788 * clock rate is 10 times the DPLL clock. At low resolution/refresh rate 1789 * modes, the bus rate would be below the limits, so SDVO allows for stuffing 1790 * dummy bytes in the datastream at an increased clock rate, with both sides of 1791 * the link knowing how many bytes are fill. 1792 * 1793 * So, for a mode with a dotclock of 65Mhz, we would want to double the clock 1794 * rate to 130Mhz to get a bus rate of 1.30Ghz. The DPLL clock rate would be 1795 * set to 130Mhz, and the SDVO multiplier set to 2x in this register and 1796 * through an SDVO command. 1797 * 1798 * This register field has values of multiplication factor minus 1, with 1799 * a maximum multiplier of 5 for SDVO. 1800 */ 1801#define DPLL_MD_UDI_MULTIPLIER_MASK 0x00003f00 1802#define DPLL_MD_UDI_MULTIPLIER_SHIFT 8 1803/* 1804 * SDVO/UDI pixel multiplier for VGA, same as DPLL_MD_UDI_MULTIPLIER_MASK. 1805 * This best be set to the default value (3) or the CRT won't work. No, 1806 * I don't entirely understand what this does... 1807 */ 1808#define DPLL_MD_VGA_UDI_MULTIPLIER_MASK 0x0000003f 1809#define DPLL_MD_VGA_UDI_MULTIPLIER_SHIFT 0 1810 1811#define _FPA0 0x06040 1812#define _FPA1 0x06044 1813#define _FPB0 0x06048 1814#define _FPB1 0x0604c 1815#define FP0(pipe) _PIPE(pipe, _FPA0, _FPB0) 1816#define FP1(pipe) _PIPE(pipe, _FPA1, _FPB1) 1817#define FP_N_DIV_MASK 0x003f0000 1818#define FP_N_PINEVIEW_DIV_MASK 0x00ff0000 1819#define FP_N_DIV_SHIFT 16 1820#define FP_M1_DIV_MASK 0x00003f00 1821#define FP_M1_DIV_SHIFT 8 1822#define FP_M2_DIV_MASK 0x0000003f 1823#define FP_M2_PINEVIEW_DIV_MASK 0x000000ff 1824#define FP_M2_DIV_SHIFT 0 1825#define DPLL_TEST 0x606c 1826#define DPLLB_TEST_SDVO_DIV_1 (0 << 22) 1827#define DPLLB_TEST_SDVO_DIV_2 (1 << 22) 1828#define DPLLB_TEST_SDVO_DIV_4 (2 << 22) 1829#define DPLLB_TEST_SDVO_DIV_MASK (3 << 22) 1830#define DPLLB_TEST_N_BYPASS (1 << 19) 1831#define DPLLB_TEST_M_BYPASS (1 << 18) 1832#define DPLLB_INPUT_BUFFER_ENABLE (1 << 16) 1833#define DPLLA_TEST_N_BYPASS (1 << 3) 1834#define DPLLA_TEST_M_BYPASS (1 << 2) 1835#define DPLLA_INPUT_BUFFER_ENABLE (1 << 0) 1836#define D_STATE 0x6104 1837#define DSTATE_GFX_RESET_I830 (1<<6) 1838#define DSTATE_PLL_D3_OFF (1<<3) 1839#define DSTATE_GFX_CLOCK_GATING (1<<1) 1840#define DSTATE_DOT_CLOCK_GATING (1<<0) 1841#define DSPCLK_GATE_D (dev_priv->info.display_mmio_offset + 0x6200) 1842# define DPUNIT_B_CLOCK_GATE_DISABLE (1 << 30) /* 965 */ 1843# define VSUNIT_CLOCK_GATE_DISABLE (1 << 29) /* 965 */ 1844# define VRHUNIT_CLOCK_GATE_DISABLE (1 << 28) /* 965 */ 1845# define VRDUNIT_CLOCK_GATE_DISABLE (1 << 27) /* 965 */ 1846# define AUDUNIT_CLOCK_GATE_DISABLE (1 << 26) /* 965 */ 1847# define DPUNIT_A_CLOCK_GATE_DISABLE (1 << 25) /* 965 */ 1848# define DPCUNIT_CLOCK_GATE_DISABLE (1 << 24) /* 965 */ 1849# define TVRUNIT_CLOCK_GATE_DISABLE (1 << 23) /* 915-945 */ 1850# define TVCUNIT_CLOCK_GATE_DISABLE (1 << 22) /* 915-945 */ 1851# define TVFUNIT_CLOCK_GATE_DISABLE (1 << 21) /* 915-945 */ 1852# define TVEUNIT_CLOCK_GATE_DISABLE (1 << 20) /* 915-945 */ 1853# define DVSUNIT_CLOCK_GATE_DISABLE (1 << 19) /* 915-945 */ 1854# define DSSUNIT_CLOCK_GATE_DISABLE (1 << 18) /* 915-945 */ 1855# define DDBUNIT_CLOCK_GATE_DISABLE (1 << 17) /* 915-945 */ 1856# define DPRUNIT_CLOCK_GATE_DISABLE (1 << 16) /* 915-945 */ 1857# define DPFUNIT_CLOCK_GATE_DISABLE (1 << 15) /* 915-945 */ 1858# define DPBMUNIT_CLOCK_GATE_DISABLE (1 << 14) /* 915-945 */ 1859# define DPLSUNIT_CLOCK_GATE_DISABLE (1 << 13) /* 915-945 */ 1860# define DPLUNIT_CLOCK_GATE_DISABLE (1 << 12) /* 915-945 */ 1861# define DPOUNIT_CLOCK_GATE_DISABLE (1 << 11) 1862# define DPBUNIT_CLOCK_GATE_DISABLE (1 << 10) 1863# define DCUNIT_CLOCK_GATE_DISABLE (1 << 9) 1864# define DPUNIT_CLOCK_GATE_DISABLE (1 << 8) 1865# define VRUNIT_CLOCK_GATE_DISABLE (1 << 7) /* 915+: reserved */ 1866# define OVHUNIT_CLOCK_GATE_DISABLE (1 << 6) /* 830-865 */ 1867# define DPIOUNIT_CLOCK_GATE_DISABLE (1 << 6) /* 915-945 */ 1868# define OVFUNIT_CLOCK_GATE_DISABLE (1 << 5) 1869# define OVBUNIT_CLOCK_GATE_DISABLE (1 << 4) 1870/* 1871 * This bit must be set on the 830 to prevent hangs when turning off the 1872 * overlay scaler. 1873 */ 1874# define OVRUNIT_CLOCK_GATE_DISABLE (1 << 3) 1875# define OVCUNIT_CLOCK_GATE_DISABLE (1 << 2) 1876# define OVUUNIT_CLOCK_GATE_DISABLE (1 << 1) 1877# define ZVUNIT_CLOCK_GATE_DISABLE (1 << 0) /* 830 */ 1878# define OVLUNIT_CLOCK_GATE_DISABLE (1 << 0) /* 845,865 */ 1879 1880#define RENCLK_GATE_D1 0x6204 1881# define BLITTER_CLOCK_GATE_DISABLE (1 << 13) /* 945GM only */ 1882# define MPEG_CLOCK_GATE_DISABLE (1 << 12) /* 945GM only */ 1883# define PC_FE_CLOCK_GATE_DISABLE (1 << 11) 1884# define PC_BE_CLOCK_GATE_DISABLE (1 << 10) 1885# define WINDOWER_CLOCK_GATE_DISABLE (1 << 9) 1886# define INTERPOLATOR_CLOCK_GATE_DISABLE (1 << 8) 1887# define COLOR_CALCULATOR_CLOCK_GATE_DISABLE (1 << 7) 1888# define MOTION_COMP_CLOCK_GATE_DISABLE (1 << 6) 1889# define MAG_CLOCK_GATE_DISABLE (1 << 5) 1890/* This bit must be unset on 855,865 */ 1891# define MECI_CLOCK_GATE_DISABLE (1 << 4) 1892# define DCMP_CLOCK_GATE_DISABLE (1 << 3) 1893# define MEC_CLOCK_GATE_DISABLE (1 << 2) 1894# define MECO_CLOCK_GATE_DISABLE (1 << 1) 1895/* This bit must be set on 855,865. */ 1896# define SV_CLOCK_GATE_DISABLE (1 << 0) 1897# define I915_MPEG_CLOCK_GATE_DISABLE (1 << 16) 1898# define I915_VLD_IP_PR_CLOCK_GATE_DISABLE (1 << 15) 1899# define I915_MOTION_COMP_CLOCK_GATE_DISABLE (1 << 14) 1900# define I915_BD_BF_CLOCK_GATE_DISABLE (1 << 13) 1901# define I915_SF_SE_CLOCK_GATE_DISABLE (1 << 12) 1902# define I915_WM_CLOCK_GATE_DISABLE (1 << 11) 1903# define I915_IZ_CLOCK_GATE_DISABLE (1 << 10) 1904# define I915_PI_CLOCK_GATE_DISABLE (1 << 9) 1905# define I915_DI_CLOCK_GATE_DISABLE (1 << 8) 1906# define I915_SH_SV_CLOCK_GATE_DISABLE (1 << 7) 1907# define I915_PL_DG_QC_FT_CLOCK_GATE_DISABLE (1 << 6) 1908# define I915_SC_CLOCK_GATE_DISABLE (1 << 5) 1909# define I915_FL_CLOCK_GATE_DISABLE (1 << 4) 1910# define I915_DM_CLOCK_GATE_DISABLE (1 << 3) 1911# define I915_PS_CLOCK_GATE_DISABLE (1 << 2) 1912# define I915_CC_CLOCK_GATE_DISABLE (1 << 1) 1913# define I915_BY_CLOCK_GATE_DISABLE (1 << 0) 1914 1915# define I965_RCZ_CLOCK_GATE_DISABLE (1 << 30) 1916/* This bit must always be set on 965G/965GM */ 1917# define I965_RCC_CLOCK_GATE_DISABLE (1 << 29) 1918# define I965_RCPB_CLOCK_GATE_DISABLE (1 << 28) 1919# define I965_DAP_CLOCK_GATE_DISABLE (1 << 27) 1920# define I965_ROC_CLOCK_GATE_DISABLE (1 << 26) 1921# define I965_GW_CLOCK_GATE_DISABLE (1 << 25) 1922# define I965_TD_CLOCK_GATE_DISABLE (1 << 24) 1923/* This bit must always be set on 965G */ 1924# define I965_ISC_CLOCK_GATE_DISABLE (1 << 23) 1925# define I965_IC_CLOCK_GATE_DISABLE (1 << 22) 1926# define I965_EU_CLOCK_GATE_DISABLE (1 << 21) 1927# define I965_IF_CLOCK_GATE_DISABLE (1 << 20) 1928# define I965_TC_CLOCK_GATE_DISABLE (1 << 19) 1929# define I965_SO_CLOCK_GATE_DISABLE (1 << 17) 1930# define I965_FBC_CLOCK_GATE_DISABLE (1 << 16) 1931# define I965_MARI_CLOCK_GATE_DISABLE (1 << 15) 1932# define I965_MASF_CLOCK_GATE_DISABLE (1 << 14) 1933# define I965_MAWB_CLOCK_GATE_DISABLE (1 << 13) 1934# define I965_EM_CLOCK_GATE_DISABLE (1 << 12) 1935# define I965_UC_CLOCK_GATE_DISABLE (1 << 11) 1936# define I965_SI_CLOCK_GATE_DISABLE (1 << 6) 1937# define I965_MT_CLOCK_GATE_DISABLE (1 << 5) 1938# define I965_PL_CLOCK_GATE_DISABLE (1 << 4) 1939# define I965_DG_CLOCK_GATE_DISABLE (1 << 3) 1940# define I965_QC_CLOCK_GATE_DISABLE (1 << 2) 1941# define I965_FT_CLOCK_GATE_DISABLE (1 << 1) 1942# define I965_DM_CLOCK_GATE_DISABLE (1 << 0) 1943 1944#define RENCLK_GATE_D2 0x6208 1945#define VF_UNIT_CLOCK_GATE_DISABLE (1 << 9) 1946#define GS_UNIT_CLOCK_GATE_DISABLE (1 << 7) 1947#define CL_UNIT_CLOCK_GATE_DISABLE (1 << 6) 1948 1949#define VDECCLK_GATE_D 0x620C /* g4x only */ 1950#define VCP_UNIT_CLOCK_GATE_DISABLE (1 << 4) 1951 1952#define RAMCLK_GATE_D 0x6210 /* CRL only */ 1953#define DEUC 0x6214 /* CRL only */ 1954 1955#define FW_BLC_SELF_VLV (VLV_DISPLAY_BASE + 0x6500) 1956#define FW_CSPWRDWNEN (1<<15) 1957 1958#define MI_ARB_VLV (VLV_DISPLAY_BASE + 0x6504) 1959 1960#define CZCLK_CDCLK_FREQ_RATIO (VLV_DISPLAY_BASE + 0x6508) 1961#define CDCLK_FREQ_SHIFT 4 1962#define CDCLK_FREQ_MASK (0x1f << CDCLK_FREQ_SHIFT) 1963#define CZCLK_FREQ_MASK 0xf 1964#define GMBUSFREQ_VLV (VLV_DISPLAY_BASE + 0x6510) 1965 1966/* 1967 * Palette regs 1968 */ 1969#define PALETTE_A_OFFSET 0xa000 1970#define PALETTE_B_OFFSET 0xa800 1971#define CHV_PALETTE_C_OFFSET 0xc000 1972#define PALETTE(pipe) (dev_priv->info.palette_offsets[pipe] + \ 1973 dev_priv->info.display_mmio_offset) 1974 1975/* MCH MMIO space */ 1976 1977/* 1978 * MCHBAR mirror. 1979 * 1980 * This mirrors the MCHBAR MMIO space whose location is determined by 1981 * device 0 function 0's pci config register 0x44 or 0x48 and matches it in 1982 * every way. It is not accessible from the CP register read instructions. 1983 * 1984 * Starting from Haswell, you can't write registers using the MCHBAR mirror, 1985 * just read. 1986 */ 1987#define MCHBAR_MIRROR_BASE 0x10000 1988 1989#define MCHBAR_MIRROR_BASE_SNB 0x140000 1990 1991/* Memory controller frequency in MCHBAR for Haswell (possible SNB+) */ 1992#define DCLK (MCHBAR_MIRROR_BASE_SNB + 0x5e04) 1993 1994/* 915-945 and GM965 MCH register controlling DRAM channel access */ 1995#define DCC 0x10200 1996#define DCC_ADDRESSING_MODE_SINGLE_CHANNEL (0 << 0) 1997#define DCC_ADDRESSING_MODE_DUAL_CHANNEL_ASYMMETRIC (1 << 0) 1998#define DCC_ADDRESSING_MODE_DUAL_CHANNEL_INTERLEAVED (2 << 0) 1999#define DCC_ADDRESSING_MODE_MASK (3 << 0) 2000#define DCC_CHANNEL_XOR_DISABLE (1 << 10) 2001#define DCC_CHANNEL_XOR_BIT_17 (1 << 9) 2002 2003/* Pineview MCH register contains DDR3 setting */ 2004#define CSHRDDR3CTL 0x101a8 2005#define CSHRDDR3CTL_DDR3 (1 << 2) 2006 2007/* 965 MCH register controlling DRAM channel configuration */ 2008#define C0DRB3 0x10206 2009#define C1DRB3 0x10606 2010 2011/* snb MCH registers for reading the DRAM channel configuration */ 2012#define MAD_DIMM_C0 (MCHBAR_MIRROR_BASE_SNB + 0x5004) 2013#define MAD_DIMM_C1 (MCHBAR_MIRROR_BASE_SNB + 0x5008) 2014#define MAD_DIMM_C2 (MCHBAR_MIRROR_BASE_SNB + 0x500C) 2015#define MAD_DIMM_ECC_MASK (0x3 << 24) 2016#define MAD_DIMM_ECC_OFF (0x0 << 24) 2017#define MAD_DIMM_ECC_IO_ON_LOGIC_OFF (0x1 << 24) 2018#define MAD_DIMM_ECC_IO_OFF_LOGIC_ON (0x2 << 24) 2019#define MAD_DIMM_ECC_ON (0x3 << 24) 2020#define MAD_DIMM_ENH_INTERLEAVE (0x1 << 22) 2021#define MAD_DIMM_RANK_INTERLEAVE (0x1 << 21) 2022#define MAD_DIMM_B_WIDTH_X16 (0x1 << 20) /* X8 chips if unset */ 2023#define MAD_DIMM_A_WIDTH_X16 (0x1 << 19) /* X8 chips if unset */ 2024#define MAD_DIMM_B_DUAL_RANK (0x1 << 18) 2025#define MAD_DIMM_A_DUAL_RANK (0x1 << 17) 2026#define MAD_DIMM_A_SELECT (0x1 << 16) 2027/* DIMM sizes are in multiples of 256mb. */ 2028#define MAD_DIMM_B_SIZE_SHIFT 8 2029#define MAD_DIMM_B_SIZE_MASK (0xff << MAD_DIMM_B_SIZE_SHIFT) 2030#define MAD_DIMM_A_SIZE_SHIFT 0 2031#define MAD_DIMM_A_SIZE_MASK (0xff << MAD_DIMM_A_SIZE_SHIFT) 2032 2033/* snb MCH registers for priority tuning */ 2034#define MCH_SSKPD (MCHBAR_MIRROR_BASE_SNB + 0x5d10) 2035#define MCH_SSKPD_WM0_MASK 0x3f 2036#define MCH_SSKPD_WM0_VAL 0xc 2037 2038#define MCH_SECP_NRG_STTS (MCHBAR_MIRROR_BASE_SNB + 0x592c) 2039 2040/* Clocking configuration register */ 2041#define CLKCFG 0x10c00 2042#define CLKCFG_FSB_400 (5 << 0) /* hrawclk 100 */ 2043#define CLKCFG_FSB_533 (1 << 0) /* hrawclk 133 */ 2044#define CLKCFG_FSB_667 (3 << 0) /* hrawclk 166 */ 2045#define CLKCFG_FSB_800 (2 << 0) /* hrawclk 200 */ 2046#define CLKCFG_FSB_1067 (6 << 0) /* hrawclk 266 */ 2047#define CLKCFG_FSB_1333 (7 << 0) /* hrawclk 333 */ 2048/* Note, below two are guess */ 2049#define CLKCFG_FSB_1600 (4 << 0) /* hrawclk 400 */ 2050#define CLKCFG_FSB_1600_ALT (0 << 0) /* hrawclk 400 */ 2051#define CLKCFG_FSB_MASK (7 << 0) 2052#define CLKCFG_MEM_533 (1 << 4) 2053#define CLKCFG_MEM_667 (2 << 4) 2054#define CLKCFG_MEM_800 (3 << 4) 2055#define CLKCFG_MEM_MASK (7 << 4) 2056 2057#define TSC1 0x11001 2058#define TSE (1<<0) 2059#define TR1 0x11006 2060#define TSFS 0x11020 2061#define TSFS_SLOPE_MASK 0x0000ff00 2062#define TSFS_SLOPE_SHIFT 8 2063#define TSFS_INTR_MASK 0x000000ff 2064 2065#define CRSTANDVID 0x11100 2066#define PXVFREQ_BASE 0x11110 /* P[0-15]VIDFREQ (0x1114c) (Ironlake) */ 2067#define PXVFREQ_PX_MASK 0x7f000000 2068#define PXVFREQ_PX_SHIFT 24 2069#define VIDFREQ_BASE 0x11110 2070#define VIDFREQ1 0x11110 /* VIDFREQ1-4 (0x1111c) (Cantiga) */ 2071#define VIDFREQ2 0x11114 2072#define VIDFREQ3 0x11118 2073#define VIDFREQ4 0x1111c 2074#define VIDFREQ_P0_MASK 0x1f000000 2075#define VIDFREQ_P0_SHIFT 24 2076#define VIDFREQ_P0_CSCLK_MASK 0x00f00000 2077#define VIDFREQ_P0_CSCLK_SHIFT 20 2078#define VIDFREQ_P0_CRCLK_MASK 0x000f0000 2079#define VIDFREQ_P0_CRCLK_SHIFT 16 2080#define VIDFREQ_P1_MASK 0x00001f00 2081#define VIDFREQ_P1_SHIFT 8 2082#define VIDFREQ_P1_CSCLK_MASK 0x000000f0 2083#define VIDFREQ_P1_CSCLK_SHIFT 4 2084#define VIDFREQ_P1_CRCLK_MASK 0x0000000f 2085#define INTTOEXT_BASE_ILK 0x11300 2086#define INTTOEXT_BASE 0x11120 /* INTTOEXT1-8 (0x1113c) */ 2087#define INTTOEXT_MAP3_SHIFT 24 2088#define INTTOEXT_MAP3_MASK (0x1f << INTTOEXT_MAP3_SHIFT) 2089#define INTTOEXT_MAP2_SHIFT 16 2090#define INTTOEXT_MAP2_MASK (0x1f << INTTOEXT_MAP2_SHIFT) 2091#define INTTOEXT_MAP1_SHIFT 8 2092#define INTTOEXT_MAP1_MASK (0x1f << INTTOEXT_MAP1_SHIFT) 2093#define INTTOEXT_MAP0_SHIFT 0 2094#define INTTOEXT_MAP0_MASK (0x1f << INTTOEXT_MAP0_SHIFT) 2095#define MEMSWCTL 0x11170 /* Ironlake only */ 2096#define MEMCTL_CMD_MASK 0xe000 2097#define MEMCTL_CMD_SHIFT 13 2098#define MEMCTL_CMD_RCLK_OFF 0 2099#define MEMCTL_CMD_RCLK_ON 1 2100#define MEMCTL_CMD_CHFREQ 2 2101#define MEMCTL_CMD_CHVID 3 2102#define MEMCTL_CMD_VMMOFF 4 2103#define MEMCTL_CMD_VMMON 5 2104#define MEMCTL_CMD_STS (1<<12) /* write 1 triggers command, clears 2105 when command complete */ 2106#define MEMCTL_FREQ_MASK 0x0f00 /* jitter, from 0-15 */ 2107#define MEMCTL_FREQ_SHIFT 8 2108#define MEMCTL_SFCAVM (1<<7) 2109#define MEMCTL_TGT_VID_MASK 0x007f 2110#define MEMIHYST 0x1117c 2111#define MEMINTREN 0x11180 /* 16 bits */ 2112#define MEMINT_RSEXIT_EN (1<<8) 2113#define MEMINT_CX_SUPR_EN (1<<7) 2114#define MEMINT_CONT_BUSY_EN (1<<6) 2115#define MEMINT_AVG_BUSY_EN (1<<5) 2116#define MEMINT_EVAL_CHG_EN (1<<4) 2117#define MEMINT_MON_IDLE_EN (1<<3) 2118#define MEMINT_UP_EVAL_EN (1<<2) 2119#define MEMINT_DOWN_EVAL_EN (1<<1) 2120#define MEMINT_SW_CMD_EN (1<<0) 2121#define MEMINTRSTR 0x11182 /* 16 bits */ 2122#define MEM_RSEXIT_MASK 0xc000 2123#define MEM_RSEXIT_SHIFT 14 2124#define MEM_CONT_BUSY_MASK 0x3000 2125#define MEM_CONT_BUSY_SHIFT 12 2126#define MEM_AVG_BUSY_MASK 0x0c00 2127#define MEM_AVG_BUSY_SHIFT 10 2128#define MEM_EVAL_CHG_MASK 0x0300 2129#define MEM_EVAL_BUSY_SHIFT 8 2130#define MEM_MON_IDLE_MASK 0x00c0 2131#define MEM_MON_IDLE_SHIFT 6 2132#define MEM_UP_EVAL_MASK 0x0030 2133#define MEM_UP_EVAL_SHIFT 4 2134#define MEM_DOWN_EVAL_MASK 0x000c 2135#define MEM_DOWN_EVAL_SHIFT 2 2136#define MEM_SW_CMD_MASK 0x0003 2137#define MEM_INT_STEER_GFX 0 2138#define MEM_INT_STEER_CMR 1 2139#define MEM_INT_STEER_SMI 2 2140#define MEM_INT_STEER_SCI 3 2141#define MEMINTRSTS 0x11184 2142#define MEMINT_RSEXIT (1<<7) 2143#define MEMINT_CONT_BUSY (1<<6) 2144#define MEMINT_AVG_BUSY (1<<5) 2145#define MEMINT_EVAL_CHG (1<<4) 2146#define MEMINT_MON_IDLE (1<<3) 2147#define MEMINT_UP_EVAL (1<<2) 2148#define MEMINT_DOWN_EVAL (1<<1) 2149#define MEMINT_SW_CMD (1<<0) 2150#define MEMMODECTL 0x11190 2151#define MEMMODE_BOOST_EN (1<<31) 2152#define MEMMODE_BOOST_FREQ_MASK 0x0f000000 /* jitter for boost, 0-15 */ 2153#define MEMMODE_BOOST_FREQ_SHIFT 24 2154#define MEMMODE_IDLE_MODE_MASK 0x00030000 2155#define MEMMODE_IDLE_MODE_SHIFT 16 2156#define MEMMODE_IDLE_MODE_EVAL 0 2157#define MEMMODE_IDLE_MODE_CONT 1 2158#define MEMMODE_HWIDLE_EN (1<<15) 2159#define MEMMODE_SWMODE_EN (1<<14) 2160#define MEMMODE_RCLK_GATE (1<<13) 2161#define MEMMODE_HW_UPDATE (1<<12) 2162#define MEMMODE_FSTART_MASK 0x00000f00 /* starting jitter, 0-15 */ 2163#define MEMMODE_FSTART_SHIFT 8 2164#define MEMMODE_FMAX_MASK 0x000000f0 /* max jitter, 0-15 */ 2165#define MEMMODE_FMAX_SHIFT 4 2166#define MEMMODE_FMIN_MASK 0x0000000f /* min jitter, 0-15 */ 2167#define RCBMAXAVG 0x1119c 2168#define MEMSWCTL2 0x1119e /* Cantiga only */ 2169#define SWMEMCMD_RENDER_OFF (0 << 13) 2170#define SWMEMCMD_RENDER_ON (1 << 13) 2171#define SWMEMCMD_SWFREQ (2 << 13) 2172#define SWMEMCMD_TARVID (3 << 13) 2173#define SWMEMCMD_VRM_OFF (4 << 13) 2174#define SWMEMCMD_VRM_ON (5 << 13) 2175#define CMDSTS (1<<12) 2176#define SFCAVM (1<<11) 2177#define SWFREQ_MASK 0x0380 /* P0-7 */ 2178#define SWFREQ_SHIFT 7 2179#define TARVID_MASK 0x001f 2180#define MEMSTAT_CTG 0x111a0 2181#define RCBMINAVG 0x111a0 2182#define RCUPEI 0x111b0 2183#define RCDNEI 0x111b4 2184#define RSTDBYCTL 0x111b8 2185#define RS1EN (1<<31) 2186#define RS2EN (1<<30) 2187#define RS3EN (1<<29) 2188#define D3RS3EN (1<<28) /* Display D3 imlies RS3 */ 2189#define SWPROMORSX (1<<27) /* RSx promotion timers ignored */ 2190#define RCWAKERW (1<<26) /* Resetwarn from PCH causes wakeup */ 2191#define DPRSLPVREN (1<<25) /* Fast voltage ramp enable */ 2192#define GFXTGHYST (1<<24) /* Hysteresis to allow trunk gating */ 2193#define RCX_SW_EXIT (1<<23) /* Leave RSx and prevent re-entry */ 2194#define RSX_STATUS_MASK (7<<20) 2195#define RSX_STATUS_ON (0<<20) 2196#define RSX_STATUS_RC1 (1<<20) 2197#define RSX_STATUS_RC1E (2<<20) 2198#define RSX_STATUS_RS1 (3<<20) 2199#define RSX_STATUS_RS2 (4<<20) /* aka rc6 */ 2200#define RSX_STATUS_RSVD (5<<20) /* deep rc6 unsupported on ilk */ 2201#define RSX_STATUS_RS3 (6<<20) /* rs3 unsupported on ilk */ 2202#define RSX_STATUS_RSVD2 (7<<20) 2203#define UWRCRSXE (1<<19) /* wake counter limit prevents rsx */ 2204#define RSCRP (1<<18) /* rs requests control on rs1/2 reqs */ 2205#define JRSC (1<<17) /* rsx coupled to cpu c-state */ 2206#define RS2INC0 (1<<16) /* allow rs2 in cpu c0 */ 2207#define RS1CONTSAV_MASK (3<<14) 2208#define RS1CONTSAV_NO_RS1 (0<<14) /* rs1 doesn't save/restore context */ 2209#define RS1CONTSAV_RSVD (1<<14) 2210#define RS1CONTSAV_SAVE_RS1 (2<<14) /* rs1 saves context */ 2211#define RS1CONTSAV_FULL_RS1 (3<<14) /* rs1 saves and restores context */ 2212#define NORMSLEXLAT_MASK (3<<12) 2213#define SLOW_RS123 (0<<12) 2214#define SLOW_RS23 (1<<12) 2215#define SLOW_RS3 (2<<12) 2216#define NORMAL_RS123 (3<<12) 2217#define RCMODE_TIMEOUT (1<<11) /* 0 is eval interval method */ 2218#define IMPROMOEN (1<<10) /* promo is immediate or delayed until next idle interval (only for timeout method above) */ 2219#define RCENTSYNC (1<<9) /* rs coupled to cpu c-state (3/6/7) */ 2220#define STATELOCK (1<<7) /* locked to rs_cstate if 0 */ 2221#define RS_CSTATE_MASK (3<<4) 2222#define RS_CSTATE_C367_RS1 (0<<4) 2223#define RS_CSTATE_C36_RS1_C7_RS2 (1<<4) 2224#define RS_CSTATE_RSVD (2<<4) 2225#define RS_CSTATE_C367_RS2 (3<<4) 2226#define REDSAVES (1<<3) /* no context save if was idle during rs0 */ 2227#define REDRESTORES (1<<2) /* no restore if was idle during rs0 */ 2228#define VIDCTL 0x111c0 2229#define VIDSTS 0x111c8 2230#define VIDSTART 0x111cc /* 8 bits */ 2231#define MEMSTAT_ILK 0x111f8 2232#define MEMSTAT_VID_MASK 0x7f00 2233#define MEMSTAT_VID_SHIFT 8 2234#define MEMSTAT_PSTATE_MASK 0x00f8 2235#define MEMSTAT_PSTATE_SHIFT 3 2236#define MEMSTAT_MON_ACTV (1<<2) 2237#define MEMSTAT_SRC_CTL_MASK 0x0003 2238#define MEMSTAT_SRC_CTL_CORE 0 2239#define MEMSTAT_SRC_CTL_TRB 1 2240#define MEMSTAT_SRC_CTL_THM 2 2241#define MEMSTAT_SRC_CTL_STDBY 3 2242#define RCPREVBSYTUPAVG 0x113b8 2243#define RCPREVBSYTDNAVG 0x113bc 2244#define PMMISC 0x11214 2245#define MCPPCE_EN (1<<0) /* enable PM_MSG from PCH->MPC */ 2246#define SDEW 0x1124c 2247#define CSIEW0 0x11250 2248#define CSIEW1 0x11254 2249#define CSIEW2 0x11258 2250#define PEW 0x1125c 2251#define DEW 0x11270 2252#define MCHAFE 0x112c0 2253#define CSIEC 0x112e0 2254#define DMIEC 0x112e4 2255#define DDREC 0x112e8 2256#define PEG0EC 0x112ec 2257#define PEG1EC 0x112f0 2258#define GFXEC 0x112f4 2259#define RPPREVBSYTUPAVG 0x113b8 2260#define RPPREVBSYTDNAVG 0x113bc 2261#define ECR 0x11600 2262#define ECR_GPFE (1<<31) 2263#define ECR_IMONE (1<<30) 2264#define ECR_CAP_MASK 0x0000001f /* Event range, 0-31 */ 2265#define OGW0 0x11608 2266#define OGW1 0x1160c 2267#define EG0 0x11610 2268#define EG1 0x11614 2269#define EG2 0x11618 2270#define EG3 0x1161c 2271#define EG4 0x11620 2272#define EG5 0x11624 2273#define EG6 0x11628 2274#define EG7 0x1162c 2275#define PXW 0x11664 2276#define PXWL 0x11680 2277#define LCFUSE02 0x116c0 2278#define LCFUSE_HIV_MASK 0x000000ff 2279#define CSIPLL0 0x12c10 2280#define DDRMPLL1 0X12c20 2281#define PEG_BAND_GAP_DATA 0x14d68 2282 2283#define GEN6_GT_THREAD_STATUS_REG 0x13805c 2284#define GEN6_GT_THREAD_STATUS_CORE_MASK 0x7 2285#define GEN6_GT_THREAD_STATUS_CORE_MASK_HSW (0x7 | (0x07 << 16)) 2286 2287#define GEN6_GT_PERF_STATUS (MCHBAR_MIRROR_BASE_SNB + 0x5948) 2288#define GEN6_RP_STATE_LIMITS (MCHBAR_MIRROR_BASE_SNB + 0x5994) 2289#define GEN6_RP_STATE_CAP (MCHBAR_MIRROR_BASE_SNB + 0x5998) 2290 2291/* 2292 * Logical Context regs 2293 */ 2294#define CCID 0x2180 2295#define CCID_EN (1<<0) 2296/* 2297 * Notes on SNB/IVB/VLV context size: 2298 * - Power context is saved elsewhere (LLC or stolen) 2299 * - Ring/execlist context is saved on SNB, not on IVB 2300 * - Extended context size already includes render context size 2301 * - We always need to follow the extended context size. 2302 * SNB BSpec has comments indicating that we should use the 2303 * render context size instead if execlists are disabled, but 2304 * based on empirical testing that's just nonsense. 2305 * - Pipelined/VF state is saved on SNB/IVB respectively 2306 * - GT1 size just indicates how much of render context 2307 * doesn't need saving on GT1 2308 */ 2309#define CXT_SIZE 0x21a0 2310#define GEN6_CXT_POWER_SIZE(cxt_reg) ((cxt_reg >> 24) & 0x3f) 2311#define GEN6_CXT_RING_SIZE(cxt_reg) ((cxt_reg >> 18) & 0x3f) 2312#define GEN6_CXT_RENDER_SIZE(cxt_reg) ((cxt_reg >> 12) & 0x3f) 2313#define GEN6_CXT_EXTENDED_SIZE(cxt_reg) ((cxt_reg >> 6) & 0x3f) 2314#define GEN6_CXT_PIPELINE_SIZE(cxt_reg) ((cxt_reg >> 0) & 0x3f) 2315#define GEN6_CXT_TOTAL_SIZE(cxt_reg) (GEN6_CXT_RING_SIZE(cxt_reg) + \ 2316 GEN6_CXT_EXTENDED_SIZE(cxt_reg) + \ 2317 GEN6_CXT_PIPELINE_SIZE(cxt_reg)) 2318#define GEN7_CXT_SIZE 0x21a8 2319#define GEN7_CXT_POWER_SIZE(ctx_reg) ((ctx_reg >> 25) & 0x7f) 2320#define GEN7_CXT_RING_SIZE(ctx_reg) ((ctx_reg >> 22) & 0x7) 2321#define GEN7_CXT_RENDER_SIZE(ctx_reg) ((ctx_reg >> 16) & 0x3f) 2322#define GEN7_CXT_EXTENDED_SIZE(ctx_reg) ((ctx_reg >> 9) & 0x7f) 2323#define GEN7_CXT_GT1_SIZE(ctx_reg) ((ctx_reg >> 6) & 0x7) 2324#define GEN7_CXT_VFSTATE_SIZE(ctx_reg) ((ctx_reg >> 0) & 0x3f) 2325#define GEN7_CXT_TOTAL_SIZE(ctx_reg) (GEN7_CXT_EXTENDED_SIZE(ctx_reg) + \ 2326 GEN7_CXT_VFSTATE_SIZE(ctx_reg)) 2327/* Haswell does have the CXT_SIZE register however it does not appear to be 2328 * valid. Now, docs explain in dwords what is in the context object. The full 2329 * size is 70720 bytes, however, the power context and execlist context will 2330 * never be saved (power context is stored elsewhere, and execlists don't work 2331 * on HSW) - so the final size is 66944 bytes, which rounds to 17 pages. 2332 */ 2333#define HSW_CXT_TOTAL_SIZE (17 * PAGE_SIZE) 2334/* Same as Haswell, but 72064 bytes now. */ 2335#define GEN8_CXT_TOTAL_SIZE (18 * PAGE_SIZE) 2336 2337#define CHV_CLK_CTL1 0x101100 2338#define VLV_CLK_CTL2 0x101104 2339#define CLK_CTL2_CZCOUNT_30NS_SHIFT 28 2340 2341/* 2342 * Overlay regs 2343 */ 2344 2345#define OVADD 0x30000 2346#define DOVSTA 0x30008 2347#define OC_BUF (0x3<<20) 2348#define OGAMC5 0x30010 2349#define OGAMC4 0x30014 2350#define OGAMC3 0x30018 2351#define OGAMC2 0x3001c 2352#define OGAMC1 0x30020 2353#define OGAMC0 0x30024 2354 2355/* 2356 * Display engine regs 2357 */ 2358 2359/* Pipe A CRC regs */ 2360#define _PIPE_CRC_CTL_A 0x60050 2361#define PIPE_CRC_ENABLE (1 << 31) 2362/* ivb+ source selection */ 2363#define PIPE_CRC_SOURCE_PRIMARY_IVB (0 << 29) 2364#define PIPE_CRC_SOURCE_SPRITE_IVB (1 << 29) 2365#define PIPE_CRC_SOURCE_PF_IVB (2 << 29) 2366/* ilk+ source selection */ 2367#define PIPE_CRC_SOURCE_PRIMARY_ILK (0 << 28) 2368#define PIPE_CRC_SOURCE_SPRITE_ILK (1 << 28) 2369#define PIPE_CRC_SOURCE_PIPE_ILK (2 << 28) 2370/* embedded DP port on the north display block, reserved on ivb */ 2371#define PIPE_CRC_SOURCE_PORT_A_ILK (4 << 28) 2372#define PIPE_CRC_SOURCE_FDI_ILK (5 << 28) /* reserved on ivb */ 2373/* vlv source selection */ 2374#define PIPE_CRC_SOURCE_PIPE_VLV (0 << 27) 2375#define PIPE_CRC_SOURCE_HDMIB_VLV (1 << 27) 2376#define PIPE_CRC_SOURCE_HDMIC_VLV (2 << 27) 2377/* with DP port the pipe source is invalid */ 2378#define PIPE_CRC_SOURCE_DP_D_VLV (3 << 27) 2379#define PIPE_CRC_SOURCE_DP_B_VLV (6 << 27) 2380#define PIPE_CRC_SOURCE_DP_C_VLV (7 << 27) 2381/* gen3+ source selection */ 2382#define PIPE_CRC_SOURCE_PIPE_I9XX (0 << 28) 2383#define PIPE_CRC_SOURCE_SDVOB_I9XX (1 << 28) 2384#define PIPE_CRC_SOURCE_SDVOC_I9XX (2 << 28) 2385/* with DP/TV port the pipe source is invalid */ 2386#define PIPE_CRC_SOURCE_DP_D_G4X (3 << 28) 2387#define PIPE_CRC_SOURCE_TV_PRE (4 << 28) 2388#define PIPE_CRC_SOURCE_TV_POST (5 << 28) 2389#define PIPE_CRC_SOURCE_DP_B_G4X (6 << 28) 2390#define PIPE_CRC_SOURCE_DP_C_G4X (7 << 28) 2391/* gen2 doesn't have source selection bits */ 2392#define PIPE_CRC_INCLUDE_BORDER_I8XX (1 << 30) 2393 2394#define _PIPE_CRC_RES_1_A_IVB 0x60064 2395#define _PIPE_CRC_RES_2_A_IVB 0x60068 2396#define _PIPE_CRC_RES_3_A_IVB 0x6006c 2397#define _PIPE_CRC_RES_4_A_IVB 0x60070 2398#define _PIPE_CRC_RES_5_A_IVB 0x60074 2399 2400#define _PIPE_CRC_RES_RED_A 0x60060 2401#define _PIPE_CRC_RES_GREEN_A 0x60064 2402#define _PIPE_CRC_RES_BLUE_A 0x60068 2403#define _PIPE_CRC_RES_RES1_A_I915 0x6006c 2404#define _PIPE_CRC_RES_RES2_A_G4X 0x60080 2405 2406/* Pipe B CRC regs */ 2407#define _PIPE_CRC_RES_1_B_IVB 0x61064 2408#define _PIPE_CRC_RES_2_B_IVB 0x61068 2409#define _PIPE_CRC_RES_3_B_IVB 0x6106c 2410#define _PIPE_CRC_RES_4_B_IVB 0x61070 2411#define _PIPE_CRC_RES_5_B_IVB 0x61074 2412 2413#define PIPE_CRC_CTL(pipe) _TRANSCODER2(pipe, _PIPE_CRC_CTL_A) 2414#define PIPE_CRC_RES_1_IVB(pipe) \ 2415 _TRANSCODER2(pipe, _PIPE_CRC_RES_1_A_IVB) 2416#define PIPE_CRC_RES_2_IVB(pipe) \ 2417 _TRANSCODER2(pipe, _PIPE_CRC_RES_2_A_IVB) 2418#define PIPE_CRC_RES_3_IVB(pipe) \ 2419 _TRANSCODER2(pipe, _PIPE_CRC_RES_3_A_IVB) 2420#define PIPE_CRC_RES_4_IVB(pipe) \ 2421 _TRANSCODER2(pipe, _PIPE_CRC_RES_4_A_IVB) 2422#define PIPE_CRC_RES_5_IVB(pipe) \ 2423 _TRANSCODER2(pipe, _PIPE_CRC_RES_5_A_IVB) 2424 2425#define PIPE_CRC_RES_RED(pipe) \ 2426 _TRANSCODER2(pipe, _PIPE_CRC_RES_RED_A) 2427#define PIPE_CRC_RES_GREEN(pipe) \ 2428 _TRANSCODER2(pipe, _PIPE_CRC_RES_GREEN_A) 2429#define PIPE_CRC_RES_BLUE(pipe) \ 2430 _TRANSCODER2(pipe, _PIPE_CRC_RES_BLUE_A) 2431#define PIPE_CRC_RES_RES1_I915(pipe) \ 2432 _TRANSCODER2(pipe, _PIPE_CRC_RES_RES1_A_I915) 2433#define PIPE_CRC_RES_RES2_G4X(pipe) \ 2434 _TRANSCODER2(pipe, _PIPE_CRC_RES_RES2_A_G4X) 2435 2436/* Pipe A timing regs */ 2437#define _HTOTAL_A 0x60000 2438#define _HBLANK_A 0x60004 2439#define _HSYNC_A 0x60008 2440#define _VTOTAL_A 0x6000c 2441#define _VBLANK_A 0x60010 2442#define _VSYNC_A 0x60014 2443#define _PIPEASRC 0x6001c 2444#define _BCLRPAT_A 0x60020 2445#define _VSYNCSHIFT_A 0x60028 2446#define _PIPE_MULT_A 0x6002c 2447 2448/* Pipe B timing regs */ 2449#define _HTOTAL_B 0x61000 2450#define _HBLANK_B 0x61004 2451#define _HSYNC_B 0x61008 2452#define _VTOTAL_B 0x6100c 2453#define _VBLANK_B 0x61010 2454#define _VSYNC_B 0x61014 2455#define _PIPEBSRC 0x6101c 2456#define _BCLRPAT_B 0x61020 2457#define _VSYNCSHIFT_B 0x61028 2458#define _PIPE_MULT_B 0x6102c 2459 2460#define TRANSCODER_A_OFFSET 0x60000 2461#define TRANSCODER_B_OFFSET 0x61000 2462#define TRANSCODER_C_OFFSET 0x62000 2463#define CHV_TRANSCODER_C_OFFSET 0x63000 2464#define TRANSCODER_EDP_OFFSET 0x6f000 2465 2466#define _TRANSCODER2(pipe, reg) (dev_priv->info.trans_offsets[(pipe)] - \ 2467 dev_priv->info.trans_offsets[TRANSCODER_A] + (reg) + \ 2468 dev_priv->info.display_mmio_offset) 2469 2470#define HTOTAL(trans) _TRANSCODER2(trans, _HTOTAL_A) 2471#define HBLANK(trans) _TRANSCODER2(trans, _HBLANK_A) 2472#define HSYNC(trans) _TRANSCODER2(trans, _HSYNC_A) 2473#define VTOTAL(trans) _TRANSCODER2(trans, _VTOTAL_A) 2474#define VBLANK(trans) _TRANSCODER2(trans, _VBLANK_A) 2475#define VSYNC(trans) _TRANSCODER2(trans, _VSYNC_A) 2476#define BCLRPAT(trans) _TRANSCODER2(trans, _BCLRPAT_A) 2477#define VSYNCSHIFT(trans) _TRANSCODER2(trans, _VSYNCSHIFT_A) 2478#define PIPESRC(trans) _TRANSCODER2(trans, _PIPEASRC) 2479#define PIPE_MULT(trans) _TRANSCODER2(trans, _PIPE_MULT_A) 2480 2481/* HSW+ eDP PSR registers */ 2482#define EDP_PSR_BASE(dev) (IS_HASWELL(dev) ? 0x64800 : 0x6f800) 2483#define EDP_PSR_CTL(dev) (EDP_PSR_BASE(dev) + 0) 2484#define EDP_PSR_ENABLE (1<<31) 2485#define BDW_PSR_SINGLE_FRAME (1<<30) 2486#define EDP_PSR_LINK_DISABLE (0<<27) 2487#define EDP_PSR_LINK_STANDBY (1<<27) 2488#define EDP_PSR_MIN_LINK_ENTRY_TIME_MASK (3<<25) 2489#define EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES (0<<25) 2490#define EDP_PSR_MIN_LINK_ENTRY_TIME_4_LINES (1<<25) 2491#define EDP_PSR_MIN_LINK_ENTRY_TIME_2_LINES (2<<25) 2492#define EDP_PSR_MIN_LINK_ENTRY_TIME_0_LINES (3<<25) 2493#define EDP_PSR_MAX_SLEEP_TIME_SHIFT 20 2494#define EDP_PSR_SKIP_AUX_EXIT (1<<12) 2495#define EDP_PSR_TP1_TP2_SEL (0<<11) 2496#define EDP_PSR_TP1_TP3_SEL (1<<11) 2497#define EDP_PSR_TP2_TP3_TIME_500us (0<<8) 2498#define EDP_PSR_TP2_TP3_TIME_100us (1<<8) 2499#define EDP_PSR_TP2_TP3_TIME_2500us (2<<8) 2500#define EDP_PSR_TP2_TP3_TIME_0us (3<<8) 2501#define EDP_PSR_TP1_TIME_500us (0<<4) 2502#define EDP_PSR_TP1_TIME_100us (1<<4) 2503#define EDP_PSR_TP1_TIME_2500us (2<<4) 2504#define EDP_PSR_TP1_TIME_0us (3<<4) 2505#define EDP_PSR_IDLE_FRAME_SHIFT 0 2506 2507#define EDP_PSR_AUX_CTL(dev) (EDP_PSR_BASE(dev) + 0x10) 2508#define EDP_PSR_AUX_DATA1(dev) (EDP_PSR_BASE(dev) + 0x14) 2509#define EDP_PSR_DPCD_COMMAND 0x80060000 2510#define EDP_PSR_AUX_DATA2(dev) (EDP_PSR_BASE(dev) + 0x18) 2511#define EDP_PSR_DPCD_NORMAL_OPERATION (1<<24) 2512#define EDP_PSR_AUX_DATA3(dev) (EDP_PSR_BASE(dev) + 0x1c) 2513#define EDP_PSR_AUX_DATA4(dev) (EDP_PSR_BASE(dev) + 0x20) 2514#define EDP_PSR_AUX_DATA5(dev) (EDP_PSR_BASE(dev) + 0x24) 2515 2516#define EDP_PSR_STATUS_CTL(dev) (EDP_PSR_BASE(dev) + 0x40) 2517#define EDP_PSR_STATUS_STATE_MASK (7<<29) 2518#define EDP_PSR_STATUS_STATE_IDLE (0<<29) 2519#define EDP_PSR_STATUS_STATE_SRDONACK (1<<29) 2520#define EDP_PSR_STATUS_STATE_SRDENT (2<<29) 2521#define EDP_PSR_STATUS_STATE_BUFOFF (3<<29) 2522#define EDP_PSR_STATUS_STATE_BUFON (4<<29) 2523#define EDP_PSR_STATUS_STATE_AUXACK (5<<29) 2524#define EDP_PSR_STATUS_STATE_SRDOFFACK (6<<29) 2525#define EDP_PSR_STATUS_LINK_MASK (3<<26) 2526#define EDP_PSR_STATUS_LINK_FULL_OFF (0<<26) 2527#define EDP_PSR_STATUS_LINK_FULL_ON (1<<26) 2528#define EDP_PSR_STATUS_LINK_STANDBY (2<<26) 2529#define EDP_PSR_STATUS_MAX_SLEEP_TIMER_SHIFT 20 2530#define EDP_PSR_STATUS_MAX_SLEEP_TIMER_MASK 0x1f 2531#define EDP_PSR_STATUS_COUNT_SHIFT 16 2532#define EDP_PSR_STATUS_COUNT_MASK 0xf 2533#define EDP_PSR_STATUS_AUX_ERROR (1<<15) 2534#define EDP_PSR_STATUS_AUX_SENDING (1<<12) 2535#define EDP_PSR_STATUS_SENDING_IDLE (1<<9) 2536#define EDP_PSR_STATUS_SENDING_TP2_TP3 (1<<8) 2537#define EDP_PSR_STATUS_SENDING_TP1 (1<<4) 2538#define EDP_PSR_STATUS_IDLE_MASK 0xf 2539 2540#define EDP_PSR_PERF_CNT(dev) (EDP_PSR_BASE(dev) + 0x44) 2541#define EDP_PSR_PERF_CNT_MASK 0xffffff 2542 2543#define EDP_PSR_DEBUG_CTL(dev) (EDP_PSR_BASE(dev) + 0x60) 2544#define EDP_PSR_DEBUG_MASK_LPSP (1<<27) 2545#define EDP_PSR_DEBUG_MASK_MEMUP (1<<26) 2546#define EDP_PSR_DEBUG_MASK_HPD (1<<25) 2547 2548/* VGA port control */ 2549#define ADPA 0x61100 2550#define PCH_ADPA 0xe1100 2551#define VLV_ADPA (VLV_DISPLAY_BASE + ADPA) 2552 2553#define ADPA_DAC_ENABLE (1<<31) 2554#define ADPA_DAC_DISABLE 0 2555#define ADPA_PIPE_SELECT_MASK (1<<30) 2556#define ADPA_PIPE_A_SELECT 0 2557#define ADPA_PIPE_B_SELECT (1<<30) 2558#define ADPA_PIPE_SELECT(pipe) ((pipe) << 30) 2559/* CPT uses bits 29:30 for pch transcoder select */ 2560#define ADPA_CRT_HOTPLUG_MASK 0x03ff0000 /* bit 25-16 */ 2561#define ADPA_CRT_HOTPLUG_MONITOR_NONE (0<<24) 2562#define ADPA_CRT_HOTPLUG_MONITOR_MASK (3<<24) 2563#define ADPA_CRT_HOTPLUG_MONITOR_COLOR (3<<24) 2564#define ADPA_CRT_HOTPLUG_MONITOR_MONO (2<<24) 2565#define ADPA_CRT_HOTPLUG_ENABLE (1<<23) 2566#define ADPA_CRT_HOTPLUG_PERIOD_64 (0<<22) 2567#define ADPA_CRT_HOTPLUG_PERIOD_128 (1<<22) 2568#define ADPA_CRT_HOTPLUG_WARMUP_5MS (0<<21) 2569#define ADPA_CRT_HOTPLUG_WARMUP_10MS (1<<21) 2570#define ADPA_CRT_HOTPLUG_SAMPLE_2S (0<<20) 2571#define ADPA_CRT_HOTPLUG_SAMPLE_4S (1<<20) 2572#define ADPA_CRT_HOTPLUG_VOLTAGE_40 (0<<18) 2573#define ADPA_CRT_HOTPLUG_VOLTAGE_50 (1<<18) 2574#define ADPA_CRT_HOTPLUG_VOLTAGE_60 (2<<18) 2575#define ADPA_CRT_HOTPLUG_VOLTAGE_70 (3<<18) 2576#define ADPA_CRT_HOTPLUG_VOLREF_325MV (0<<17) 2577#define ADPA_CRT_HOTPLUG_VOLREF_475MV (1<<17) 2578#define ADPA_CRT_HOTPLUG_FORCE_TRIGGER (1<<16) 2579#define ADPA_USE_VGA_HVPOLARITY (1<<15) 2580#define ADPA_SETS_HVPOLARITY 0 2581#define ADPA_VSYNC_CNTL_DISABLE (1<<10) 2582#define ADPA_VSYNC_CNTL_ENABLE 0 2583#define ADPA_HSYNC_CNTL_DISABLE (1<<11) 2584#define ADPA_HSYNC_CNTL_ENABLE 0 2585#define ADPA_VSYNC_ACTIVE_HIGH (1<<4) 2586#define ADPA_VSYNC_ACTIVE_LOW 0 2587#define ADPA_HSYNC_ACTIVE_HIGH (1<<3) 2588#define ADPA_HSYNC_ACTIVE_LOW 0 2589#define ADPA_DPMS_MASK (~(3<<10)) 2590#define ADPA_DPMS_ON (0<<10) 2591#define ADPA_DPMS_SUSPEND (1<<10) 2592#define ADPA_DPMS_STANDBY (2<<10) 2593#define ADPA_DPMS_OFF (3<<10) 2594 2595 2596/* Hotplug control (945+ only) */ 2597#define PORT_HOTPLUG_EN (dev_priv->info.display_mmio_offset + 0x61110) 2598#define PORTB_HOTPLUG_INT_EN (1 << 29) 2599#define PORTC_HOTPLUG_INT_EN (1 << 28) 2600#define PORTD_HOTPLUG_INT_EN (1 << 27) 2601#define SDVOB_HOTPLUG_INT_EN (1 << 26) 2602#define SDVOC_HOTPLUG_INT_EN (1 << 25) 2603#define TV_HOTPLUG_INT_EN (1 << 18) 2604#define CRT_HOTPLUG_INT_EN (1 << 9) 2605#define HOTPLUG_INT_EN_MASK (PORTB_HOTPLUG_INT_EN | \ 2606 PORTC_HOTPLUG_INT_EN | \ 2607 PORTD_HOTPLUG_INT_EN | \ 2608 SDVOC_HOTPLUG_INT_EN | \ 2609 SDVOB_HOTPLUG_INT_EN | \ 2610 CRT_HOTPLUG_INT_EN) 2611#define CRT_HOTPLUG_FORCE_DETECT (1 << 3) 2612#define CRT_HOTPLUG_ACTIVATION_PERIOD_32 (0 << 8) 2613/* must use period 64 on GM45 according to docs */ 2614#define CRT_HOTPLUG_ACTIVATION_PERIOD_64 (1 << 8) 2615#define CRT_HOTPLUG_DAC_ON_TIME_2M (0 << 7) 2616#define CRT_HOTPLUG_DAC_ON_TIME_4M (1 << 7) 2617#define CRT_HOTPLUG_VOLTAGE_COMPARE_40 (0 << 5) 2618#define CRT_HOTPLUG_VOLTAGE_COMPARE_50 (1 << 5) 2619#define CRT_HOTPLUG_VOLTAGE_COMPARE_60 (2 << 5) 2620#define CRT_HOTPLUG_VOLTAGE_COMPARE_70 (3 << 5) 2621#define CRT_HOTPLUG_VOLTAGE_COMPARE_MASK (3 << 5) 2622#define CRT_HOTPLUG_DETECT_DELAY_1G (0 << 4) 2623#define CRT_HOTPLUG_DETECT_DELAY_2G (1 << 4) 2624#define CRT_HOTPLUG_DETECT_VOLTAGE_325MV (0 << 2) 2625#define CRT_HOTPLUG_DETECT_VOLTAGE_475MV (1 << 2) 2626 2627#define PORT_HOTPLUG_STAT (dev_priv->info.display_mmio_offset + 0x61114) 2628/* 2629 * HDMI/DP bits are gen4+ 2630 * 2631 * WARNING: Bspec for hpd status bits on gen4 seems to be completely confused. 2632 * Please check the detailed lore in the commit message for for experimental 2633 * evidence. 2634 */ 2635#define PORTD_HOTPLUG_LIVE_STATUS_G4X (1 << 29) 2636#define PORTC_HOTPLUG_LIVE_STATUS_G4X (1 << 28) 2637#define PORTB_HOTPLUG_LIVE_STATUS_G4X (1 << 27) 2638/* VLV DP/HDMI bits again match Bspec */ 2639#define PORTD_HOTPLUG_LIVE_STATUS_VLV (1 << 27) 2640#define PORTC_HOTPLUG_LIVE_STATUS_VLV (1 << 28) 2641#define PORTB_HOTPLUG_LIVE_STATUS_VLV (1 << 29) 2642#define PORTD_HOTPLUG_INT_STATUS (3 << 21) 2643#define PORTD_HOTPLUG_INT_LONG_PULSE (2 << 21) 2644#define PORTD_HOTPLUG_INT_SHORT_PULSE (1 << 21) 2645#define PORTC_HOTPLUG_INT_STATUS (3 << 19) 2646#define PORTC_HOTPLUG_INT_LONG_PULSE (2 << 19) 2647#define PORTC_HOTPLUG_INT_SHORT_PULSE (1 << 19) 2648#define PORTB_HOTPLUG_INT_STATUS (3 << 17) 2649#define PORTB_HOTPLUG_INT_LONG_PULSE (2 << 17) 2650#define PORTB_HOTPLUG_INT_SHORT_PLUSE (1 << 17) 2651/* CRT/TV common between gen3+ */ 2652#define CRT_HOTPLUG_INT_STATUS (1 << 11) 2653#define TV_HOTPLUG_INT_STATUS (1 << 10) 2654#define CRT_HOTPLUG_MONITOR_MASK (3 << 8) 2655#define CRT_HOTPLUG_MONITOR_COLOR (3 << 8) 2656#define CRT_HOTPLUG_MONITOR_MONO (2 << 8) 2657#define CRT_HOTPLUG_MONITOR_NONE (0 << 8) 2658#define DP_AUX_CHANNEL_D_INT_STATUS_G4X (1 << 6) 2659#define DP_AUX_CHANNEL_C_INT_STATUS_G4X (1 << 5) 2660#define DP_AUX_CHANNEL_B_INT_STATUS_G4X (1 << 4) 2661#define DP_AUX_CHANNEL_MASK_INT_STATUS_G4X (7 << 4) 2662 2663/* SDVO is different across gen3/4 */ 2664#define SDVOC_HOTPLUG_INT_STATUS_G4X (1 << 3) 2665#define SDVOB_HOTPLUG_INT_STATUS_G4X (1 << 2) 2666/* 2667 * Bspec seems to be seriously misleaded about the SDVO hpd bits on i965g/gm, 2668 * since reality corrobates that they're the same as on gen3. But keep these 2669 * bits here (and the comment!) to help any other lost wanderers back onto the 2670 * right tracks. 2671 */ 2672#define SDVOC_HOTPLUG_INT_STATUS_I965 (3 << 4) 2673#define SDVOB_HOTPLUG_INT_STATUS_I965 (3 << 2) 2674#define SDVOC_HOTPLUG_INT_STATUS_I915 (1 << 7) 2675#define SDVOB_HOTPLUG_INT_STATUS_I915 (1 << 6) 2676#define HOTPLUG_INT_STATUS_G4X (CRT_HOTPLUG_INT_STATUS | \ 2677 SDVOB_HOTPLUG_INT_STATUS_G4X | \ 2678 SDVOC_HOTPLUG_INT_STATUS_G4X | \ 2679 PORTB_HOTPLUG_INT_STATUS | \ 2680 PORTC_HOTPLUG_INT_STATUS | \ 2681 PORTD_HOTPLUG_INT_STATUS) 2682 2683#define HOTPLUG_INT_STATUS_I915 (CRT_HOTPLUG_INT_STATUS | \ 2684 SDVOB_HOTPLUG_INT_STATUS_I915 | \ 2685 SDVOC_HOTPLUG_INT_STATUS_I915 | \ 2686 PORTB_HOTPLUG_INT_STATUS | \ 2687 PORTC_HOTPLUG_INT_STATUS | \ 2688 PORTD_HOTPLUG_INT_STATUS) 2689 2690/* SDVO and HDMI port control. 2691 * The same register may be used for SDVO or HDMI */ 2692#define GEN3_SDVOB 0x61140 2693#define GEN3_SDVOC 0x61160 2694#define GEN4_HDMIB GEN3_SDVOB 2695#define GEN4_HDMIC GEN3_SDVOC 2696#define CHV_HDMID 0x6116C 2697#define PCH_SDVOB 0xe1140 2698#define PCH_HDMIB PCH_SDVOB 2699#define PCH_HDMIC 0xe1150 2700#define PCH_HDMID 0xe1160 2701 2702#define PORT_DFT_I9XX 0x61150 2703#define DC_BALANCE_RESET (1 << 25) 2704#define PORT_DFT2_G4X (dev_priv->info.display_mmio_offset + 0x61154) 2705#define DC_BALANCE_RESET_VLV (1 << 31) 2706#define PIPE_SCRAMBLE_RESET_MASK (0x3 << 0) 2707#define PIPE_B_SCRAMBLE_RESET (1 << 1) 2708#define PIPE_A_SCRAMBLE_RESET (1 << 0) 2709 2710/* Gen 3 SDVO bits: */ 2711#define SDVO_ENABLE (1 << 31) 2712#define SDVO_PIPE_SEL(pipe) ((pipe) << 30) 2713#define SDVO_PIPE_SEL_MASK (1 << 30) 2714#define SDVO_PIPE_B_SELECT (1 << 30) 2715#define SDVO_STALL_SELECT (1 << 29) 2716#define SDVO_INTERRUPT_ENABLE (1 << 26) 2717/* 2718 * 915G/GM SDVO pixel multiplier. 2719 * Programmed value is multiplier - 1, up to 5x. 2720 * \sa DPLL_MD_UDI_MULTIPLIER_MASK 2721 */ 2722#define SDVO_PORT_MULTIPLY_MASK (7 << 23) 2723#define SDVO_PORT_MULTIPLY_SHIFT 23 2724#define SDVO_PHASE_SELECT_MASK (15 << 19) 2725#define SDVO_PHASE_SELECT_DEFAULT (6 << 19) 2726#define SDVO_CLOCK_OUTPUT_INVERT (1 << 18) 2727#define SDVOC_GANG_MODE (1 << 16) /* Port C only */ 2728#define SDVO_BORDER_ENABLE (1 << 7) /* SDVO only */ 2729#define SDVOB_PCIE_CONCURRENCY (1 << 3) /* Port B only */ 2730#define SDVO_DETECTED (1 << 2) 2731/* Bits to be preserved when writing */ 2732#define SDVOB_PRESERVE_MASK ((1 << 17) | (1 << 16) | (1 << 14) | \ 2733 SDVO_INTERRUPT_ENABLE) 2734#define SDVOC_PRESERVE_MASK ((1 << 17) | SDVO_INTERRUPT_ENABLE) 2735 2736/* Gen 4 SDVO/HDMI bits: */ 2737#define SDVO_COLOR_FORMAT_8bpc (0 << 26) 2738#define SDVO_COLOR_FORMAT_MASK (7 << 26) 2739#define SDVO_ENCODING_SDVO (0 << 10) 2740#define SDVO_ENCODING_HDMI (2 << 10) 2741#define HDMI_MODE_SELECT_HDMI (1 << 9) /* HDMI only */ 2742#define HDMI_MODE_SELECT_DVI (0 << 9) /* HDMI only */ 2743#define HDMI_COLOR_RANGE_16_235 (1 << 8) /* HDMI only */ 2744#define SDVO_AUDIO_ENABLE (1 << 6) 2745/* VSYNC/HSYNC bits new with 965, default is to be set */ 2746#define SDVO_VSYNC_ACTIVE_HIGH (1 << 4) 2747#define SDVO_HSYNC_ACTIVE_HIGH (1 << 3) 2748 2749/* Gen 5 (IBX) SDVO/HDMI bits: */ 2750#define HDMI_COLOR_FORMAT_12bpc (3 << 26) /* HDMI only */ 2751#define SDVOB_HOTPLUG_ENABLE (1 << 23) /* SDVO only */ 2752 2753/* Gen 6 (CPT) SDVO/HDMI bits: */ 2754#define SDVO_PIPE_SEL_CPT(pipe) ((pipe) << 29) 2755#define SDVO_PIPE_SEL_MASK_CPT (3 << 29) 2756 2757/* CHV SDVO/HDMI bits: */ 2758#define SDVO_PIPE_SEL_CHV(pipe) ((pipe) << 24) 2759#define SDVO_PIPE_SEL_MASK_CHV (3 << 24) 2760 2761 2762/* DVO port control */ 2763#define DVOA 0x61120 2764#define DVOB 0x61140 2765#define DVOC 0x61160 2766#define DVO_ENABLE (1 << 31) 2767#define DVO_PIPE_B_SELECT (1 << 30) 2768#define DVO_PIPE_STALL_UNUSED (0 << 28) 2769#define DVO_PIPE_STALL (1 << 28) 2770#define DVO_PIPE_STALL_TV (2 << 28) 2771#define DVO_PIPE_STALL_MASK (3 << 28) 2772#define DVO_USE_VGA_SYNC (1 << 15) 2773#define DVO_DATA_ORDER_I740 (0 << 14) 2774#define DVO_DATA_ORDER_FP (1 << 14) 2775#define DVO_VSYNC_DISABLE (1 << 11) 2776#define DVO_HSYNC_DISABLE (1 << 10) 2777#define DVO_VSYNC_TRISTATE (1 << 9) 2778#define DVO_HSYNC_TRISTATE (1 << 8) 2779#define DVO_BORDER_ENABLE (1 << 7) 2780#define DVO_DATA_ORDER_GBRG (1 << 6) 2781#define DVO_DATA_ORDER_RGGB (0 << 6) 2782#define DVO_DATA_ORDER_GBRG_ERRATA (0 << 6) 2783#define DVO_DATA_ORDER_RGGB_ERRATA (1 << 6) 2784#define DVO_VSYNC_ACTIVE_HIGH (1 << 4) 2785#define DVO_HSYNC_ACTIVE_HIGH (1 << 3) 2786#define DVO_BLANK_ACTIVE_HIGH (1 << 2) 2787#define DVO_OUTPUT_CSTATE_PIXELS (1 << 1) /* SDG only */ 2788#define DVO_OUTPUT_SOURCE_SIZE_PIXELS (1 << 0) /* SDG only */ 2789#define DVO_PRESERVE_MASK (0x7<<24) 2790#define DVOA_SRCDIM 0x61124 2791#define DVOB_SRCDIM 0x61144 2792#define DVOC_SRCDIM 0x61164 2793#define DVO_SRCDIM_HORIZONTAL_SHIFT 12 2794#define DVO_SRCDIM_VERTICAL_SHIFT 0 2795 2796/* LVDS port control */ 2797#define LVDS 0x61180 2798/* 2799 * Enables the LVDS port. This bit must be set before DPLLs are enabled, as 2800 * the DPLL semantics change when the LVDS is assigned to that pipe. 2801 */ 2802#define LVDS_PORT_EN (1 << 31) 2803/* Selects pipe B for LVDS data. Must be set on pre-965. */ 2804#define LVDS_PIPEB_SELECT (1 << 30) 2805#define LVDS_PIPE_MASK (1 << 30) 2806#define LVDS_PIPE(pipe) ((pipe) << 30) 2807/* LVDS dithering flag on 965/g4x platform */ 2808#define LVDS_ENABLE_DITHER (1 << 25) 2809/* LVDS sync polarity flags. Set to invert (i.e. negative) */ 2810#define LVDS_VSYNC_POLARITY (1 << 21) 2811#define LVDS_HSYNC_POLARITY (1 << 20) 2812 2813/* Enable border for unscaled (or aspect-scaled) display */ 2814#define LVDS_BORDER_ENABLE (1 << 15) 2815/* 2816 * Enables the A0-A2 data pairs and CLKA, containing 18 bits of color data per 2817 * pixel. 2818 */ 2819#define LVDS_A0A2_CLKA_POWER_MASK (3 << 8) 2820#define LVDS_A0A2_CLKA_POWER_DOWN (0 << 8) 2821#define LVDS_A0A2_CLKA_POWER_UP (3 << 8) 2822/* 2823 * Controls the A3 data pair, which contains the additional LSBs for 24 bit 2824 * mode. Only enabled if LVDS_A0A2_CLKA_POWER_UP also indicates it should be 2825 * on. 2826 */ 2827#define LVDS_A3_POWER_MASK (3 << 6) 2828#define LVDS_A3_POWER_DOWN (0 << 6) 2829#define LVDS_A3_POWER_UP (3 << 6) 2830/* 2831 * Controls the CLKB pair. This should only be set when LVDS_B0B3_POWER_UP 2832 * is set. 2833 */ 2834#define LVDS_CLKB_POWER_MASK (3 << 4) 2835#define LVDS_CLKB_POWER_DOWN (0 << 4) 2836#define LVDS_CLKB_POWER_UP (3 << 4) 2837/* 2838 * Controls the B0-B3 data pairs. This must be set to match the DPLL p2 2839 * setting for whether we are in dual-channel mode. The B3 pair will 2840 * additionally only be powered up when LVDS_A3_POWER_UP is set. 2841 */ 2842#define LVDS_B0B3_POWER_MASK (3 << 2) 2843#define LVDS_B0B3_POWER_DOWN (0 << 2) 2844#define LVDS_B0B3_POWER_UP (3 << 2) 2845 2846/* Video Data Island Packet control */ 2847#define VIDEO_DIP_DATA 0x61178 2848/* Read the description of VIDEO_DIP_DATA (before Haswel) or VIDEO_DIP_ECC 2849 * (Haswell and newer) to see which VIDEO_DIP_DATA byte corresponds to each byte 2850 * of the infoframe structure specified by CEA-861. */ 2851#define VIDEO_DIP_DATA_SIZE 32 2852#define VIDEO_DIP_VSC_DATA_SIZE 36 2853#define VIDEO_DIP_CTL 0x61170 2854/* Pre HSW: */ 2855#define VIDEO_DIP_ENABLE (1 << 31) 2856#define VIDEO_DIP_PORT(port) ((port) << 29) 2857#define VIDEO_DIP_PORT_MASK (3 << 29) 2858#define VIDEO_DIP_ENABLE_GCP (1 << 25) 2859#define VIDEO_DIP_ENABLE_AVI (1 << 21) 2860#define VIDEO_DIP_ENABLE_VENDOR (2 << 21) 2861#define VIDEO_DIP_ENABLE_GAMUT (4 << 21) 2862#define VIDEO_DIP_ENABLE_SPD (8 << 21) 2863#define VIDEO_DIP_SELECT_AVI (0 << 19) 2864#define VIDEO_DIP_SELECT_VENDOR (1 << 19) 2865#define VIDEO_DIP_SELECT_SPD (3 << 19) 2866#define VIDEO_DIP_SELECT_MASK (3 << 19) 2867#define VIDEO_DIP_FREQ_ONCE (0 << 16) 2868#define VIDEO_DIP_FREQ_VSYNC (1 << 16) 2869#define VIDEO_DIP_FREQ_2VSYNC (2 << 16) 2870#define VIDEO_DIP_FREQ_MASK (3 << 16) 2871/* HSW and later: */ 2872#define VIDEO_DIP_ENABLE_VSC_HSW (1 << 20) 2873#define VIDEO_DIP_ENABLE_GCP_HSW (1 << 16) 2874#define VIDEO_DIP_ENABLE_AVI_HSW (1 << 12) 2875#define VIDEO_DIP_ENABLE_VS_HSW (1 << 8) 2876#define VIDEO_DIP_ENABLE_GMP_HSW (1 << 4) 2877#define VIDEO_DIP_ENABLE_SPD_HSW (1 << 0) 2878 2879/* Panel power sequencing */ 2880#define PP_STATUS 0x61200 2881#define PP_ON (1 << 31) 2882/* 2883 * Indicates that all dependencies of the panel are on: 2884 * 2885 * - PLL enabled 2886 * - pipe enabled 2887 * - LVDS/DVOB/DVOC on 2888 */ 2889#define PP_READY (1 << 30) 2890#define PP_SEQUENCE_NONE (0 << 28) 2891#define PP_SEQUENCE_POWER_UP (1 << 28) 2892#define PP_SEQUENCE_POWER_DOWN (2 << 28) 2893#define PP_SEQUENCE_MASK (3 << 28) 2894#define PP_SEQUENCE_SHIFT 28 2895#define PP_CYCLE_DELAY_ACTIVE (1 << 27) 2896#define PP_SEQUENCE_STATE_MASK 0x0000000f 2897#define PP_SEQUENCE_STATE_OFF_IDLE (0x0 << 0) 2898#define PP_SEQUENCE_STATE_OFF_S0_1 (0x1 << 0) 2899#define PP_SEQUENCE_STATE_OFF_S0_2 (0x2 << 0) 2900#define PP_SEQUENCE_STATE_OFF_S0_3 (0x3 << 0) 2901#define PP_SEQUENCE_STATE_ON_IDLE (0x8 << 0) 2902#define PP_SEQUENCE_STATE_ON_S1_0 (0x9 << 0) 2903#define PP_SEQUENCE_STATE_ON_S1_2 (0xa << 0) 2904#define PP_SEQUENCE_STATE_ON_S1_3 (0xb << 0) 2905#define PP_SEQUENCE_STATE_RESET (0xf << 0) 2906#define PP_CONTROL 0x61204 2907#define POWER_TARGET_ON (1 << 0) 2908#define PP_ON_DELAYS 0x61208 2909#define PP_OFF_DELAYS 0x6120c 2910#define PP_DIVISOR 0x61210 2911 2912/* Panel fitting */ 2913#define PFIT_CONTROL (dev_priv->info.display_mmio_offset + 0x61230) 2914#define PFIT_ENABLE (1 << 31) 2915#define PFIT_PIPE_MASK (3 << 29) 2916#define PFIT_PIPE_SHIFT 29 2917#define VERT_INTERP_DISABLE (0 << 10) 2918#define VERT_INTERP_BILINEAR (1 << 10) 2919#define VERT_INTERP_MASK (3 << 10) 2920#define VERT_AUTO_SCALE (1 << 9) 2921#define HORIZ_INTERP_DISABLE (0 << 6) 2922#define HORIZ_INTERP_BILINEAR (1 << 6) 2923#define HORIZ_INTERP_MASK (3 << 6) 2924#define HORIZ_AUTO_SCALE (1 << 5) 2925#define PANEL_8TO6_DITHER_ENABLE (1 << 3) 2926#define PFIT_FILTER_FUZZY (0 << 24) 2927#define PFIT_SCALING_AUTO (0 << 26) 2928#define PFIT_SCALING_PROGRAMMED (1 << 26) 2929#define PFIT_SCALING_PILLAR (2 << 26) 2930#define PFIT_SCALING_LETTER (3 << 26) 2931#define PFIT_PGM_RATIOS (dev_priv->info.display_mmio_offset + 0x61234) 2932/* Pre-965 */ 2933#define PFIT_VERT_SCALE_SHIFT 20 2934#define PFIT_VERT_SCALE_MASK 0xfff00000 2935#define PFIT_HORIZ_SCALE_SHIFT 4 2936#define PFIT_HORIZ_SCALE_MASK 0x0000fff0 2937/* 965+ */ 2938#define PFIT_VERT_SCALE_SHIFT_965 16 2939#define PFIT_VERT_SCALE_MASK_965 0x1fff0000 2940#define PFIT_HORIZ_SCALE_SHIFT_965 0 2941#define PFIT_HORIZ_SCALE_MASK_965 0x00001fff 2942 2943#define PFIT_AUTO_RATIOS (dev_priv->info.display_mmio_offset + 0x61238) 2944 2945#define _VLV_BLC_PWM_CTL2_A (dev_priv->info.display_mmio_offset + 0x61250) 2946#define _VLV_BLC_PWM_CTL2_B (dev_priv->info.display_mmio_offset + 0x61350) 2947#define VLV_BLC_PWM_CTL2(pipe) _PIPE(pipe, _VLV_BLC_PWM_CTL2_A, \ 2948 _VLV_BLC_PWM_CTL2_B) 2949 2950#define _VLV_BLC_PWM_CTL_A (dev_priv->info.display_mmio_offset + 0x61254) 2951#define _VLV_BLC_PWM_CTL_B (dev_priv->info.display_mmio_offset + 0x61354) 2952#define VLV_BLC_PWM_CTL(pipe) _PIPE(pipe, _VLV_BLC_PWM_CTL_A, \ 2953 _VLV_BLC_PWM_CTL_B) 2954 2955#define _VLV_BLC_HIST_CTL_A (dev_priv->info.display_mmio_offset + 0x61260) 2956#define _VLV_BLC_HIST_CTL_B (dev_priv->info.display_mmio_offset + 0x61360) 2957#define VLV_BLC_HIST_CTL(pipe) _PIPE(pipe, _VLV_BLC_HIST_CTL_A, \ 2958 _VLV_BLC_HIST_CTL_B) 2959 2960/* Backlight control */ 2961#define BLC_PWM_CTL2 (dev_priv->info.display_mmio_offset + 0x61250) /* 965+ only */ 2962#define BLM_PWM_ENABLE (1 << 31) 2963#define BLM_COMBINATION_MODE (1 << 30) /* gen4 only */ 2964#define BLM_PIPE_SELECT (1 << 29) 2965#define BLM_PIPE_SELECT_IVB (3 << 29) 2966#define BLM_PIPE_A (0 << 29) 2967#define BLM_PIPE_B (1 << 29) 2968#define BLM_PIPE_C (2 << 29) /* ivb + */ 2969#define BLM_TRANSCODER_A BLM_PIPE_A /* hsw */ 2970#define BLM_TRANSCODER_B BLM_PIPE_B 2971#define BLM_TRANSCODER_C BLM_PIPE_C 2972#define BLM_TRANSCODER_EDP (3 << 29) 2973#define BLM_PIPE(pipe) ((pipe) << 29) 2974#define BLM_POLARITY_I965 (1 << 28) /* gen4 only */ 2975#define BLM_PHASE_IN_INTERUPT_STATUS (1 << 26) 2976#define BLM_PHASE_IN_ENABLE (1 << 25) 2977#define BLM_PHASE_IN_INTERUPT_ENABL (1 << 24) 2978#define BLM_PHASE_IN_TIME_BASE_SHIFT (16) 2979#define BLM_PHASE_IN_TIME_BASE_MASK (0xff << 16) 2980#define BLM_PHASE_IN_COUNT_SHIFT (8) 2981#define BLM_PHASE_IN_COUNT_MASK (0xff << 8) 2982#define BLM_PHASE_IN_INCR_SHIFT (0) 2983#define BLM_PHASE_IN_INCR_MASK (0xff << 0) 2984#define BLC_PWM_CTL (dev_priv->info.display_mmio_offset + 0x61254) 2985/* 2986 * This is the most significant 15 bits of the number of backlight cycles in a 2987 * complete cycle of the modulated backlight control. 2988 * 2989 * The actual value is this field multiplied by two. 2990 */ 2991#define BACKLIGHT_MODULATION_FREQ_SHIFT (17) 2992#define BACKLIGHT_MODULATION_FREQ_MASK (0x7fff << 17) 2993#define BLM_LEGACY_MODE (1 << 16) /* gen2 only */ 2994/* 2995 * This is the number of cycles out of the backlight modulation cycle for which 2996 * the backlight is on. 2997 * 2998 * This field must be no greater than the number of cycles in the complete 2999 * backlight modulation cycle. 3000 */ 3001#define BACKLIGHT_DUTY_CYCLE_SHIFT (0) 3002#define BACKLIGHT_DUTY_CYCLE_MASK (0xffff) 3003#define BACKLIGHT_DUTY_CYCLE_MASK_PNV (0xfffe) 3004#define BLM_POLARITY_PNV (1 << 0) /* pnv only */ 3005 3006#define BLC_HIST_CTL (dev_priv->info.display_mmio_offset + 0x61260) 3007 3008/* New registers for PCH-split platforms. Safe where new bits show up, the 3009 * register layout machtes with gen4 BLC_PWM_CTL[12]. */ 3010#define BLC_PWM_CPU_CTL2 0x48250 3011#define BLC_PWM_CPU_CTL 0x48254 3012 3013#define HSW_BLC_PWM2_CTL 0x48350 3014 3015/* PCH CTL1 is totally different, all but the below bits are reserved. CTL2 is 3016 * like the normal CTL from gen4 and earlier. Hooray for confusing naming. */ 3017#define BLC_PWM_PCH_CTL1 0xc8250 3018#define BLM_PCH_PWM_ENABLE (1 << 31) 3019#define BLM_PCH_OVERRIDE_ENABLE (1 << 30) 3020#define BLM_PCH_POLARITY (1 << 29) 3021#define BLC_PWM_PCH_CTL2 0xc8254 3022 3023#define UTIL_PIN_CTL 0x48400 3024#define UTIL_PIN_ENABLE (1 << 31) 3025 3026#define PCH_GTC_CTL 0xe7000 3027#define PCH_GTC_ENABLE (1 << 31) 3028 3029/* TV port control */ 3030#define TV_CTL 0x68000 3031/* Enables the TV encoder */ 3032# define TV_ENC_ENABLE (1 << 31) 3033/* Sources the TV encoder input from pipe B instead of A. */ 3034# define TV_ENC_PIPEB_SELECT (1 << 30) 3035/* Outputs composite video (DAC A only) */ 3036# define TV_ENC_OUTPUT_COMPOSITE (0 << 28) 3037/* Outputs SVideo video (DAC B/C) */ 3038# define TV_ENC_OUTPUT_SVIDEO (1 << 28) 3039/* Outputs Component video (DAC A/B/C) */ 3040# define TV_ENC_OUTPUT_COMPONENT (2 << 28) 3041/* Outputs Composite and SVideo (DAC A/B/C) */ 3042# define TV_ENC_OUTPUT_SVIDEO_COMPOSITE (3 << 28) 3043# define TV_TRILEVEL_SYNC (1 << 21) 3044/* Enables slow sync generation (945GM only) */ 3045# define TV_SLOW_SYNC (1 << 20) 3046/* Selects 4x oversampling for 480i and 576p */ 3047# define TV_OVERSAMPLE_4X (0 << 18) 3048/* Selects 2x oversampling for 720p and 1080i */ 3049# define TV_OVERSAMPLE_2X (1 << 18) 3050/* Selects no oversampling for 1080p */ 3051# define TV_OVERSAMPLE_NONE (2 << 18) 3052/* Selects 8x oversampling */ 3053# define TV_OVERSAMPLE_8X (3 << 18) 3054/* Selects progressive mode rather than interlaced */ 3055# define TV_PROGRESSIVE (1 << 17) 3056/* Sets the colorburst to PAL mode. Required for non-M PAL modes. */ 3057# define TV_PAL_BURST (1 << 16) 3058/* Field for setting delay of Y compared to C */ 3059# define TV_YC_SKEW_MASK (7 << 12) 3060/* Enables a fix for 480p/576p standard definition modes on the 915GM only */ 3061# define TV_ENC_SDP_FIX (1 << 11) 3062/* 3063 * Enables a fix for the 915GM only. 3064 * 3065 * Not sure what it does. 3066 */ 3067# define TV_ENC_C0_FIX (1 << 10) 3068/* Bits that must be preserved by software */ 3069# define TV_CTL_SAVE ((1 << 11) | (3 << 9) | (7 << 6) | 0xf) 3070# define TV_FUSE_STATE_MASK (3 << 4) 3071/* Read-only state that reports all features enabled */ 3072# define TV_FUSE_STATE_ENABLED (0 << 4) 3073/* Read-only state that reports that Macrovision is disabled in hardware*/ 3074# define TV_FUSE_STATE_NO_MACROVISION (1 << 4) 3075/* Read-only state that reports that TV-out is disabled in hardware. */ 3076# define TV_FUSE_STATE_DISABLED (2 << 4) 3077/* Normal operation */ 3078# define TV_TEST_MODE_NORMAL (0 << 0) 3079/* Encoder test pattern 1 - combo pattern */ 3080# define TV_TEST_MODE_PATTERN_1 (1 << 0) 3081/* Encoder test pattern 2 - full screen vertical 75% color bars */ 3082# define TV_TEST_MODE_PATTERN_2 (2 << 0) 3083/* Encoder test pattern 3 - full screen horizontal 75% color bars */ 3084# define TV_TEST_MODE_PATTERN_3 (3 << 0) 3085/* Encoder test pattern 4 - random noise */ 3086# define TV_TEST_MODE_PATTERN_4 (4 << 0) 3087/* Encoder test pattern 5 - linear color ramps */ 3088# define TV_TEST_MODE_PATTERN_5 (5 << 0) 3089/* 3090 * This test mode forces the DACs to 50% of full output. 3091 * 3092 * This is used for load detection in combination with TVDAC_SENSE_MASK 3093 */ 3094# define TV_TEST_MODE_MONITOR_DETECT (7 << 0) 3095# define TV_TEST_MODE_MASK (7 << 0) 3096 3097#define TV_DAC 0x68004 3098# define TV_DAC_SAVE 0x00ffff00 3099/* 3100 * Reports that DAC state change logic has reported change (RO). 3101 * 3102 * This gets cleared when TV_DAC_STATE_EN is cleared 3103*/ 3104# define TVDAC_STATE_CHG (1 << 31) 3105# define TVDAC_SENSE_MASK (7 << 28) 3106/* Reports that DAC A voltage is above the detect threshold */ 3107# define TVDAC_A_SENSE (1 << 30) 3108/* Reports that DAC B voltage is above the detect threshold */ 3109# define TVDAC_B_SENSE (1 << 29) 3110/* Reports that DAC C voltage is above the detect threshold */ 3111# define TVDAC_C_SENSE (1 << 28) 3112/* 3113 * Enables DAC state detection logic, for load-based TV detection. 3114 * 3115 * The PLL of the chosen pipe (in TV_CTL) must be running, and the encoder set 3116 * to off, for load detection to work. 3117 */ 3118# define TVDAC_STATE_CHG_EN (1 << 27) 3119/* Sets the DAC A sense value to high */ 3120# define TVDAC_A_SENSE_CTL (1 << 26) 3121/* Sets the DAC B sense value to high */ 3122# define TVDAC_B_SENSE_CTL (1 << 25) 3123/* Sets the DAC C sense value to high */ 3124# define TVDAC_C_SENSE_CTL (1 << 24) 3125/* Overrides the ENC_ENABLE and DAC voltage levels */ 3126# define DAC_CTL_OVERRIDE (1 << 7) 3127/* Sets the slew rate. Must be preserved in software */ 3128# define ENC_TVDAC_SLEW_FAST (1 << 6) 3129# define DAC_A_1_3_V (0 << 4) 3130# define DAC_A_1_1_V (1 << 4) 3131# define DAC_A_0_7_V (2 << 4) 3132# define DAC_A_MASK (3 << 4) 3133# define DAC_B_1_3_V (0 << 2) 3134# define DAC_B_1_1_V (1 << 2) 3135# define DAC_B_0_7_V (2 << 2) 3136# define DAC_B_MASK (3 << 2) 3137# define DAC_C_1_3_V (0 << 0) 3138# define DAC_C_1_1_V (1 << 0) 3139# define DAC_C_0_7_V (2 << 0) 3140# define DAC_C_MASK (3 << 0) 3141 3142/* 3143 * CSC coefficients are stored in a floating point format with 9 bits of 3144 * mantissa and 2 or 3 bits of exponent. The exponent is represented as 2**-n, 3145 * where 2-bit exponents are unsigned n, and 3-bit exponents are signed n with 3146 * -1 (0x3) being the only legal negative value. 3147 */ 3148#define TV_CSC_Y 0x68010 3149# define TV_RY_MASK 0x07ff0000 3150# define TV_RY_SHIFT 16 3151# define TV_GY_MASK 0x00000fff 3152# define TV_GY_SHIFT 0 3153 3154#define TV_CSC_Y2 0x68014 3155# define TV_BY_MASK 0x07ff0000 3156# define TV_BY_SHIFT 16 3157/* 3158 * Y attenuation for component video. 3159 * 3160 * Stored in 1.9 fixed point. 3161 */ 3162# define TV_AY_MASK 0x000003ff 3163# define TV_AY_SHIFT 0 3164 3165#define TV_CSC_U 0x68018 3166# define TV_RU_MASK 0x07ff0000 3167# define TV_RU_SHIFT 16 3168# define TV_GU_MASK 0x000007ff 3169# define TV_GU_SHIFT 0 3170 3171#define TV_CSC_U2 0x6801c 3172# define TV_BU_MASK 0x07ff0000 3173# define TV_BU_SHIFT 16 3174/* 3175 * U attenuation for component video. 3176 * 3177 * Stored in 1.9 fixed point. 3178 */ 3179# define TV_AU_MASK 0x000003ff 3180# define TV_AU_SHIFT 0 3181 3182#define TV_CSC_V 0x68020 3183# define TV_RV_MASK 0x0fff0000 3184# define TV_RV_SHIFT 16 3185# define TV_GV_MASK 0x000007ff 3186# define TV_GV_SHIFT 0 3187 3188#define TV_CSC_V2 0x68024 3189# define TV_BV_MASK 0x07ff0000 3190# define TV_BV_SHIFT 16 3191/* 3192 * V attenuation for component video. 3193 * 3194 * Stored in 1.9 fixed point. 3195 */ 3196# define TV_AV_MASK 0x000007ff 3197# define TV_AV_SHIFT 0 3198 3199#define TV_CLR_KNOBS 0x68028 3200/* 2s-complement brightness adjustment */ 3201# define TV_BRIGHTNESS_MASK 0xff000000 3202# define TV_BRIGHTNESS_SHIFT 24 3203/* Contrast adjustment, as a 2.6 unsigned floating point number */ 3204# define TV_CONTRAST_MASK 0x00ff0000 3205# define TV_CONTRAST_SHIFT 16 3206/* Saturation adjustment, as a 2.6 unsigned floating point number */ 3207# define TV_SATURATION_MASK 0x0000ff00 3208# define TV_SATURATION_SHIFT 8 3209/* Hue adjustment, as an integer phase angle in degrees */ 3210# define TV_HUE_MASK 0x000000ff 3211# define TV_HUE_SHIFT 0 3212 3213#define TV_CLR_LEVEL 0x6802c 3214/* Controls the DAC level for black */ 3215# define TV_BLACK_LEVEL_MASK 0x01ff0000 3216# define TV_BLACK_LEVEL_SHIFT 16 3217/* Controls the DAC level for blanking */ 3218# define TV_BLANK_LEVEL_MASK 0x000001ff 3219# define TV_BLANK_LEVEL_SHIFT 0 3220 3221#define TV_H_CTL_1 0x68030 3222/* Number of pixels in the hsync. */ 3223# define TV_HSYNC_END_MASK 0x1fff0000 3224# define TV_HSYNC_END_SHIFT 16 3225/* Total number of pixels minus one in the line (display and blanking). */ 3226# define TV_HTOTAL_MASK 0x00001fff 3227# define TV_HTOTAL_SHIFT 0 3228 3229#define TV_H_CTL_2 0x68034 3230/* Enables the colorburst (needed for non-component color) */ 3231# define TV_BURST_ENA (1 << 31) 3232/* Offset of the colorburst from the start of hsync, in pixels minus one. */ 3233# define TV_HBURST_START_SHIFT 16 3234# define TV_HBURST_START_MASK 0x1fff0000 3235/* Length of the colorburst */ 3236# define TV_HBURST_LEN_SHIFT 0 3237# define TV_HBURST_LEN_MASK 0x0001fff 3238 3239#define TV_H_CTL_3 0x68038 3240/* End of hblank, measured in pixels minus one from start of hsync */ 3241# define TV_HBLANK_END_SHIFT 16 3242# define TV_HBLANK_END_MASK 0x1fff0000 3243/* Start of hblank, measured in pixels minus one from start of hsync */ 3244# define TV_HBLANK_START_SHIFT 0 3245# define TV_HBLANK_START_MASK 0x0001fff 3246 3247#define TV_V_CTL_1 0x6803c 3248/* XXX */ 3249# define TV_NBR_END_SHIFT 16 3250# define TV_NBR_END_MASK 0x07ff0000 3251/* XXX */ 3252# define TV_VI_END_F1_SHIFT 8 3253# define TV_VI_END_F1_MASK 0x00003f00 3254/* XXX */ 3255# define TV_VI_END_F2_SHIFT 0 3256# define TV_VI_END_F2_MASK 0x0000003f 3257 3258#define TV_V_CTL_2 0x68040 3259/* Length of vsync, in half lines */ 3260# define TV_VSYNC_LEN_MASK 0x07ff0000 3261# define TV_VSYNC_LEN_SHIFT 16 3262/* Offset of the start of vsync in field 1, measured in one less than the 3263 * number of half lines. 3264 */ 3265# define TV_VSYNC_START_F1_MASK 0x00007f00 3266# define TV_VSYNC_START_F1_SHIFT 8 3267/* 3268 * Offset of the start of vsync in field 2, measured in one less than the 3269 * number of half lines. 3270 */ 3271# define TV_VSYNC_START_F2_MASK 0x0000007f 3272# define TV_VSYNC_START_F2_SHIFT 0 3273 3274#define TV_V_CTL_3 0x68044 3275/* Enables generation of the equalization signal */ 3276# define TV_EQUAL_ENA (1 << 31) 3277/* Length of vsync, in half lines */ 3278# define TV_VEQ_LEN_MASK 0x007f0000 3279# define TV_VEQ_LEN_SHIFT 16 3280/* Offset of the start of equalization in field 1, measured in one less than 3281 * the number of half lines. 3282 */ 3283# define TV_VEQ_START_F1_MASK 0x0007f00 3284# define TV_VEQ_START_F1_SHIFT 8 3285/* 3286 * Offset of the start of equalization in field 2, measured in one less than 3287 * the number of half lines. 3288 */ 3289# define TV_VEQ_START_F2_MASK 0x000007f 3290# define TV_VEQ_START_F2_SHIFT 0 3291 3292#define TV_V_CTL_4 0x68048 3293/* 3294 * Offset to start of vertical colorburst, measured in one less than the 3295 * number of lines from vertical start. 3296 */ 3297# define TV_VBURST_START_F1_MASK 0x003f0000 3298# define TV_VBURST_START_F1_SHIFT 16 3299/* 3300 * Offset to the end of vertical colorburst, measured in one less than the 3301 * number of lines from the start of NBR. 3302 */ 3303# define TV_VBURST_END_F1_MASK 0x000000ff 3304# define TV_VBURST_END_F1_SHIFT 0 3305 3306#define TV_V_CTL_5 0x6804c 3307/* 3308 * Offset to start of vertical colorburst, measured in one less than the 3309 * number of lines from vertical start. 3310 */ 3311# define TV_VBURST_START_F2_MASK 0x003f0000 3312# define TV_VBURST_START_F2_SHIFT 16 3313/* 3314 * Offset to the end of vertical colorburst, measured in one less than the 3315 * number of lines from the start of NBR. 3316 */ 3317# define TV_VBURST_END_F2_MASK 0x000000ff 3318# define TV_VBURST_END_F2_SHIFT 0 3319 3320#define TV_V_CTL_6 0x68050 3321/* 3322 * Offset to start of vertical colorburst, measured in one less than the 3323 * number of lines from vertical start. 3324 */ 3325# define TV_VBURST_START_F3_MASK 0x003f0000 3326# define TV_VBURST_START_F3_SHIFT 16 3327/* 3328 * Offset to the end of vertical colorburst, measured in one less than the 3329 * number of lines from the start of NBR. 3330 */ 3331# define TV_VBURST_END_F3_MASK 0x000000ff 3332# define TV_VBURST_END_F3_SHIFT 0 3333 3334#define TV_V_CTL_7 0x68054 3335/* 3336 * Offset to start of vertical colorburst, measured in one less than the 3337 * number of lines from vertical start. 3338 */ 3339# define TV_VBURST_START_F4_MASK 0x003f0000 3340# define TV_VBURST_START_F4_SHIFT 16 3341/* 3342 * Offset to the end of vertical colorburst, measured in one less than the 3343 * number of lines from the start of NBR. 3344 */ 3345# define TV_VBURST_END_F4_MASK 0x000000ff 3346# define TV_VBURST_END_F4_SHIFT 0 3347 3348#define TV_SC_CTL_1 0x68060 3349/* Turns on the first subcarrier phase generation DDA */ 3350# define TV_SC_DDA1_EN (1 << 31) 3351/* Turns on the first subcarrier phase generation DDA */ 3352# define TV_SC_DDA2_EN (1 << 30) 3353/* Turns on the first subcarrier phase generation DDA */ 3354# define TV_SC_DDA3_EN (1 << 29) 3355/* Sets the subcarrier DDA to reset frequency every other field */ 3356# define TV_SC_RESET_EVERY_2 (0 << 24) 3357/* Sets the subcarrier DDA to reset frequency every fourth field */ 3358# define TV_SC_RESET_EVERY_4 (1 << 24) 3359/* Sets the subcarrier DDA to reset frequency every eighth field */ 3360# define TV_SC_RESET_EVERY_8 (2 << 24) 3361/* Sets the subcarrier DDA to never reset the frequency */ 3362# define TV_SC_RESET_NEVER (3 << 24) 3363/* Sets the peak amplitude of the colorburst.*/ 3364# define TV_BURST_LEVEL_MASK 0x00ff0000 3365# define TV_BURST_LEVEL_SHIFT 16 3366/* Sets the increment of the first subcarrier phase generation DDA */ 3367# define TV_SCDDA1_INC_MASK 0x00000fff 3368# define TV_SCDDA1_INC_SHIFT 0 3369 3370#define TV_SC_CTL_2 0x68064 3371/* Sets the rollover for the second subcarrier phase generation DDA */ 3372# define TV_SCDDA2_SIZE_MASK 0x7fff0000 3373# define TV_SCDDA2_SIZE_SHIFT 16 3374/* Sets the increent of the second subcarrier phase generation DDA */ 3375# define TV_SCDDA2_INC_MASK 0x00007fff 3376# define TV_SCDDA2_INC_SHIFT 0 3377 3378#define TV_SC_CTL_3 0x68068 3379/* Sets the rollover for the third subcarrier phase generation DDA */ 3380# define TV_SCDDA3_SIZE_MASK 0x7fff0000 3381# define TV_SCDDA3_SIZE_SHIFT 16 3382/* Sets the increent of the third subcarrier phase generation DDA */ 3383# define TV_SCDDA3_INC_MASK 0x00007fff 3384# define TV_SCDDA3_INC_SHIFT 0 3385 3386#define TV_WIN_POS 0x68070 3387/* X coordinate of the display from the start of horizontal active */ 3388# define TV_XPOS_MASK 0x1fff0000 3389# define TV_XPOS_SHIFT 16 3390/* Y coordinate of the display from the start of vertical active (NBR) */ 3391# define TV_YPOS_MASK 0x00000fff 3392# define TV_YPOS_SHIFT 0 3393 3394#define TV_WIN_SIZE 0x68074 3395/* Horizontal size of the display window, measured in pixels*/ 3396# define TV_XSIZE_MASK 0x1fff0000 3397# define TV_XSIZE_SHIFT 16 3398/* 3399 * Vertical size of the display window, measured in pixels. 3400 * 3401 * Must be even for interlaced modes. 3402 */ 3403# define TV_YSIZE_MASK 0x00000fff 3404# define TV_YSIZE_SHIFT 0 3405 3406#define TV_FILTER_CTL_1 0x68080 3407/* 3408 * Enables automatic scaling calculation. 3409 * 3410 * If set, the rest of the registers are ignored, and the calculated values can 3411 * be read back from the register. 3412 */ 3413# define TV_AUTO_SCALE (1 << 31) 3414/* 3415 * Disables the vertical filter. 3416 * 3417 * This is required on modes more than 1024 pixels wide */ 3418# define TV_V_FILTER_BYPASS (1 << 29) 3419/* Enables adaptive vertical filtering */ 3420# define TV_VADAPT (1 << 28) 3421# define TV_VADAPT_MODE_MASK (3 << 26) 3422/* Selects the least adaptive vertical filtering mode */ 3423# define TV_VADAPT_MODE_LEAST (0 << 26) 3424/* Selects the moderately adaptive vertical filtering mode */ 3425# define TV_VADAPT_MODE_MODERATE (1 << 26) 3426/* Selects the most adaptive vertical filtering mode */ 3427# define TV_VADAPT_MODE_MOST (3 << 26) 3428/* 3429 * Sets the horizontal scaling factor. 3430 * 3431 * This should be the fractional part of the horizontal scaling factor divided 3432 * by the oversampling rate. TV_HSCALE should be less than 1, and set to: 3433 * 3434 * (src width - 1) / ((oversample * dest width) - 1) 3435 */ 3436# define TV_HSCALE_FRAC_MASK 0x00003fff 3437# define TV_HSCALE_FRAC_SHIFT 0 3438 3439#define TV_FILTER_CTL_2 0x68084 3440/* 3441 * Sets the integer part of the 3.15 fixed-point vertical scaling factor. 3442 * 3443 * TV_VSCALE should be (src height - 1) / ((interlace * dest height) - 1) 3444 */ 3445# define TV_VSCALE_INT_MASK 0x00038000 3446# define TV_VSCALE_INT_SHIFT 15 3447/* 3448 * Sets the fractional part of the 3.15 fixed-point vertical scaling factor. 3449 * 3450 * \sa TV_VSCALE_INT_MASK 3451 */ 3452# define TV_VSCALE_FRAC_MASK 0x00007fff 3453# define TV_VSCALE_FRAC_SHIFT 0 3454 3455#define TV_FILTER_CTL_3 0x68088 3456/* 3457 * Sets the integer part of the 3.15 fixed-point vertical scaling factor. 3458 * 3459 * TV_VSCALE should be (src height - 1) / (1/4 * (dest height - 1)) 3460 * 3461 * For progressive modes, TV_VSCALE_IP_INT should be set to zeroes. 3462 */ 3463# define TV_VSCALE_IP_INT_MASK 0x00038000 3464# define TV_VSCALE_IP_INT_SHIFT 15 3465/* 3466 * Sets the fractional part of the 3.15 fixed-point vertical scaling factor. 3467 * 3468 * For progressive modes, TV_VSCALE_IP_INT should be set to zeroes. 3469 * 3470 * \sa TV_VSCALE_IP_INT_MASK 3471 */ 3472# define TV_VSCALE_IP_FRAC_MASK 0x00007fff 3473# define TV_VSCALE_IP_FRAC_SHIFT 0 3474 3475#define TV_CC_CONTROL 0x68090 3476# define TV_CC_ENABLE (1 << 31) 3477/* 3478 * Specifies which field to send the CC data in. 3479 * 3480 * CC data is usually sent in field 0. 3481 */ 3482# define TV_CC_FID_MASK (1 << 27) 3483# define TV_CC_FID_SHIFT 27 3484/* Sets the horizontal position of the CC data. Usually 135. */ 3485# define TV_CC_HOFF_MASK 0x03ff0000 3486# define TV_CC_HOFF_SHIFT 16 3487/* Sets the vertical position of the CC data. Usually 21 */ 3488# define TV_CC_LINE_MASK 0x0000003f 3489# define TV_CC_LINE_SHIFT 0 3490 3491#define TV_CC_DATA 0x68094 3492# define TV_CC_RDY (1 << 31) 3493/* Second word of CC data to be transmitted. */ 3494# define TV_CC_DATA_2_MASK 0x007f0000 3495# define TV_CC_DATA_2_SHIFT 16 3496/* First word of CC data to be transmitted. */ 3497# define TV_CC_DATA_1_MASK 0x0000007f 3498# define TV_CC_DATA_1_SHIFT 0 3499 3500#define TV_H_LUMA_0 0x68100 3501#define TV_H_LUMA_59 0x681ec 3502#define TV_H_CHROMA_0 0x68200 3503#define TV_H_CHROMA_59 0x682ec 3504#define TV_V_LUMA_0 0x68300 3505#define TV_V_LUMA_42 0x683a8 3506#define TV_V_CHROMA_0 0x68400 3507#define TV_V_CHROMA_42 0x684a8 3508 3509/* Display Port */ 3510#define DP_A 0x64000 /* eDP */ 3511#define DP_B 0x64100 3512#define DP_C 0x64200 3513#define DP_D 0x64300 3514 3515#define DP_PORT_EN (1 << 31) 3516#define DP_PIPEB_SELECT (1 << 30) 3517#define DP_PIPE_MASK (1 << 30) 3518#define DP_PIPE_SELECT_CHV(pipe) ((pipe) << 16) 3519#define DP_PIPE_MASK_CHV (3 << 16) 3520 3521/* Link training mode - select a suitable mode for each stage */ 3522#define DP_LINK_TRAIN_PAT_1 (0 << 28) 3523#define DP_LINK_TRAIN_PAT_2 (1 << 28) 3524#define DP_LINK_TRAIN_PAT_IDLE (2 << 28) 3525#define DP_LINK_TRAIN_OFF (3 << 28) 3526#define DP_LINK_TRAIN_MASK (3 << 28) 3527#define DP_LINK_TRAIN_SHIFT 28 3528#define DP_LINK_TRAIN_PAT_3_CHV (1 << 14) 3529#define DP_LINK_TRAIN_MASK_CHV ((3 << 28)|(1<<14)) 3530 3531/* CPT Link training mode */ 3532#define DP_LINK_TRAIN_PAT_1_CPT (0 << 8) 3533#define DP_LINK_TRAIN_PAT_2_CPT (1 << 8) 3534#define DP_LINK_TRAIN_PAT_IDLE_CPT (2 << 8) 3535#define DP_LINK_TRAIN_OFF_CPT (3 << 8) 3536#define DP_LINK_TRAIN_MASK_CPT (7 << 8) 3537#define DP_LINK_TRAIN_SHIFT_CPT 8 3538 3539/* Signal voltages. These are mostly controlled by the other end */ 3540#define DP_VOLTAGE_0_4 (0 << 25) 3541#define DP_VOLTAGE_0_6 (1 << 25) 3542#define DP_VOLTAGE_0_8 (2 << 25) 3543#define DP_VOLTAGE_1_2 (3 << 25) 3544#define DP_VOLTAGE_MASK (7 << 25) 3545#define DP_VOLTAGE_SHIFT 25 3546 3547/* Signal pre-emphasis levels, like voltages, the other end tells us what 3548 * they want 3549 */ 3550#define DP_PRE_EMPHASIS_0 (0 << 22) 3551#define DP_PRE_EMPHASIS_3_5 (1 << 22) 3552#define DP_PRE_EMPHASIS_6 (2 << 22) 3553#define DP_PRE_EMPHASIS_9_5 (3 << 22) 3554#define DP_PRE_EMPHASIS_MASK (7 << 22) 3555#define DP_PRE_EMPHASIS_SHIFT 22 3556 3557/* How many wires to use. I guess 3 was too hard */ 3558#define DP_PORT_WIDTH(width) (((width) - 1) << 19) 3559#define DP_PORT_WIDTH_MASK (7 << 19) 3560 3561/* Mystic DPCD version 1.1 special mode */ 3562#define DP_ENHANCED_FRAMING (1 << 18) 3563 3564/* eDP */ 3565#define DP_PLL_FREQ_270MHZ (0 << 16) 3566#define DP_PLL_FREQ_160MHZ (1 << 16) 3567#define DP_PLL_FREQ_MASK (3 << 16) 3568 3569/* locked once port is enabled */ 3570#define DP_PORT_REVERSAL (1 << 15) 3571 3572/* eDP */ 3573#define DP_PLL_ENABLE (1 << 14) 3574 3575/* sends the clock on lane 15 of the PEG for debug */ 3576#define DP_CLOCK_OUTPUT_ENABLE (1 << 13) 3577 3578#define DP_SCRAMBLING_DISABLE (1 << 12) 3579#define DP_SCRAMBLING_DISABLE_IRONLAKE (1 << 7) 3580 3581/* limit RGB values to avoid confusing TVs */ 3582#define DP_COLOR_RANGE_16_235 (1 << 8) 3583 3584/* Turn on the audio link */ 3585#define DP_AUDIO_OUTPUT_ENABLE (1 << 6) 3586 3587/* vs and hs sync polarity */ 3588#define DP_SYNC_VS_HIGH (1 << 4) 3589#define DP_SYNC_HS_HIGH (1 << 3) 3590 3591/* A fantasy */ 3592#define DP_DETECTED (1 << 2) 3593 3594/* The aux channel provides a way to talk to the 3595 * signal sink for DDC etc. Max packet size supported 3596 * is 20 bytes in each direction, hence the 5 fixed 3597 * data registers 3598 */ 3599#define DPA_AUX_CH_CTL 0x64010 3600#define DPA_AUX_CH_DATA1 0x64014 3601#define DPA_AUX_CH_DATA2 0x64018 3602#define DPA_AUX_CH_DATA3 0x6401c 3603#define DPA_AUX_CH_DATA4 0x64020 3604#define DPA_AUX_CH_DATA5 0x64024 3605 3606#define DPB_AUX_CH_CTL 0x64110 3607#define DPB_AUX_CH_DATA1 0x64114 3608#define DPB_AUX_CH_DATA2 0x64118 3609#define DPB_AUX_CH_DATA3 0x6411c 3610#define DPB_AUX_CH_DATA4 0x64120 3611#define DPB_AUX_CH_DATA5 0x64124 3612 3613#define DPC_AUX_CH_CTL 0x64210 3614#define DPC_AUX_CH_DATA1 0x64214 3615#define DPC_AUX_CH_DATA2 0x64218 3616#define DPC_AUX_CH_DATA3 0x6421c 3617#define DPC_AUX_CH_DATA4 0x64220 3618#define DPC_AUX_CH_DATA5 0x64224 3619 3620#define DPD_AUX_CH_CTL 0x64310 3621#define DPD_AUX_CH_DATA1 0x64314 3622#define DPD_AUX_CH_DATA2 0x64318 3623#define DPD_AUX_CH_DATA3 0x6431c 3624#define DPD_AUX_CH_DATA4 0x64320 3625#define DPD_AUX_CH_DATA5 0x64324 3626 3627#define DP_AUX_CH_CTL_SEND_BUSY (1 << 31) 3628#define DP_AUX_CH_CTL_DONE (1 << 30) 3629#define DP_AUX_CH_CTL_INTERRUPT (1 << 29) 3630#define DP_AUX_CH_CTL_TIME_OUT_ERROR (1 << 28) 3631#define DP_AUX_CH_CTL_TIME_OUT_400us (0 << 26) 3632#define DP_AUX_CH_CTL_TIME_OUT_600us (1 << 26) 3633#define DP_AUX_CH_CTL_TIME_OUT_800us (2 << 26) 3634#define DP_AUX_CH_CTL_TIME_OUT_1600us (3 << 26) 3635#define DP_AUX_CH_CTL_TIME_OUT_MASK (3 << 26) 3636#define DP_AUX_CH_CTL_RECEIVE_ERROR (1 << 25) 3637#define DP_AUX_CH_CTL_MESSAGE_SIZE_MASK (0x1f << 20) 3638#define DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT 20 3639#define DP_AUX_CH_CTL_PRECHARGE_2US_MASK (0xf << 16) 3640#define DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT 16 3641#define DP_AUX_CH_CTL_AUX_AKSV_SELECT (1 << 15) 3642#define DP_AUX_CH_CTL_MANCHESTER_TEST (1 << 14) 3643#define DP_AUX_CH_CTL_SYNC_TEST (1 << 13) 3644#define DP_AUX_CH_CTL_DEGLITCH_TEST (1 << 12) 3645#define DP_AUX_CH_CTL_PRECHARGE_TEST (1 << 11) 3646#define DP_AUX_CH_CTL_BIT_CLOCK_2X_MASK (0x7ff) 3647#define DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT 0 3648 3649/* 3650 * Computing GMCH M and N values for the Display Port link 3651 * 3652 * GMCH M/N = dot clock * bytes per pixel / ls_clk * # of lanes 3653 * 3654 * ls_clk (we assume) is the DP link clock (1.62 or 2.7 GHz) 3655 * 3656 * The GMCH value is used internally 3657 * 3658 * bytes_per_pixel is the number of bytes coming out of the plane, 3659 * which is after the LUTs, so we want the bytes for our color format. 3660 * For our current usage, this is always 3, one byte for R, G and B. 3661 */ 3662#define _PIPEA_DATA_M_G4X 0x70050 3663#define _PIPEB_DATA_M_G4X 0x71050 3664 3665/* Transfer unit size for display port - 1, default is 0x3f (for TU size 64) */ 3666#define TU_SIZE(x) (((x)-1) << 25) /* default size 64 */ 3667#define TU_SIZE_SHIFT 25 3668#define TU_SIZE_MASK (0x3f << 25) 3669 3670#define DATA_LINK_M_N_MASK (0xffffff) 3671#define DATA_LINK_N_MAX (0x800000) 3672 3673#define _PIPEA_DATA_N_G4X 0x70054 3674#define _PIPEB_DATA_N_G4X 0x71054 3675#define PIPE_GMCH_DATA_N_MASK (0xffffff) 3676 3677/* 3678 * Computing Link M and N values for the Display Port link 3679 * 3680 * Link M / N = pixel_clock / ls_clk 3681 * 3682 * (the DP spec calls pixel_clock the 'strm_clk') 3683 * 3684 * The Link value is transmitted in the Main Stream 3685 * Attributes and VB-ID. 3686 */ 3687 3688#define _PIPEA_LINK_M_G4X 0x70060 3689#define _PIPEB_LINK_M_G4X 0x71060 3690#define PIPEA_DP_LINK_M_MASK (0xffffff) 3691 3692#define _PIPEA_LINK_N_G4X 0x70064 3693#define _PIPEB_LINK_N_G4X 0x71064 3694#define PIPEA_DP_LINK_N_MASK (0xffffff) 3695 3696#define PIPE_DATA_M_G4X(pipe) _PIPE(pipe, _PIPEA_DATA_M_G4X, _PIPEB_DATA_M_G4X) 3697#define PIPE_DATA_N_G4X(pipe) _PIPE(pipe, _PIPEA_DATA_N_G4X, _PIPEB_DATA_N_G4X) 3698#define PIPE_LINK_M_G4X(pipe) _PIPE(pipe, _PIPEA_LINK_M_G4X, _PIPEB_LINK_M_G4X) 3699#define PIPE_LINK_N_G4X(pipe) _PIPE(pipe, _PIPEA_LINK_N_G4X, _PIPEB_LINK_N_G4X) 3700 3701/* Display & cursor control */ 3702 3703/* Pipe A */ 3704#define _PIPEADSL 0x70000 3705#define DSL_LINEMASK_GEN2 0x00000fff 3706#define DSL_LINEMASK_GEN3 0x00001fff 3707#define _PIPEACONF 0x70008 3708#define PIPECONF_ENABLE (1<<31) 3709#define PIPECONF_DISABLE 0 3710#define PIPECONF_DOUBLE_WIDE (1<<30) 3711#define I965_PIPECONF_ACTIVE (1<<30) 3712#define PIPECONF_DSI_PLL_LOCKED (1<<29) /* vlv & pipe A only */ 3713#define PIPECONF_FRAME_START_DELAY_MASK (3<<27) 3714#define PIPECONF_SINGLE_WIDE 0 3715#define PIPECONF_PIPE_UNLOCKED 0 3716#define PIPECONF_PIPE_LOCKED (1<<25) 3717#define PIPECONF_PALETTE 0 3718#define PIPECONF_GAMMA (1<<24) 3719#define PIPECONF_FORCE_BORDER (1<<25) 3720#define PIPECONF_INTERLACE_MASK (7 << 21) 3721#define PIPECONF_INTERLACE_MASK_HSW (3 << 21) 3722/* Note that pre-gen3 does not support interlaced display directly. Panel 3723 * fitting must be disabled on pre-ilk for interlaced. */ 3724#define PIPECONF_PROGRESSIVE (0 << 21) 3725#define PIPECONF_INTERLACE_W_SYNC_SHIFT_PANEL (4 << 21) /* gen4 only */ 3726#define PIPECONF_INTERLACE_W_SYNC_SHIFT (5 << 21) /* gen4 only */ 3727#define PIPECONF_INTERLACE_W_FIELD_INDICATION (6 << 21) 3728#define PIPECONF_INTERLACE_FIELD_0_ONLY (7 << 21) /* gen3 only */ 3729/* Ironlake and later have a complete new set of values for interlaced. PFIT 3730 * means panel fitter required, PF means progressive fetch, DBL means power 3731 * saving pixel doubling. */ 3732#define PIPECONF_PFIT_PF_INTERLACED_ILK (1 << 21) 3733#define PIPECONF_INTERLACED_ILK (3 << 21) 3734#define PIPECONF_INTERLACED_DBL_ILK (4 << 21) /* ilk/snb only */ 3735#define PIPECONF_PFIT_PF_INTERLACED_DBL_ILK (5 << 21) /* ilk/snb only */ 3736#define PIPECONF_INTERLACE_MODE_MASK (7 << 21) 3737#define PIPECONF_EDP_RR_MODE_SWITCH (1 << 20) 3738#define PIPECONF_CXSR_DOWNCLOCK (1<<16) 3739#define PIPECONF_COLOR_RANGE_SELECT (1 << 13) 3740#define PIPECONF_BPC_MASK (0x7 << 5) 3741#define PIPECONF_8BPC (0<<5) 3742#define PIPECONF_10BPC (1<<5) 3743#define PIPECONF_6BPC (2<<5) 3744#define PIPECONF_12BPC (3<<5) 3745#define PIPECONF_DITHER_EN (1<<4) 3746#define PIPECONF_DITHER_TYPE_MASK (0x0000000c) 3747#define PIPECONF_DITHER_TYPE_SP (0<<2) 3748#define PIPECONF_DITHER_TYPE_ST1 (1<<2) 3749#define PIPECONF_DITHER_TYPE_ST2 (2<<2) 3750#define PIPECONF_DITHER_TYPE_TEMP (3<<2) 3751#define _PIPEASTAT 0x70024 3752#define PIPE_FIFO_UNDERRUN_STATUS (1UL<<31) 3753#define SPRITE1_FLIP_DONE_INT_EN_VLV (1UL<<30) 3754#define PIPE_CRC_ERROR_ENABLE (1UL<<29) 3755#define PIPE_CRC_DONE_ENABLE (1UL<<28) 3756#define PERF_COUNTER2_INTERRUPT_EN (1UL<<27) 3757#define PIPE_GMBUS_EVENT_ENABLE (1UL<<27) 3758#define PLANE_FLIP_DONE_INT_EN_VLV (1UL<<26) 3759#define PIPE_HOTPLUG_INTERRUPT_ENABLE (1UL<<26) 3760#define PIPE_VSYNC_INTERRUPT_ENABLE (1UL<<25) 3761#define PIPE_DISPLAY_LINE_COMPARE_ENABLE (1UL<<24) 3762#define PIPE_DPST_EVENT_ENABLE (1UL<<23) 3763#define SPRITE0_FLIP_DONE_INT_EN_VLV (1UL<<22) 3764#define PIPE_LEGACY_BLC_EVENT_ENABLE (1UL<<22) 3765#define PIPE_ODD_FIELD_INTERRUPT_ENABLE (1UL<<21) 3766#define PIPE_EVEN_FIELD_INTERRUPT_ENABLE (1UL<<20) 3767#define PIPE_B_PSR_INTERRUPT_ENABLE_VLV (1UL<<19) 3768#define PERF_COUNTER_INTERRUPT_EN (1UL<<19) 3769#define PIPE_HOTPLUG_TV_INTERRUPT_ENABLE (1UL<<18) /* pre-965 */ 3770#define PIPE_START_VBLANK_INTERRUPT_ENABLE (1UL<<18) /* 965 or later */ 3771#define PIPE_FRAMESTART_INTERRUPT_ENABLE (1UL<<17) 3772#define PIPE_VBLANK_INTERRUPT_ENABLE (1UL<<17) 3773#define PIPEA_HBLANK_INT_EN_VLV (1UL<<16) 3774#define PIPE_OVERLAY_UPDATED_ENABLE (1UL<<16) 3775#define SPRITE1_FLIP_DONE_INT_STATUS_VLV (1UL<<15) 3776#define SPRITE0_FLIP_DONE_INT_STATUS_VLV (1UL<<14) 3777#define PIPE_CRC_ERROR_INTERRUPT_STATUS (1UL<<13) 3778#define PIPE_CRC_DONE_INTERRUPT_STATUS (1UL<<12) 3779#define PERF_COUNTER2_INTERRUPT_STATUS (1UL<<11) 3780#define PIPE_GMBUS_INTERRUPT_STATUS (1UL<<11) 3781#define PLANE_FLIP_DONE_INT_STATUS_VLV (1UL<<10) 3782#define PIPE_HOTPLUG_INTERRUPT_STATUS (1UL<<10) 3783#define PIPE_VSYNC_INTERRUPT_STATUS (1UL<<9) 3784#define PIPE_DISPLAY_LINE_COMPARE_STATUS (1UL<<8) 3785#define PIPE_DPST_EVENT_STATUS (1UL<<7) 3786#define PIPE_A_PSR_STATUS_VLV (1UL<<6) 3787#define PIPE_LEGACY_BLC_EVENT_STATUS (1UL<<6) 3788#define PIPE_ODD_FIELD_INTERRUPT_STATUS (1UL<<5) 3789#define PIPE_EVEN_FIELD_INTERRUPT_STATUS (1UL<<4) 3790#define PIPE_B_PSR_STATUS_VLV (1UL<<3) 3791#define PERF_COUNTER_INTERRUPT_STATUS (1UL<<3) 3792#define PIPE_HOTPLUG_TV_INTERRUPT_STATUS (1UL<<2) /* pre-965 */ 3793#define PIPE_START_VBLANK_INTERRUPT_STATUS (1UL<<2) /* 965 or later */ 3794#define PIPE_FRAMESTART_INTERRUPT_STATUS (1UL<<1) 3795#define PIPE_VBLANK_INTERRUPT_STATUS (1UL<<1) 3796#define PIPE_HBLANK_INT_STATUS (1UL<<0) 3797#define PIPE_OVERLAY_UPDATED_STATUS (1UL<<0) 3798 3799#define PIPESTAT_INT_ENABLE_MASK 0x7fff0000 3800#define PIPESTAT_INT_STATUS_MASK 0x0000ffff 3801 3802#define PIPE_A_OFFSET 0x70000 3803#define PIPE_B_OFFSET 0x71000 3804#define PIPE_C_OFFSET 0x72000 3805#define CHV_PIPE_C_OFFSET 0x74000 3806/* 3807 * There's actually no pipe EDP. Some pipe registers have 3808 * simply shifted from the pipe to the transcoder, while 3809 * keeping their original offset. Thus we need PIPE_EDP_OFFSET 3810 * to access such registers in transcoder EDP. 3811 */ 3812#define PIPE_EDP_OFFSET 0x7f000 3813 3814#define _PIPE2(pipe, reg) (dev_priv->info.pipe_offsets[pipe] - \ 3815 dev_priv->info.pipe_offsets[PIPE_A] + (reg) + \ 3816 dev_priv->info.display_mmio_offset) 3817 3818#define PIPECONF(pipe) _PIPE2(pipe, _PIPEACONF) 3819#define PIPEDSL(pipe) _PIPE2(pipe, _PIPEADSL) 3820#define PIPEFRAME(pipe) _PIPE2(pipe, _PIPEAFRAMEHIGH) 3821#define PIPEFRAMEPIXEL(pipe) _PIPE2(pipe, _PIPEAFRAMEPIXEL) 3822#define PIPESTAT(pipe) _PIPE2(pipe, _PIPEASTAT) 3823 3824#define _PIPE_MISC_A 0x70030 3825#define _PIPE_MISC_B 0x71030 3826#define PIPEMISC_DITHER_BPC_MASK (7<<5) 3827#define PIPEMISC_DITHER_8_BPC (0<<5) 3828#define PIPEMISC_DITHER_10_BPC (1<<5) 3829#define PIPEMISC_DITHER_6_BPC (2<<5) 3830#define PIPEMISC_DITHER_12_BPC (3<<5) 3831#define PIPEMISC_DITHER_ENABLE (1<<4) 3832#define PIPEMISC_DITHER_TYPE_MASK (3<<2) 3833#define PIPEMISC_DITHER_TYPE_SP (0<<2) 3834#define PIPEMISC(pipe) _PIPE2(pipe, _PIPE_MISC_A) 3835 3836#define VLV_DPFLIPSTAT (VLV_DISPLAY_BASE + 0x70028) 3837#define PIPEB_LINE_COMPARE_INT_EN (1<<29) 3838#define PIPEB_HLINE_INT_EN (1<<28) 3839#define PIPEB_VBLANK_INT_EN (1<<27) 3840#define SPRITED_FLIP_DONE_INT_EN (1<<26) 3841#define SPRITEC_FLIP_DONE_INT_EN (1<<25) 3842#define PLANEB_FLIP_DONE_INT_EN (1<<24) 3843#define PIPE_PSR_INT_EN (1<<22) 3844#define PIPEA_LINE_COMPARE_INT_EN (1<<21) 3845#define PIPEA_HLINE_INT_EN (1<<20) 3846#define PIPEA_VBLANK_INT_EN (1<<19) 3847#define SPRITEB_FLIP_DONE_INT_EN (1<<18) 3848#define SPRITEA_FLIP_DONE_INT_EN (1<<17) 3849#define PLANEA_FLIPDONE_INT_EN (1<<16) 3850#define PIPEC_LINE_COMPARE_INT_EN (1<<13) 3851#define PIPEC_HLINE_INT_EN (1<<12) 3852#define PIPEC_VBLANK_INT_EN (1<<11) 3853#define SPRITEF_FLIPDONE_INT_EN (1<<10) 3854#define SPRITEE_FLIPDONE_INT_EN (1<<9) 3855#define PLANEC_FLIPDONE_INT_EN (1<<8) 3856 3857#define DPINVGTT (VLV_DISPLAY_BASE + 0x7002c) /* VLV/CHV only */ 3858#define SPRITEF_INVALID_GTT_INT_EN (1<<27) 3859#define SPRITEE_INVALID_GTT_INT_EN (1<<26) 3860#define PLANEC_INVALID_GTT_INT_EN (1<<25) 3861#define CURSORC_INVALID_GTT_INT_EN (1<<24) 3862#define CURSORB_INVALID_GTT_INT_EN (1<<23) 3863#define CURSORA_INVALID_GTT_INT_EN (1<<22) 3864#define SPRITED_INVALID_GTT_INT_EN (1<<21) 3865#define SPRITEC_INVALID_GTT_INT_EN (1<<20) 3866#define PLANEB_INVALID_GTT_INT_EN (1<<19) 3867#define SPRITEB_INVALID_GTT_INT_EN (1<<18) 3868#define SPRITEA_INVALID_GTT_INT_EN (1<<17) 3869#define PLANEA_INVALID_GTT_INT_EN (1<<16) 3870#define DPINVGTT_EN_MASK 0xff0000 3871#define DPINVGTT_EN_MASK_CHV 0xfff0000 3872#define SPRITEF_INVALID_GTT_STATUS (1<<11) 3873#define SPRITEE_INVALID_GTT_STATUS (1<<10) 3874#define PLANEC_INVALID_GTT_STATUS (1<<9) 3875#define CURSORC_INVALID_GTT_STATUS (1<<8) 3876#define CURSORB_INVALID_GTT_STATUS (1<<7) 3877#define CURSORA_INVALID_GTT_STATUS (1<<6) 3878#define SPRITED_INVALID_GTT_STATUS (1<<5) 3879#define SPRITEC_INVALID_GTT_STATUS (1<<4) 3880#define PLANEB_INVALID_GTT_STATUS (1<<3) 3881#define SPRITEB_INVALID_GTT_STATUS (1<<2) 3882#define SPRITEA_INVALID_GTT_STATUS (1<<1) 3883#define PLANEA_INVALID_GTT_STATUS (1<<0) 3884#define DPINVGTT_STATUS_MASK 0xff 3885#define DPINVGTT_STATUS_MASK_CHV 0xfff 3886 3887#define DSPARB 0x70030 3888#define DSPARB_CSTART_MASK (0x7f << 7) 3889#define DSPARB_CSTART_SHIFT 7 3890#define DSPARB_BSTART_MASK (0x7f) 3891#define DSPARB_BSTART_SHIFT 0 3892#define DSPARB_BEND_SHIFT 9 /* on 855 */ 3893#define DSPARB_AEND_SHIFT 0 3894 3895/* pnv/gen4/g4x/vlv/chv */ 3896#define DSPFW1 (dev_priv->info.display_mmio_offset + 0x70034) 3897#define DSPFW_SR_SHIFT 23 3898#define DSPFW_SR_MASK (0x1ff<<23) 3899#define DSPFW_CURSORB_SHIFT 16 3900#define DSPFW_CURSORB_MASK (0x3f<<16) 3901#define DSPFW_PLANEB_SHIFT 8 3902#define DSPFW_PLANEB_MASK (0x7f<<8) 3903#define DSPFW_PLANEB_MASK_VLV (0xff<<8) /* vlv/chv */ 3904#define DSPFW_PLANEA_SHIFT 0 3905#define DSPFW_PLANEA_MASK (0x7f<<0) 3906#define DSPFW_PLANEA_MASK_VLV (0xff<<0) /* vlv/chv */ 3907#define DSPFW2 (dev_priv->info.display_mmio_offset + 0x70038) 3908#define DSPFW_FBC_SR_EN (1<<31) /* g4x */ 3909#define DSPFW_FBC_SR_SHIFT 28 3910#define DSPFW_FBC_SR_MASK (0x7<<28) /* g4x */ 3911#define DSPFW_FBC_HPLL_SR_SHIFT 24 3912#define DSPFW_FBC_HPLL_SR_MASK (0xf<<24) /* g4x */ 3913#define DSPFW_SPRITEB_SHIFT (16) 3914#define DSPFW_SPRITEB_MASK (0x7f<<16) /* g4x */ 3915#define DSPFW_SPRITEB_MASK_VLV (0xff<<16) /* vlv/chv */ 3916#define DSPFW_CURSORA_SHIFT 8 3917#define DSPFW_CURSORA_MASK (0x3f<<8) 3918#define DSPFW_PLANEC_SHIFT_OLD 0 3919#define DSPFW_PLANEC_MASK_OLD (0x7f<<0) /* pre-gen4 sprite C */ 3920#define DSPFW_SPRITEA_SHIFT 0 3921#define DSPFW_SPRITEA_MASK (0x7f<<0) /* g4x */ 3922#define DSPFW_SPRITEA_MASK_VLV (0xff<<0) /* vlv/chv */ 3923#define DSPFW3 (dev_priv->info.display_mmio_offset + 0x7003c) 3924#define DSPFW_HPLL_SR_EN (1<<31) 3925#define PINEVIEW_SELF_REFRESH_EN (1<<30) 3926#define DSPFW_CURSOR_SR_SHIFT 24 3927#define DSPFW_CURSOR_SR_MASK (0x3f<<24) 3928#define DSPFW_HPLL_CURSOR_SHIFT 16 3929#define DSPFW_HPLL_CURSOR_MASK (0x3f<<16) 3930#define DSPFW_HPLL_SR_SHIFT 0 3931#define DSPFW_HPLL_SR_MASK (0x1ff<<0) 3932 3933/* vlv/chv */ 3934#define DSPFW4 (VLV_DISPLAY_BASE + 0x70070) 3935#define DSPFW_SPRITEB_WM1_SHIFT 16 3936#define DSPFW_SPRITEB_WM1_MASK (0xff<<16) 3937#define DSPFW_CURSORA_WM1_SHIFT 8 3938#define DSPFW_CURSORA_WM1_MASK (0x3f<<8) 3939#define DSPFW_SPRITEA_WM1_SHIFT 0 3940#define DSPFW_SPRITEA_WM1_MASK (0xff<<0) 3941#define DSPFW5 (VLV_DISPLAY_BASE + 0x70074) 3942#define DSPFW_PLANEB_WM1_SHIFT 24 3943#define DSPFW_PLANEB_WM1_MASK (0xff<<24) 3944#define DSPFW_PLANEA_WM1_SHIFT 16 3945#define DSPFW_PLANEA_WM1_MASK (0xff<<16) 3946#define DSPFW_CURSORB_WM1_SHIFT 8 3947#define DSPFW_CURSORB_WM1_MASK (0x3f<<8) 3948#define DSPFW_CURSOR_SR_WM1_SHIFT 0 3949#define DSPFW_CURSOR_SR_WM1_MASK (0x3f<<0) 3950#define DSPFW6 (VLV_DISPLAY_BASE + 0x70078) 3951#define DSPFW_SR_WM1_SHIFT 0 3952#define DSPFW_SR_WM1_MASK (0x1ff<<0) 3953#define DSPFW7 (VLV_DISPLAY_BASE + 0x7007c) 3954#define DSPFW7_CHV (VLV_DISPLAY_BASE + 0x700b4) /* wtf #1? */ 3955#define DSPFW_SPRITED_WM1_SHIFT 24 3956#define DSPFW_SPRITED_WM1_MASK (0xff<<24) 3957#define DSPFW_SPRITED_SHIFT 16 3958#define DSPFW_SPRITED_MASK (0xff<<16) 3959#define DSPFW_SPRITEC_WM1_SHIFT 8 3960#define DSPFW_SPRITEC_WM1_MASK (0xff<<8) 3961#define DSPFW_SPRITEC_SHIFT 0 3962#define DSPFW_SPRITEC_MASK (0xff<<0) 3963#define DSPFW8_CHV (VLV_DISPLAY_BASE + 0x700b8) 3964#define DSPFW_SPRITEF_WM1_SHIFT 24 3965#define DSPFW_SPRITEF_WM1_MASK (0xff<<24) 3966#define DSPFW_SPRITEF_SHIFT 16 3967#define DSPFW_SPRITEF_MASK (0xff<<16) 3968#define DSPFW_SPRITEE_WM1_SHIFT 8 3969#define DSPFW_SPRITEE_WM1_MASK (0xff<<8) 3970#define DSPFW_SPRITEE_SHIFT 0 3971#define DSPFW_SPRITEE_MASK (0xff<<0) 3972#define DSPFW9_CHV (VLV_DISPLAY_BASE + 0x7007c) /* wtf #2? */ 3973#define DSPFW_PLANEC_WM1_SHIFT 24 3974#define DSPFW_PLANEC_WM1_MASK (0xff<<24) 3975#define DSPFW_PLANEC_SHIFT 16 3976#define DSPFW_PLANEC_MASK (0xff<<16) 3977#define DSPFW_CURSORC_WM1_SHIFT 8 3978#define DSPFW_CURSORC_WM1_MASK (0x3f<<16) 3979#define DSPFW_CURSORC_SHIFT 0 3980#define DSPFW_CURSORC_MASK (0x3f<<0) 3981 3982/* vlv/chv high order bits */ 3983#define DSPHOWM (VLV_DISPLAY_BASE + 0x70064) 3984#define DSPFW_SR_HI_SHIFT 24 3985#define DSPFW_SR_HI_MASK (1<<24) 3986#define DSPFW_SPRITEF_HI_SHIFT 23 3987#define DSPFW_SPRITEF_HI_MASK (1<<23) 3988#define DSPFW_SPRITEE_HI_SHIFT 22 3989#define DSPFW_SPRITEE_HI_MASK (1<<22) 3990#define DSPFW_PLANEC_HI_SHIFT 21 3991#define DSPFW_PLANEC_HI_MASK (1<<21) 3992#define DSPFW_SPRITED_HI_SHIFT 20 3993#define DSPFW_SPRITED_HI_MASK (1<<20) 3994#define DSPFW_SPRITEC_HI_SHIFT 16 3995#define DSPFW_SPRITEC_HI_MASK (1<<16) 3996#define DSPFW_PLANEB_HI_SHIFT 12 3997#define DSPFW_PLANEB_HI_MASK (1<<12) 3998#define DSPFW_SPRITEB_HI_SHIFT 8 3999#define DSPFW_SPRITEB_HI_MASK (1<<8) 4000#define DSPFW_SPRITEA_HI_SHIFT 4 4001#define DSPFW_SPRITEA_HI_MASK (1<<4) 4002#define DSPFW_PLANEA_HI_SHIFT 0 4003#define DSPFW_PLANEA_HI_MASK (1<<0) 4004#define DSPHOWM1 (VLV_DISPLAY_BASE + 0x70068) 4005#define DSPFW_SR_WM1_HI_SHIFT 24 4006#define DSPFW_SR_WM1_HI_MASK (1<<24) 4007#define DSPFW_SPRITEF_WM1_HI_SHIFT 23 4008#define DSPFW_SPRITEF_WM1_HI_MASK (1<<23) 4009#define DSPFW_SPRITEE_WM1_HI_SHIFT 22 4010#define DSPFW_SPRITEE_WM1_HI_MASK (1<<22) 4011#define DSPFW_PLANEC_WM1_HI_SHIFT 21 4012#define DSPFW_PLANEC_WM1_HI_MASK (1<<21) 4013#define DSPFW_SPRITED_WM1_HI_SHIFT 20 4014#define DSPFW_SPRITED_WM1_HI_MASK (1<<20) 4015#define DSPFW_SPRITEC_WM1_HI_SHIFT 16 4016#define DSPFW_SPRITEC_WM1_HI_MASK (1<<16) 4017#define DSPFW_PLANEB_WM1_HI_SHIFT 12 4018#define DSPFW_PLANEB_WM1_HI_MASK (1<<12) 4019#define DSPFW_SPRITEB_WM1_HI_SHIFT 8 4020#define DSPFW_SPRITEB_WM1_HI_MASK (1<<8) 4021#define DSPFW_SPRITEA_WM1_HI_SHIFT 4 4022#define DSPFW_SPRITEA_WM1_HI_MASK (1<<4) 4023#define DSPFW_PLANEA_WM1_HI_SHIFT 0 4024#define DSPFW_PLANEA_WM1_HI_MASK (1<<0) 4025 4026/* drain latency register values*/ 4027#define DRAIN_LATENCY_PRECISION_32 32 4028#define DRAIN_LATENCY_PRECISION_64 64 4029#define VLV_DDL(pipe) (VLV_DISPLAY_BASE + 0x70050 + 4 * (pipe)) 4030#define DDL_CURSOR_PRECISION_64 (1<<31) 4031#define DDL_CURSOR_PRECISION_32 (0<<31) 4032#define DDL_CURSOR_SHIFT 24 4033#define DDL_SPRITE_PRECISION_64(sprite) (1<<(15+8*(sprite))) 4034#define DDL_SPRITE_PRECISION_32(sprite) (0<<(15+8*(sprite))) 4035#define DDL_SPRITE_SHIFT(sprite) (8+8*(sprite)) 4036#define DDL_PLANE_PRECISION_64 (1<<7) 4037#define DDL_PLANE_PRECISION_32 (0<<7) 4038#define DDL_PLANE_SHIFT 0 4039#define DRAIN_LATENCY_MASK 0x7f 4040 4041/* FIFO watermark sizes etc */ 4042#define G4X_FIFO_LINE_SIZE 64 4043#define I915_FIFO_LINE_SIZE 64 4044#define I830_FIFO_LINE_SIZE 32 4045 4046#define VALLEYVIEW_FIFO_SIZE 255 4047#define G4X_FIFO_SIZE 127 4048#define I965_FIFO_SIZE 512 4049#define I945_FIFO_SIZE 127 4050#define I915_FIFO_SIZE 95 4051#define I855GM_FIFO_SIZE 127 /* In cachelines */ 4052#define I830_FIFO_SIZE 95 4053 4054#define VALLEYVIEW_MAX_WM 0xff 4055#define G4X_MAX_WM 0x3f 4056#define I915_MAX_WM 0x3f 4057 4058#define PINEVIEW_DISPLAY_FIFO 512 /* in 64byte unit */ 4059#define PINEVIEW_FIFO_LINE_SIZE 64 4060#define PINEVIEW_MAX_WM 0x1ff 4061#define PINEVIEW_DFT_WM 0x3f 4062#define PINEVIEW_DFT_HPLLOFF_WM 0 4063#define PINEVIEW_GUARD_WM 10 4064#define PINEVIEW_CURSOR_FIFO 64 4065#define PINEVIEW_CURSOR_MAX_WM 0x3f 4066#define PINEVIEW_CURSOR_DFT_WM 0 4067#define PINEVIEW_CURSOR_GUARD_WM 5 4068 4069#define VALLEYVIEW_CURSOR_MAX_WM 64 4070#define I965_CURSOR_FIFO 64 4071#define I965_CURSOR_MAX_WM 32 4072#define I965_CURSOR_DFT_WM 8 4073 4074/* define the Watermark register on Ironlake */ 4075#define WM0_PIPEA_ILK 0x45100 4076#define WM0_PIPE_PLANE_MASK (0xffff<<16) 4077#define WM0_PIPE_PLANE_SHIFT 16 4078#define WM0_PIPE_SPRITE_MASK (0xff<<8) 4079#define WM0_PIPE_SPRITE_SHIFT 8 4080#define WM0_PIPE_CURSOR_MASK (0xff) 4081 4082#define WM0_PIPEB_ILK 0x45104 4083#define WM0_PIPEC_IVB 0x45200 4084#define WM1_LP_ILK 0x45108 4085#define WM1_LP_SR_EN (1<<31) 4086#define WM1_LP_LATENCY_SHIFT 24 4087#define WM1_LP_LATENCY_MASK (0x7f<<24) 4088#define WM1_LP_FBC_MASK (0xf<<20) 4089#define WM1_LP_FBC_SHIFT 20 4090#define WM1_LP_FBC_SHIFT_BDW 19 4091#define WM1_LP_SR_MASK (0x7ff<<8) 4092#define WM1_LP_SR_SHIFT 8 4093#define WM1_LP_CURSOR_MASK (0xff) 4094#define WM2_LP_ILK 0x4510c 4095#define WM2_LP_EN (1<<31) 4096#define WM3_LP_ILK 0x45110 4097#define WM3_LP_EN (1<<31) 4098#define WM1S_LP_ILK 0x45120 4099#define WM2S_LP_IVB 0x45124 4100#define WM3S_LP_IVB 0x45128 4101#define WM1S_LP_EN (1<<31) 4102 4103#define HSW_WM_LP_VAL(lat, fbc, pri, cur) \ 4104 (WM3_LP_EN | ((lat) << WM1_LP_LATENCY_SHIFT) | \ 4105 ((fbc) << WM1_LP_FBC_SHIFT) | ((pri) << WM1_LP_SR_SHIFT) | (cur)) 4106 4107/* Memory latency timer register */ 4108#define MLTR_ILK 0x11222 4109#define MLTR_WM1_SHIFT 0 4110#define MLTR_WM2_SHIFT 8 4111/* the unit of memory self-refresh latency time is 0.5us */ 4112#define ILK_SRLT_MASK 0x3f 4113 4114 4115/* the address where we get all kinds of latency value */ 4116#define SSKPD 0x5d10 4117#define SSKPD_WM_MASK 0x3f 4118#define SSKPD_WM0_SHIFT 0 4119#define SSKPD_WM1_SHIFT 8 4120#define SSKPD_WM2_SHIFT 16 4121#define SSKPD_WM3_SHIFT 24 4122 4123/* 4124 * The two pipe frame counter registers are not synchronized, so 4125 * reading a stable value is somewhat tricky. The following code 4126 * should work: 4127 * 4128 * do { 4129 * high1 = ((INREG(PIPEAFRAMEHIGH) & PIPE_FRAME_HIGH_MASK) >> 4130 * PIPE_FRAME_HIGH_SHIFT; 4131 * low1 = ((INREG(PIPEAFRAMEPIXEL) & PIPE_FRAME_LOW_MASK) >> 4132 * PIPE_FRAME_LOW_SHIFT); 4133 * high2 = ((INREG(PIPEAFRAMEHIGH) & PIPE_FRAME_HIGH_MASK) >> 4134 * PIPE_FRAME_HIGH_SHIFT); 4135 * } while (high1 != high2); 4136 * frame = (high1 << 8) | low1; 4137 */ 4138#define _PIPEAFRAMEHIGH 0x70040 4139#define PIPE_FRAME_HIGH_MASK 0x0000ffff 4140#define PIPE_FRAME_HIGH_SHIFT 0 4141#define _PIPEAFRAMEPIXEL 0x70044 4142#define PIPE_FRAME_LOW_MASK 0xff000000 4143#define PIPE_FRAME_LOW_SHIFT 24 4144#define PIPE_PIXEL_MASK 0x00ffffff 4145#define PIPE_PIXEL_SHIFT 0 4146/* GM45+ just has to be different */ 4147#define _PIPEA_FRMCOUNT_GM45 0x70040 4148#define _PIPEA_FLIPCOUNT_GM45 0x70044 4149#define PIPE_FRMCOUNT_GM45(pipe) _PIPE2(pipe, _PIPEA_FRMCOUNT_GM45) 4150#define PIPE_FLIPCOUNT_GM45(pipe) _PIPE2(pipe, _PIPEA_FLIPCOUNT_GM45) 4151 4152/* Cursor A & B regs */ 4153#define _CURACNTR 0x70080 4154/* Old style CUR*CNTR flags (desktop 8xx) */ 4155#define CURSOR_ENABLE 0x80000000 4156#define CURSOR_GAMMA_ENABLE 0x40000000 4157#define CURSOR_STRIDE_SHIFT 28 4158#define CURSOR_STRIDE(x) ((ffs(x)-9) << CURSOR_STRIDE_SHIFT) /* 256,512,1k,2k */ 4159#define CURSOR_PIPE_CSC_ENABLE (1<<24) 4160#define CURSOR_FORMAT_SHIFT 24 4161#define CURSOR_FORMAT_MASK (0x07 << CURSOR_FORMAT_SHIFT) 4162#define CURSOR_FORMAT_2C (0x00 << CURSOR_FORMAT_SHIFT) 4163#define CURSOR_FORMAT_3C (0x01 << CURSOR_FORMAT_SHIFT) 4164#define CURSOR_FORMAT_4C (0x02 << CURSOR_FORMAT_SHIFT) 4165#define CURSOR_FORMAT_ARGB (0x04 << CURSOR_FORMAT_SHIFT) 4166#define CURSOR_FORMAT_XRGB (0x05 << CURSOR_FORMAT_SHIFT) 4167/* New style CUR*CNTR flags */ 4168#define CURSOR_MODE 0x27 4169#define CURSOR_MODE_DISABLE 0x00 4170#define CURSOR_MODE_128_32B_AX 0x02 4171#define CURSOR_MODE_256_32B_AX 0x03 4172#define CURSOR_MODE_64_32B_AX 0x07 4173#define CURSOR_MODE_128_ARGB_AX ((1 << 5) | CURSOR_MODE_128_32B_AX) 4174#define CURSOR_MODE_256_ARGB_AX ((1 << 5) | CURSOR_MODE_256_32B_AX) 4175#define CURSOR_MODE_64_ARGB_AX ((1 << 5) | CURSOR_MODE_64_32B_AX) 4176#define MCURSOR_PIPE_SELECT (1 << 28) 4177#define MCURSOR_PIPE_A 0x00 4178#define MCURSOR_PIPE_B (1 << 28) 4179#define MCURSOR_GAMMA_ENABLE (1 << 26) 4180#define CURSOR_TRICKLE_FEED_DISABLE (1 << 14) 4181#define _CURABASE 0x70084 4182#define _CURAPOS 0x70088 4183#define CURSOR_POS_MASK 0x007FF 4184#define CURSOR_POS_SIGN 0x8000 4185#define CURSOR_X_SHIFT 0 4186#define CURSOR_Y_SHIFT 16 4187#define CURSIZE 0x700a0 4188#define _CURBCNTR 0x700c0 4189#define _CURBBASE 0x700c4 4190#define _CURBPOS 0x700c8 4191 4192#define _CURBCNTR_IVB 0x71080 4193#define _CURBBASE_IVB 0x71084 4194#define _CURBPOS_IVB 0x71088 4195 4196#define _CURSOR2(pipe, reg) (dev_priv->info.cursor_offsets[(pipe)] - \ 4197 dev_priv->info.cursor_offsets[PIPE_A] + (reg) + \ 4198 dev_priv->info.display_mmio_offset) 4199 4200#define CURCNTR(pipe) _CURSOR2(pipe, _CURACNTR) 4201#define CURBASE(pipe) _CURSOR2(pipe, _CURABASE) 4202#define CURPOS(pipe) _CURSOR2(pipe, _CURAPOS) 4203 4204#define CURSOR_A_OFFSET 0x70080 4205#define CURSOR_B_OFFSET 0x700c0 4206#define CHV_CURSOR_C_OFFSET 0x700e0 4207#define IVB_CURSOR_B_OFFSET 0x71080 4208#define IVB_CURSOR_C_OFFSET 0x72080 4209 4210/* Display A control */ 4211#define _DSPACNTR 0x70180 4212#define DISPLAY_PLANE_ENABLE (1<<31) 4213#define DISPLAY_PLANE_DISABLE 0 4214#define DISPPLANE_GAMMA_ENABLE (1<<30) 4215#define DISPPLANE_GAMMA_DISABLE 0 4216#define DISPPLANE_PIXFORMAT_MASK (0xf<<26) 4217#define DISPPLANE_YUV422 (0x0<<26) 4218#define DISPPLANE_8BPP (0x2<<26) 4219#define DISPPLANE_BGRA555 (0x3<<26) 4220#define DISPPLANE_BGRX555 (0x4<<26) 4221#define DISPPLANE_BGRX565 (0x5<<26) 4222#define DISPPLANE_BGRX888 (0x6<<26) 4223#define DISPPLANE_BGRA888 (0x7<<26) 4224#define DISPPLANE_RGBX101010 (0x8<<26) 4225#define DISPPLANE_RGBA101010 (0x9<<26) 4226#define DISPPLANE_BGRX101010 (0xa<<26) 4227#define DISPPLANE_RGBX161616 (0xc<<26) 4228#define DISPPLANE_RGBX888 (0xe<<26) 4229#define DISPPLANE_RGBA888 (0xf<<26) 4230#define DISPPLANE_STEREO_ENABLE (1<<25) 4231#define DISPPLANE_STEREO_DISABLE 0 4232#define DISPPLANE_PIPE_CSC_ENABLE (1<<24) 4233#define DISPPLANE_SEL_PIPE_SHIFT 24 4234#define DISPPLANE_SEL_PIPE_MASK (3<<DISPPLANE_SEL_PIPE_SHIFT) 4235#define DISPPLANE_SEL_PIPE_A 0 4236#define DISPPLANE_SEL_PIPE_B (1<<DISPPLANE_SEL_PIPE_SHIFT) 4237#define DISPPLANE_SRC_KEY_ENABLE (1<<22) 4238#define DISPPLANE_SRC_KEY_DISABLE 0 4239#define DISPPLANE_LINE_DOUBLE (1<<20) 4240#define DISPPLANE_NO_LINE_DOUBLE 0 4241#define DISPPLANE_STEREO_POLARITY_FIRST 0 4242#define DISPPLANE_STEREO_POLARITY_SECOND (1<<18) 4243#define DISPPLANE_ROTATE_180 (1<<15) 4244#define DISPPLANE_TRICKLE_FEED_DISABLE (1<<14) /* Ironlake */ 4245#define DISPPLANE_TILED (1<<10) 4246#define _DSPAADDR 0x70184 4247#define _DSPASTRIDE 0x70188 4248#define _DSPAPOS 0x7018C /* reserved */ 4249#define _DSPASIZE 0x70190 4250#define _DSPASURF 0x7019C /* 965+ only */ 4251#define _DSPATILEOFF 0x701A4 /* 965+ only */ 4252#define _DSPAOFFSET 0x701A4 /* HSW */ 4253#define _DSPASURFLIVE 0x701AC 4254 4255#define DSPCNTR(plane) _PIPE2(plane, _DSPACNTR) 4256#define DSPADDR(plane) _PIPE2(plane, _DSPAADDR) 4257#define DSPSTRIDE(plane) _PIPE2(plane, _DSPASTRIDE) 4258#define DSPPOS(plane) _PIPE2(plane, _DSPAPOS) 4259#define DSPSIZE(plane) _PIPE2(plane, _DSPASIZE) 4260#define DSPSURF(plane) _PIPE2(plane, _DSPASURF) 4261#define DSPTILEOFF(plane) _PIPE2(plane, _DSPATILEOFF) 4262#define DSPLINOFF(plane) DSPADDR(plane) 4263#define DSPOFFSET(plane) _PIPE2(plane, _DSPAOFFSET) 4264#define DSPSURFLIVE(plane) _PIPE2(plane, _DSPASURFLIVE) 4265 4266/* Display/Sprite base address macros */ 4267#define DISP_BASEADDR_MASK (0xfffff000) 4268#define I915_LO_DISPBASE(val) (val & ~DISP_BASEADDR_MASK) 4269#define I915_HI_DISPBASE(val) (val & DISP_BASEADDR_MASK) 4270 4271/* VBIOS flags */ 4272#define SWF00 (dev_priv->info.display_mmio_offset + 0x71410) 4273#define SWF01 (dev_priv->info.display_mmio_offset + 0x71414) 4274#define SWF02 (dev_priv->info.display_mmio_offset + 0x71418) 4275#define SWF03 (dev_priv->info.display_mmio_offset + 0x7141c) 4276#define SWF04 (dev_priv->info.display_mmio_offset + 0x71420) 4277#define SWF05 (dev_priv->info.display_mmio_offset + 0x71424) 4278#define SWF06 (dev_priv->info.display_mmio_offset + 0x71428) 4279#define SWF10 (dev_priv->info.display_mmio_offset + 0x70410) 4280#define SWF11 (dev_priv->info.display_mmio_offset + 0x70414) 4281#define SWF14 (dev_priv->info.display_mmio_offset + 0x71420) 4282#define SWF30 (dev_priv->info.display_mmio_offset + 0x72414) 4283#define SWF31 (dev_priv->info.display_mmio_offset + 0x72418) 4284#define SWF32 (dev_priv->info.display_mmio_offset + 0x7241c) 4285 4286/* Pipe B */ 4287#define _PIPEBDSL (dev_priv->info.display_mmio_offset + 0x71000) 4288#define _PIPEBCONF (dev_priv->info.display_mmio_offset + 0x71008) 4289#define _PIPEBSTAT (dev_priv->info.display_mmio_offset + 0x71024) 4290#define _PIPEBFRAMEHIGH 0x71040 4291#define _PIPEBFRAMEPIXEL 0x71044 4292#define _PIPEB_FRMCOUNT_GM45 (dev_priv->info.display_mmio_offset + 0x71040) 4293#define _PIPEB_FLIPCOUNT_GM45 (dev_priv->info.display_mmio_offset + 0x71044) 4294 4295 4296/* Display B control */ 4297#define _DSPBCNTR (dev_priv->info.display_mmio_offset + 0x71180) 4298#define DISPPLANE_ALPHA_TRANS_ENABLE (1<<15) 4299#define DISPPLANE_ALPHA_TRANS_DISABLE 0 4300#define DISPPLANE_SPRITE_ABOVE_DISPLAY 0 4301#define DISPPLANE_SPRITE_ABOVE_OVERLAY (1) 4302#define _DSPBADDR (dev_priv->info.display_mmio_offset + 0x71184) 4303#define _DSPBSTRIDE (dev_priv->info.display_mmio_offset + 0x71188) 4304#define _DSPBPOS (dev_priv->info.display_mmio_offset + 0x7118C) 4305#define _DSPBSIZE (dev_priv->info.display_mmio_offset + 0x71190) 4306#define _DSPBSURF (dev_priv->info.display_mmio_offset + 0x7119C) 4307#define _DSPBTILEOFF (dev_priv->info.display_mmio_offset + 0x711A4) 4308#define _DSPBOFFSET (dev_priv->info.display_mmio_offset + 0x711A4) 4309#define _DSPBSURFLIVE (dev_priv->info.display_mmio_offset + 0x711AC) 4310 4311/* Sprite A control */ 4312#define _DVSACNTR 0x72180 4313#define DVS_ENABLE (1<<31) 4314#define DVS_GAMMA_ENABLE (1<<30) 4315#define DVS_PIXFORMAT_MASK (3<<25) 4316#define DVS_FORMAT_YUV422 (0<<25) 4317#define DVS_FORMAT_RGBX101010 (1<<25) 4318#define DVS_FORMAT_RGBX888 (2<<25) 4319#define DVS_FORMAT_RGBX161616 (3<<25) 4320#define DVS_PIPE_CSC_ENABLE (1<<24) 4321#define DVS_SOURCE_KEY (1<<22) 4322#define DVS_RGB_ORDER_XBGR (1<<20) 4323#define DVS_YUV_BYTE_ORDER_MASK (3<<16) 4324#define DVS_YUV_ORDER_YUYV (0<<16) 4325#define DVS_YUV_ORDER_UYVY (1<<16) 4326#define DVS_YUV_ORDER_YVYU (2<<16) 4327#define DVS_YUV_ORDER_VYUY (3<<16) 4328#define DVS_ROTATE_180 (1<<15) 4329#define DVS_DEST_KEY (1<<2) 4330#define DVS_TRICKLE_FEED_DISABLE (1<<14) 4331#define DVS_TILED (1<<10) 4332#define _DVSALINOFF 0x72184 4333#define _DVSASTRIDE 0x72188 4334#define _DVSAPOS 0x7218c 4335#define _DVSASIZE 0x72190 4336#define _DVSAKEYVAL 0x72194 4337#define _DVSAKEYMSK 0x72198 4338#define _DVSASURF 0x7219c 4339#define _DVSAKEYMAXVAL 0x721a0 4340#define _DVSATILEOFF 0x721a4 4341#define _DVSASURFLIVE 0x721ac 4342#define _DVSASCALE 0x72204 4343#define DVS_SCALE_ENABLE (1<<31) 4344#define DVS_FILTER_MASK (3<<29) 4345#define DVS_FILTER_MEDIUM (0<<29) 4346#define DVS_FILTER_ENHANCING (1<<29) 4347#define DVS_FILTER_SOFTENING (2<<29) 4348#define DVS_VERTICAL_OFFSET_HALF (1<<28) /* must be enabled below */ 4349#define DVS_VERTICAL_OFFSET_ENABLE (1<<27) 4350#define _DVSAGAMC 0x72300 4351 4352#define _DVSBCNTR 0x73180 4353#define _DVSBLINOFF 0x73184 4354#define _DVSBSTRIDE 0x73188 4355#define _DVSBPOS 0x7318c 4356#define _DVSBSIZE 0x73190 4357#define _DVSBKEYVAL 0x73194 4358#define _DVSBKEYMSK 0x73198 4359#define _DVSBSURF 0x7319c 4360#define _DVSBKEYMAXVAL 0x731a0 4361#define _DVSBTILEOFF 0x731a4 4362#define _DVSBSURFLIVE 0x731ac 4363#define _DVSBSCALE 0x73204 4364#define _DVSBGAMC 0x73300 4365 4366#define DVSCNTR(pipe) _PIPE(pipe, _DVSACNTR, _DVSBCNTR) 4367#define DVSLINOFF(pipe) _PIPE(pipe, _DVSALINOFF, _DVSBLINOFF) 4368#define DVSSTRIDE(pipe) _PIPE(pipe, _DVSASTRIDE, _DVSBSTRIDE) 4369#define DVSPOS(pipe) _PIPE(pipe, _DVSAPOS, _DVSBPOS) 4370#define DVSSURF(pipe) _PIPE(pipe, _DVSASURF, _DVSBSURF) 4371#define DVSKEYMAX(pipe) _PIPE(pipe, _DVSAKEYMAXVAL, _DVSBKEYMAXVAL) 4372#define DVSSIZE(pipe) _PIPE(pipe, _DVSASIZE, _DVSBSIZE) 4373#define DVSSCALE(pipe) _PIPE(pipe, _DVSASCALE, _DVSBSCALE) 4374#define DVSTILEOFF(pipe) _PIPE(pipe, _DVSATILEOFF, _DVSBTILEOFF) 4375#define DVSKEYVAL(pipe) _PIPE(pipe, _DVSAKEYVAL, _DVSBKEYVAL) 4376#define DVSKEYMSK(pipe) _PIPE(pipe, _DVSAKEYMSK, _DVSBKEYMSK) 4377#define DVSSURFLIVE(pipe) _PIPE(pipe, _DVSASURFLIVE, _DVSBSURFLIVE) 4378 4379#define _SPRA_CTL 0x70280 4380#define SPRITE_ENABLE (1<<31) 4381#define SPRITE_GAMMA_ENABLE (1<<30) 4382#define SPRITE_PIXFORMAT_MASK (7<<25) 4383#define SPRITE_FORMAT_YUV422 (0<<25) 4384#define SPRITE_FORMAT_RGBX101010 (1<<25) 4385#define SPRITE_FORMAT_RGBX888 (2<<25) 4386#define SPRITE_FORMAT_RGBX161616 (3<<25) 4387#define SPRITE_FORMAT_YUV444 (4<<25) 4388#define SPRITE_FORMAT_XR_BGR101010 (5<<25) /* Extended range */ 4389#define SPRITE_PIPE_CSC_ENABLE (1<<24) 4390#define SPRITE_SOURCE_KEY (1<<22) 4391#define SPRITE_RGB_ORDER_RGBX (1<<20) /* only for 888 and 161616 */ 4392#define SPRITE_YUV_TO_RGB_CSC_DISABLE (1<<19) 4393#define SPRITE_YUV_CSC_FORMAT_BT709 (1<<18) /* 0 is BT601 */ 4394#define SPRITE_YUV_BYTE_ORDER_MASK (3<<16) 4395#define SPRITE_YUV_ORDER_YUYV (0<<16) 4396#define SPRITE_YUV_ORDER_UYVY (1<<16) 4397#define SPRITE_YUV_ORDER_YVYU (2<<16) 4398#define SPRITE_YUV_ORDER_VYUY (3<<16) 4399#define SPRITE_ROTATE_180 (1<<15) 4400#define SPRITE_TRICKLE_FEED_DISABLE (1<<14) 4401#define SPRITE_INT_GAMMA_ENABLE (1<<13) 4402#define SPRITE_TILED (1<<10) 4403#define SPRITE_DEST_KEY (1<<2) 4404#define _SPRA_LINOFF 0x70284 4405#define _SPRA_STRIDE 0x70288 4406#define _SPRA_POS 0x7028c 4407#define _SPRA_SIZE 0x70290 4408#define _SPRA_KEYVAL 0x70294 4409#define _SPRA_KEYMSK 0x70298 4410#define _SPRA_SURF 0x7029c 4411#define _SPRA_KEYMAX 0x702a0 4412#define _SPRA_TILEOFF 0x702a4 4413#define _SPRA_OFFSET 0x702a4 4414#define _SPRA_SURFLIVE 0x702ac 4415#define _SPRA_SCALE 0x70304 4416#define SPRITE_SCALE_ENABLE (1<<31) 4417#define SPRITE_FILTER_MASK (3<<29) 4418#define SPRITE_FILTER_MEDIUM (0<<29) 4419#define SPRITE_FILTER_ENHANCING (1<<29) 4420#define SPRITE_FILTER_SOFTENING (2<<29) 4421#define SPRITE_VERTICAL_OFFSET_HALF (1<<28) /* must be enabled below */ 4422#define SPRITE_VERTICAL_OFFSET_ENABLE (1<<27) 4423#define _SPRA_GAMC 0x70400 4424 4425#define _SPRB_CTL 0x71280 4426#define _SPRB_LINOFF 0x71284 4427#define _SPRB_STRIDE 0x71288 4428#define _SPRB_POS 0x7128c 4429#define _SPRB_SIZE 0x71290 4430#define _SPRB_KEYVAL 0x71294 4431#define _SPRB_KEYMSK 0x71298 4432#define _SPRB_SURF 0x7129c 4433#define _SPRB_KEYMAX 0x712a0 4434#define _SPRB_TILEOFF 0x712a4 4435#define _SPRB_OFFSET 0x712a4 4436#define _SPRB_SURFLIVE 0x712ac 4437#define _SPRB_SCALE 0x71304 4438#define _SPRB_GAMC 0x71400 4439 4440#define SPRCTL(pipe) _PIPE(pipe, _SPRA_CTL, _SPRB_CTL) 4441#define SPRLINOFF(pipe) _PIPE(pipe, _SPRA_LINOFF, _SPRB_LINOFF) 4442#define SPRSTRIDE(pipe) _PIPE(pipe, _SPRA_STRIDE, _SPRB_STRIDE) 4443#define SPRPOS(pipe) _PIPE(pipe, _SPRA_POS, _SPRB_POS) 4444#define SPRSIZE(pipe) _PIPE(pipe, _SPRA_SIZE, _SPRB_SIZE) 4445#define SPRKEYVAL(pipe) _PIPE(pipe, _SPRA_KEYVAL, _SPRB_KEYVAL) 4446#define SPRKEYMSK(pipe) _PIPE(pipe, _SPRA_KEYMSK, _SPRB_KEYMSK) 4447#define SPRSURF(pipe) _PIPE(pipe, _SPRA_SURF, _SPRB_SURF) 4448#define SPRKEYMAX(pipe) _PIPE(pipe, _SPRA_KEYMAX, _SPRB_KEYMAX) 4449#define SPRTILEOFF(pipe) _PIPE(pipe, _SPRA_TILEOFF, _SPRB_TILEOFF) 4450#define SPROFFSET(pipe) _PIPE(pipe, _SPRA_OFFSET, _SPRB_OFFSET) 4451#define SPRSCALE(pipe) _PIPE(pipe, _SPRA_SCALE, _SPRB_SCALE) 4452#define SPRGAMC(pipe) _PIPE(pipe, _SPRA_GAMC, _SPRB_GAMC) 4453#define SPRSURFLIVE(pipe) _PIPE(pipe, _SPRA_SURFLIVE, _SPRB_SURFLIVE) 4454 4455#define _SPACNTR (VLV_DISPLAY_BASE + 0x72180) 4456#define SP_ENABLE (1<<31) 4457#define SP_GAMMA_ENABLE (1<<30) 4458#define SP_PIXFORMAT_MASK (0xf<<26) 4459#define SP_FORMAT_YUV422 (0<<26) 4460#define SP_FORMAT_BGR565 (5<<26) 4461#define SP_FORMAT_BGRX8888 (6<<26) 4462#define SP_FORMAT_BGRA8888 (7<<26) 4463#define SP_FORMAT_RGBX1010102 (8<<26) 4464#define SP_FORMAT_RGBA1010102 (9<<26) 4465#define SP_FORMAT_RGBX8888 (0xe<<26) 4466#define SP_FORMAT_RGBA8888 (0xf<<26) 4467#define SP_SOURCE_KEY (1<<22) 4468#define SP_YUV_BYTE_ORDER_MASK (3<<16) 4469#define SP_YUV_ORDER_YUYV (0<<16) 4470#define SP_YUV_ORDER_UYVY (1<<16) 4471#define SP_YUV_ORDER_YVYU (2<<16) 4472#define SP_YUV_ORDER_VYUY (3<<16) 4473#define SP_ROTATE_180 (1<<15) 4474#define SP_TILED (1<<10) 4475#define _SPALINOFF (VLV_DISPLAY_BASE + 0x72184) 4476#define _SPASTRIDE (VLV_DISPLAY_BASE + 0x72188) 4477#define _SPAPOS (VLV_DISPLAY_BASE + 0x7218c) 4478#define _SPASIZE (VLV_DISPLAY_BASE + 0x72190) 4479#define _SPAKEYMINVAL (VLV_DISPLAY_BASE + 0x72194) 4480#define _SPAKEYMSK (VLV_DISPLAY_BASE + 0x72198) 4481#define _SPASURF (VLV_DISPLAY_BASE + 0x7219c) 4482#define _SPAKEYMAXVAL (VLV_DISPLAY_BASE + 0x721a0) 4483#define _SPATILEOFF (VLV_DISPLAY_BASE + 0x721a4) 4484#define _SPACONSTALPHA (VLV_DISPLAY_BASE + 0x721a8) 4485#define _SPAGAMC (VLV_DISPLAY_BASE + 0x721f4) 4486 4487#define _SPBCNTR (VLV_DISPLAY_BASE + 0x72280) 4488#define _SPBLINOFF (VLV_DISPLAY_BASE + 0x72284) 4489#define _SPBSTRIDE (VLV_DISPLAY_BASE + 0x72288) 4490#define _SPBPOS (VLV_DISPLAY_BASE + 0x7228c) 4491#define _SPBSIZE (VLV_DISPLAY_BASE + 0x72290) 4492#define _SPBKEYMINVAL (VLV_DISPLAY_BASE + 0x72294) 4493#define _SPBKEYMSK (VLV_DISPLAY_BASE + 0x72298) 4494#define _SPBSURF (VLV_DISPLAY_BASE + 0x7229c) 4495#define _SPBKEYMAXVAL (VLV_DISPLAY_BASE + 0x722a0) 4496#define _SPBTILEOFF (VLV_DISPLAY_BASE + 0x722a4) 4497#define _SPBCONSTALPHA (VLV_DISPLAY_BASE + 0x722a8) 4498#define _SPBGAMC (VLV_DISPLAY_BASE + 0x722f4) 4499 4500#define SPCNTR(pipe, plane) _PIPE(pipe * 2 + plane, _SPACNTR, _SPBCNTR) 4501#define SPLINOFF(pipe, plane) _PIPE(pipe * 2 + plane, _SPALINOFF, _SPBLINOFF) 4502#define SPSTRIDE(pipe, plane) _PIPE(pipe * 2 + plane, _SPASTRIDE, _SPBSTRIDE) 4503#define SPPOS(pipe, plane) _PIPE(pipe * 2 + plane, _SPAPOS, _SPBPOS) 4504#define SPSIZE(pipe, plane) _PIPE(pipe * 2 + plane, _SPASIZE, _SPBSIZE) 4505#define SPKEYMINVAL(pipe, plane) _PIPE(pipe * 2 + plane, _SPAKEYMINVAL, _SPBKEYMINVAL) 4506#define SPKEYMSK(pipe, plane) _PIPE(pipe * 2 + plane, _SPAKEYMSK, _SPBKEYMSK) 4507#define SPSURF(pipe, plane) _PIPE(pipe * 2 + plane, _SPASURF, _SPBSURF) 4508#define SPKEYMAXVAL(pipe, plane) _PIPE(pipe * 2 + plane, _SPAKEYMAXVAL, _SPBKEYMAXVAL) 4509#define SPTILEOFF(pipe, plane) _PIPE(pipe * 2 + plane, _SPATILEOFF, _SPBTILEOFF) 4510#define SPCONSTALPHA(pipe, plane) _PIPE(pipe * 2 + plane, _SPACONSTALPHA, _SPBCONSTALPHA) 4511#define SPGAMC(pipe, plane) _PIPE(pipe * 2 + plane, _SPAGAMC, _SPBGAMC) 4512 4513/* VBIOS regs */ 4514#define VGACNTRL 0x71400 4515# define VGA_DISP_DISABLE (1 << 31) 4516# define VGA_2X_MODE (1 << 30) 4517# define VGA_PIPE_B_SELECT (1 << 29) 4518 4519#define VLV_VGACNTRL (VLV_DISPLAY_BASE + 0x71400) 4520 4521/* Ironlake */ 4522 4523#define CPU_VGACNTRL 0x41000 4524 4525#define DIGITAL_PORT_HOTPLUG_CNTRL 0x44030 4526#define DIGITAL_PORTA_HOTPLUG_ENABLE (1 << 4) 4527#define DIGITAL_PORTA_SHORT_PULSE_2MS (0 << 2) 4528#define DIGITAL_PORTA_SHORT_PULSE_4_5MS (1 << 2) 4529#define DIGITAL_PORTA_SHORT_PULSE_6MS (2 << 2) 4530#define DIGITAL_PORTA_SHORT_PULSE_100MS (3 << 2) 4531#define DIGITAL_PORTA_NO_DETECT (0 << 0) 4532#define DIGITAL_PORTA_LONG_PULSE_DETECT_MASK (1 << 1) 4533#define DIGITAL_PORTA_SHORT_PULSE_DETECT_MASK (1 << 0) 4534 4535/* refresh rate hardware control */ 4536#define RR_HW_CTL 0x45300 4537#define RR_HW_LOW_POWER_FRAMES_MASK 0xff 4538#define RR_HW_HIGH_POWER_FRAMES_MASK 0xff00 4539 4540#define FDI_PLL_BIOS_0 0x46000 4541#define FDI_PLL_FB_CLOCK_MASK 0xff 4542#define FDI_PLL_BIOS_1 0x46004 4543#define FDI_PLL_BIOS_2 0x46008 4544#define DISPLAY_PORT_PLL_BIOS_0 0x4600c 4545#define DISPLAY_PORT_PLL_BIOS_1 0x46010 4546#define DISPLAY_PORT_PLL_BIOS_2 0x46014 4547 4548#define PCH_3DCGDIS0 0x46020 4549# define MARIUNIT_CLOCK_GATE_DISABLE (1 << 18) 4550# define SVSMUNIT_CLOCK_GATE_DISABLE (1 << 1) 4551 4552#define PCH_3DCGDIS1 0x46024 4553# define VFMUNIT_CLOCK_GATE_DISABLE (1 << 11) 4554 4555#define FDI_PLL_FREQ_CTL 0x46030 4556#define FDI_PLL_FREQ_CHANGE_REQUEST (1<<24) 4557#define FDI_PLL_FREQ_LOCK_LIMIT_MASK 0xfff00 4558#define FDI_PLL_FREQ_DISABLE_COUNT_LIMIT_MASK 0xff 4559 4560 4561#define _PIPEA_DATA_M1 0x60030 4562#define PIPE_DATA_M1_OFFSET 0 4563#define _PIPEA_DATA_N1 0x60034 4564#define PIPE_DATA_N1_OFFSET 0 4565 4566#define _PIPEA_DATA_M2 0x60038 4567#define PIPE_DATA_M2_OFFSET 0 4568#define _PIPEA_DATA_N2 0x6003c 4569#define PIPE_DATA_N2_OFFSET 0 4570 4571#define _PIPEA_LINK_M1 0x60040 4572#define PIPE_LINK_M1_OFFSET 0 4573#define _PIPEA_LINK_N1 0x60044 4574#define PIPE_LINK_N1_OFFSET 0 4575 4576#define _PIPEA_LINK_M2 0x60048 4577#define PIPE_LINK_M2_OFFSET 0 4578#define _PIPEA_LINK_N2 0x6004c 4579#define PIPE_LINK_N2_OFFSET 0 4580 4581/* PIPEB timing regs are same start from 0x61000 */ 4582 4583#define _PIPEB_DATA_M1 0x61030 4584#define _PIPEB_DATA_N1 0x61034 4585#define _PIPEB_DATA_M2 0x61038 4586#define _PIPEB_DATA_N2 0x6103c 4587#define _PIPEB_LINK_M1 0x61040 4588#define _PIPEB_LINK_N1 0x61044 4589#define _PIPEB_LINK_M2 0x61048 4590#define _PIPEB_LINK_N2 0x6104c 4591 4592#define PIPE_DATA_M1(tran) _TRANSCODER2(tran, _PIPEA_DATA_M1) 4593#define PIPE_DATA_N1(tran) _TRANSCODER2(tran, _PIPEA_DATA_N1) 4594#define PIPE_DATA_M2(tran) _TRANSCODER2(tran, _PIPEA_DATA_M2) 4595#define PIPE_DATA_N2(tran) _TRANSCODER2(tran, _PIPEA_DATA_N2) 4596#define PIPE_LINK_M1(tran) _TRANSCODER2(tran, _PIPEA_LINK_M1) 4597#define PIPE_LINK_N1(tran) _TRANSCODER2(tran, _PIPEA_LINK_N1) 4598#define PIPE_LINK_M2(tran) _TRANSCODER2(tran, _PIPEA_LINK_M2) 4599#define PIPE_LINK_N2(tran) _TRANSCODER2(tran, _PIPEA_LINK_N2) 4600 4601/* CPU panel fitter */ 4602/* IVB+ has 3 fitters, 0 is 7x5 capable, the other two only 3x3 */ 4603#define _PFA_CTL_1 0x68080 4604#define _PFB_CTL_1 0x68880 4605#define PF_ENABLE (1<<31) 4606#define PF_PIPE_SEL_MASK_IVB (3<<29) 4607#define PF_PIPE_SEL_IVB(pipe) ((pipe)<<29) 4608#define PF_FILTER_MASK (3<<23) 4609#define PF_FILTER_PROGRAMMED (0<<23) 4610#define PF_FILTER_MED_3x3 (1<<23) 4611#define PF_FILTER_EDGE_ENHANCE (2<<23) 4612#define PF_FILTER_EDGE_SOFTEN (3<<23) 4613#define _PFA_WIN_SZ 0x68074 4614#define _PFB_WIN_SZ 0x68874 4615#define _PFA_WIN_POS 0x68070 4616#define _PFB_WIN_POS 0x68870 4617#define _PFA_VSCALE 0x68084 4618#define _PFB_VSCALE 0x68884 4619#define _PFA_HSCALE 0x68090 4620#define _PFB_HSCALE 0x68890 4621 4622#define PF_CTL(pipe) _PIPE(pipe, _PFA_CTL_1, _PFB_CTL_1) 4623#define PF_WIN_SZ(pipe) _PIPE(pipe, _PFA_WIN_SZ, _PFB_WIN_SZ) 4624#define PF_WIN_POS(pipe) _PIPE(pipe, _PFA_WIN_POS, _PFB_WIN_POS) 4625#define PF_VSCALE(pipe) _PIPE(pipe, _PFA_VSCALE, _PFB_VSCALE) 4626#define PF_HSCALE(pipe) _PIPE(pipe, _PFA_HSCALE, _PFB_HSCALE) 4627 4628/* legacy palette */ 4629#define _LGC_PALETTE_A 0x4a000 4630#define _LGC_PALETTE_B 0x4a800 4631#define LGC_PALETTE(pipe) _PIPE(pipe, _LGC_PALETTE_A, _LGC_PALETTE_B) 4632 4633#define _GAMMA_MODE_A 0x4a480 4634#define _GAMMA_MODE_B 0x4ac80 4635#define GAMMA_MODE(pipe) _PIPE(pipe, _GAMMA_MODE_A, _GAMMA_MODE_B) 4636#define GAMMA_MODE_MODE_MASK (3 << 0) 4637#define GAMMA_MODE_MODE_8BIT (0 << 0) 4638#define GAMMA_MODE_MODE_10BIT (1 << 0) 4639#define GAMMA_MODE_MODE_12BIT (2 << 0) 4640#define GAMMA_MODE_MODE_SPLIT (3 << 0) 4641 4642/* interrupts */ 4643#define DE_MASTER_IRQ_CONTROL (1 << 31) 4644#define DE_SPRITEB_FLIP_DONE (1 << 29) 4645#define DE_SPRITEA_FLIP_DONE (1 << 28) 4646#define DE_PLANEB_FLIP_DONE (1 << 27) 4647#define DE_PLANEA_FLIP_DONE (1 << 26) 4648#define DE_PLANE_FLIP_DONE(plane) (1 << (26 + (plane))) 4649#define DE_PCU_EVENT (1 << 25) 4650#define DE_GTT_FAULT (1 << 24) 4651#define DE_POISON (1 << 23) 4652#define DE_PERFORM_COUNTER (1 << 22) 4653#define DE_PCH_EVENT (1 << 21) 4654#define DE_AUX_CHANNEL_A (1 << 20) 4655#define DE_DP_A_HOTPLUG (1 << 19) 4656#define DE_GSE (1 << 18) 4657#define DE_PIPEB_VBLANK (1 << 15) 4658#define DE_PIPEB_EVEN_FIELD (1 << 14) 4659#define DE_PIPEB_ODD_FIELD (1 << 13) 4660#define DE_PIPEB_LINE_COMPARE (1 << 12) 4661#define DE_PIPEB_VSYNC (1 << 11) 4662#define DE_PIPEB_CRC_DONE (1 << 10) 4663#define DE_PIPEB_FIFO_UNDERRUN (1 << 8) 4664#define DE_PIPEA_VBLANK (1 << 7) 4665#define DE_PIPE_VBLANK(pipe) (1 << (7 + 8*(pipe))) 4666#define DE_PIPEA_EVEN_FIELD (1 << 6) 4667#define DE_PIPEA_ODD_FIELD (1 << 5) 4668#define DE_PIPEA_LINE_COMPARE (1 << 4) 4669#define DE_PIPEA_VSYNC (1 << 3) 4670#define DE_PIPEA_CRC_DONE (1 << 2) 4671#define DE_PIPE_CRC_DONE(pipe) (1 << (2 + 8*(pipe))) 4672#define DE_PIPEA_FIFO_UNDERRUN (1 << 0) 4673#define DE_PIPE_FIFO_UNDERRUN(pipe) (1 << (8*(pipe))) 4674 4675/* More Ivybridge lolz */ 4676#define DE_ERR_INT_IVB (1<<30) 4677#define DE_GSE_IVB (1<<29) 4678#define DE_PCH_EVENT_IVB (1<<28) 4679#define DE_DP_A_HOTPLUG_IVB (1<<27) 4680#define DE_AUX_CHANNEL_A_IVB (1<<26) 4681#define DE_SPRITEC_FLIP_DONE_IVB (1<<14) 4682#define DE_PLANEC_FLIP_DONE_IVB (1<<13) 4683#define DE_PIPEC_VBLANK_IVB (1<<10) 4684#define DE_SPRITEB_FLIP_DONE_IVB (1<<9) 4685#define DE_PLANEB_FLIP_DONE_IVB (1<<8) 4686#define DE_PIPEB_VBLANK_IVB (1<<5) 4687#define DE_SPRITEA_FLIP_DONE_IVB (1<<4) 4688#define DE_PLANEA_FLIP_DONE_IVB (1<<3) 4689#define DE_PLANE_FLIP_DONE_IVB(plane) (1<< (3 + 5*(plane))) 4690#define DE_PIPEA_VBLANK_IVB (1<<0) 4691#define DE_PIPE_VBLANK_IVB(pipe) (1 << (pipe * 5)) 4692 4693#define VLV_MASTER_IER 0x4400c /* Gunit master IER */ 4694#define MASTER_INTERRUPT_ENABLE (1<<31) 4695 4696#define DEISR 0x44000 4697#define DEIMR 0x44004 4698#define DEIIR 0x44008 4699#define DEIER 0x4400c 4700 4701#define GTISR 0x44010 4702#define GTIMR 0x44014 4703#define GTIIR 0x44018 4704#define GTIER 0x4401c 4705 4706#define GEN8_MASTER_IRQ 0x44200 4707#define GEN8_MASTER_IRQ_CONTROL (1<<31) 4708#define GEN8_PCU_IRQ (1<<30) 4709#define GEN8_DE_PCH_IRQ (1<<23) 4710#define GEN8_DE_MISC_IRQ (1<<22) 4711#define GEN8_DE_PORT_IRQ (1<<20) 4712#define GEN8_DE_PIPE_C_IRQ (1<<18) 4713#define GEN8_DE_PIPE_B_IRQ (1<<17) 4714#define GEN8_DE_PIPE_A_IRQ (1<<16) 4715#define GEN8_DE_PIPE_IRQ(pipe) (1<<(16+pipe)) 4716#define GEN8_GT_VECS_IRQ (1<<6) 4717#define GEN8_GT_PM_IRQ (1<<4) 4718#define GEN8_GT_VCS2_IRQ (1<<3) 4719#define GEN8_GT_VCS1_IRQ (1<<2) 4720#define GEN8_GT_BCS_IRQ (1<<1) 4721#define GEN8_GT_RCS_IRQ (1<<0) 4722 4723#define GEN8_GT_ISR(which) (0x44300 + (0x10 * (which))) 4724#define GEN8_GT_IMR(which) (0x44304 + (0x10 * (which))) 4725#define GEN8_GT_IIR(which) (0x44308 + (0x10 * (which))) 4726#define GEN8_GT_IER(which) (0x4430c + (0x10 * (which))) 4727 4728#define GEN8_BCS_IRQ_SHIFT 16 4729#define GEN8_RCS_IRQ_SHIFT 0 4730#define GEN8_VCS2_IRQ_SHIFT 16 4731#define GEN8_VCS1_IRQ_SHIFT 0 4732#define GEN8_VECS_IRQ_SHIFT 0 4733 4734#define GEN8_DE_PIPE_ISR(pipe) (0x44400 + (0x10 * (pipe))) 4735#define GEN8_DE_PIPE_IMR(pipe) (0x44404 + (0x10 * (pipe))) 4736#define GEN8_DE_PIPE_IIR(pipe) (0x44408 + (0x10 * (pipe))) 4737#define GEN8_DE_PIPE_IER(pipe) (0x4440c + (0x10 * (pipe))) 4738#define GEN8_PIPE_FIFO_UNDERRUN (1 << 31) 4739#define GEN8_PIPE_CDCLK_CRC_ERROR (1 << 29) 4740#define GEN8_PIPE_CDCLK_CRC_DONE (1 << 28) 4741#define GEN8_PIPE_CURSOR_FAULT (1 << 10) 4742#define GEN8_PIPE_SPRITE_FAULT (1 << 9) 4743#define GEN8_PIPE_PRIMARY_FAULT (1 << 8) 4744#define GEN8_PIPE_SPRITE_FLIP_DONE (1 << 5) 4745#define GEN8_PIPE_PRIMARY_FLIP_DONE (1 << 4) 4746#define GEN8_PIPE_SCAN_LINE_EVENT (1 << 2) 4747#define GEN8_PIPE_VSYNC (1 << 1) 4748#define GEN8_PIPE_VBLANK (1 << 0) 4749#define GEN8_DE_PIPE_IRQ_FAULT_ERRORS \ 4750 (GEN8_PIPE_CURSOR_FAULT | \ 4751 GEN8_PIPE_SPRITE_FAULT | \ 4752 GEN8_PIPE_PRIMARY_FAULT) 4753 4754#define GEN8_DE_PORT_ISR 0x44440 4755#define GEN8_DE_PORT_IMR 0x44444 4756#define GEN8_DE_PORT_IIR 0x44448 4757#define GEN8_DE_PORT_IER 0x4444c 4758#define GEN8_PORT_DP_A_HOTPLUG (1 << 3) 4759#define GEN8_AUX_CHANNEL_A (1 << 0) 4760 4761#define GEN8_DE_MISC_ISR 0x44460 4762#define GEN8_DE_MISC_IMR 0x44464 4763#define GEN8_DE_MISC_IIR 0x44468 4764#define GEN8_DE_MISC_IER 0x4446c 4765#define GEN8_DE_MISC_GSE (1 << 27) 4766 4767#define GEN8_PCU_ISR 0x444e0 4768#define GEN8_PCU_IMR 0x444e4 4769#define GEN8_PCU_IIR 0x444e8 4770#define GEN8_PCU_IER 0x444ec 4771 4772#define ILK_DISPLAY_CHICKEN2 0x42004 4773/* Required on all Ironlake and Sandybridge according to the B-Spec. */ 4774#define ILK_ELPIN_409_SELECT (1 << 25) 4775#define ILK_DPARB_GATE (1<<22) 4776#define ILK_VSDPFD_FULL (1<<21) 4777#define FUSE_STRAP 0x42014 4778#define ILK_INTERNAL_GRAPHICS_DISABLE (1 << 31) 4779#define ILK_INTERNAL_DISPLAY_DISABLE (1 << 30) 4780#define ILK_DISPLAY_DEBUG_DISABLE (1 << 29) 4781#define ILK_HDCP_DISABLE (1 << 25) 4782#define ILK_eDP_A_DISABLE (1 << 24) 4783#define HSW_CDCLK_LIMIT (1 << 24) 4784#define ILK_DESKTOP (1 << 23) 4785 4786#define ILK_DSPCLK_GATE_D 0x42020 4787#define ILK_VRHUNIT_CLOCK_GATE_DISABLE (1 << 28) 4788#define ILK_DPFCUNIT_CLOCK_GATE_DISABLE (1 << 9) 4789#define ILK_DPFCRUNIT_CLOCK_GATE_DISABLE (1 << 8) 4790#define ILK_DPFDUNIT_CLOCK_GATE_ENABLE (1 << 7) 4791#define ILK_DPARBUNIT_CLOCK_GATE_ENABLE (1 << 5) 4792 4793#define IVB_CHICKEN3 0x4200c 4794# define CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE (1 << 5) 4795# define CHICKEN3_DGMG_DONE_FIX_DISABLE (1 << 2) 4796 4797#define CHICKEN_PAR1_1 0x42080 4798#define DPA_MASK_VBLANK_SRD (1 << 15) 4799#define FORCE_ARB_IDLE_PLANES (1 << 14) 4800 4801#define _CHICKEN_PIPESL_1_A 0x420b0 4802#define _CHICKEN_PIPESL_1_B 0x420b4 4803#define HSW_FBCQ_DIS (1 << 22) 4804#define BDW_DPRS_MASK_VBLANK_SRD (1 << 0) 4805#define CHICKEN_PIPESL_1(pipe) _PIPE(pipe, _CHICKEN_PIPESL_1_A, _CHICKEN_PIPESL_1_B) 4806 4807#define DISP_ARB_CTL 0x45000 4808#define DISP_TILE_SURFACE_SWIZZLING (1<<13) 4809#define DISP_FBC_WM_DIS (1<<15) 4810#define DISP_ARB_CTL2 0x45004 4811#define DISP_DATA_PARTITION_5_6 (1<<6) 4812#define GEN7_MSG_CTL 0x45010 4813#define WAIT_FOR_PCH_RESET_ACK (1<<1) 4814#define WAIT_FOR_PCH_FLR_ACK (1<<0) 4815#define HSW_NDE_RSTWRN_OPT 0x46408 4816#define RESET_PCH_HANDSHAKE_ENABLE (1<<4) 4817 4818/* GEN7 chicken */ 4819#define GEN7_COMMON_SLICE_CHICKEN1 0x7010 4820# define GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC ((1<<10) | (1<<26)) 4821#define COMMON_SLICE_CHICKEN2 0x7014 4822# define GEN8_CSC2_SBE_VUE_CACHE_CONSERVATIVE (1<<0) 4823 4824#define GEN7_L3SQCREG1 0xB010 4825#define VLV_B0_WA_L3SQCREG1_VALUE 0x00D30000 4826 4827#define GEN7_L3CNTLREG1 0xB01C 4828#define GEN7_WA_FOR_GEN7_L3_CONTROL 0x3C47FF8C 4829#define GEN7_L3AGDIS (1<<19) 4830#define GEN7_L3CNTLREG2 0xB020 4831#define GEN7_L3CNTLREG3 0xB024 4832 4833#define GEN7_L3_CHICKEN_MODE_REGISTER 0xB030 4834#define GEN7_WA_L3_CHICKEN_MODE 0x20000000 4835 4836#define GEN7_L3SQCREG4 0xb034 4837#define L3SQ_URB_READ_CAM_MATCH_DISABLE (1<<27) 4838 4839/* GEN8 chicken */ 4840#define HDC_CHICKEN0 0x7300 4841#define HDC_FORCE_NON_COHERENT (1<<4) 4842 4843/* WaCatErrorRejectionIssue */ 4844#define GEN7_SQ_CHICKEN_MBCUNIT_CONFIG 0x9030 4845#define GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB (1<<11) 4846 4847#define HSW_SCRATCH1 0xb038 4848#define HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE (1<<27) 4849 4850/* PCH */ 4851 4852/* south display engine interrupt: IBX */ 4853#define SDE_AUDIO_POWER_D (1 << 27) 4854#define SDE_AUDIO_POWER_C (1 << 26) 4855#define SDE_AUDIO_POWER_B (1 << 25) 4856#define SDE_AUDIO_POWER_SHIFT (25) 4857#define SDE_AUDIO_POWER_MASK (7 << SDE_AUDIO_POWER_SHIFT) 4858#define SDE_GMBUS (1 << 24) 4859#define SDE_AUDIO_HDCP_TRANSB (1 << 23) 4860#define SDE_AUDIO_HDCP_TRANSA (1 << 22) 4861#define SDE_AUDIO_HDCP_MASK (3 << 22) 4862#define SDE_AUDIO_TRANSB (1 << 21) 4863#define SDE_AUDIO_TRANSA (1 << 20) 4864#define SDE_AUDIO_TRANS_MASK (3 << 20) 4865#define SDE_POISON (1 << 19) 4866/* 18 reserved */ 4867#define SDE_FDI_RXB (1 << 17) 4868#define SDE_FDI_RXA (1 << 16) 4869#define SDE_FDI_MASK (3 << 16) 4870#define SDE_AUXD (1 << 15) 4871#define SDE_AUXC (1 << 14) 4872#define SDE_AUXB (1 << 13) 4873#define SDE_AUX_MASK (7 << 13) 4874/* 12 reserved */ 4875#define SDE_CRT_HOTPLUG (1 << 11) 4876#define SDE_PORTD_HOTPLUG (1 << 10) 4877#define SDE_PORTC_HOTPLUG (1 << 9) 4878#define SDE_PORTB_HOTPLUG (1 << 8) 4879#define SDE_SDVOB_HOTPLUG (1 << 6) 4880#define SDE_HOTPLUG_MASK (SDE_CRT_HOTPLUG | \ 4881 SDE_SDVOB_HOTPLUG | \ 4882 SDE_PORTB_HOTPLUG | \ 4883 SDE_PORTC_HOTPLUG | \ 4884 SDE_PORTD_HOTPLUG) 4885#define SDE_TRANSB_CRC_DONE (1 << 5) 4886#define SDE_TRANSB_CRC_ERR (1 << 4) 4887#define SDE_TRANSB_FIFO_UNDER (1 << 3) 4888#define SDE_TRANSA_CRC_DONE (1 << 2) 4889#define SDE_TRANSA_CRC_ERR (1 << 1) 4890#define SDE_TRANSA_FIFO_UNDER (1 << 0) 4891#define SDE_TRANS_MASK (0x3f) 4892 4893/* south display engine interrupt: CPT/PPT */ 4894#define SDE_AUDIO_POWER_D_CPT (1 << 31) 4895#define SDE_AUDIO_POWER_C_CPT (1 << 30) 4896#define SDE_AUDIO_POWER_B_CPT (1 << 29) 4897#define SDE_AUDIO_POWER_SHIFT_CPT 29 4898#define SDE_AUDIO_POWER_MASK_CPT (7 << 29) 4899#define SDE_AUXD_CPT (1 << 27) 4900#define SDE_AUXC_CPT (1 << 26) 4901#define SDE_AUXB_CPT (1 << 25) 4902#define SDE_AUX_MASK_CPT (7 << 25) 4903#define SDE_PORTD_HOTPLUG_CPT (1 << 23) 4904#define SDE_PORTC_HOTPLUG_CPT (1 << 22) 4905#define SDE_PORTB_HOTPLUG_CPT (1 << 21) 4906#define SDE_CRT_HOTPLUG_CPT (1 << 19) 4907#define SDE_SDVOB_HOTPLUG_CPT (1 << 18) 4908#define SDE_HOTPLUG_MASK_CPT (SDE_CRT_HOTPLUG_CPT | \ 4909 SDE_SDVOB_HOTPLUG_CPT | \ 4910 SDE_PORTD_HOTPLUG_CPT | \ 4911 SDE_PORTC_HOTPLUG_CPT | \ 4912 SDE_PORTB_HOTPLUG_CPT) 4913#define SDE_GMBUS_CPT (1 << 17) 4914#define SDE_ERROR_CPT (1 << 16) 4915#define SDE_AUDIO_CP_REQ_C_CPT (1 << 10) 4916#define SDE_AUDIO_CP_CHG_C_CPT (1 << 9) 4917#define SDE_FDI_RXC_CPT (1 << 8) 4918#define SDE_AUDIO_CP_REQ_B_CPT (1 << 6) 4919#define SDE_AUDIO_CP_CHG_B_CPT (1 << 5) 4920#define SDE_FDI_RXB_CPT (1 << 4) 4921#define SDE_AUDIO_CP_REQ_A_CPT (1 << 2) 4922#define SDE_AUDIO_CP_CHG_A_CPT (1 << 1) 4923#define SDE_FDI_RXA_CPT (1 << 0) 4924#define SDE_AUDIO_CP_REQ_CPT (SDE_AUDIO_CP_REQ_C_CPT | \ 4925 SDE_AUDIO_CP_REQ_B_CPT | \ 4926 SDE_AUDIO_CP_REQ_A_CPT) 4927#define SDE_AUDIO_CP_CHG_CPT (SDE_AUDIO_CP_CHG_C_CPT | \ 4928 SDE_AUDIO_CP_CHG_B_CPT | \ 4929 SDE_AUDIO_CP_CHG_A_CPT) 4930#define SDE_FDI_MASK_CPT (SDE_FDI_RXC_CPT | \ 4931 SDE_FDI_RXB_CPT | \ 4932 SDE_FDI_RXA_CPT) 4933 4934#define SDEISR 0xc4000 4935#define SDEIMR 0xc4004 4936#define SDEIIR 0xc4008 4937#define SDEIER 0xc400c 4938 4939#define SERR_INT 0xc4040 4940#define SERR_INT_POISON (1<<31) 4941#define SERR_INT_TRANS_C_FIFO_UNDERRUN (1<<6) 4942#define SERR_INT_TRANS_B_FIFO_UNDERRUN (1<<3) 4943#define SERR_INT_TRANS_A_FIFO_UNDERRUN (1<<0) 4944#define SERR_INT_TRANS_FIFO_UNDERRUN(pipe) (1<<(pipe*3)) 4945 4946/* digital port hotplug */ 4947#define PCH_PORT_HOTPLUG 0xc4030 /* SHOTPLUG_CTL */ 4948#define PORTD_HOTPLUG_ENABLE (1 << 20) 4949#define PORTD_PULSE_DURATION_2ms (0) 4950#define PORTD_PULSE_DURATION_4_5ms (1 << 18) 4951#define PORTD_PULSE_DURATION_6ms (2 << 18) 4952#define PORTD_PULSE_DURATION_100ms (3 << 18) 4953#define PORTD_PULSE_DURATION_MASK (3 << 18) 4954#define PORTD_HOTPLUG_STATUS_MASK (0x3 << 16) 4955#define PORTD_HOTPLUG_NO_DETECT (0 << 16) 4956#define PORTD_HOTPLUG_SHORT_DETECT (1 << 16) 4957#define PORTD_HOTPLUG_LONG_DETECT (2 << 16) 4958#define PORTC_HOTPLUG_ENABLE (1 << 12) 4959#define PORTC_PULSE_DURATION_2ms (0) 4960#define PORTC_PULSE_DURATION_4_5ms (1 << 10) 4961#define PORTC_PULSE_DURATION_6ms (2 << 10) 4962#define PORTC_PULSE_DURATION_100ms (3 << 10) 4963#define PORTC_PULSE_DURATION_MASK (3 << 10) 4964#define PORTC_HOTPLUG_STATUS_MASK (0x3 << 8) 4965#define PORTC_HOTPLUG_NO_DETECT (0 << 8) 4966#define PORTC_HOTPLUG_SHORT_DETECT (1 << 8) 4967#define PORTC_HOTPLUG_LONG_DETECT (2 << 8) 4968#define PORTB_HOTPLUG_ENABLE (1 << 4) 4969#define PORTB_PULSE_DURATION_2ms (0) 4970#define PORTB_PULSE_DURATION_4_5ms (1 << 2) 4971#define PORTB_PULSE_DURATION_6ms (2 << 2) 4972#define PORTB_PULSE_DURATION_100ms (3 << 2) 4973#define PORTB_PULSE_DURATION_MASK (3 << 2) 4974#define PORTB_HOTPLUG_STATUS_MASK (0x3 << 0) 4975#define PORTB_HOTPLUG_NO_DETECT (0 << 0) 4976#define PORTB_HOTPLUG_SHORT_DETECT (1 << 0) 4977#define PORTB_HOTPLUG_LONG_DETECT (2 << 0) 4978 4979#define PCH_GPIOA 0xc5010 4980#define PCH_GPIOB 0xc5014 4981#define PCH_GPIOC 0xc5018 4982#define PCH_GPIOD 0xc501c 4983#define PCH_GPIOE 0xc5020 4984#define PCH_GPIOF 0xc5024 4985 4986#define PCH_GMBUS0 0xc5100 4987#define PCH_GMBUS1 0xc5104 4988#define PCH_GMBUS2 0xc5108 4989#define PCH_GMBUS3 0xc510c 4990#define PCH_GMBUS4 0xc5110 4991#define PCH_GMBUS5 0xc5120 4992 4993#define _PCH_DPLL_A 0xc6014 4994#define _PCH_DPLL_B 0xc6018 4995#define PCH_DPLL(pll) (pll == 0 ? _PCH_DPLL_A : _PCH_DPLL_B) 4996 4997#define _PCH_FPA0 0xc6040 4998#define FP_CB_TUNE (0x3<<22) 4999#define _PCH_FPA1 0xc6044 5000#define _PCH_FPB0 0xc6048 5001#define _PCH_FPB1 0xc604c 5002#define PCH_FP0(pll) (pll == 0 ? _PCH_FPA0 : _PCH_FPB0) 5003#define PCH_FP1(pll) (pll == 0 ? _PCH_FPA1 : _PCH_FPB1) 5004 5005#define PCH_DPLL_TEST 0xc606c 5006 5007#define PCH_DREF_CONTROL 0xC6200 5008#define DREF_CONTROL_MASK 0x7fc3 5009#define DREF_CPU_SOURCE_OUTPUT_DISABLE (0<<13) 5010#define DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD (2<<13) 5011#define DREF_CPU_SOURCE_OUTPUT_NONSPREAD (3<<13) 5012#define DREF_CPU_SOURCE_OUTPUT_MASK (3<<13) 5013#define DREF_SSC_SOURCE_DISABLE (0<<11) 5014#define DREF_SSC_SOURCE_ENABLE (2<<11) 5015#define DREF_SSC_SOURCE_MASK (3<<11) 5016#define DREF_NONSPREAD_SOURCE_DISABLE (0<<9) 5017#define DREF_NONSPREAD_CK505_ENABLE (1<<9) 5018#define DREF_NONSPREAD_SOURCE_ENABLE (2<<9) 5019#define DREF_NONSPREAD_SOURCE_MASK (3<<9) 5020#define DREF_SUPERSPREAD_SOURCE_DISABLE (0<<7) 5021#define DREF_SUPERSPREAD_SOURCE_ENABLE (2<<7) 5022#define DREF_SUPERSPREAD_SOURCE_MASK (3<<7) 5023#define DREF_SSC4_DOWNSPREAD (0<<6) 5024#define DREF_SSC4_CENTERSPREAD (1<<6) 5025#define DREF_SSC1_DISABLE (0<<1) 5026#define DREF_SSC1_ENABLE (1<<1) 5027#define DREF_SSC4_DISABLE (0) 5028#define DREF_SSC4_ENABLE (1) 5029 5030#define PCH_RAWCLK_FREQ 0xc6204 5031#define FDL_TP1_TIMER_SHIFT 12 5032#define FDL_TP1_TIMER_MASK (3<<12) 5033#define FDL_TP2_TIMER_SHIFT 10 5034#define FDL_TP2_TIMER_MASK (3<<10) 5035#define RAWCLK_FREQ_MASK 0x3ff 5036 5037#define PCH_DPLL_TMR_CFG 0xc6208 5038 5039#define PCH_SSC4_PARMS 0xc6210 5040#define PCH_SSC4_AUX_PARMS 0xc6214 5041 5042#define PCH_DPLL_SEL 0xc7000 5043#define TRANS_DPLLB_SEL(pipe) (1 << (pipe * 4)) 5044#define TRANS_DPLLA_SEL(pipe) 0 5045#define TRANS_DPLL_ENABLE(pipe) (1 << (pipe * 4 + 3)) 5046 5047/* transcoder */ 5048 5049#define _PCH_TRANS_HTOTAL_A 0xe0000 5050#define TRANS_HTOTAL_SHIFT 16 5051#define TRANS_HACTIVE_SHIFT 0 5052#define _PCH_TRANS_HBLANK_A 0xe0004 5053#define TRANS_HBLANK_END_SHIFT 16 5054#define TRANS_HBLANK_START_SHIFT 0 5055#define _PCH_TRANS_HSYNC_A 0xe0008 5056#define TRANS_HSYNC_END_SHIFT 16 5057#define TRANS_HSYNC_START_SHIFT 0 5058#define _PCH_TRANS_VTOTAL_A 0xe000c 5059#define TRANS_VTOTAL_SHIFT 16 5060#define TRANS_VACTIVE_SHIFT 0 5061#define _PCH_TRANS_VBLANK_A 0xe0010 5062#define TRANS_VBLANK_END_SHIFT 16 5063#define TRANS_VBLANK_START_SHIFT 0 5064#define _PCH_TRANS_VSYNC_A 0xe0014 5065#define TRANS_VSYNC_END_SHIFT 16 5066#define TRANS_VSYNC_START_SHIFT 0 5067#define _PCH_TRANS_VSYNCSHIFT_A 0xe0028 5068 5069#define _PCH_TRANSA_DATA_M1 0xe0030 5070#define _PCH_TRANSA_DATA_N1 0xe0034 5071#define _PCH_TRANSA_DATA_M2 0xe0038 5072#define _PCH_TRANSA_DATA_N2 0xe003c 5073#define _PCH_TRANSA_LINK_M1 0xe0040 5074#define _PCH_TRANSA_LINK_N1 0xe0044 5075#define _PCH_TRANSA_LINK_M2 0xe0048 5076#define _PCH_TRANSA_LINK_N2 0xe004c 5077 5078/* Per-transcoder DIP controls (PCH) */ 5079#define _VIDEO_DIP_CTL_A 0xe0200 5080#define _VIDEO_DIP_DATA_A 0xe0208 5081#define _VIDEO_DIP_GCP_A 0xe0210 5082 5083#define _VIDEO_DIP_CTL_B 0xe1200 5084#define _VIDEO_DIP_DATA_B 0xe1208 5085#define _VIDEO_DIP_GCP_B 0xe1210 5086 5087#define TVIDEO_DIP_CTL(pipe) _PIPE(pipe, _VIDEO_DIP_CTL_A, _VIDEO_DIP_CTL_B) 5088#define TVIDEO_DIP_DATA(pipe) _PIPE(pipe, _VIDEO_DIP_DATA_A, _VIDEO_DIP_DATA_B) 5089#define TVIDEO_DIP_GCP(pipe) _PIPE(pipe, _VIDEO_DIP_GCP_A, _VIDEO_DIP_GCP_B) 5090 5091/* Per-transcoder DIP controls (VLV) */ 5092#define VLV_VIDEO_DIP_CTL_A (VLV_DISPLAY_BASE + 0x60200) 5093#define VLV_VIDEO_DIP_DATA_A (VLV_DISPLAY_BASE + 0x60208) 5094#define VLV_VIDEO_DIP_GDCP_PAYLOAD_A (VLV_DISPLAY_BASE + 0x60210) 5095 5096#define VLV_VIDEO_DIP_CTL_B (VLV_DISPLAY_BASE + 0x61170) 5097#define VLV_VIDEO_DIP_DATA_B (VLV_DISPLAY_BASE + 0x61174) 5098#define VLV_VIDEO_DIP_GDCP_PAYLOAD_B (VLV_DISPLAY_BASE + 0x61178) 5099 5100#define CHV_VIDEO_DIP_CTL_C (VLV_DISPLAY_BASE + 0x611f0) 5101#define CHV_VIDEO_DIP_DATA_C (VLV_DISPLAY_BASE + 0x611f4) 5102#define CHV_VIDEO_DIP_GDCP_PAYLOAD_C (VLV_DISPLAY_BASE + 0x611f8) 5103 5104#define VLV_TVIDEO_DIP_CTL(pipe) \ 5105 _PIPE3((pipe), VLV_VIDEO_DIP_CTL_A, \ 5106 VLV_VIDEO_DIP_CTL_B, CHV_VIDEO_DIP_CTL_C) 5107#define VLV_TVIDEO_DIP_DATA(pipe) \ 5108 _PIPE3((pipe), VLV_VIDEO_DIP_DATA_A, \ 5109 VLV_VIDEO_DIP_DATA_B, CHV_VIDEO_DIP_DATA_C) 5110#define VLV_TVIDEO_DIP_GCP(pipe) \ 5111 _PIPE3((pipe), VLV_VIDEO_DIP_GDCP_PAYLOAD_A, \ 5112 VLV_VIDEO_DIP_GDCP_PAYLOAD_B, CHV_VIDEO_DIP_GDCP_PAYLOAD_C) 5113 5114/* Haswell DIP controls */ 5115#define HSW_VIDEO_DIP_CTL_A 0x60200 5116#define HSW_VIDEO_DIP_AVI_DATA_A 0x60220 5117#define HSW_VIDEO_DIP_VS_DATA_A 0x60260 5118#define HSW_VIDEO_DIP_SPD_DATA_A 0x602A0 5119#define HSW_VIDEO_DIP_GMP_DATA_A 0x602E0 5120#define HSW_VIDEO_DIP_VSC_DATA_A 0x60320 5121#define HSW_VIDEO_DIP_AVI_ECC_A 0x60240 5122#define HSW_VIDEO_DIP_VS_ECC_A 0x60280 5123#define HSW_VIDEO_DIP_SPD_ECC_A 0x602C0 5124#define HSW_VIDEO_DIP_GMP_ECC_A 0x60300 5125#define HSW_VIDEO_DIP_VSC_ECC_A 0x60344 5126#define HSW_VIDEO_DIP_GCP_A 0x60210 5127 5128#define HSW_VIDEO_DIP_CTL_B 0x61200 5129#define HSW_VIDEO_DIP_AVI_DATA_B 0x61220 5130#define HSW_VIDEO_DIP_VS_DATA_B 0x61260 5131#define HSW_VIDEO_DIP_SPD_DATA_B 0x612A0 5132#define HSW_VIDEO_DIP_GMP_DATA_B 0x612E0 5133#define HSW_VIDEO_DIP_VSC_DATA_B 0x61320 5134#define HSW_VIDEO_DIP_BVI_ECC_B 0x61240 5135#define HSW_VIDEO_DIP_VS_ECC_B 0x61280 5136#define HSW_VIDEO_DIP_SPD_ECC_B 0x612C0 5137#define HSW_VIDEO_DIP_GMP_ECC_B 0x61300 5138#define HSW_VIDEO_DIP_VSC_ECC_B 0x61344 5139#define HSW_VIDEO_DIP_GCP_B 0x61210 5140 5141#define HSW_TVIDEO_DIP_CTL(trans) \ 5142 _TRANSCODER2(trans, HSW_VIDEO_DIP_CTL_A) 5143#define HSW_TVIDEO_DIP_AVI_DATA(trans) \ 5144 _TRANSCODER2(trans, HSW_VIDEO_DIP_AVI_DATA_A) 5145#define HSW_TVIDEO_DIP_VS_DATA(trans) \ 5146 _TRANSCODER2(trans, HSW_VIDEO_DIP_VS_DATA_A) 5147#define HSW_TVIDEO_DIP_SPD_DATA(trans) \ 5148 _TRANSCODER2(trans, HSW_VIDEO_DIP_SPD_DATA_A) 5149#define HSW_TVIDEO_DIP_GCP(trans) \ 5150 _TRANSCODER2(trans, HSW_VIDEO_DIP_GCP_A) 5151#define HSW_TVIDEO_DIP_VSC_DATA(trans) \ 5152 _TRANSCODER2(trans, HSW_VIDEO_DIP_VSC_DATA_A) 5153 5154#define HSW_STEREO_3D_CTL_A 0x70020 5155#define S3D_ENABLE (1<<31) 5156#define HSW_STEREO_3D_CTL_B 0x71020 5157 5158#define HSW_STEREO_3D_CTL(trans) \ 5159 _PIPE2(trans, HSW_STEREO_3D_CTL_A) 5160 5161#define _PCH_TRANS_HTOTAL_B 0xe1000 5162#define _PCH_TRANS_HBLANK_B 0xe1004 5163#define _PCH_TRANS_HSYNC_B 0xe1008 5164#define _PCH_TRANS_VTOTAL_B 0xe100c 5165#define _PCH_TRANS_VBLANK_B 0xe1010 5166#define _PCH_TRANS_VSYNC_B 0xe1014 5167#define _PCH_TRANS_VSYNCSHIFT_B 0xe1028 5168 5169#define PCH_TRANS_HTOTAL(pipe) _PIPE(pipe, _PCH_TRANS_HTOTAL_A, _PCH_TRANS_HTOTAL_B) 5170#define PCH_TRANS_HBLANK(pipe) _PIPE(pipe, _PCH_TRANS_HBLANK_A, _PCH_TRANS_HBLANK_B) 5171#define PCH_TRANS_HSYNC(pipe) _PIPE(pipe, _PCH_TRANS_HSYNC_A, _PCH_TRANS_HSYNC_B) 5172#define PCH_TRANS_VTOTAL(pipe) _PIPE(pipe, _PCH_TRANS_VTOTAL_A, _PCH_TRANS_VTOTAL_B) 5173#define PCH_TRANS_VBLANK(pipe) _PIPE(pipe, _PCH_TRANS_VBLANK_A, _PCH_TRANS_VBLANK_B) 5174#define PCH_TRANS_VSYNC(pipe) _PIPE(pipe, _PCH_TRANS_VSYNC_A, _PCH_TRANS_VSYNC_B) 5175#define PCH_TRANS_VSYNCSHIFT(pipe) _PIPE(pipe, _PCH_TRANS_VSYNCSHIFT_A, \ 5176 _PCH_TRANS_VSYNCSHIFT_B) 5177 5178#define _PCH_TRANSB_DATA_M1 0xe1030 5179#define _PCH_TRANSB_DATA_N1 0xe1034 5180#define _PCH_TRANSB_DATA_M2 0xe1038 5181#define _PCH_TRANSB_DATA_N2 0xe103c 5182#define _PCH_TRANSB_LINK_M1 0xe1040 5183#define _PCH_TRANSB_LINK_N1 0xe1044 5184#define _PCH_TRANSB_LINK_M2 0xe1048 5185#define _PCH_TRANSB_LINK_N2 0xe104c 5186 5187#define PCH_TRANS_DATA_M1(pipe) _PIPE(pipe, _PCH_TRANSA_DATA_M1, _PCH_TRANSB_DATA_M1) 5188#define PCH_TRANS_DATA_N1(pipe) _PIPE(pipe, _PCH_TRANSA_DATA_N1, _PCH_TRANSB_DATA_N1) 5189#define PCH_TRANS_DATA_M2(pipe) _PIPE(pipe, _PCH_TRANSA_DATA_M2, _PCH_TRANSB_DATA_M2) 5190#define PCH_TRANS_DATA_N2(pipe) _PIPE(pipe, _PCH_TRANSA_DATA_N2, _PCH_TRANSB_DATA_N2) 5191#define PCH_TRANS_LINK_M1(pipe) _PIPE(pipe, _PCH_TRANSA_LINK_M1, _PCH_TRANSB_LINK_M1) 5192#define PCH_TRANS_LINK_N1(pipe) _PIPE(pipe, _PCH_TRANSA_LINK_N1, _PCH_TRANSB_LINK_N1) 5193#define PCH_TRANS_LINK_M2(pipe) _PIPE(pipe, _PCH_TRANSA_LINK_M2, _PCH_TRANSB_LINK_M2) 5194#define PCH_TRANS_LINK_N2(pipe) _PIPE(pipe, _PCH_TRANSA_LINK_N2, _PCH_TRANSB_LINK_N2) 5195 5196#define _PCH_TRANSACONF 0xf0008 5197#define _PCH_TRANSBCONF 0xf1008 5198#define PCH_TRANSCONF(pipe) _PIPE(pipe, _PCH_TRANSACONF, _PCH_TRANSBCONF) 5199#define LPT_TRANSCONF _PCH_TRANSACONF /* lpt has only one transcoder */ 5200#define TRANS_DISABLE (0<<31) 5201#define TRANS_ENABLE (1<<31) 5202#define TRANS_STATE_MASK (1<<30) 5203#define TRANS_STATE_DISABLE (0<<30) 5204#define TRANS_STATE_ENABLE (1<<30) 5205#define TRANS_FSYNC_DELAY_HB1 (0<<27) 5206#define TRANS_FSYNC_DELAY_HB2 (1<<27) 5207#define TRANS_FSYNC_DELAY_HB3 (2<<27) 5208#define TRANS_FSYNC_DELAY_HB4 (3<<27) 5209#define TRANS_INTERLACE_MASK (7<<21) 5210#define TRANS_PROGRESSIVE (0<<21) 5211#define TRANS_INTERLACED (3<<21) 5212#define TRANS_LEGACY_INTERLACED_ILK (2<<21) 5213#define TRANS_8BPC (0<<5) 5214#define TRANS_10BPC (1<<5) 5215#define TRANS_6BPC (2<<5) 5216#define TRANS_12BPC (3<<5) 5217 5218#define _TRANSA_CHICKEN1 0xf0060 5219#define _TRANSB_CHICKEN1 0xf1060 5220#define TRANS_CHICKEN1(pipe) _PIPE(pipe, _TRANSA_CHICKEN1, _TRANSB_CHICKEN1) 5221#define TRANS_CHICKEN1_DP0UNIT_GC_DISABLE (1<<4) 5222#define _TRANSA_CHICKEN2 0xf0064 5223#define _TRANSB_CHICKEN2 0xf1064 5224#define TRANS_CHICKEN2(pipe) _PIPE(pipe, _TRANSA_CHICKEN2, _TRANSB_CHICKEN2) 5225#define TRANS_CHICKEN2_TIMING_OVERRIDE (1<<31) 5226#define TRANS_CHICKEN2_FDI_POLARITY_REVERSED (1<<29) 5227#define TRANS_CHICKEN2_FRAME_START_DELAY_MASK (3<<27) 5228#define TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER (1<<26) 5229#define TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH (1<<25) 5230 5231#define SOUTH_CHICKEN1 0xc2000 5232#define FDIA_PHASE_SYNC_SHIFT_OVR 19 5233#define FDIA_PHASE_SYNC_SHIFT_EN 18 5234#define FDI_PHASE_SYNC_OVR(pipe) (1<<(FDIA_PHASE_SYNC_SHIFT_OVR - ((pipe) * 2))) 5235#define FDI_PHASE_SYNC_EN(pipe) (1<<(FDIA_PHASE_SYNC_SHIFT_EN - ((pipe) * 2))) 5236#define FDI_BC_BIFURCATION_SELECT (1 << 12) 5237#define SOUTH_CHICKEN2 0xc2004 5238#define FDI_MPHY_IOSFSB_RESET_STATUS (1<<13) 5239#define FDI_MPHY_IOSFSB_RESET_CTL (1<<12) 5240#define DPLS_EDP_PPS_FIX_DIS (1<<0) 5241 5242#define _FDI_RXA_CHICKEN 0xc200c 5243#define _FDI_RXB_CHICKEN 0xc2010 5244#define FDI_RX_PHASE_SYNC_POINTER_OVR (1<<1) 5245#define FDI_RX_PHASE_SYNC_POINTER_EN (1<<0) 5246#define FDI_RX_CHICKEN(pipe) _PIPE(pipe, _FDI_RXA_CHICKEN, _FDI_RXB_CHICKEN) 5247 5248#define SOUTH_DSPCLK_GATE_D 0xc2020 5249#define PCH_DPLUNIT_CLOCK_GATE_DISABLE (1<<30) 5250#define PCH_DPLSUNIT_CLOCK_GATE_DISABLE (1<<29) 5251#define PCH_CPUNIT_CLOCK_GATE_DISABLE (1<<14) 5252#define PCH_LP_PARTITION_LEVEL_DISABLE (1<<12) 5253 5254/* CPU: FDI_TX */ 5255#define _FDI_TXA_CTL 0x60100 5256#define _FDI_TXB_CTL 0x61100 5257#define FDI_TX_CTL(pipe) _PIPE(pipe, _FDI_TXA_CTL, _FDI_TXB_CTL) 5258#define FDI_TX_DISABLE (0<<31) 5259#define FDI_TX_ENABLE (1<<31) 5260#define FDI_LINK_TRAIN_PATTERN_1 (0<<28) 5261#define FDI_LINK_TRAIN_PATTERN_2 (1<<28) 5262#define FDI_LINK_TRAIN_PATTERN_IDLE (2<<28) 5263#define FDI_LINK_TRAIN_NONE (3<<28) 5264#define FDI_LINK_TRAIN_VOLTAGE_0_4V (0<<25) 5265#define FDI_LINK_TRAIN_VOLTAGE_0_6V (1<<25) 5266#define FDI_LINK_TRAIN_VOLTAGE_0_8V (2<<25) 5267#define FDI_LINK_TRAIN_VOLTAGE_1_2V (3<<25) 5268#define FDI_LINK_TRAIN_PRE_EMPHASIS_NONE (0<<22) 5269#define FDI_LINK_TRAIN_PRE_EMPHASIS_1_5X (1<<22) 5270#define FDI_LINK_TRAIN_PRE_EMPHASIS_2X (2<<22) 5271#define FDI_LINK_TRAIN_PRE_EMPHASIS_3X (3<<22) 5272/* ILK always use 400mV 0dB for voltage swing and pre-emphasis level. 5273 SNB has different settings. */ 5274/* SNB A-stepping */ 5275#define FDI_LINK_TRAIN_400MV_0DB_SNB_A (0x38<<22) 5276#define FDI_LINK_TRAIN_400MV_6DB_SNB_A (0x02<<22) 5277#define FDI_LINK_TRAIN_600MV_3_5DB_SNB_A (0x01<<22) 5278#define FDI_LINK_TRAIN_800MV_0DB_SNB_A (0x0<<22) 5279/* SNB B-stepping */ 5280#define FDI_LINK_TRAIN_400MV_0DB_SNB_B (0x0<<22) 5281#define FDI_LINK_TRAIN_400MV_6DB_SNB_B (0x3a<<22) 5282#define FDI_LINK_TRAIN_600MV_3_5DB_SNB_B (0x39<<22) 5283#define FDI_LINK_TRAIN_800MV_0DB_SNB_B (0x38<<22) 5284#define FDI_LINK_TRAIN_VOL_EMP_MASK (0x3f<<22) 5285#define FDI_DP_PORT_WIDTH_SHIFT 19 5286#define FDI_DP_PORT_WIDTH_MASK (7 << FDI_DP_PORT_WIDTH_SHIFT) 5287#define FDI_DP_PORT_WIDTH(width) (((width) - 1) << FDI_DP_PORT_WIDTH_SHIFT) 5288#define FDI_TX_ENHANCE_FRAME_ENABLE (1<<18) 5289/* Ironlake: hardwired to 1 */ 5290#define FDI_TX_PLL_ENABLE (1<<14) 5291 5292/* Ivybridge has different bits for lolz */ 5293#define FDI_LINK_TRAIN_PATTERN_1_IVB (0<<8) 5294#define FDI_LINK_TRAIN_PATTERN_2_IVB (1<<8) 5295#define FDI_LINK_TRAIN_PATTERN_IDLE_IVB (2<<8) 5296#define FDI_LINK_TRAIN_NONE_IVB (3<<8) 5297 5298/* both Tx and Rx */ 5299#define FDI_COMPOSITE_SYNC (1<<11) 5300#define FDI_LINK_TRAIN_AUTO (1<<10) 5301#define FDI_SCRAMBLING_ENABLE (0<<7) 5302#define FDI_SCRAMBLING_DISABLE (1<<7) 5303 5304/* FDI_RX, FDI_X is hard-wired to Transcoder_X */ 5305#define _FDI_RXA_CTL 0xf000c 5306#define _FDI_RXB_CTL 0xf100c 5307#define FDI_RX_CTL(pipe) _PIPE(pipe, _FDI_RXA_CTL, _FDI_RXB_CTL) 5308#define FDI_RX_ENABLE (1<<31) 5309/* train, dp width same as FDI_TX */ 5310#define FDI_FS_ERRC_ENABLE (1<<27) 5311#define FDI_FE_ERRC_ENABLE (1<<26) 5312#define FDI_RX_POLARITY_REVERSED_LPT (1<<16) 5313#define FDI_8BPC (0<<16) 5314#define FDI_10BPC (1<<16) 5315#define FDI_6BPC (2<<16) 5316#define FDI_12BPC (3<<16) 5317#define FDI_RX_LINK_REVERSAL_OVERRIDE (1<<15) 5318#define FDI_DMI_LINK_REVERSE_MASK (1<<14) 5319#define FDI_RX_PLL_ENABLE (1<<13) 5320#define FDI_FS_ERR_CORRECT_ENABLE (1<<11) 5321#define FDI_FE_ERR_CORRECT_ENABLE (1<<10) 5322#define FDI_FS_ERR_REPORT_ENABLE (1<<9) 5323#define FDI_FE_ERR_REPORT_ENABLE (1<<8) 5324#define FDI_RX_ENHANCE_FRAME_ENABLE (1<<6) 5325#define FDI_PCDCLK (1<<4) 5326/* CPT */ 5327#define FDI_AUTO_TRAINING (1<<10) 5328#define FDI_LINK_TRAIN_PATTERN_1_CPT (0<<8) 5329#define FDI_LINK_TRAIN_PATTERN_2_CPT (1<<8) 5330#define FDI_LINK_TRAIN_PATTERN_IDLE_CPT (2<<8) 5331#define FDI_LINK_TRAIN_NORMAL_CPT (3<<8) 5332#define FDI_LINK_TRAIN_PATTERN_MASK_CPT (3<<8) 5333 5334#define _FDI_RXA_MISC 0xf0010 5335#define _FDI_RXB_MISC 0xf1010 5336#define FDI_RX_PWRDN_LANE1_MASK (3<<26) 5337#define FDI_RX_PWRDN_LANE1_VAL(x) ((x)<<26) 5338#define FDI_RX_PWRDN_LANE0_MASK (3<<24) 5339#define FDI_RX_PWRDN_LANE0_VAL(x) ((x)<<24) 5340#define FDI_RX_TP1_TO_TP2_48 (2<<20) 5341#define FDI_RX_TP1_TO_TP2_64 (3<<20) 5342#define FDI_RX_FDI_DELAY_90 (0x90<<0) 5343#define FDI_RX_MISC(pipe) _PIPE(pipe, _FDI_RXA_MISC, _FDI_RXB_MISC) 5344 5345#define _FDI_RXA_TUSIZE1 0xf0030 5346#define _FDI_RXA_TUSIZE2 0xf0038 5347#define _FDI_RXB_TUSIZE1 0xf1030 5348#define _FDI_RXB_TUSIZE2 0xf1038 5349#define FDI_RX_TUSIZE1(pipe) _PIPE(pipe, _FDI_RXA_TUSIZE1, _FDI_RXB_TUSIZE1) 5350#define FDI_RX_TUSIZE2(pipe) _PIPE(pipe, _FDI_RXA_TUSIZE2, _FDI_RXB_TUSIZE2) 5351 5352/* FDI_RX interrupt register format */ 5353#define FDI_RX_INTER_LANE_ALIGN (1<<10) 5354#define FDI_RX_SYMBOL_LOCK (1<<9) /* train 2 */ 5355#define FDI_RX_BIT_LOCK (1<<8) /* train 1 */ 5356#define FDI_RX_TRAIN_PATTERN_2_FAIL (1<<7) 5357#define FDI_RX_FS_CODE_ERR (1<<6) 5358#define FDI_RX_FE_CODE_ERR (1<<5) 5359#define FDI_RX_SYMBOL_ERR_RATE_ABOVE (1<<4) 5360#define FDI_RX_HDCP_LINK_FAIL (1<<3) 5361#define FDI_RX_PIXEL_FIFO_OVERFLOW (1<<2) 5362#define FDI_RX_CROSS_CLOCK_OVERFLOW (1<<1) 5363#define FDI_RX_SYMBOL_QUEUE_OVERFLOW (1<<0) 5364 5365#define _FDI_RXA_IIR 0xf0014 5366#define _FDI_RXA_IMR 0xf0018 5367#define _FDI_RXB_IIR 0xf1014 5368#define _FDI_RXB_IMR 0xf1018 5369#define FDI_RX_IIR(pipe) _PIPE(pipe, _FDI_RXA_IIR, _FDI_RXB_IIR) 5370#define FDI_RX_IMR(pipe) _PIPE(pipe, _FDI_RXA_IMR, _FDI_RXB_IMR) 5371 5372#define FDI_PLL_CTL_1 0xfe000 5373#define FDI_PLL_CTL_2 0xfe004 5374 5375#define PCH_LVDS 0xe1180 5376#define LVDS_DETECTED (1 << 1) 5377 5378/* vlv has 2 sets of panel control regs. */ 5379#define PIPEA_PP_STATUS (VLV_DISPLAY_BASE + 0x61200) 5380#define PIPEA_PP_CONTROL (VLV_DISPLAY_BASE + 0x61204) 5381#define PIPEA_PP_ON_DELAYS (VLV_DISPLAY_BASE + 0x61208) 5382#define PANEL_PORT_SELECT_VLV(port) ((port) << 30) 5383#define PIPEA_PP_OFF_DELAYS (VLV_DISPLAY_BASE + 0x6120c) 5384#define PIPEA_PP_DIVISOR (VLV_DISPLAY_BASE + 0x61210) 5385 5386#define PIPEB_PP_STATUS (VLV_DISPLAY_BASE + 0x61300) 5387#define PIPEB_PP_CONTROL (VLV_DISPLAY_BASE + 0x61304) 5388#define PIPEB_PP_ON_DELAYS (VLV_DISPLAY_BASE + 0x61308) 5389#define PIPEB_PP_OFF_DELAYS (VLV_DISPLAY_BASE + 0x6130c) 5390#define PIPEB_PP_DIVISOR (VLV_DISPLAY_BASE + 0x61310) 5391 5392#define VLV_PIPE_PP_STATUS(pipe) _PIPE(pipe, PIPEA_PP_STATUS, PIPEB_PP_STATUS) 5393#define VLV_PIPE_PP_CONTROL(pipe) _PIPE(pipe, PIPEA_PP_CONTROL, PIPEB_PP_CONTROL) 5394#define VLV_PIPE_PP_ON_DELAYS(pipe) \ 5395 _PIPE(pipe, PIPEA_PP_ON_DELAYS, PIPEB_PP_ON_DELAYS) 5396#define VLV_PIPE_PP_OFF_DELAYS(pipe) \ 5397 _PIPE(pipe, PIPEA_PP_OFF_DELAYS, PIPEB_PP_OFF_DELAYS) 5398#define VLV_PIPE_PP_DIVISOR(pipe) \ 5399 _PIPE(pipe, PIPEA_PP_DIVISOR, PIPEB_PP_DIVISOR) 5400 5401#define PCH_PP_STATUS 0xc7200 5402#define PCH_PP_CONTROL 0xc7204 5403#define PANEL_UNLOCK_REGS (0xabcd << 16) 5404#define PANEL_UNLOCK_MASK (0xffff << 16) 5405#define EDP_FORCE_VDD (1 << 3) 5406#define EDP_BLC_ENABLE (1 << 2) 5407#define PANEL_POWER_RESET (1 << 1) 5408#define PANEL_POWER_OFF (0 << 0) 5409#define PANEL_POWER_ON (1 << 0) 5410#define PCH_PP_ON_DELAYS 0xc7208 5411#define PANEL_PORT_SELECT_MASK (3 << 30) 5412#define PANEL_PORT_SELECT_LVDS (0 << 30) 5413#define PANEL_PORT_SELECT_DPA (1 << 30) 5414#define PANEL_PORT_SELECT_DPC (2 << 30) 5415#define PANEL_PORT_SELECT_DPD (3 << 30) 5416#define PANEL_POWER_UP_DELAY_MASK (0x1fff0000) 5417#define PANEL_POWER_UP_DELAY_SHIFT 16 5418#define PANEL_LIGHT_ON_DELAY_MASK (0x1fff) 5419#define PANEL_LIGHT_ON_DELAY_SHIFT 0 5420 5421#define PCH_PP_OFF_DELAYS 0xc720c 5422#define PANEL_POWER_DOWN_DELAY_MASK (0x1fff0000) 5423#define PANEL_POWER_DOWN_DELAY_SHIFT 16 5424#define PANEL_LIGHT_OFF_DELAY_MASK (0x1fff) 5425#define PANEL_LIGHT_OFF_DELAY_SHIFT 0 5426 5427#define PCH_PP_DIVISOR 0xc7210 5428#define PP_REFERENCE_DIVIDER_MASK (0xffffff00) 5429#define PP_REFERENCE_DIVIDER_SHIFT 8 5430#define PANEL_POWER_CYCLE_DELAY_MASK (0x1f) 5431#define PANEL_POWER_CYCLE_DELAY_SHIFT 0 5432 5433#define PCH_DP_B 0xe4100 5434#define PCH_DPB_AUX_CH_CTL 0xe4110 5435#define PCH_DPB_AUX_CH_DATA1 0xe4114 5436#define PCH_DPB_AUX_CH_DATA2 0xe4118 5437#define PCH_DPB_AUX_CH_DATA3 0xe411c 5438#define PCH_DPB_AUX_CH_DATA4 0xe4120 5439#define PCH_DPB_AUX_CH_DATA5 0xe4124 5440 5441#define PCH_DP_C 0xe4200 5442#define PCH_DPC_AUX_CH_CTL 0xe4210 5443#define PCH_DPC_AUX_CH_DATA1 0xe4214 5444#define PCH_DPC_AUX_CH_DATA2 0xe4218 5445#define PCH_DPC_AUX_CH_DATA3 0xe421c 5446#define PCH_DPC_AUX_CH_DATA4 0xe4220 5447#define PCH_DPC_AUX_CH_DATA5 0xe4224 5448 5449#define PCH_DP_D 0xe4300 5450#define PCH_DPD_AUX_CH_CTL 0xe4310 5451#define PCH_DPD_AUX_CH_DATA1 0xe4314 5452#define PCH_DPD_AUX_CH_DATA2 0xe4318 5453#define PCH_DPD_AUX_CH_DATA3 0xe431c 5454#define PCH_DPD_AUX_CH_DATA4 0xe4320 5455#define PCH_DPD_AUX_CH_DATA5 0xe4324 5456 5457/* CPT */ 5458#define PORT_TRANS_A_SEL_CPT 0 5459#define PORT_TRANS_B_SEL_CPT (1<<29) 5460#define PORT_TRANS_C_SEL_CPT (2<<29) 5461#define PORT_TRANS_SEL_MASK (3<<29) 5462#define PORT_TRANS_SEL_CPT(pipe) ((pipe) << 29) 5463#define PORT_TO_PIPE(val) (((val) & (1<<30)) >> 30) 5464#define PORT_TO_PIPE_CPT(val) (((val) & PORT_TRANS_SEL_MASK) >> 29) 5465#define SDVO_PORT_TO_PIPE_CHV(val) (((val) & (3<<24)) >> 24) 5466#define DP_PORT_TO_PIPE_CHV(val) (((val) & (3<<16)) >> 16) 5467 5468#define TRANS_DP_CTL_A 0xe0300 5469#define TRANS_DP_CTL_B 0xe1300 5470#define TRANS_DP_CTL_C 0xe2300 5471#define TRANS_DP_CTL(pipe) _PIPE(pipe, TRANS_DP_CTL_A, TRANS_DP_CTL_B) 5472#define TRANS_DP_OUTPUT_ENABLE (1<<31) 5473#define TRANS_DP_PORT_SEL_B (0<<29) 5474#define TRANS_DP_PORT_SEL_C (1<<29) 5475#define TRANS_DP_PORT_SEL_D (2<<29) 5476#define TRANS_DP_PORT_SEL_NONE (3<<29) 5477#define TRANS_DP_PORT_SEL_MASK (3<<29) 5478#define TRANS_DP_AUDIO_ONLY (1<<26) 5479#define TRANS_DP_ENH_FRAMING (1<<18) 5480#define TRANS_DP_8BPC (0<<9) 5481#define TRANS_DP_10BPC (1<<9) 5482#define TRANS_DP_6BPC (2<<9) 5483#define TRANS_DP_12BPC (3<<9) 5484#define TRANS_DP_BPC_MASK (3<<9) 5485#define TRANS_DP_VSYNC_ACTIVE_HIGH (1<<4) 5486#define TRANS_DP_VSYNC_ACTIVE_LOW 0 5487#define TRANS_DP_HSYNC_ACTIVE_HIGH (1<<3) 5488#define TRANS_DP_HSYNC_ACTIVE_LOW 0 5489#define TRANS_DP_SYNC_MASK (3<<3) 5490 5491/* SNB eDP training params */ 5492/* SNB A-stepping */ 5493#define EDP_LINK_TRAIN_400MV_0DB_SNB_A (0x38<<22) 5494#define EDP_LINK_TRAIN_400MV_6DB_SNB_A (0x02<<22) 5495#define EDP_LINK_TRAIN_600MV_3_5DB_SNB_A (0x01<<22) 5496#define EDP_LINK_TRAIN_800MV_0DB_SNB_A (0x0<<22) 5497/* SNB B-stepping */ 5498#define EDP_LINK_TRAIN_400_600MV_0DB_SNB_B (0x0<<22) 5499#define EDP_LINK_TRAIN_400MV_3_5DB_SNB_B (0x1<<22) 5500#define EDP_LINK_TRAIN_400_600MV_6DB_SNB_B (0x3a<<22) 5501#define EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B (0x39<<22) 5502#define EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B (0x38<<22) 5503#define EDP_LINK_TRAIN_VOL_EMP_MASK_SNB (0x3f<<22) 5504 5505/* IVB */ 5506#define EDP_LINK_TRAIN_400MV_0DB_IVB (0x24 <<22) 5507#define EDP_LINK_TRAIN_400MV_3_5DB_IVB (0x2a <<22) 5508#define EDP_LINK_TRAIN_400MV_6DB_IVB (0x2f <<22) 5509#define EDP_LINK_TRAIN_600MV_0DB_IVB (0x30 <<22) 5510#define EDP_LINK_TRAIN_600MV_3_5DB_IVB (0x36 <<22) 5511#define EDP_LINK_TRAIN_800MV_0DB_IVB (0x38 <<22) 5512#define EDP_LINK_TRAIN_800MV_3_5DB_IVB (0x3e <<22) 5513 5514/* legacy values */ 5515#define EDP_LINK_TRAIN_500MV_0DB_IVB (0x00 <<22) 5516#define EDP_LINK_TRAIN_1000MV_0DB_IVB (0x20 <<22) 5517#define EDP_LINK_TRAIN_500MV_3_5DB_IVB (0x02 <<22) 5518#define EDP_LINK_TRAIN_1000MV_3_5DB_IVB (0x22 <<22) 5519#define EDP_LINK_TRAIN_1000MV_6DB_IVB (0x23 <<22) 5520 5521#define EDP_LINK_TRAIN_VOL_EMP_MASK_IVB (0x3f<<22) 5522 5523#define VLV_PMWGICZ 0x1300a4 5524 5525#define FORCEWAKE 0xA18C 5526#define FORCEWAKE_VLV 0x1300b0 5527#define FORCEWAKE_ACK_VLV 0x1300b4 5528#define FORCEWAKE_MEDIA_VLV 0x1300b8 5529#define FORCEWAKE_ACK_MEDIA_VLV 0x1300bc 5530#define FORCEWAKE_ACK_HSW 0x130044 5531#define FORCEWAKE_ACK 0x130090 5532#define VLV_GTLC_WAKE_CTRL 0x130090 5533#define VLV_GTLC_RENDER_CTX_EXISTS (1 << 25) 5534#define VLV_GTLC_MEDIA_CTX_EXISTS (1 << 24) 5535#define VLV_GTLC_ALLOWWAKEREQ (1 << 0) 5536 5537#define VLV_GTLC_PW_STATUS 0x130094 5538#define VLV_GTLC_ALLOWWAKEACK (1 << 0) 5539#define VLV_GTLC_ALLOWWAKEERR (1 << 1) 5540#define VLV_GTLC_PW_MEDIA_STATUS_MASK (1 << 5) 5541#define VLV_GTLC_PW_RENDER_STATUS_MASK (1 << 7) 5542#define FORCEWAKE_MT 0xa188 /* multi-threaded */ 5543#define FORCEWAKE_KERNEL 0x1 5544#define FORCEWAKE_USER 0x2 5545#define FORCEWAKE_MT_ACK 0x130040 5546#define ECOBUS 0xa180 5547#define FORCEWAKE_MT_ENABLE (1<<5) 5548#define VLV_SPAREG2H 0xA194 5549 5550#define GTFIFODBG 0x120000 5551#define GT_FIFO_SBDROPERR (1<<6) 5552#define GT_FIFO_BLOBDROPERR (1<<5) 5553#define GT_FIFO_SB_READ_ABORTERR (1<<4) 5554#define GT_FIFO_DROPERR (1<<3) 5555#define GT_FIFO_OVFERR (1<<2) 5556#define GT_FIFO_IAWRERR (1<<1) 5557#define GT_FIFO_IARDERR (1<<0) 5558 5559#define GTFIFOCTL 0x120008 5560#define GT_FIFO_FREE_ENTRIES_MASK 0x7f 5561#define GT_FIFO_NUM_RESERVED_ENTRIES 20 5562 5563#define HSW_IDICR 0x9008 5564#define IDIHASHMSK(x) (((x) & 0x3f) << 16) 5565#define HSW_EDRAM_PRESENT 0x120010 5566 5567#define GEN6_UCGCTL1 0x9400 5568# define GEN6_EU_TCUNIT_CLOCK_GATE_DISABLE (1 << 16) 5569# define GEN6_BLBUNIT_CLOCK_GATE_DISABLE (1 << 5) 5570# define GEN6_CSUNIT_CLOCK_GATE_DISABLE (1 << 7) 5571 5572#define GEN6_UCGCTL2 0x9404 5573# define GEN7_VDSUNIT_CLOCK_GATE_DISABLE (1 << 30) 5574# define GEN7_TDLUNIT_CLOCK_GATE_DISABLE (1 << 22) 5575# define GEN6_RCZUNIT_CLOCK_GATE_DISABLE (1 << 13) 5576# define GEN6_RCPBUNIT_CLOCK_GATE_DISABLE (1 << 12) 5577# define GEN6_RCCUNIT_CLOCK_GATE_DISABLE (1 << 11) 5578 5579#define GEN6_UCGCTL3 0x9408 5580 5581#define GEN7_UCGCTL4 0x940c 5582#define GEN7_L3BANK2X_CLOCK_GATE_DISABLE (1<<25) 5583 5584#define GEN6_RCGCTL1 0x9410 5585#define GEN6_RCGCTL2 0x9414 5586#define GEN6_RSTCTL 0x9420 5587 5588#define GEN8_UCGCTL6 0x9430 5589#define GEN8_SDEUNIT_CLOCK_GATE_DISABLE (1<<14) 5590 5591#define GEN6_GFXPAUSE 0xA000 5592#define GEN6_RPNSWREQ 0xA008 5593#define GEN6_TURBO_DISABLE (1<<31) 5594#define GEN6_FREQUENCY(x) ((x)<<25) 5595#define HSW_FREQUENCY(x) ((x)<<24) 5596#define GEN6_OFFSET(x) ((x)<<19) 5597#define GEN6_AGGRESSIVE_TURBO (0<<15) 5598#define GEN6_RC_VIDEO_FREQ 0xA00C 5599#define GEN6_RC_CONTROL 0xA090 5600#define GEN6_RC_CTL_RC6pp_ENABLE (1<<16) 5601#define GEN6_RC_CTL_RC6p_ENABLE (1<<17) 5602#define GEN6_RC_CTL_RC6_ENABLE (1<<18) 5603#define GEN6_RC_CTL_RC1e_ENABLE (1<<20) 5604#define GEN6_RC_CTL_RC7_ENABLE (1<<22) 5605#define VLV_RC_CTL_CTX_RST_PARALLEL (1<<24) 5606#define GEN7_RC_CTL_TO_MODE (1<<28) 5607#define GEN6_RC_CTL_EI_MODE(x) ((x)<<27) 5608#define GEN6_RC_CTL_HW_ENABLE (1<<31) 5609#define GEN6_RP_DOWN_TIMEOUT 0xA010 5610#define GEN6_RP_INTERRUPT_LIMITS 0xA014 5611#define GEN6_RPSTAT1 0xA01C 5612#define GEN6_CAGF_SHIFT 8 5613#define HSW_CAGF_SHIFT 7 5614#define GEN6_CAGF_MASK (0x7f << GEN6_CAGF_SHIFT) 5615#define HSW_CAGF_MASK (0x7f << HSW_CAGF_SHIFT) 5616#define GEN6_RP_CONTROL 0xA024 5617#define GEN6_RP_MEDIA_TURBO (1<<11) 5618#define GEN6_RP_MEDIA_MODE_MASK (3<<9) 5619#define GEN6_RP_MEDIA_HW_TURBO_MODE (3<<9) 5620#define GEN6_RP_MEDIA_HW_NORMAL_MODE (2<<9) 5621#define GEN6_RP_MEDIA_HW_MODE (1<<9) 5622#define GEN6_RP_MEDIA_SW_MODE (0<<9) 5623#define GEN6_RP_MEDIA_IS_GFX (1<<8) 5624#define GEN6_RP_ENABLE (1<<7) 5625#define GEN6_RP_UP_IDLE_MIN (0x1<<3) 5626#define GEN6_RP_UP_BUSY_AVG (0x2<<3) 5627#define GEN6_RP_UP_BUSY_CONT (0x4<<3) 5628#define GEN6_RP_DOWN_IDLE_AVG (0x2<<0) 5629#define GEN6_RP_DOWN_IDLE_CONT (0x1<<0) 5630#define GEN6_RP_UP_THRESHOLD 0xA02C 5631#define GEN6_RP_DOWN_THRESHOLD 0xA030 5632#define GEN6_RP_CUR_UP_EI 0xA050 5633#define GEN6_CURICONT_MASK 0xffffff 5634#define GEN6_RP_CUR_UP 0xA054 5635#define GEN6_CURBSYTAVG_MASK 0xffffff 5636#define GEN6_RP_PREV_UP 0xA058 5637#define GEN6_RP_CUR_DOWN_EI 0xA05C 5638#define GEN6_CURIAVG_MASK 0xffffff 5639#define GEN6_RP_CUR_DOWN 0xA060 5640#define GEN6_RP_PREV_DOWN 0xA064 5641#define GEN6_RP_UP_EI 0xA068 5642#define GEN6_RP_DOWN_EI 0xA06C 5643#define GEN6_RP_IDLE_HYSTERSIS 0xA070 5644#define GEN6_RPDEUHWTC 0xA080 5645#define GEN6_RPDEUC 0xA084 5646#define GEN6_RPDEUCSW 0xA088 5647#define GEN6_RC_STATE 0xA094 5648#define GEN6_RC1_WAKE_RATE_LIMIT 0xA098 5649#define GEN6_RC6_WAKE_RATE_LIMIT 0xA09C 5650#define GEN6_RC6pp_WAKE_RATE_LIMIT 0xA0A0 5651#define GEN6_RC_EVALUATION_INTERVAL 0xA0A8 5652#define GEN6_RC_IDLE_HYSTERSIS 0xA0AC 5653#define GEN6_RC_SLEEP 0xA0B0 5654#define GEN6_RCUBMABDTMR 0xA0B0 5655#define GEN6_RC1e_THRESHOLD 0xA0B4 5656#define GEN6_RC6_THRESHOLD 0xA0B8 5657#define GEN6_RC6p_THRESHOLD 0xA0BC 5658#define VLV_RCEDATA 0xA0BC 5659#define GEN6_RC6pp_THRESHOLD 0xA0C0 5660#define GEN6_PMINTRMSK 0xA168 5661#define GEN8_PMINTR_REDIRECT_TO_NON_DISP (1<<31) 5662#define VLV_PWRDWNUPCTL 0xA294 5663 5664#define GEN6_PMISR 0x44020 5665#define GEN6_PMIMR 0x44024 /* rps_lock */ 5666#define GEN6_PMIIR 0x44028 5667#define GEN6_PMIER 0x4402C 5668#define GEN6_PM_MBOX_EVENT (1<<25) 5669#define GEN6_PM_THERMAL_EVENT (1<<24) 5670#define GEN6_PM_RP_DOWN_TIMEOUT (1<<6) 5671#define GEN6_PM_RP_UP_THRESHOLD (1<<5) 5672#define GEN6_PM_RP_DOWN_THRESHOLD (1<<4) 5673#define GEN6_PM_RP_UP_EI_EXPIRED (1<<2) 5674#define GEN6_PM_RP_DOWN_EI_EXPIRED (1<<1) 5675#define GEN6_PM_RPS_EVENTS (GEN6_PM_RP_UP_THRESHOLD | \ 5676 GEN6_PM_RP_DOWN_THRESHOLD | \ 5677 GEN6_PM_RP_DOWN_TIMEOUT) 5678 5679#define GEN7_GT_SCRATCH_BASE 0x4F100 5680#define GEN7_GT_SCRATCH_REG_NUM 8 5681 5682#define VLV_GTLC_SURVIVABILITY_REG 0x130098 5683#define VLV_GFX_CLK_STATUS_BIT (1<<3) 5684#define VLV_GFX_CLK_FORCE_ON_BIT (1<<2) 5685 5686#define GEN6_GT_GFX_RC6_LOCKED 0x138104 5687#define VLV_COUNTER_CONTROL 0x138104 5688#define VLV_COUNT_RANGE_HIGH (1<<15) 5689#define VLV_MEDIA_RC0_COUNT_EN (1<<5) 5690#define VLV_RENDER_RC0_COUNT_EN (1<<4) 5691#define VLV_MEDIA_RC6_COUNT_EN (1<<1) 5692#define VLV_RENDER_RC6_COUNT_EN (1<<0) 5693#define GEN6_GT_GFX_RC6 0x138108 5694#define VLV_GT_RENDER_RC6 0x138108 5695#define VLV_GT_MEDIA_RC6 0x13810C 5696 5697#define GEN6_GT_GFX_RC6p 0x13810C 5698#define GEN6_GT_GFX_RC6pp 0x138110 5699#define VLV_RENDER_C0_COUNT_REG 0x138118 5700#define VLV_MEDIA_C0_COUNT_REG 0x13811C 5701 5702#define GEN6_PCODE_MAILBOX 0x138124 5703#define GEN6_PCODE_READY (1<<31) 5704#define GEN6_READ_OC_PARAMS 0xc 5705#define GEN6_PCODE_WRITE_MIN_FREQ_TABLE 0x8 5706#define GEN6_PCODE_READ_MIN_FREQ_TABLE 0x9 5707#define GEN6_PCODE_WRITE_RC6VIDS 0x4 5708#define GEN6_PCODE_READ_RC6VIDS 0x5 5709#define GEN6_PCODE_READ_D_COMP 0x10 5710#define GEN6_PCODE_WRITE_D_COMP 0x11 5711#define GEN6_ENCODE_RC6_VID(mv) (((mv) - 245) / 5) 5712#define GEN6_DECODE_RC6_VID(vids) (((vids) * 5) + 245) 5713#define DISPLAY_IPS_CONTROL 0x19 5714#define GEN6_PCODE_DATA 0x138128 5715#define GEN6_PCODE_FREQ_IA_RATIO_SHIFT 8 5716#define GEN6_PCODE_FREQ_RING_RATIO_SHIFT 16 5717 5718#define GEN6_GT_CORE_STATUS 0x138060 5719#define GEN6_CORE_CPD_STATE_MASK (7<<4) 5720#define GEN6_RCn_MASK 7 5721#define GEN6_RC0 0 5722#define GEN6_RC3 2 5723#define GEN6_RC6 3 5724#define GEN6_RC7 4 5725 5726#define GEN7_MISCCPCTL (0x9424) 5727#define GEN7_DOP_CLOCK_GATE_ENABLE (1<<0) 5728 5729/* IVYBRIDGE DPF */ 5730#define GEN7_L3CDERRST1 0xB008 /* L3CD Error Status 1 */ 5731#define HSW_L3CDERRST11 0xB208 /* L3CD Error Status register 1 slice 1 */ 5732#define GEN7_L3CDERRST1_ROW_MASK (0x7ff<<14) 5733#define GEN7_PARITY_ERROR_VALID (1<<13) 5734#define GEN7_L3CDERRST1_BANK_MASK (3<<11) 5735#define GEN7_L3CDERRST1_SUBBANK_MASK (7<<8) 5736#define GEN7_PARITY_ERROR_ROW(reg) \ 5737 ((reg & GEN7_L3CDERRST1_ROW_MASK) >> 14) 5738#define GEN7_PARITY_ERROR_BANK(reg) \ 5739 ((reg & GEN7_L3CDERRST1_BANK_MASK) >> 11) 5740#define GEN7_PARITY_ERROR_SUBBANK(reg) \ 5741 ((reg & GEN7_L3CDERRST1_SUBBANK_MASK) >> 8) 5742#define GEN7_L3CDERRST1_ENABLE (1<<7) 5743 5744#define GEN7_L3LOG_BASE 0xB070 5745#define HSW_L3LOG_BASE_SLICE1 0xB270 5746#define GEN7_L3LOG_SIZE 0x80 5747 5748#define GEN7_HALF_SLICE_CHICKEN1 0xe100 /* IVB GT1 + VLV */ 5749#define GEN7_HALF_SLICE_CHICKEN1_GT2 0xf100 5750#define GEN7_MAX_PS_THREAD_DEP (8<<12) 5751#define GEN7_SINGLE_SUBSCAN_DISPATCH_ENABLE (1<<10) 5752#define GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE (1<<3) 5753 5754#define GEN8_ROW_CHICKEN 0xe4f0 5755#define PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE (1<<8) 5756#define STALL_DOP_GATING_DISABLE (1<<5) 5757 5758#define GEN7_ROW_CHICKEN2 0xe4f4 5759#define GEN7_ROW_CHICKEN2_GT2 0xf4f4 5760#define DOP_CLOCK_GATING_DISABLE (1<<0) 5761 5762#define HSW_ROW_CHICKEN3 0xe49c 5763#define HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE (1 << 6) 5764 5765#define HALF_SLICE_CHICKEN3 0xe184 5766#define GEN8_CENTROID_PIXEL_OPT_DIS (1<<8) 5767#define GEN8_SAMPLER_POWER_BYPASS_DIS (1<<1) 5768 5769#define G4X_AUD_VID_DID (dev_priv->info.display_mmio_offset + 0x62020) 5770#define INTEL_AUDIO_DEVCL 0x808629FB 5771#define INTEL_AUDIO_DEVBLC 0x80862801 5772#define INTEL_AUDIO_DEVCTG 0x80862802 5773 5774#define G4X_AUD_CNTL_ST 0x620B4 5775#define G4X_ELDV_DEVCL_DEVBLC (1 << 13) 5776#define G4X_ELDV_DEVCTG (1 << 14) 5777#define G4X_ELD_ADDR (0xf << 5) 5778#define G4X_ELD_ACK (1 << 4) 5779#define G4X_HDMIW_HDMIEDID 0x6210C 5780 5781#define IBX_HDMIW_HDMIEDID_A 0xE2050 5782#define IBX_HDMIW_HDMIEDID_B 0xE2150 5783#define IBX_HDMIW_HDMIEDID(pipe) _PIPE(pipe, \ 5784 IBX_HDMIW_HDMIEDID_A, \ 5785 IBX_HDMIW_HDMIEDID_B) 5786#define IBX_AUD_CNTL_ST_A 0xE20B4 5787#define IBX_AUD_CNTL_ST_B 0xE21B4 5788#define IBX_AUD_CNTL_ST(pipe) _PIPE(pipe, \ 5789 IBX_AUD_CNTL_ST_A, \ 5790 IBX_AUD_CNTL_ST_B) 5791#define IBX_ELD_BUFFER_SIZE (0x1f << 10) 5792#define IBX_ELD_ADDRESS (0x1f << 5) 5793#define IBX_ELD_ACK (1 << 4) 5794#define IBX_AUD_CNTL_ST2 0xE20C0 5795#define IBX_ELD_VALIDB (1 << 0) 5796#define IBX_CP_READYB (1 << 1) 5797 5798#define CPT_HDMIW_HDMIEDID_A 0xE5050 5799#define CPT_HDMIW_HDMIEDID_B 0xE5150 5800#define CPT_HDMIW_HDMIEDID(pipe) _PIPE(pipe, \ 5801 CPT_HDMIW_HDMIEDID_A, \ 5802 CPT_HDMIW_HDMIEDID_B) 5803#define CPT_AUD_CNTL_ST_A 0xE50B4 5804#define CPT_AUD_CNTL_ST_B 0xE51B4 5805#define CPT_AUD_CNTL_ST(pipe) _PIPE(pipe, \ 5806 CPT_AUD_CNTL_ST_A, \ 5807 CPT_AUD_CNTL_ST_B) 5808#define CPT_AUD_CNTRL_ST2 0xE50C0 5809 5810#define VLV_HDMIW_HDMIEDID_A (VLV_DISPLAY_BASE + 0x62050) 5811#define VLV_HDMIW_HDMIEDID_B (VLV_DISPLAY_BASE + 0x62150) 5812#define VLV_HDMIW_HDMIEDID(pipe) _PIPE(pipe, \ 5813 VLV_HDMIW_HDMIEDID_A, \ 5814 VLV_HDMIW_HDMIEDID_B) 5815#define VLV_AUD_CNTL_ST_A (VLV_DISPLAY_BASE + 0x620B4) 5816#define VLV_AUD_CNTL_ST_B (VLV_DISPLAY_BASE + 0x621B4) 5817#define VLV_AUD_CNTL_ST(pipe) _PIPE(pipe, \ 5818 VLV_AUD_CNTL_ST_A, \ 5819 VLV_AUD_CNTL_ST_B) 5820#define VLV_AUD_CNTL_ST2 (VLV_DISPLAY_BASE + 0x620C0) 5821 5822/* These are the 4 32-bit write offset registers for each stream 5823 * output buffer. It determines the offset from the 5824 * 3DSTATE_SO_BUFFERs that the next streamed vertex output goes to. 5825 */ 5826#define GEN7_SO_WRITE_OFFSET(n) (0x5280 + (n) * 4) 5827 5828#define IBX_AUD_CONFIG_A 0xe2000 5829#define IBX_AUD_CONFIG_B 0xe2100 5830#define IBX_AUD_CFG(pipe) _PIPE(pipe, \ 5831 IBX_AUD_CONFIG_A, \ 5832 IBX_AUD_CONFIG_B) 5833#define CPT_AUD_CONFIG_A 0xe5000 5834#define CPT_AUD_CONFIG_B 0xe5100 5835#define CPT_AUD_CFG(pipe) _PIPE(pipe, \ 5836 CPT_AUD_CONFIG_A, \ 5837 CPT_AUD_CONFIG_B) 5838#define VLV_AUD_CONFIG_A (VLV_DISPLAY_BASE + 0x62000) 5839#define VLV_AUD_CONFIG_B (VLV_DISPLAY_BASE + 0x62100) 5840#define VLV_AUD_CFG(pipe) _PIPE(pipe, \ 5841 VLV_AUD_CONFIG_A, \ 5842 VLV_AUD_CONFIG_B) 5843 5844#define AUD_CONFIG_N_VALUE_INDEX (1 << 29) 5845#define AUD_CONFIG_N_PROG_ENABLE (1 << 28) 5846#define AUD_CONFIG_UPPER_N_SHIFT 20 5847#define AUD_CONFIG_UPPER_N_VALUE (0xff << 20) 5848#define AUD_CONFIG_LOWER_N_SHIFT 4 5849#define AUD_CONFIG_LOWER_N_VALUE (0xfff << 4) 5850#define AUD_CONFIG_PIXEL_CLOCK_HDMI_SHIFT 16 5851#define AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK (0xf << 16) 5852#define AUD_CONFIG_PIXEL_CLOCK_HDMI_25175 (0 << 16) 5853#define AUD_CONFIG_PIXEL_CLOCK_HDMI_25200 (1 << 16) 5854#define AUD_CONFIG_PIXEL_CLOCK_HDMI_27000 (2 << 16) 5855#define AUD_CONFIG_PIXEL_CLOCK_HDMI_27027 (3 << 16) 5856#define AUD_CONFIG_PIXEL_CLOCK_HDMI_54000 (4 << 16) 5857#define AUD_CONFIG_PIXEL_CLOCK_HDMI_54054 (5 << 16) 5858#define AUD_CONFIG_PIXEL_CLOCK_HDMI_74176 (6 << 16) 5859#define AUD_CONFIG_PIXEL_CLOCK_HDMI_74250 (7 << 16) 5860#define AUD_CONFIG_PIXEL_CLOCK_HDMI_148352 (8 << 16) 5861#define AUD_CONFIG_PIXEL_CLOCK_HDMI_148500 (9 << 16) 5862#define AUD_CONFIG_DISABLE_NCTS (1 << 3) 5863 5864/* HSW Audio */ 5865#define HSW_AUD_CONFIG_A 0x65000 /* Audio Configuration Transcoder A */ 5866#define HSW_AUD_CONFIG_B 0x65100 /* Audio Configuration Transcoder B */ 5867#define HSW_AUD_CFG(pipe) _PIPE(pipe, \ 5868 HSW_AUD_CONFIG_A, \ 5869 HSW_AUD_CONFIG_B) 5870 5871#define HSW_AUD_MISC_CTRL_A 0x65010 /* Audio Misc Control Convert 1 */ 5872#define HSW_AUD_MISC_CTRL_B 0x65110 /* Audio Misc Control Convert 2 */ 5873#define HSW_AUD_MISC_CTRL(pipe) _PIPE(pipe, \ 5874 HSW_AUD_MISC_CTRL_A, \ 5875 HSW_AUD_MISC_CTRL_B) 5876 5877#define HSW_AUD_DIP_ELD_CTRL_ST_A 0x650b4 /* Audio DIP and ELD Control State Transcoder A */ 5878#define HSW_AUD_DIP_ELD_CTRL_ST_B 0x651b4 /* Audio DIP and ELD Control State Transcoder B */ 5879#define HSW_AUD_DIP_ELD_CTRL(pipe) _PIPE(pipe, \ 5880 HSW_AUD_DIP_ELD_CTRL_ST_A, \ 5881 HSW_AUD_DIP_ELD_CTRL_ST_B) 5882 5883/* Audio Digital Converter */ 5884#define HSW_AUD_DIG_CNVT_1 0x65080 /* Audio Converter 1 */ 5885#define HSW_AUD_DIG_CNVT_2 0x65180 /* Audio Converter 1 */ 5886#define AUD_DIG_CNVT(pipe) _PIPE(pipe, \ 5887 HSW_AUD_DIG_CNVT_1, \ 5888 HSW_AUD_DIG_CNVT_2) 5889#define DIP_PORT_SEL_MASK 0x3 5890 5891#define HSW_AUD_EDID_DATA_A 0x65050 5892#define HSW_AUD_EDID_DATA_B 0x65150 5893#define HSW_AUD_EDID_DATA(pipe) _PIPE(pipe, \ 5894 HSW_AUD_EDID_DATA_A, \ 5895 HSW_AUD_EDID_DATA_B) 5896 5897#define HSW_AUD_PIPE_CONV_CFG 0x6507c /* Audio pipe and converter configs */ 5898#define HSW_AUD_PIN_ELD_CP_VLD 0x650c0 /* Audio ELD and CP Ready Status */ 5899#define AUDIO_INACTIVE_C (1<<11) 5900#define AUDIO_INACTIVE_B (1<<7) 5901#define AUDIO_INACTIVE_A (1<<3) 5902#define AUDIO_OUTPUT_ENABLE_A (1<<2) 5903#define AUDIO_OUTPUT_ENABLE_B (1<<6) 5904#define AUDIO_OUTPUT_ENABLE_C (1<<10) 5905#define AUDIO_ELD_VALID_A (1<<0) 5906#define AUDIO_ELD_VALID_B (1<<4) 5907#define AUDIO_ELD_VALID_C (1<<8) 5908#define AUDIO_CP_READY_A (1<<1) 5909#define AUDIO_CP_READY_B (1<<5) 5910#define AUDIO_CP_READY_C (1<<9) 5911 5912/* HSW Power Wells */ 5913#define HSW_PWR_WELL_BIOS 0x45400 /* CTL1 */ 5914#define HSW_PWR_WELL_DRIVER 0x45404 /* CTL2 */ 5915#define HSW_PWR_WELL_KVMR 0x45408 /* CTL3 */ 5916#define HSW_PWR_WELL_DEBUG 0x4540C /* CTL4 */ 5917#define HSW_PWR_WELL_ENABLE_REQUEST (1<<31) 5918#define HSW_PWR_WELL_STATE_ENABLED (1<<30) 5919#define HSW_PWR_WELL_CTL5 0x45410 5920#define HSW_PWR_WELL_ENABLE_SINGLE_STEP (1<<31) 5921#define HSW_PWR_WELL_PWR_GATE_OVERRIDE (1<<20) 5922#define HSW_PWR_WELL_FORCE_ON (1<<19) 5923#define HSW_PWR_WELL_CTL6 0x45414 5924 5925/* Per-pipe DDI Function Control */ 5926#define TRANS_DDI_FUNC_CTL_A 0x60400 5927#define TRANS_DDI_FUNC_CTL_B 0x61400 5928#define TRANS_DDI_FUNC_CTL_C 0x62400 5929#define TRANS_DDI_FUNC_CTL_EDP 0x6F400 5930#define TRANS_DDI_FUNC_CTL(tran) _TRANSCODER2(tran, TRANS_DDI_FUNC_CTL_A) 5931 5932#define TRANS_DDI_FUNC_ENABLE (1<<31) 5933/* Those bits are ignored by pipe EDP since it can only connect to DDI A */ 5934#define TRANS_DDI_PORT_MASK (7<<28) 5935#define TRANS_DDI_PORT_SHIFT 28 5936#define TRANS_DDI_SELECT_PORT(x) ((x)<<28) 5937#define TRANS_DDI_PORT_NONE (0<<28) 5938#define TRANS_DDI_MODE_SELECT_MASK (7<<24) 5939#define TRANS_DDI_MODE_SELECT_HDMI (0<<24) 5940#define TRANS_DDI_MODE_SELECT_DVI (1<<24) 5941#define TRANS_DDI_MODE_SELECT_DP_SST (2<<24) 5942#define TRANS_DDI_MODE_SELECT_DP_MST (3<<24) 5943#define TRANS_DDI_MODE_SELECT_FDI (4<<24) 5944#define TRANS_DDI_BPC_MASK (7<<20) 5945#define TRANS_DDI_BPC_8 (0<<20) 5946#define TRANS_DDI_BPC_10 (1<<20) 5947#define TRANS_DDI_BPC_6 (2<<20) 5948#define TRANS_DDI_BPC_12 (3<<20) 5949#define TRANS_DDI_PVSYNC (1<<17) 5950#define TRANS_DDI_PHSYNC (1<<16) 5951#define TRANS_DDI_EDP_INPUT_MASK (7<<12) 5952#define TRANS_DDI_EDP_INPUT_A_ON (0<<12) 5953#define TRANS_DDI_EDP_INPUT_A_ONOFF (4<<12) 5954#define TRANS_DDI_EDP_INPUT_B_ONOFF (5<<12) 5955#define TRANS_DDI_EDP_INPUT_C_ONOFF (6<<12) 5956#define TRANS_DDI_DP_VC_PAYLOAD_ALLOC (1<<8) 5957#define TRANS_DDI_BFI_ENABLE (1<<4) 5958 5959/* DisplayPort Transport Control */ 5960#define DP_TP_CTL_A 0x64040 5961#define DP_TP_CTL_B 0x64140 5962#define DP_TP_CTL(port) _PORT(port, DP_TP_CTL_A, DP_TP_CTL_B) 5963#define DP_TP_CTL_ENABLE (1<<31) 5964#define DP_TP_CTL_MODE_SST (0<<27) 5965#define DP_TP_CTL_MODE_MST (1<<27) 5966#define DP_TP_CTL_FORCE_ACT (1<<25) 5967#define DP_TP_CTL_ENHANCED_FRAME_ENABLE (1<<18) 5968#define DP_TP_CTL_FDI_AUTOTRAIN (1<<15) 5969#define DP_TP_CTL_LINK_TRAIN_MASK (7<<8) 5970#define DP_TP_CTL_LINK_TRAIN_PAT1 (0<<8) 5971#define DP_TP_CTL_LINK_TRAIN_PAT2 (1<<8) 5972#define DP_TP_CTL_LINK_TRAIN_PAT3 (4<<8) 5973#define DP_TP_CTL_LINK_TRAIN_IDLE (2<<8) 5974#define DP_TP_CTL_LINK_TRAIN_NORMAL (3<<8) 5975#define DP_TP_CTL_SCRAMBLE_DISABLE (1<<7) 5976 5977/* DisplayPort Transport Status */ 5978#define DP_TP_STATUS_A 0x64044 5979#define DP_TP_STATUS_B 0x64144 5980#define DP_TP_STATUS(port) _PORT(port, DP_TP_STATUS_A, DP_TP_STATUS_B) 5981#define DP_TP_STATUS_IDLE_DONE (1<<25) 5982#define DP_TP_STATUS_ACT_SENT (1<<24) 5983#define DP_TP_STATUS_MODE_STATUS_MST (1<<23) 5984#define DP_TP_STATUS_AUTOTRAIN_DONE (1<<12) 5985#define DP_TP_STATUS_PAYLOAD_MAPPING_VC2 (3 << 8) 5986#define DP_TP_STATUS_PAYLOAD_MAPPING_VC1 (3 << 4) 5987#define DP_TP_STATUS_PAYLOAD_MAPPING_VC0 (3 << 0) 5988 5989/* DDI Buffer Control */ 5990#define DDI_BUF_CTL_A 0x64000 5991#define DDI_BUF_CTL_B 0x64100 5992#define DDI_BUF_CTL(port) _PORT(port, DDI_BUF_CTL_A, DDI_BUF_CTL_B) 5993#define DDI_BUF_CTL_ENABLE (1<<31) 5994#define DDI_BUF_TRANS_SELECT(n) ((n) << 24) 5995#define DDI_BUF_EMP_MASK (0xf<<24) 5996#define DDI_BUF_PORT_REVERSAL (1<<16) 5997#define DDI_BUF_IS_IDLE (1<<7) 5998#define DDI_A_4_LANES (1<<4) 5999#define DDI_PORT_WIDTH(width) (((width) - 1) << 1) 6000#define DDI_INIT_DISPLAY_DETECTED (1<<0) 6001 6002/* DDI Buffer Translations */ 6003#define DDI_BUF_TRANS_A 0x64E00 6004#define DDI_BUF_TRANS_B 0x64E60 6005#define DDI_BUF_TRANS(port) _PORT(port, DDI_BUF_TRANS_A, DDI_BUF_TRANS_B) 6006 6007/* Sideband Interface (SBI) is programmed indirectly, via 6008 * SBI_ADDR, which contains the register offset; and SBI_DATA, 6009 * which contains the payload */ 6010#define SBI_ADDR 0xC6000 6011#define SBI_DATA 0xC6004 6012#define SBI_CTL_STAT 0xC6008 6013#define SBI_CTL_DEST_ICLK (0x0<<16) 6014#define SBI_CTL_DEST_MPHY (0x1<<16) 6015#define SBI_CTL_OP_IORD (0x2<<8) 6016#define SBI_CTL_OP_IOWR (0x3<<8) 6017#define SBI_CTL_OP_CRRD (0x6<<8) 6018#define SBI_CTL_OP_CRWR (0x7<<8) 6019#define SBI_RESPONSE_FAIL (0x1<<1) 6020#define SBI_RESPONSE_SUCCESS (0x0<<1) 6021#define SBI_BUSY (0x1<<0) 6022#define SBI_READY (0x0<<0) 6023 6024/* SBI offsets */ 6025#define SBI_SSCDIVINTPHASE6 0x0600 6026#define SBI_SSCDIVINTPHASE_DIVSEL_MASK ((0x7f)<<1) 6027#define SBI_SSCDIVINTPHASE_DIVSEL(x) ((x)<<1) 6028#define SBI_SSCDIVINTPHASE_INCVAL_MASK ((0x7f)<<8) 6029#define SBI_SSCDIVINTPHASE_INCVAL(x) ((x)<<8) 6030#define SBI_SSCDIVINTPHASE_DIR(x) ((x)<<15) 6031#define SBI_SSCDIVINTPHASE_PROPAGATE (1<<0) 6032#define SBI_SSCCTL 0x020c 6033#define SBI_SSCCTL6 0x060C 6034#define SBI_SSCCTL_PATHALT (1<<3) 6035#define SBI_SSCCTL_DISABLE (1<<0) 6036#define SBI_SSCAUXDIV6 0x0610 6037#define SBI_SSCAUXDIV_FINALDIV2SEL(x) ((x)<<4) 6038#define SBI_DBUFF0 0x2a00 6039#define SBI_GEN0 0x1f00 6040#define SBI_GEN0_CFG_BUFFENABLE_DISABLE (1<<0) 6041 6042/* LPT PIXCLK_GATE */ 6043#define PIXCLK_GATE 0xC6020 6044#define PIXCLK_GATE_UNGATE (1<<0) 6045#define PIXCLK_GATE_GATE (0<<0) 6046 6047/* SPLL */ 6048#define SPLL_CTL 0x46020 6049#define SPLL_PLL_ENABLE (1<<31) 6050#define SPLL_PLL_SSC (1<<28) 6051#define SPLL_PLL_NON_SSC (2<<28) 6052#define SPLL_PLL_LCPLL (3<<28) 6053#define SPLL_PLL_REF_MASK (3<<28) 6054#define SPLL_PLL_FREQ_810MHz (0<<26) 6055#define SPLL_PLL_FREQ_1350MHz (1<<26) 6056#define SPLL_PLL_FREQ_2700MHz (2<<26) 6057#define SPLL_PLL_FREQ_MASK (3<<26) 6058 6059/* WRPLL */ 6060#define WRPLL_CTL1 0x46040 6061#define WRPLL_CTL2 0x46060 6062#define WRPLL_CTL(pll) (pll == 0 ? WRPLL_CTL1 : WRPLL_CTL2) 6063#define WRPLL_PLL_ENABLE (1<<31) 6064#define WRPLL_PLL_SSC (1<<28) 6065#define WRPLL_PLL_NON_SSC (2<<28) 6066#define WRPLL_PLL_LCPLL (3<<28) 6067#define WRPLL_PLL_REF_MASK (3<<28) 6068/* WRPLL divider programming */ 6069#define WRPLL_DIVIDER_REFERENCE(x) ((x)<<0) 6070#define WRPLL_DIVIDER_REF_MASK (0xff) 6071#define WRPLL_DIVIDER_POST(x) ((x)<<8) 6072#define WRPLL_DIVIDER_POST_MASK (0x3f<<8) 6073#define WRPLL_DIVIDER_POST_SHIFT 8 6074#define WRPLL_DIVIDER_FEEDBACK(x) ((x)<<16) 6075#define WRPLL_DIVIDER_FB_SHIFT 16 6076#define WRPLL_DIVIDER_FB_MASK (0xff<<16) 6077 6078/* Port clock selection */ 6079#define PORT_CLK_SEL_A 0x46100 6080#define PORT_CLK_SEL_B 0x46104 6081#define PORT_CLK_SEL(port) _PORT(port, PORT_CLK_SEL_A, PORT_CLK_SEL_B) 6082#define PORT_CLK_SEL_LCPLL_2700 (0<<29) 6083#define PORT_CLK_SEL_LCPLL_1350 (1<<29) 6084#define PORT_CLK_SEL_LCPLL_810 (2<<29) 6085#define PORT_CLK_SEL_SPLL (3<<29) 6086#define PORT_CLK_SEL_WRPLL(pll) (((pll)+4)<<29) 6087#define PORT_CLK_SEL_WRPLL1 (4<<29) 6088#define PORT_CLK_SEL_WRPLL2 (5<<29) 6089#define PORT_CLK_SEL_NONE (7<<29) 6090#define PORT_CLK_SEL_MASK (7<<29) 6091 6092/* Transcoder clock selection */ 6093#define TRANS_CLK_SEL_A 0x46140 6094#define TRANS_CLK_SEL_B 0x46144 6095#define TRANS_CLK_SEL(tran) _TRANSCODER(tran, TRANS_CLK_SEL_A, TRANS_CLK_SEL_B) 6096/* For each transcoder, we need to select the corresponding port clock */ 6097#define TRANS_CLK_SEL_DISABLED (0x0<<29) 6098#define TRANS_CLK_SEL_PORT(x) ((x+1)<<29) 6099 6100#define TRANSA_MSA_MISC 0x60410 6101#define TRANSB_MSA_MISC 0x61410 6102#define TRANSC_MSA_MISC 0x62410 6103#define TRANS_EDP_MSA_MISC 0x6f410 6104#define TRANS_MSA_MISC(tran) _TRANSCODER2(tran, TRANSA_MSA_MISC) 6105 6106#define TRANS_MSA_SYNC_CLK (1<<0) 6107#define TRANS_MSA_6_BPC (0<<5) 6108#define TRANS_MSA_8_BPC (1<<5) 6109#define TRANS_MSA_10_BPC (2<<5) 6110#define TRANS_MSA_12_BPC (3<<5) 6111#define TRANS_MSA_16_BPC (4<<5) 6112 6113/* LCPLL Control */ 6114#define LCPLL_CTL 0x130040 6115#define LCPLL_PLL_DISABLE (1<<31) 6116#define LCPLL_PLL_LOCK (1<<30) 6117#define LCPLL_CLK_FREQ_MASK (3<<26) 6118#define LCPLL_CLK_FREQ_450 (0<<26) 6119#define LCPLL_CLK_FREQ_54O_BDW (1<<26) 6120#define LCPLL_CLK_FREQ_337_5_BDW (2<<26) 6121#define LCPLL_CLK_FREQ_675_BDW (3<<26) 6122#define LCPLL_CD_CLOCK_DISABLE (1<<25) 6123#define LCPLL_CD2X_CLOCK_DISABLE (1<<23) 6124#define LCPLL_POWER_DOWN_ALLOW (1<<22) 6125#define LCPLL_CD_SOURCE_FCLK (1<<21) 6126#define LCPLL_CD_SOURCE_FCLK_DONE (1<<19) 6127 6128/* Please see hsw_read_dcomp() and hsw_write_dcomp() before using this register, 6129 * since on HSW we can't write to it using I915_WRITE. */ 6130#define D_COMP_HSW (MCHBAR_MIRROR_BASE_SNB + 0x5F0C) 6131#define D_COMP_BDW 0x138144 6132#define D_COMP_RCOMP_IN_PROGRESS (1<<9) 6133#define D_COMP_COMP_FORCE (1<<8) 6134#define D_COMP_COMP_DISABLE (1<<0) 6135 6136/* Pipe WM_LINETIME - watermark line time */ 6137#define PIPE_WM_LINETIME_A 0x45270 6138#define PIPE_WM_LINETIME_B 0x45274 6139#define PIPE_WM_LINETIME(pipe) _PIPE(pipe, PIPE_WM_LINETIME_A, \ 6140 PIPE_WM_LINETIME_B) 6141#define PIPE_WM_LINETIME_MASK (0x1ff) 6142#define PIPE_WM_LINETIME_TIME(x) ((x)) 6143#define PIPE_WM_LINETIME_IPS_LINETIME_MASK (0x1ff<<16) 6144#define PIPE_WM_LINETIME_IPS_LINETIME(x) ((x)<<16) 6145 6146/* SFUSE_STRAP */ 6147#define SFUSE_STRAP 0xc2014 6148#define SFUSE_STRAP_FUSE_LOCK (1<<13) 6149#define SFUSE_STRAP_DISPLAY_DISABLED (1<<7) 6150#define SFUSE_STRAP_DDIB_DETECTED (1<<2) 6151#define SFUSE_STRAP_DDIC_DETECTED (1<<1) 6152#define SFUSE_STRAP_DDID_DETECTED (1<<0) 6153 6154#define WM_MISC 0x45260 6155#define WM_MISC_DATA_PARTITION_5_6 (1 << 0) 6156 6157#define WM_DBG 0x45280 6158#define WM_DBG_DISALLOW_MULTIPLE_LP (1<<0) 6159#define WM_DBG_DISALLOW_MAXFIFO (1<<1) 6160#define WM_DBG_DISALLOW_SPRITE (1<<2) 6161 6162/* pipe CSC */ 6163#define _PIPE_A_CSC_COEFF_RY_GY 0x49010 6164#define _PIPE_A_CSC_COEFF_BY 0x49014 6165#define _PIPE_A_CSC_COEFF_RU_GU 0x49018 6166#define _PIPE_A_CSC_COEFF_BU 0x4901c 6167#define _PIPE_A_CSC_COEFF_RV_GV 0x49020 6168#define _PIPE_A_CSC_COEFF_BV 0x49024 6169#define _PIPE_A_CSC_MODE 0x49028 6170#define CSC_BLACK_SCREEN_OFFSET (1 << 2) 6171#define CSC_POSITION_BEFORE_GAMMA (1 << 1) 6172#define CSC_MODE_YUV_TO_RGB (1 << 0) 6173#define _PIPE_A_CSC_PREOFF_HI 0x49030 6174#define _PIPE_A_CSC_PREOFF_ME 0x49034 6175#define _PIPE_A_CSC_PREOFF_LO 0x49038 6176#define _PIPE_A_CSC_POSTOFF_HI 0x49040 6177#define _PIPE_A_CSC_POSTOFF_ME 0x49044 6178#define _PIPE_A_CSC_POSTOFF_LO 0x49048 6179 6180#define _PIPE_B_CSC_COEFF_RY_GY 0x49110 6181#define _PIPE_B_CSC_COEFF_BY 0x49114 6182#define _PIPE_B_CSC_COEFF_RU_GU 0x49118 6183#define _PIPE_B_CSC_COEFF_BU 0x4911c 6184#define _PIPE_B_CSC_COEFF_RV_GV 0x49120 6185#define _PIPE_B_CSC_COEFF_BV 0x49124 6186#define _PIPE_B_CSC_MODE 0x49128 6187#define _PIPE_B_CSC_PREOFF_HI 0x49130 6188#define _PIPE_B_CSC_PREOFF_ME 0x49134 6189#define _PIPE_B_CSC_PREOFF_LO 0x49138 6190#define _PIPE_B_CSC_POSTOFF_HI 0x49140 6191#define _PIPE_B_CSC_POSTOFF_ME 0x49144 6192#define _PIPE_B_CSC_POSTOFF_LO 0x49148 6193 6194#define PIPE_CSC_COEFF_RY_GY(pipe) _PIPE(pipe, _PIPE_A_CSC_COEFF_RY_GY, _PIPE_B_CSC_COEFF_RY_GY) 6195#define PIPE_CSC_COEFF_BY(pipe) _PIPE(pipe, _PIPE_A_CSC_COEFF_BY, _PIPE_B_CSC_COEFF_BY) 6196#define PIPE_CSC_COEFF_RU_GU(pipe) _PIPE(pipe, _PIPE_A_CSC_COEFF_RU_GU, _PIPE_B_CSC_COEFF_RU_GU) 6197#define PIPE_CSC_COEFF_BU(pipe) _PIPE(pipe, _PIPE_A_CSC_COEFF_BU, _PIPE_B_CSC_COEFF_BU) 6198#define PIPE_CSC_COEFF_RV_GV(pipe) _PIPE(pipe, _PIPE_A_CSC_COEFF_RV_GV, _PIPE_B_CSC_COEFF_RV_GV) 6199#define PIPE_CSC_COEFF_BV(pipe) _PIPE(pipe, _PIPE_A_CSC_COEFF_BV, _PIPE_B_CSC_COEFF_BV) 6200#define PIPE_CSC_MODE(pipe) _PIPE(pipe, _PIPE_A_CSC_MODE, _PIPE_B_CSC_MODE) 6201#define PIPE_CSC_PREOFF_HI(pipe) _PIPE(pipe, _PIPE_A_CSC_PREOFF_HI, _PIPE_B_CSC_PREOFF_HI) 6202#define PIPE_CSC_PREOFF_ME(pipe) _PIPE(pipe, _PIPE_A_CSC_PREOFF_ME, _PIPE_B_CSC_PREOFF_ME) 6203#define PIPE_CSC_PREOFF_LO(pipe) _PIPE(pipe, _PIPE_A_CSC_PREOFF_LO, _PIPE_B_CSC_PREOFF_LO) 6204#define PIPE_CSC_POSTOFF_HI(pipe) _PIPE(pipe, _PIPE_A_CSC_POSTOFF_HI, _PIPE_B_CSC_POSTOFF_HI) 6205#define PIPE_CSC_POSTOFF_ME(pipe) _PIPE(pipe, _PIPE_A_CSC_POSTOFF_ME, _PIPE_B_CSC_POSTOFF_ME) 6206#define PIPE_CSC_POSTOFF_LO(pipe) _PIPE(pipe, _PIPE_A_CSC_POSTOFF_LO, _PIPE_B_CSC_POSTOFF_LO) 6207 6208/* VLV MIPI registers */ 6209 6210#define _MIPIA_PORT_CTRL (VLV_DISPLAY_BASE + 0x61190) 6211#define _MIPIB_PORT_CTRL (VLV_DISPLAY_BASE + 0x61700) 6212#define MIPI_PORT_CTRL(tc) _TRANSCODER(tc, _MIPIA_PORT_CTRL, \ 6213 _MIPIB_PORT_CTRL) 6214#define DPI_ENABLE (1 << 31) /* A + B */ 6215#define MIPIA_MIPI4DPHY_DELAY_COUNT_SHIFT 27 6216#define MIPIA_MIPI4DPHY_DELAY_COUNT_MASK (0xf << 27) 6217#define DUAL_LINK_MODE_MASK (1 << 26) 6218#define DUAL_LINK_MODE_FRONT_BACK (0 << 26) 6219#define DUAL_LINK_MODE_PIXEL_ALTERNATIVE (1 << 26) 6220#define DITHERING_ENABLE (1 << 25) /* A + B */ 6221#define FLOPPED_HSTX (1 << 23) 6222#define DE_INVERT (1 << 19) /* XXX */ 6223#define MIPIA_FLISDSI_DELAY_COUNT_SHIFT 18 6224#define MIPIA_FLISDSI_DELAY_COUNT_MASK (0xf << 18) 6225#define AFE_LATCHOUT (1 << 17) 6226#define LP_OUTPUT_HOLD (1 << 16) 6227#define MIPIB_FLISDSI_DELAY_COUNT_HIGH_SHIFT 15 6228#define MIPIB_FLISDSI_DELAY_COUNT_HIGH_MASK (1 << 15) 6229#define MIPIB_MIPI4DPHY_DELAY_COUNT_SHIFT 11 6230#define MIPIB_MIPI4DPHY_DELAY_COUNT_MASK (0xf << 11) 6231#define CSB_SHIFT 9 6232#define CSB_MASK (3 << 9) 6233#define CSB_20MHZ (0 << 9) 6234#define CSB_10MHZ (1 << 9) 6235#define CSB_40MHZ (2 << 9) 6236#define BANDGAP_MASK (1 << 8) 6237#define BANDGAP_PNW_CIRCUIT (0 << 8) 6238#define BANDGAP_LNC_CIRCUIT (1 << 8) 6239#define MIPIB_FLISDSI_DELAY_COUNT_LOW_SHIFT 5 6240#define MIPIB_FLISDSI_DELAY_COUNT_LOW_MASK (7 << 5) 6241#define TEARING_EFFECT_DELAY (1 << 4) /* A + B */ 6242#define TEARING_EFFECT_SHIFT 2 /* A + B */ 6243#define TEARING_EFFECT_MASK (3 << 2) 6244#define TEARING_EFFECT_OFF (0 << 2) 6245#define TEARING_EFFECT_DSI (1 << 2) 6246#define TEARING_EFFECT_GPIO (2 << 2) 6247#define LANE_CONFIGURATION_SHIFT 0 6248#define LANE_CONFIGURATION_MASK (3 << 0) 6249#define LANE_CONFIGURATION_4LANE (0 << 0) 6250#define LANE_CONFIGURATION_DUAL_LINK_A (1 << 0) 6251#define LANE_CONFIGURATION_DUAL_LINK_B (2 << 0) 6252 6253#define _MIPIA_TEARING_CTRL (VLV_DISPLAY_BASE + 0x61194) 6254#define _MIPIB_TEARING_CTRL (VLV_DISPLAY_BASE + 0x61704) 6255#define MIPI_TEARING_CTRL(tc) _TRANSCODER(tc, \ 6256 _MIPIA_TEARING_CTRL, _MIPIB_TEARING_CTRL) 6257#define TEARING_EFFECT_DELAY_SHIFT 0 6258#define TEARING_EFFECT_DELAY_MASK (0xffff << 0) 6259 6260/* XXX: all bits reserved */ 6261#define _MIPIA_AUTOPWG (VLV_DISPLAY_BASE + 0x611a0) 6262 6263/* MIPI DSI Controller and D-PHY registers */ 6264 6265#define _MIPIA_DEVICE_READY (dev_priv->mipi_mmio_base + 0xb000) 6266#define _MIPIB_DEVICE_READY (dev_priv->mipi_mmio_base + 0xb800) 6267#define MIPI_DEVICE_READY(tc) _TRANSCODER(tc, _MIPIA_DEVICE_READY, \ 6268 _MIPIB_DEVICE_READY) 6269#define BUS_POSSESSION (1 << 3) /* set to give bus to receiver */ 6270#define ULPS_STATE_MASK (3 << 1) 6271#define ULPS_STATE_ENTER (2 << 1) 6272#define ULPS_STATE_EXIT (1 << 1) 6273#define ULPS_STATE_NORMAL_OPERATION (0 << 1) 6274#define DEVICE_READY (1 << 0) 6275 6276#define _MIPIA_INTR_STAT (dev_priv->mipi_mmio_base + 0xb004) 6277#define _MIPIB_INTR_STAT (dev_priv->mipi_mmio_base + 0xb804) 6278#define MIPI_INTR_STAT(tc) _TRANSCODER(tc, _MIPIA_INTR_STAT, \ 6279 _MIPIB_INTR_STAT) 6280#define _MIPIA_INTR_EN (dev_priv->mipi_mmio_base + 0xb008) 6281#define _MIPIB_INTR_EN (dev_priv->mipi_mmio_base + 0xb808) 6282#define MIPI_INTR_EN(tc) _TRANSCODER(tc, _MIPIA_INTR_EN, \ 6283 _MIPIB_INTR_EN) 6284#define TEARING_EFFECT (1 << 31) 6285#define SPL_PKT_SENT_INTERRUPT (1 << 30) 6286#define GEN_READ_DATA_AVAIL (1 << 29) 6287#define LP_GENERIC_WR_FIFO_FULL (1 << 28) 6288#define HS_GENERIC_WR_FIFO_FULL (1 << 27) 6289#define RX_PROT_VIOLATION (1 << 26) 6290#define RX_INVALID_TX_LENGTH (1 << 25) 6291#define ACK_WITH_NO_ERROR (1 << 24) 6292#define TURN_AROUND_ACK_TIMEOUT (1 << 23) 6293#define LP_RX_TIMEOUT (1 << 22) 6294#define HS_TX_TIMEOUT (1 << 21) 6295#define DPI_FIFO_UNDERRUN (1 << 20) 6296#define LOW_CONTENTION (1 << 19) 6297#define HIGH_CONTENTION (1 << 18) 6298#define TXDSI_VC_ID_INVALID (1 << 17) 6299#define TXDSI_DATA_TYPE_NOT_RECOGNISED (1 << 16) 6300#define TXCHECKSUM_ERROR (1 << 15) 6301#define TXECC_MULTIBIT_ERROR (1 << 14) 6302#define TXECC_SINGLE_BIT_ERROR (1 << 13) 6303#define TXFALSE_CONTROL_ERROR (1 << 12) 6304#define RXDSI_VC_ID_INVALID (1 << 11) 6305#define RXDSI_DATA_TYPE_NOT_REGOGNISED (1 << 10) 6306#define RXCHECKSUM_ERROR (1 << 9) 6307#define RXECC_MULTIBIT_ERROR (1 << 8) 6308#define RXECC_SINGLE_BIT_ERROR (1 << 7) 6309#define RXFALSE_CONTROL_ERROR (1 << 6) 6310#define RXHS_RECEIVE_TIMEOUT_ERROR (1 << 5) 6311#define RX_LP_TX_SYNC_ERROR (1 << 4) 6312#define RXEXCAPE_MODE_ENTRY_ERROR (1 << 3) 6313#define RXEOT_SYNC_ERROR (1 << 2) 6314#define RXSOT_SYNC_ERROR (1 << 1) 6315#define RXSOT_ERROR (1 << 0) 6316 6317#define _MIPIA_DSI_FUNC_PRG (dev_priv->mipi_mmio_base + 0xb00c) 6318#define _MIPIB_DSI_FUNC_PRG (dev_priv->mipi_mmio_base + 0xb80c) 6319#define MIPI_DSI_FUNC_PRG(tc) _TRANSCODER(tc, _MIPIA_DSI_FUNC_PRG, \ 6320 _MIPIB_DSI_FUNC_PRG) 6321#define CMD_MODE_DATA_WIDTH_MASK (7 << 13) 6322#define CMD_MODE_NOT_SUPPORTED (0 << 13) 6323#define CMD_MODE_DATA_WIDTH_16_BIT (1 << 13) 6324#define CMD_MODE_DATA_WIDTH_9_BIT (2 << 13) 6325#define CMD_MODE_DATA_WIDTH_8_BIT (3 << 13) 6326#define CMD_MODE_DATA_WIDTH_OPTION1 (4 << 13) 6327#define CMD_MODE_DATA_WIDTH_OPTION2 (5 << 13) 6328#define VID_MODE_FORMAT_MASK (0xf << 7) 6329#define VID_MODE_NOT_SUPPORTED (0 << 7) 6330#define VID_MODE_FORMAT_RGB565 (1 << 7) 6331#define VID_MODE_FORMAT_RGB666 (2 << 7) 6332#define VID_MODE_FORMAT_RGB666_LOOSE (3 << 7) 6333#define VID_MODE_FORMAT_RGB888 (4 << 7) 6334#define CMD_MODE_CHANNEL_NUMBER_SHIFT 5 6335#define CMD_MODE_CHANNEL_NUMBER_MASK (3 << 5) 6336#define VID_MODE_CHANNEL_NUMBER_SHIFT 3 6337#define VID_MODE_CHANNEL_NUMBER_MASK (3 << 3) 6338#define DATA_LANES_PRG_REG_SHIFT 0 6339#define DATA_LANES_PRG_REG_MASK (7 << 0) 6340 6341#define _MIPIA_HS_TX_TIMEOUT (dev_priv->mipi_mmio_base + 0xb010) 6342#define _MIPIB_HS_TX_TIMEOUT (dev_priv->mipi_mmio_base + 0xb810) 6343#define MIPI_HS_TX_TIMEOUT(tc) _TRANSCODER(tc, _MIPIA_HS_TX_TIMEOUT, \ 6344 _MIPIB_HS_TX_TIMEOUT) 6345#define HIGH_SPEED_TX_TIMEOUT_COUNTER_MASK 0xffffff 6346 6347#define _MIPIA_LP_RX_TIMEOUT (dev_priv->mipi_mmio_base + 0xb014) 6348#define _MIPIB_LP_RX_TIMEOUT (dev_priv->mipi_mmio_base + 0xb814) 6349#define MIPI_LP_RX_TIMEOUT(tc) _TRANSCODER(tc, _MIPIA_LP_RX_TIMEOUT, \ 6350 _MIPIB_LP_RX_TIMEOUT) 6351#define LOW_POWER_RX_TIMEOUT_COUNTER_MASK 0xffffff 6352 6353#define _MIPIA_TURN_AROUND_TIMEOUT (dev_priv->mipi_mmio_base + 0xb018) 6354#define _MIPIB_TURN_AROUND_TIMEOUT (dev_priv->mipi_mmio_base + 0xb818) 6355#define MIPI_TURN_AROUND_TIMEOUT(tc) _TRANSCODER(tc, \ 6356 _MIPIA_TURN_AROUND_TIMEOUT, _MIPIB_TURN_AROUND_TIMEOUT) 6357#define TURN_AROUND_TIMEOUT_MASK 0x3f 6358 6359#define _MIPIA_DEVICE_RESET_TIMER (dev_priv->mipi_mmio_base + 0xb01c) 6360#define _MIPIB_DEVICE_RESET_TIMER (dev_priv->mipi_mmio_base + 0xb81c) 6361#define MIPI_DEVICE_RESET_TIMER(tc) _TRANSCODER(tc, \ 6362 _MIPIA_DEVICE_RESET_TIMER, _MIPIB_DEVICE_RESET_TIMER) 6363#define DEVICE_RESET_TIMER_MASK 0xffff 6364 6365#define _MIPIA_DPI_RESOLUTION (dev_priv->mipi_mmio_base + 0xb020) 6366#define _MIPIB_DPI_RESOLUTION (dev_priv->mipi_mmio_base + 0xb820) 6367#define MIPI_DPI_RESOLUTION(tc) _TRANSCODER(tc, _MIPIA_DPI_RESOLUTION, \ 6368 _MIPIB_DPI_RESOLUTION) 6369#define VERTICAL_ADDRESS_SHIFT 16 6370#define VERTICAL_ADDRESS_MASK (0xffff << 16) 6371#define HORIZONTAL_ADDRESS_SHIFT 0 6372#define HORIZONTAL_ADDRESS_MASK 0xffff 6373 6374#define _MIPIA_DBI_FIFO_THROTTLE (dev_priv->mipi_mmio_base + 0xb024) 6375#define _MIPIB_DBI_FIFO_THROTTLE (dev_priv->mipi_mmio_base + 0xb824) 6376#define MIPI_DBI_FIFO_THROTTLE(tc) _TRANSCODER(tc, \ 6377 _MIPIA_DBI_FIFO_THROTTLE, _MIPIB_DBI_FIFO_THROTTLE) 6378#define DBI_FIFO_EMPTY_HALF (0 << 0) 6379#define DBI_FIFO_EMPTY_QUARTER (1 << 0) 6380#define DBI_FIFO_EMPTY_7_LOCATIONS (2 << 0) 6381 6382/* regs below are bits 15:0 */ 6383#define _MIPIA_HSYNC_PADDING_COUNT (dev_priv->mipi_mmio_base + 0xb028) 6384#define _MIPIB_HSYNC_PADDING_COUNT (dev_priv->mipi_mmio_base + 0xb828) 6385#define MIPI_HSYNC_PADDING_COUNT(tc) _TRANSCODER(tc, \ 6386 _MIPIA_HSYNC_PADDING_COUNT, _MIPIB_HSYNC_PADDING_COUNT) 6387 6388#define _MIPIA_HBP_COUNT (dev_priv->mipi_mmio_base + 0xb02c) 6389#define _MIPIB_HBP_COUNT (dev_priv->mipi_mmio_base + 0xb82c) 6390#define MIPI_HBP_COUNT(tc) _TRANSCODER(tc, _MIPIA_HBP_COUNT, \ 6391 _MIPIB_HBP_COUNT) 6392 6393#define _MIPIA_HFP_COUNT (dev_priv->mipi_mmio_base + 0xb030) 6394#define _MIPIB_HFP_COUNT (dev_priv->mipi_mmio_base + 0xb830) 6395#define MIPI_HFP_COUNT(tc) _TRANSCODER(tc, _MIPIA_HFP_COUNT, \ 6396 _MIPIB_HFP_COUNT) 6397 6398#define _MIPIA_HACTIVE_AREA_COUNT (dev_priv->mipi_mmio_base + 0xb034) 6399#define _MIPIB_HACTIVE_AREA_COUNT (dev_priv->mipi_mmio_base + 0xb834) 6400#define MIPI_HACTIVE_AREA_COUNT(tc) _TRANSCODER(tc, \ 6401 _MIPIA_HACTIVE_AREA_COUNT, _MIPIB_HACTIVE_AREA_COUNT) 6402 6403#define _MIPIA_VSYNC_PADDING_COUNT (dev_priv->mipi_mmio_base + 0xb038) 6404#define _MIPIB_VSYNC_PADDING_COUNT (dev_priv->mipi_mmio_base + 0xb838) 6405#define MIPI_VSYNC_PADDING_COUNT(tc) _TRANSCODER(tc, \ 6406 _MIPIA_VSYNC_PADDING_COUNT, _MIPIB_VSYNC_PADDING_COUNT) 6407 6408#define _MIPIA_VBP_COUNT (dev_priv->mipi_mmio_base + 0xb03c) 6409#define _MIPIB_VBP_COUNT (dev_priv->mipi_mmio_base + 0xb83c) 6410#define MIPI_VBP_COUNT(tc) _TRANSCODER(tc, _MIPIA_VBP_COUNT, \ 6411 _MIPIB_VBP_COUNT) 6412 6413#define _MIPIA_VFP_COUNT (dev_priv->mipi_mmio_base + 0xb040) 6414#define _MIPIB_VFP_COUNT (dev_priv->mipi_mmio_base + 0xb840) 6415#define MIPI_VFP_COUNT(tc) _TRANSCODER(tc, _MIPIA_VFP_COUNT, \ 6416 _MIPIB_VFP_COUNT) 6417 6418#define _MIPIA_HIGH_LOW_SWITCH_COUNT (dev_priv->mipi_mmio_base + 0xb044) 6419#define _MIPIB_HIGH_LOW_SWITCH_COUNT (dev_priv->mipi_mmio_base + 0xb844) 6420#define MIPI_HIGH_LOW_SWITCH_COUNT(tc) _TRANSCODER(tc, \ 6421 _MIPIA_HIGH_LOW_SWITCH_COUNT, _MIPIB_HIGH_LOW_SWITCH_COUNT) 6422 6423/* regs above are bits 15:0 */ 6424 6425#define _MIPIA_DPI_CONTROL (dev_priv->mipi_mmio_base + 0xb048) 6426#define _MIPIB_DPI_CONTROL (dev_priv->mipi_mmio_base + 0xb848) 6427#define MIPI_DPI_CONTROL(tc) _TRANSCODER(tc, _MIPIA_DPI_CONTROL, \ 6428 _MIPIB_DPI_CONTROL) 6429#define DPI_LP_MODE (1 << 6) 6430#define BACKLIGHT_OFF (1 << 5) 6431#define BACKLIGHT_ON (1 << 4) 6432#define COLOR_MODE_OFF (1 << 3) 6433#define COLOR_MODE_ON (1 << 2) 6434#define TURN_ON (1 << 1) 6435#define SHUTDOWN (1 << 0) 6436 6437#define _MIPIA_DPI_DATA (dev_priv->mipi_mmio_base + 0xb04c) 6438#define _MIPIB_DPI_DATA (dev_priv->mipi_mmio_base + 0xb84c) 6439#define MIPI_DPI_DATA(tc) _TRANSCODER(tc, _MIPIA_DPI_DATA, \ 6440 _MIPIB_DPI_DATA) 6441#define COMMAND_BYTE_SHIFT 0 6442#define COMMAND_BYTE_MASK (0x3f << 0) 6443 6444#define _MIPIA_INIT_COUNT (dev_priv->mipi_mmio_base + 0xb050) 6445#define _MIPIB_INIT_COUNT (dev_priv->mipi_mmio_base + 0xb850) 6446#define MIPI_INIT_COUNT(tc) _TRANSCODER(tc, _MIPIA_INIT_COUNT, \ 6447 _MIPIB_INIT_COUNT) 6448#define MASTER_INIT_TIMER_SHIFT 0 6449#define MASTER_INIT_TIMER_MASK (0xffff << 0) 6450 6451#define _MIPIA_MAX_RETURN_PKT_SIZE (dev_priv->mipi_mmio_base + 0xb054) 6452#define _MIPIB_MAX_RETURN_PKT_SIZE (dev_priv->mipi_mmio_base + 0xb854) 6453#define MIPI_MAX_RETURN_PKT_SIZE(tc) _TRANSCODER(tc, \ 6454 _MIPIA_MAX_RETURN_PKT_SIZE, _MIPIB_MAX_RETURN_PKT_SIZE) 6455#define MAX_RETURN_PKT_SIZE_SHIFT 0 6456#define MAX_RETURN_PKT_SIZE_MASK (0x3ff << 0) 6457 6458#define _MIPIA_VIDEO_MODE_FORMAT (dev_priv->mipi_mmio_base + 0xb058) 6459#define _MIPIB_VIDEO_MODE_FORMAT (dev_priv->mipi_mmio_base + 0xb858) 6460#define MIPI_VIDEO_MODE_FORMAT(tc) _TRANSCODER(tc, \ 6461 _MIPIA_VIDEO_MODE_FORMAT, _MIPIB_VIDEO_MODE_FORMAT) 6462#define RANDOM_DPI_DISPLAY_RESOLUTION (1 << 4) 6463#define DISABLE_VIDEO_BTA (1 << 3) 6464#define IP_TG_CONFIG (1 << 2) 6465#define VIDEO_MODE_NON_BURST_WITH_SYNC_PULSE (1 << 0) 6466#define VIDEO_MODE_NON_BURST_WITH_SYNC_EVENTS (2 << 0) 6467#define VIDEO_MODE_BURST (3 << 0) 6468 6469#define _MIPIA_EOT_DISABLE (dev_priv->mipi_mmio_base + 0xb05c) 6470#define _MIPIB_EOT_DISABLE (dev_priv->mipi_mmio_base + 0xb85c) 6471#define MIPI_EOT_DISABLE(tc) _TRANSCODER(tc, _MIPIA_EOT_DISABLE, \ 6472 _MIPIB_EOT_DISABLE) 6473#define LP_RX_TIMEOUT_ERROR_RECOVERY_DISABLE (1 << 7) 6474#define HS_RX_TIMEOUT_ERROR_RECOVERY_DISABLE (1 << 6) 6475#define LOW_CONTENTION_RECOVERY_DISABLE (1 << 5) 6476#define HIGH_CONTENTION_RECOVERY_DISABLE (1 << 4) 6477#define TXDSI_TYPE_NOT_RECOGNISED_ERROR_RECOVERY_DISABLE (1 << 3) 6478#define TXECC_MULTIBIT_ERROR_RECOVERY_DISABLE (1 << 2) 6479#define CLOCKSTOP (1 << 1) 6480#define EOT_DISABLE (1 << 0) 6481 6482#define _MIPIA_LP_BYTECLK (dev_priv->mipi_mmio_base + 0xb060) 6483#define _MIPIB_LP_BYTECLK (dev_priv->mipi_mmio_base + 0xb860) 6484#define MIPI_LP_BYTECLK(tc) _TRANSCODER(tc, _MIPIA_LP_BYTECLK, \ 6485 _MIPIB_LP_BYTECLK) 6486#define LP_BYTECLK_SHIFT 0 6487#define LP_BYTECLK_MASK (0xffff << 0) 6488 6489/* bits 31:0 */ 6490#define _MIPIA_LP_GEN_DATA (dev_priv->mipi_mmio_base + 0xb064) 6491#define _MIPIB_LP_GEN_DATA (dev_priv->mipi_mmio_base + 0xb864) 6492#define MIPI_LP_GEN_DATA(tc) _TRANSCODER(tc, _MIPIA_LP_GEN_DATA, \ 6493 _MIPIB_LP_GEN_DATA) 6494 6495/* bits 31:0 */ 6496#define _MIPIA_HS_GEN_DATA (dev_priv->mipi_mmio_base + 0xb068) 6497#define _MIPIB_HS_GEN_DATA (dev_priv->mipi_mmio_base + 0xb868) 6498#define MIPI_HS_GEN_DATA(tc) _TRANSCODER(tc, _MIPIA_HS_GEN_DATA, \ 6499 _MIPIB_HS_GEN_DATA) 6500 6501#define _MIPIA_LP_GEN_CTRL (dev_priv->mipi_mmio_base + 0xb06c) 6502#define _MIPIB_LP_GEN_CTRL (dev_priv->mipi_mmio_base + 0xb86c) 6503#define MIPI_LP_GEN_CTRL(tc) _TRANSCODER(tc, _MIPIA_LP_GEN_CTRL, \ 6504 _MIPIB_LP_GEN_CTRL) 6505#define _MIPIA_HS_GEN_CTRL (dev_priv->mipi_mmio_base + 0xb070) 6506#define _MIPIB_HS_GEN_CTRL (dev_priv->mipi_mmio_base + 0xb870) 6507#define MIPI_HS_GEN_CTRL(tc) _TRANSCODER(tc, _MIPIA_HS_GEN_CTRL, \ 6508 _MIPIB_HS_GEN_CTRL) 6509#define LONG_PACKET_WORD_COUNT_SHIFT 8 6510#define LONG_PACKET_WORD_COUNT_MASK (0xffff << 8) 6511#define SHORT_PACKET_PARAM_SHIFT 8 6512#define SHORT_PACKET_PARAM_MASK (0xffff << 8) 6513#define VIRTUAL_CHANNEL_SHIFT 6 6514#define VIRTUAL_CHANNEL_MASK (3 << 6) 6515#define DATA_TYPE_SHIFT 0 6516#define DATA_TYPE_MASK (3f << 0) 6517/* data type values, see include/video/mipi_display.h */ 6518 6519#define _MIPIA_GEN_FIFO_STAT (dev_priv->mipi_mmio_base + 0xb074) 6520#define _MIPIB_GEN_FIFO_STAT (dev_priv->mipi_mmio_base + 0xb874) 6521#define MIPI_GEN_FIFO_STAT(tc) _TRANSCODER(tc, _MIPIA_GEN_FIFO_STAT, \ 6522 _MIPIB_GEN_FIFO_STAT) 6523#define DPI_FIFO_EMPTY (1 << 28) 6524#define DBI_FIFO_EMPTY (1 << 27) 6525#define LP_CTRL_FIFO_EMPTY (1 << 26) 6526#define LP_CTRL_FIFO_HALF_EMPTY (1 << 25) 6527#define LP_CTRL_FIFO_FULL (1 << 24) 6528#define HS_CTRL_FIFO_EMPTY (1 << 18) 6529#define HS_CTRL_FIFO_HALF_EMPTY (1 << 17) 6530#define HS_CTRL_FIFO_FULL (1 << 16) 6531#define LP_DATA_FIFO_EMPTY (1 << 10) 6532#define LP_DATA_FIFO_HALF_EMPTY (1 << 9) 6533#define LP_DATA_FIFO_FULL (1 << 8) 6534#define HS_DATA_FIFO_EMPTY (1 << 2) 6535#define HS_DATA_FIFO_HALF_EMPTY (1 << 1) 6536#define HS_DATA_FIFO_FULL (1 << 0) 6537 6538#define _MIPIA_HS_LS_DBI_ENABLE (dev_priv->mipi_mmio_base + 0xb078) 6539#define _MIPIB_HS_LS_DBI_ENABLE (dev_priv->mipi_mmio_base + 0xb878) 6540#define MIPI_HS_LP_DBI_ENABLE(tc) _TRANSCODER(tc, \ 6541 _MIPIA_HS_LS_DBI_ENABLE, _MIPIB_HS_LS_DBI_ENABLE) 6542#define DBI_HS_LP_MODE_MASK (1 << 0) 6543#define DBI_LP_MODE (1 << 0) 6544#define DBI_HS_MODE (0 << 0) 6545 6546#define _MIPIA_DPHY_PARAM (dev_priv->mipi_mmio_base + 0xb080) 6547#define _MIPIB_DPHY_PARAM (dev_priv->mipi_mmio_base + 0xb880) 6548#define MIPI_DPHY_PARAM(tc) _TRANSCODER(tc, _MIPIA_DPHY_PARAM, \ 6549 _MIPIB_DPHY_PARAM) 6550#define EXIT_ZERO_COUNT_SHIFT 24 6551#define EXIT_ZERO_COUNT_MASK (0x3f << 24) 6552#define TRAIL_COUNT_SHIFT 16 6553#define TRAIL_COUNT_MASK (0x1f << 16) 6554#define CLK_ZERO_COUNT_SHIFT 8 6555#define CLK_ZERO_COUNT_MASK (0xff << 8) 6556#define PREPARE_COUNT_SHIFT 0 6557#define PREPARE_COUNT_MASK (0x3f << 0) 6558 6559/* bits 31:0 */ 6560#define _MIPIA_DBI_BW_CTRL (dev_priv->mipi_mmio_base + 0xb084) 6561#define _MIPIB_DBI_BW_CTRL (dev_priv->mipi_mmio_base + 0xb884) 6562#define MIPI_DBI_BW_CTRL(tc) _TRANSCODER(tc, _MIPIA_DBI_BW_CTRL, \ 6563 _MIPIB_DBI_BW_CTRL) 6564 6565#define _MIPIA_CLK_LANE_SWITCH_TIME_CNT (dev_priv->mipi_mmio_base \ 6566 + 0xb088) 6567#define _MIPIB_CLK_LANE_SWITCH_TIME_CNT (dev_priv->mipi_mmio_base \ 6568 + 0xb888) 6569#define MIPI_CLK_LANE_SWITCH_TIME_CNT(tc) _TRANSCODER(tc, \ 6570 _MIPIA_CLK_LANE_SWITCH_TIME_CNT, _MIPIB_CLK_LANE_SWITCH_TIME_CNT) 6571#define LP_HS_SSW_CNT_SHIFT 16 6572#define LP_HS_SSW_CNT_MASK (0xffff << 16) 6573#define HS_LP_PWR_SW_CNT_SHIFT 0 6574#define HS_LP_PWR_SW_CNT_MASK (0xffff << 0) 6575 6576#define _MIPIA_STOP_STATE_STALL (dev_priv->mipi_mmio_base + 0xb08c) 6577#define _MIPIB_STOP_STATE_STALL (dev_priv->mipi_mmio_base + 0xb88c) 6578#define MIPI_STOP_STATE_STALL(tc) _TRANSCODER(tc, \ 6579 _MIPIA_STOP_STATE_STALL, _MIPIB_STOP_STATE_STALL) 6580#define STOP_STATE_STALL_COUNTER_SHIFT 0 6581#define STOP_STATE_STALL_COUNTER_MASK (0xff << 0) 6582 6583#define _MIPIA_INTR_STAT_REG_1 (dev_priv->mipi_mmio_base + 0xb090) 6584#define _MIPIB_INTR_STAT_REG_1 (dev_priv->mipi_mmio_base + 0xb890) 6585#define MIPI_INTR_STAT_REG_1(tc) _TRANSCODER(tc, \ 6586 _MIPIA_INTR_STAT_REG_1, _MIPIB_INTR_STAT_REG_1) 6587#define _MIPIA_INTR_EN_REG_1 (dev_priv->mipi_mmio_base + 0xb094) 6588#define _MIPIB_INTR_EN_REG_1 (dev_priv->mipi_mmio_base + 0xb894) 6589#define MIPI_INTR_EN_REG_1(tc) _TRANSCODER(tc, _MIPIA_INTR_EN_REG_1, \ 6590 _MIPIB_INTR_EN_REG_1) 6591#define RX_CONTENTION_DETECTED (1 << 0) 6592 6593/* XXX: only pipe A ?!? */ 6594#define MIPIA_DBI_TYPEC_CTRL (dev_priv->mipi_mmio_base + 0xb100) 6595#define DBI_TYPEC_ENABLE (1 << 31) 6596#define DBI_TYPEC_WIP (1 << 30) 6597#define DBI_TYPEC_OPTION_SHIFT 28 6598#define DBI_TYPEC_OPTION_MASK (3 << 28) 6599#define DBI_TYPEC_FREQ_SHIFT 24 6600#define DBI_TYPEC_FREQ_MASK (0xf << 24) 6601#define DBI_TYPEC_OVERRIDE (1 << 8) 6602#define DBI_TYPEC_OVERRIDE_COUNTER_SHIFT 0 6603#define DBI_TYPEC_OVERRIDE_COUNTER_MASK (0xff << 0) 6604 6605 6606/* MIPI adapter registers */ 6607 6608#define _MIPIA_CTRL (dev_priv->mipi_mmio_base + 0xb104) 6609#define _MIPIB_CTRL (dev_priv->mipi_mmio_base + 0xb904) 6610#define MIPI_CTRL(tc) _TRANSCODER(tc, _MIPIA_CTRL, \ 6611 _MIPIB_CTRL) 6612#define ESCAPE_CLOCK_DIVIDER_SHIFT 5 /* A only */ 6613#define ESCAPE_CLOCK_DIVIDER_MASK (3 << 5) 6614#define ESCAPE_CLOCK_DIVIDER_1 (0 << 5) 6615#define ESCAPE_CLOCK_DIVIDER_2 (1 << 5) 6616#define ESCAPE_CLOCK_DIVIDER_4 (2 << 5) 6617#define READ_REQUEST_PRIORITY_SHIFT 3 6618#define READ_REQUEST_PRIORITY_MASK (3 << 3) 6619#define READ_REQUEST_PRIORITY_LOW (0 << 3) 6620#define READ_REQUEST_PRIORITY_HIGH (3 << 3) 6621#define RGB_FLIP_TO_BGR (1 << 2) 6622 6623#define _MIPIA_DATA_ADDRESS (dev_priv->mipi_mmio_base + 0xb108) 6624#define _MIPIB_DATA_ADDRESS (dev_priv->mipi_mmio_base + 0xb908) 6625#define MIPI_DATA_ADDRESS(tc) _TRANSCODER(tc, _MIPIA_DATA_ADDRESS, \ 6626 _MIPIB_DATA_ADDRESS) 6627#define DATA_MEM_ADDRESS_SHIFT 5 6628#define DATA_MEM_ADDRESS_MASK (0x7ffffff << 5) 6629#define DATA_VALID (1 << 0) 6630 6631#define _MIPIA_DATA_LENGTH (dev_priv->mipi_mmio_base + 0xb10c) 6632#define _MIPIB_DATA_LENGTH (dev_priv->mipi_mmio_base + 0xb90c) 6633#define MIPI_DATA_LENGTH(tc) _TRANSCODER(tc, _MIPIA_DATA_LENGTH, \ 6634 _MIPIB_DATA_LENGTH) 6635#define DATA_LENGTH_SHIFT 0 6636#define DATA_LENGTH_MASK (0xfffff << 0) 6637 6638#define _MIPIA_COMMAND_ADDRESS (dev_priv->mipi_mmio_base + 0xb110) 6639#define _MIPIB_COMMAND_ADDRESS (dev_priv->mipi_mmio_base + 0xb910) 6640#define MIPI_COMMAND_ADDRESS(tc) _TRANSCODER(tc, \ 6641 _MIPIA_COMMAND_ADDRESS, _MIPIB_COMMAND_ADDRESS) 6642#define COMMAND_MEM_ADDRESS_SHIFT 5 6643#define COMMAND_MEM_ADDRESS_MASK (0x7ffffff << 5) 6644#define AUTO_PWG_ENABLE (1 << 2) 6645#define MEMORY_WRITE_DATA_FROM_PIPE_RENDERING (1 << 1) 6646#define COMMAND_VALID (1 << 0) 6647 6648#define _MIPIA_COMMAND_LENGTH (dev_priv->mipi_mmio_base + 0xb114) 6649#define _MIPIB_COMMAND_LENGTH (dev_priv->mipi_mmio_base + 0xb914) 6650#define MIPI_COMMAND_LENGTH(tc) _TRANSCODER(tc, _MIPIA_COMMAND_LENGTH, \ 6651 _MIPIB_COMMAND_LENGTH) 6652#define COMMAND_LENGTH_SHIFT(n) (8 * (n)) /* n: 0...3 */ 6653#define COMMAND_LENGTH_MASK(n) (0xff << (8 * (n))) 6654 6655#define _MIPIA_READ_DATA_RETURN0 (dev_priv->mipi_mmio_base + 0xb118) 6656#define _MIPIB_READ_DATA_RETURN0 (dev_priv->mipi_mmio_base + 0xb918) 6657#define MIPI_READ_DATA_RETURN(tc, n) \ 6658 (_TRANSCODER(tc, _MIPIA_READ_DATA_RETURN0, _MIPIB_READ_DATA_RETURN0) \ 6659 + 4 * (n)) /* n: 0...7 */ 6660 6661#define _MIPIA_READ_DATA_VALID (dev_priv->mipi_mmio_base + 0xb138) 6662#define _MIPIB_READ_DATA_VALID (dev_priv->mipi_mmio_base + 0xb938) 6663#define MIPI_READ_DATA_VALID(tc) _TRANSCODER(tc, \ 6664 _MIPIA_READ_DATA_VALID, _MIPIB_READ_DATA_VALID) 6665#define READ_DATA_VALID(n) (1 << (n)) 6666 6667/* For UMS only (deprecated): */ 6668#define _PALETTE_A (dev_priv->info.display_mmio_offset + 0xa000) 6669#define _PALETTE_B (dev_priv->info.display_mmio_offset + 0xa800) 6670 6671#endif /* _I915_REG_H_ */ 6672