intel_dp.c revision 0e50338cf0f0009a5c9bc847a4c86a1d4438af66
1/* 2 * Copyright © 2008 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 * Authors: 24 * Keith Packard <keithp@keithp.com> 25 * 26 */ 27 28#include <linux/i2c.h> 29#include <linux/slab.h> 30#include <linux/export.h> 31#include <drm/drmP.h> 32#include <drm/drm_crtc.h> 33#include <drm/drm_crtc_helper.h> 34#include <drm/drm_edid.h> 35#include "intel_drv.h" 36#include <drm/i915_drm.h> 37#include "i915_drv.h" 38 39#define DP_LINK_CHECK_TIMEOUT (10 * 1000) 40 41struct dp_link_dpll { 42 int link_bw; 43 struct dpll dpll; 44}; 45 46static const struct dp_link_dpll gen4_dpll[] = { 47 { DP_LINK_BW_1_62, 48 { .p1 = 2, .p2 = 10, .n = 2, .m1 = 23, .m2 = 8 } }, 49 { DP_LINK_BW_2_7, 50 { .p1 = 1, .p2 = 10, .n = 1, .m1 = 14, .m2 = 2 } } 51}; 52 53static const struct dp_link_dpll pch_dpll[] = { 54 { DP_LINK_BW_1_62, 55 { .p1 = 2, .p2 = 10, .n = 1, .m1 = 12, .m2 = 9 } }, 56 { DP_LINK_BW_2_7, 57 { .p1 = 1, .p2 = 10, .n = 2, .m1 = 14, .m2 = 8 } } 58}; 59 60static const struct dp_link_dpll vlv_dpll[] = { 61 { DP_LINK_BW_1_62, 62 { .p1 = 3, .p2 = 2, .n = 5, .m1 = 3, .m2 = 81 } }, 63 { DP_LINK_BW_2_7, 64 { .p1 = 2, .p2 = 2, .n = 1, .m1 = 2, .m2 = 27 } } 65}; 66 67/* 68 * CHV supports eDP 1.4 that have more link rates. 69 * Below only provides the fixed rate but exclude variable rate. 70 */ 71static const struct dp_link_dpll chv_dpll[] = { 72 /* 73 * CHV requires to program fractional division for m2. 74 * m2 is stored in fixed point format using formula below 75 * (m2_int << 22) | m2_fraction 76 */ 77 { DP_LINK_BW_1_62, /* m2_int = 32, m2_fraction = 1677722 */ 78 { .p1 = 4, .p2 = 2, .n = 1, .m1 = 2, .m2 = 0x819999a } }, 79 { DP_LINK_BW_2_7, /* m2_int = 27, m2_fraction = 0 */ 80 { .p1 = 4, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } }, 81 { DP_LINK_BW_5_4, /* m2_int = 27, m2_fraction = 0 */ 82 { .p1 = 2, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } } 83}; 84 85/** 86 * is_edp - is the given port attached to an eDP panel (either CPU or PCH) 87 * @intel_dp: DP struct 88 * 89 * If a CPU or PCH DP output is attached to an eDP panel, this function 90 * will return true, and false otherwise. 91 */ 92static bool is_edp(struct intel_dp *intel_dp) 93{ 94 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 95 96 return intel_dig_port->base.type == INTEL_OUTPUT_EDP; 97} 98 99static struct drm_device *intel_dp_to_dev(struct intel_dp *intel_dp) 100{ 101 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 102 103 return intel_dig_port->base.base.dev; 104} 105 106static struct intel_dp *intel_attached_dp(struct drm_connector *connector) 107{ 108 return enc_to_intel_dp(&intel_attached_encoder(connector)->base); 109} 110 111static void intel_dp_link_down(struct intel_dp *intel_dp); 112static bool _edp_panel_vdd_on(struct intel_dp *intel_dp); 113static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync); 114 115static int 116intel_dp_max_link_bw(struct intel_dp *intel_dp) 117{ 118 int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE]; 119 struct drm_device *dev = intel_dp->attached_connector->base.dev; 120 121 switch (max_link_bw) { 122 case DP_LINK_BW_1_62: 123 case DP_LINK_BW_2_7: 124 break; 125 case DP_LINK_BW_5_4: /* 1.2 capable displays may advertise higher bw */ 126 if (((IS_HASWELL(dev) && !IS_HSW_ULX(dev)) || 127 INTEL_INFO(dev)->gen >= 8) && 128 intel_dp->dpcd[DP_DPCD_REV] >= 0x12) 129 max_link_bw = DP_LINK_BW_5_4; 130 else 131 max_link_bw = DP_LINK_BW_2_7; 132 break; 133 default: 134 WARN(1, "invalid max DP link bw val %x, using 1.62Gbps\n", 135 max_link_bw); 136 max_link_bw = DP_LINK_BW_1_62; 137 break; 138 } 139 return max_link_bw; 140} 141 142static u8 intel_dp_max_lane_count(struct intel_dp *intel_dp) 143{ 144 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 145 struct drm_device *dev = intel_dig_port->base.base.dev; 146 u8 source_max, sink_max; 147 148 source_max = 4; 149 if (HAS_DDI(dev) && intel_dig_port->port == PORT_A && 150 (intel_dig_port->saved_port_bits & DDI_A_4_LANES) == 0) 151 source_max = 2; 152 153 sink_max = drm_dp_max_lane_count(intel_dp->dpcd); 154 155 return min(source_max, sink_max); 156} 157 158/* 159 * The units on the numbers in the next two are... bizarre. Examples will 160 * make it clearer; this one parallels an example in the eDP spec. 161 * 162 * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as: 163 * 164 * 270000 * 1 * 8 / 10 == 216000 165 * 166 * The actual data capacity of that configuration is 2.16Gbit/s, so the 167 * units are decakilobits. ->clock in a drm_display_mode is in kilohertz - 168 * or equivalently, kilopixels per second - so for 1680x1050R it'd be 169 * 119000. At 18bpp that's 2142000 kilobits per second. 170 * 171 * Thus the strange-looking division by 10 in intel_dp_link_required, to 172 * get the result in decakilobits instead of kilobits. 173 */ 174 175static int 176intel_dp_link_required(int pixel_clock, int bpp) 177{ 178 return (pixel_clock * bpp + 9) / 10; 179} 180 181static int 182intel_dp_max_data_rate(int max_link_clock, int max_lanes) 183{ 184 return (max_link_clock * max_lanes * 8) / 10; 185} 186 187static enum drm_mode_status 188intel_dp_mode_valid(struct drm_connector *connector, 189 struct drm_display_mode *mode) 190{ 191 struct intel_dp *intel_dp = intel_attached_dp(connector); 192 struct intel_connector *intel_connector = to_intel_connector(connector); 193 struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode; 194 int target_clock = mode->clock; 195 int max_rate, mode_rate, max_lanes, max_link_clock; 196 197 if (is_edp(intel_dp) && fixed_mode) { 198 if (mode->hdisplay > fixed_mode->hdisplay) 199 return MODE_PANEL; 200 201 if (mode->vdisplay > fixed_mode->vdisplay) 202 return MODE_PANEL; 203 204 target_clock = fixed_mode->clock; 205 } 206 207 max_link_clock = drm_dp_bw_code_to_link_rate(intel_dp_max_link_bw(intel_dp)); 208 max_lanes = intel_dp_max_lane_count(intel_dp); 209 210 max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes); 211 mode_rate = intel_dp_link_required(target_clock, 18); 212 213 if (mode_rate > max_rate) 214 return MODE_CLOCK_HIGH; 215 216 if (mode->clock < 10000) 217 return MODE_CLOCK_LOW; 218 219 if (mode->flags & DRM_MODE_FLAG_DBLCLK) 220 return MODE_H_ILLEGAL; 221 222 return MODE_OK; 223} 224 225static uint32_t 226pack_aux(uint8_t *src, int src_bytes) 227{ 228 int i; 229 uint32_t v = 0; 230 231 if (src_bytes > 4) 232 src_bytes = 4; 233 for (i = 0; i < src_bytes; i++) 234 v |= ((uint32_t) src[i]) << ((3-i) * 8); 235 return v; 236} 237 238static void 239unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes) 240{ 241 int i; 242 if (dst_bytes > 4) 243 dst_bytes = 4; 244 for (i = 0; i < dst_bytes; i++) 245 dst[i] = src >> ((3-i) * 8); 246} 247 248/* hrawclock is 1/4 the FSB frequency */ 249static int 250intel_hrawclk(struct drm_device *dev) 251{ 252 struct drm_i915_private *dev_priv = dev->dev_private; 253 uint32_t clkcfg; 254 255 /* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */ 256 if (IS_VALLEYVIEW(dev)) 257 return 200; 258 259 clkcfg = I915_READ(CLKCFG); 260 switch (clkcfg & CLKCFG_FSB_MASK) { 261 case CLKCFG_FSB_400: 262 return 100; 263 case CLKCFG_FSB_533: 264 return 133; 265 case CLKCFG_FSB_667: 266 return 166; 267 case CLKCFG_FSB_800: 268 return 200; 269 case CLKCFG_FSB_1067: 270 return 266; 271 case CLKCFG_FSB_1333: 272 return 333; 273 /* these two are just a guess; one of them might be right */ 274 case CLKCFG_FSB_1600: 275 case CLKCFG_FSB_1600_ALT: 276 return 400; 277 default: 278 return 133; 279 } 280} 281 282static void 283intel_dp_init_panel_power_sequencer(struct drm_device *dev, 284 struct intel_dp *intel_dp, 285 struct edp_power_seq *out); 286static void 287intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev, 288 struct intel_dp *intel_dp, 289 struct edp_power_seq *out); 290 291static enum pipe 292vlv_power_sequencer_pipe(struct intel_dp *intel_dp) 293{ 294 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 295 struct drm_crtc *crtc = intel_dig_port->base.base.crtc; 296 struct drm_device *dev = intel_dig_port->base.base.dev; 297 struct drm_i915_private *dev_priv = dev->dev_private; 298 enum port port = intel_dig_port->port; 299 enum pipe pipe; 300 301 /* modeset should have pipe */ 302 if (crtc) 303 return to_intel_crtc(crtc)->pipe; 304 305 /* init time, try to find a pipe with this port selected */ 306 for (pipe = PIPE_A; pipe <= PIPE_B; pipe++) { 307 u32 port_sel = I915_READ(VLV_PIPE_PP_ON_DELAYS(pipe)) & 308 PANEL_PORT_SELECT_MASK; 309 if (port_sel == PANEL_PORT_SELECT_DPB_VLV && port == PORT_B) 310 return pipe; 311 if (port_sel == PANEL_PORT_SELECT_DPC_VLV && port == PORT_C) 312 return pipe; 313 } 314 315 /* shrug */ 316 return PIPE_A; 317} 318 319static u32 _pp_ctrl_reg(struct intel_dp *intel_dp) 320{ 321 struct drm_device *dev = intel_dp_to_dev(intel_dp); 322 323 if (HAS_PCH_SPLIT(dev)) 324 return PCH_PP_CONTROL; 325 else 326 return VLV_PIPE_PP_CONTROL(vlv_power_sequencer_pipe(intel_dp)); 327} 328 329static u32 _pp_stat_reg(struct intel_dp *intel_dp) 330{ 331 struct drm_device *dev = intel_dp_to_dev(intel_dp); 332 333 if (HAS_PCH_SPLIT(dev)) 334 return PCH_PP_STATUS; 335 else 336 return VLV_PIPE_PP_STATUS(vlv_power_sequencer_pipe(intel_dp)); 337} 338 339static bool edp_have_panel_power(struct intel_dp *intel_dp) 340{ 341 struct drm_device *dev = intel_dp_to_dev(intel_dp); 342 struct drm_i915_private *dev_priv = dev->dev_private; 343 344 return (I915_READ(_pp_stat_reg(intel_dp)) & PP_ON) != 0; 345} 346 347static bool edp_have_panel_vdd(struct intel_dp *intel_dp) 348{ 349 struct drm_device *dev = intel_dp_to_dev(intel_dp); 350 struct drm_i915_private *dev_priv = dev->dev_private; 351 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 352 struct intel_encoder *intel_encoder = &intel_dig_port->base; 353 enum intel_display_power_domain power_domain; 354 355 power_domain = intel_display_port_power_domain(intel_encoder); 356 return intel_display_power_enabled(dev_priv, power_domain) && 357 (I915_READ(_pp_ctrl_reg(intel_dp)) & EDP_FORCE_VDD) != 0; 358} 359 360static void 361intel_dp_check_edp(struct intel_dp *intel_dp) 362{ 363 struct drm_device *dev = intel_dp_to_dev(intel_dp); 364 struct drm_i915_private *dev_priv = dev->dev_private; 365 366 if (!is_edp(intel_dp)) 367 return; 368 369 if (!edp_have_panel_power(intel_dp) && !edp_have_panel_vdd(intel_dp)) { 370 WARN(1, "eDP powered off while attempting aux channel communication.\n"); 371 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n", 372 I915_READ(_pp_stat_reg(intel_dp)), 373 I915_READ(_pp_ctrl_reg(intel_dp))); 374 } 375} 376 377static uint32_t 378intel_dp_aux_wait_done(struct intel_dp *intel_dp, bool has_aux_irq) 379{ 380 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 381 struct drm_device *dev = intel_dig_port->base.base.dev; 382 struct drm_i915_private *dev_priv = dev->dev_private; 383 uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg; 384 uint32_t status; 385 bool done; 386 387#define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0) 388 if (has_aux_irq) 389 done = wait_event_timeout(dev_priv->gmbus_wait_queue, C, 390 msecs_to_jiffies_timeout(10)); 391 else 392 done = wait_for_atomic(C, 10) == 0; 393 if (!done) 394 DRM_ERROR("dp aux hw did not signal timeout (has irq: %i)!\n", 395 has_aux_irq); 396#undef C 397 398 return status; 399} 400 401static uint32_t i9xx_get_aux_clock_divider(struct intel_dp *intel_dp, int index) 402{ 403 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 404 struct drm_device *dev = intel_dig_port->base.base.dev; 405 406 /* 407 * The clock divider is based off the hrawclk, and would like to run at 408 * 2MHz. So, take the hrawclk value and divide by 2 and use that 409 */ 410 return index ? 0 : intel_hrawclk(dev) / 2; 411} 412 413static uint32_t ilk_get_aux_clock_divider(struct intel_dp *intel_dp, int index) 414{ 415 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 416 struct drm_device *dev = intel_dig_port->base.base.dev; 417 418 if (index) 419 return 0; 420 421 if (intel_dig_port->port == PORT_A) { 422 if (IS_GEN6(dev) || IS_GEN7(dev)) 423 return 200; /* SNB & IVB eDP input clock at 400Mhz */ 424 else 425 return 225; /* eDP input clock at 450Mhz */ 426 } else { 427 return DIV_ROUND_UP(intel_pch_rawclk(dev), 2); 428 } 429} 430 431static uint32_t hsw_get_aux_clock_divider(struct intel_dp *intel_dp, int index) 432{ 433 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 434 struct drm_device *dev = intel_dig_port->base.base.dev; 435 struct drm_i915_private *dev_priv = dev->dev_private; 436 437 if (intel_dig_port->port == PORT_A) { 438 if (index) 439 return 0; 440 return DIV_ROUND_CLOSEST(intel_ddi_get_cdclk_freq(dev_priv), 2000); 441 } else if (dev_priv->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE) { 442 /* Workaround for non-ULT HSW */ 443 switch (index) { 444 case 0: return 63; 445 case 1: return 72; 446 default: return 0; 447 } 448 } else { 449 return index ? 0 : DIV_ROUND_UP(intel_pch_rawclk(dev), 2); 450 } 451} 452 453static uint32_t vlv_get_aux_clock_divider(struct intel_dp *intel_dp, int index) 454{ 455 return index ? 0 : 100; 456} 457 458static uint32_t i9xx_get_aux_send_ctl(struct intel_dp *intel_dp, 459 bool has_aux_irq, 460 int send_bytes, 461 uint32_t aux_clock_divider) 462{ 463 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 464 struct drm_device *dev = intel_dig_port->base.base.dev; 465 uint32_t precharge, timeout; 466 467 if (IS_GEN6(dev)) 468 precharge = 3; 469 else 470 precharge = 5; 471 472 if (IS_BROADWELL(dev) && intel_dp->aux_ch_ctl_reg == DPA_AUX_CH_CTL) 473 timeout = DP_AUX_CH_CTL_TIME_OUT_600us; 474 else 475 timeout = DP_AUX_CH_CTL_TIME_OUT_400us; 476 477 return DP_AUX_CH_CTL_SEND_BUSY | 478 DP_AUX_CH_CTL_DONE | 479 (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) | 480 DP_AUX_CH_CTL_TIME_OUT_ERROR | 481 timeout | 482 DP_AUX_CH_CTL_RECEIVE_ERROR | 483 (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) | 484 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) | 485 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT); 486} 487 488static int 489intel_dp_aux_ch(struct intel_dp *intel_dp, 490 uint8_t *send, int send_bytes, 491 uint8_t *recv, int recv_size) 492{ 493 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 494 struct drm_device *dev = intel_dig_port->base.base.dev; 495 struct drm_i915_private *dev_priv = dev->dev_private; 496 uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg; 497 uint32_t ch_data = ch_ctl + 4; 498 uint32_t aux_clock_divider; 499 int i, ret, recv_bytes; 500 uint32_t status; 501 int try, clock = 0; 502 bool has_aux_irq = HAS_AUX_IRQ(dev); 503 bool vdd; 504 505 vdd = _edp_panel_vdd_on(intel_dp); 506 507 /* dp aux is extremely sensitive to irq latency, hence request the 508 * lowest possible wakeup latency and so prevent the cpu from going into 509 * deep sleep states. 510 */ 511 pm_qos_update_request(&dev_priv->pm_qos, 0); 512 513 intel_dp_check_edp(intel_dp); 514 515 intel_aux_display_runtime_get(dev_priv); 516 517 /* Try to wait for any previous AUX channel activity */ 518 for (try = 0; try < 3; try++) { 519 status = I915_READ_NOTRACE(ch_ctl); 520 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0) 521 break; 522 msleep(1); 523 } 524 525 if (try == 3) { 526 WARN(1, "dp_aux_ch not started status 0x%08x\n", 527 I915_READ(ch_ctl)); 528 ret = -EBUSY; 529 goto out; 530 } 531 532 /* Only 5 data registers! */ 533 if (WARN_ON(send_bytes > 20 || recv_size > 20)) { 534 ret = -E2BIG; 535 goto out; 536 } 537 538 while ((aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, clock++))) { 539 u32 send_ctl = intel_dp->get_aux_send_ctl(intel_dp, 540 has_aux_irq, 541 send_bytes, 542 aux_clock_divider); 543 544 /* Must try at least 3 times according to DP spec */ 545 for (try = 0; try < 5; try++) { 546 /* Load the send data into the aux channel data registers */ 547 for (i = 0; i < send_bytes; i += 4) 548 I915_WRITE(ch_data + i, 549 pack_aux(send + i, send_bytes - i)); 550 551 /* Send the command and wait for it to complete */ 552 I915_WRITE(ch_ctl, send_ctl); 553 554 status = intel_dp_aux_wait_done(intel_dp, has_aux_irq); 555 556 /* Clear done status and any errors */ 557 I915_WRITE(ch_ctl, 558 status | 559 DP_AUX_CH_CTL_DONE | 560 DP_AUX_CH_CTL_TIME_OUT_ERROR | 561 DP_AUX_CH_CTL_RECEIVE_ERROR); 562 563 if (status & (DP_AUX_CH_CTL_TIME_OUT_ERROR | 564 DP_AUX_CH_CTL_RECEIVE_ERROR)) 565 continue; 566 if (status & DP_AUX_CH_CTL_DONE) 567 break; 568 } 569 if (status & DP_AUX_CH_CTL_DONE) 570 break; 571 } 572 573 if ((status & DP_AUX_CH_CTL_DONE) == 0) { 574 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status); 575 ret = -EBUSY; 576 goto out; 577 } 578 579 /* Check for timeout or receive error. 580 * Timeouts occur when the sink is not connected 581 */ 582 if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) { 583 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status); 584 ret = -EIO; 585 goto out; 586 } 587 588 /* Timeouts occur when the device isn't connected, so they're 589 * "normal" -- don't fill the kernel log with these */ 590 if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) { 591 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status); 592 ret = -ETIMEDOUT; 593 goto out; 594 } 595 596 /* Unload any bytes sent back from the other side */ 597 recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >> 598 DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT); 599 if (recv_bytes > recv_size) 600 recv_bytes = recv_size; 601 602 for (i = 0; i < recv_bytes; i += 4) 603 unpack_aux(I915_READ(ch_data + i), 604 recv + i, recv_bytes - i); 605 606 ret = recv_bytes; 607out: 608 pm_qos_update_request(&dev_priv->pm_qos, PM_QOS_DEFAULT_VALUE); 609 intel_aux_display_runtime_put(dev_priv); 610 611 if (vdd) 612 edp_panel_vdd_off(intel_dp, false); 613 614 return ret; 615} 616 617#define BARE_ADDRESS_SIZE 3 618#define HEADER_SIZE (BARE_ADDRESS_SIZE + 1) 619static ssize_t 620intel_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg) 621{ 622 struct intel_dp *intel_dp = container_of(aux, struct intel_dp, aux); 623 uint8_t txbuf[20], rxbuf[20]; 624 size_t txsize, rxsize; 625 int ret; 626 627 txbuf[0] = msg->request << 4; 628 txbuf[1] = msg->address >> 8; 629 txbuf[2] = msg->address & 0xff; 630 txbuf[3] = msg->size - 1; 631 632 switch (msg->request & ~DP_AUX_I2C_MOT) { 633 case DP_AUX_NATIVE_WRITE: 634 case DP_AUX_I2C_WRITE: 635 txsize = msg->size ? HEADER_SIZE + msg->size : BARE_ADDRESS_SIZE; 636 rxsize = 1; 637 638 if (WARN_ON(txsize > 20)) 639 return -E2BIG; 640 641 memcpy(txbuf + HEADER_SIZE, msg->buffer, msg->size); 642 643 ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize); 644 if (ret > 0) { 645 msg->reply = rxbuf[0] >> 4; 646 647 /* Return payload size. */ 648 ret = msg->size; 649 } 650 break; 651 652 case DP_AUX_NATIVE_READ: 653 case DP_AUX_I2C_READ: 654 txsize = msg->size ? HEADER_SIZE : BARE_ADDRESS_SIZE; 655 rxsize = msg->size + 1; 656 657 if (WARN_ON(rxsize > 20)) 658 return -E2BIG; 659 660 ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize); 661 if (ret > 0) { 662 msg->reply = rxbuf[0] >> 4; 663 /* 664 * Assume happy day, and copy the data. The caller is 665 * expected to check msg->reply before touching it. 666 * 667 * Return payload size. 668 */ 669 ret--; 670 memcpy(msg->buffer, rxbuf + 1, ret); 671 } 672 break; 673 674 default: 675 ret = -EINVAL; 676 break; 677 } 678 679 return ret; 680} 681 682static void 683intel_dp_aux_init(struct intel_dp *intel_dp, struct intel_connector *connector) 684{ 685 struct drm_device *dev = intel_dp_to_dev(intel_dp); 686 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 687 enum port port = intel_dig_port->port; 688 const char *name = NULL; 689 int ret; 690 691 switch (port) { 692 case PORT_A: 693 intel_dp->aux_ch_ctl_reg = DPA_AUX_CH_CTL; 694 name = "DPDDC-A"; 695 break; 696 case PORT_B: 697 intel_dp->aux_ch_ctl_reg = PCH_DPB_AUX_CH_CTL; 698 name = "DPDDC-B"; 699 break; 700 case PORT_C: 701 intel_dp->aux_ch_ctl_reg = PCH_DPC_AUX_CH_CTL; 702 name = "DPDDC-C"; 703 break; 704 case PORT_D: 705 intel_dp->aux_ch_ctl_reg = PCH_DPD_AUX_CH_CTL; 706 name = "DPDDC-D"; 707 break; 708 default: 709 BUG(); 710 } 711 712 if (!HAS_DDI(dev)) 713 intel_dp->aux_ch_ctl_reg = intel_dp->output_reg + 0x10; 714 715 intel_dp->aux.name = name; 716 intel_dp->aux.dev = dev->dev; 717 intel_dp->aux.transfer = intel_dp_aux_transfer; 718 719 DRM_DEBUG_KMS("registering %s bus for %s\n", name, 720 connector->base.kdev->kobj.name); 721 722 ret = drm_dp_aux_register(&intel_dp->aux); 723 if (ret < 0) { 724 DRM_ERROR("drm_dp_aux_register() for %s failed (%d)\n", 725 name, ret); 726 return; 727 } 728 729 ret = sysfs_create_link(&connector->base.kdev->kobj, 730 &intel_dp->aux.ddc.dev.kobj, 731 intel_dp->aux.ddc.dev.kobj.name); 732 if (ret < 0) { 733 DRM_ERROR("sysfs_create_link() for %s failed (%d)\n", name, ret); 734 drm_dp_aux_unregister(&intel_dp->aux); 735 } 736} 737 738static void 739intel_dp_connector_unregister(struct intel_connector *intel_connector) 740{ 741 struct intel_dp *intel_dp = intel_attached_dp(&intel_connector->base); 742 743 sysfs_remove_link(&intel_connector->base.kdev->kobj, 744 intel_dp->aux.ddc.dev.kobj.name); 745 intel_connector_unregister(intel_connector); 746} 747 748static void 749hsw_dp_set_ddi_pll_sel(struct intel_crtc_config *pipe_config, int link_bw) 750{ 751 switch (link_bw) { 752 case DP_LINK_BW_1_62: 753 pipe_config->ddi_pll_sel = PORT_CLK_SEL_LCPLL_810; 754 break; 755 case DP_LINK_BW_2_7: 756 pipe_config->ddi_pll_sel = PORT_CLK_SEL_LCPLL_1350; 757 break; 758 case DP_LINK_BW_5_4: 759 pipe_config->ddi_pll_sel = PORT_CLK_SEL_LCPLL_2700; 760 break; 761 } 762} 763 764static void 765intel_dp_set_clock(struct intel_encoder *encoder, 766 struct intel_crtc_config *pipe_config, int link_bw) 767{ 768 struct drm_device *dev = encoder->base.dev; 769 const struct dp_link_dpll *divisor = NULL; 770 int i, count = 0; 771 772 if (IS_G4X(dev)) { 773 divisor = gen4_dpll; 774 count = ARRAY_SIZE(gen4_dpll); 775 } else if (HAS_PCH_SPLIT(dev)) { 776 divisor = pch_dpll; 777 count = ARRAY_SIZE(pch_dpll); 778 } else if (IS_CHERRYVIEW(dev)) { 779 divisor = chv_dpll; 780 count = ARRAY_SIZE(chv_dpll); 781 } else if (IS_VALLEYVIEW(dev)) { 782 divisor = vlv_dpll; 783 count = ARRAY_SIZE(vlv_dpll); 784 } 785 786 if (divisor && count) { 787 for (i = 0; i < count; i++) { 788 if (link_bw == divisor[i].link_bw) { 789 pipe_config->dpll = divisor[i].dpll; 790 pipe_config->clock_set = true; 791 break; 792 } 793 } 794 } 795} 796 797static void 798intel_dp_set_m2_n2(struct intel_crtc *crtc, struct intel_link_m_n *m_n) 799{ 800 struct drm_device *dev = crtc->base.dev; 801 struct drm_i915_private *dev_priv = dev->dev_private; 802 enum transcoder transcoder = crtc->config.cpu_transcoder; 803 804 I915_WRITE(PIPE_DATA_M2(transcoder), 805 TU_SIZE(m_n->tu) | m_n->gmch_m); 806 I915_WRITE(PIPE_DATA_N2(transcoder), m_n->gmch_n); 807 I915_WRITE(PIPE_LINK_M2(transcoder), m_n->link_m); 808 I915_WRITE(PIPE_LINK_N2(transcoder), m_n->link_n); 809} 810 811bool 812intel_dp_compute_config(struct intel_encoder *encoder, 813 struct intel_crtc_config *pipe_config) 814{ 815 struct drm_device *dev = encoder->base.dev; 816 struct drm_i915_private *dev_priv = dev->dev_private; 817 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode; 818 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); 819 enum port port = dp_to_dig_port(intel_dp)->port; 820 struct intel_crtc *intel_crtc = encoder->new_crtc; 821 struct intel_connector *intel_connector = intel_dp->attached_connector; 822 int lane_count, clock; 823 int min_lane_count = 1; 824 int max_lane_count = intel_dp_max_lane_count(intel_dp); 825 /* Conveniently, the link BW constants become indices with a shift...*/ 826 int min_clock = 0; 827 int max_clock = intel_dp_max_link_bw(intel_dp) >> 3; 828 int bpp, mode_rate; 829 static int bws[] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7, DP_LINK_BW_5_4 }; 830 int link_avail, link_clock; 831 832 if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev) && port != PORT_A) 833 pipe_config->has_pch_encoder = true; 834 835 pipe_config->has_dp_encoder = true; 836 pipe_config->has_audio = intel_dp->has_audio; 837 838 if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) { 839 intel_fixed_panel_mode(intel_connector->panel.fixed_mode, 840 adjusted_mode); 841 if (!HAS_PCH_SPLIT(dev)) 842 intel_gmch_panel_fitting(intel_crtc, pipe_config, 843 intel_connector->panel.fitting_mode); 844 else 845 intel_pch_panel_fitting(intel_crtc, pipe_config, 846 intel_connector->panel.fitting_mode); 847 } 848 849 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK) 850 return false; 851 852 DRM_DEBUG_KMS("DP link computation with max lane count %i " 853 "max bw %02x pixel clock %iKHz\n", 854 max_lane_count, bws[max_clock], 855 adjusted_mode->crtc_clock); 856 857 /* Walk through all bpp values. Luckily they're all nicely spaced with 2 858 * bpc in between. */ 859 bpp = pipe_config->pipe_bpp; 860 if (is_edp(intel_dp)) { 861 if (dev_priv->vbt.edp_bpp && dev_priv->vbt.edp_bpp < bpp) { 862 DRM_DEBUG_KMS("clamping bpp for eDP panel to BIOS-provided %i\n", 863 dev_priv->vbt.edp_bpp); 864 bpp = dev_priv->vbt.edp_bpp; 865 } 866 867 if (IS_BROADWELL(dev)) { 868 /* Yes, it's an ugly hack. */ 869 min_lane_count = max_lane_count; 870 DRM_DEBUG_KMS("forcing lane count to max (%u) on BDW\n", 871 min_lane_count); 872 } else if (dev_priv->vbt.edp_lanes) { 873 min_lane_count = min(dev_priv->vbt.edp_lanes, 874 max_lane_count); 875 DRM_DEBUG_KMS("using min %u lanes per VBT\n", 876 min_lane_count); 877 } 878 879 if (dev_priv->vbt.edp_rate) { 880 min_clock = min(dev_priv->vbt.edp_rate >> 3, max_clock); 881 DRM_DEBUG_KMS("using min %02x link bw per VBT\n", 882 bws[min_clock]); 883 } 884 } 885 886 for (; bpp >= 6*3; bpp -= 2*3) { 887 mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock, 888 bpp); 889 890 for (lane_count = min_lane_count; lane_count <= max_lane_count; lane_count <<= 1) { 891 for (clock = min_clock; clock <= max_clock; clock++) { 892 link_clock = drm_dp_bw_code_to_link_rate(bws[clock]); 893 link_avail = intel_dp_max_data_rate(link_clock, 894 lane_count); 895 896 if (mode_rate <= link_avail) { 897 goto found; 898 } 899 } 900 } 901 } 902 903 return false; 904 905found: 906 if (intel_dp->color_range_auto) { 907 /* 908 * See: 909 * CEA-861-E - 5.1 Default Encoding Parameters 910 * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry 911 */ 912 if (bpp != 18 && drm_match_cea_mode(adjusted_mode) > 1) 913 intel_dp->color_range = DP_COLOR_RANGE_16_235; 914 else 915 intel_dp->color_range = 0; 916 } 917 918 if (intel_dp->color_range) 919 pipe_config->limited_color_range = true; 920 921 intel_dp->link_bw = bws[clock]; 922 intel_dp->lane_count = lane_count; 923 pipe_config->pipe_bpp = bpp; 924 pipe_config->port_clock = drm_dp_bw_code_to_link_rate(intel_dp->link_bw); 925 926 DRM_DEBUG_KMS("DP link bw %02x lane count %d clock %d bpp %d\n", 927 intel_dp->link_bw, intel_dp->lane_count, 928 pipe_config->port_clock, bpp); 929 DRM_DEBUG_KMS("DP link bw required %i available %i\n", 930 mode_rate, link_avail); 931 932 intel_link_compute_m_n(bpp, lane_count, 933 adjusted_mode->crtc_clock, 934 pipe_config->port_clock, 935 &pipe_config->dp_m_n); 936 937 if (intel_connector->panel.downclock_mode != NULL && 938 intel_dp->drrs_state.type == SEAMLESS_DRRS_SUPPORT) { 939 intel_link_compute_m_n(bpp, lane_count, 940 intel_connector->panel.downclock_mode->clock, 941 pipe_config->port_clock, 942 &pipe_config->dp_m2_n2); 943 } 944 945 if (HAS_DDI(dev)) 946 hsw_dp_set_ddi_pll_sel(pipe_config, intel_dp->link_bw); 947 else 948 intel_dp_set_clock(encoder, pipe_config, intel_dp->link_bw); 949 950 return true; 951} 952 953static void ironlake_set_pll_cpu_edp(struct intel_dp *intel_dp) 954{ 955 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 956 struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc); 957 struct drm_device *dev = crtc->base.dev; 958 struct drm_i915_private *dev_priv = dev->dev_private; 959 u32 dpa_ctl; 960 961 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", crtc->config.port_clock); 962 dpa_ctl = I915_READ(DP_A); 963 dpa_ctl &= ~DP_PLL_FREQ_MASK; 964 965 if (crtc->config.port_clock == 162000) { 966 /* For a long time we've carried around a ILK-DevA w/a for the 967 * 160MHz clock. If we're really unlucky, it's still required. 968 */ 969 DRM_DEBUG_KMS("160MHz cpu eDP clock, might need ilk devA w/a\n"); 970 dpa_ctl |= DP_PLL_FREQ_160MHZ; 971 intel_dp->DP |= DP_PLL_FREQ_160MHZ; 972 } else { 973 dpa_ctl |= DP_PLL_FREQ_270MHZ; 974 intel_dp->DP |= DP_PLL_FREQ_270MHZ; 975 } 976 977 I915_WRITE(DP_A, dpa_ctl); 978 979 POSTING_READ(DP_A); 980 udelay(500); 981} 982 983static void intel_dp_prepare(struct intel_encoder *encoder) 984{ 985 struct drm_device *dev = encoder->base.dev; 986 struct drm_i915_private *dev_priv = dev->dev_private; 987 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); 988 enum port port = dp_to_dig_port(intel_dp)->port; 989 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); 990 struct drm_display_mode *adjusted_mode = &crtc->config.adjusted_mode; 991 992 /* 993 * There are four kinds of DP registers: 994 * 995 * IBX PCH 996 * SNB CPU 997 * IVB CPU 998 * CPT PCH 999 * 1000 * IBX PCH and CPU are the same for almost everything, 1001 * except that the CPU DP PLL is configured in this 1002 * register 1003 * 1004 * CPT PCH is quite different, having many bits moved 1005 * to the TRANS_DP_CTL register instead. That 1006 * configuration happens (oddly) in ironlake_pch_enable 1007 */ 1008 1009 /* Preserve the BIOS-computed detected bit. This is 1010 * supposed to be read-only. 1011 */ 1012 intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED; 1013 1014 /* Handle DP bits in common between all three register formats */ 1015 intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0; 1016 intel_dp->DP |= DP_PORT_WIDTH(intel_dp->lane_count); 1017 1018 if (crtc->config.has_audio) { 1019 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n", 1020 pipe_name(crtc->pipe)); 1021 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE; 1022 intel_write_eld(&encoder->base, adjusted_mode); 1023 } 1024 1025 /* Split out the IBX/CPU vs CPT settings */ 1026 1027 if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) { 1028 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) 1029 intel_dp->DP |= DP_SYNC_HS_HIGH; 1030 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) 1031 intel_dp->DP |= DP_SYNC_VS_HIGH; 1032 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT; 1033 1034 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd)) 1035 intel_dp->DP |= DP_ENHANCED_FRAMING; 1036 1037 intel_dp->DP |= crtc->pipe << 29; 1038 } else if (!HAS_PCH_CPT(dev) || port == PORT_A) { 1039 if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev)) 1040 intel_dp->DP |= intel_dp->color_range; 1041 1042 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) 1043 intel_dp->DP |= DP_SYNC_HS_HIGH; 1044 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) 1045 intel_dp->DP |= DP_SYNC_VS_HIGH; 1046 intel_dp->DP |= DP_LINK_TRAIN_OFF; 1047 1048 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd)) 1049 intel_dp->DP |= DP_ENHANCED_FRAMING; 1050 1051 if (!IS_CHERRYVIEW(dev)) { 1052 if (crtc->pipe == 1) 1053 intel_dp->DP |= DP_PIPEB_SELECT; 1054 } else { 1055 intel_dp->DP |= DP_PIPE_SELECT_CHV(crtc->pipe); 1056 } 1057 } else { 1058 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT; 1059 } 1060} 1061 1062#define IDLE_ON_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK) 1063#define IDLE_ON_VALUE (PP_ON | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE) 1064 1065#define IDLE_OFF_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | 0) 1066#define IDLE_OFF_VALUE (0 | PP_SEQUENCE_NONE | 0 | 0) 1067 1068#define IDLE_CYCLE_MASK (PP_ON | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK) 1069#define IDLE_CYCLE_VALUE (0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE) 1070 1071static void wait_panel_status(struct intel_dp *intel_dp, 1072 u32 mask, 1073 u32 value) 1074{ 1075 struct drm_device *dev = intel_dp_to_dev(intel_dp); 1076 struct drm_i915_private *dev_priv = dev->dev_private; 1077 u32 pp_stat_reg, pp_ctrl_reg; 1078 1079 pp_stat_reg = _pp_stat_reg(intel_dp); 1080 pp_ctrl_reg = _pp_ctrl_reg(intel_dp); 1081 1082 DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n", 1083 mask, value, 1084 I915_READ(pp_stat_reg), 1085 I915_READ(pp_ctrl_reg)); 1086 1087 if (_wait_for((I915_READ(pp_stat_reg) & mask) == value, 5000, 10)) { 1088 DRM_ERROR("Panel status timeout: status %08x control %08x\n", 1089 I915_READ(pp_stat_reg), 1090 I915_READ(pp_ctrl_reg)); 1091 } 1092 1093 DRM_DEBUG_KMS("Wait complete\n"); 1094} 1095 1096static void wait_panel_on(struct intel_dp *intel_dp) 1097{ 1098 DRM_DEBUG_KMS("Wait for panel power on\n"); 1099 wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE); 1100} 1101 1102static void wait_panel_off(struct intel_dp *intel_dp) 1103{ 1104 DRM_DEBUG_KMS("Wait for panel power off time\n"); 1105 wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE); 1106} 1107 1108static void wait_panel_power_cycle(struct intel_dp *intel_dp) 1109{ 1110 DRM_DEBUG_KMS("Wait for panel power cycle\n"); 1111 1112 /* When we disable the VDD override bit last we have to do the manual 1113 * wait. */ 1114 wait_remaining_ms_from_jiffies(intel_dp->last_power_cycle, 1115 intel_dp->panel_power_cycle_delay); 1116 1117 wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE); 1118} 1119 1120static void wait_backlight_on(struct intel_dp *intel_dp) 1121{ 1122 wait_remaining_ms_from_jiffies(intel_dp->last_power_on, 1123 intel_dp->backlight_on_delay); 1124} 1125 1126static void edp_wait_backlight_off(struct intel_dp *intel_dp) 1127{ 1128 wait_remaining_ms_from_jiffies(intel_dp->last_backlight_off, 1129 intel_dp->backlight_off_delay); 1130} 1131 1132/* Read the current pp_control value, unlocking the register if it 1133 * is locked 1134 */ 1135 1136static u32 ironlake_get_pp_control(struct intel_dp *intel_dp) 1137{ 1138 struct drm_device *dev = intel_dp_to_dev(intel_dp); 1139 struct drm_i915_private *dev_priv = dev->dev_private; 1140 u32 control; 1141 1142 control = I915_READ(_pp_ctrl_reg(intel_dp)); 1143 control &= ~PANEL_UNLOCK_MASK; 1144 control |= PANEL_UNLOCK_REGS; 1145 return control; 1146} 1147 1148static bool _edp_panel_vdd_on(struct intel_dp *intel_dp) 1149{ 1150 struct drm_device *dev = intel_dp_to_dev(intel_dp); 1151 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 1152 struct intel_encoder *intel_encoder = &intel_dig_port->base; 1153 struct drm_i915_private *dev_priv = dev->dev_private; 1154 enum intel_display_power_domain power_domain; 1155 u32 pp; 1156 u32 pp_stat_reg, pp_ctrl_reg; 1157 bool need_to_disable = !intel_dp->want_panel_vdd; 1158 1159 if (!is_edp(intel_dp)) 1160 return false; 1161 1162 intel_dp->want_panel_vdd = true; 1163 1164 if (edp_have_panel_vdd(intel_dp)) 1165 return need_to_disable; 1166 1167 power_domain = intel_display_port_power_domain(intel_encoder); 1168 intel_display_power_get(dev_priv, power_domain); 1169 1170 DRM_DEBUG_KMS("Turning eDP VDD on\n"); 1171 1172 if (!edp_have_panel_power(intel_dp)) 1173 wait_panel_power_cycle(intel_dp); 1174 1175 pp = ironlake_get_pp_control(intel_dp); 1176 pp |= EDP_FORCE_VDD; 1177 1178 pp_stat_reg = _pp_stat_reg(intel_dp); 1179 pp_ctrl_reg = _pp_ctrl_reg(intel_dp); 1180 1181 I915_WRITE(pp_ctrl_reg, pp); 1182 POSTING_READ(pp_ctrl_reg); 1183 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n", 1184 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg)); 1185 /* 1186 * If the panel wasn't on, delay before accessing aux channel 1187 */ 1188 if (!edp_have_panel_power(intel_dp)) { 1189 DRM_DEBUG_KMS("eDP was not running\n"); 1190 msleep(intel_dp->panel_power_up_delay); 1191 } 1192 1193 return need_to_disable; 1194} 1195 1196void intel_edp_panel_vdd_on(struct intel_dp *intel_dp) 1197{ 1198 if (is_edp(intel_dp)) { 1199 bool vdd = _edp_panel_vdd_on(intel_dp); 1200 1201 WARN(!vdd, "eDP VDD already requested on\n"); 1202 } 1203} 1204 1205static void edp_panel_vdd_off_sync(struct intel_dp *intel_dp) 1206{ 1207 struct drm_device *dev = intel_dp_to_dev(intel_dp); 1208 struct drm_i915_private *dev_priv = dev->dev_private; 1209 u32 pp; 1210 u32 pp_stat_reg, pp_ctrl_reg; 1211 1212 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex)); 1213 1214 if (!intel_dp->want_panel_vdd && edp_have_panel_vdd(intel_dp)) { 1215 struct intel_digital_port *intel_dig_port = 1216 dp_to_dig_port(intel_dp); 1217 struct intel_encoder *intel_encoder = &intel_dig_port->base; 1218 enum intel_display_power_domain power_domain; 1219 1220 DRM_DEBUG_KMS("Turning eDP VDD off\n"); 1221 1222 pp = ironlake_get_pp_control(intel_dp); 1223 pp &= ~EDP_FORCE_VDD; 1224 1225 pp_ctrl_reg = _pp_ctrl_reg(intel_dp); 1226 pp_stat_reg = _pp_stat_reg(intel_dp); 1227 1228 I915_WRITE(pp_ctrl_reg, pp); 1229 POSTING_READ(pp_ctrl_reg); 1230 1231 /* Make sure sequencer is idle before allowing subsequent activity */ 1232 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n", 1233 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg)); 1234 1235 if ((pp & POWER_TARGET_ON) == 0) 1236 intel_dp->last_power_cycle = jiffies; 1237 1238 power_domain = intel_display_port_power_domain(intel_encoder); 1239 intel_display_power_put(dev_priv, power_domain); 1240 } 1241} 1242 1243static void edp_panel_vdd_work(struct work_struct *__work) 1244{ 1245 struct intel_dp *intel_dp = container_of(to_delayed_work(__work), 1246 struct intel_dp, panel_vdd_work); 1247 struct drm_device *dev = intel_dp_to_dev(intel_dp); 1248 1249 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL); 1250 edp_panel_vdd_off_sync(intel_dp); 1251 drm_modeset_unlock(&dev->mode_config.connection_mutex); 1252} 1253 1254static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync) 1255{ 1256 if (!is_edp(intel_dp)) 1257 return; 1258 1259 WARN(!intel_dp->want_panel_vdd, "eDP VDD not forced on"); 1260 1261 intel_dp->want_panel_vdd = false; 1262 1263 if (sync) { 1264 edp_panel_vdd_off_sync(intel_dp); 1265 } else { 1266 /* 1267 * Queue the timer to fire a long 1268 * time from now (relative to the power down delay) 1269 * to keep the panel power up across a sequence of operations 1270 */ 1271 schedule_delayed_work(&intel_dp->panel_vdd_work, 1272 msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5)); 1273 } 1274} 1275 1276void intel_edp_panel_on(struct intel_dp *intel_dp) 1277{ 1278 struct drm_device *dev = intel_dp_to_dev(intel_dp); 1279 struct drm_i915_private *dev_priv = dev->dev_private; 1280 u32 pp; 1281 u32 pp_ctrl_reg; 1282 1283 if (!is_edp(intel_dp)) 1284 return; 1285 1286 DRM_DEBUG_KMS("Turn eDP power on\n"); 1287 1288 if (edp_have_panel_power(intel_dp)) { 1289 DRM_DEBUG_KMS("eDP power already on\n"); 1290 return; 1291 } 1292 1293 wait_panel_power_cycle(intel_dp); 1294 1295 pp_ctrl_reg = _pp_ctrl_reg(intel_dp); 1296 pp = ironlake_get_pp_control(intel_dp); 1297 if (IS_GEN5(dev)) { 1298 /* ILK workaround: disable reset around power sequence */ 1299 pp &= ~PANEL_POWER_RESET; 1300 I915_WRITE(pp_ctrl_reg, pp); 1301 POSTING_READ(pp_ctrl_reg); 1302 } 1303 1304 pp |= POWER_TARGET_ON; 1305 if (!IS_GEN5(dev)) 1306 pp |= PANEL_POWER_RESET; 1307 1308 I915_WRITE(pp_ctrl_reg, pp); 1309 POSTING_READ(pp_ctrl_reg); 1310 1311 wait_panel_on(intel_dp); 1312 intel_dp->last_power_on = jiffies; 1313 1314 if (IS_GEN5(dev)) { 1315 pp |= PANEL_POWER_RESET; /* restore panel reset bit */ 1316 I915_WRITE(pp_ctrl_reg, pp); 1317 POSTING_READ(pp_ctrl_reg); 1318 } 1319} 1320 1321void intel_edp_panel_off(struct intel_dp *intel_dp) 1322{ 1323 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 1324 struct intel_encoder *intel_encoder = &intel_dig_port->base; 1325 struct drm_device *dev = intel_dp_to_dev(intel_dp); 1326 struct drm_i915_private *dev_priv = dev->dev_private; 1327 enum intel_display_power_domain power_domain; 1328 u32 pp; 1329 u32 pp_ctrl_reg; 1330 1331 if (!is_edp(intel_dp)) 1332 return; 1333 1334 DRM_DEBUG_KMS("Turn eDP power off\n"); 1335 1336 WARN(!intel_dp->want_panel_vdd, "Need VDD to turn off panel\n"); 1337 1338 pp = ironlake_get_pp_control(intel_dp); 1339 /* We need to switch off panel power _and_ force vdd, for otherwise some 1340 * panels get very unhappy and cease to work. */ 1341 pp &= ~(POWER_TARGET_ON | PANEL_POWER_RESET | EDP_FORCE_VDD | 1342 EDP_BLC_ENABLE); 1343 1344 pp_ctrl_reg = _pp_ctrl_reg(intel_dp); 1345 1346 intel_dp->want_panel_vdd = false; 1347 1348 I915_WRITE(pp_ctrl_reg, pp); 1349 POSTING_READ(pp_ctrl_reg); 1350 1351 intel_dp->last_power_cycle = jiffies; 1352 wait_panel_off(intel_dp); 1353 1354 /* We got a reference when we enabled the VDD. */ 1355 power_domain = intel_display_port_power_domain(intel_encoder); 1356 intel_display_power_put(dev_priv, power_domain); 1357} 1358 1359void intel_edp_backlight_on(struct intel_dp *intel_dp) 1360{ 1361 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 1362 struct drm_device *dev = intel_dig_port->base.base.dev; 1363 struct drm_i915_private *dev_priv = dev->dev_private; 1364 u32 pp; 1365 u32 pp_ctrl_reg; 1366 1367 if (!is_edp(intel_dp)) 1368 return; 1369 1370 DRM_DEBUG_KMS("\n"); 1371 1372 intel_panel_enable_backlight(intel_dp->attached_connector); 1373 1374 /* 1375 * If we enable the backlight right away following a panel power 1376 * on, we may see slight flicker as the panel syncs with the eDP 1377 * link. So delay a bit to make sure the image is solid before 1378 * allowing it to appear. 1379 */ 1380 wait_backlight_on(intel_dp); 1381 pp = ironlake_get_pp_control(intel_dp); 1382 pp |= EDP_BLC_ENABLE; 1383 1384 pp_ctrl_reg = _pp_ctrl_reg(intel_dp); 1385 1386 I915_WRITE(pp_ctrl_reg, pp); 1387 POSTING_READ(pp_ctrl_reg); 1388} 1389 1390void intel_edp_backlight_off(struct intel_dp *intel_dp) 1391{ 1392 struct drm_device *dev = intel_dp_to_dev(intel_dp); 1393 struct drm_i915_private *dev_priv = dev->dev_private; 1394 u32 pp; 1395 u32 pp_ctrl_reg; 1396 1397 if (!is_edp(intel_dp)) 1398 return; 1399 1400 DRM_DEBUG_KMS("\n"); 1401 pp = ironlake_get_pp_control(intel_dp); 1402 pp &= ~EDP_BLC_ENABLE; 1403 1404 pp_ctrl_reg = _pp_ctrl_reg(intel_dp); 1405 1406 I915_WRITE(pp_ctrl_reg, pp); 1407 POSTING_READ(pp_ctrl_reg); 1408 intel_dp->last_backlight_off = jiffies; 1409 1410 edp_wait_backlight_off(intel_dp); 1411 1412 intel_panel_disable_backlight(intel_dp->attached_connector); 1413} 1414 1415static void ironlake_edp_pll_on(struct intel_dp *intel_dp) 1416{ 1417 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 1418 struct drm_crtc *crtc = intel_dig_port->base.base.crtc; 1419 struct drm_device *dev = crtc->dev; 1420 struct drm_i915_private *dev_priv = dev->dev_private; 1421 u32 dpa_ctl; 1422 1423 assert_pipe_disabled(dev_priv, 1424 to_intel_crtc(crtc)->pipe); 1425 1426 DRM_DEBUG_KMS("\n"); 1427 dpa_ctl = I915_READ(DP_A); 1428 WARN(dpa_ctl & DP_PLL_ENABLE, "dp pll on, should be off\n"); 1429 WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n"); 1430 1431 /* We don't adjust intel_dp->DP while tearing down the link, to 1432 * facilitate link retraining (e.g. after hotplug). Hence clear all 1433 * enable bits here to ensure that we don't enable too much. */ 1434 intel_dp->DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE); 1435 intel_dp->DP |= DP_PLL_ENABLE; 1436 I915_WRITE(DP_A, intel_dp->DP); 1437 POSTING_READ(DP_A); 1438 udelay(200); 1439} 1440 1441static void ironlake_edp_pll_off(struct intel_dp *intel_dp) 1442{ 1443 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 1444 struct drm_crtc *crtc = intel_dig_port->base.base.crtc; 1445 struct drm_device *dev = crtc->dev; 1446 struct drm_i915_private *dev_priv = dev->dev_private; 1447 u32 dpa_ctl; 1448 1449 assert_pipe_disabled(dev_priv, 1450 to_intel_crtc(crtc)->pipe); 1451 1452 dpa_ctl = I915_READ(DP_A); 1453 WARN((dpa_ctl & DP_PLL_ENABLE) == 0, 1454 "dp pll off, should be on\n"); 1455 WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n"); 1456 1457 /* We can't rely on the value tracked for the DP register in 1458 * intel_dp->DP because link_down must not change that (otherwise link 1459 * re-training will fail. */ 1460 dpa_ctl &= ~DP_PLL_ENABLE; 1461 I915_WRITE(DP_A, dpa_ctl); 1462 POSTING_READ(DP_A); 1463 udelay(200); 1464} 1465 1466/* If the sink supports it, try to set the power state appropriately */ 1467void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode) 1468{ 1469 int ret, i; 1470 1471 /* Should have a valid DPCD by this point */ 1472 if (intel_dp->dpcd[DP_DPCD_REV] < 0x11) 1473 return; 1474 1475 if (mode != DRM_MODE_DPMS_ON) { 1476 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER, 1477 DP_SET_POWER_D3); 1478 if (ret != 1) 1479 DRM_DEBUG_DRIVER("failed to write sink power state\n"); 1480 } else { 1481 /* 1482 * When turning on, we need to retry for 1ms to give the sink 1483 * time to wake up. 1484 */ 1485 for (i = 0; i < 3; i++) { 1486 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER, 1487 DP_SET_POWER_D0); 1488 if (ret == 1) 1489 break; 1490 msleep(1); 1491 } 1492 } 1493} 1494 1495static bool intel_dp_get_hw_state(struct intel_encoder *encoder, 1496 enum pipe *pipe) 1497{ 1498 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); 1499 enum port port = dp_to_dig_port(intel_dp)->port; 1500 struct drm_device *dev = encoder->base.dev; 1501 struct drm_i915_private *dev_priv = dev->dev_private; 1502 enum intel_display_power_domain power_domain; 1503 u32 tmp; 1504 1505 power_domain = intel_display_port_power_domain(encoder); 1506 if (!intel_display_power_enabled(dev_priv, power_domain)) 1507 return false; 1508 1509 tmp = I915_READ(intel_dp->output_reg); 1510 1511 if (!(tmp & DP_PORT_EN)) 1512 return false; 1513 1514 if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) { 1515 *pipe = PORT_TO_PIPE_CPT(tmp); 1516 } else if (IS_CHERRYVIEW(dev)) { 1517 *pipe = DP_PORT_TO_PIPE_CHV(tmp); 1518 } else if (!HAS_PCH_CPT(dev) || port == PORT_A) { 1519 *pipe = PORT_TO_PIPE(tmp); 1520 } else { 1521 u32 trans_sel; 1522 u32 trans_dp; 1523 int i; 1524 1525 switch (intel_dp->output_reg) { 1526 case PCH_DP_B: 1527 trans_sel = TRANS_DP_PORT_SEL_B; 1528 break; 1529 case PCH_DP_C: 1530 trans_sel = TRANS_DP_PORT_SEL_C; 1531 break; 1532 case PCH_DP_D: 1533 trans_sel = TRANS_DP_PORT_SEL_D; 1534 break; 1535 default: 1536 return true; 1537 } 1538 1539 for_each_pipe(i) { 1540 trans_dp = I915_READ(TRANS_DP_CTL(i)); 1541 if ((trans_dp & TRANS_DP_PORT_SEL_MASK) == trans_sel) { 1542 *pipe = i; 1543 return true; 1544 } 1545 } 1546 1547 DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n", 1548 intel_dp->output_reg); 1549 } 1550 1551 return true; 1552} 1553 1554static void intel_dp_get_config(struct intel_encoder *encoder, 1555 struct intel_crtc_config *pipe_config) 1556{ 1557 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); 1558 u32 tmp, flags = 0; 1559 struct drm_device *dev = encoder->base.dev; 1560 struct drm_i915_private *dev_priv = dev->dev_private; 1561 enum port port = dp_to_dig_port(intel_dp)->port; 1562 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); 1563 int dotclock; 1564 1565 tmp = I915_READ(intel_dp->output_reg); 1566 if (tmp & DP_AUDIO_OUTPUT_ENABLE) 1567 pipe_config->has_audio = true; 1568 1569 if ((port == PORT_A) || !HAS_PCH_CPT(dev)) { 1570 if (tmp & DP_SYNC_HS_HIGH) 1571 flags |= DRM_MODE_FLAG_PHSYNC; 1572 else 1573 flags |= DRM_MODE_FLAG_NHSYNC; 1574 1575 if (tmp & DP_SYNC_VS_HIGH) 1576 flags |= DRM_MODE_FLAG_PVSYNC; 1577 else 1578 flags |= DRM_MODE_FLAG_NVSYNC; 1579 } else { 1580 tmp = I915_READ(TRANS_DP_CTL(crtc->pipe)); 1581 if (tmp & TRANS_DP_HSYNC_ACTIVE_HIGH) 1582 flags |= DRM_MODE_FLAG_PHSYNC; 1583 else 1584 flags |= DRM_MODE_FLAG_NHSYNC; 1585 1586 if (tmp & TRANS_DP_VSYNC_ACTIVE_HIGH) 1587 flags |= DRM_MODE_FLAG_PVSYNC; 1588 else 1589 flags |= DRM_MODE_FLAG_NVSYNC; 1590 } 1591 1592 pipe_config->adjusted_mode.flags |= flags; 1593 1594 pipe_config->has_dp_encoder = true; 1595 1596 intel_dp_get_m_n(crtc, pipe_config); 1597 1598 if (port == PORT_A) { 1599 if ((I915_READ(DP_A) & DP_PLL_FREQ_MASK) == DP_PLL_FREQ_160MHZ) 1600 pipe_config->port_clock = 162000; 1601 else 1602 pipe_config->port_clock = 270000; 1603 } 1604 1605 dotclock = intel_dotclock_calculate(pipe_config->port_clock, 1606 &pipe_config->dp_m_n); 1607 1608 if (HAS_PCH_SPLIT(dev_priv->dev) && port != PORT_A) 1609 ironlake_check_encoder_dotclock(pipe_config, dotclock); 1610 1611 pipe_config->adjusted_mode.crtc_clock = dotclock; 1612 1613 if (is_edp(intel_dp) && dev_priv->vbt.edp_bpp && 1614 pipe_config->pipe_bpp > dev_priv->vbt.edp_bpp) { 1615 /* 1616 * This is a big fat ugly hack. 1617 * 1618 * Some machines in UEFI boot mode provide us a VBT that has 18 1619 * bpp and 1.62 GHz link bandwidth for eDP, which for reasons 1620 * unknown we fail to light up. Yet the same BIOS boots up with 1621 * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as 1622 * max, not what it tells us to use. 1623 * 1624 * Note: This will still be broken if the eDP panel is not lit 1625 * up by the BIOS, and thus we can't get the mode at module 1626 * load. 1627 */ 1628 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n", 1629 pipe_config->pipe_bpp, dev_priv->vbt.edp_bpp); 1630 dev_priv->vbt.edp_bpp = pipe_config->pipe_bpp; 1631 } 1632} 1633 1634static bool is_edp_psr(struct intel_dp *intel_dp) 1635{ 1636 return intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED; 1637} 1638 1639static bool intel_edp_is_psr_enabled(struct drm_device *dev) 1640{ 1641 struct drm_i915_private *dev_priv = dev->dev_private; 1642 1643 if (!HAS_PSR(dev)) 1644 return false; 1645 1646 return I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE; 1647} 1648 1649static void intel_edp_psr_write_vsc(struct intel_dp *intel_dp, 1650 struct edp_vsc_psr *vsc_psr) 1651{ 1652 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 1653 struct drm_device *dev = dig_port->base.base.dev; 1654 struct drm_i915_private *dev_priv = dev->dev_private; 1655 struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc); 1656 u32 ctl_reg = HSW_TVIDEO_DIP_CTL(crtc->config.cpu_transcoder); 1657 u32 data_reg = HSW_TVIDEO_DIP_VSC_DATA(crtc->config.cpu_transcoder); 1658 uint32_t *data = (uint32_t *) vsc_psr; 1659 unsigned int i; 1660 1661 /* As per BSPec (Pipe Video Data Island Packet), we need to disable 1662 the video DIP being updated before program video DIP data buffer 1663 registers for DIP being updated. */ 1664 I915_WRITE(ctl_reg, 0); 1665 POSTING_READ(ctl_reg); 1666 1667 for (i = 0; i < VIDEO_DIP_VSC_DATA_SIZE; i += 4) { 1668 if (i < sizeof(struct edp_vsc_psr)) 1669 I915_WRITE(data_reg + i, *data++); 1670 else 1671 I915_WRITE(data_reg + i, 0); 1672 } 1673 1674 I915_WRITE(ctl_reg, VIDEO_DIP_ENABLE_VSC_HSW); 1675 POSTING_READ(ctl_reg); 1676} 1677 1678static void intel_edp_psr_setup(struct intel_dp *intel_dp) 1679{ 1680 struct drm_device *dev = intel_dp_to_dev(intel_dp); 1681 struct drm_i915_private *dev_priv = dev->dev_private; 1682 struct edp_vsc_psr psr_vsc; 1683 1684 if (dev_priv->psr.setup_done) 1685 return; 1686 1687 /* Prepare VSC packet as per EDP 1.3 spec, Table 3.10 */ 1688 memset(&psr_vsc, 0, sizeof(psr_vsc)); 1689 psr_vsc.sdp_header.HB0 = 0; 1690 psr_vsc.sdp_header.HB1 = 0x7; 1691 psr_vsc.sdp_header.HB2 = 0x2; 1692 psr_vsc.sdp_header.HB3 = 0x8; 1693 intel_edp_psr_write_vsc(intel_dp, &psr_vsc); 1694 1695 /* Avoid continuous PSR exit by masking memup and hpd */ 1696 I915_WRITE(EDP_PSR_DEBUG_CTL(dev), EDP_PSR_DEBUG_MASK_MEMUP | 1697 EDP_PSR_DEBUG_MASK_HPD | EDP_PSR_DEBUG_MASK_LPSP); 1698 1699 dev_priv->psr.setup_done = true; 1700} 1701 1702static void intel_edp_psr_enable_sink(struct intel_dp *intel_dp) 1703{ 1704 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 1705 struct drm_device *dev = dig_port->base.base.dev; 1706 struct drm_i915_private *dev_priv = dev->dev_private; 1707 uint32_t aux_clock_divider; 1708 int precharge = 0x3; 1709 int msg_size = 5; /* Header(4) + Message(1) */ 1710 bool only_standby = false; 1711 1712 aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, 0); 1713 1714 if (IS_BROADWELL(dev) && dig_port->port != PORT_A) 1715 only_standby = true; 1716 1717 /* Enable PSR in sink */ 1718 if (intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT || only_standby) 1719 drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG, 1720 DP_PSR_ENABLE & ~DP_PSR_MAIN_LINK_ACTIVE); 1721 else 1722 drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG, 1723 DP_PSR_ENABLE | DP_PSR_MAIN_LINK_ACTIVE); 1724 1725 /* Setup AUX registers */ 1726 I915_WRITE(EDP_PSR_AUX_DATA1(dev), EDP_PSR_DPCD_COMMAND); 1727 I915_WRITE(EDP_PSR_AUX_DATA2(dev), EDP_PSR_DPCD_NORMAL_OPERATION); 1728 I915_WRITE(EDP_PSR_AUX_CTL(dev), 1729 DP_AUX_CH_CTL_TIME_OUT_400us | 1730 (msg_size << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) | 1731 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) | 1732 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT)); 1733} 1734 1735static void intel_edp_psr_enable_source(struct intel_dp *intel_dp) 1736{ 1737 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 1738 struct drm_device *dev = dig_port->base.base.dev; 1739 struct drm_i915_private *dev_priv = dev->dev_private; 1740 uint32_t max_sleep_time = 0x1f; 1741 uint32_t idle_frames = 1; 1742 uint32_t val = 0x0; 1743 const uint32_t link_entry_time = EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES; 1744 bool only_standby = false; 1745 1746 if (IS_BROADWELL(dev) && dig_port->port != PORT_A) 1747 only_standby = true; 1748 1749 if (intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT || only_standby) { 1750 val |= EDP_PSR_LINK_STANDBY; 1751 val |= EDP_PSR_TP2_TP3_TIME_0us; 1752 val |= EDP_PSR_TP1_TIME_0us; 1753 val |= EDP_PSR_SKIP_AUX_EXIT; 1754 val |= IS_BROADWELL(dev) ? BDW_PSR_SINGLE_FRAME : 0; 1755 } else 1756 val |= EDP_PSR_LINK_DISABLE; 1757 1758 I915_WRITE(EDP_PSR_CTL(dev), val | 1759 (IS_BROADWELL(dev) ? 0 : link_entry_time) | 1760 max_sleep_time << EDP_PSR_MAX_SLEEP_TIME_SHIFT | 1761 idle_frames << EDP_PSR_IDLE_FRAME_SHIFT | 1762 EDP_PSR_ENABLE); 1763} 1764 1765static bool intel_edp_psr_match_conditions(struct intel_dp *intel_dp) 1766{ 1767 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 1768 struct drm_device *dev = dig_port->base.base.dev; 1769 struct drm_i915_private *dev_priv = dev->dev_private; 1770 struct drm_crtc *crtc = dig_port->base.base.crtc; 1771 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 1772 struct drm_i915_gem_object *obj = intel_fb_obj(crtc->primary->fb); 1773 struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base; 1774 1775 dev_priv->psr.source_ok = false; 1776 1777 if (!HAS_PSR(dev)) { 1778 DRM_DEBUG_KMS("PSR not supported on this platform\n"); 1779 return false; 1780 } 1781 1782 if (IS_HASWELL(dev) && (intel_encoder->type != INTEL_OUTPUT_EDP || 1783 dig_port->port != PORT_A)) { 1784 DRM_DEBUG_KMS("HSW ties PSR to DDI A (eDP)\n"); 1785 return false; 1786 } 1787 1788 if (!i915.enable_psr) { 1789 DRM_DEBUG_KMS("PSR disable by flag\n"); 1790 return false; 1791 } 1792 1793 crtc = dig_port->base.base.crtc; 1794 if (crtc == NULL) { 1795 DRM_DEBUG_KMS("crtc not active for PSR\n"); 1796 return false; 1797 } 1798 1799 intel_crtc = to_intel_crtc(crtc); 1800 if (!intel_crtc_active(crtc)) { 1801 DRM_DEBUG_KMS("crtc not active for PSR\n"); 1802 return false; 1803 } 1804 1805 if (obj->tiling_mode != I915_TILING_X || 1806 obj->fence_reg == I915_FENCE_REG_NONE) { 1807 DRM_DEBUG_KMS("PSR condition failed: fb not tiled or fenced\n"); 1808 return false; 1809 } 1810 1811 /* Below limitations aren't valid for Broadwell */ 1812 if (IS_BROADWELL(dev)) 1813 goto out; 1814 1815 if (I915_READ(SPRCTL(intel_crtc->pipe)) & SPRITE_ENABLE) { 1816 DRM_DEBUG_KMS("PSR condition failed: Sprite is Enabled\n"); 1817 return false; 1818 } 1819 1820 if (I915_READ(HSW_STEREO_3D_CTL(intel_crtc->config.cpu_transcoder)) & 1821 S3D_ENABLE) { 1822 DRM_DEBUG_KMS("PSR condition failed: Stereo 3D is Enabled\n"); 1823 return false; 1824 } 1825 1826 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) { 1827 DRM_DEBUG_KMS("PSR condition failed: Interlaced is Enabled\n"); 1828 return false; 1829 } 1830 1831 out: 1832 dev_priv->psr.source_ok = true; 1833 return true; 1834} 1835 1836static void intel_edp_psr_do_enable(struct intel_dp *intel_dp) 1837{ 1838 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 1839 struct drm_device *dev = intel_dig_port->base.base.dev; 1840 struct drm_i915_private *dev_priv = dev->dev_private; 1841 1842 if (intel_edp_is_psr_enabled(dev)) 1843 return; 1844 1845 /* Enable PSR on the panel */ 1846 intel_edp_psr_enable_sink(intel_dp); 1847 1848 /* Enable PSR on the host */ 1849 intel_edp_psr_enable_source(intel_dp); 1850 1851 dev_priv->psr.enabled = true; 1852 dev_priv->psr.active = true; 1853} 1854 1855void intel_edp_psr_enable(struct intel_dp *intel_dp) 1856{ 1857 struct drm_device *dev = intel_dp_to_dev(intel_dp); 1858 1859 if (!HAS_PSR(dev)) { 1860 DRM_DEBUG_KMS("PSR not supported on this platform\n"); 1861 return; 1862 } 1863 1864 if (!is_edp_psr(intel_dp)) { 1865 DRM_DEBUG_KMS("PSR not supported by this panel\n"); 1866 return; 1867 } 1868 1869 /* Setup PSR once */ 1870 intel_edp_psr_setup(intel_dp); 1871 1872 if (intel_edp_psr_match_conditions(intel_dp)) 1873 intel_edp_psr_do_enable(intel_dp); 1874} 1875 1876void intel_edp_psr_disable(struct intel_dp *intel_dp) 1877{ 1878 struct drm_device *dev = intel_dp_to_dev(intel_dp); 1879 struct drm_i915_private *dev_priv = dev->dev_private; 1880 1881 if (!dev_priv->psr.enabled) 1882 return; 1883 1884 I915_WRITE(EDP_PSR_CTL(dev), 1885 I915_READ(EDP_PSR_CTL(dev)) & ~EDP_PSR_ENABLE); 1886 1887 /* Wait till PSR is idle */ 1888 if (_wait_for((I915_READ(EDP_PSR_STATUS_CTL(dev)) & 1889 EDP_PSR_STATUS_STATE_MASK) == 0, 2000, 10)) 1890 DRM_ERROR("Timed out waiting for PSR Idle State\n"); 1891 1892 dev_priv->psr.enabled = false; 1893} 1894 1895static void intel_edp_psr_work(struct work_struct *work) 1896{ 1897 struct drm_i915_private *dev_priv = 1898 container_of(work, typeof(*dev_priv), psr.work.work); 1899 struct drm_device *dev = dev_priv->dev; 1900 struct intel_encoder *encoder; 1901 struct intel_dp *intel_dp = NULL; 1902 1903 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) 1904 if (encoder->type == INTEL_OUTPUT_EDP) { 1905 intel_dp = enc_to_intel_dp(&encoder->base); 1906 1907 if (!intel_edp_psr_match_conditions(intel_dp)) 1908 intel_edp_psr_disable(intel_dp); 1909 else 1910 intel_edp_psr_do_enable(intel_dp); 1911 } 1912} 1913 1914static void intel_edp_psr_inactivate(struct drm_device *dev) 1915{ 1916 struct drm_i915_private *dev_priv = dev->dev_private; 1917 1918 dev_priv->psr.active = false; 1919 1920 I915_WRITE(EDP_PSR_CTL(dev), I915_READ(EDP_PSR_CTL(dev)) 1921 & ~EDP_PSR_ENABLE); 1922} 1923 1924void intel_edp_psr_exit(struct drm_device *dev) 1925{ 1926 struct drm_i915_private *dev_priv = dev->dev_private; 1927 1928 if (!HAS_PSR(dev)) 1929 return; 1930 1931 if (!dev_priv->psr.setup_done) 1932 return; 1933 1934 cancel_delayed_work_sync(&dev_priv->psr.work); 1935 1936 if (dev_priv->psr.active) 1937 intel_edp_psr_inactivate(dev); 1938 1939 schedule_delayed_work(&dev_priv->psr.work, 1940 msecs_to_jiffies(100)); 1941} 1942 1943void intel_edp_psr_init(struct drm_device *dev) 1944{ 1945 struct drm_i915_private *dev_priv = dev->dev_private; 1946 1947 if (!HAS_PSR(dev)) 1948 return; 1949 1950 INIT_DELAYED_WORK(&dev_priv->psr.work, intel_edp_psr_work); 1951} 1952 1953static void intel_disable_dp(struct intel_encoder *encoder) 1954{ 1955 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); 1956 enum port port = dp_to_dig_port(intel_dp)->port; 1957 struct drm_device *dev = encoder->base.dev; 1958 1959 /* Make sure the panel is off before trying to change the mode. But also 1960 * ensure that we have vdd while we switch off the panel. */ 1961 intel_edp_panel_vdd_on(intel_dp); 1962 intel_edp_backlight_off(intel_dp); 1963 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF); 1964 intel_edp_panel_off(intel_dp); 1965 1966 /* cpu edp my only be disable _after_ the cpu pipe/plane is disabled. */ 1967 if (!(port == PORT_A || IS_VALLEYVIEW(dev))) 1968 intel_dp_link_down(intel_dp); 1969} 1970 1971static void g4x_post_disable_dp(struct intel_encoder *encoder) 1972{ 1973 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); 1974 enum port port = dp_to_dig_port(intel_dp)->port; 1975 1976 if (port != PORT_A) 1977 return; 1978 1979 intel_dp_link_down(intel_dp); 1980 ironlake_edp_pll_off(intel_dp); 1981} 1982 1983static void vlv_post_disable_dp(struct intel_encoder *encoder) 1984{ 1985 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); 1986 1987 intel_dp_link_down(intel_dp); 1988} 1989 1990static void chv_post_disable_dp(struct intel_encoder *encoder) 1991{ 1992 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); 1993 struct intel_digital_port *dport = dp_to_dig_port(intel_dp); 1994 struct drm_device *dev = encoder->base.dev; 1995 struct drm_i915_private *dev_priv = dev->dev_private; 1996 struct intel_crtc *intel_crtc = 1997 to_intel_crtc(encoder->base.crtc); 1998 enum dpio_channel ch = vlv_dport_to_channel(dport); 1999 enum pipe pipe = intel_crtc->pipe; 2000 u32 val; 2001 2002 intel_dp_link_down(intel_dp); 2003 2004 mutex_lock(&dev_priv->dpio_lock); 2005 2006 /* Propagate soft reset to data lane reset */ 2007 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch)); 2008 val |= CHV_PCS_REQ_SOFTRESET_EN; 2009 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val); 2010 2011 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch)); 2012 val |= CHV_PCS_REQ_SOFTRESET_EN; 2013 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val); 2014 2015 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch)); 2016 val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET); 2017 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val); 2018 2019 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch)); 2020 val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET); 2021 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val); 2022 2023 mutex_unlock(&dev_priv->dpio_lock); 2024} 2025 2026static void intel_enable_dp(struct intel_encoder *encoder) 2027{ 2028 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); 2029 struct drm_device *dev = encoder->base.dev; 2030 struct drm_i915_private *dev_priv = dev->dev_private; 2031 uint32_t dp_reg = I915_READ(intel_dp->output_reg); 2032 2033 if (WARN_ON(dp_reg & DP_PORT_EN)) 2034 return; 2035 2036 intel_edp_panel_vdd_on(intel_dp); 2037 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON); 2038 intel_dp_start_link_train(intel_dp); 2039 intel_edp_panel_on(intel_dp); 2040 edp_panel_vdd_off(intel_dp, true); 2041 intel_dp_complete_link_train(intel_dp); 2042 intel_dp_stop_link_train(intel_dp); 2043} 2044 2045static void g4x_enable_dp(struct intel_encoder *encoder) 2046{ 2047 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); 2048 2049 intel_enable_dp(encoder); 2050 intel_edp_backlight_on(intel_dp); 2051} 2052 2053static void vlv_enable_dp(struct intel_encoder *encoder) 2054{ 2055 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); 2056 2057 intel_edp_backlight_on(intel_dp); 2058} 2059 2060static void g4x_pre_enable_dp(struct intel_encoder *encoder) 2061{ 2062 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); 2063 struct intel_digital_port *dport = dp_to_dig_port(intel_dp); 2064 2065 intel_dp_prepare(encoder); 2066 2067 /* Only ilk+ has port A */ 2068 if (dport->port == PORT_A) { 2069 ironlake_set_pll_cpu_edp(intel_dp); 2070 ironlake_edp_pll_on(intel_dp); 2071 } 2072} 2073 2074static void vlv_pre_enable_dp(struct intel_encoder *encoder) 2075{ 2076 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); 2077 struct intel_digital_port *dport = dp_to_dig_port(intel_dp); 2078 struct drm_device *dev = encoder->base.dev; 2079 struct drm_i915_private *dev_priv = dev->dev_private; 2080 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc); 2081 enum dpio_channel port = vlv_dport_to_channel(dport); 2082 int pipe = intel_crtc->pipe; 2083 struct edp_power_seq power_seq; 2084 u32 val; 2085 2086 mutex_lock(&dev_priv->dpio_lock); 2087 2088 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(port)); 2089 val = 0; 2090 if (pipe) 2091 val |= (1<<21); 2092 else 2093 val &= ~(1<<21); 2094 val |= 0x001000c4; 2095 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW8(port), val); 2096 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW14(port), 0x00760018); 2097 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW23(port), 0x00400888); 2098 2099 mutex_unlock(&dev_priv->dpio_lock); 2100 2101 if (is_edp(intel_dp)) { 2102 /* init power sequencer on this pipe and port */ 2103 intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq); 2104 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp, 2105 &power_seq); 2106 } 2107 2108 intel_enable_dp(encoder); 2109 2110 vlv_wait_port_ready(dev_priv, dport); 2111} 2112 2113static void vlv_dp_pre_pll_enable(struct intel_encoder *encoder) 2114{ 2115 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base); 2116 struct drm_device *dev = encoder->base.dev; 2117 struct drm_i915_private *dev_priv = dev->dev_private; 2118 struct intel_crtc *intel_crtc = 2119 to_intel_crtc(encoder->base.crtc); 2120 enum dpio_channel port = vlv_dport_to_channel(dport); 2121 int pipe = intel_crtc->pipe; 2122 2123 intel_dp_prepare(encoder); 2124 2125 /* Program Tx lane resets to default */ 2126 mutex_lock(&dev_priv->dpio_lock); 2127 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port), 2128 DPIO_PCS_TX_LANE2_RESET | 2129 DPIO_PCS_TX_LANE1_RESET); 2130 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port), 2131 DPIO_PCS_CLK_CRI_RXEB_EIOS_EN | 2132 DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN | 2133 (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT) | 2134 DPIO_PCS_CLK_SOFT_RESET); 2135 2136 /* Fix up inter-pair skew failure */ 2137 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW12(port), 0x00750f00); 2138 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW11(port), 0x00001500); 2139 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW14(port), 0x40400000); 2140 mutex_unlock(&dev_priv->dpio_lock); 2141} 2142 2143static void chv_pre_enable_dp(struct intel_encoder *encoder) 2144{ 2145 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); 2146 struct intel_digital_port *dport = dp_to_dig_port(intel_dp); 2147 struct drm_device *dev = encoder->base.dev; 2148 struct drm_i915_private *dev_priv = dev->dev_private; 2149 struct edp_power_seq power_seq; 2150 struct intel_crtc *intel_crtc = 2151 to_intel_crtc(encoder->base.crtc); 2152 enum dpio_channel ch = vlv_dport_to_channel(dport); 2153 int pipe = intel_crtc->pipe; 2154 int data, i; 2155 u32 val; 2156 2157 mutex_lock(&dev_priv->dpio_lock); 2158 2159 /* Deassert soft data lane reset*/ 2160 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch)); 2161 val |= CHV_PCS_REQ_SOFTRESET_EN; 2162 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val); 2163 2164 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch)); 2165 val |= CHV_PCS_REQ_SOFTRESET_EN; 2166 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val); 2167 2168 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch)); 2169 val |= (DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET); 2170 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val); 2171 2172 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch)); 2173 val |= (DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET); 2174 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val); 2175 2176 /* Program Tx lane latency optimal setting*/ 2177 for (i = 0; i < 4; i++) { 2178 /* Set the latency optimal bit */ 2179 data = (i == 1) ? 0x0 : 0x6; 2180 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW11(ch, i), 2181 data << DPIO_FRC_LATENCY_SHFIT); 2182 2183 /* Set the upar bit */ 2184 data = (i == 1) ? 0x0 : 0x1; 2185 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW14(ch, i), 2186 data << DPIO_UPAR_SHIFT); 2187 } 2188 2189 /* Data lane stagger programming */ 2190 /* FIXME: Fix up value only after power analysis */ 2191 2192 mutex_unlock(&dev_priv->dpio_lock); 2193 2194 if (is_edp(intel_dp)) { 2195 /* init power sequencer on this pipe and port */ 2196 intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq); 2197 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp, 2198 &power_seq); 2199 } 2200 2201 intel_enable_dp(encoder); 2202 2203 vlv_wait_port_ready(dev_priv, dport); 2204} 2205 2206static void chv_dp_pre_pll_enable(struct intel_encoder *encoder) 2207{ 2208 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base); 2209 struct drm_device *dev = encoder->base.dev; 2210 struct drm_i915_private *dev_priv = dev->dev_private; 2211 struct intel_crtc *intel_crtc = 2212 to_intel_crtc(encoder->base.crtc); 2213 enum dpio_channel ch = vlv_dport_to_channel(dport); 2214 enum pipe pipe = intel_crtc->pipe; 2215 u32 val; 2216 2217 mutex_lock(&dev_priv->dpio_lock); 2218 2219 /* program left/right clock distribution */ 2220 if (pipe != PIPE_B) { 2221 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0); 2222 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK); 2223 if (ch == DPIO_CH0) 2224 val |= CHV_BUFLEFTENA1_FORCE; 2225 if (ch == DPIO_CH1) 2226 val |= CHV_BUFRIGHTENA1_FORCE; 2227 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val); 2228 } else { 2229 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1); 2230 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK); 2231 if (ch == DPIO_CH0) 2232 val |= CHV_BUFLEFTENA2_FORCE; 2233 if (ch == DPIO_CH1) 2234 val |= CHV_BUFRIGHTENA2_FORCE; 2235 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val); 2236 } 2237 2238 /* program clock channel usage */ 2239 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(ch)); 2240 val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE; 2241 if (pipe != PIPE_B) 2242 val &= ~CHV_PCS_USEDCLKCHANNEL; 2243 else 2244 val |= CHV_PCS_USEDCLKCHANNEL; 2245 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW8(ch), val); 2246 2247 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW8(ch)); 2248 val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE; 2249 if (pipe != PIPE_B) 2250 val &= ~CHV_PCS_USEDCLKCHANNEL; 2251 else 2252 val |= CHV_PCS_USEDCLKCHANNEL; 2253 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW8(ch), val); 2254 2255 /* 2256 * This a a bit weird since generally CL 2257 * matches the pipe, but here we need to 2258 * pick the CL based on the port. 2259 */ 2260 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW19(ch)); 2261 if (pipe != PIPE_B) 2262 val &= ~CHV_CMN_USEDCLKCHANNEL; 2263 else 2264 val |= CHV_CMN_USEDCLKCHANNEL; 2265 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW19(ch), val); 2266 2267 mutex_unlock(&dev_priv->dpio_lock); 2268} 2269 2270/* 2271 * Native read with retry for link status and receiver capability reads for 2272 * cases where the sink may still be asleep. 2273 * 2274 * Sinks are *supposed* to come up within 1ms from an off state, but we're also 2275 * supposed to retry 3 times per the spec. 2276 */ 2277static ssize_t 2278intel_dp_dpcd_read_wake(struct drm_dp_aux *aux, unsigned int offset, 2279 void *buffer, size_t size) 2280{ 2281 ssize_t ret; 2282 int i; 2283 2284 for (i = 0; i < 3; i++) { 2285 ret = drm_dp_dpcd_read(aux, offset, buffer, size); 2286 if (ret == size) 2287 return ret; 2288 msleep(1); 2289 } 2290 2291 return ret; 2292} 2293 2294/* 2295 * Fetch AUX CH registers 0x202 - 0x207 which contain 2296 * link status information 2297 */ 2298static bool 2299intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE]) 2300{ 2301 return intel_dp_dpcd_read_wake(&intel_dp->aux, 2302 DP_LANE0_1_STATUS, 2303 link_status, 2304 DP_LINK_STATUS_SIZE) == DP_LINK_STATUS_SIZE; 2305} 2306 2307/* These are source-specific values. */ 2308static uint8_t 2309intel_dp_voltage_max(struct intel_dp *intel_dp) 2310{ 2311 struct drm_device *dev = intel_dp_to_dev(intel_dp); 2312 enum port port = dp_to_dig_port(intel_dp)->port; 2313 2314 if (IS_VALLEYVIEW(dev)) 2315 return DP_TRAIN_VOLTAGE_SWING_1200; 2316 else if (IS_GEN7(dev) && port == PORT_A) 2317 return DP_TRAIN_VOLTAGE_SWING_800; 2318 else if (HAS_PCH_CPT(dev) && port != PORT_A) 2319 return DP_TRAIN_VOLTAGE_SWING_1200; 2320 else 2321 return DP_TRAIN_VOLTAGE_SWING_800; 2322} 2323 2324static uint8_t 2325intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing) 2326{ 2327 struct drm_device *dev = intel_dp_to_dev(intel_dp); 2328 enum port port = dp_to_dig_port(intel_dp)->port; 2329 2330 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { 2331 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) { 2332 case DP_TRAIN_VOLTAGE_SWING_400: 2333 return DP_TRAIN_PRE_EMPHASIS_9_5; 2334 case DP_TRAIN_VOLTAGE_SWING_600: 2335 return DP_TRAIN_PRE_EMPHASIS_6; 2336 case DP_TRAIN_VOLTAGE_SWING_800: 2337 return DP_TRAIN_PRE_EMPHASIS_3_5; 2338 case DP_TRAIN_VOLTAGE_SWING_1200: 2339 default: 2340 return DP_TRAIN_PRE_EMPHASIS_0; 2341 } 2342 } else if (IS_VALLEYVIEW(dev)) { 2343 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) { 2344 case DP_TRAIN_VOLTAGE_SWING_400: 2345 return DP_TRAIN_PRE_EMPHASIS_9_5; 2346 case DP_TRAIN_VOLTAGE_SWING_600: 2347 return DP_TRAIN_PRE_EMPHASIS_6; 2348 case DP_TRAIN_VOLTAGE_SWING_800: 2349 return DP_TRAIN_PRE_EMPHASIS_3_5; 2350 case DP_TRAIN_VOLTAGE_SWING_1200: 2351 default: 2352 return DP_TRAIN_PRE_EMPHASIS_0; 2353 } 2354 } else if (IS_GEN7(dev) && port == PORT_A) { 2355 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) { 2356 case DP_TRAIN_VOLTAGE_SWING_400: 2357 return DP_TRAIN_PRE_EMPHASIS_6; 2358 case DP_TRAIN_VOLTAGE_SWING_600: 2359 case DP_TRAIN_VOLTAGE_SWING_800: 2360 return DP_TRAIN_PRE_EMPHASIS_3_5; 2361 default: 2362 return DP_TRAIN_PRE_EMPHASIS_0; 2363 } 2364 } else { 2365 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) { 2366 case DP_TRAIN_VOLTAGE_SWING_400: 2367 return DP_TRAIN_PRE_EMPHASIS_6; 2368 case DP_TRAIN_VOLTAGE_SWING_600: 2369 return DP_TRAIN_PRE_EMPHASIS_6; 2370 case DP_TRAIN_VOLTAGE_SWING_800: 2371 return DP_TRAIN_PRE_EMPHASIS_3_5; 2372 case DP_TRAIN_VOLTAGE_SWING_1200: 2373 default: 2374 return DP_TRAIN_PRE_EMPHASIS_0; 2375 } 2376 } 2377} 2378 2379static uint32_t intel_vlv_signal_levels(struct intel_dp *intel_dp) 2380{ 2381 struct drm_device *dev = intel_dp_to_dev(intel_dp); 2382 struct drm_i915_private *dev_priv = dev->dev_private; 2383 struct intel_digital_port *dport = dp_to_dig_port(intel_dp); 2384 struct intel_crtc *intel_crtc = 2385 to_intel_crtc(dport->base.base.crtc); 2386 unsigned long demph_reg_value, preemph_reg_value, 2387 uniqtranscale_reg_value; 2388 uint8_t train_set = intel_dp->train_set[0]; 2389 enum dpio_channel port = vlv_dport_to_channel(dport); 2390 int pipe = intel_crtc->pipe; 2391 2392 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) { 2393 case DP_TRAIN_PRE_EMPHASIS_0: 2394 preemph_reg_value = 0x0004000; 2395 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { 2396 case DP_TRAIN_VOLTAGE_SWING_400: 2397 demph_reg_value = 0x2B405555; 2398 uniqtranscale_reg_value = 0x552AB83A; 2399 break; 2400 case DP_TRAIN_VOLTAGE_SWING_600: 2401 demph_reg_value = 0x2B404040; 2402 uniqtranscale_reg_value = 0x5548B83A; 2403 break; 2404 case DP_TRAIN_VOLTAGE_SWING_800: 2405 demph_reg_value = 0x2B245555; 2406 uniqtranscale_reg_value = 0x5560B83A; 2407 break; 2408 case DP_TRAIN_VOLTAGE_SWING_1200: 2409 demph_reg_value = 0x2B405555; 2410 uniqtranscale_reg_value = 0x5598DA3A; 2411 break; 2412 default: 2413 return 0; 2414 } 2415 break; 2416 case DP_TRAIN_PRE_EMPHASIS_3_5: 2417 preemph_reg_value = 0x0002000; 2418 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { 2419 case DP_TRAIN_VOLTAGE_SWING_400: 2420 demph_reg_value = 0x2B404040; 2421 uniqtranscale_reg_value = 0x5552B83A; 2422 break; 2423 case DP_TRAIN_VOLTAGE_SWING_600: 2424 demph_reg_value = 0x2B404848; 2425 uniqtranscale_reg_value = 0x5580B83A; 2426 break; 2427 case DP_TRAIN_VOLTAGE_SWING_800: 2428 demph_reg_value = 0x2B404040; 2429 uniqtranscale_reg_value = 0x55ADDA3A; 2430 break; 2431 default: 2432 return 0; 2433 } 2434 break; 2435 case DP_TRAIN_PRE_EMPHASIS_6: 2436 preemph_reg_value = 0x0000000; 2437 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { 2438 case DP_TRAIN_VOLTAGE_SWING_400: 2439 demph_reg_value = 0x2B305555; 2440 uniqtranscale_reg_value = 0x5570B83A; 2441 break; 2442 case DP_TRAIN_VOLTAGE_SWING_600: 2443 demph_reg_value = 0x2B2B4040; 2444 uniqtranscale_reg_value = 0x55ADDA3A; 2445 break; 2446 default: 2447 return 0; 2448 } 2449 break; 2450 case DP_TRAIN_PRE_EMPHASIS_9_5: 2451 preemph_reg_value = 0x0006000; 2452 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { 2453 case DP_TRAIN_VOLTAGE_SWING_400: 2454 demph_reg_value = 0x1B405555; 2455 uniqtranscale_reg_value = 0x55ADDA3A; 2456 break; 2457 default: 2458 return 0; 2459 } 2460 break; 2461 default: 2462 return 0; 2463 } 2464 2465 mutex_lock(&dev_priv->dpio_lock); 2466 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x00000000); 2467 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW4(port), demph_reg_value); 2468 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(port), 2469 uniqtranscale_reg_value); 2470 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(port), 0x0C782040); 2471 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW11(port), 0x00030000); 2472 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), preemph_reg_value); 2473 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x80000000); 2474 mutex_unlock(&dev_priv->dpio_lock); 2475 2476 return 0; 2477} 2478 2479static uint32_t intel_chv_signal_levels(struct intel_dp *intel_dp) 2480{ 2481 struct drm_device *dev = intel_dp_to_dev(intel_dp); 2482 struct drm_i915_private *dev_priv = dev->dev_private; 2483 struct intel_digital_port *dport = dp_to_dig_port(intel_dp); 2484 struct intel_crtc *intel_crtc = to_intel_crtc(dport->base.base.crtc); 2485 u32 deemph_reg_value, margin_reg_value, val; 2486 uint8_t train_set = intel_dp->train_set[0]; 2487 enum dpio_channel ch = vlv_dport_to_channel(dport); 2488 enum pipe pipe = intel_crtc->pipe; 2489 int i; 2490 2491 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) { 2492 case DP_TRAIN_PRE_EMPHASIS_0: 2493 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { 2494 case DP_TRAIN_VOLTAGE_SWING_400: 2495 deemph_reg_value = 128; 2496 margin_reg_value = 52; 2497 break; 2498 case DP_TRAIN_VOLTAGE_SWING_600: 2499 deemph_reg_value = 128; 2500 margin_reg_value = 77; 2501 break; 2502 case DP_TRAIN_VOLTAGE_SWING_800: 2503 deemph_reg_value = 128; 2504 margin_reg_value = 102; 2505 break; 2506 case DP_TRAIN_VOLTAGE_SWING_1200: 2507 deemph_reg_value = 128; 2508 margin_reg_value = 154; 2509 /* FIXME extra to set for 1200 */ 2510 break; 2511 default: 2512 return 0; 2513 } 2514 break; 2515 case DP_TRAIN_PRE_EMPHASIS_3_5: 2516 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { 2517 case DP_TRAIN_VOLTAGE_SWING_400: 2518 deemph_reg_value = 85; 2519 margin_reg_value = 78; 2520 break; 2521 case DP_TRAIN_VOLTAGE_SWING_600: 2522 deemph_reg_value = 85; 2523 margin_reg_value = 116; 2524 break; 2525 case DP_TRAIN_VOLTAGE_SWING_800: 2526 deemph_reg_value = 85; 2527 margin_reg_value = 154; 2528 break; 2529 default: 2530 return 0; 2531 } 2532 break; 2533 case DP_TRAIN_PRE_EMPHASIS_6: 2534 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { 2535 case DP_TRAIN_VOLTAGE_SWING_400: 2536 deemph_reg_value = 64; 2537 margin_reg_value = 104; 2538 break; 2539 case DP_TRAIN_VOLTAGE_SWING_600: 2540 deemph_reg_value = 64; 2541 margin_reg_value = 154; 2542 break; 2543 default: 2544 return 0; 2545 } 2546 break; 2547 case DP_TRAIN_PRE_EMPHASIS_9_5: 2548 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { 2549 case DP_TRAIN_VOLTAGE_SWING_400: 2550 deemph_reg_value = 43; 2551 margin_reg_value = 154; 2552 break; 2553 default: 2554 return 0; 2555 } 2556 break; 2557 default: 2558 return 0; 2559 } 2560 2561 mutex_lock(&dev_priv->dpio_lock); 2562 2563 /* Clear calc init */ 2564 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch)); 2565 val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3); 2566 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val); 2567 2568 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch)); 2569 val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3); 2570 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val); 2571 2572 /* Program swing deemph */ 2573 for (i = 0; i < 4; i++) { 2574 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW4(ch, i)); 2575 val &= ~DPIO_SWING_DEEMPH9P5_MASK; 2576 val |= deemph_reg_value << DPIO_SWING_DEEMPH9P5_SHIFT; 2577 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW4(ch, i), val); 2578 } 2579 2580 /* Program swing margin */ 2581 for (i = 0; i < 4; i++) { 2582 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW2(ch, i)); 2583 val &= ~DPIO_SWING_MARGIN_MASK; 2584 val |= margin_reg_value << DPIO_SWING_MARGIN_SHIFT; 2585 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW2(ch, i), val); 2586 } 2587 2588 /* Disable unique transition scale */ 2589 for (i = 0; i < 4; i++) { 2590 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW3(ch, i)); 2591 val &= ~DPIO_TX_UNIQ_TRANS_SCALE_EN; 2592 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW3(ch, i), val); 2593 } 2594 2595 if (((train_set & DP_TRAIN_PRE_EMPHASIS_MASK) 2596 == DP_TRAIN_PRE_EMPHASIS_0) && 2597 ((train_set & DP_TRAIN_VOLTAGE_SWING_MASK) 2598 == DP_TRAIN_VOLTAGE_SWING_1200)) { 2599 2600 /* 2601 * The document said it needs to set bit 27 for ch0 and bit 26 2602 * for ch1. Might be a typo in the doc. 2603 * For now, for this unique transition scale selection, set bit 2604 * 27 for ch0 and ch1. 2605 */ 2606 for (i = 0; i < 4; i++) { 2607 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW3(ch, i)); 2608 val |= DPIO_TX_UNIQ_TRANS_SCALE_EN; 2609 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW3(ch, i), val); 2610 } 2611 2612 for (i = 0; i < 4; i++) { 2613 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW2(ch, i)); 2614 val &= ~(0xff << DPIO_UNIQ_TRANS_SCALE_SHIFT); 2615 val |= (0x9a << DPIO_UNIQ_TRANS_SCALE_SHIFT); 2616 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW2(ch, i), val); 2617 } 2618 } 2619 2620 /* Start swing calculation */ 2621 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch)); 2622 val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3; 2623 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val); 2624 2625 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch)); 2626 val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3; 2627 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val); 2628 2629 /* LRC Bypass */ 2630 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW30); 2631 val |= DPIO_LRC_BYPASS; 2632 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW30, val); 2633 2634 mutex_unlock(&dev_priv->dpio_lock); 2635 2636 return 0; 2637} 2638 2639static void 2640intel_get_adjust_train(struct intel_dp *intel_dp, 2641 const uint8_t link_status[DP_LINK_STATUS_SIZE]) 2642{ 2643 uint8_t v = 0; 2644 uint8_t p = 0; 2645 int lane; 2646 uint8_t voltage_max; 2647 uint8_t preemph_max; 2648 2649 for (lane = 0; lane < intel_dp->lane_count; lane++) { 2650 uint8_t this_v = drm_dp_get_adjust_request_voltage(link_status, lane); 2651 uint8_t this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane); 2652 2653 if (this_v > v) 2654 v = this_v; 2655 if (this_p > p) 2656 p = this_p; 2657 } 2658 2659 voltage_max = intel_dp_voltage_max(intel_dp); 2660 if (v >= voltage_max) 2661 v = voltage_max | DP_TRAIN_MAX_SWING_REACHED; 2662 2663 preemph_max = intel_dp_pre_emphasis_max(intel_dp, v); 2664 if (p >= preemph_max) 2665 p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED; 2666 2667 for (lane = 0; lane < 4; lane++) 2668 intel_dp->train_set[lane] = v | p; 2669} 2670 2671static uint32_t 2672intel_gen4_signal_levels(uint8_t train_set) 2673{ 2674 uint32_t signal_levels = 0; 2675 2676 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { 2677 case DP_TRAIN_VOLTAGE_SWING_400: 2678 default: 2679 signal_levels |= DP_VOLTAGE_0_4; 2680 break; 2681 case DP_TRAIN_VOLTAGE_SWING_600: 2682 signal_levels |= DP_VOLTAGE_0_6; 2683 break; 2684 case DP_TRAIN_VOLTAGE_SWING_800: 2685 signal_levels |= DP_VOLTAGE_0_8; 2686 break; 2687 case DP_TRAIN_VOLTAGE_SWING_1200: 2688 signal_levels |= DP_VOLTAGE_1_2; 2689 break; 2690 } 2691 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) { 2692 case DP_TRAIN_PRE_EMPHASIS_0: 2693 default: 2694 signal_levels |= DP_PRE_EMPHASIS_0; 2695 break; 2696 case DP_TRAIN_PRE_EMPHASIS_3_5: 2697 signal_levels |= DP_PRE_EMPHASIS_3_5; 2698 break; 2699 case DP_TRAIN_PRE_EMPHASIS_6: 2700 signal_levels |= DP_PRE_EMPHASIS_6; 2701 break; 2702 case DP_TRAIN_PRE_EMPHASIS_9_5: 2703 signal_levels |= DP_PRE_EMPHASIS_9_5; 2704 break; 2705 } 2706 return signal_levels; 2707} 2708 2709/* Gen6's DP voltage swing and pre-emphasis control */ 2710static uint32_t 2711intel_gen6_edp_signal_levels(uint8_t train_set) 2712{ 2713 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK | 2714 DP_TRAIN_PRE_EMPHASIS_MASK); 2715 switch (signal_levels) { 2716 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0: 2717 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0: 2718 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B; 2719 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5: 2720 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B; 2721 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6: 2722 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6: 2723 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B; 2724 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5: 2725 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5: 2726 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B; 2727 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0: 2728 case DP_TRAIN_VOLTAGE_SWING_1200 | DP_TRAIN_PRE_EMPHASIS_0: 2729 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B; 2730 default: 2731 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:" 2732 "0x%x\n", signal_levels); 2733 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B; 2734 } 2735} 2736 2737/* Gen7's DP voltage swing and pre-emphasis control */ 2738static uint32_t 2739intel_gen7_edp_signal_levels(uint8_t train_set) 2740{ 2741 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK | 2742 DP_TRAIN_PRE_EMPHASIS_MASK); 2743 switch (signal_levels) { 2744 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0: 2745 return EDP_LINK_TRAIN_400MV_0DB_IVB; 2746 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5: 2747 return EDP_LINK_TRAIN_400MV_3_5DB_IVB; 2748 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6: 2749 return EDP_LINK_TRAIN_400MV_6DB_IVB; 2750 2751 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0: 2752 return EDP_LINK_TRAIN_600MV_0DB_IVB; 2753 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5: 2754 return EDP_LINK_TRAIN_600MV_3_5DB_IVB; 2755 2756 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0: 2757 return EDP_LINK_TRAIN_800MV_0DB_IVB; 2758 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5: 2759 return EDP_LINK_TRAIN_800MV_3_5DB_IVB; 2760 2761 default: 2762 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:" 2763 "0x%x\n", signal_levels); 2764 return EDP_LINK_TRAIN_500MV_0DB_IVB; 2765 } 2766} 2767 2768/* Gen7.5's (HSW) DP voltage swing and pre-emphasis control */ 2769static uint32_t 2770intel_hsw_signal_levels(uint8_t train_set) 2771{ 2772 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK | 2773 DP_TRAIN_PRE_EMPHASIS_MASK); 2774 switch (signal_levels) { 2775 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0: 2776 return DDI_BUF_EMP_400MV_0DB_HSW; 2777 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5: 2778 return DDI_BUF_EMP_400MV_3_5DB_HSW; 2779 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6: 2780 return DDI_BUF_EMP_400MV_6DB_HSW; 2781 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_9_5: 2782 return DDI_BUF_EMP_400MV_9_5DB_HSW; 2783 2784 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0: 2785 return DDI_BUF_EMP_600MV_0DB_HSW; 2786 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5: 2787 return DDI_BUF_EMP_600MV_3_5DB_HSW; 2788 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6: 2789 return DDI_BUF_EMP_600MV_6DB_HSW; 2790 2791 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0: 2792 return DDI_BUF_EMP_800MV_0DB_HSW; 2793 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5: 2794 return DDI_BUF_EMP_800MV_3_5DB_HSW; 2795 default: 2796 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:" 2797 "0x%x\n", signal_levels); 2798 return DDI_BUF_EMP_400MV_0DB_HSW; 2799 } 2800} 2801 2802/* Properly updates "DP" with the correct signal levels. */ 2803static void 2804intel_dp_set_signal_levels(struct intel_dp *intel_dp, uint32_t *DP) 2805{ 2806 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 2807 enum port port = intel_dig_port->port; 2808 struct drm_device *dev = intel_dig_port->base.base.dev; 2809 uint32_t signal_levels, mask; 2810 uint8_t train_set = intel_dp->train_set[0]; 2811 2812 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { 2813 signal_levels = intel_hsw_signal_levels(train_set); 2814 mask = DDI_BUF_EMP_MASK; 2815 } else if (IS_CHERRYVIEW(dev)) { 2816 signal_levels = intel_chv_signal_levels(intel_dp); 2817 mask = 0; 2818 } else if (IS_VALLEYVIEW(dev)) { 2819 signal_levels = intel_vlv_signal_levels(intel_dp); 2820 mask = 0; 2821 } else if (IS_GEN7(dev) && port == PORT_A) { 2822 signal_levels = intel_gen7_edp_signal_levels(train_set); 2823 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_IVB; 2824 } else if (IS_GEN6(dev) && port == PORT_A) { 2825 signal_levels = intel_gen6_edp_signal_levels(train_set); 2826 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB; 2827 } else { 2828 signal_levels = intel_gen4_signal_levels(train_set); 2829 mask = DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK; 2830 } 2831 2832 DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels); 2833 2834 *DP = (*DP & ~mask) | signal_levels; 2835} 2836 2837static bool 2838intel_dp_set_link_train(struct intel_dp *intel_dp, 2839 uint32_t *DP, 2840 uint8_t dp_train_pat) 2841{ 2842 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 2843 struct drm_device *dev = intel_dig_port->base.base.dev; 2844 struct drm_i915_private *dev_priv = dev->dev_private; 2845 enum port port = intel_dig_port->port; 2846 uint8_t buf[sizeof(intel_dp->train_set) + 1]; 2847 int ret, len; 2848 2849 if (HAS_DDI(dev)) { 2850 uint32_t temp = I915_READ(DP_TP_CTL(port)); 2851 2852 if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE) 2853 temp |= DP_TP_CTL_SCRAMBLE_DISABLE; 2854 else 2855 temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE; 2856 2857 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK; 2858 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) { 2859 case DP_TRAINING_PATTERN_DISABLE: 2860 temp |= DP_TP_CTL_LINK_TRAIN_NORMAL; 2861 2862 break; 2863 case DP_TRAINING_PATTERN_1: 2864 temp |= DP_TP_CTL_LINK_TRAIN_PAT1; 2865 break; 2866 case DP_TRAINING_PATTERN_2: 2867 temp |= DP_TP_CTL_LINK_TRAIN_PAT2; 2868 break; 2869 case DP_TRAINING_PATTERN_3: 2870 temp |= DP_TP_CTL_LINK_TRAIN_PAT3; 2871 break; 2872 } 2873 I915_WRITE(DP_TP_CTL(port), temp); 2874 2875 } else if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) { 2876 *DP &= ~DP_LINK_TRAIN_MASK_CPT; 2877 2878 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) { 2879 case DP_TRAINING_PATTERN_DISABLE: 2880 *DP |= DP_LINK_TRAIN_OFF_CPT; 2881 break; 2882 case DP_TRAINING_PATTERN_1: 2883 *DP |= DP_LINK_TRAIN_PAT_1_CPT; 2884 break; 2885 case DP_TRAINING_PATTERN_2: 2886 *DP |= DP_LINK_TRAIN_PAT_2_CPT; 2887 break; 2888 case DP_TRAINING_PATTERN_3: 2889 DRM_ERROR("DP training pattern 3 not supported\n"); 2890 *DP |= DP_LINK_TRAIN_PAT_2_CPT; 2891 break; 2892 } 2893 2894 } else { 2895 *DP &= ~DP_LINK_TRAIN_MASK; 2896 2897 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) { 2898 case DP_TRAINING_PATTERN_DISABLE: 2899 *DP |= DP_LINK_TRAIN_OFF; 2900 break; 2901 case DP_TRAINING_PATTERN_1: 2902 *DP |= DP_LINK_TRAIN_PAT_1; 2903 break; 2904 case DP_TRAINING_PATTERN_2: 2905 *DP |= DP_LINK_TRAIN_PAT_2; 2906 break; 2907 case DP_TRAINING_PATTERN_3: 2908 DRM_ERROR("DP training pattern 3 not supported\n"); 2909 *DP |= DP_LINK_TRAIN_PAT_2; 2910 break; 2911 } 2912 } 2913 2914 I915_WRITE(intel_dp->output_reg, *DP); 2915 POSTING_READ(intel_dp->output_reg); 2916 2917 buf[0] = dp_train_pat; 2918 if ((dp_train_pat & DP_TRAINING_PATTERN_MASK) == 2919 DP_TRAINING_PATTERN_DISABLE) { 2920 /* don't write DP_TRAINING_LANEx_SET on disable */ 2921 len = 1; 2922 } else { 2923 /* DP_TRAINING_LANEx_SET follow DP_TRAINING_PATTERN_SET */ 2924 memcpy(buf + 1, intel_dp->train_set, intel_dp->lane_count); 2925 len = intel_dp->lane_count + 1; 2926 } 2927 2928 ret = drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_PATTERN_SET, 2929 buf, len); 2930 2931 return ret == len; 2932} 2933 2934static bool 2935intel_dp_reset_link_train(struct intel_dp *intel_dp, uint32_t *DP, 2936 uint8_t dp_train_pat) 2937{ 2938 memset(intel_dp->train_set, 0, sizeof(intel_dp->train_set)); 2939 intel_dp_set_signal_levels(intel_dp, DP); 2940 return intel_dp_set_link_train(intel_dp, DP, dp_train_pat); 2941} 2942 2943static bool 2944intel_dp_update_link_train(struct intel_dp *intel_dp, uint32_t *DP, 2945 const uint8_t link_status[DP_LINK_STATUS_SIZE]) 2946{ 2947 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 2948 struct drm_device *dev = intel_dig_port->base.base.dev; 2949 struct drm_i915_private *dev_priv = dev->dev_private; 2950 int ret; 2951 2952 intel_get_adjust_train(intel_dp, link_status); 2953 intel_dp_set_signal_levels(intel_dp, DP); 2954 2955 I915_WRITE(intel_dp->output_reg, *DP); 2956 POSTING_READ(intel_dp->output_reg); 2957 2958 ret = drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_LANE0_SET, 2959 intel_dp->train_set, intel_dp->lane_count); 2960 2961 return ret == intel_dp->lane_count; 2962} 2963 2964static void intel_dp_set_idle_link_train(struct intel_dp *intel_dp) 2965{ 2966 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 2967 struct drm_device *dev = intel_dig_port->base.base.dev; 2968 struct drm_i915_private *dev_priv = dev->dev_private; 2969 enum port port = intel_dig_port->port; 2970 uint32_t val; 2971 2972 if (!HAS_DDI(dev)) 2973 return; 2974 2975 val = I915_READ(DP_TP_CTL(port)); 2976 val &= ~DP_TP_CTL_LINK_TRAIN_MASK; 2977 val |= DP_TP_CTL_LINK_TRAIN_IDLE; 2978 I915_WRITE(DP_TP_CTL(port), val); 2979 2980 /* 2981 * On PORT_A we can have only eDP in SST mode. There the only reason 2982 * we need to set idle transmission mode is to work around a HW issue 2983 * where we enable the pipe while not in idle link-training mode. 2984 * In this case there is requirement to wait for a minimum number of 2985 * idle patterns to be sent. 2986 */ 2987 if (port == PORT_A) 2988 return; 2989 2990 if (wait_for((I915_READ(DP_TP_STATUS(port)) & DP_TP_STATUS_IDLE_DONE), 2991 1)) 2992 DRM_ERROR("Timed out waiting for DP idle patterns\n"); 2993} 2994 2995/* Enable corresponding port and start training pattern 1 */ 2996void 2997intel_dp_start_link_train(struct intel_dp *intel_dp) 2998{ 2999 struct drm_encoder *encoder = &dp_to_dig_port(intel_dp)->base.base; 3000 struct drm_device *dev = encoder->dev; 3001 int i; 3002 uint8_t voltage; 3003 int voltage_tries, loop_tries; 3004 uint32_t DP = intel_dp->DP; 3005 uint8_t link_config[2]; 3006 3007 if (HAS_DDI(dev)) 3008 intel_ddi_prepare_link_retrain(encoder); 3009 3010 /* Write the link configuration data */ 3011 link_config[0] = intel_dp->link_bw; 3012 link_config[1] = intel_dp->lane_count; 3013 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd)) 3014 link_config[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN; 3015 drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_BW_SET, link_config, 2); 3016 3017 link_config[0] = 0; 3018 link_config[1] = DP_SET_ANSI_8B10B; 3019 drm_dp_dpcd_write(&intel_dp->aux, DP_DOWNSPREAD_CTRL, link_config, 2); 3020 3021 DP |= DP_PORT_EN; 3022 3023 /* clock recovery */ 3024 if (!intel_dp_reset_link_train(intel_dp, &DP, 3025 DP_TRAINING_PATTERN_1 | 3026 DP_LINK_SCRAMBLING_DISABLE)) { 3027 DRM_ERROR("failed to enable link training\n"); 3028 return; 3029 } 3030 3031 voltage = 0xff; 3032 voltage_tries = 0; 3033 loop_tries = 0; 3034 for (;;) { 3035 uint8_t link_status[DP_LINK_STATUS_SIZE]; 3036 3037 drm_dp_link_train_clock_recovery_delay(intel_dp->dpcd); 3038 if (!intel_dp_get_link_status(intel_dp, link_status)) { 3039 DRM_ERROR("failed to get link status\n"); 3040 break; 3041 } 3042 3043 if (drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) { 3044 DRM_DEBUG_KMS("clock recovery OK\n"); 3045 break; 3046 } 3047 3048 /* Check to see if we've tried the max voltage */ 3049 for (i = 0; i < intel_dp->lane_count; i++) 3050 if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0) 3051 break; 3052 if (i == intel_dp->lane_count) { 3053 ++loop_tries; 3054 if (loop_tries == 5) { 3055 DRM_ERROR("too many full retries, give up\n"); 3056 break; 3057 } 3058 intel_dp_reset_link_train(intel_dp, &DP, 3059 DP_TRAINING_PATTERN_1 | 3060 DP_LINK_SCRAMBLING_DISABLE); 3061 voltage_tries = 0; 3062 continue; 3063 } 3064 3065 /* Check to see if we've tried the same voltage 5 times */ 3066 if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) { 3067 ++voltage_tries; 3068 if (voltage_tries == 5) { 3069 DRM_ERROR("too many voltage retries, give up\n"); 3070 break; 3071 } 3072 } else 3073 voltage_tries = 0; 3074 voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK; 3075 3076 /* Update training set as requested by target */ 3077 if (!intel_dp_update_link_train(intel_dp, &DP, link_status)) { 3078 DRM_ERROR("failed to update link training\n"); 3079 break; 3080 } 3081 } 3082 3083 intel_dp->DP = DP; 3084} 3085 3086void 3087intel_dp_complete_link_train(struct intel_dp *intel_dp) 3088{ 3089 bool channel_eq = false; 3090 int tries, cr_tries; 3091 uint32_t DP = intel_dp->DP; 3092 uint32_t training_pattern = DP_TRAINING_PATTERN_2; 3093 3094 /* Training Pattern 3 for HBR2 ot 1.2 devices that support it*/ 3095 if (intel_dp->link_bw == DP_LINK_BW_5_4 || intel_dp->use_tps3) 3096 training_pattern = DP_TRAINING_PATTERN_3; 3097 3098 /* channel equalization */ 3099 if (!intel_dp_set_link_train(intel_dp, &DP, 3100 training_pattern | 3101 DP_LINK_SCRAMBLING_DISABLE)) { 3102 DRM_ERROR("failed to start channel equalization\n"); 3103 return; 3104 } 3105 3106 tries = 0; 3107 cr_tries = 0; 3108 channel_eq = false; 3109 for (;;) { 3110 uint8_t link_status[DP_LINK_STATUS_SIZE]; 3111 3112 if (cr_tries > 5) { 3113 DRM_ERROR("failed to train DP, aborting\n"); 3114 break; 3115 } 3116 3117 drm_dp_link_train_channel_eq_delay(intel_dp->dpcd); 3118 if (!intel_dp_get_link_status(intel_dp, link_status)) { 3119 DRM_ERROR("failed to get link status\n"); 3120 break; 3121 } 3122 3123 /* Make sure clock is still ok */ 3124 if (!drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) { 3125 intel_dp_start_link_train(intel_dp); 3126 intel_dp_set_link_train(intel_dp, &DP, 3127 training_pattern | 3128 DP_LINK_SCRAMBLING_DISABLE); 3129 cr_tries++; 3130 continue; 3131 } 3132 3133 if (drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) { 3134 channel_eq = true; 3135 break; 3136 } 3137 3138 /* Try 5 times, then try clock recovery if that fails */ 3139 if (tries > 5) { 3140 intel_dp_link_down(intel_dp); 3141 intel_dp_start_link_train(intel_dp); 3142 intel_dp_set_link_train(intel_dp, &DP, 3143 training_pattern | 3144 DP_LINK_SCRAMBLING_DISABLE); 3145 tries = 0; 3146 cr_tries++; 3147 continue; 3148 } 3149 3150 /* Update training set as requested by target */ 3151 if (!intel_dp_update_link_train(intel_dp, &DP, link_status)) { 3152 DRM_ERROR("failed to update link training\n"); 3153 break; 3154 } 3155 ++tries; 3156 } 3157 3158 intel_dp_set_idle_link_train(intel_dp); 3159 3160 intel_dp->DP = DP; 3161 3162 if (channel_eq) 3163 DRM_DEBUG_KMS("Channel EQ done. DP Training successful\n"); 3164 3165} 3166 3167void intel_dp_stop_link_train(struct intel_dp *intel_dp) 3168{ 3169 intel_dp_set_link_train(intel_dp, &intel_dp->DP, 3170 DP_TRAINING_PATTERN_DISABLE); 3171} 3172 3173static void 3174intel_dp_link_down(struct intel_dp *intel_dp) 3175{ 3176 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 3177 enum port port = intel_dig_port->port; 3178 struct drm_device *dev = intel_dig_port->base.base.dev; 3179 struct drm_i915_private *dev_priv = dev->dev_private; 3180 struct intel_crtc *intel_crtc = 3181 to_intel_crtc(intel_dig_port->base.base.crtc); 3182 uint32_t DP = intel_dp->DP; 3183 3184 if (WARN_ON(HAS_DDI(dev))) 3185 return; 3186 3187 if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0)) 3188 return; 3189 3190 DRM_DEBUG_KMS("\n"); 3191 3192 if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) { 3193 DP &= ~DP_LINK_TRAIN_MASK_CPT; 3194 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT); 3195 } else { 3196 DP &= ~DP_LINK_TRAIN_MASK; 3197 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE); 3198 } 3199 POSTING_READ(intel_dp->output_reg); 3200 3201 if (HAS_PCH_IBX(dev) && 3202 I915_READ(intel_dp->output_reg) & DP_PIPEB_SELECT) { 3203 struct drm_crtc *crtc = intel_dig_port->base.base.crtc; 3204 3205 /* Hardware workaround: leaving our transcoder select 3206 * set to transcoder B while it's off will prevent the 3207 * corresponding HDMI output on transcoder A. 3208 * 3209 * Combine this with another hardware workaround: 3210 * transcoder select bit can only be cleared while the 3211 * port is enabled. 3212 */ 3213 DP &= ~DP_PIPEB_SELECT; 3214 I915_WRITE(intel_dp->output_reg, DP); 3215 3216 /* Changes to enable or select take place the vblank 3217 * after being written. 3218 */ 3219 if (WARN_ON(crtc == NULL)) { 3220 /* We should never try to disable a port without a crtc 3221 * attached. For paranoia keep the code around for a 3222 * bit. */ 3223 POSTING_READ(intel_dp->output_reg); 3224 msleep(50); 3225 } else 3226 intel_wait_for_vblank(dev, intel_crtc->pipe); 3227 } 3228 3229 DP &= ~DP_AUDIO_OUTPUT_ENABLE; 3230 I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN); 3231 POSTING_READ(intel_dp->output_reg); 3232 msleep(intel_dp->panel_power_down_delay); 3233} 3234 3235static bool 3236intel_dp_get_dpcd(struct intel_dp *intel_dp) 3237{ 3238 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 3239 struct drm_device *dev = dig_port->base.base.dev; 3240 struct drm_i915_private *dev_priv = dev->dev_private; 3241 3242 char dpcd_hex_dump[sizeof(intel_dp->dpcd) * 3]; 3243 3244 if (intel_dp_dpcd_read_wake(&intel_dp->aux, 0x000, intel_dp->dpcd, 3245 sizeof(intel_dp->dpcd)) < 0) 3246 return false; /* aux transfer failed */ 3247 3248 hex_dump_to_buffer(intel_dp->dpcd, sizeof(intel_dp->dpcd), 3249 32, 1, dpcd_hex_dump, sizeof(dpcd_hex_dump), false); 3250 DRM_DEBUG_KMS("DPCD: %s\n", dpcd_hex_dump); 3251 3252 if (intel_dp->dpcd[DP_DPCD_REV] == 0) 3253 return false; /* DPCD not present */ 3254 3255 /* Check if the panel supports PSR */ 3256 memset(intel_dp->psr_dpcd, 0, sizeof(intel_dp->psr_dpcd)); 3257 if (is_edp(intel_dp)) { 3258 intel_dp_dpcd_read_wake(&intel_dp->aux, DP_PSR_SUPPORT, 3259 intel_dp->psr_dpcd, 3260 sizeof(intel_dp->psr_dpcd)); 3261 if (intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED) { 3262 dev_priv->psr.sink_support = true; 3263 DRM_DEBUG_KMS("Detected EDP PSR Panel.\n"); 3264 } 3265 } 3266 3267 /* Training Pattern 3 support */ 3268 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x12 && 3269 intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_TPS3_SUPPORTED) { 3270 intel_dp->use_tps3 = true; 3271 DRM_DEBUG_KMS("Displayport TPS3 supported"); 3272 } else 3273 intel_dp->use_tps3 = false; 3274 3275 if (!(intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] & 3276 DP_DWN_STRM_PORT_PRESENT)) 3277 return true; /* native DP sink */ 3278 3279 if (intel_dp->dpcd[DP_DPCD_REV] == 0x10) 3280 return true; /* no per-port downstream info */ 3281 3282 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_DOWNSTREAM_PORT_0, 3283 intel_dp->downstream_ports, 3284 DP_MAX_DOWNSTREAM_PORTS) < 0) 3285 return false; /* downstream port status fetch failed */ 3286 3287 return true; 3288} 3289 3290static void 3291intel_dp_probe_oui(struct intel_dp *intel_dp) 3292{ 3293 u8 buf[3]; 3294 3295 if (!(intel_dp->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT)) 3296 return; 3297 3298 intel_edp_panel_vdd_on(intel_dp); 3299 3300 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_SINK_OUI, buf, 3) == 3) 3301 DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n", 3302 buf[0], buf[1], buf[2]); 3303 3304 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_BRANCH_OUI, buf, 3) == 3) 3305 DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n", 3306 buf[0], buf[1], buf[2]); 3307 3308 edp_panel_vdd_off(intel_dp, false); 3309} 3310 3311int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc) 3312{ 3313 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 3314 struct drm_device *dev = intel_dig_port->base.base.dev; 3315 struct intel_crtc *intel_crtc = 3316 to_intel_crtc(intel_dig_port->base.base.crtc); 3317 u8 buf[1]; 3318 3319 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK_MISC, buf) < 0) 3320 return -EAGAIN; 3321 3322 if (!(buf[0] & DP_TEST_CRC_SUPPORTED)) 3323 return -ENOTTY; 3324 3325 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK, 3326 DP_TEST_SINK_START) < 0) 3327 return -EAGAIN; 3328 3329 /* Wait 2 vblanks to be sure we will have the correct CRC value */ 3330 intel_wait_for_vblank(dev, intel_crtc->pipe); 3331 intel_wait_for_vblank(dev, intel_crtc->pipe); 3332 3333 if (drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_CRC_R_CR, crc, 6) < 0) 3334 return -EAGAIN; 3335 3336 drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK, 0); 3337 return 0; 3338} 3339 3340static bool 3341intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector) 3342{ 3343 return intel_dp_dpcd_read_wake(&intel_dp->aux, 3344 DP_DEVICE_SERVICE_IRQ_VECTOR, 3345 sink_irq_vector, 1) == 1; 3346} 3347 3348static void 3349intel_dp_handle_test_request(struct intel_dp *intel_dp) 3350{ 3351 /* NAK by default */ 3352 drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_RESPONSE, DP_TEST_NAK); 3353} 3354 3355/* 3356 * According to DP spec 3357 * 5.1.2: 3358 * 1. Read DPCD 3359 * 2. Configure link according to Receiver Capabilities 3360 * 3. Use Link Training from 2.5.3.3 and 3.5.1.3 3361 * 4. Check link status on receipt of hot-plug interrupt 3362 */ 3363 3364void 3365intel_dp_check_link_status(struct intel_dp *intel_dp) 3366{ 3367 struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base; 3368 u8 sink_irq_vector; 3369 u8 link_status[DP_LINK_STATUS_SIZE]; 3370 3371 /* FIXME: This access isn't protected by any locks. */ 3372 if (!intel_encoder->connectors_active) 3373 return; 3374 3375 if (WARN_ON(!intel_encoder->base.crtc)) 3376 return; 3377 3378 /* Try to read receiver status if the link appears to be up */ 3379 if (!intel_dp_get_link_status(intel_dp, link_status)) { 3380 return; 3381 } 3382 3383 /* Now read the DPCD to see if it's actually running */ 3384 if (!intel_dp_get_dpcd(intel_dp)) { 3385 return; 3386 } 3387 3388 /* Try to read the source of the interrupt */ 3389 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 && 3390 intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) { 3391 /* Clear interrupt source */ 3392 drm_dp_dpcd_writeb(&intel_dp->aux, 3393 DP_DEVICE_SERVICE_IRQ_VECTOR, 3394 sink_irq_vector); 3395 3396 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST) 3397 intel_dp_handle_test_request(intel_dp); 3398 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ)) 3399 DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n"); 3400 } 3401 3402 if (!drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) { 3403 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n", 3404 intel_encoder->base.name); 3405 intel_dp_start_link_train(intel_dp); 3406 intel_dp_complete_link_train(intel_dp); 3407 intel_dp_stop_link_train(intel_dp); 3408 } 3409} 3410 3411/* XXX this is probably wrong for multiple downstream ports */ 3412static enum drm_connector_status 3413intel_dp_detect_dpcd(struct intel_dp *intel_dp) 3414{ 3415 uint8_t *dpcd = intel_dp->dpcd; 3416 uint8_t type; 3417 3418 if (!intel_dp_get_dpcd(intel_dp)) 3419 return connector_status_disconnected; 3420 3421 /* if there's no downstream port, we're done */ 3422 if (!(dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT)) 3423 return connector_status_connected; 3424 3425 /* If we're HPD-aware, SINK_COUNT changes dynamically */ 3426 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 && 3427 intel_dp->downstream_ports[0] & DP_DS_PORT_HPD) { 3428 uint8_t reg; 3429 3430 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_SINK_COUNT, 3431 ®, 1) < 0) 3432 return connector_status_unknown; 3433 3434 return DP_GET_SINK_COUNT(reg) ? connector_status_connected 3435 : connector_status_disconnected; 3436 } 3437 3438 /* If no HPD, poke DDC gently */ 3439 if (drm_probe_ddc(&intel_dp->aux.ddc)) 3440 return connector_status_connected; 3441 3442 /* Well we tried, say unknown for unreliable port types */ 3443 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) { 3444 type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK; 3445 if (type == DP_DS_PORT_TYPE_VGA || 3446 type == DP_DS_PORT_TYPE_NON_EDID) 3447 return connector_status_unknown; 3448 } else { 3449 type = intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] & 3450 DP_DWN_STRM_PORT_TYPE_MASK; 3451 if (type == DP_DWN_STRM_PORT_TYPE_ANALOG || 3452 type == DP_DWN_STRM_PORT_TYPE_OTHER) 3453 return connector_status_unknown; 3454 } 3455 3456 /* Anything else is out of spec, warn and ignore */ 3457 DRM_DEBUG_KMS("Broken DP branch device, ignoring\n"); 3458 return connector_status_disconnected; 3459} 3460 3461static enum drm_connector_status 3462ironlake_dp_detect(struct intel_dp *intel_dp) 3463{ 3464 struct drm_device *dev = intel_dp_to_dev(intel_dp); 3465 struct drm_i915_private *dev_priv = dev->dev_private; 3466 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 3467 enum drm_connector_status status; 3468 3469 /* Can't disconnect eDP, but you can close the lid... */ 3470 if (is_edp(intel_dp)) { 3471 status = intel_panel_detect(dev); 3472 if (status == connector_status_unknown) 3473 status = connector_status_connected; 3474 return status; 3475 } 3476 3477 if (!ibx_digital_port_connected(dev_priv, intel_dig_port)) 3478 return connector_status_disconnected; 3479 3480 return intel_dp_detect_dpcd(intel_dp); 3481} 3482 3483static enum drm_connector_status 3484g4x_dp_detect(struct intel_dp *intel_dp) 3485{ 3486 struct drm_device *dev = intel_dp_to_dev(intel_dp); 3487 struct drm_i915_private *dev_priv = dev->dev_private; 3488 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 3489 uint32_t bit; 3490 3491 /* Can't disconnect eDP, but you can close the lid... */ 3492 if (is_edp(intel_dp)) { 3493 enum drm_connector_status status; 3494 3495 status = intel_panel_detect(dev); 3496 if (status == connector_status_unknown) 3497 status = connector_status_connected; 3498 return status; 3499 } 3500 3501 if (IS_VALLEYVIEW(dev)) { 3502 switch (intel_dig_port->port) { 3503 case PORT_B: 3504 bit = PORTB_HOTPLUG_LIVE_STATUS_VLV; 3505 break; 3506 case PORT_C: 3507 bit = PORTC_HOTPLUG_LIVE_STATUS_VLV; 3508 break; 3509 case PORT_D: 3510 bit = PORTD_HOTPLUG_LIVE_STATUS_VLV; 3511 break; 3512 default: 3513 return connector_status_unknown; 3514 } 3515 } else { 3516 switch (intel_dig_port->port) { 3517 case PORT_B: 3518 bit = PORTB_HOTPLUG_LIVE_STATUS_G4X; 3519 break; 3520 case PORT_C: 3521 bit = PORTC_HOTPLUG_LIVE_STATUS_G4X; 3522 break; 3523 case PORT_D: 3524 bit = PORTD_HOTPLUG_LIVE_STATUS_G4X; 3525 break; 3526 default: 3527 return connector_status_unknown; 3528 } 3529 } 3530 3531 if ((I915_READ(PORT_HOTPLUG_STAT) & bit) == 0) 3532 return connector_status_disconnected; 3533 3534 return intel_dp_detect_dpcd(intel_dp); 3535} 3536 3537static struct edid * 3538intel_dp_get_edid(struct drm_connector *connector, struct i2c_adapter *adapter) 3539{ 3540 struct intel_connector *intel_connector = to_intel_connector(connector); 3541 3542 /* use cached edid if we have one */ 3543 if (intel_connector->edid) { 3544 /* invalid edid */ 3545 if (IS_ERR(intel_connector->edid)) 3546 return NULL; 3547 3548 return drm_edid_duplicate(intel_connector->edid); 3549 } 3550 3551 return drm_get_edid(connector, adapter); 3552} 3553 3554static int 3555intel_dp_get_edid_modes(struct drm_connector *connector, struct i2c_adapter *adapter) 3556{ 3557 struct intel_connector *intel_connector = to_intel_connector(connector); 3558 3559 /* use cached edid if we have one */ 3560 if (intel_connector->edid) { 3561 /* invalid edid */ 3562 if (IS_ERR(intel_connector->edid)) 3563 return 0; 3564 3565 return intel_connector_update_modes(connector, 3566 intel_connector->edid); 3567 } 3568 3569 return intel_ddc_get_modes(connector, adapter); 3570} 3571 3572static enum drm_connector_status 3573intel_dp_detect(struct drm_connector *connector, bool force) 3574{ 3575 struct intel_dp *intel_dp = intel_attached_dp(connector); 3576 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 3577 struct intel_encoder *intel_encoder = &intel_dig_port->base; 3578 struct drm_device *dev = connector->dev; 3579 struct drm_i915_private *dev_priv = dev->dev_private; 3580 enum drm_connector_status status; 3581 enum intel_display_power_domain power_domain; 3582 struct edid *edid = NULL; 3583 3584 intel_runtime_pm_get(dev_priv); 3585 3586 power_domain = intel_display_port_power_domain(intel_encoder); 3587 intel_display_power_get(dev_priv, power_domain); 3588 3589 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", 3590 connector->base.id, connector->name); 3591 3592 intel_dp->has_audio = false; 3593 3594 if (HAS_PCH_SPLIT(dev)) 3595 status = ironlake_dp_detect(intel_dp); 3596 else 3597 status = g4x_dp_detect(intel_dp); 3598 3599 if (status != connector_status_connected) 3600 goto out; 3601 3602 intel_dp_probe_oui(intel_dp); 3603 3604 if (intel_dp->force_audio != HDMI_AUDIO_AUTO) { 3605 intel_dp->has_audio = (intel_dp->force_audio == HDMI_AUDIO_ON); 3606 } else { 3607 edid = intel_dp_get_edid(connector, &intel_dp->aux.ddc); 3608 if (edid) { 3609 intel_dp->has_audio = drm_detect_monitor_audio(edid); 3610 kfree(edid); 3611 } 3612 } 3613 3614 if (intel_encoder->type != INTEL_OUTPUT_EDP) 3615 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT; 3616 status = connector_status_connected; 3617 3618out: 3619 intel_display_power_put(dev_priv, power_domain); 3620 3621 intel_runtime_pm_put(dev_priv); 3622 3623 return status; 3624} 3625 3626static int intel_dp_get_modes(struct drm_connector *connector) 3627{ 3628 struct intel_dp *intel_dp = intel_attached_dp(connector); 3629 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 3630 struct intel_encoder *intel_encoder = &intel_dig_port->base; 3631 struct intel_connector *intel_connector = to_intel_connector(connector); 3632 struct drm_device *dev = connector->dev; 3633 struct drm_i915_private *dev_priv = dev->dev_private; 3634 enum intel_display_power_domain power_domain; 3635 int ret; 3636 3637 /* We should parse the EDID data and find out if it has an audio sink 3638 */ 3639 3640 power_domain = intel_display_port_power_domain(intel_encoder); 3641 intel_display_power_get(dev_priv, power_domain); 3642 3643 ret = intel_dp_get_edid_modes(connector, &intel_dp->aux.ddc); 3644 intel_display_power_put(dev_priv, power_domain); 3645 if (ret) 3646 return ret; 3647 3648 /* if eDP has no EDID, fall back to fixed mode */ 3649 if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) { 3650 struct drm_display_mode *mode; 3651 mode = drm_mode_duplicate(dev, 3652 intel_connector->panel.fixed_mode); 3653 if (mode) { 3654 drm_mode_probed_add(connector, mode); 3655 return 1; 3656 } 3657 } 3658 return 0; 3659} 3660 3661static bool 3662intel_dp_detect_audio(struct drm_connector *connector) 3663{ 3664 struct intel_dp *intel_dp = intel_attached_dp(connector); 3665 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 3666 struct intel_encoder *intel_encoder = &intel_dig_port->base; 3667 struct drm_device *dev = connector->dev; 3668 struct drm_i915_private *dev_priv = dev->dev_private; 3669 enum intel_display_power_domain power_domain; 3670 struct edid *edid; 3671 bool has_audio = false; 3672 3673 power_domain = intel_display_port_power_domain(intel_encoder); 3674 intel_display_power_get(dev_priv, power_domain); 3675 3676 edid = intel_dp_get_edid(connector, &intel_dp->aux.ddc); 3677 if (edid) { 3678 has_audio = drm_detect_monitor_audio(edid); 3679 kfree(edid); 3680 } 3681 3682 intel_display_power_put(dev_priv, power_domain); 3683 3684 return has_audio; 3685} 3686 3687static int 3688intel_dp_set_property(struct drm_connector *connector, 3689 struct drm_property *property, 3690 uint64_t val) 3691{ 3692 struct drm_i915_private *dev_priv = connector->dev->dev_private; 3693 struct intel_connector *intel_connector = to_intel_connector(connector); 3694 struct intel_encoder *intel_encoder = intel_attached_encoder(connector); 3695 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base); 3696 int ret; 3697 3698 ret = drm_object_property_set_value(&connector->base, property, val); 3699 if (ret) 3700 return ret; 3701 3702 if (property == dev_priv->force_audio_property) { 3703 int i = val; 3704 bool has_audio; 3705 3706 if (i == intel_dp->force_audio) 3707 return 0; 3708 3709 intel_dp->force_audio = i; 3710 3711 if (i == HDMI_AUDIO_AUTO) 3712 has_audio = intel_dp_detect_audio(connector); 3713 else 3714 has_audio = (i == HDMI_AUDIO_ON); 3715 3716 if (has_audio == intel_dp->has_audio) 3717 return 0; 3718 3719 intel_dp->has_audio = has_audio; 3720 goto done; 3721 } 3722 3723 if (property == dev_priv->broadcast_rgb_property) { 3724 bool old_auto = intel_dp->color_range_auto; 3725 uint32_t old_range = intel_dp->color_range; 3726 3727 switch (val) { 3728 case INTEL_BROADCAST_RGB_AUTO: 3729 intel_dp->color_range_auto = true; 3730 break; 3731 case INTEL_BROADCAST_RGB_FULL: 3732 intel_dp->color_range_auto = false; 3733 intel_dp->color_range = 0; 3734 break; 3735 case INTEL_BROADCAST_RGB_LIMITED: 3736 intel_dp->color_range_auto = false; 3737 intel_dp->color_range = DP_COLOR_RANGE_16_235; 3738 break; 3739 default: 3740 return -EINVAL; 3741 } 3742 3743 if (old_auto == intel_dp->color_range_auto && 3744 old_range == intel_dp->color_range) 3745 return 0; 3746 3747 goto done; 3748 } 3749 3750 if (is_edp(intel_dp) && 3751 property == connector->dev->mode_config.scaling_mode_property) { 3752 if (val == DRM_MODE_SCALE_NONE) { 3753 DRM_DEBUG_KMS("no scaling not supported\n"); 3754 return -EINVAL; 3755 } 3756 3757 if (intel_connector->panel.fitting_mode == val) { 3758 /* the eDP scaling property is not changed */ 3759 return 0; 3760 } 3761 intel_connector->panel.fitting_mode = val; 3762 3763 goto done; 3764 } 3765 3766 return -EINVAL; 3767 3768done: 3769 if (intel_encoder->base.crtc) 3770 intel_crtc_restore_mode(intel_encoder->base.crtc); 3771 3772 return 0; 3773} 3774 3775static void 3776intel_dp_connector_destroy(struct drm_connector *connector) 3777{ 3778 struct intel_connector *intel_connector = to_intel_connector(connector); 3779 3780 if (!IS_ERR_OR_NULL(intel_connector->edid)) 3781 kfree(intel_connector->edid); 3782 3783 /* Can't call is_edp() since the encoder may have been destroyed 3784 * already. */ 3785 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) 3786 intel_panel_fini(&intel_connector->panel); 3787 3788 drm_connector_cleanup(connector); 3789 kfree(connector); 3790} 3791 3792void intel_dp_encoder_destroy(struct drm_encoder *encoder) 3793{ 3794 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); 3795 struct intel_dp *intel_dp = &intel_dig_port->dp; 3796 struct drm_device *dev = intel_dp_to_dev(intel_dp); 3797 3798 drm_dp_aux_unregister(&intel_dp->aux); 3799 drm_encoder_cleanup(encoder); 3800 if (is_edp(intel_dp)) { 3801 cancel_delayed_work_sync(&intel_dp->panel_vdd_work); 3802 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL); 3803 edp_panel_vdd_off_sync(intel_dp); 3804 drm_modeset_unlock(&dev->mode_config.connection_mutex); 3805 } 3806 kfree(intel_dig_port); 3807} 3808 3809static const struct drm_connector_funcs intel_dp_connector_funcs = { 3810 .dpms = intel_connector_dpms, 3811 .detect = intel_dp_detect, 3812 .fill_modes = drm_helper_probe_single_connector_modes, 3813 .set_property = intel_dp_set_property, 3814 .destroy = intel_dp_connector_destroy, 3815}; 3816 3817static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = { 3818 .get_modes = intel_dp_get_modes, 3819 .mode_valid = intel_dp_mode_valid, 3820 .best_encoder = intel_best_encoder, 3821}; 3822 3823static const struct drm_encoder_funcs intel_dp_enc_funcs = { 3824 .destroy = intel_dp_encoder_destroy, 3825}; 3826 3827static void 3828intel_dp_hot_plug(struct intel_encoder *intel_encoder) 3829{ 3830 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base); 3831 3832 intel_dp_check_link_status(intel_dp); 3833} 3834 3835bool 3836intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port, bool long_hpd) 3837{ 3838 struct intel_dp *intel_dp = &intel_dig_port->dp; 3839 3840 if (long_hpd) 3841 return true; 3842 3843 /* 3844 * we'll check the link status via the normal hot plug path later - 3845 * but for short hpds we should check it now 3846 */ 3847 intel_dp_check_link_status(intel_dp); 3848 return false; 3849} 3850 3851/* Return which DP Port should be selected for Transcoder DP control */ 3852int 3853intel_trans_dp_port_sel(struct drm_crtc *crtc) 3854{ 3855 struct drm_device *dev = crtc->dev; 3856 struct intel_encoder *intel_encoder; 3857 struct intel_dp *intel_dp; 3858 3859 for_each_encoder_on_crtc(dev, crtc, intel_encoder) { 3860 intel_dp = enc_to_intel_dp(&intel_encoder->base); 3861 3862 if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT || 3863 intel_encoder->type == INTEL_OUTPUT_EDP) 3864 return intel_dp->output_reg; 3865 } 3866 3867 return -1; 3868} 3869 3870/* check the VBT to see whether the eDP is on DP-D port */ 3871bool intel_dp_is_edp(struct drm_device *dev, enum port port) 3872{ 3873 struct drm_i915_private *dev_priv = dev->dev_private; 3874 union child_device_config *p_child; 3875 int i; 3876 static const short port_mapping[] = { 3877 [PORT_B] = PORT_IDPB, 3878 [PORT_C] = PORT_IDPC, 3879 [PORT_D] = PORT_IDPD, 3880 }; 3881 3882 if (port == PORT_A) 3883 return true; 3884 3885 if (!dev_priv->vbt.child_dev_num) 3886 return false; 3887 3888 for (i = 0; i < dev_priv->vbt.child_dev_num; i++) { 3889 p_child = dev_priv->vbt.child_dev + i; 3890 3891 if (p_child->common.dvo_port == port_mapping[port] && 3892 (p_child->common.device_type & DEVICE_TYPE_eDP_BITS) == 3893 (DEVICE_TYPE_eDP & DEVICE_TYPE_eDP_BITS)) 3894 return true; 3895 } 3896 return false; 3897} 3898 3899static void 3900intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector) 3901{ 3902 struct intel_connector *intel_connector = to_intel_connector(connector); 3903 3904 intel_attach_force_audio_property(connector); 3905 intel_attach_broadcast_rgb_property(connector); 3906 intel_dp->color_range_auto = true; 3907 3908 if (is_edp(intel_dp)) { 3909 drm_mode_create_scaling_mode_property(connector->dev); 3910 drm_object_attach_property( 3911 &connector->base, 3912 connector->dev->mode_config.scaling_mode_property, 3913 DRM_MODE_SCALE_ASPECT); 3914 intel_connector->panel.fitting_mode = DRM_MODE_SCALE_ASPECT; 3915 } 3916} 3917 3918static void intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp) 3919{ 3920 intel_dp->last_power_cycle = jiffies; 3921 intel_dp->last_power_on = jiffies; 3922 intel_dp->last_backlight_off = jiffies; 3923} 3924 3925static void 3926intel_dp_init_panel_power_sequencer(struct drm_device *dev, 3927 struct intel_dp *intel_dp, 3928 struct edp_power_seq *out) 3929{ 3930 struct drm_i915_private *dev_priv = dev->dev_private; 3931 struct edp_power_seq cur, vbt, spec, final; 3932 u32 pp_on, pp_off, pp_div, pp; 3933 int pp_ctrl_reg, pp_on_reg, pp_off_reg, pp_div_reg; 3934 3935 if (HAS_PCH_SPLIT(dev)) { 3936 pp_ctrl_reg = PCH_PP_CONTROL; 3937 pp_on_reg = PCH_PP_ON_DELAYS; 3938 pp_off_reg = PCH_PP_OFF_DELAYS; 3939 pp_div_reg = PCH_PP_DIVISOR; 3940 } else { 3941 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp); 3942 3943 pp_ctrl_reg = VLV_PIPE_PP_CONTROL(pipe); 3944 pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe); 3945 pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe); 3946 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe); 3947 } 3948 3949 /* Workaround: Need to write PP_CONTROL with the unlock key as 3950 * the very first thing. */ 3951 pp = ironlake_get_pp_control(intel_dp); 3952 I915_WRITE(pp_ctrl_reg, pp); 3953 3954 pp_on = I915_READ(pp_on_reg); 3955 pp_off = I915_READ(pp_off_reg); 3956 pp_div = I915_READ(pp_div_reg); 3957 3958 /* Pull timing values out of registers */ 3959 cur.t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >> 3960 PANEL_POWER_UP_DELAY_SHIFT; 3961 3962 cur.t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >> 3963 PANEL_LIGHT_ON_DELAY_SHIFT; 3964 3965 cur.t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >> 3966 PANEL_LIGHT_OFF_DELAY_SHIFT; 3967 3968 cur.t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >> 3969 PANEL_POWER_DOWN_DELAY_SHIFT; 3970 3971 cur.t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >> 3972 PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000; 3973 3974 DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n", 3975 cur.t1_t3, cur.t8, cur.t9, cur.t10, cur.t11_t12); 3976 3977 vbt = dev_priv->vbt.edp_pps; 3978 3979 /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of 3980 * our hw here, which are all in 100usec. */ 3981 spec.t1_t3 = 210 * 10; 3982 spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */ 3983 spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */ 3984 spec.t10 = 500 * 10; 3985 /* This one is special and actually in units of 100ms, but zero 3986 * based in the hw (so we need to add 100 ms). But the sw vbt 3987 * table multiplies it with 1000 to make it in units of 100usec, 3988 * too. */ 3989 spec.t11_t12 = (510 + 100) * 10; 3990 3991 DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n", 3992 vbt.t1_t3, vbt.t8, vbt.t9, vbt.t10, vbt.t11_t12); 3993 3994 /* Use the max of the register settings and vbt. If both are 3995 * unset, fall back to the spec limits. */ 3996#define assign_final(field) final.field = (max(cur.field, vbt.field) == 0 ? \ 3997 spec.field : \ 3998 max(cur.field, vbt.field)) 3999 assign_final(t1_t3); 4000 assign_final(t8); 4001 assign_final(t9); 4002 assign_final(t10); 4003 assign_final(t11_t12); 4004#undef assign_final 4005 4006#define get_delay(field) (DIV_ROUND_UP(final.field, 10)) 4007 intel_dp->panel_power_up_delay = get_delay(t1_t3); 4008 intel_dp->backlight_on_delay = get_delay(t8); 4009 intel_dp->backlight_off_delay = get_delay(t9); 4010 intel_dp->panel_power_down_delay = get_delay(t10); 4011 intel_dp->panel_power_cycle_delay = get_delay(t11_t12); 4012#undef get_delay 4013 4014 DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n", 4015 intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay, 4016 intel_dp->panel_power_cycle_delay); 4017 4018 DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n", 4019 intel_dp->backlight_on_delay, intel_dp->backlight_off_delay); 4020 4021 if (out) 4022 *out = final; 4023} 4024 4025static void 4026intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev, 4027 struct intel_dp *intel_dp, 4028 struct edp_power_seq *seq) 4029{ 4030 struct drm_i915_private *dev_priv = dev->dev_private; 4031 u32 pp_on, pp_off, pp_div, port_sel = 0; 4032 int div = HAS_PCH_SPLIT(dev) ? intel_pch_rawclk(dev) : intel_hrawclk(dev); 4033 int pp_on_reg, pp_off_reg, pp_div_reg; 4034 4035 if (HAS_PCH_SPLIT(dev)) { 4036 pp_on_reg = PCH_PP_ON_DELAYS; 4037 pp_off_reg = PCH_PP_OFF_DELAYS; 4038 pp_div_reg = PCH_PP_DIVISOR; 4039 } else { 4040 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp); 4041 4042 pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe); 4043 pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe); 4044 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe); 4045 } 4046 4047 /* 4048 * And finally store the new values in the power sequencer. The 4049 * backlight delays are set to 1 because we do manual waits on them. For 4050 * T8, even BSpec recommends doing it. For T9, if we don't do this, 4051 * we'll end up waiting for the backlight off delay twice: once when we 4052 * do the manual sleep, and once when we disable the panel and wait for 4053 * the PP_STATUS bit to become zero. 4054 */ 4055 pp_on = (seq->t1_t3 << PANEL_POWER_UP_DELAY_SHIFT) | 4056 (1 << PANEL_LIGHT_ON_DELAY_SHIFT); 4057 pp_off = (1 << PANEL_LIGHT_OFF_DELAY_SHIFT) | 4058 (seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT); 4059 /* Compute the divisor for the pp clock, simply match the Bspec 4060 * formula. */ 4061 pp_div = ((100 * div)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT; 4062 pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000) 4063 << PANEL_POWER_CYCLE_DELAY_SHIFT); 4064 4065 /* Haswell doesn't have any port selection bits for the panel 4066 * power sequencer any more. */ 4067 if (IS_VALLEYVIEW(dev)) { 4068 if (dp_to_dig_port(intel_dp)->port == PORT_B) 4069 port_sel = PANEL_PORT_SELECT_DPB_VLV; 4070 else 4071 port_sel = PANEL_PORT_SELECT_DPC_VLV; 4072 } else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) { 4073 if (dp_to_dig_port(intel_dp)->port == PORT_A) 4074 port_sel = PANEL_PORT_SELECT_DPA; 4075 else 4076 port_sel = PANEL_PORT_SELECT_DPD; 4077 } 4078 4079 pp_on |= port_sel; 4080 4081 I915_WRITE(pp_on_reg, pp_on); 4082 I915_WRITE(pp_off_reg, pp_off); 4083 I915_WRITE(pp_div_reg, pp_div); 4084 4085 DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n", 4086 I915_READ(pp_on_reg), 4087 I915_READ(pp_off_reg), 4088 I915_READ(pp_div_reg)); 4089} 4090 4091void intel_dp_set_drrs_state(struct drm_device *dev, int refresh_rate) 4092{ 4093 struct drm_i915_private *dev_priv = dev->dev_private; 4094 struct intel_encoder *encoder; 4095 struct intel_dp *intel_dp = NULL; 4096 struct intel_crtc_config *config = NULL; 4097 struct intel_crtc *intel_crtc = NULL; 4098 struct intel_connector *intel_connector = dev_priv->drrs.connector; 4099 u32 reg, val; 4100 enum edp_drrs_refresh_rate_type index = DRRS_HIGH_RR; 4101 4102 if (refresh_rate <= 0) { 4103 DRM_DEBUG_KMS("Refresh rate should be positive non-zero.\n"); 4104 return; 4105 } 4106 4107 if (intel_connector == NULL) { 4108 DRM_DEBUG_KMS("DRRS supported for eDP only.\n"); 4109 return; 4110 } 4111 4112 if (INTEL_INFO(dev)->gen < 8 && intel_edp_is_psr_enabled(dev)) { 4113 DRM_DEBUG_KMS("DRRS is disabled as PSR is enabled\n"); 4114 return; 4115 } 4116 4117 encoder = intel_attached_encoder(&intel_connector->base); 4118 intel_dp = enc_to_intel_dp(&encoder->base); 4119 intel_crtc = encoder->new_crtc; 4120 4121 if (!intel_crtc) { 4122 DRM_DEBUG_KMS("DRRS: intel_crtc not initialized\n"); 4123 return; 4124 } 4125 4126 config = &intel_crtc->config; 4127 4128 if (intel_dp->drrs_state.type < SEAMLESS_DRRS_SUPPORT) { 4129 DRM_DEBUG_KMS("Only Seamless DRRS supported.\n"); 4130 return; 4131 } 4132 4133 if (intel_connector->panel.downclock_mode->vrefresh == refresh_rate) 4134 index = DRRS_LOW_RR; 4135 4136 if (index == intel_dp->drrs_state.refresh_rate_type) { 4137 DRM_DEBUG_KMS( 4138 "DRRS requested for previously set RR...ignoring\n"); 4139 return; 4140 } 4141 4142 if (!intel_crtc->active) { 4143 DRM_DEBUG_KMS("eDP encoder disabled. CRTC not Active\n"); 4144 return; 4145 } 4146 4147 if (INTEL_INFO(dev)->gen > 6 && INTEL_INFO(dev)->gen < 8) { 4148 reg = PIPECONF(intel_crtc->config.cpu_transcoder); 4149 val = I915_READ(reg); 4150 if (index > DRRS_HIGH_RR) { 4151 val |= PIPECONF_EDP_RR_MODE_SWITCH; 4152 intel_dp_set_m2_n2(intel_crtc, &config->dp_m2_n2); 4153 } else { 4154 val &= ~PIPECONF_EDP_RR_MODE_SWITCH; 4155 } 4156 I915_WRITE(reg, val); 4157 } 4158 4159 /* 4160 * mutex taken to ensure that there is no race between differnt 4161 * drrs calls trying to update refresh rate. This scenario may occur 4162 * in future when idleness detection based DRRS in kernel and 4163 * possible calls from user space to set differnt RR are made. 4164 */ 4165 4166 mutex_lock(&intel_dp->drrs_state.mutex); 4167 4168 intel_dp->drrs_state.refresh_rate_type = index; 4169 4170 mutex_unlock(&intel_dp->drrs_state.mutex); 4171 4172 DRM_DEBUG_KMS("eDP Refresh Rate set to : %dHz\n", refresh_rate); 4173} 4174 4175static struct drm_display_mode * 4176intel_dp_drrs_init(struct intel_digital_port *intel_dig_port, 4177 struct intel_connector *intel_connector, 4178 struct drm_display_mode *fixed_mode) 4179{ 4180 struct drm_connector *connector = &intel_connector->base; 4181 struct intel_dp *intel_dp = &intel_dig_port->dp; 4182 struct drm_device *dev = intel_dig_port->base.base.dev; 4183 struct drm_i915_private *dev_priv = dev->dev_private; 4184 struct drm_display_mode *downclock_mode = NULL; 4185 4186 if (INTEL_INFO(dev)->gen <= 6) { 4187 DRM_DEBUG_KMS("DRRS supported for Gen7 and above\n"); 4188 return NULL; 4189 } 4190 4191 if (dev_priv->vbt.drrs_type != SEAMLESS_DRRS_SUPPORT) { 4192 DRM_INFO("VBT doesn't support DRRS\n"); 4193 return NULL; 4194 } 4195 4196 downclock_mode = intel_find_panel_downclock 4197 (dev, fixed_mode, connector); 4198 4199 if (!downclock_mode) { 4200 DRM_INFO("DRRS not supported\n"); 4201 return NULL; 4202 } 4203 4204 dev_priv->drrs.connector = intel_connector; 4205 4206 mutex_init(&intel_dp->drrs_state.mutex); 4207 4208 intel_dp->drrs_state.type = dev_priv->vbt.drrs_type; 4209 4210 intel_dp->drrs_state.refresh_rate_type = DRRS_HIGH_RR; 4211 DRM_INFO("seamless DRRS supported for eDP panel.\n"); 4212 return downclock_mode; 4213} 4214 4215static bool intel_edp_init_connector(struct intel_dp *intel_dp, 4216 struct intel_connector *intel_connector, 4217 struct edp_power_seq *power_seq) 4218{ 4219 struct drm_connector *connector = &intel_connector->base; 4220 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 4221 struct intel_encoder *intel_encoder = &intel_dig_port->base; 4222 struct drm_device *dev = intel_encoder->base.dev; 4223 struct drm_i915_private *dev_priv = dev->dev_private; 4224 struct drm_display_mode *fixed_mode = NULL; 4225 struct drm_display_mode *downclock_mode = NULL; 4226 bool has_dpcd; 4227 struct drm_display_mode *scan; 4228 struct edid *edid; 4229 4230 intel_dp->drrs_state.type = DRRS_NOT_SUPPORTED; 4231 4232 if (!is_edp(intel_dp)) 4233 return true; 4234 4235 /* The VDD bit needs a power domain reference, so if the bit is already 4236 * enabled when we boot, grab this reference. */ 4237 if (edp_have_panel_vdd(intel_dp)) { 4238 enum intel_display_power_domain power_domain; 4239 power_domain = intel_display_port_power_domain(intel_encoder); 4240 intel_display_power_get(dev_priv, power_domain); 4241 } 4242 4243 /* Cache DPCD and EDID for edp. */ 4244 intel_edp_panel_vdd_on(intel_dp); 4245 has_dpcd = intel_dp_get_dpcd(intel_dp); 4246 edp_panel_vdd_off(intel_dp, false); 4247 4248 if (has_dpcd) { 4249 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) 4250 dev_priv->no_aux_handshake = 4251 intel_dp->dpcd[DP_MAX_DOWNSPREAD] & 4252 DP_NO_AUX_HANDSHAKE_LINK_TRAINING; 4253 } else { 4254 /* if this fails, presume the device is a ghost */ 4255 DRM_INFO("failed to retrieve link info, disabling eDP\n"); 4256 return false; 4257 } 4258 4259 /* We now know it's not a ghost, init power sequence regs. */ 4260 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp, power_seq); 4261 4262 mutex_lock(&dev->mode_config.mutex); 4263 edid = drm_get_edid(connector, &intel_dp->aux.ddc); 4264 if (edid) { 4265 if (drm_add_edid_modes(connector, edid)) { 4266 drm_mode_connector_update_edid_property(connector, 4267 edid); 4268 drm_edid_to_eld(connector, edid); 4269 } else { 4270 kfree(edid); 4271 edid = ERR_PTR(-EINVAL); 4272 } 4273 } else { 4274 edid = ERR_PTR(-ENOENT); 4275 } 4276 intel_connector->edid = edid; 4277 4278 /* prefer fixed mode from EDID if available */ 4279 list_for_each_entry(scan, &connector->probed_modes, head) { 4280 if ((scan->type & DRM_MODE_TYPE_PREFERRED)) { 4281 fixed_mode = drm_mode_duplicate(dev, scan); 4282 downclock_mode = intel_dp_drrs_init( 4283 intel_dig_port, 4284 intel_connector, fixed_mode); 4285 break; 4286 } 4287 } 4288 4289 /* fallback to VBT if available for eDP */ 4290 if (!fixed_mode && dev_priv->vbt.lfp_lvds_vbt_mode) { 4291 fixed_mode = drm_mode_duplicate(dev, 4292 dev_priv->vbt.lfp_lvds_vbt_mode); 4293 if (fixed_mode) 4294 fixed_mode->type |= DRM_MODE_TYPE_PREFERRED; 4295 } 4296 mutex_unlock(&dev->mode_config.mutex); 4297 4298 intel_panel_init(&intel_connector->panel, fixed_mode, downclock_mode); 4299 intel_panel_setup_backlight(connector); 4300 4301 return true; 4302} 4303 4304bool 4305intel_dp_init_connector(struct intel_digital_port *intel_dig_port, 4306 struct intel_connector *intel_connector) 4307{ 4308 struct drm_connector *connector = &intel_connector->base; 4309 struct intel_dp *intel_dp = &intel_dig_port->dp; 4310 struct intel_encoder *intel_encoder = &intel_dig_port->base; 4311 struct drm_device *dev = intel_encoder->base.dev; 4312 struct drm_i915_private *dev_priv = dev->dev_private; 4313 enum port port = intel_dig_port->port; 4314 struct edp_power_seq power_seq = { 0 }; 4315 int type; 4316 4317 /* intel_dp vfuncs */ 4318 if (IS_VALLEYVIEW(dev)) 4319 intel_dp->get_aux_clock_divider = vlv_get_aux_clock_divider; 4320 else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) 4321 intel_dp->get_aux_clock_divider = hsw_get_aux_clock_divider; 4322 else if (HAS_PCH_SPLIT(dev)) 4323 intel_dp->get_aux_clock_divider = ilk_get_aux_clock_divider; 4324 else 4325 intel_dp->get_aux_clock_divider = i9xx_get_aux_clock_divider; 4326 4327 intel_dp->get_aux_send_ctl = i9xx_get_aux_send_ctl; 4328 4329 /* Preserve the current hw state. */ 4330 intel_dp->DP = I915_READ(intel_dp->output_reg); 4331 intel_dp->attached_connector = intel_connector; 4332 4333 if (intel_dp_is_edp(dev, port)) 4334 type = DRM_MODE_CONNECTOR_eDP; 4335 else 4336 type = DRM_MODE_CONNECTOR_DisplayPort; 4337 4338 /* 4339 * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but 4340 * for DP the encoder type can be set by the caller to 4341 * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it. 4342 */ 4343 if (type == DRM_MODE_CONNECTOR_eDP) 4344 intel_encoder->type = INTEL_OUTPUT_EDP; 4345 4346 DRM_DEBUG_KMS("Adding %s connector on port %c\n", 4347 type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP", 4348 port_name(port)); 4349 4350 drm_connector_init(dev, connector, &intel_dp_connector_funcs, type); 4351 drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs); 4352 4353 connector->interlace_allowed = true; 4354 connector->doublescan_allowed = 0; 4355 4356 INIT_DELAYED_WORK(&intel_dp->panel_vdd_work, 4357 edp_panel_vdd_work); 4358 4359 intel_connector_attach_encoder(intel_connector, intel_encoder); 4360 drm_sysfs_connector_add(connector); 4361 4362 if (HAS_DDI(dev)) 4363 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state; 4364 else 4365 intel_connector->get_hw_state = intel_connector_get_hw_state; 4366 intel_connector->unregister = intel_dp_connector_unregister; 4367 4368 /* Set up the hotplug pin. */ 4369 switch (port) { 4370 case PORT_A: 4371 intel_encoder->hpd_pin = HPD_PORT_A; 4372 break; 4373 case PORT_B: 4374 intel_encoder->hpd_pin = HPD_PORT_B; 4375 break; 4376 case PORT_C: 4377 intel_encoder->hpd_pin = HPD_PORT_C; 4378 break; 4379 case PORT_D: 4380 intel_encoder->hpd_pin = HPD_PORT_D; 4381 break; 4382 default: 4383 BUG(); 4384 } 4385 4386 if (is_edp(intel_dp)) { 4387 intel_dp_init_panel_power_timestamps(intel_dp); 4388 intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq); 4389 } 4390 4391 intel_dp_aux_init(intel_dp, intel_connector); 4392 4393 if (!intel_edp_init_connector(intel_dp, intel_connector, &power_seq)) { 4394 drm_dp_aux_unregister(&intel_dp->aux); 4395 if (is_edp(intel_dp)) { 4396 cancel_delayed_work_sync(&intel_dp->panel_vdd_work); 4397 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL); 4398 edp_panel_vdd_off_sync(intel_dp); 4399 drm_modeset_unlock(&dev->mode_config.connection_mutex); 4400 } 4401 drm_sysfs_connector_remove(connector); 4402 drm_connector_cleanup(connector); 4403 return false; 4404 } 4405 4406 intel_dp_add_properties(intel_dp, connector); 4407 4408 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written 4409 * 0xd. Failure to do so will result in spurious interrupts being 4410 * generated on the port when a cable is not attached. 4411 */ 4412 if (IS_G4X(dev) && !IS_GM45(dev)) { 4413 u32 temp = I915_READ(PEG_BAND_GAP_DATA); 4414 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd); 4415 } 4416 4417 return true; 4418} 4419 4420void 4421intel_dp_init(struct drm_device *dev, int output_reg, enum port port) 4422{ 4423 struct drm_i915_private *dev_priv = dev->dev_private; 4424 struct intel_digital_port *intel_dig_port; 4425 struct intel_encoder *intel_encoder; 4426 struct drm_encoder *encoder; 4427 struct intel_connector *intel_connector; 4428 4429 intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL); 4430 if (!intel_dig_port) 4431 return; 4432 4433 intel_connector = kzalloc(sizeof(*intel_connector), GFP_KERNEL); 4434 if (!intel_connector) { 4435 kfree(intel_dig_port); 4436 return; 4437 } 4438 4439 intel_encoder = &intel_dig_port->base; 4440 encoder = &intel_encoder->base; 4441 4442 drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs, 4443 DRM_MODE_ENCODER_TMDS); 4444 4445 intel_encoder->compute_config = intel_dp_compute_config; 4446 intel_encoder->disable = intel_disable_dp; 4447 intel_encoder->get_hw_state = intel_dp_get_hw_state; 4448 intel_encoder->get_config = intel_dp_get_config; 4449 if (IS_CHERRYVIEW(dev)) { 4450 intel_encoder->pre_pll_enable = chv_dp_pre_pll_enable; 4451 intel_encoder->pre_enable = chv_pre_enable_dp; 4452 intel_encoder->enable = vlv_enable_dp; 4453 intel_encoder->post_disable = chv_post_disable_dp; 4454 } else if (IS_VALLEYVIEW(dev)) { 4455 intel_encoder->pre_pll_enable = vlv_dp_pre_pll_enable; 4456 intel_encoder->pre_enable = vlv_pre_enable_dp; 4457 intel_encoder->enable = vlv_enable_dp; 4458 intel_encoder->post_disable = vlv_post_disable_dp; 4459 } else { 4460 intel_encoder->pre_enable = g4x_pre_enable_dp; 4461 intel_encoder->enable = g4x_enable_dp; 4462 intel_encoder->post_disable = g4x_post_disable_dp; 4463 } 4464 4465 intel_dig_port->port = port; 4466 intel_dig_port->dp.output_reg = output_reg; 4467 4468 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT; 4469 if (IS_CHERRYVIEW(dev)) { 4470 if (port == PORT_D) 4471 intel_encoder->crtc_mask = 1 << 2; 4472 else 4473 intel_encoder->crtc_mask = (1 << 0) | (1 << 1); 4474 } else { 4475 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2); 4476 } 4477 intel_encoder->cloneable = 0; 4478 intel_encoder->hot_plug = intel_dp_hot_plug; 4479 4480 intel_dig_port->hpd_pulse = intel_dp_hpd_pulse; 4481 dev_priv->hpd_irq_port[port] = intel_dig_port; 4482 4483 if (!intel_dp_init_connector(intel_dig_port, intel_connector)) { 4484 drm_encoder_cleanup(encoder); 4485 kfree(intel_dig_port); 4486 kfree(intel_connector); 4487 } 4488} 4489