intel_dp.c revision 10aa17c86f0de1fd902f7b8ee487a3682d7401df
1/* 2 * Copyright © 2008 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 * Authors: 24 * Keith Packard <keithp@keithp.com> 25 * 26 */ 27 28#include <linux/i2c.h> 29#include <linux/slab.h> 30#include <linux/export.h> 31#include <drm/drmP.h> 32#include <drm/drm_crtc.h> 33#include <drm/drm_crtc_helper.h> 34#include <drm/drm_edid.h> 35#include "intel_drv.h" 36#include <drm/i915_drm.h> 37#include "i915_drv.h" 38 39#define DP_LINK_CHECK_TIMEOUT (10 * 1000) 40 41/** 42 * is_edp - is the given port attached to an eDP panel (either CPU or PCH) 43 * @intel_dp: DP struct 44 * 45 * If a CPU or PCH DP output is attached to an eDP panel, this function 46 * will return true, and false otherwise. 47 */ 48static bool is_edp(struct intel_dp *intel_dp) 49{ 50 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 51 52 return intel_dig_port->base.type == INTEL_OUTPUT_EDP; 53} 54 55/** 56 * is_pch_edp - is the port on the PCH and attached to an eDP panel? 57 * @intel_dp: DP struct 58 * 59 * Returns true if the given DP struct corresponds to a PCH DP port attached 60 * to an eDP panel, false otherwise. Helpful for determining whether we 61 * may need FDI resources for a given DP output or not. 62 */ 63static bool is_pch_edp(struct intel_dp *intel_dp) 64{ 65 return intel_dp->is_pch_edp; 66} 67 68/** 69 * is_cpu_edp - is the port on the CPU and attached to an eDP panel? 70 * @intel_dp: DP struct 71 * 72 * Returns true if the given DP struct corresponds to a CPU eDP port. 73 */ 74static bool is_cpu_edp(struct intel_dp *intel_dp) 75{ 76 return is_edp(intel_dp) && !is_pch_edp(intel_dp); 77} 78 79static struct drm_device *intel_dp_to_dev(struct intel_dp *intel_dp) 80{ 81 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 82 83 return intel_dig_port->base.base.dev; 84} 85 86static struct intel_dp *intel_attached_dp(struct drm_connector *connector) 87{ 88 return enc_to_intel_dp(&intel_attached_encoder(connector)->base); 89} 90 91/** 92 * intel_encoder_is_pch_edp - is the given encoder a PCH attached eDP? 93 * @encoder: DRM encoder 94 * 95 * Return true if @encoder corresponds to a PCH attached eDP panel. Needed 96 * by intel_display.c. 97 */ 98bool intel_encoder_is_pch_edp(struct drm_encoder *encoder) 99{ 100 struct intel_dp *intel_dp; 101 102 if (!encoder) 103 return false; 104 105 intel_dp = enc_to_intel_dp(encoder); 106 107 return is_pch_edp(intel_dp); 108} 109 110static void intel_dp_link_down(struct intel_dp *intel_dp); 111 112void 113intel_edp_link_config(struct intel_encoder *intel_encoder, 114 int *lane_num, int *link_bw) 115{ 116 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base); 117 118 *lane_num = intel_dp->lane_count; 119 *link_bw = drm_dp_bw_code_to_link_rate(intel_dp->link_bw); 120} 121 122int 123intel_edp_target_clock(struct intel_encoder *intel_encoder, 124 struct drm_display_mode *mode) 125{ 126 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base); 127 struct intel_connector *intel_connector = intel_dp->attached_connector; 128 129 if (intel_connector->panel.fixed_mode) 130 return intel_connector->panel.fixed_mode->clock; 131 else 132 return mode->clock; 133} 134 135static int 136intel_dp_max_link_bw(struct intel_dp *intel_dp) 137{ 138 int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE]; 139 140 switch (max_link_bw) { 141 case DP_LINK_BW_1_62: 142 case DP_LINK_BW_2_7: 143 break; 144 default: 145 max_link_bw = DP_LINK_BW_1_62; 146 break; 147 } 148 return max_link_bw; 149} 150 151/* 152 * The units on the numbers in the next two are... bizarre. Examples will 153 * make it clearer; this one parallels an example in the eDP spec. 154 * 155 * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as: 156 * 157 * 270000 * 1 * 8 / 10 == 216000 158 * 159 * The actual data capacity of that configuration is 2.16Gbit/s, so the 160 * units are decakilobits. ->clock in a drm_display_mode is in kilohertz - 161 * or equivalently, kilopixels per second - so for 1680x1050R it'd be 162 * 119000. At 18bpp that's 2142000 kilobits per second. 163 * 164 * Thus the strange-looking division by 10 in intel_dp_link_required, to 165 * get the result in decakilobits instead of kilobits. 166 */ 167 168static int 169intel_dp_link_required(int pixel_clock, int bpp) 170{ 171 return (pixel_clock * bpp + 9) / 10; 172} 173 174static int 175intel_dp_max_data_rate(int max_link_clock, int max_lanes) 176{ 177 return (max_link_clock * max_lanes * 8) / 10; 178} 179 180static bool 181intel_dp_adjust_dithering(struct intel_dp *intel_dp, 182 struct drm_display_mode *mode, 183 bool adjust_mode) 184{ 185 int max_link_clock = 186 drm_dp_bw_code_to_link_rate(intel_dp_max_link_bw(intel_dp)); 187 int max_lanes = drm_dp_max_lane_count(intel_dp->dpcd); 188 int max_rate, mode_rate; 189 190 mode_rate = intel_dp_link_required(mode->clock, 24); 191 max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes); 192 193 if (mode_rate > max_rate) { 194 mode_rate = intel_dp_link_required(mode->clock, 18); 195 if (mode_rate > max_rate) 196 return false; 197 198 if (adjust_mode) 199 mode->private_flags 200 |= INTEL_MODE_DP_FORCE_6BPC; 201 202 return true; 203 } 204 205 return true; 206} 207 208static int 209intel_dp_mode_valid(struct drm_connector *connector, 210 struct drm_display_mode *mode) 211{ 212 struct intel_dp *intel_dp = intel_attached_dp(connector); 213 struct intel_connector *intel_connector = to_intel_connector(connector); 214 struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode; 215 216 if (is_edp(intel_dp) && fixed_mode) { 217 if (mode->hdisplay > fixed_mode->hdisplay) 218 return MODE_PANEL; 219 220 if (mode->vdisplay > fixed_mode->vdisplay) 221 return MODE_PANEL; 222 } 223 224 if (!intel_dp_adjust_dithering(intel_dp, mode, false)) 225 return MODE_CLOCK_HIGH; 226 227 if (mode->clock < 10000) 228 return MODE_CLOCK_LOW; 229 230 if (mode->flags & DRM_MODE_FLAG_DBLCLK) 231 return MODE_H_ILLEGAL; 232 233 return MODE_OK; 234} 235 236static uint32_t 237pack_aux(uint8_t *src, int src_bytes) 238{ 239 int i; 240 uint32_t v = 0; 241 242 if (src_bytes > 4) 243 src_bytes = 4; 244 for (i = 0; i < src_bytes; i++) 245 v |= ((uint32_t) src[i]) << ((3-i) * 8); 246 return v; 247} 248 249static void 250unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes) 251{ 252 int i; 253 if (dst_bytes > 4) 254 dst_bytes = 4; 255 for (i = 0; i < dst_bytes; i++) 256 dst[i] = src >> ((3-i) * 8); 257} 258 259/* hrawclock is 1/4 the FSB frequency */ 260static int 261intel_hrawclk(struct drm_device *dev) 262{ 263 struct drm_i915_private *dev_priv = dev->dev_private; 264 uint32_t clkcfg; 265 266 /* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */ 267 if (IS_VALLEYVIEW(dev)) 268 return 200; 269 270 clkcfg = I915_READ(CLKCFG); 271 switch (clkcfg & CLKCFG_FSB_MASK) { 272 case CLKCFG_FSB_400: 273 return 100; 274 case CLKCFG_FSB_533: 275 return 133; 276 case CLKCFG_FSB_667: 277 return 166; 278 case CLKCFG_FSB_800: 279 return 200; 280 case CLKCFG_FSB_1067: 281 return 266; 282 case CLKCFG_FSB_1333: 283 return 333; 284 /* these two are just a guess; one of them might be right */ 285 case CLKCFG_FSB_1600: 286 case CLKCFG_FSB_1600_ALT: 287 return 400; 288 default: 289 return 133; 290 } 291} 292 293static bool ironlake_edp_have_panel_power(struct intel_dp *intel_dp) 294{ 295 struct drm_device *dev = intel_dp_to_dev(intel_dp); 296 struct drm_i915_private *dev_priv = dev->dev_private; 297 298 return (I915_READ(PCH_PP_STATUS) & PP_ON) != 0; 299} 300 301static bool ironlake_edp_have_panel_vdd(struct intel_dp *intel_dp) 302{ 303 struct drm_device *dev = intel_dp_to_dev(intel_dp); 304 struct drm_i915_private *dev_priv = dev->dev_private; 305 306 return (I915_READ(PCH_PP_CONTROL) & EDP_FORCE_VDD) != 0; 307} 308 309static void 310intel_dp_check_edp(struct intel_dp *intel_dp) 311{ 312 struct drm_device *dev = intel_dp_to_dev(intel_dp); 313 struct drm_i915_private *dev_priv = dev->dev_private; 314 315 if (!is_edp(intel_dp)) 316 return; 317 if (!ironlake_edp_have_panel_power(intel_dp) && !ironlake_edp_have_panel_vdd(intel_dp)) { 318 WARN(1, "eDP powered off while attempting aux channel communication.\n"); 319 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n", 320 I915_READ(PCH_PP_STATUS), 321 I915_READ(PCH_PP_CONTROL)); 322 } 323} 324 325static uint32_t 326intel_dp_aux_wait_done(struct intel_dp *intel_dp, bool has_aux_irq) 327{ 328 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 329 struct drm_device *dev = intel_dig_port->base.base.dev; 330 struct drm_i915_private *dev_priv = dev->dev_private; 331 uint32_t ch_ctl = intel_dp->output_reg + 0x10; 332 uint32_t status; 333 bool done; 334 335 if (IS_HASWELL(dev)) { 336 switch (intel_dig_port->port) { 337 case PORT_A: 338 ch_ctl = DPA_AUX_CH_CTL; 339 break; 340 case PORT_B: 341 ch_ctl = PCH_DPB_AUX_CH_CTL; 342 break; 343 case PORT_C: 344 ch_ctl = PCH_DPC_AUX_CH_CTL; 345 break; 346 case PORT_D: 347 ch_ctl = PCH_DPD_AUX_CH_CTL; 348 break; 349 default: 350 BUG(); 351 } 352 } 353 354#define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0) 355 if (has_aux_irq) 356 done = wait_event_timeout(dev_priv->gmbus_wait_queue, C, 10); 357 else 358 done = wait_for_atomic(C, 10) == 0; 359 if (!done) 360 DRM_ERROR("dp aux hw did not signal timeout (has irq: %i)!\n", 361 has_aux_irq); 362#undef C 363 364 return status; 365} 366 367static int 368intel_dp_aux_ch(struct intel_dp *intel_dp, 369 uint8_t *send, int send_bytes, 370 uint8_t *recv, int recv_size) 371{ 372 uint32_t output_reg = intel_dp->output_reg; 373 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 374 struct drm_device *dev = intel_dig_port->base.base.dev; 375 struct drm_i915_private *dev_priv = dev->dev_private; 376 uint32_t ch_ctl = output_reg + 0x10; 377 uint32_t ch_data = ch_ctl + 4; 378 int i, ret, recv_bytes; 379 uint32_t status; 380 uint32_t aux_clock_divider; 381 int try, precharge; 382 bool has_aux_irq = INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev); 383 384 /* dp aux is extremely sensitive to irq latency, hence request the 385 * lowest possible wakeup latency and so prevent the cpu from going into 386 * deep sleep states. 387 */ 388 pm_qos_update_request(&dev_priv->pm_qos, 0); 389 390 if (IS_HASWELL(dev)) { 391 switch (intel_dig_port->port) { 392 case PORT_A: 393 ch_ctl = DPA_AUX_CH_CTL; 394 ch_data = DPA_AUX_CH_DATA1; 395 break; 396 case PORT_B: 397 ch_ctl = PCH_DPB_AUX_CH_CTL; 398 ch_data = PCH_DPB_AUX_CH_DATA1; 399 break; 400 case PORT_C: 401 ch_ctl = PCH_DPC_AUX_CH_CTL; 402 ch_data = PCH_DPC_AUX_CH_DATA1; 403 break; 404 case PORT_D: 405 ch_ctl = PCH_DPD_AUX_CH_CTL; 406 ch_data = PCH_DPD_AUX_CH_DATA1; 407 break; 408 default: 409 BUG(); 410 } 411 } 412 413 intel_dp_check_edp(intel_dp); 414 /* The clock divider is based off the hrawclk, 415 * and would like to run at 2MHz. So, take the 416 * hrawclk value and divide by 2 and use that 417 * 418 * Note that PCH attached eDP panels should use a 125MHz input 419 * clock divider. 420 */ 421 if (is_cpu_edp(intel_dp)) { 422 if (HAS_DDI(dev)) 423 aux_clock_divider = intel_ddi_get_cdclk_freq(dev_priv) >> 1; 424 else if (IS_VALLEYVIEW(dev)) 425 aux_clock_divider = 100; 426 else if (IS_GEN6(dev) || IS_GEN7(dev)) 427 aux_clock_divider = 200; /* SNB & IVB eDP input clock at 400Mhz */ 428 else 429 aux_clock_divider = 225; /* eDP input clock at 450Mhz */ 430 } else if (HAS_PCH_SPLIT(dev)) 431 aux_clock_divider = DIV_ROUND_UP(intel_pch_rawclk(dev), 2); 432 else 433 aux_clock_divider = intel_hrawclk(dev) / 2; 434 435 if (IS_GEN6(dev)) 436 precharge = 3; 437 else 438 precharge = 5; 439 440 /* Try to wait for any previous AUX channel activity */ 441 for (try = 0; try < 3; try++) { 442 status = I915_READ_NOTRACE(ch_ctl); 443 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0) 444 break; 445 msleep(1); 446 } 447 448 if (try == 3) { 449 WARN(1, "dp_aux_ch not started status 0x%08x\n", 450 I915_READ(ch_ctl)); 451 ret = -EBUSY; 452 goto out; 453 } 454 455 /* Must try at least 3 times according to DP spec */ 456 for (try = 0; try < 5; try++) { 457 /* Load the send data into the aux channel data registers */ 458 for (i = 0; i < send_bytes; i += 4) 459 I915_WRITE(ch_data + i, 460 pack_aux(send + i, send_bytes - i)); 461 462 /* Send the command and wait for it to complete */ 463 I915_WRITE(ch_ctl, 464 DP_AUX_CH_CTL_SEND_BUSY | 465 (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) | 466 DP_AUX_CH_CTL_TIME_OUT_400us | 467 (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) | 468 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) | 469 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT) | 470 DP_AUX_CH_CTL_DONE | 471 DP_AUX_CH_CTL_TIME_OUT_ERROR | 472 DP_AUX_CH_CTL_RECEIVE_ERROR); 473 474 status = intel_dp_aux_wait_done(intel_dp, has_aux_irq); 475 476 /* Clear done status and any errors */ 477 I915_WRITE(ch_ctl, 478 status | 479 DP_AUX_CH_CTL_DONE | 480 DP_AUX_CH_CTL_TIME_OUT_ERROR | 481 DP_AUX_CH_CTL_RECEIVE_ERROR); 482 483 if (status & (DP_AUX_CH_CTL_TIME_OUT_ERROR | 484 DP_AUX_CH_CTL_RECEIVE_ERROR)) 485 continue; 486 if (status & DP_AUX_CH_CTL_DONE) 487 break; 488 } 489 490 if ((status & DP_AUX_CH_CTL_DONE) == 0) { 491 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status); 492 ret = -EBUSY; 493 goto out; 494 } 495 496 /* Check for timeout or receive error. 497 * Timeouts occur when the sink is not connected 498 */ 499 if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) { 500 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status); 501 ret = -EIO; 502 goto out; 503 } 504 505 /* Timeouts occur when the device isn't connected, so they're 506 * "normal" -- don't fill the kernel log with these */ 507 if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) { 508 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status); 509 ret = -ETIMEDOUT; 510 goto out; 511 } 512 513 /* Unload any bytes sent back from the other side */ 514 recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >> 515 DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT); 516 if (recv_bytes > recv_size) 517 recv_bytes = recv_size; 518 519 for (i = 0; i < recv_bytes; i += 4) 520 unpack_aux(I915_READ(ch_data + i), 521 recv + i, recv_bytes - i); 522 523 ret = recv_bytes; 524out: 525 pm_qos_update_request(&dev_priv->pm_qos, PM_QOS_DEFAULT_VALUE); 526 527 return ret; 528} 529 530/* Write data to the aux channel in native mode */ 531static int 532intel_dp_aux_native_write(struct intel_dp *intel_dp, 533 uint16_t address, uint8_t *send, int send_bytes) 534{ 535 int ret; 536 uint8_t msg[20]; 537 int msg_bytes; 538 uint8_t ack; 539 540 intel_dp_check_edp(intel_dp); 541 if (send_bytes > 16) 542 return -1; 543 msg[0] = AUX_NATIVE_WRITE << 4; 544 msg[1] = address >> 8; 545 msg[2] = address & 0xff; 546 msg[3] = send_bytes - 1; 547 memcpy(&msg[4], send, send_bytes); 548 msg_bytes = send_bytes + 4; 549 for (;;) { 550 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes, &ack, 1); 551 if (ret < 0) 552 return ret; 553 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK) 554 break; 555 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER) 556 udelay(100); 557 else 558 return -EIO; 559 } 560 return send_bytes; 561} 562 563/* Write a single byte to the aux channel in native mode */ 564static int 565intel_dp_aux_native_write_1(struct intel_dp *intel_dp, 566 uint16_t address, uint8_t byte) 567{ 568 return intel_dp_aux_native_write(intel_dp, address, &byte, 1); 569} 570 571/* read bytes from a native aux channel */ 572static int 573intel_dp_aux_native_read(struct intel_dp *intel_dp, 574 uint16_t address, uint8_t *recv, int recv_bytes) 575{ 576 uint8_t msg[4]; 577 int msg_bytes; 578 uint8_t reply[20]; 579 int reply_bytes; 580 uint8_t ack; 581 int ret; 582 583 intel_dp_check_edp(intel_dp); 584 msg[0] = AUX_NATIVE_READ << 4; 585 msg[1] = address >> 8; 586 msg[2] = address & 0xff; 587 msg[3] = recv_bytes - 1; 588 589 msg_bytes = 4; 590 reply_bytes = recv_bytes + 1; 591 592 for (;;) { 593 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes, 594 reply, reply_bytes); 595 if (ret == 0) 596 return -EPROTO; 597 if (ret < 0) 598 return ret; 599 ack = reply[0]; 600 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK) { 601 memcpy(recv, reply + 1, ret - 1); 602 return ret - 1; 603 } 604 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER) 605 udelay(100); 606 else 607 return -EIO; 608 } 609} 610 611static int 612intel_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode, 613 uint8_t write_byte, uint8_t *read_byte) 614{ 615 struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data; 616 struct intel_dp *intel_dp = container_of(adapter, 617 struct intel_dp, 618 adapter); 619 uint16_t address = algo_data->address; 620 uint8_t msg[5]; 621 uint8_t reply[2]; 622 unsigned retry; 623 int msg_bytes; 624 int reply_bytes; 625 int ret; 626 627 intel_dp_check_edp(intel_dp); 628 /* Set up the command byte */ 629 if (mode & MODE_I2C_READ) 630 msg[0] = AUX_I2C_READ << 4; 631 else 632 msg[0] = AUX_I2C_WRITE << 4; 633 634 if (!(mode & MODE_I2C_STOP)) 635 msg[0] |= AUX_I2C_MOT << 4; 636 637 msg[1] = address >> 8; 638 msg[2] = address; 639 640 switch (mode) { 641 case MODE_I2C_WRITE: 642 msg[3] = 0; 643 msg[4] = write_byte; 644 msg_bytes = 5; 645 reply_bytes = 1; 646 break; 647 case MODE_I2C_READ: 648 msg[3] = 0; 649 msg_bytes = 4; 650 reply_bytes = 2; 651 break; 652 default: 653 msg_bytes = 3; 654 reply_bytes = 1; 655 break; 656 } 657 658 for (retry = 0; retry < 5; retry++) { 659 ret = intel_dp_aux_ch(intel_dp, 660 msg, msg_bytes, 661 reply, reply_bytes); 662 if (ret < 0) { 663 DRM_DEBUG_KMS("aux_ch failed %d\n", ret); 664 return ret; 665 } 666 667 switch (reply[0] & AUX_NATIVE_REPLY_MASK) { 668 case AUX_NATIVE_REPLY_ACK: 669 /* I2C-over-AUX Reply field is only valid 670 * when paired with AUX ACK. 671 */ 672 break; 673 case AUX_NATIVE_REPLY_NACK: 674 DRM_DEBUG_KMS("aux_ch native nack\n"); 675 return -EREMOTEIO; 676 case AUX_NATIVE_REPLY_DEFER: 677 udelay(100); 678 continue; 679 default: 680 DRM_ERROR("aux_ch invalid native reply 0x%02x\n", 681 reply[0]); 682 return -EREMOTEIO; 683 } 684 685 switch (reply[0] & AUX_I2C_REPLY_MASK) { 686 case AUX_I2C_REPLY_ACK: 687 if (mode == MODE_I2C_READ) { 688 *read_byte = reply[1]; 689 } 690 return reply_bytes - 1; 691 case AUX_I2C_REPLY_NACK: 692 DRM_DEBUG_KMS("aux_i2c nack\n"); 693 return -EREMOTEIO; 694 case AUX_I2C_REPLY_DEFER: 695 DRM_DEBUG_KMS("aux_i2c defer\n"); 696 udelay(100); 697 break; 698 default: 699 DRM_ERROR("aux_i2c invalid reply 0x%02x\n", reply[0]); 700 return -EREMOTEIO; 701 } 702 } 703 704 DRM_ERROR("too many retries, giving up\n"); 705 return -EREMOTEIO; 706} 707 708static int 709intel_dp_i2c_init(struct intel_dp *intel_dp, 710 struct intel_connector *intel_connector, const char *name) 711{ 712 int ret; 713 714 DRM_DEBUG_KMS("i2c_init %s\n", name); 715 intel_dp->algo.running = false; 716 intel_dp->algo.address = 0; 717 intel_dp->algo.aux_ch = intel_dp_i2c_aux_ch; 718 719 memset(&intel_dp->adapter, '\0', sizeof(intel_dp->adapter)); 720 intel_dp->adapter.owner = THIS_MODULE; 721 intel_dp->adapter.class = I2C_CLASS_DDC; 722 strncpy(intel_dp->adapter.name, name, sizeof(intel_dp->adapter.name) - 1); 723 intel_dp->adapter.name[sizeof(intel_dp->adapter.name) - 1] = '\0'; 724 intel_dp->adapter.algo_data = &intel_dp->algo; 725 intel_dp->adapter.dev.parent = &intel_connector->base.kdev; 726 727 ironlake_edp_panel_vdd_on(intel_dp); 728 ret = i2c_dp_aux_add_bus(&intel_dp->adapter); 729 ironlake_edp_panel_vdd_off(intel_dp, false); 730 return ret; 731} 732 733bool 734intel_dp_mode_fixup(struct drm_encoder *encoder, 735 const struct drm_display_mode *mode, 736 struct drm_display_mode *adjusted_mode) 737{ 738 struct drm_device *dev = encoder->dev; 739 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 740 struct intel_connector *intel_connector = intel_dp->attached_connector; 741 int lane_count, clock; 742 int max_lane_count = drm_dp_max_lane_count(intel_dp->dpcd); 743 int max_clock = intel_dp_max_link_bw(intel_dp) == DP_LINK_BW_2_7 ? 1 : 0; 744 int bpp, mode_rate; 745 static int bws[2] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7 }; 746 747 if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) { 748 intel_fixed_panel_mode(intel_connector->panel.fixed_mode, 749 adjusted_mode); 750 intel_pch_panel_fitting(dev, 751 intel_connector->panel.fitting_mode, 752 mode, adjusted_mode); 753 } 754 755 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK) 756 return false; 757 758 DRM_DEBUG_KMS("DP link computation with max lane count %i " 759 "max bw %02x pixel clock %iKHz\n", 760 max_lane_count, bws[max_clock], adjusted_mode->clock); 761 762 if (!intel_dp_adjust_dithering(intel_dp, adjusted_mode, true)) 763 return false; 764 765 bpp = adjusted_mode->private_flags & INTEL_MODE_DP_FORCE_6BPC ? 18 : 24; 766 767 if (intel_dp->color_range_auto) { 768 /* 769 * See: 770 * CEA-861-E - 5.1 Default Encoding Parameters 771 * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry 772 */ 773 if (bpp != 18 && drm_mode_cea_vic(adjusted_mode) > 1) 774 intel_dp->color_range = DP_COLOR_RANGE_16_235; 775 else 776 intel_dp->color_range = 0; 777 } 778 779 if (intel_dp->color_range) 780 adjusted_mode->private_flags |= INTEL_MODE_LIMITED_COLOR_RANGE; 781 782 mode_rate = intel_dp_link_required(adjusted_mode->clock, bpp); 783 784 for (clock = 0; clock <= max_clock; clock++) { 785 for (lane_count = 1; lane_count <= max_lane_count; lane_count <<= 1) { 786 int link_bw_clock = 787 drm_dp_bw_code_to_link_rate(bws[clock]); 788 int link_avail = intel_dp_max_data_rate(link_bw_clock, 789 lane_count); 790 791 if (mode_rate <= link_avail) { 792 intel_dp->link_bw = bws[clock]; 793 intel_dp->lane_count = lane_count; 794 adjusted_mode->clock = link_bw_clock; 795 DRM_DEBUG_KMS("DP link bw %02x lane " 796 "count %d clock %d bpp %d\n", 797 intel_dp->link_bw, intel_dp->lane_count, 798 adjusted_mode->clock, bpp); 799 DRM_DEBUG_KMS("DP link bw required %i available %i\n", 800 mode_rate, link_avail); 801 return true; 802 } 803 } 804 } 805 806 return false; 807} 808 809void 810intel_dp_set_m_n(struct drm_crtc *crtc, struct drm_display_mode *mode, 811 struct drm_display_mode *adjusted_mode) 812{ 813 struct drm_device *dev = crtc->dev; 814 struct intel_encoder *intel_encoder; 815 struct intel_dp *intel_dp; 816 struct drm_i915_private *dev_priv = dev->dev_private; 817 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 818 int lane_count = 4; 819 struct intel_link_m_n m_n; 820 int pipe = intel_crtc->pipe; 821 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder; 822 823 /* 824 * Find the lane count in the intel_encoder private 825 */ 826 for_each_encoder_on_crtc(dev, crtc, intel_encoder) { 827 intel_dp = enc_to_intel_dp(&intel_encoder->base); 828 829 if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT || 830 intel_encoder->type == INTEL_OUTPUT_EDP) 831 { 832 lane_count = intel_dp->lane_count; 833 break; 834 } 835 } 836 837 /* 838 * Compute the GMCH and Link ratios. The '3' here is 839 * the number of bytes_per_pixel post-LUT, which we always 840 * set up for 8-bits of R/G/B, or 3 bytes total. 841 */ 842 intel_link_compute_m_n(intel_crtc->bpp, lane_count, 843 mode->clock, adjusted_mode->clock, &m_n); 844 845 if (IS_HASWELL(dev)) { 846 I915_WRITE(PIPE_DATA_M1(cpu_transcoder), 847 TU_SIZE(m_n.tu) | m_n.gmch_m); 848 I915_WRITE(PIPE_DATA_N1(cpu_transcoder), m_n.gmch_n); 849 I915_WRITE(PIPE_LINK_M1(cpu_transcoder), m_n.link_m); 850 I915_WRITE(PIPE_LINK_N1(cpu_transcoder), m_n.link_n); 851 } else if (HAS_PCH_SPLIT(dev)) { 852 I915_WRITE(TRANSDATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m); 853 I915_WRITE(TRANSDATA_N1(pipe), m_n.gmch_n); 854 I915_WRITE(TRANSDPLINK_M1(pipe), m_n.link_m); 855 I915_WRITE(TRANSDPLINK_N1(pipe), m_n.link_n); 856 } else if (IS_VALLEYVIEW(dev)) { 857 I915_WRITE(PIPE_DATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m); 858 I915_WRITE(PIPE_DATA_N1(pipe), m_n.gmch_n); 859 I915_WRITE(PIPE_LINK_M1(pipe), m_n.link_m); 860 I915_WRITE(PIPE_LINK_N1(pipe), m_n.link_n); 861 } else { 862 I915_WRITE(PIPE_GMCH_DATA_M(pipe), 863 TU_SIZE(m_n.tu) | m_n.gmch_m); 864 I915_WRITE(PIPE_GMCH_DATA_N(pipe), m_n.gmch_n); 865 I915_WRITE(PIPE_DP_LINK_M(pipe), m_n.link_m); 866 I915_WRITE(PIPE_DP_LINK_N(pipe), m_n.link_n); 867 } 868} 869 870void intel_dp_init_link_config(struct intel_dp *intel_dp) 871{ 872 memset(intel_dp->link_configuration, 0, DP_LINK_CONFIGURATION_SIZE); 873 intel_dp->link_configuration[0] = intel_dp->link_bw; 874 intel_dp->link_configuration[1] = intel_dp->lane_count; 875 intel_dp->link_configuration[8] = DP_SET_ANSI_8B10B; 876 /* 877 * Check for DPCD version > 1.1 and enhanced framing support 878 */ 879 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 && 880 (intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_ENHANCED_FRAME_CAP)) { 881 intel_dp->link_configuration[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN; 882 } 883} 884 885static void ironlake_set_pll_edp(struct drm_crtc *crtc, int clock) 886{ 887 struct drm_device *dev = crtc->dev; 888 struct drm_i915_private *dev_priv = dev->dev_private; 889 u32 dpa_ctl; 890 891 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock); 892 dpa_ctl = I915_READ(DP_A); 893 dpa_ctl &= ~DP_PLL_FREQ_MASK; 894 895 if (clock < 200000) { 896 /* For a long time we've carried around a ILK-DevA w/a for the 897 * 160MHz clock. If we're really unlucky, it's still required. 898 */ 899 DRM_DEBUG_KMS("160MHz cpu eDP clock, might need ilk devA w/a\n"); 900 dpa_ctl |= DP_PLL_FREQ_160MHZ; 901 } else { 902 dpa_ctl |= DP_PLL_FREQ_270MHZ; 903 } 904 905 I915_WRITE(DP_A, dpa_ctl); 906 907 POSTING_READ(DP_A); 908 udelay(500); 909} 910 911static void 912intel_dp_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode, 913 struct drm_display_mode *adjusted_mode) 914{ 915 struct drm_device *dev = encoder->dev; 916 struct drm_i915_private *dev_priv = dev->dev_private; 917 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 918 struct drm_crtc *crtc = encoder->crtc; 919 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 920 921 /* 922 * There are four kinds of DP registers: 923 * 924 * IBX PCH 925 * SNB CPU 926 * IVB CPU 927 * CPT PCH 928 * 929 * IBX PCH and CPU are the same for almost everything, 930 * except that the CPU DP PLL is configured in this 931 * register 932 * 933 * CPT PCH is quite different, having many bits moved 934 * to the TRANS_DP_CTL register instead. That 935 * configuration happens (oddly) in ironlake_pch_enable 936 */ 937 938 /* Preserve the BIOS-computed detected bit. This is 939 * supposed to be read-only. 940 */ 941 intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED; 942 943 /* Handle DP bits in common between all three register formats */ 944 intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0; 945 946 switch (intel_dp->lane_count) { 947 case 1: 948 intel_dp->DP |= DP_PORT_WIDTH_1; 949 break; 950 case 2: 951 intel_dp->DP |= DP_PORT_WIDTH_2; 952 break; 953 case 4: 954 intel_dp->DP |= DP_PORT_WIDTH_4; 955 break; 956 } 957 if (intel_dp->has_audio) { 958 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n", 959 pipe_name(intel_crtc->pipe)); 960 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE; 961 intel_write_eld(encoder, adjusted_mode); 962 } 963 964 intel_dp_init_link_config(intel_dp); 965 966 /* Split out the IBX/CPU vs CPT settings */ 967 968 if (is_cpu_edp(intel_dp) && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) { 969 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) 970 intel_dp->DP |= DP_SYNC_HS_HIGH; 971 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) 972 intel_dp->DP |= DP_SYNC_VS_HIGH; 973 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT; 974 975 if (intel_dp->link_configuration[1] & DP_LANE_COUNT_ENHANCED_FRAME_EN) 976 intel_dp->DP |= DP_ENHANCED_FRAMING; 977 978 intel_dp->DP |= intel_crtc->pipe << 29; 979 980 /* don't miss out required setting for eDP */ 981 if (adjusted_mode->clock < 200000) 982 intel_dp->DP |= DP_PLL_FREQ_160MHZ; 983 else 984 intel_dp->DP |= DP_PLL_FREQ_270MHZ; 985 } else if (!HAS_PCH_CPT(dev) || is_cpu_edp(intel_dp)) { 986 if (!HAS_PCH_SPLIT(dev)) 987 intel_dp->DP |= intel_dp->color_range; 988 989 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) 990 intel_dp->DP |= DP_SYNC_HS_HIGH; 991 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) 992 intel_dp->DP |= DP_SYNC_VS_HIGH; 993 intel_dp->DP |= DP_LINK_TRAIN_OFF; 994 995 if (intel_dp->link_configuration[1] & DP_LANE_COUNT_ENHANCED_FRAME_EN) 996 intel_dp->DP |= DP_ENHANCED_FRAMING; 997 998 if (intel_crtc->pipe == 1) 999 intel_dp->DP |= DP_PIPEB_SELECT; 1000 1001 if (is_cpu_edp(intel_dp)) { 1002 /* don't miss out required setting for eDP */ 1003 if (adjusted_mode->clock < 200000) 1004 intel_dp->DP |= DP_PLL_FREQ_160MHZ; 1005 else 1006 intel_dp->DP |= DP_PLL_FREQ_270MHZ; 1007 } 1008 } else { 1009 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT; 1010 } 1011 1012 if (is_cpu_edp(intel_dp)) 1013 ironlake_set_pll_edp(crtc, adjusted_mode->clock); 1014} 1015 1016#define IDLE_ON_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK) 1017#define IDLE_ON_VALUE (PP_ON | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE) 1018 1019#define IDLE_OFF_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK) 1020#define IDLE_OFF_VALUE (0 | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE) 1021 1022#define IDLE_CYCLE_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK) 1023#define IDLE_CYCLE_VALUE (0 | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE) 1024 1025static void ironlake_wait_panel_status(struct intel_dp *intel_dp, 1026 u32 mask, 1027 u32 value) 1028{ 1029 struct drm_device *dev = intel_dp_to_dev(intel_dp); 1030 struct drm_i915_private *dev_priv = dev->dev_private; 1031 1032 DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n", 1033 mask, value, 1034 I915_READ(PCH_PP_STATUS), 1035 I915_READ(PCH_PP_CONTROL)); 1036 1037 if (_wait_for((I915_READ(PCH_PP_STATUS) & mask) == value, 5000, 10)) { 1038 DRM_ERROR("Panel status timeout: status %08x control %08x\n", 1039 I915_READ(PCH_PP_STATUS), 1040 I915_READ(PCH_PP_CONTROL)); 1041 } 1042} 1043 1044static void ironlake_wait_panel_on(struct intel_dp *intel_dp) 1045{ 1046 DRM_DEBUG_KMS("Wait for panel power on\n"); 1047 ironlake_wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE); 1048} 1049 1050static void ironlake_wait_panel_off(struct intel_dp *intel_dp) 1051{ 1052 DRM_DEBUG_KMS("Wait for panel power off time\n"); 1053 ironlake_wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE); 1054} 1055 1056static void ironlake_wait_panel_power_cycle(struct intel_dp *intel_dp) 1057{ 1058 DRM_DEBUG_KMS("Wait for panel power cycle\n"); 1059 ironlake_wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE); 1060} 1061 1062 1063/* Read the current pp_control value, unlocking the register if it 1064 * is locked 1065 */ 1066 1067static u32 ironlake_get_pp_control(struct drm_i915_private *dev_priv) 1068{ 1069 u32 control = I915_READ(PCH_PP_CONTROL); 1070 1071 control &= ~PANEL_UNLOCK_MASK; 1072 control |= PANEL_UNLOCK_REGS; 1073 return control; 1074} 1075 1076void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp) 1077{ 1078 struct drm_device *dev = intel_dp_to_dev(intel_dp); 1079 struct drm_i915_private *dev_priv = dev->dev_private; 1080 u32 pp; 1081 1082 if (!is_edp(intel_dp)) 1083 return; 1084 DRM_DEBUG_KMS("Turn eDP VDD on\n"); 1085 1086 WARN(intel_dp->want_panel_vdd, 1087 "eDP VDD already requested on\n"); 1088 1089 intel_dp->want_panel_vdd = true; 1090 1091 if (ironlake_edp_have_panel_vdd(intel_dp)) { 1092 DRM_DEBUG_KMS("eDP VDD already on\n"); 1093 return; 1094 } 1095 1096 if (!ironlake_edp_have_panel_power(intel_dp)) 1097 ironlake_wait_panel_power_cycle(intel_dp); 1098 1099 pp = ironlake_get_pp_control(dev_priv); 1100 pp |= EDP_FORCE_VDD; 1101 I915_WRITE(PCH_PP_CONTROL, pp); 1102 POSTING_READ(PCH_PP_CONTROL); 1103 DRM_DEBUG_KMS("PCH_PP_STATUS: 0x%08x PCH_PP_CONTROL: 0x%08x\n", 1104 I915_READ(PCH_PP_STATUS), I915_READ(PCH_PP_CONTROL)); 1105 1106 /* 1107 * If the panel wasn't on, delay before accessing aux channel 1108 */ 1109 if (!ironlake_edp_have_panel_power(intel_dp)) { 1110 DRM_DEBUG_KMS("eDP was not running\n"); 1111 msleep(intel_dp->panel_power_up_delay); 1112 } 1113} 1114 1115static void ironlake_panel_vdd_off_sync(struct intel_dp *intel_dp) 1116{ 1117 struct drm_device *dev = intel_dp_to_dev(intel_dp); 1118 struct drm_i915_private *dev_priv = dev->dev_private; 1119 u32 pp; 1120 1121 if (!intel_dp->want_panel_vdd && ironlake_edp_have_panel_vdd(intel_dp)) { 1122 pp = ironlake_get_pp_control(dev_priv); 1123 pp &= ~EDP_FORCE_VDD; 1124 I915_WRITE(PCH_PP_CONTROL, pp); 1125 POSTING_READ(PCH_PP_CONTROL); 1126 1127 /* Make sure sequencer is idle before allowing subsequent activity */ 1128 DRM_DEBUG_KMS("PCH_PP_STATUS: 0x%08x PCH_PP_CONTROL: 0x%08x\n", 1129 I915_READ(PCH_PP_STATUS), I915_READ(PCH_PP_CONTROL)); 1130 1131 msleep(intel_dp->panel_power_down_delay); 1132 } 1133} 1134 1135static void ironlake_panel_vdd_work(struct work_struct *__work) 1136{ 1137 struct intel_dp *intel_dp = container_of(to_delayed_work(__work), 1138 struct intel_dp, panel_vdd_work); 1139 struct drm_device *dev = intel_dp_to_dev(intel_dp); 1140 1141 mutex_lock(&dev->mode_config.mutex); 1142 ironlake_panel_vdd_off_sync(intel_dp); 1143 mutex_unlock(&dev->mode_config.mutex); 1144} 1145 1146void ironlake_edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync) 1147{ 1148 if (!is_edp(intel_dp)) 1149 return; 1150 1151 DRM_DEBUG_KMS("Turn eDP VDD off %d\n", intel_dp->want_panel_vdd); 1152 WARN(!intel_dp->want_panel_vdd, "eDP VDD not forced on"); 1153 1154 intel_dp->want_panel_vdd = false; 1155 1156 if (sync) { 1157 ironlake_panel_vdd_off_sync(intel_dp); 1158 } else { 1159 /* 1160 * Queue the timer to fire a long 1161 * time from now (relative to the power down delay) 1162 * to keep the panel power up across a sequence of operations 1163 */ 1164 schedule_delayed_work(&intel_dp->panel_vdd_work, 1165 msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5)); 1166 } 1167} 1168 1169void ironlake_edp_panel_on(struct intel_dp *intel_dp) 1170{ 1171 struct drm_device *dev = intel_dp_to_dev(intel_dp); 1172 struct drm_i915_private *dev_priv = dev->dev_private; 1173 u32 pp; 1174 1175 if (!is_edp(intel_dp)) 1176 return; 1177 1178 DRM_DEBUG_KMS("Turn eDP power on\n"); 1179 1180 if (ironlake_edp_have_panel_power(intel_dp)) { 1181 DRM_DEBUG_KMS("eDP power already on\n"); 1182 return; 1183 } 1184 1185 ironlake_wait_panel_power_cycle(intel_dp); 1186 1187 pp = ironlake_get_pp_control(dev_priv); 1188 if (IS_GEN5(dev)) { 1189 /* ILK workaround: disable reset around power sequence */ 1190 pp &= ~PANEL_POWER_RESET; 1191 I915_WRITE(PCH_PP_CONTROL, pp); 1192 POSTING_READ(PCH_PP_CONTROL); 1193 } 1194 1195 pp |= POWER_TARGET_ON; 1196 if (!IS_GEN5(dev)) 1197 pp |= PANEL_POWER_RESET; 1198 1199 I915_WRITE(PCH_PP_CONTROL, pp); 1200 POSTING_READ(PCH_PP_CONTROL); 1201 1202 ironlake_wait_panel_on(intel_dp); 1203 1204 if (IS_GEN5(dev)) { 1205 pp |= PANEL_POWER_RESET; /* restore panel reset bit */ 1206 I915_WRITE(PCH_PP_CONTROL, pp); 1207 POSTING_READ(PCH_PP_CONTROL); 1208 } 1209} 1210 1211void ironlake_edp_panel_off(struct intel_dp *intel_dp) 1212{ 1213 struct drm_device *dev = intel_dp_to_dev(intel_dp); 1214 struct drm_i915_private *dev_priv = dev->dev_private; 1215 u32 pp; 1216 1217 if (!is_edp(intel_dp)) 1218 return; 1219 1220 DRM_DEBUG_KMS("Turn eDP power off\n"); 1221 1222 WARN(!intel_dp->want_panel_vdd, "Need VDD to turn off panel\n"); 1223 1224 pp = ironlake_get_pp_control(dev_priv); 1225 /* We need to switch off panel power _and_ force vdd, for otherwise some 1226 * panels get very unhappy and cease to work. */ 1227 pp &= ~(POWER_TARGET_ON | EDP_FORCE_VDD | PANEL_POWER_RESET | EDP_BLC_ENABLE); 1228 I915_WRITE(PCH_PP_CONTROL, pp); 1229 POSTING_READ(PCH_PP_CONTROL); 1230 1231 intel_dp->want_panel_vdd = false; 1232 1233 ironlake_wait_panel_off(intel_dp); 1234} 1235 1236void ironlake_edp_backlight_on(struct intel_dp *intel_dp) 1237{ 1238 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 1239 struct drm_device *dev = intel_dig_port->base.base.dev; 1240 struct drm_i915_private *dev_priv = dev->dev_private; 1241 int pipe = to_intel_crtc(intel_dig_port->base.base.crtc)->pipe; 1242 u32 pp; 1243 1244 if (!is_edp(intel_dp)) 1245 return; 1246 1247 DRM_DEBUG_KMS("\n"); 1248 /* 1249 * If we enable the backlight right away following a panel power 1250 * on, we may see slight flicker as the panel syncs with the eDP 1251 * link. So delay a bit to make sure the image is solid before 1252 * allowing it to appear. 1253 */ 1254 msleep(intel_dp->backlight_on_delay); 1255 pp = ironlake_get_pp_control(dev_priv); 1256 pp |= EDP_BLC_ENABLE; 1257 I915_WRITE(PCH_PP_CONTROL, pp); 1258 POSTING_READ(PCH_PP_CONTROL); 1259 1260 intel_panel_enable_backlight(dev, pipe); 1261} 1262 1263void ironlake_edp_backlight_off(struct intel_dp *intel_dp) 1264{ 1265 struct drm_device *dev = intel_dp_to_dev(intel_dp); 1266 struct drm_i915_private *dev_priv = dev->dev_private; 1267 u32 pp; 1268 1269 if (!is_edp(intel_dp)) 1270 return; 1271 1272 intel_panel_disable_backlight(dev); 1273 1274 DRM_DEBUG_KMS("\n"); 1275 pp = ironlake_get_pp_control(dev_priv); 1276 pp &= ~EDP_BLC_ENABLE; 1277 I915_WRITE(PCH_PP_CONTROL, pp); 1278 POSTING_READ(PCH_PP_CONTROL); 1279 msleep(intel_dp->backlight_off_delay); 1280} 1281 1282static void ironlake_edp_pll_on(struct intel_dp *intel_dp) 1283{ 1284 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 1285 struct drm_crtc *crtc = intel_dig_port->base.base.crtc; 1286 struct drm_device *dev = crtc->dev; 1287 struct drm_i915_private *dev_priv = dev->dev_private; 1288 u32 dpa_ctl; 1289 1290 assert_pipe_disabled(dev_priv, 1291 to_intel_crtc(crtc)->pipe); 1292 1293 DRM_DEBUG_KMS("\n"); 1294 dpa_ctl = I915_READ(DP_A); 1295 WARN(dpa_ctl & DP_PLL_ENABLE, "dp pll on, should be off\n"); 1296 WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n"); 1297 1298 /* We don't adjust intel_dp->DP while tearing down the link, to 1299 * facilitate link retraining (e.g. after hotplug). Hence clear all 1300 * enable bits here to ensure that we don't enable too much. */ 1301 intel_dp->DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE); 1302 intel_dp->DP |= DP_PLL_ENABLE; 1303 I915_WRITE(DP_A, intel_dp->DP); 1304 POSTING_READ(DP_A); 1305 udelay(200); 1306} 1307 1308static void ironlake_edp_pll_off(struct intel_dp *intel_dp) 1309{ 1310 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 1311 struct drm_crtc *crtc = intel_dig_port->base.base.crtc; 1312 struct drm_device *dev = crtc->dev; 1313 struct drm_i915_private *dev_priv = dev->dev_private; 1314 u32 dpa_ctl; 1315 1316 assert_pipe_disabled(dev_priv, 1317 to_intel_crtc(crtc)->pipe); 1318 1319 dpa_ctl = I915_READ(DP_A); 1320 WARN((dpa_ctl & DP_PLL_ENABLE) == 0, 1321 "dp pll off, should be on\n"); 1322 WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n"); 1323 1324 /* We can't rely on the value tracked for the DP register in 1325 * intel_dp->DP because link_down must not change that (otherwise link 1326 * re-training will fail. */ 1327 dpa_ctl &= ~DP_PLL_ENABLE; 1328 I915_WRITE(DP_A, dpa_ctl); 1329 POSTING_READ(DP_A); 1330 udelay(200); 1331} 1332 1333/* If the sink supports it, try to set the power state appropriately */ 1334void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode) 1335{ 1336 int ret, i; 1337 1338 /* Should have a valid DPCD by this point */ 1339 if (intel_dp->dpcd[DP_DPCD_REV] < 0x11) 1340 return; 1341 1342 if (mode != DRM_MODE_DPMS_ON) { 1343 ret = intel_dp_aux_native_write_1(intel_dp, DP_SET_POWER, 1344 DP_SET_POWER_D3); 1345 if (ret != 1) 1346 DRM_DEBUG_DRIVER("failed to write sink power state\n"); 1347 } else { 1348 /* 1349 * When turning on, we need to retry for 1ms to give the sink 1350 * time to wake up. 1351 */ 1352 for (i = 0; i < 3; i++) { 1353 ret = intel_dp_aux_native_write_1(intel_dp, 1354 DP_SET_POWER, 1355 DP_SET_POWER_D0); 1356 if (ret == 1) 1357 break; 1358 msleep(1); 1359 } 1360 } 1361} 1362 1363static bool intel_dp_get_hw_state(struct intel_encoder *encoder, 1364 enum pipe *pipe) 1365{ 1366 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); 1367 struct drm_device *dev = encoder->base.dev; 1368 struct drm_i915_private *dev_priv = dev->dev_private; 1369 u32 tmp = I915_READ(intel_dp->output_reg); 1370 1371 if (!(tmp & DP_PORT_EN)) 1372 return false; 1373 1374 if (is_cpu_edp(intel_dp) && IS_GEN7(dev)) { 1375 *pipe = PORT_TO_PIPE_CPT(tmp); 1376 } else if (!HAS_PCH_CPT(dev) || is_cpu_edp(intel_dp)) { 1377 *pipe = PORT_TO_PIPE(tmp); 1378 } else { 1379 u32 trans_sel; 1380 u32 trans_dp; 1381 int i; 1382 1383 switch (intel_dp->output_reg) { 1384 case PCH_DP_B: 1385 trans_sel = TRANS_DP_PORT_SEL_B; 1386 break; 1387 case PCH_DP_C: 1388 trans_sel = TRANS_DP_PORT_SEL_C; 1389 break; 1390 case PCH_DP_D: 1391 trans_sel = TRANS_DP_PORT_SEL_D; 1392 break; 1393 default: 1394 return true; 1395 } 1396 1397 for_each_pipe(i) { 1398 trans_dp = I915_READ(TRANS_DP_CTL(i)); 1399 if ((trans_dp & TRANS_DP_PORT_SEL_MASK) == trans_sel) { 1400 *pipe = i; 1401 return true; 1402 } 1403 } 1404 1405 DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n", 1406 intel_dp->output_reg); 1407 } 1408 1409 return true; 1410} 1411 1412static void intel_disable_dp(struct intel_encoder *encoder) 1413{ 1414 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); 1415 1416 /* Make sure the panel is off before trying to change the mode. But also 1417 * ensure that we have vdd while we switch off the panel. */ 1418 ironlake_edp_panel_vdd_on(intel_dp); 1419 ironlake_edp_backlight_off(intel_dp); 1420 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON); 1421 ironlake_edp_panel_off(intel_dp); 1422 1423 /* cpu edp my only be disable _after_ the cpu pipe/plane is disabled. */ 1424 if (!is_cpu_edp(intel_dp)) 1425 intel_dp_link_down(intel_dp); 1426} 1427 1428static void intel_post_disable_dp(struct intel_encoder *encoder) 1429{ 1430 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); 1431 1432 if (is_cpu_edp(intel_dp)) { 1433 intel_dp_link_down(intel_dp); 1434 ironlake_edp_pll_off(intel_dp); 1435 } 1436} 1437 1438static void intel_enable_dp(struct intel_encoder *encoder) 1439{ 1440 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); 1441 struct drm_device *dev = encoder->base.dev; 1442 struct drm_i915_private *dev_priv = dev->dev_private; 1443 uint32_t dp_reg = I915_READ(intel_dp->output_reg); 1444 1445 if (WARN_ON(dp_reg & DP_PORT_EN)) 1446 return; 1447 1448 ironlake_edp_panel_vdd_on(intel_dp); 1449 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON); 1450 intel_dp_start_link_train(intel_dp); 1451 ironlake_edp_panel_on(intel_dp); 1452 ironlake_edp_panel_vdd_off(intel_dp, true); 1453 intel_dp_complete_link_train(intel_dp); 1454 ironlake_edp_backlight_on(intel_dp); 1455} 1456 1457static void intel_pre_enable_dp(struct intel_encoder *encoder) 1458{ 1459 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); 1460 1461 if (is_cpu_edp(intel_dp)) 1462 ironlake_edp_pll_on(intel_dp); 1463} 1464 1465/* 1466 * Native read with retry for link status and receiver capability reads for 1467 * cases where the sink may still be asleep. 1468 */ 1469static bool 1470intel_dp_aux_native_read_retry(struct intel_dp *intel_dp, uint16_t address, 1471 uint8_t *recv, int recv_bytes) 1472{ 1473 int ret, i; 1474 1475 /* 1476 * Sinks are *supposed* to come up within 1ms from an off state, 1477 * but we're also supposed to retry 3 times per the spec. 1478 */ 1479 for (i = 0; i < 3; i++) { 1480 ret = intel_dp_aux_native_read(intel_dp, address, recv, 1481 recv_bytes); 1482 if (ret == recv_bytes) 1483 return true; 1484 msleep(1); 1485 } 1486 1487 return false; 1488} 1489 1490/* 1491 * Fetch AUX CH registers 0x202 - 0x207 which contain 1492 * link status information 1493 */ 1494static bool 1495intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE]) 1496{ 1497 return intel_dp_aux_native_read_retry(intel_dp, 1498 DP_LANE0_1_STATUS, 1499 link_status, 1500 DP_LINK_STATUS_SIZE); 1501} 1502 1503#if 0 1504static char *voltage_names[] = { 1505 "0.4V", "0.6V", "0.8V", "1.2V" 1506}; 1507static char *pre_emph_names[] = { 1508 "0dB", "3.5dB", "6dB", "9.5dB" 1509}; 1510static char *link_train_names[] = { 1511 "pattern 1", "pattern 2", "idle", "off" 1512}; 1513#endif 1514 1515/* 1516 * These are source-specific values; current Intel hardware supports 1517 * a maximum voltage of 800mV and a maximum pre-emphasis of 6dB 1518 */ 1519 1520static uint8_t 1521intel_dp_voltage_max(struct intel_dp *intel_dp) 1522{ 1523 struct drm_device *dev = intel_dp_to_dev(intel_dp); 1524 1525 if (IS_GEN7(dev) && is_cpu_edp(intel_dp)) 1526 return DP_TRAIN_VOLTAGE_SWING_800; 1527 else if (HAS_PCH_CPT(dev) && !is_cpu_edp(intel_dp)) 1528 return DP_TRAIN_VOLTAGE_SWING_1200; 1529 else 1530 return DP_TRAIN_VOLTAGE_SWING_800; 1531} 1532 1533static uint8_t 1534intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing) 1535{ 1536 struct drm_device *dev = intel_dp_to_dev(intel_dp); 1537 1538 if (IS_HASWELL(dev)) { 1539 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) { 1540 case DP_TRAIN_VOLTAGE_SWING_400: 1541 return DP_TRAIN_PRE_EMPHASIS_9_5; 1542 case DP_TRAIN_VOLTAGE_SWING_600: 1543 return DP_TRAIN_PRE_EMPHASIS_6; 1544 case DP_TRAIN_VOLTAGE_SWING_800: 1545 return DP_TRAIN_PRE_EMPHASIS_3_5; 1546 case DP_TRAIN_VOLTAGE_SWING_1200: 1547 default: 1548 return DP_TRAIN_PRE_EMPHASIS_0; 1549 } 1550 } else if (IS_GEN7(dev) && is_cpu_edp(intel_dp) && !IS_VALLEYVIEW(dev)) { 1551 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) { 1552 case DP_TRAIN_VOLTAGE_SWING_400: 1553 return DP_TRAIN_PRE_EMPHASIS_6; 1554 case DP_TRAIN_VOLTAGE_SWING_600: 1555 case DP_TRAIN_VOLTAGE_SWING_800: 1556 return DP_TRAIN_PRE_EMPHASIS_3_5; 1557 default: 1558 return DP_TRAIN_PRE_EMPHASIS_0; 1559 } 1560 } else { 1561 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) { 1562 case DP_TRAIN_VOLTAGE_SWING_400: 1563 return DP_TRAIN_PRE_EMPHASIS_6; 1564 case DP_TRAIN_VOLTAGE_SWING_600: 1565 return DP_TRAIN_PRE_EMPHASIS_6; 1566 case DP_TRAIN_VOLTAGE_SWING_800: 1567 return DP_TRAIN_PRE_EMPHASIS_3_5; 1568 case DP_TRAIN_VOLTAGE_SWING_1200: 1569 default: 1570 return DP_TRAIN_PRE_EMPHASIS_0; 1571 } 1572 } 1573} 1574 1575static void 1576intel_get_adjust_train(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE]) 1577{ 1578 uint8_t v = 0; 1579 uint8_t p = 0; 1580 int lane; 1581 uint8_t voltage_max; 1582 uint8_t preemph_max; 1583 1584 for (lane = 0; lane < intel_dp->lane_count; lane++) { 1585 uint8_t this_v = drm_dp_get_adjust_request_voltage(link_status, lane); 1586 uint8_t this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane); 1587 1588 if (this_v > v) 1589 v = this_v; 1590 if (this_p > p) 1591 p = this_p; 1592 } 1593 1594 voltage_max = intel_dp_voltage_max(intel_dp); 1595 if (v >= voltage_max) 1596 v = voltage_max | DP_TRAIN_MAX_SWING_REACHED; 1597 1598 preemph_max = intel_dp_pre_emphasis_max(intel_dp, v); 1599 if (p >= preemph_max) 1600 p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED; 1601 1602 for (lane = 0; lane < 4; lane++) 1603 intel_dp->train_set[lane] = v | p; 1604} 1605 1606static uint32_t 1607intel_gen4_signal_levels(uint8_t train_set) 1608{ 1609 uint32_t signal_levels = 0; 1610 1611 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { 1612 case DP_TRAIN_VOLTAGE_SWING_400: 1613 default: 1614 signal_levels |= DP_VOLTAGE_0_4; 1615 break; 1616 case DP_TRAIN_VOLTAGE_SWING_600: 1617 signal_levels |= DP_VOLTAGE_0_6; 1618 break; 1619 case DP_TRAIN_VOLTAGE_SWING_800: 1620 signal_levels |= DP_VOLTAGE_0_8; 1621 break; 1622 case DP_TRAIN_VOLTAGE_SWING_1200: 1623 signal_levels |= DP_VOLTAGE_1_2; 1624 break; 1625 } 1626 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) { 1627 case DP_TRAIN_PRE_EMPHASIS_0: 1628 default: 1629 signal_levels |= DP_PRE_EMPHASIS_0; 1630 break; 1631 case DP_TRAIN_PRE_EMPHASIS_3_5: 1632 signal_levels |= DP_PRE_EMPHASIS_3_5; 1633 break; 1634 case DP_TRAIN_PRE_EMPHASIS_6: 1635 signal_levels |= DP_PRE_EMPHASIS_6; 1636 break; 1637 case DP_TRAIN_PRE_EMPHASIS_9_5: 1638 signal_levels |= DP_PRE_EMPHASIS_9_5; 1639 break; 1640 } 1641 return signal_levels; 1642} 1643 1644/* Gen6's DP voltage swing and pre-emphasis control */ 1645static uint32_t 1646intel_gen6_edp_signal_levels(uint8_t train_set) 1647{ 1648 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK | 1649 DP_TRAIN_PRE_EMPHASIS_MASK); 1650 switch (signal_levels) { 1651 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0: 1652 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0: 1653 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B; 1654 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5: 1655 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B; 1656 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6: 1657 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6: 1658 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B; 1659 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5: 1660 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5: 1661 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B; 1662 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0: 1663 case DP_TRAIN_VOLTAGE_SWING_1200 | DP_TRAIN_PRE_EMPHASIS_0: 1664 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B; 1665 default: 1666 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:" 1667 "0x%x\n", signal_levels); 1668 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B; 1669 } 1670} 1671 1672/* Gen7's DP voltage swing and pre-emphasis control */ 1673static uint32_t 1674intel_gen7_edp_signal_levels(uint8_t train_set) 1675{ 1676 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK | 1677 DP_TRAIN_PRE_EMPHASIS_MASK); 1678 switch (signal_levels) { 1679 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0: 1680 return EDP_LINK_TRAIN_400MV_0DB_IVB; 1681 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5: 1682 return EDP_LINK_TRAIN_400MV_3_5DB_IVB; 1683 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6: 1684 return EDP_LINK_TRAIN_400MV_6DB_IVB; 1685 1686 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0: 1687 return EDP_LINK_TRAIN_600MV_0DB_IVB; 1688 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5: 1689 return EDP_LINK_TRAIN_600MV_3_5DB_IVB; 1690 1691 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0: 1692 return EDP_LINK_TRAIN_800MV_0DB_IVB; 1693 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5: 1694 return EDP_LINK_TRAIN_800MV_3_5DB_IVB; 1695 1696 default: 1697 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:" 1698 "0x%x\n", signal_levels); 1699 return EDP_LINK_TRAIN_500MV_0DB_IVB; 1700 } 1701} 1702 1703/* Gen7.5's (HSW) DP voltage swing and pre-emphasis control */ 1704static uint32_t 1705intel_hsw_signal_levels(uint8_t train_set) 1706{ 1707 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK | 1708 DP_TRAIN_PRE_EMPHASIS_MASK); 1709 switch (signal_levels) { 1710 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0: 1711 return DDI_BUF_EMP_400MV_0DB_HSW; 1712 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5: 1713 return DDI_BUF_EMP_400MV_3_5DB_HSW; 1714 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6: 1715 return DDI_BUF_EMP_400MV_6DB_HSW; 1716 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_9_5: 1717 return DDI_BUF_EMP_400MV_9_5DB_HSW; 1718 1719 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0: 1720 return DDI_BUF_EMP_600MV_0DB_HSW; 1721 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5: 1722 return DDI_BUF_EMP_600MV_3_5DB_HSW; 1723 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6: 1724 return DDI_BUF_EMP_600MV_6DB_HSW; 1725 1726 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0: 1727 return DDI_BUF_EMP_800MV_0DB_HSW; 1728 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5: 1729 return DDI_BUF_EMP_800MV_3_5DB_HSW; 1730 default: 1731 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:" 1732 "0x%x\n", signal_levels); 1733 return DDI_BUF_EMP_400MV_0DB_HSW; 1734 } 1735} 1736 1737/* Properly updates "DP" with the correct signal levels. */ 1738static void 1739intel_dp_set_signal_levels(struct intel_dp *intel_dp, uint32_t *DP) 1740{ 1741 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 1742 struct drm_device *dev = intel_dig_port->base.base.dev; 1743 uint32_t signal_levels, mask; 1744 uint8_t train_set = intel_dp->train_set[0]; 1745 1746 if (IS_HASWELL(dev)) { 1747 signal_levels = intel_hsw_signal_levels(train_set); 1748 mask = DDI_BUF_EMP_MASK; 1749 } else if (IS_GEN7(dev) && is_cpu_edp(intel_dp) && !IS_VALLEYVIEW(dev)) { 1750 signal_levels = intel_gen7_edp_signal_levels(train_set); 1751 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_IVB; 1752 } else if (IS_GEN6(dev) && is_cpu_edp(intel_dp)) { 1753 signal_levels = intel_gen6_edp_signal_levels(train_set); 1754 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB; 1755 } else { 1756 signal_levels = intel_gen4_signal_levels(train_set); 1757 mask = DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK; 1758 } 1759 1760 DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels); 1761 1762 *DP = (*DP & ~mask) | signal_levels; 1763} 1764 1765static bool 1766intel_dp_set_link_train(struct intel_dp *intel_dp, 1767 uint32_t dp_reg_value, 1768 uint8_t dp_train_pat) 1769{ 1770 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 1771 struct drm_device *dev = intel_dig_port->base.base.dev; 1772 struct drm_i915_private *dev_priv = dev->dev_private; 1773 enum port port = intel_dig_port->port; 1774 int ret; 1775 uint32_t temp; 1776 1777 if (IS_HASWELL(dev)) { 1778 temp = I915_READ(DP_TP_CTL(port)); 1779 1780 if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE) 1781 temp |= DP_TP_CTL_SCRAMBLE_DISABLE; 1782 else 1783 temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE; 1784 1785 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK; 1786 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) { 1787 case DP_TRAINING_PATTERN_DISABLE: 1788 1789 if (port != PORT_A) { 1790 temp |= DP_TP_CTL_LINK_TRAIN_IDLE; 1791 I915_WRITE(DP_TP_CTL(port), temp); 1792 1793 if (wait_for((I915_READ(DP_TP_STATUS(port)) & 1794 DP_TP_STATUS_IDLE_DONE), 1)) 1795 DRM_ERROR("Timed out waiting for DP idle patterns\n"); 1796 1797 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK; 1798 } 1799 1800 temp |= DP_TP_CTL_LINK_TRAIN_NORMAL; 1801 1802 break; 1803 case DP_TRAINING_PATTERN_1: 1804 temp |= DP_TP_CTL_LINK_TRAIN_PAT1; 1805 break; 1806 case DP_TRAINING_PATTERN_2: 1807 temp |= DP_TP_CTL_LINK_TRAIN_PAT2; 1808 break; 1809 case DP_TRAINING_PATTERN_3: 1810 temp |= DP_TP_CTL_LINK_TRAIN_PAT3; 1811 break; 1812 } 1813 I915_WRITE(DP_TP_CTL(port), temp); 1814 1815 } else if (HAS_PCH_CPT(dev) && 1816 (IS_GEN7(dev) || !is_cpu_edp(intel_dp))) { 1817 dp_reg_value &= ~DP_LINK_TRAIN_MASK_CPT; 1818 1819 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) { 1820 case DP_TRAINING_PATTERN_DISABLE: 1821 dp_reg_value |= DP_LINK_TRAIN_OFF_CPT; 1822 break; 1823 case DP_TRAINING_PATTERN_1: 1824 dp_reg_value |= DP_LINK_TRAIN_PAT_1_CPT; 1825 break; 1826 case DP_TRAINING_PATTERN_2: 1827 dp_reg_value |= DP_LINK_TRAIN_PAT_2_CPT; 1828 break; 1829 case DP_TRAINING_PATTERN_3: 1830 DRM_ERROR("DP training pattern 3 not supported\n"); 1831 dp_reg_value |= DP_LINK_TRAIN_PAT_2_CPT; 1832 break; 1833 } 1834 1835 } else { 1836 dp_reg_value &= ~DP_LINK_TRAIN_MASK; 1837 1838 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) { 1839 case DP_TRAINING_PATTERN_DISABLE: 1840 dp_reg_value |= DP_LINK_TRAIN_OFF; 1841 break; 1842 case DP_TRAINING_PATTERN_1: 1843 dp_reg_value |= DP_LINK_TRAIN_PAT_1; 1844 break; 1845 case DP_TRAINING_PATTERN_2: 1846 dp_reg_value |= DP_LINK_TRAIN_PAT_2; 1847 break; 1848 case DP_TRAINING_PATTERN_3: 1849 DRM_ERROR("DP training pattern 3 not supported\n"); 1850 dp_reg_value |= DP_LINK_TRAIN_PAT_2; 1851 break; 1852 } 1853 } 1854 1855 I915_WRITE(intel_dp->output_reg, dp_reg_value); 1856 POSTING_READ(intel_dp->output_reg); 1857 1858 intel_dp_aux_native_write_1(intel_dp, 1859 DP_TRAINING_PATTERN_SET, 1860 dp_train_pat); 1861 1862 if ((dp_train_pat & DP_TRAINING_PATTERN_MASK) != 1863 DP_TRAINING_PATTERN_DISABLE) { 1864 ret = intel_dp_aux_native_write(intel_dp, 1865 DP_TRAINING_LANE0_SET, 1866 intel_dp->train_set, 1867 intel_dp->lane_count); 1868 if (ret != intel_dp->lane_count) 1869 return false; 1870 } 1871 1872 return true; 1873} 1874 1875/* Enable corresponding port and start training pattern 1 */ 1876void 1877intel_dp_start_link_train(struct intel_dp *intel_dp) 1878{ 1879 struct drm_encoder *encoder = &dp_to_dig_port(intel_dp)->base.base; 1880 struct drm_device *dev = encoder->dev; 1881 int i; 1882 uint8_t voltage; 1883 bool clock_recovery = false; 1884 int voltage_tries, loop_tries; 1885 uint32_t DP = intel_dp->DP; 1886 1887 if (HAS_DDI(dev)) 1888 intel_ddi_prepare_link_retrain(encoder); 1889 1890 /* Write the link configuration data */ 1891 intel_dp_aux_native_write(intel_dp, DP_LINK_BW_SET, 1892 intel_dp->link_configuration, 1893 DP_LINK_CONFIGURATION_SIZE); 1894 1895 DP |= DP_PORT_EN; 1896 1897 memset(intel_dp->train_set, 0, 4); 1898 voltage = 0xff; 1899 voltage_tries = 0; 1900 loop_tries = 0; 1901 clock_recovery = false; 1902 for (;;) { 1903 /* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */ 1904 uint8_t link_status[DP_LINK_STATUS_SIZE]; 1905 1906 intel_dp_set_signal_levels(intel_dp, &DP); 1907 1908 /* Set training pattern 1 */ 1909 if (!intel_dp_set_link_train(intel_dp, DP, 1910 DP_TRAINING_PATTERN_1 | 1911 DP_LINK_SCRAMBLING_DISABLE)) 1912 break; 1913 1914 drm_dp_link_train_clock_recovery_delay(intel_dp->dpcd); 1915 if (!intel_dp_get_link_status(intel_dp, link_status)) { 1916 DRM_ERROR("failed to get link status\n"); 1917 break; 1918 } 1919 1920 if (drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) { 1921 DRM_DEBUG_KMS("clock recovery OK\n"); 1922 clock_recovery = true; 1923 break; 1924 } 1925 1926 /* Check to see if we've tried the max voltage */ 1927 for (i = 0; i < intel_dp->lane_count; i++) 1928 if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0) 1929 break; 1930 if (i == intel_dp->lane_count && voltage_tries == 5) { 1931 ++loop_tries; 1932 if (loop_tries == 5) { 1933 DRM_DEBUG_KMS("too many full retries, give up\n"); 1934 break; 1935 } 1936 memset(intel_dp->train_set, 0, 4); 1937 voltage_tries = 0; 1938 continue; 1939 } 1940 1941 /* Check to see if we've tried the same voltage 5 times */ 1942 if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) { 1943 ++voltage_tries; 1944 if (voltage_tries == 5) { 1945 DRM_DEBUG_KMS("too many voltage retries, give up\n"); 1946 break; 1947 } 1948 } else 1949 voltage_tries = 0; 1950 voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK; 1951 1952 /* Compute new intel_dp->train_set as requested by target */ 1953 intel_get_adjust_train(intel_dp, link_status); 1954 } 1955 1956 intel_dp->DP = DP; 1957} 1958 1959void 1960intel_dp_complete_link_train(struct intel_dp *intel_dp) 1961{ 1962 bool channel_eq = false; 1963 int tries, cr_tries; 1964 uint32_t DP = intel_dp->DP; 1965 1966 /* channel equalization */ 1967 tries = 0; 1968 cr_tries = 0; 1969 channel_eq = false; 1970 for (;;) { 1971 uint8_t link_status[DP_LINK_STATUS_SIZE]; 1972 1973 if (cr_tries > 5) { 1974 DRM_ERROR("failed to train DP, aborting\n"); 1975 intel_dp_link_down(intel_dp); 1976 break; 1977 } 1978 1979 intel_dp_set_signal_levels(intel_dp, &DP); 1980 1981 /* channel eq pattern */ 1982 if (!intel_dp_set_link_train(intel_dp, DP, 1983 DP_TRAINING_PATTERN_2 | 1984 DP_LINK_SCRAMBLING_DISABLE)) 1985 break; 1986 1987 drm_dp_link_train_channel_eq_delay(intel_dp->dpcd); 1988 if (!intel_dp_get_link_status(intel_dp, link_status)) 1989 break; 1990 1991 /* Make sure clock is still ok */ 1992 if (!drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) { 1993 intel_dp_start_link_train(intel_dp); 1994 cr_tries++; 1995 continue; 1996 } 1997 1998 if (drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) { 1999 channel_eq = true; 2000 break; 2001 } 2002 2003 /* Try 5 times, then try clock recovery if that fails */ 2004 if (tries > 5) { 2005 intel_dp_link_down(intel_dp); 2006 intel_dp_start_link_train(intel_dp); 2007 tries = 0; 2008 cr_tries++; 2009 continue; 2010 } 2011 2012 /* Compute new intel_dp->train_set as requested by target */ 2013 intel_get_adjust_train(intel_dp, link_status); 2014 ++tries; 2015 } 2016 2017 if (channel_eq) 2018 DRM_DEBUG_KMS("Channel EQ done. DP Training successfull\n"); 2019 2020 intel_dp_set_link_train(intel_dp, DP, DP_TRAINING_PATTERN_DISABLE); 2021} 2022 2023static void 2024intel_dp_link_down(struct intel_dp *intel_dp) 2025{ 2026 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 2027 struct drm_device *dev = intel_dig_port->base.base.dev; 2028 struct drm_i915_private *dev_priv = dev->dev_private; 2029 struct intel_crtc *intel_crtc = 2030 to_intel_crtc(intel_dig_port->base.base.crtc); 2031 uint32_t DP = intel_dp->DP; 2032 2033 /* 2034 * DDI code has a strict mode set sequence and we should try to respect 2035 * it, otherwise we might hang the machine in many different ways. So we 2036 * really should be disabling the port only on a complete crtc_disable 2037 * sequence. This function is just called under two conditions on DDI 2038 * code: 2039 * - Link train failed while doing crtc_enable, and on this case we 2040 * really should respect the mode set sequence and wait for a 2041 * crtc_disable. 2042 * - Someone turned the monitor off and intel_dp_check_link_status 2043 * called us. We don't need to disable the whole port on this case, so 2044 * when someone turns the monitor on again, 2045 * intel_ddi_prepare_link_retrain will take care of redoing the link 2046 * train. 2047 */ 2048 if (HAS_DDI(dev)) 2049 return; 2050 2051 if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0)) 2052 return; 2053 2054 DRM_DEBUG_KMS("\n"); 2055 2056 if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || !is_cpu_edp(intel_dp))) { 2057 DP &= ~DP_LINK_TRAIN_MASK_CPT; 2058 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT); 2059 } else { 2060 DP &= ~DP_LINK_TRAIN_MASK; 2061 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE); 2062 } 2063 POSTING_READ(intel_dp->output_reg); 2064 2065 /* We don't really know why we're doing this */ 2066 intel_wait_for_vblank(dev, intel_crtc->pipe); 2067 2068 if (HAS_PCH_IBX(dev) && 2069 I915_READ(intel_dp->output_reg) & DP_PIPEB_SELECT) { 2070 struct drm_crtc *crtc = intel_dig_port->base.base.crtc; 2071 2072 /* Hardware workaround: leaving our transcoder select 2073 * set to transcoder B while it's off will prevent the 2074 * corresponding HDMI output on transcoder A. 2075 * 2076 * Combine this with another hardware workaround: 2077 * transcoder select bit can only be cleared while the 2078 * port is enabled. 2079 */ 2080 DP &= ~DP_PIPEB_SELECT; 2081 I915_WRITE(intel_dp->output_reg, DP); 2082 2083 /* Changes to enable or select take place the vblank 2084 * after being written. 2085 */ 2086 if (WARN_ON(crtc == NULL)) { 2087 /* We should never try to disable a port without a crtc 2088 * attached. For paranoia keep the code around for a 2089 * bit. */ 2090 POSTING_READ(intel_dp->output_reg); 2091 msleep(50); 2092 } else 2093 intel_wait_for_vblank(dev, intel_crtc->pipe); 2094 } 2095 2096 DP &= ~DP_AUDIO_OUTPUT_ENABLE; 2097 I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN); 2098 POSTING_READ(intel_dp->output_reg); 2099 msleep(intel_dp->panel_power_down_delay); 2100} 2101 2102static bool 2103intel_dp_get_dpcd(struct intel_dp *intel_dp) 2104{ 2105 char dpcd_hex_dump[sizeof(intel_dp->dpcd) * 3]; 2106 2107 if (intel_dp_aux_native_read_retry(intel_dp, 0x000, intel_dp->dpcd, 2108 sizeof(intel_dp->dpcd)) == 0) 2109 return false; /* aux transfer failed */ 2110 2111 hex_dump_to_buffer(intel_dp->dpcd, sizeof(intel_dp->dpcd), 2112 32, 1, dpcd_hex_dump, sizeof(dpcd_hex_dump), false); 2113 DRM_DEBUG_KMS("DPCD: %s\n", dpcd_hex_dump); 2114 2115 if (intel_dp->dpcd[DP_DPCD_REV] == 0) 2116 return false; /* DPCD not present */ 2117 2118 if (!(intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] & 2119 DP_DWN_STRM_PORT_PRESENT)) 2120 return true; /* native DP sink */ 2121 2122 if (intel_dp->dpcd[DP_DPCD_REV] == 0x10) 2123 return true; /* no per-port downstream info */ 2124 2125 if (intel_dp_aux_native_read_retry(intel_dp, DP_DOWNSTREAM_PORT_0, 2126 intel_dp->downstream_ports, 2127 DP_MAX_DOWNSTREAM_PORTS) == 0) 2128 return false; /* downstream port status fetch failed */ 2129 2130 return true; 2131} 2132 2133static void 2134intel_dp_probe_oui(struct intel_dp *intel_dp) 2135{ 2136 u8 buf[3]; 2137 2138 if (!(intel_dp->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT)) 2139 return; 2140 2141 ironlake_edp_panel_vdd_on(intel_dp); 2142 2143 if (intel_dp_aux_native_read_retry(intel_dp, DP_SINK_OUI, buf, 3)) 2144 DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n", 2145 buf[0], buf[1], buf[2]); 2146 2147 if (intel_dp_aux_native_read_retry(intel_dp, DP_BRANCH_OUI, buf, 3)) 2148 DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n", 2149 buf[0], buf[1], buf[2]); 2150 2151 ironlake_edp_panel_vdd_off(intel_dp, false); 2152} 2153 2154static bool 2155intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector) 2156{ 2157 int ret; 2158 2159 ret = intel_dp_aux_native_read_retry(intel_dp, 2160 DP_DEVICE_SERVICE_IRQ_VECTOR, 2161 sink_irq_vector, 1); 2162 if (!ret) 2163 return false; 2164 2165 return true; 2166} 2167 2168static void 2169intel_dp_handle_test_request(struct intel_dp *intel_dp) 2170{ 2171 /* NAK by default */ 2172 intel_dp_aux_native_write_1(intel_dp, DP_TEST_RESPONSE, DP_TEST_NAK); 2173} 2174 2175/* 2176 * According to DP spec 2177 * 5.1.2: 2178 * 1. Read DPCD 2179 * 2. Configure link according to Receiver Capabilities 2180 * 3. Use Link Training from 2.5.3.3 and 3.5.1.3 2181 * 4. Check link status on receipt of hot-plug interrupt 2182 */ 2183 2184void 2185intel_dp_check_link_status(struct intel_dp *intel_dp) 2186{ 2187 struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base; 2188 u8 sink_irq_vector; 2189 u8 link_status[DP_LINK_STATUS_SIZE]; 2190 2191 if (!intel_encoder->connectors_active) 2192 return; 2193 2194 if (WARN_ON(!intel_encoder->base.crtc)) 2195 return; 2196 2197 /* Try to read receiver status if the link appears to be up */ 2198 if (!intel_dp_get_link_status(intel_dp, link_status)) { 2199 intel_dp_link_down(intel_dp); 2200 return; 2201 } 2202 2203 /* Now read the DPCD to see if it's actually running */ 2204 if (!intel_dp_get_dpcd(intel_dp)) { 2205 intel_dp_link_down(intel_dp); 2206 return; 2207 } 2208 2209 /* Try to read the source of the interrupt */ 2210 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 && 2211 intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) { 2212 /* Clear interrupt source */ 2213 intel_dp_aux_native_write_1(intel_dp, 2214 DP_DEVICE_SERVICE_IRQ_VECTOR, 2215 sink_irq_vector); 2216 2217 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST) 2218 intel_dp_handle_test_request(intel_dp); 2219 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ)) 2220 DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n"); 2221 } 2222 2223 if (!drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) { 2224 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n", 2225 drm_get_encoder_name(&intel_encoder->base)); 2226 intel_dp_start_link_train(intel_dp); 2227 intel_dp_complete_link_train(intel_dp); 2228 } 2229} 2230 2231/* XXX this is probably wrong for multiple downstream ports */ 2232static enum drm_connector_status 2233intel_dp_detect_dpcd(struct intel_dp *intel_dp) 2234{ 2235 uint8_t *dpcd = intel_dp->dpcd; 2236 bool hpd; 2237 uint8_t type; 2238 2239 if (!intel_dp_get_dpcd(intel_dp)) 2240 return connector_status_disconnected; 2241 2242 /* if there's no downstream port, we're done */ 2243 if (!(dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT)) 2244 return connector_status_connected; 2245 2246 /* If we're HPD-aware, SINK_COUNT changes dynamically */ 2247 hpd = !!(intel_dp->downstream_ports[0] & DP_DS_PORT_HPD); 2248 if (hpd) { 2249 uint8_t reg; 2250 if (!intel_dp_aux_native_read_retry(intel_dp, DP_SINK_COUNT, 2251 ®, 1)) 2252 return connector_status_unknown; 2253 return DP_GET_SINK_COUNT(reg) ? connector_status_connected 2254 : connector_status_disconnected; 2255 } 2256 2257 /* If no HPD, poke DDC gently */ 2258 if (drm_probe_ddc(&intel_dp->adapter)) 2259 return connector_status_connected; 2260 2261 /* Well we tried, say unknown for unreliable port types */ 2262 type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK; 2263 if (type == DP_DS_PORT_TYPE_VGA || type == DP_DS_PORT_TYPE_NON_EDID) 2264 return connector_status_unknown; 2265 2266 /* Anything else is out of spec, warn and ignore */ 2267 DRM_DEBUG_KMS("Broken DP branch device, ignoring\n"); 2268 return connector_status_disconnected; 2269} 2270 2271static enum drm_connector_status 2272ironlake_dp_detect(struct intel_dp *intel_dp) 2273{ 2274 struct drm_device *dev = intel_dp_to_dev(intel_dp); 2275 struct drm_i915_private *dev_priv = dev->dev_private; 2276 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 2277 enum drm_connector_status status; 2278 2279 /* Can't disconnect eDP, but you can close the lid... */ 2280 if (is_edp(intel_dp)) { 2281 status = intel_panel_detect(dev); 2282 if (status == connector_status_unknown) 2283 status = connector_status_connected; 2284 return status; 2285 } 2286 2287 if (!ibx_digital_port_connected(dev_priv, intel_dig_port)) 2288 return connector_status_disconnected; 2289 2290 return intel_dp_detect_dpcd(intel_dp); 2291} 2292 2293static enum drm_connector_status 2294g4x_dp_detect(struct intel_dp *intel_dp) 2295{ 2296 struct drm_device *dev = intel_dp_to_dev(intel_dp); 2297 struct drm_i915_private *dev_priv = dev->dev_private; 2298 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 2299 uint32_t bit; 2300 2301 switch (intel_dig_port->port) { 2302 case PORT_B: 2303 bit = DPB_HOTPLUG_LIVE_STATUS; 2304 break; 2305 case PORT_C: 2306 bit = DPC_HOTPLUG_LIVE_STATUS; 2307 break; 2308 case PORT_D: 2309 bit = DPD_HOTPLUG_LIVE_STATUS; 2310 break; 2311 default: 2312 return connector_status_unknown; 2313 } 2314 2315 if ((I915_READ(PORT_HOTPLUG_STAT) & bit) == 0) 2316 return connector_status_disconnected; 2317 2318 return intel_dp_detect_dpcd(intel_dp); 2319} 2320 2321static struct edid * 2322intel_dp_get_edid(struct drm_connector *connector, struct i2c_adapter *adapter) 2323{ 2324 struct intel_connector *intel_connector = to_intel_connector(connector); 2325 2326 /* use cached edid if we have one */ 2327 if (intel_connector->edid) { 2328 struct edid *edid; 2329 int size; 2330 2331 /* invalid edid */ 2332 if (IS_ERR(intel_connector->edid)) 2333 return NULL; 2334 2335 size = (intel_connector->edid->extensions + 1) * EDID_LENGTH; 2336 edid = kmalloc(size, GFP_KERNEL); 2337 if (!edid) 2338 return NULL; 2339 2340 memcpy(edid, intel_connector->edid, size); 2341 return edid; 2342 } 2343 2344 return drm_get_edid(connector, adapter); 2345} 2346 2347static int 2348intel_dp_get_edid_modes(struct drm_connector *connector, struct i2c_adapter *adapter) 2349{ 2350 struct intel_connector *intel_connector = to_intel_connector(connector); 2351 2352 /* use cached edid if we have one */ 2353 if (intel_connector->edid) { 2354 /* invalid edid */ 2355 if (IS_ERR(intel_connector->edid)) 2356 return 0; 2357 2358 return intel_connector_update_modes(connector, 2359 intel_connector->edid); 2360 } 2361 2362 return intel_ddc_get_modes(connector, adapter); 2363} 2364 2365static enum drm_connector_status 2366intel_dp_detect(struct drm_connector *connector, bool force) 2367{ 2368 struct intel_dp *intel_dp = intel_attached_dp(connector); 2369 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 2370 struct intel_encoder *intel_encoder = &intel_dig_port->base; 2371 struct drm_device *dev = connector->dev; 2372 enum drm_connector_status status; 2373 struct edid *edid = NULL; 2374 2375 intel_dp->has_audio = false; 2376 2377 if (HAS_PCH_SPLIT(dev)) 2378 status = ironlake_dp_detect(intel_dp); 2379 else 2380 status = g4x_dp_detect(intel_dp); 2381 2382 if (status != connector_status_connected) 2383 return status; 2384 2385 intel_dp_probe_oui(intel_dp); 2386 2387 if (intel_dp->force_audio != HDMI_AUDIO_AUTO) { 2388 intel_dp->has_audio = (intel_dp->force_audio == HDMI_AUDIO_ON); 2389 } else { 2390 edid = intel_dp_get_edid(connector, &intel_dp->adapter); 2391 if (edid) { 2392 intel_dp->has_audio = drm_detect_monitor_audio(edid); 2393 kfree(edid); 2394 } 2395 } 2396 2397 if (intel_encoder->type != INTEL_OUTPUT_EDP) 2398 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT; 2399 return connector_status_connected; 2400} 2401 2402static int intel_dp_get_modes(struct drm_connector *connector) 2403{ 2404 struct intel_dp *intel_dp = intel_attached_dp(connector); 2405 struct intel_connector *intel_connector = to_intel_connector(connector); 2406 struct drm_device *dev = connector->dev; 2407 int ret; 2408 2409 /* We should parse the EDID data and find out if it has an audio sink 2410 */ 2411 2412 ret = intel_dp_get_edid_modes(connector, &intel_dp->adapter); 2413 if (ret) 2414 return ret; 2415 2416 /* if eDP has no EDID, fall back to fixed mode */ 2417 if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) { 2418 struct drm_display_mode *mode; 2419 mode = drm_mode_duplicate(dev, 2420 intel_connector->panel.fixed_mode); 2421 if (mode) { 2422 drm_mode_probed_add(connector, mode); 2423 return 1; 2424 } 2425 } 2426 return 0; 2427} 2428 2429static bool 2430intel_dp_detect_audio(struct drm_connector *connector) 2431{ 2432 struct intel_dp *intel_dp = intel_attached_dp(connector); 2433 struct edid *edid; 2434 bool has_audio = false; 2435 2436 edid = intel_dp_get_edid(connector, &intel_dp->adapter); 2437 if (edid) { 2438 has_audio = drm_detect_monitor_audio(edid); 2439 kfree(edid); 2440 } 2441 2442 return has_audio; 2443} 2444 2445static int 2446intel_dp_set_property(struct drm_connector *connector, 2447 struct drm_property *property, 2448 uint64_t val) 2449{ 2450 struct drm_i915_private *dev_priv = connector->dev->dev_private; 2451 struct intel_connector *intel_connector = to_intel_connector(connector); 2452 struct intel_encoder *intel_encoder = intel_attached_encoder(connector); 2453 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base); 2454 int ret; 2455 2456 ret = drm_object_property_set_value(&connector->base, property, val); 2457 if (ret) 2458 return ret; 2459 2460 if (property == dev_priv->force_audio_property) { 2461 int i = val; 2462 bool has_audio; 2463 2464 if (i == intel_dp->force_audio) 2465 return 0; 2466 2467 intel_dp->force_audio = i; 2468 2469 if (i == HDMI_AUDIO_AUTO) 2470 has_audio = intel_dp_detect_audio(connector); 2471 else 2472 has_audio = (i == HDMI_AUDIO_ON); 2473 2474 if (has_audio == intel_dp->has_audio) 2475 return 0; 2476 2477 intel_dp->has_audio = has_audio; 2478 goto done; 2479 } 2480 2481 if (property == dev_priv->broadcast_rgb_property) { 2482 switch (val) { 2483 case INTEL_BROADCAST_RGB_AUTO: 2484 intel_dp->color_range_auto = true; 2485 break; 2486 case INTEL_BROADCAST_RGB_FULL: 2487 intel_dp->color_range_auto = false; 2488 intel_dp->color_range = 0; 2489 break; 2490 case INTEL_BROADCAST_RGB_LIMITED: 2491 intel_dp->color_range_auto = false; 2492 intel_dp->color_range = DP_COLOR_RANGE_16_235; 2493 break; 2494 default: 2495 return -EINVAL; 2496 } 2497 goto done; 2498 } 2499 2500 if (is_edp(intel_dp) && 2501 property == connector->dev->mode_config.scaling_mode_property) { 2502 if (val == DRM_MODE_SCALE_NONE) { 2503 DRM_DEBUG_KMS("no scaling not supported\n"); 2504 return -EINVAL; 2505 } 2506 2507 if (intel_connector->panel.fitting_mode == val) { 2508 /* the eDP scaling property is not changed */ 2509 return 0; 2510 } 2511 intel_connector->panel.fitting_mode = val; 2512 2513 goto done; 2514 } 2515 2516 return -EINVAL; 2517 2518done: 2519 if (intel_encoder->base.crtc) 2520 intel_crtc_restore_mode(intel_encoder->base.crtc); 2521 2522 return 0; 2523} 2524 2525static void 2526intel_dp_destroy(struct drm_connector *connector) 2527{ 2528 struct drm_device *dev = connector->dev; 2529 struct intel_dp *intel_dp = intel_attached_dp(connector); 2530 struct intel_connector *intel_connector = to_intel_connector(connector); 2531 2532 if (!IS_ERR_OR_NULL(intel_connector->edid)) 2533 kfree(intel_connector->edid); 2534 2535 if (is_edp(intel_dp)) { 2536 intel_panel_destroy_backlight(dev); 2537 intel_panel_fini(&intel_connector->panel); 2538 } 2539 2540 drm_sysfs_connector_remove(connector); 2541 drm_connector_cleanup(connector); 2542 kfree(connector); 2543} 2544 2545void intel_dp_encoder_destroy(struct drm_encoder *encoder) 2546{ 2547 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); 2548 struct intel_dp *intel_dp = &intel_dig_port->dp; 2549 2550 i2c_del_adapter(&intel_dp->adapter); 2551 drm_encoder_cleanup(encoder); 2552 if (is_edp(intel_dp)) { 2553 cancel_delayed_work_sync(&intel_dp->panel_vdd_work); 2554 ironlake_panel_vdd_off_sync(intel_dp); 2555 } 2556 kfree(intel_dig_port); 2557} 2558 2559static const struct drm_encoder_helper_funcs intel_dp_helper_funcs = { 2560 .mode_fixup = intel_dp_mode_fixup, 2561 .mode_set = intel_dp_mode_set, 2562 .disable = intel_encoder_noop, 2563}; 2564 2565static const struct drm_connector_funcs intel_dp_connector_funcs = { 2566 .dpms = intel_connector_dpms, 2567 .detect = intel_dp_detect, 2568 .fill_modes = drm_helper_probe_single_connector_modes, 2569 .set_property = intel_dp_set_property, 2570 .destroy = intel_dp_destroy, 2571}; 2572 2573static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = { 2574 .get_modes = intel_dp_get_modes, 2575 .mode_valid = intel_dp_mode_valid, 2576 .best_encoder = intel_best_encoder, 2577}; 2578 2579static const struct drm_encoder_funcs intel_dp_enc_funcs = { 2580 .destroy = intel_dp_encoder_destroy, 2581}; 2582 2583static void 2584intel_dp_hot_plug(struct intel_encoder *intel_encoder) 2585{ 2586 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base); 2587 2588 intel_dp_check_link_status(intel_dp); 2589} 2590 2591/* Return which DP Port should be selected for Transcoder DP control */ 2592int 2593intel_trans_dp_port_sel(struct drm_crtc *crtc) 2594{ 2595 struct drm_device *dev = crtc->dev; 2596 struct intel_encoder *intel_encoder; 2597 struct intel_dp *intel_dp; 2598 2599 for_each_encoder_on_crtc(dev, crtc, intel_encoder) { 2600 intel_dp = enc_to_intel_dp(&intel_encoder->base); 2601 2602 if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT || 2603 intel_encoder->type == INTEL_OUTPUT_EDP) 2604 return intel_dp->output_reg; 2605 } 2606 2607 return -1; 2608} 2609 2610/* check the VBT to see whether the eDP is on DP-D port */ 2611bool intel_dpd_is_edp(struct drm_device *dev) 2612{ 2613 struct drm_i915_private *dev_priv = dev->dev_private; 2614 struct child_device_config *p_child; 2615 int i; 2616 2617 if (!dev_priv->child_dev_num) 2618 return false; 2619 2620 for (i = 0; i < dev_priv->child_dev_num; i++) { 2621 p_child = dev_priv->child_dev + i; 2622 2623 if (p_child->dvo_port == PORT_IDPD && 2624 p_child->device_type == DEVICE_TYPE_eDP) 2625 return true; 2626 } 2627 return false; 2628} 2629 2630static void 2631intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector) 2632{ 2633 struct intel_connector *intel_connector = to_intel_connector(connector); 2634 2635 intel_attach_force_audio_property(connector); 2636 intel_attach_broadcast_rgb_property(connector); 2637 intel_dp->color_range_auto = true; 2638 2639 if (is_edp(intel_dp)) { 2640 drm_mode_create_scaling_mode_property(connector->dev); 2641 drm_object_attach_property( 2642 &connector->base, 2643 connector->dev->mode_config.scaling_mode_property, 2644 DRM_MODE_SCALE_ASPECT); 2645 intel_connector->panel.fitting_mode = DRM_MODE_SCALE_ASPECT; 2646 } 2647} 2648 2649static void 2650intel_dp_init_panel_power_sequencer(struct drm_device *dev, 2651 struct intel_dp *intel_dp) 2652{ 2653 struct drm_i915_private *dev_priv = dev->dev_private; 2654 struct edp_power_seq cur, vbt, spec, final; 2655 u32 pp_on, pp_off, pp_div, pp; 2656 2657 /* Workaround: Need to write PP_CONTROL with the unlock key as 2658 * the very first thing. */ 2659 pp = ironlake_get_pp_control(dev_priv); 2660 I915_WRITE(PCH_PP_CONTROL, pp); 2661 2662 pp_on = I915_READ(PCH_PP_ON_DELAYS); 2663 pp_off = I915_READ(PCH_PP_OFF_DELAYS); 2664 pp_div = I915_READ(PCH_PP_DIVISOR); 2665 2666 /* Pull timing values out of registers */ 2667 cur.t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >> 2668 PANEL_POWER_UP_DELAY_SHIFT; 2669 2670 cur.t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >> 2671 PANEL_LIGHT_ON_DELAY_SHIFT; 2672 2673 cur.t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >> 2674 PANEL_LIGHT_OFF_DELAY_SHIFT; 2675 2676 cur.t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >> 2677 PANEL_POWER_DOWN_DELAY_SHIFT; 2678 2679 cur.t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >> 2680 PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000; 2681 2682 DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n", 2683 cur.t1_t3, cur.t8, cur.t9, cur.t10, cur.t11_t12); 2684 2685 vbt = dev_priv->edp.pps; 2686 2687 /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of 2688 * our hw here, which are all in 100usec. */ 2689 spec.t1_t3 = 210 * 10; 2690 spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */ 2691 spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */ 2692 spec.t10 = 500 * 10; 2693 /* This one is special and actually in units of 100ms, but zero 2694 * based in the hw (so we need to add 100 ms). But the sw vbt 2695 * table multiplies it with 1000 to make it in units of 100usec, 2696 * too. */ 2697 spec.t11_t12 = (510 + 100) * 10; 2698 2699 DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n", 2700 vbt.t1_t3, vbt.t8, vbt.t9, vbt.t10, vbt.t11_t12); 2701 2702 /* Use the max of the register settings and vbt. If both are 2703 * unset, fall back to the spec limits. */ 2704#define assign_final(field) final.field = (max(cur.field, vbt.field) == 0 ? \ 2705 spec.field : \ 2706 max(cur.field, vbt.field)) 2707 assign_final(t1_t3); 2708 assign_final(t8); 2709 assign_final(t9); 2710 assign_final(t10); 2711 assign_final(t11_t12); 2712#undef assign_final 2713 2714#define get_delay(field) (DIV_ROUND_UP(final.field, 10)) 2715 intel_dp->panel_power_up_delay = get_delay(t1_t3); 2716 intel_dp->backlight_on_delay = get_delay(t8); 2717 intel_dp->backlight_off_delay = get_delay(t9); 2718 intel_dp->panel_power_down_delay = get_delay(t10); 2719 intel_dp->panel_power_cycle_delay = get_delay(t11_t12); 2720#undef get_delay 2721 2722 /* And finally store the new values in the power sequencer. */ 2723 pp_on = (final.t1_t3 << PANEL_POWER_UP_DELAY_SHIFT) | 2724 (final.t8 << PANEL_LIGHT_ON_DELAY_SHIFT); 2725 pp_off = (final.t9 << PANEL_LIGHT_OFF_DELAY_SHIFT) | 2726 (final.t10 << PANEL_POWER_DOWN_DELAY_SHIFT); 2727 /* Compute the divisor for the pp clock, simply match the Bspec 2728 * formula. */ 2729 pp_div = ((100 * intel_pch_rawclk(dev))/2 - 1) 2730 << PP_REFERENCE_DIVIDER_SHIFT; 2731 pp_div |= (DIV_ROUND_UP(final.t11_t12, 1000) 2732 << PANEL_POWER_CYCLE_DELAY_SHIFT); 2733 2734 /* Haswell doesn't have any port selection bits for the panel 2735 * power sequencer any more. */ 2736 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) { 2737 if (is_cpu_edp(intel_dp)) 2738 pp_on |= PANEL_POWER_PORT_DP_A; 2739 else 2740 pp_on |= PANEL_POWER_PORT_DP_D; 2741 } 2742 2743 I915_WRITE(PCH_PP_ON_DELAYS, pp_on); 2744 I915_WRITE(PCH_PP_OFF_DELAYS, pp_off); 2745 I915_WRITE(PCH_PP_DIVISOR, pp_div); 2746 2747 2748 DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n", 2749 intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay, 2750 intel_dp->panel_power_cycle_delay); 2751 2752 DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n", 2753 intel_dp->backlight_on_delay, intel_dp->backlight_off_delay); 2754 2755 DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n", 2756 I915_READ(PCH_PP_ON_DELAYS), 2757 I915_READ(PCH_PP_OFF_DELAYS), 2758 I915_READ(PCH_PP_DIVISOR)); 2759} 2760 2761void 2762intel_dp_init_connector(struct intel_digital_port *intel_dig_port, 2763 struct intel_connector *intel_connector) 2764{ 2765 struct drm_connector *connector = &intel_connector->base; 2766 struct intel_dp *intel_dp = &intel_dig_port->dp; 2767 struct intel_encoder *intel_encoder = &intel_dig_port->base; 2768 struct drm_device *dev = intel_encoder->base.dev; 2769 struct drm_i915_private *dev_priv = dev->dev_private; 2770 struct drm_display_mode *fixed_mode = NULL; 2771 enum port port = intel_dig_port->port; 2772 const char *name = NULL; 2773 int type; 2774 2775 /* Preserve the current hw state. */ 2776 intel_dp->DP = I915_READ(intel_dp->output_reg); 2777 intel_dp->attached_connector = intel_connector; 2778 2779 if (HAS_PCH_SPLIT(dev) && port == PORT_D) 2780 if (intel_dpd_is_edp(dev)) 2781 intel_dp->is_pch_edp = true; 2782 2783 /* 2784 * FIXME : We need to initialize built-in panels before external panels. 2785 * For X0, DP_C is fixed as eDP. Revisit this as part of VLV eDP cleanup 2786 */ 2787 if (IS_VALLEYVIEW(dev) && port == PORT_C) { 2788 type = DRM_MODE_CONNECTOR_eDP; 2789 intel_encoder->type = INTEL_OUTPUT_EDP; 2790 } else if (port == PORT_A || is_pch_edp(intel_dp)) { 2791 type = DRM_MODE_CONNECTOR_eDP; 2792 intel_encoder->type = INTEL_OUTPUT_EDP; 2793 } else { 2794 /* The intel_encoder->type value may be INTEL_OUTPUT_UNKNOWN for 2795 * DDI or INTEL_OUTPUT_DISPLAYPORT for the older gens, so don't 2796 * rewrite it. 2797 */ 2798 type = DRM_MODE_CONNECTOR_DisplayPort; 2799 } 2800 2801 drm_connector_init(dev, connector, &intel_dp_connector_funcs, type); 2802 drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs); 2803 2804 connector->polled = DRM_CONNECTOR_POLL_HPD; 2805 connector->interlace_allowed = true; 2806 connector->doublescan_allowed = 0; 2807 2808 INIT_DELAYED_WORK(&intel_dp->panel_vdd_work, 2809 ironlake_panel_vdd_work); 2810 2811 intel_connector_attach_encoder(intel_connector, intel_encoder); 2812 drm_sysfs_connector_add(connector); 2813 2814 if (HAS_DDI(dev)) 2815 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state; 2816 else 2817 intel_connector->get_hw_state = intel_connector_get_hw_state; 2818 2819 2820 /* Set up the DDC bus. */ 2821 switch (port) { 2822 case PORT_A: 2823 name = "DPDDC-A"; 2824 break; 2825 case PORT_B: 2826 dev_priv->hotplug_supported_mask |= DPB_HOTPLUG_INT_STATUS; 2827 name = "DPDDC-B"; 2828 break; 2829 case PORT_C: 2830 dev_priv->hotplug_supported_mask |= DPC_HOTPLUG_INT_STATUS; 2831 name = "DPDDC-C"; 2832 break; 2833 case PORT_D: 2834 dev_priv->hotplug_supported_mask |= DPD_HOTPLUG_INT_STATUS; 2835 name = "DPDDC-D"; 2836 break; 2837 default: 2838 WARN(1, "Invalid port %c\n", port_name(port)); 2839 break; 2840 } 2841 2842 if (is_edp(intel_dp)) 2843 intel_dp_init_panel_power_sequencer(dev, intel_dp); 2844 2845 intel_dp_i2c_init(intel_dp, intel_connector, name); 2846 2847 /* Cache DPCD and EDID for edp. */ 2848 if (is_edp(intel_dp)) { 2849 bool ret; 2850 struct drm_display_mode *scan; 2851 struct edid *edid; 2852 2853 ironlake_edp_panel_vdd_on(intel_dp); 2854 ret = intel_dp_get_dpcd(intel_dp); 2855 ironlake_edp_panel_vdd_off(intel_dp, false); 2856 2857 if (ret) { 2858 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) 2859 dev_priv->no_aux_handshake = 2860 intel_dp->dpcd[DP_MAX_DOWNSPREAD] & 2861 DP_NO_AUX_HANDSHAKE_LINK_TRAINING; 2862 } else { 2863 /* if this fails, presume the device is a ghost */ 2864 DRM_INFO("failed to retrieve link info, disabling eDP\n"); 2865 intel_dp_encoder_destroy(&intel_encoder->base); 2866 intel_dp_destroy(connector); 2867 return; 2868 } 2869 2870 ironlake_edp_panel_vdd_on(intel_dp); 2871 edid = drm_get_edid(connector, &intel_dp->adapter); 2872 if (edid) { 2873 if (drm_add_edid_modes(connector, edid)) { 2874 drm_mode_connector_update_edid_property(connector, edid); 2875 drm_edid_to_eld(connector, edid); 2876 } else { 2877 kfree(edid); 2878 edid = ERR_PTR(-EINVAL); 2879 } 2880 } else { 2881 edid = ERR_PTR(-ENOENT); 2882 } 2883 intel_connector->edid = edid; 2884 2885 /* prefer fixed mode from EDID if available */ 2886 list_for_each_entry(scan, &connector->probed_modes, head) { 2887 if ((scan->type & DRM_MODE_TYPE_PREFERRED)) { 2888 fixed_mode = drm_mode_duplicate(dev, scan); 2889 break; 2890 } 2891 } 2892 2893 /* fallback to VBT if available for eDP */ 2894 if (!fixed_mode && dev_priv->lfp_lvds_vbt_mode) { 2895 fixed_mode = drm_mode_duplicate(dev, dev_priv->lfp_lvds_vbt_mode); 2896 if (fixed_mode) 2897 fixed_mode->type |= DRM_MODE_TYPE_PREFERRED; 2898 } 2899 2900 ironlake_edp_panel_vdd_off(intel_dp, false); 2901 } 2902 2903 if (is_edp(intel_dp)) { 2904 intel_panel_init(&intel_connector->panel, fixed_mode); 2905 intel_panel_setup_backlight(connector); 2906 } 2907 2908 intel_dp_add_properties(intel_dp, connector); 2909 2910 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written 2911 * 0xd. Failure to do so will result in spurious interrupts being 2912 * generated on the port when a cable is not attached. 2913 */ 2914 if (IS_G4X(dev) && !IS_GM45(dev)) { 2915 u32 temp = I915_READ(PEG_BAND_GAP_DATA); 2916 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd); 2917 } 2918} 2919 2920void 2921intel_dp_init(struct drm_device *dev, int output_reg, enum port port) 2922{ 2923 struct intel_digital_port *intel_dig_port; 2924 struct intel_encoder *intel_encoder; 2925 struct drm_encoder *encoder; 2926 struct intel_connector *intel_connector; 2927 2928 intel_dig_port = kzalloc(sizeof(struct intel_digital_port), GFP_KERNEL); 2929 if (!intel_dig_port) 2930 return; 2931 2932 intel_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL); 2933 if (!intel_connector) { 2934 kfree(intel_dig_port); 2935 return; 2936 } 2937 2938 intel_encoder = &intel_dig_port->base; 2939 encoder = &intel_encoder->base; 2940 2941 drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs, 2942 DRM_MODE_ENCODER_TMDS); 2943 drm_encoder_helper_add(&intel_encoder->base, &intel_dp_helper_funcs); 2944 2945 intel_encoder->enable = intel_enable_dp; 2946 intel_encoder->pre_enable = intel_pre_enable_dp; 2947 intel_encoder->disable = intel_disable_dp; 2948 intel_encoder->post_disable = intel_post_disable_dp; 2949 intel_encoder->get_hw_state = intel_dp_get_hw_state; 2950 2951 intel_dig_port->port = port; 2952 intel_dig_port->dp.output_reg = output_reg; 2953 2954 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT; 2955 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2); 2956 intel_encoder->cloneable = false; 2957 intel_encoder->hot_plug = intel_dp_hot_plug; 2958 2959 intel_dp_init_connector(intel_dig_port, intel_connector); 2960} 2961