intel_dp.c revision 3c5a62b5226ca5db993660281e9c2a7275d9fb02
1/* 2 * Copyright © 2008 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 * Authors: 24 * Keith Packard <keithp@keithp.com> 25 * 26 */ 27 28#include <linux/i2c.h> 29#include <linux/slab.h> 30#include "drmP.h" 31#include "drm.h" 32#include "drm_crtc.h" 33#include "drm_crtc_helper.h" 34#include "intel_drv.h" 35#include "i915_drm.h" 36#include "i915_drv.h" 37#include "drm_dp_helper.h" 38 39 40#define DP_LINK_STATUS_SIZE 6 41#define DP_LINK_CHECK_TIMEOUT (10 * 1000) 42 43#define DP_LINK_CONFIGURATION_SIZE 9 44 45struct intel_dp { 46 struct intel_encoder base; 47 uint32_t output_reg; 48 uint32_t DP; 49 uint8_t link_configuration[DP_LINK_CONFIGURATION_SIZE]; 50 bool has_audio; 51 int force_audio; 52 int dpms_mode; 53 uint8_t link_bw; 54 uint8_t lane_count; 55 uint8_t dpcd[4]; 56 struct i2c_adapter adapter; 57 struct i2c_algo_dp_aux_data algo; 58 bool is_pch_edp; 59 uint8_t train_set[4]; 60 uint8_t link_status[DP_LINK_STATUS_SIZE]; 61 62 struct drm_property *force_audio_property; 63}; 64 65/** 66 * is_edp - is the given port attached to an eDP panel (either CPU or PCH) 67 * @intel_dp: DP struct 68 * 69 * If a CPU or PCH DP output is attached to an eDP panel, this function 70 * will return true, and false otherwise. 71 */ 72static bool is_edp(struct intel_dp *intel_dp) 73{ 74 return intel_dp->base.type == INTEL_OUTPUT_EDP; 75} 76 77/** 78 * is_pch_edp - is the port on the PCH and attached to an eDP panel? 79 * @intel_dp: DP struct 80 * 81 * Returns true if the given DP struct corresponds to a PCH DP port attached 82 * to an eDP panel, false otherwise. Helpful for determining whether we 83 * may need FDI resources for a given DP output or not. 84 */ 85static bool is_pch_edp(struct intel_dp *intel_dp) 86{ 87 return intel_dp->is_pch_edp; 88} 89 90static struct intel_dp *enc_to_intel_dp(struct drm_encoder *encoder) 91{ 92 return container_of(encoder, struct intel_dp, base.base); 93} 94 95static struct intel_dp *intel_attached_dp(struct drm_connector *connector) 96{ 97 return container_of(intel_attached_encoder(connector), 98 struct intel_dp, base); 99} 100 101/** 102 * intel_encoder_is_pch_edp - is the given encoder a PCH attached eDP? 103 * @encoder: DRM encoder 104 * 105 * Return true if @encoder corresponds to a PCH attached eDP panel. Needed 106 * by intel_display.c. 107 */ 108bool intel_encoder_is_pch_edp(struct drm_encoder *encoder) 109{ 110 struct intel_dp *intel_dp; 111 112 if (!encoder) 113 return false; 114 115 intel_dp = enc_to_intel_dp(encoder); 116 117 return is_pch_edp(intel_dp); 118} 119 120static void intel_dp_start_link_train(struct intel_dp *intel_dp); 121static void intel_dp_complete_link_train(struct intel_dp *intel_dp); 122static void intel_dp_link_down(struct intel_dp *intel_dp); 123 124void 125intel_edp_link_config (struct intel_encoder *intel_encoder, 126 int *lane_num, int *link_bw) 127{ 128 struct intel_dp *intel_dp = container_of(intel_encoder, struct intel_dp, base); 129 130 *lane_num = intel_dp->lane_count; 131 if (intel_dp->link_bw == DP_LINK_BW_1_62) 132 *link_bw = 162000; 133 else if (intel_dp->link_bw == DP_LINK_BW_2_7) 134 *link_bw = 270000; 135} 136 137static int 138intel_dp_max_lane_count(struct intel_dp *intel_dp) 139{ 140 int max_lane_count = 4; 141 142 if (intel_dp->dpcd[0] >= 0x11) { 143 max_lane_count = intel_dp->dpcd[2] & 0x1f; 144 switch (max_lane_count) { 145 case 1: case 2: case 4: 146 break; 147 default: 148 max_lane_count = 4; 149 } 150 } 151 return max_lane_count; 152} 153 154static int 155intel_dp_max_link_bw(struct intel_dp *intel_dp) 156{ 157 int max_link_bw = intel_dp->dpcd[1]; 158 159 switch (max_link_bw) { 160 case DP_LINK_BW_1_62: 161 case DP_LINK_BW_2_7: 162 break; 163 default: 164 max_link_bw = DP_LINK_BW_1_62; 165 break; 166 } 167 return max_link_bw; 168} 169 170static int 171intel_dp_link_clock(uint8_t link_bw) 172{ 173 if (link_bw == DP_LINK_BW_2_7) 174 return 270000; 175 else 176 return 162000; 177} 178 179/* I think this is a fiction */ 180static int 181intel_dp_link_required(struct drm_device *dev, struct intel_dp *intel_dp, int pixel_clock) 182{ 183 struct drm_i915_private *dev_priv = dev->dev_private; 184 185 if (is_edp(intel_dp)) 186 return (pixel_clock * dev_priv->edp.bpp + 7) / 8; 187 else 188 return pixel_clock * 3; 189} 190 191static int 192intel_dp_max_data_rate(int max_link_clock, int max_lanes) 193{ 194 return (max_link_clock * max_lanes * 8) / 10; 195} 196 197static int 198intel_dp_mode_valid(struct drm_connector *connector, 199 struct drm_display_mode *mode) 200{ 201 struct intel_dp *intel_dp = intel_attached_dp(connector); 202 struct drm_device *dev = connector->dev; 203 struct drm_i915_private *dev_priv = dev->dev_private; 204 int max_link_clock = intel_dp_link_clock(intel_dp_max_link_bw(intel_dp)); 205 int max_lanes = intel_dp_max_lane_count(intel_dp); 206 207 if (is_edp(intel_dp) && dev_priv->panel_fixed_mode) { 208 if (mode->hdisplay > dev_priv->panel_fixed_mode->hdisplay) 209 return MODE_PANEL; 210 211 if (mode->vdisplay > dev_priv->panel_fixed_mode->vdisplay) 212 return MODE_PANEL; 213 } 214 215 /* only refuse the mode on non eDP since we have seen some wierd eDP panels 216 which are outside spec tolerances but somehow work by magic */ 217 if (!is_edp(intel_dp) && 218 (intel_dp_link_required(connector->dev, intel_dp, mode->clock) 219 > intel_dp_max_data_rate(max_link_clock, max_lanes))) 220 return MODE_CLOCK_HIGH; 221 222 if (mode->clock < 10000) 223 return MODE_CLOCK_LOW; 224 225 return MODE_OK; 226} 227 228static uint32_t 229pack_aux(uint8_t *src, int src_bytes) 230{ 231 int i; 232 uint32_t v = 0; 233 234 if (src_bytes > 4) 235 src_bytes = 4; 236 for (i = 0; i < src_bytes; i++) 237 v |= ((uint32_t) src[i]) << ((3-i) * 8); 238 return v; 239} 240 241static void 242unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes) 243{ 244 int i; 245 if (dst_bytes > 4) 246 dst_bytes = 4; 247 for (i = 0; i < dst_bytes; i++) 248 dst[i] = src >> ((3-i) * 8); 249} 250 251/* hrawclock is 1/4 the FSB frequency */ 252static int 253intel_hrawclk(struct drm_device *dev) 254{ 255 struct drm_i915_private *dev_priv = dev->dev_private; 256 uint32_t clkcfg; 257 258 clkcfg = I915_READ(CLKCFG); 259 switch (clkcfg & CLKCFG_FSB_MASK) { 260 case CLKCFG_FSB_400: 261 return 100; 262 case CLKCFG_FSB_533: 263 return 133; 264 case CLKCFG_FSB_667: 265 return 166; 266 case CLKCFG_FSB_800: 267 return 200; 268 case CLKCFG_FSB_1067: 269 return 266; 270 case CLKCFG_FSB_1333: 271 return 333; 272 /* these two are just a guess; one of them might be right */ 273 case CLKCFG_FSB_1600: 274 case CLKCFG_FSB_1600_ALT: 275 return 400; 276 default: 277 return 133; 278 } 279} 280 281static int 282intel_dp_aux_ch(struct intel_dp *intel_dp, 283 uint8_t *send, int send_bytes, 284 uint8_t *recv, int recv_size) 285{ 286 uint32_t output_reg = intel_dp->output_reg; 287 struct drm_device *dev = intel_dp->base.base.dev; 288 struct drm_i915_private *dev_priv = dev->dev_private; 289 uint32_t ch_ctl = output_reg + 0x10; 290 uint32_t ch_data = ch_ctl + 4; 291 int i; 292 int recv_bytes; 293 uint32_t status; 294 uint32_t aux_clock_divider; 295 int try, precharge; 296 297 /* The clock divider is based off the hrawclk, 298 * and would like to run at 2MHz. So, take the 299 * hrawclk value and divide by 2 and use that 300 * 301 * Note that PCH attached eDP panels should use a 125MHz input 302 * clock divider. 303 */ 304 if (is_edp(intel_dp) && !is_pch_edp(intel_dp)) { 305 if (IS_GEN6(dev)) 306 aux_clock_divider = 200; /* SNB eDP input clock at 400Mhz */ 307 else 308 aux_clock_divider = 225; /* eDP input clock at 450Mhz */ 309 } else if (HAS_PCH_SPLIT(dev)) 310 aux_clock_divider = 62; /* IRL input clock fixed at 125Mhz */ 311 else 312 aux_clock_divider = intel_hrawclk(dev) / 2; 313 314 if (IS_GEN6(dev)) 315 precharge = 3; 316 else 317 precharge = 5; 318 319 if (I915_READ(ch_ctl) & DP_AUX_CH_CTL_SEND_BUSY) { 320 DRM_ERROR("dp_aux_ch not started status 0x%08x\n", 321 I915_READ(ch_ctl)); 322 return -EBUSY; 323 } 324 325 /* Must try at least 3 times according to DP spec */ 326 for (try = 0; try < 5; try++) { 327 /* Load the send data into the aux channel data registers */ 328 for (i = 0; i < send_bytes; i += 4) 329 I915_WRITE(ch_data + i, 330 pack_aux(send + i, send_bytes - i)); 331 332 /* Send the command and wait for it to complete */ 333 I915_WRITE(ch_ctl, 334 DP_AUX_CH_CTL_SEND_BUSY | 335 DP_AUX_CH_CTL_TIME_OUT_400us | 336 (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) | 337 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) | 338 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT) | 339 DP_AUX_CH_CTL_DONE | 340 DP_AUX_CH_CTL_TIME_OUT_ERROR | 341 DP_AUX_CH_CTL_RECEIVE_ERROR); 342 for (;;) { 343 status = I915_READ(ch_ctl); 344 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0) 345 break; 346 udelay(100); 347 } 348 349 /* Clear done status and any errors */ 350 I915_WRITE(ch_ctl, 351 status | 352 DP_AUX_CH_CTL_DONE | 353 DP_AUX_CH_CTL_TIME_OUT_ERROR | 354 DP_AUX_CH_CTL_RECEIVE_ERROR); 355 if (status & DP_AUX_CH_CTL_DONE) 356 break; 357 } 358 359 if ((status & DP_AUX_CH_CTL_DONE) == 0) { 360 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status); 361 return -EBUSY; 362 } 363 364 /* Check for timeout or receive error. 365 * Timeouts occur when the sink is not connected 366 */ 367 if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) { 368 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status); 369 return -EIO; 370 } 371 372 /* Timeouts occur when the device isn't connected, so they're 373 * "normal" -- don't fill the kernel log with these */ 374 if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) { 375 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status); 376 return -ETIMEDOUT; 377 } 378 379 /* Unload any bytes sent back from the other side */ 380 recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >> 381 DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT); 382 if (recv_bytes > recv_size) 383 recv_bytes = recv_size; 384 385 for (i = 0; i < recv_bytes; i += 4) 386 unpack_aux(I915_READ(ch_data + i), 387 recv + i, recv_bytes - i); 388 389 return recv_bytes; 390} 391 392/* Write data to the aux channel in native mode */ 393static int 394intel_dp_aux_native_write(struct intel_dp *intel_dp, 395 uint16_t address, uint8_t *send, int send_bytes) 396{ 397 int ret; 398 uint8_t msg[20]; 399 int msg_bytes; 400 uint8_t ack; 401 402 if (send_bytes > 16) 403 return -1; 404 msg[0] = AUX_NATIVE_WRITE << 4; 405 msg[1] = address >> 8; 406 msg[2] = address & 0xff; 407 msg[3] = send_bytes - 1; 408 memcpy(&msg[4], send, send_bytes); 409 msg_bytes = send_bytes + 4; 410 for (;;) { 411 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes, &ack, 1); 412 if (ret < 0) 413 return ret; 414 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK) 415 break; 416 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER) 417 udelay(100); 418 else 419 return -EIO; 420 } 421 return send_bytes; 422} 423 424/* Write a single byte to the aux channel in native mode */ 425static int 426intel_dp_aux_native_write_1(struct intel_dp *intel_dp, 427 uint16_t address, uint8_t byte) 428{ 429 return intel_dp_aux_native_write(intel_dp, address, &byte, 1); 430} 431 432/* read bytes from a native aux channel */ 433static int 434intel_dp_aux_native_read(struct intel_dp *intel_dp, 435 uint16_t address, uint8_t *recv, int recv_bytes) 436{ 437 uint8_t msg[4]; 438 int msg_bytes; 439 uint8_t reply[20]; 440 int reply_bytes; 441 uint8_t ack; 442 int ret; 443 444 msg[0] = AUX_NATIVE_READ << 4; 445 msg[1] = address >> 8; 446 msg[2] = address & 0xff; 447 msg[3] = recv_bytes - 1; 448 449 msg_bytes = 4; 450 reply_bytes = recv_bytes + 1; 451 452 for (;;) { 453 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes, 454 reply, reply_bytes); 455 if (ret == 0) 456 return -EPROTO; 457 if (ret < 0) 458 return ret; 459 ack = reply[0]; 460 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK) { 461 memcpy(recv, reply + 1, ret - 1); 462 return ret - 1; 463 } 464 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER) 465 udelay(100); 466 else 467 return -EIO; 468 } 469} 470 471static int 472intel_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode, 473 uint8_t write_byte, uint8_t *read_byte) 474{ 475 struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data; 476 struct intel_dp *intel_dp = container_of(adapter, 477 struct intel_dp, 478 adapter); 479 uint16_t address = algo_data->address; 480 uint8_t msg[5]; 481 uint8_t reply[2]; 482 unsigned retry; 483 int msg_bytes; 484 int reply_bytes; 485 int ret; 486 487 /* Set up the command byte */ 488 if (mode & MODE_I2C_READ) 489 msg[0] = AUX_I2C_READ << 4; 490 else 491 msg[0] = AUX_I2C_WRITE << 4; 492 493 if (!(mode & MODE_I2C_STOP)) 494 msg[0] |= AUX_I2C_MOT << 4; 495 496 msg[1] = address >> 8; 497 msg[2] = address; 498 499 switch (mode) { 500 case MODE_I2C_WRITE: 501 msg[3] = 0; 502 msg[4] = write_byte; 503 msg_bytes = 5; 504 reply_bytes = 1; 505 break; 506 case MODE_I2C_READ: 507 msg[3] = 0; 508 msg_bytes = 4; 509 reply_bytes = 2; 510 break; 511 default: 512 msg_bytes = 3; 513 reply_bytes = 1; 514 break; 515 } 516 517 for (retry = 0; retry < 5; retry++) { 518 ret = intel_dp_aux_ch(intel_dp, 519 msg, msg_bytes, 520 reply, reply_bytes); 521 if (ret < 0) { 522 DRM_DEBUG_KMS("aux_ch failed %d\n", ret); 523 return ret; 524 } 525 526 switch (reply[0] & AUX_NATIVE_REPLY_MASK) { 527 case AUX_NATIVE_REPLY_ACK: 528 /* I2C-over-AUX Reply field is only valid 529 * when paired with AUX ACK. 530 */ 531 break; 532 case AUX_NATIVE_REPLY_NACK: 533 DRM_DEBUG_KMS("aux_ch native nack\n"); 534 return -EREMOTEIO; 535 case AUX_NATIVE_REPLY_DEFER: 536 udelay(100); 537 continue; 538 default: 539 DRM_ERROR("aux_ch invalid native reply 0x%02x\n", 540 reply[0]); 541 return -EREMOTEIO; 542 } 543 544 switch (reply[0] & AUX_I2C_REPLY_MASK) { 545 case AUX_I2C_REPLY_ACK: 546 if (mode == MODE_I2C_READ) { 547 *read_byte = reply[1]; 548 } 549 return reply_bytes - 1; 550 case AUX_I2C_REPLY_NACK: 551 DRM_DEBUG_KMS("aux_i2c nack\n"); 552 return -EREMOTEIO; 553 case AUX_I2C_REPLY_DEFER: 554 DRM_DEBUG_KMS("aux_i2c defer\n"); 555 udelay(100); 556 break; 557 default: 558 DRM_ERROR("aux_i2c invalid reply 0x%02x\n", reply[0]); 559 return -EREMOTEIO; 560 } 561 } 562 563 DRM_ERROR("too many retries, giving up\n"); 564 return -EREMOTEIO; 565} 566 567static int 568intel_dp_i2c_init(struct intel_dp *intel_dp, 569 struct intel_connector *intel_connector, const char *name) 570{ 571 DRM_DEBUG_KMS("i2c_init %s\n", name); 572 intel_dp->algo.running = false; 573 intel_dp->algo.address = 0; 574 intel_dp->algo.aux_ch = intel_dp_i2c_aux_ch; 575 576 memset(&intel_dp->adapter, '\0', sizeof (intel_dp->adapter)); 577 intel_dp->adapter.owner = THIS_MODULE; 578 intel_dp->adapter.class = I2C_CLASS_DDC; 579 strncpy (intel_dp->adapter.name, name, sizeof(intel_dp->adapter.name) - 1); 580 intel_dp->adapter.name[sizeof(intel_dp->adapter.name) - 1] = '\0'; 581 intel_dp->adapter.algo_data = &intel_dp->algo; 582 intel_dp->adapter.dev.parent = &intel_connector->base.kdev; 583 584 return i2c_dp_aux_add_bus(&intel_dp->adapter); 585} 586 587static bool 588intel_dp_mode_fixup(struct drm_encoder *encoder, struct drm_display_mode *mode, 589 struct drm_display_mode *adjusted_mode) 590{ 591 struct drm_device *dev = encoder->dev; 592 struct drm_i915_private *dev_priv = dev->dev_private; 593 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 594 int lane_count, clock; 595 int max_lane_count = intel_dp_max_lane_count(intel_dp); 596 int max_clock = intel_dp_max_link_bw(intel_dp) == DP_LINK_BW_2_7 ? 1 : 0; 597 static int bws[2] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7 }; 598 599 if (is_edp(intel_dp) && dev_priv->panel_fixed_mode) { 600 intel_fixed_panel_mode(dev_priv->panel_fixed_mode, adjusted_mode); 601 intel_pch_panel_fitting(dev, DRM_MODE_SCALE_FULLSCREEN, 602 mode, adjusted_mode); 603 /* 604 * the mode->clock is used to calculate the Data&Link M/N 605 * of the pipe. For the eDP the fixed clock should be used. 606 */ 607 mode->clock = dev_priv->panel_fixed_mode->clock; 608 } 609 610 for (lane_count = 1; lane_count <= max_lane_count; lane_count <<= 1) { 611 for (clock = 0; clock <= max_clock; clock++) { 612 int link_avail = intel_dp_max_data_rate(intel_dp_link_clock(bws[clock]), lane_count); 613 614 if (intel_dp_link_required(encoder->dev, intel_dp, mode->clock) 615 <= link_avail) { 616 intel_dp->link_bw = bws[clock]; 617 intel_dp->lane_count = lane_count; 618 adjusted_mode->clock = intel_dp_link_clock(intel_dp->link_bw); 619 DRM_DEBUG_KMS("Display port link bw %02x lane " 620 "count %d clock %d\n", 621 intel_dp->link_bw, intel_dp->lane_count, 622 adjusted_mode->clock); 623 return true; 624 } 625 } 626 } 627 628 if (is_edp(intel_dp)) { 629 /* okay we failed just pick the highest */ 630 intel_dp->lane_count = max_lane_count; 631 intel_dp->link_bw = bws[max_clock]; 632 adjusted_mode->clock = intel_dp_link_clock(intel_dp->link_bw); 633 DRM_DEBUG_KMS("Force picking display port link bw %02x lane " 634 "count %d clock %d\n", 635 intel_dp->link_bw, intel_dp->lane_count, 636 adjusted_mode->clock); 637 638 return true; 639 } 640 641 return false; 642} 643 644struct intel_dp_m_n { 645 uint32_t tu; 646 uint32_t gmch_m; 647 uint32_t gmch_n; 648 uint32_t link_m; 649 uint32_t link_n; 650}; 651 652static void 653intel_reduce_ratio(uint32_t *num, uint32_t *den) 654{ 655 while (*num > 0xffffff || *den > 0xffffff) { 656 *num >>= 1; 657 *den >>= 1; 658 } 659} 660 661static void 662intel_dp_compute_m_n(int bpp, 663 int nlanes, 664 int pixel_clock, 665 int link_clock, 666 struct intel_dp_m_n *m_n) 667{ 668 m_n->tu = 64; 669 m_n->gmch_m = (pixel_clock * bpp) >> 3; 670 m_n->gmch_n = link_clock * nlanes; 671 intel_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n); 672 m_n->link_m = pixel_clock; 673 m_n->link_n = link_clock; 674 intel_reduce_ratio(&m_n->link_m, &m_n->link_n); 675} 676 677void 678intel_dp_set_m_n(struct drm_crtc *crtc, struct drm_display_mode *mode, 679 struct drm_display_mode *adjusted_mode) 680{ 681 struct drm_device *dev = crtc->dev; 682 struct drm_mode_config *mode_config = &dev->mode_config; 683 struct drm_encoder *encoder; 684 struct drm_i915_private *dev_priv = dev->dev_private; 685 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 686 int lane_count = 4, bpp = 24; 687 struct intel_dp_m_n m_n; 688 689 /* 690 * Find the lane count in the intel_encoder private 691 */ 692 list_for_each_entry(encoder, &mode_config->encoder_list, head) { 693 struct intel_dp *intel_dp; 694 695 if (encoder->crtc != crtc) 696 continue; 697 698 intel_dp = enc_to_intel_dp(encoder); 699 if (intel_dp->base.type == INTEL_OUTPUT_DISPLAYPORT) { 700 lane_count = intel_dp->lane_count; 701 break; 702 } else if (is_edp(intel_dp)) { 703 lane_count = dev_priv->edp.lanes; 704 bpp = dev_priv->edp.bpp; 705 break; 706 } 707 } 708 709 /* 710 * Compute the GMCH and Link ratios. The '3' here is 711 * the number of bytes_per_pixel post-LUT, which we always 712 * set up for 8-bits of R/G/B, or 3 bytes total. 713 */ 714 intel_dp_compute_m_n(bpp, lane_count, 715 mode->clock, adjusted_mode->clock, &m_n); 716 717 if (HAS_PCH_SPLIT(dev)) { 718 if (intel_crtc->pipe == 0) { 719 I915_WRITE(TRANSA_DATA_M1, 720 ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) | 721 m_n.gmch_m); 722 I915_WRITE(TRANSA_DATA_N1, m_n.gmch_n); 723 I915_WRITE(TRANSA_DP_LINK_M1, m_n.link_m); 724 I915_WRITE(TRANSA_DP_LINK_N1, m_n.link_n); 725 } else { 726 I915_WRITE(TRANSB_DATA_M1, 727 ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) | 728 m_n.gmch_m); 729 I915_WRITE(TRANSB_DATA_N1, m_n.gmch_n); 730 I915_WRITE(TRANSB_DP_LINK_M1, m_n.link_m); 731 I915_WRITE(TRANSB_DP_LINK_N1, m_n.link_n); 732 } 733 } else { 734 if (intel_crtc->pipe == 0) { 735 I915_WRITE(PIPEA_GMCH_DATA_M, 736 ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) | 737 m_n.gmch_m); 738 I915_WRITE(PIPEA_GMCH_DATA_N, 739 m_n.gmch_n); 740 I915_WRITE(PIPEA_DP_LINK_M, m_n.link_m); 741 I915_WRITE(PIPEA_DP_LINK_N, m_n.link_n); 742 } else { 743 I915_WRITE(PIPEB_GMCH_DATA_M, 744 ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) | 745 m_n.gmch_m); 746 I915_WRITE(PIPEB_GMCH_DATA_N, 747 m_n.gmch_n); 748 I915_WRITE(PIPEB_DP_LINK_M, m_n.link_m); 749 I915_WRITE(PIPEB_DP_LINK_N, m_n.link_n); 750 } 751 } 752} 753 754static void 755intel_dp_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode, 756 struct drm_display_mode *adjusted_mode) 757{ 758 struct drm_device *dev = encoder->dev; 759 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 760 struct drm_crtc *crtc = intel_dp->base.base.crtc; 761 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 762 763 intel_dp->DP = (DP_VOLTAGE_0_4 | 764 DP_PRE_EMPHASIS_0); 765 766 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) 767 intel_dp->DP |= DP_SYNC_HS_HIGH; 768 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) 769 intel_dp->DP |= DP_SYNC_VS_HIGH; 770 771 if (HAS_PCH_CPT(dev) && !is_edp(intel_dp)) 772 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT; 773 else 774 intel_dp->DP |= DP_LINK_TRAIN_OFF; 775 776 switch (intel_dp->lane_count) { 777 case 1: 778 intel_dp->DP |= DP_PORT_WIDTH_1; 779 break; 780 case 2: 781 intel_dp->DP |= DP_PORT_WIDTH_2; 782 break; 783 case 4: 784 intel_dp->DP |= DP_PORT_WIDTH_4; 785 break; 786 } 787 if (intel_dp->has_audio) 788 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE; 789 790 memset(intel_dp->link_configuration, 0, DP_LINK_CONFIGURATION_SIZE); 791 intel_dp->link_configuration[0] = intel_dp->link_bw; 792 intel_dp->link_configuration[1] = intel_dp->lane_count; 793 794 /* 795 * Check for DPCD version > 1.1 and enhanced framing support 796 */ 797 if (intel_dp->dpcd[0] >= 0x11 && (intel_dp->dpcd[2] & DP_ENHANCED_FRAME_CAP)) { 798 intel_dp->link_configuration[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN; 799 intel_dp->DP |= DP_ENHANCED_FRAMING; 800 } 801 802 /* CPT DP's pipe select is decided in TRANS_DP_CTL */ 803 if (intel_crtc->pipe == 1 && !HAS_PCH_CPT(dev)) 804 intel_dp->DP |= DP_PIPEB_SELECT; 805 806 if (is_edp(intel_dp) && !is_pch_edp(intel_dp)) { 807 /* don't miss out required setting for eDP */ 808 intel_dp->DP |= DP_PLL_ENABLE; 809 if (adjusted_mode->clock < 200000) 810 intel_dp->DP |= DP_PLL_FREQ_160MHZ; 811 else 812 intel_dp->DP |= DP_PLL_FREQ_270MHZ; 813 } 814} 815 816/* Returns true if the panel was already on when called */ 817static bool ironlake_edp_panel_on (struct intel_dp *intel_dp) 818{ 819 struct drm_device *dev = intel_dp->base.base.dev; 820 struct drm_i915_private *dev_priv = dev->dev_private; 821 u32 pp, idle_on_mask = PP_ON | PP_SEQUENCE_STATE_ON_IDLE; 822 823 if (I915_READ(PCH_PP_STATUS) & PP_ON) 824 return true; 825 826 pp = I915_READ(PCH_PP_CONTROL); 827 828 /* ILK workaround: disable reset around power sequence */ 829 pp &= ~PANEL_POWER_RESET; 830 I915_WRITE(PCH_PP_CONTROL, pp); 831 POSTING_READ(PCH_PP_CONTROL); 832 833 pp |= PANEL_UNLOCK_REGS | POWER_TARGET_ON; 834 I915_WRITE(PCH_PP_CONTROL, pp); 835 POSTING_READ(PCH_PP_CONTROL); 836 837 /* Ouch. We need to wait here for some panels, like Dell e6510 838 * https://bugs.freedesktop.org/show_bug.cgi?id=29278i 839 */ 840 msleep(300); 841 842 if (wait_for((I915_READ(PCH_PP_STATUS) & idle_on_mask) == idle_on_mask, 843 5000)) 844 DRM_ERROR("panel on wait timed out: 0x%08x\n", 845 I915_READ(PCH_PP_STATUS)); 846 847 pp |= PANEL_POWER_RESET; /* restore panel reset bit */ 848 I915_WRITE(PCH_PP_CONTROL, pp); 849 POSTING_READ(PCH_PP_CONTROL); 850 851 return false; 852} 853 854static void ironlake_edp_panel_off (struct drm_device *dev) 855{ 856 struct drm_i915_private *dev_priv = dev->dev_private; 857 u32 pp, idle_off_mask = PP_ON | PP_SEQUENCE_MASK | 858 PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK; 859 860 pp = I915_READ(PCH_PP_CONTROL); 861 862 /* ILK workaround: disable reset around power sequence */ 863 pp &= ~PANEL_POWER_RESET; 864 I915_WRITE(PCH_PP_CONTROL, pp); 865 POSTING_READ(PCH_PP_CONTROL); 866 867 pp &= ~POWER_TARGET_ON; 868 I915_WRITE(PCH_PP_CONTROL, pp); 869 POSTING_READ(PCH_PP_CONTROL); 870 871 if (wait_for((I915_READ(PCH_PP_STATUS) & idle_off_mask) == 0, 5000)) 872 DRM_ERROR("panel off wait timed out: 0x%08x\n", 873 I915_READ(PCH_PP_STATUS)); 874 875 pp |= PANEL_POWER_RESET; /* restore panel reset bit */ 876 I915_WRITE(PCH_PP_CONTROL, pp); 877 POSTING_READ(PCH_PP_CONTROL); 878 879 /* Ouch. We need to wait here for some panels, like Dell e6510 880 * https://bugs.freedesktop.org/show_bug.cgi?id=29278i 881 */ 882 msleep(300); 883} 884 885static void ironlake_edp_backlight_on (struct drm_device *dev) 886{ 887 struct drm_i915_private *dev_priv = dev->dev_private; 888 u32 pp; 889 890 DRM_DEBUG_KMS("\n"); 891 /* 892 * If we enable the backlight right away following a panel power 893 * on, we may see slight flicker as the panel syncs with the eDP 894 * link. So delay a bit to make sure the image is solid before 895 * allowing it to appear. 896 */ 897 msleep(300); 898 pp = I915_READ(PCH_PP_CONTROL); 899 pp |= EDP_BLC_ENABLE; 900 I915_WRITE(PCH_PP_CONTROL, pp); 901} 902 903static void ironlake_edp_backlight_off (struct drm_device *dev) 904{ 905 struct drm_i915_private *dev_priv = dev->dev_private; 906 u32 pp; 907 908 DRM_DEBUG_KMS("\n"); 909 pp = I915_READ(PCH_PP_CONTROL); 910 pp &= ~EDP_BLC_ENABLE; 911 I915_WRITE(PCH_PP_CONTROL, pp); 912} 913 914static void ironlake_edp_pll_on(struct drm_encoder *encoder) 915{ 916 struct drm_device *dev = encoder->dev; 917 struct drm_i915_private *dev_priv = dev->dev_private; 918 u32 dpa_ctl; 919 920 DRM_DEBUG_KMS("\n"); 921 dpa_ctl = I915_READ(DP_A); 922 dpa_ctl |= DP_PLL_ENABLE; 923 I915_WRITE(DP_A, dpa_ctl); 924 POSTING_READ(DP_A); 925 udelay(200); 926} 927 928static void ironlake_edp_pll_off(struct drm_encoder *encoder) 929{ 930 struct drm_device *dev = encoder->dev; 931 struct drm_i915_private *dev_priv = dev->dev_private; 932 u32 dpa_ctl; 933 934 dpa_ctl = I915_READ(DP_A); 935 dpa_ctl &= ~DP_PLL_ENABLE; 936 I915_WRITE(DP_A, dpa_ctl); 937 POSTING_READ(DP_A); 938 udelay(200); 939} 940 941static void intel_dp_prepare(struct drm_encoder *encoder) 942{ 943 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 944 struct drm_device *dev = encoder->dev; 945 946 if (is_edp(intel_dp)) { 947 ironlake_edp_backlight_off(dev); 948 ironlake_edp_panel_on(intel_dp); 949 if (!is_pch_edp(intel_dp)) 950 ironlake_edp_pll_on(encoder); 951 else 952 ironlake_edp_pll_off(encoder); 953 } 954 intel_dp_link_down(intel_dp); 955} 956 957static void intel_dp_commit(struct drm_encoder *encoder) 958{ 959 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 960 struct drm_device *dev = encoder->dev; 961 962 intel_dp_start_link_train(intel_dp); 963 964 if (is_edp(intel_dp)) 965 ironlake_edp_panel_on(intel_dp); 966 967 intel_dp_complete_link_train(intel_dp); 968 969 if (is_edp(intel_dp)) 970 ironlake_edp_backlight_on(dev); 971} 972 973static void 974intel_dp_dpms(struct drm_encoder *encoder, int mode) 975{ 976 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 977 struct drm_device *dev = encoder->dev; 978 struct drm_i915_private *dev_priv = dev->dev_private; 979 uint32_t dp_reg = I915_READ(intel_dp->output_reg); 980 981 if (mode != DRM_MODE_DPMS_ON) { 982 if (is_edp(intel_dp)) 983 ironlake_edp_backlight_off(dev); 984 intel_dp_link_down(intel_dp); 985 if (is_edp(intel_dp)) 986 ironlake_edp_panel_off(dev); 987 if (is_edp(intel_dp) && !is_pch_edp(intel_dp)) 988 ironlake_edp_pll_off(encoder); 989 } else { 990 if (is_edp(intel_dp)) 991 ironlake_edp_panel_on(intel_dp); 992 if (!(dp_reg & DP_PORT_EN)) { 993 intel_dp_start_link_train(intel_dp); 994 intel_dp_complete_link_train(intel_dp); 995 } 996 if (is_edp(intel_dp)) 997 ironlake_edp_backlight_on(dev); 998 } 999 intel_dp->dpms_mode = mode; 1000} 1001 1002/* 1003 * Fetch AUX CH registers 0x202 - 0x207 which contain 1004 * link status information 1005 */ 1006static bool 1007intel_dp_get_link_status(struct intel_dp *intel_dp) 1008{ 1009 int ret; 1010 1011 ret = intel_dp_aux_native_read(intel_dp, 1012 DP_LANE0_1_STATUS, 1013 intel_dp->link_status, DP_LINK_STATUS_SIZE); 1014 if (ret != DP_LINK_STATUS_SIZE) 1015 return false; 1016 return true; 1017} 1018 1019static uint8_t 1020intel_dp_link_status(uint8_t link_status[DP_LINK_STATUS_SIZE], 1021 int r) 1022{ 1023 return link_status[r - DP_LANE0_1_STATUS]; 1024} 1025 1026static uint8_t 1027intel_get_adjust_request_voltage(uint8_t link_status[DP_LINK_STATUS_SIZE], 1028 int lane) 1029{ 1030 int i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1); 1031 int s = ((lane & 1) ? 1032 DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT : 1033 DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT); 1034 uint8_t l = intel_dp_link_status(link_status, i); 1035 1036 return ((l >> s) & 3) << DP_TRAIN_VOLTAGE_SWING_SHIFT; 1037} 1038 1039static uint8_t 1040intel_get_adjust_request_pre_emphasis(uint8_t link_status[DP_LINK_STATUS_SIZE], 1041 int lane) 1042{ 1043 int i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1); 1044 int s = ((lane & 1) ? 1045 DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT : 1046 DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT); 1047 uint8_t l = intel_dp_link_status(link_status, i); 1048 1049 return ((l >> s) & 3) << DP_TRAIN_PRE_EMPHASIS_SHIFT; 1050} 1051 1052 1053#if 0 1054static char *voltage_names[] = { 1055 "0.4V", "0.6V", "0.8V", "1.2V" 1056}; 1057static char *pre_emph_names[] = { 1058 "0dB", "3.5dB", "6dB", "9.5dB" 1059}; 1060static char *link_train_names[] = { 1061 "pattern 1", "pattern 2", "idle", "off" 1062}; 1063#endif 1064 1065/* 1066 * These are source-specific values; current Intel hardware supports 1067 * a maximum voltage of 800mV and a maximum pre-emphasis of 6dB 1068 */ 1069#define I830_DP_VOLTAGE_MAX DP_TRAIN_VOLTAGE_SWING_800 1070 1071static uint8_t 1072intel_dp_pre_emphasis_max(uint8_t voltage_swing) 1073{ 1074 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) { 1075 case DP_TRAIN_VOLTAGE_SWING_400: 1076 return DP_TRAIN_PRE_EMPHASIS_6; 1077 case DP_TRAIN_VOLTAGE_SWING_600: 1078 return DP_TRAIN_PRE_EMPHASIS_6; 1079 case DP_TRAIN_VOLTAGE_SWING_800: 1080 return DP_TRAIN_PRE_EMPHASIS_3_5; 1081 case DP_TRAIN_VOLTAGE_SWING_1200: 1082 default: 1083 return DP_TRAIN_PRE_EMPHASIS_0; 1084 } 1085} 1086 1087static void 1088intel_get_adjust_train(struct intel_dp *intel_dp) 1089{ 1090 uint8_t v = 0; 1091 uint8_t p = 0; 1092 int lane; 1093 1094 for (lane = 0; lane < intel_dp->lane_count; lane++) { 1095 uint8_t this_v = intel_get_adjust_request_voltage(intel_dp->link_status, lane); 1096 uint8_t this_p = intel_get_adjust_request_pre_emphasis(intel_dp->link_status, lane); 1097 1098 if (this_v > v) 1099 v = this_v; 1100 if (this_p > p) 1101 p = this_p; 1102 } 1103 1104 if (v >= I830_DP_VOLTAGE_MAX) 1105 v = I830_DP_VOLTAGE_MAX | DP_TRAIN_MAX_SWING_REACHED; 1106 1107 if (p >= intel_dp_pre_emphasis_max(v)) 1108 p = intel_dp_pre_emphasis_max(v) | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED; 1109 1110 for (lane = 0; lane < 4; lane++) 1111 intel_dp->train_set[lane] = v | p; 1112} 1113 1114static uint32_t 1115intel_dp_signal_levels(uint8_t train_set, int lane_count) 1116{ 1117 uint32_t signal_levels = 0; 1118 1119 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { 1120 case DP_TRAIN_VOLTAGE_SWING_400: 1121 default: 1122 signal_levels |= DP_VOLTAGE_0_4; 1123 break; 1124 case DP_TRAIN_VOLTAGE_SWING_600: 1125 signal_levels |= DP_VOLTAGE_0_6; 1126 break; 1127 case DP_TRAIN_VOLTAGE_SWING_800: 1128 signal_levels |= DP_VOLTAGE_0_8; 1129 break; 1130 case DP_TRAIN_VOLTAGE_SWING_1200: 1131 signal_levels |= DP_VOLTAGE_1_2; 1132 break; 1133 } 1134 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) { 1135 case DP_TRAIN_PRE_EMPHASIS_0: 1136 default: 1137 signal_levels |= DP_PRE_EMPHASIS_0; 1138 break; 1139 case DP_TRAIN_PRE_EMPHASIS_3_5: 1140 signal_levels |= DP_PRE_EMPHASIS_3_5; 1141 break; 1142 case DP_TRAIN_PRE_EMPHASIS_6: 1143 signal_levels |= DP_PRE_EMPHASIS_6; 1144 break; 1145 case DP_TRAIN_PRE_EMPHASIS_9_5: 1146 signal_levels |= DP_PRE_EMPHASIS_9_5; 1147 break; 1148 } 1149 return signal_levels; 1150} 1151 1152/* Gen6's DP voltage swing and pre-emphasis control */ 1153static uint32_t 1154intel_gen6_edp_signal_levels(uint8_t train_set) 1155{ 1156 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK | 1157 DP_TRAIN_PRE_EMPHASIS_MASK); 1158 switch (signal_levels) { 1159 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0: 1160 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0: 1161 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B; 1162 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5: 1163 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B; 1164 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6: 1165 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6: 1166 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B; 1167 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5: 1168 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5: 1169 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B; 1170 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0: 1171 case DP_TRAIN_VOLTAGE_SWING_1200 | DP_TRAIN_PRE_EMPHASIS_0: 1172 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B; 1173 default: 1174 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:" 1175 "0x%x\n", signal_levels); 1176 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B; 1177 } 1178} 1179 1180static uint8_t 1181intel_get_lane_status(uint8_t link_status[DP_LINK_STATUS_SIZE], 1182 int lane) 1183{ 1184 int i = DP_LANE0_1_STATUS + (lane >> 1); 1185 int s = (lane & 1) * 4; 1186 uint8_t l = intel_dp_link_status(link_status, i); 1187 1188 return (l >> s) & 0xf; 1189} 1190 1191/* Check for clock recovery is done on all channels */ 1192static bool 1193intel_clock_recovery_ok(uint8_t link_status[DP_LINK_STATUS_SIZE], int lane_count) 1194{ 1195 int lane; 1196 uint8_t lane_status; 1197 1198 for (lane = 0; lane < lane_count; lane++) { 1199 lane_status = intel_get_lane_status(link_status, lane); 1200 if ((lane_status & DP_LANE_CR_DONE) == 0) 1201 return false; 1202 } 1203 return true; 1204} 1205 1206/* Check to see if channel eq is done on all channels */ 1207#define CHANNEL_EQ_BITS (DP_LANE_CR_DONE|\ 1208 DP_LANE_CHANNEL_EQ_DONE|\ 1209 DP_LANE_SYMBOL_LOCKED) 1210static bool 1211intel_channel_eq_ok(struct intel_dp *intel_dp) 1212{ 1213 uint8_t lane_align; 1214 uint8_t lane_status; 1215 int lane; 1216 1217 lane_align = intel_dp_link_status(intel_dp->link_status, 1218 DP_LANE_ALIGN_STATUS_UPDATED); 1219 if ((lane_align & DP_INTERLANE_ALIGN_DONE) == 0) 1220 return false; 1221 for (lane = 0; lane < intel_dp->lane_count; lane++) { 1222 lane_status = intel_get_lane_status(intel_dp->link_status, lane); 1223 if ((lane_status & CHANNEL_EQ_BITS) != CHANNEL_EQ_BITS) 1224 return false; 1225 } 1226 return true; 1227} 1228 1229static bool 1230intel_dp_set_link_train(struct intel_dp *intel_dp, 1231 uint32_t dp_reg_value, 1232 uint8_t dp_train_pat) 1233{ 1234 struct drm_device *dev = intel_dp->base.base.dev; 1235 struct drm_i915_private *dev_priv = dev->dev_private; 1236 int ret; 1237 1238 I915_WRITE(intel_dp->output_reg, dp_reg_value); 1239 POSTING_READ(intel_dp->output_reg); 1240 1241 intel_dp_aux_native_write_1(intel_dp, 1242 DP_TRAINING_PATTERN_SET, 1243 dp_train_pat); 1244 1245 ret = intel_dp_aux_native_write(intel_dp, 1246 DP_TRAINING_LANE0_SET, 1247 intel_dp->train_set, 4); 1248 if (ret != 4) 1249 return false; 1250 1251 return true; 1252} 1253 1254/* Enable corresponding port and start training pattern 1 */ 1255static void 1256intel_dp_start_link_train(struct intel_dp *intel_dp) 1257{ 1258 struct drm_device *dev = intel_dp->base.base.dev; 1259 struct drm_i915_private *dev_priv = dev->dev_private; 1260 struct intel_crtc *intel_crtc = to_intel_crtc(intel_dp->base.base.crtc); 1261 int i; 1262 uint8_t voltage; 1263 bool clock_recovery = false; 1264 int tries; 1265 u32 reg; 1266 uint32_t DP = intel_dp->DP; 1267 1268 /* Enable output, wait for it to become active */ 1269 I915_WRITE(intel_dp->output_reg, intel_dp->DP); 1270 POSTING_READ(intel_dp->output_reg); 1271 intel_wait_for_vblank(dev, intel_crtc->pipe); 1272 1273 /* Write the link configuration data */ 1274 intel_dp_aux_native_write(intel_dp, DP_LINK_BW_SET, 1275 intel_dp->link_configuration, 1276 DP_LINK_CONFIGURATION_SIZE); 1277 1278 DP |= DP_PORT_EN; 1279 if (HAS_PCH_CPT(dev) && !is_edp(intel_dp)) 1280 DP &= ~DP_LINK_TRAIN_MASK_CPT; 1281 else 1282 DP &= ~DP_LINK_TRAIN_MASK; 1283 memset(intel_dp->train_set, 0, 4); 1284 voltage = 0xff; 1285 tries = 0; 1286 clock_recovery = false; 1287 for (;;) { 1288 /* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */ 1289 uint32_t signal_levels; 1290 if (IS_GEN6(dev) && is_edp(intel_dp)) { 1291 signal_levels = intel_gen6_edp_signal_levels(intel_dp->train_set[0]); 1292 DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB) | signal_levels; 1293 } else { 1294 signal_levels = intel_dp_signal_levels(intel_dp->train_set[0], intel_dp->lane_count); 1295 DP = (DP & ~(DP_VOLTAGE_MASK|DP_PRE_EMPHASIS_MASK)) | signal_levels; 1296 } 1297 1298 if (HAS_PCH_CPT(dev) && !is_edp(intel_dp)) 1299 reg = DP | DP_LINK_TRAIN_PAT_1_CPT; 1300 else 1301 reg = DP | DP_LINK_TRAIN_PAT_1; 1302 1303 if (!intel_dp_set_link_train(intel_dp, reg, 1304 DP_TRAINING_PATTERN_1)) 1305 break; 1306 /* Set training pattern 1 */ 1307 1308 udelay(100); 1309 if (!intel_dp_get_link_status(intel_dp)) 1310 break; 1311 1312 if (intel_clock_recovery_ok(intel_dp->link_status, intel_dp->lane_count)) { 1313 clock_recovery = true; 1314 break; 1315 } 1316 1317 /* Check to see if we've tried the max voltage */ 1318 for (i = 0; i < intel_dp->lane_count; i++) 1319 if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0) 1320 break; 1321 if (i == intel_dp->lane_count) 1322 break; 1323 1324 /* Check to see if we've tried the same voltage 5 times */ 1325 if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) { 1326 ++tries; 1327 if (tries == 5) 1328 break; 1329 } else 1330 tries = 0; 1331 voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK; 1332 1333 /* Compute new intel_dp->train_set as requested by target */ 1334 intel_get_adjust_train(intel_dp); 1335 } 1336 1337 intel_dp->DP = DP; 1338} 1339 1340static void 1341intel_dp_complete_link_train(struct intel_dp *intel_dp) 1342{ 1343 struct drm_device *dev = intel_dp->base.base.dev; 1344 struct drm_i915_private *dev_priv = dev->dev_private; 1345 bool channel_eq = false; 1346 int tries, cr_tries; 1347 u32 reg; 1348 uint32_t DP = intel_dp->DP; 1349 1350 /* channel equalization */ 1351 tries = 0; 1352 cr_tries = 0; 1353 channel_eq = false; 1354 for (;;) { 1355 /* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */ 1356 uint32_t signal_levels; 1357 1358 if (cr_tries > 5) { 1359 DRM_ERROR("failed to train DP, aborting\n"); 1360 intel_dp_link_down(intel_dp); 1361 break; 1362 } 1363 1364 if (IS_GEN6(dev) && is_edp(intel_dp)) { 1365 signal_levels = intel_gen6_edp_signal_levels(intel_dp->train_set[0]); 1366 DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB) | signal_levels; 1367 } else { 1368 signal_levels = intel_dp_signal_levels(intel_dp->train_set[0], intel_dp->lane_count); 1369 DP = (DP & ~(DP_VOLTAGE_MASK|DP_PRE_EMPHASIS_MASK)) | signal_levels; 1370 } 1371 1372 if (HAS_PCH_CPT(dev) && !is_edp(intel_dp)) 1373 reg = DP | DP_LINK_TRAIN_PAT_2_CPT; 1374 else 1375 reg = DP | DP_LINK_TRAIN_PAT_2; 1376 1377 /* channel eq pattern */ 1378 if (!intel_dp_set_link_train(intel_dp, reg, 1379 DP_TRAINING_PATTERN_2)) 1380 break; 1381 1382 udelay(400); 1383 if (!intel_dp_get_link_status(intel_dp)) 1384 break; 1385 1386 /* Make sure clock is still ok */ 1387 if (!intel_clock_recovery_ok(intel_dp->link_status, intel_dp->lane_count)) { 1388 intel_dp_start_link_train(intel_dp); 1389 cr_tries++; 1390 continue; 1391 } 1392 1393 if (intel_channel_eq_ok(intel_dp)) { 1394 channel_eq = true; 1395 break; 1396 } 1397 1398 /* Try 5 times, then try clock recovery if that fails */ 1399 if (tries > 5) { 1400 intel_dp_link_down(intel_dp); 1401 intel_dp_start_link_train(intel_dp); 1402 tries = 0; 1403 cr_tries++; 1404 continue; 1405 } 1406 1407 /* Compute new intel_dp->train_set as requested by target */ 1408 intel_get_adjust_train(intel_dp); 1409 ++tries; 1410 } 1411 1412 if (HAS_PCH_CPT(dev) && !is_edp(intel_dp)) 1413 reg = DP | DP_LINK_TRAIN_OFF_CPT; 1414 else 1415 reg = DP | DP_LINK_TRAIN_OFF; 1416 1417 I915_WRITE(intel_dp->output_reg, reg); 1418 POSTING_READ(intel_dp->output_reg); 1419 intel_dp_aux_native_write_1(intel_dp, 1420 DP_TRAINING_PATTERN_SET, DP_TRAINING_PATTERN_DISABLE); 1421} 1422 1423static void 1424intel_dp_link_down(struct intel_dp *intel_dp) 1425{ 1426 struct drm_device *dev = intel_dp->base.base.dev; 1427 struct drm_i915_private *dev_priv = dev->dev_private; 1428 uint32_t DP = intel_dp->DP; 1429 1430 if ((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0) 1431 return; 1432 1433 DRM_DEBUG_KMS("\n"); 1434 1435 if (is_edp(intel_dp)) { 1436 DP &= ~DP_PLL_ENABLE; 1437 I915_WRITE(intel_dp->output_reg, DP); 1438 POSTING_READ(intel_dp->output_reg); 1439 udelay(100); 1440 } 1441 1442 if (HAS_PCH_CPT(dev) && !is_edp(intel_dp)) { 1443 DP &= ~DP_LINK_TRAIN_MASK_CPT; 1444 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT); 1445 } else { 1446 DP &= ~DP_LINK_TRAIN_MASK; 1447 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE); 1448 } 1449 POSTING_READ(intel_dp->output_reg); 1450 1451 msleep(17); 1452 1453 if (is_edp(intel_dp)) 1454 DP |= DP_LINK_TRAIN_OFF; 1455 1456 if (!HAS_PCH_CPT(dev) && 1457 I915_READ(intel_dp->output_reg) & DP_PIPEB_SELECT) { 1458 struct intel_crtc *intel_crtc = to_intel_crtc(intel_dp->base.base.crtc); 1459 /* Hardware workaround: leaving our transcoder select 1460 * set to transcoder B while it's off will prevent the 1461 * corresponding HDMI output on transcoder A. 1462 * 1463 * Combine this with another hardware workaround: 1464 * transcoder select bit can only be cleared while the 1465 * port is enabled. 1466 */ 1467 DP &= ~DP_PIPEB_SELECT; 1468 I915_WRITE(intel_dp->output_reg, DP); 1469 1470 /* Changes to enable or select take place the vblank 1471 * after being written. 1472 */ 1473 intel_wait_for_vblank(dev, intel_crtc->pipe); 1474 } 1475 1476 I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN); 1477 POSTING_READ(intel_dp->output_reg); 1478} 1479 1480/* 1481 * According to DP spec 1482 * 5.1.2: 1483 * 1. Read DPCD 1484 * 2. Configure link according to Receiver Capabilities 1485 * 3. Use Link Training from 2.5.3.3 and 3.5.1.3 1486 * 4. Check link status on receipt of hot-plug interrupt 1487 */ 1488 1489static void 1490intel_dp_check_link_status(struct intel_dp *intel_dp) 1491{ 1492 if (!intel_dp->base.base.crtc) 1493 return; 1494 1495 if (!intel_dp_get_link_status(intel_dp)) { 1496 intel_dp_link_down(intel_dp); 1497 return; 1498 } 1499 1500 if (!intel_channel_eq_ok(intel_dp)) { 1501 intel_dp_start_link_train(intel_dp); 1502 intel_dp_complete_link_train(intel_dp); 1503 } 1504} 1505 1506static enum drm_connector_status 1507ironlake_dp_detect(struct intel_dp *intel_dp) 1508{ 1509 enum drm_connector_status status; 1510 1511 /* Can't disconnect eDP */ 1512 if (is_edp(intel_dp)) 1513 return connector_status_connected; 1514 1515 status = connector_status_disconnected; 1516 if (intel_dp_aux_native_read(intel_dp, 1517 0x000, intel_dp->dpcd, 1518 sizeof (intel_dp->dpcd)) 1519 == sizeof(intel_dp->dpcd)) { 1520 if (intel_dp->dpcd[0] != 0) 1521 status = connector_status_connected; 1522 } 1523 DRM_DEBUG_KMS("DPCD: %hx%hx%hx%hx\n", intel_dp->dpcd[0], 1524 intel_dp->dpcd[1], intel_dp->dpcd[2], intel_dp->dpcd[3]); 1525 return status; 1526} 1527 1528static enum drm_connector_status 1529g4x_dp_detect(struct intel_dp *intel_dp) 1530{ 1531 struct drm_device *dev = intel_dp->base.base.dev; 1532 struct drm_i915_private *dev_priv = dev->dev_private; 1533 enum drm_connector_status status; 1534 uint32_t temp, bit; 1535 1536 switch (intel_dp->output_reg) { 1537 case DP_B: 1538 bit = DPB_HOTPLUG_INT_STATUS; 1539 break; 1540 case DP_C: 1541 bit = DPC_HOTPLUG_INT_STATUS; 1542 break; 1543 case DP_D: 1544 bit = DPD_HOTPLUG_INT_STATUS; 1545 break; 1546 default: 1547 return connector_status_unknown; 1548 } 1549 1550 temp = I915_READ(PORT_HOTPLUG_STAT); 1551 1552 if ((temp & bit) == 0) 1553 return connector_status_disconnected; 1554 1555 status = connector_status_disconnected; 1556 if (intel_dp_aux_native_read(intel_dp, 0x000, intel_dp->dpcd, 1557 sizeof (intel_dp->dpcd)) == sizeof (intel_dp->dpcd)) 1558 { 1559 if (intel_dp->dpcd[0] != 0) 1560 status = connector_status_connected; 1561 } 1562 1563 return status; 1564} 1565 1566/** 1567 * Uses CRT_HOTPLUG_EN and CRT_HOTPLUG_STAT to detect DP connection. 1568 * 1569 * \return true if DP port is connected. 1570 * \return false if DP port is disconnected. 1571 */ 1572static enum drm_connector_status 1573intel_dp_detect(struct drm_connector *connector, bool force) 1574{ 1575 struct intel_dp *intel_dp = intel_attached_dp(connector); 1576 struct drm_device *dev = intel_dp->base.base.dev; 1577 enum drm_connector_status status; 1578 struct edid *edid = NULL; 1579 1580 intel_dp->has_audio = false; 1581 1582 if (HAS_PCH_SPLIT(dev)) 1583 status = ironlake_dp_detect(intel_dp); 1584 else 1585 status = g4x_dp_detect(intel_dp); 1586 if (status != connector_status_connected) 1587 return status; 1588 1589 if (intel_dp->force_audio) { 1590 intel_dp->has_audio = intel_dp->force_audio > 0; 1591 } else { 1592 edid = drm_get_edid(connector, &intel_dp->adapter); 1593 if (edid) { 1594 intel_dp->has_audio = drm_detect_monitor_audio(edid); 1595 connector->display_info.raw_edid = NULL; 1596 kfree(edid); 1597 } 1598 } 1599 1600 return connector_status_connected; 1601} 1602 1603static int intel_dp_get_modes(struct drm_connector *connector) 1604{ 1605 struct intel_dp *intel_dp = intel_attached_dp(connector); 1606 struct drm_device *dev = intel_dp->base.base.dev; 1607 struct drm_i915_private *dev_priv = dev->dev_private; 1608 int ret; 1609 1610 /* We should parse the EDID data and find out if it has an audio sink 1611 */ 1612 1613 ret = intel_ddc_get_modes(connector, &intel_dp->adapter); 1614 if (ret) { 1615 if (is_edp(intel_dp) && !dev_priv->panel_fixed_mode) { 1616 struct drm_display_mode *newmode; 1617 list_for_each_entry(newmode, &connector->probed_modes, 1618 head) { 1619 if (newmode->type & DRM_MODE_TYPE_PREFERRED) { 1620 dev_priv->panel_fixed_mode = 1621 drm_mode_duplicate(dev, newmode); 1622 break; 1623 } 1624 } 1625 } 1626 1627 return ret; 1628 } 1629 1630 /* if eDP has no EDID, try to use fixed panel mode from VBT */ 1631 if (is_edp(intel_dp)) { 1632 if (dev_priv->panel_fixed_mode != NULL) { 1633 struct drm_display_mode *mode; 1634 mode = drm_mode_duplicate(dev, dev_priv->panel_fixed_mode); 1635 drm_mode_probed_add(connector, mode); 1636 return 1; 1637 } 1638 } 1639 return 0; 1640} 1641 1642static int 1643intel_dp_set_property(struct drm_connector *connector, 1644 struct drm_property *property, 1645 uint64_t val) 1646{ 1647 struct intel_dp *intel_dp = intel_attached_dp(connector); 1648 int ret; 1649 1650 ret = drm_connector_property_set_value(connector, property, val); 1651 if (ret) 1652 return ret; 1653 1654 if (property == intel_dp->force_audio_property) { 1655 if (val == intel_dp->force_audio) 1656 return 0; 1657 1658 intel_dp->force_audio = val; 1659 1660 if (val > 0 && intel_dp->has_audio) 1661 return 0; 1662 if (val < 0 && !intel_dp->has_audio) 1663 return 0; 1664 1665 intel_dp->has_audio = val > 0; 1666 goto done; 1667 } 1668 1669 return -EINVAL; 1670 1671done: 1672 if (intel_dp->base.base.crtc) { 1673 struct drm_crtc *crtc = intel_dp->base.base.crtc; 1674 drm_crtc_helper_set_mode(crtc, &crtc->mode, 1675 crtc->x, crtc->y, 1676 crtc->fb); 1677 } 1678 1679 return 0; 1680} 1681 1682static void 1683intel_dp_destroy (struct drm_connector *connector) 1684{ 1685 drm_sysfs_connector_remove(connector); 1686 drm_connector_cleanup(connector); 1687 kfree(connector); 1688} 1689 1690static void intel_dp_encoder_destroy(struct drm_encoder *encoder) 1691{ 1692 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 1693 1694 i2c_del_adapter(&intel_dp->adapter); 1695 drm_encoder_cleanup(encoder); 1696 kfree(intel_dp); 1697} 1698 1699static const struct drm_encoder_helper_funcs intel_dp_helper_funcs = { 1700 .dpms = intel_dp_dpms, 1701 .mode_fixup = intel_dp_mode_fixup, 1702 .prepare = intel_dp_prepare, 1703 .mode_set = intel_dp_mode_set, 1704 .commit = intel_dp_commit, 1705}; 1706 1707static const struct drm_connector_funcs intel_dp_connector_funcs = { 1708 .dpms = drm_helper_connector_dpms, 1709 .detect = intel_dp_detect, 1710 .fill_modes = drm_helper_probe_single_connector_modes, 1711 .set_property = intel_dp_set_property, 1712 .destroy = intel_dp_destroy, 1713}; 1714 1715static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = { 1716 .get_modes = intel_dp_get_modes, 1717 .mode_valid = intel_dp_mode_valid, 1718 .best_encoder = intel_best_encoder, 1719}; 1720 1721static const struct drm_encoder_funcs intel_dp_enc_funcs = { 1722 .destroy = intel_dp_encoder_destroy, 1723}; 1724 1725static void 1726intel_dp_hot_plug(struct intel_encoder *intel_encoder) 1727{ 1728 struct intel_dp *intel_dp = container_of(intel_encoder, struct intel_dp, base); 1729 1730 if (intel_dp->dpms_mode == DRM_MODE_DPMS_ON) 1731 intel_dp_check_link_status(intel_dp); 1732} 1733 1734/* Return which DP Port should be selected for Transcoder DP control */ 1735int 1736intel_trans_dp_port_sel (struct drm_crtc *crtc) 1737{ 1738 struct drm_device *dev = crtc->dev; 1739 struct drm_mode_config *mode_config = &dev->mode_config; 1740 struct drm_encoder *encoder; 1741 1742 list_for_each_entry(encoder, &mode_config->encoder_list, head) { 1743 struct intel_dp *intel_dp; 1744 1745 if (encoder->crtc != crtc) 1746 continue; 1747 1748 intel_dp = enc_to_intel_dp(encoder); 1749 if (intel_dp->base.type == INTEL_OUTPUT_DISPLAYPORT) 1750 return intel_dp->output_reg; 1751 } 1752 1753 return -1; 1754} 1755 1756/* check the VBT to see whether the eDP is on DP-D port */ 1757bool intel_dpd_is_edp(struct drm_device *dev) 1758{ 1759 struct drm_i915_private *dev_priv = dev->dev_private; 1760 struct child_device_config *p_child; 1761 int i; 1762 1763 if (!dev_priv->child_dev_num) 1764 return false; 1765 1766 for (i = 0; i < dev_priv->child_dev_num; i++) { 1767 p_child = dev_priv->child_dev + i; 1768 1769 if (p_child->dvo_port == PORT_IDPD && 1770 p_child->device_type == DEVICE_TYPE_eDP) 1771 return true; 1772 } 1773 return false; 1774} 1775 1776static void 1777intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector) 1778{ 1779 struct drm_device *dev = connector->dev; 1780 1781 intel_dp->force_audio_property = 1782 drm_property_create(dev, DRM_MODE_PROP_RANGE, "force_audio", 2); 1783 if (intel_dp->force_audio_property) { 1784 intel_dp->force_audio_property->values[0] = -1; 1785 intel_dp->force_audio_property->values[1] = 1; 1786 drm_connector_attach_property(connector, intel_dp->force_audio_property, 0); 1787 } 1788} 1789 1790void 1791intel_dp_init(struct drm_device *dev, int output_reg) 1792{ 1793 struct drm_i915_private *dev_priv = dev->dev_private; 1794 struct drm_connector *connector; 1795 struct intel_dp *intel_dp; 1796 struct intel_encoder *intel_encoder; 1797 struct intel_connector *intel_connector; 1798 const char *name = NULL; 1799 int type; 1800 1801 intel_dp = kzalloc(sizeof(struct intel_dp), GFP_KERNEL); 1802 if (!intel_dp) 1803 return; 1804 1805 intel_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL); 1806 if (!intel_connector) { 1807 kfree(intel_dp); 1808 return; 1809 } 1810 intel_encoder = &intel_dp->base; 1811 1812 if (HAS_PCH_SPLIT(dev) && output_reg == PCH_DP_D) 1813 if (intel_dpd_is_edp(dev)) 1814 intel_dp->is_pch_edp = true; 1815 1816 if (output_reg == DP_A || is_pch_edp(intel_dp)) { 1817 type = DRM_MODE_CONNECTOR_eDP; 1818 intel_encoder->type = INTEL_OUTPUT_EDP; 1819 } else { 1820 type = DRM_MODE_CONNECTOR_DisplayPort; 1821 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT; 1822 } 1823 1824 connector = &intel_connector->base; 1825 drm_connector_init(dev, connector, &intel_dp_connector_funcs, type); 1826 drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs); 1827 1828 connector->polled = DRM_CONNECTOR_POLL_HPD; 1829 1830 if (output_reg == DP_B || output_reg == PCH_DP_B) 1831 intel_encoder->clone_mask = (1 << INTEL_DP_B_CLONE_BIT); 1832 else if (output_reg == DP_C || output_reg == PCH_DP_C) 1833 intel_encoder->clone_mask = (1 << INTEL_DP_C_CLONE_BIT); 1834 else if (output_reg == DP_D || output_reg == PCH_DP_D) 1835 intel_encoder->clone_mask = (1 << INTEL_DP_D_CLONE_BIT); 1836 1837 if (is_edp(intel_dp)) 1838 intel_encoder->clone_mask = (1 << INTEL_EDP_CLONE_BIT); 1839 1840 intel_encoder->crtc_mask = (1 << 0) | (1 << 1); 1841 connector->interlace_allowed = true; 1842 connector->doublescan_allowed = 0; 1843 1844 intel_dp->output_reg = output_reg; 1845 intel_dp->has_audio = false; 1846 intel_dp->dpms_mode = DRM_MODE_DPMS_ON; 1847 1848 drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs, 1849 DRM_MODE_ENCODER_TMDS); 1850 drm_encoder_helper_add(&intel_encoder->base, &intel_dp_helper_funcs); 1851 1852 intel_connector_attach_encoder(intel_connector, intel_encoder); 1853 drm_sysfs_connector_add(connector); 1854 1855 /* Set up the DDC bus. */ 1856 switch (output_reg) { 1857 case DP_A: 1858 name = "DPDDC-A"; 1859 break; 1860 case DP_B: 1861 case PCH_DP_B: 1862 dev_priv->hotplug_supported_mask |= 1863 HDMIB_HOTPLUG_INT_STATUS; 1864 name = "DPDDC-B"; 1865 break; 1866 case DP_C: 1867 case PCH_DP_C: 1868 dev_priv->hotplug_supported_mask |= 1869 HDMIC_HOTPLUG_INT_STATUS; 1870 name = "DPDDC-C"; 1871 break; 1872 case DP_D: 1873 case PCH_DP_D: 1874 dev_priv->hotplug_supported_mask |= 1875 HDMID_HOTPLUG_INT_STATUS; 1876 name = "DPDDC-D"; 1877 break; 1878 } 1879 1880 intel_dp_i2c_init(intel_dp, intel_connector, name); 1881 1882 /* Cache some DPCD data in the eDP case */ 1883 if (is_edp(intel_dp)) { 1884 int ret; 1885 bool was_on; 1886 1887 was_on = ironlake_edp_panel_on(intel_dp); 1888 ret = intel_dp_aux_native_read(intel_dp, DP_DPCD_REV, 1889 intel_dp->dpcd, 1890 sizeof(intel_dp->dpcd)); 1891 if (ret == sizeof(intel_dp->dpcd)) { 1892 if (intel_dp->dpcd[0] >= 0x11) 1893 dev_priv->no_aux_handshake = intel_dp->dpcd[3] & 1894 DP_NO_AUX_HANDSHAKE_LINK_TRAINING; 1895 } else { 1896 DRM_ERROR("failed to retrieve link info\n"); 1897 } 1898 if (!was_on) 1899 ironlake_edp_panel_off(dev); 1900 } 1901 1902 intel_encoder->hot_plug = intel_dp_hot_plug; 1903 1904 if (is_edp(intel_dp)) { 1905 /* initialize panel mode from VBT if available for eDP */ 1906 if (dev_priv->lfp_lvds_vbt_mode) { 1907 dev_priv->panel_fixed_mode = 1908 drm_mode_duplicate(dev, dev_priv->lfp_lvds_vbt_mode); 1909 if (dev_priv->panel_fixed_mode) { 1910 dev_priv->panel_fixed_mode->type |= 1911 DRM_MODE_TYPE_PREFERRED; 1912 } 1913 } 1914 } 1915 1916 intel_dp_add_properties(intel_dp, connector); 1917 1918 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written 1919 * 0xd. Failure to do so will result in spurious interrupts being 1920 * generated on the port when a cable is not attached. 1921 */ 1922 if (IS_G4X(dev) && !IS_GM45(dev)) { 1923 u32 temp = I915_READ(PEG_BAND_GAP_DATA); 1924 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd); 1925 } 1926} 1927