intel_dp.c revision 4f9db5b51cb1dfa9b6d5060dc4316e82d53e1b6c
1/* 2 * Copyright © 2008 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 * Authors: 24 * Keith Packard <keithp@keithp.com> 25 * 26 */ 27 28#include <linux/i2c.h> 29#include <linux/slab.h> 30#include <linux/export.h> 31#include <drm/drmP.h> 32#include <drm/drm_crtc.h> 33#include <drm/drm_crtc_helper.h> 34#include <drm/drm_edid.h> 35#include "intel_drv.h" 36#include <drm/i915_drm.h> 37#include "i915_drv.h" 38 39#define DP_LINK_CHECK_TIMEOUT (10 * 1000) 40 41struct dp_link_dpll { 42 int link_bw; 43 struct dpll dpll; 44}; 45 46static const struct dp_link_dpll gen4_dpll[] = { 47 { DP_LINK_BW_1_62, 48 { .p1 = 2, .p2 = 10, .n = 2, .m1 = 23, .m2 = 8 } }, 49 { DP_LINK_BW_2_7, 50 { .p1 = 1, .p2 = 10, .n = 1, .m1 = 14, .m2 = 2 } } 51}; 52 53static const struct dp_link_dpll pch_dpll[] = { 54 { DP_LINK_BW_1_62, 55 { .p1 = 2, .p2 = 10, .n = 1, .m1 = 12, .m2 = 9 } }, 56 { DP_LINK_BW_2_7, 57 { .p1 = 1, .p2 = 10, .n = 2, .m1 = 14, .m2 = 8 } } 58}; 59 60static const struct dp_link_dpll vlv_dpll[] = { 61 { DP_LINK_BW_1_62, 62 { .p1 = 3, .p2 = 2, .n = 5, .m1 = 3, .m2 = 81 } }, 63 { DP_LINK_BW_2_7, 64 { .p1 = 2, .p2 = 2, .n = 1, .m1 = 2, .m2 = 27 } } 65}; 66 67/** 68 * is_edp - is the given port attached to an eDP panel (either CPU or PCH) 69 * @intel_dp: DP struct 70 * 71 * If a CPU or PCH DP output is attached to an eDP panel, this function 72 * will return true, and false otherwise. 73 */ 74static bool is_edp(struct intel_dp *intel_dp) 75{ 76 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 77 78 return intel_dig_port->base.type == INTEL_OUTPUT_EDP; 79} 80 81static struct drm_device *intel_dp_to_dev(struct intel_dp *intel_dp) 82{ 83 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 84 85 return intel_dig_port->base.base.dev; 86} 87 88static struct intel_dp *intel_attached_dp(struct drm_connector *connector) 89{ 90 return enc_to_intel_dp(&intel_attached_encoder(connector)->base); 91} 92 93static void intel_dp_link_down(struct intel_dp *intel_dp); 94static bool _edp_panel_vdd_on(struct intel_dp *intel_dp); 95static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync); 96 97static int 98intel_dp_max_link_bw(struct intel_dp *intel_dp) 99{ 100 int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE]; 101 struct drm_device *dev = intel_dp->attached_connector->base.dev; 102 103 switch (max_link_bw) { 104 case DP_LINK_BW_1_62: 105 case DP_LINK_BW_2_7: 106 break; 107 case DP_LINK_BW_5_4: /* 1.2 capable displays may advertise higher bw */ 108 if ((IS_HASWELL(dev) || INTEL_INFO(dev)->gen >= 8) && 109 intel_dp->dpcd[DP_DPCD_REV] >= 0x12) 110 max_link_bw = DP_LINK_BW_5_4; 111 else 112 max_link_bw = DP_LINK_BW_2_7; 113 break; 114 default: 115 WARN(1, "invalid max DP link bw val %x, using 1.62Gbps\n", 116 max_link_bw); 117 max_link_bw = DP_LINK_BW_1_62; 118 break; 119 } 120 return max_link_bw; 121} 122 123/* 124 * The units on the numbers in the next two are... bizarre. Examples will 125 * make it clearer; this one parallels an example in the eDP spec. 126 * 127 * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as: 128 * 129 * 270000 * 1 * 8 / 10 == 216000 130 * 131 * The actual data capacity of that configuration is 2.16Gbit/s, so the 132 * units are decakilobits. ->clock in a drm_display_mode is in kilohertz - 133 * or equivalently, kilopixels per second - so for 1680x1050R it'd be 134 * 119000. At 18bpp that's 2142000 kilobits per second. 135 * 136 * Thus the strange-looking division by 10 in intel_dp_link_required, to 137 * get the result in decakilobits instead of kilobits. 138 */ 139 140static int 141intel_dp_link_required(int pixel_clock, int bpp) 142{ 143 return (pixel_clock * bpp + 9) / 10; 144} 145 146static int 147intel_dp_max_data_rate(int max_link_clock, int max_lanes) 148{ 149 return (max_link_clock * max_lanes * 8) / 10; 150} 151 152static enum drm_mode_status 153intel_dp_mode_valid(struct drm_connector *connector, 154 struct drm_display_mode *mode) 155{ 156 struct intel_dp *intel_dp = intel_attached_dp(connector); 157 struct intel_connector *intel_connector = to_intel_connector(connector); 158 struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode; 159 int target_clock = mode->clock; 160 int max_rate, mode_rate, max_lanes, max_link_clock; 161 162 if (is_edp(intel_dp) && fixed_mode) { 163 if (mode->hdisplay > fixed_mode->hdisplay) 164 return MODE_PANEL; 165 166 if (mode->vdisplay > fixed_mode->vdisplay) 167 return MODE_PANEL; 168 169 target_clock = fixed_mode->clock; 170 } 171 172 max_link_clock = drm_dp_bw_code_to_link_rate(intel_dp_max_link_bw(intel_dp)); 173 max_lanes = drm_dp_max_lane_count(intel_dp->dpcd); 174 175 max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes); 176 mode_rate = intel_dp_link_required(target_clock, 18); 177 178 if (mode_rate > max_rate) 179 return MODE_CLOCK_HIGH; 180 181 if (mode->clock < 10000) 182 return MODE_CLOCK_LOW; 183 184 if (mode->flags & DRM_MODE_FLAG_DBLCLK) 185 return MODE_H_ILLEGAL; 186 187 return MODE_OK; 188} 189 190static uint32_t 191pack_aux(uint8_t *src, int src_bytes) 192{ 193 int i; 194 uint32_t v = 0; 195 196 if (src_bytes > 4) 197 src_bytes = 4; 198 for (i = 0; i < src_bytes; i++) 199 v |= ((uint32_t) src[i]) << ((3-i) * 8); 200 return v; 201} 202 203static void 204unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes) 205{ 206 int i; 207 if (dst_bytes > 4) 208 dst_bytes = 4; 209 for (i = 0; i < dst_bytes; i++) 210 dst[i] = src >> ((3-i) * 8); 211} 212 213/* hrawclock is 1/4 the FSB frequency */ 214static int 215intel_hrawclk(struct drm_device *dev) 216{ 217 struct drm_i915_private *dev_priv = dev->dev_private; 218 uint32_t clkcfg; 219 220 /* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */ 221 if (IS_VALLEYVIEW(dev)) 222 return 200; 223 224 clkcfg = I915_READ(CLKCFG); 225 switch (clkcfg & CLKCFG_FSB_MASK) { 226 case CLKCFG_FSB_400: 227 return 100; 228 case CLKCFG_FSB_533: 229 return 133; 230 case CLKCFG_FSB_667: 231 return 166; 232 case CLKCFG_FSB_800: 233 return 200; 234 case CLKCFG_FSB_1067: 235 return 266; 236 case CLKCFG_FSB_1333: 237 return 333; 238 /* these two are just a guess; one of them might be right */ 239 case CLKCFG_FSB_1600: 240 case CLKCFG_FSB_1600_ALT: 241 return 400; 242 default: 243 return 133; 244 } 245} 246 247static void 248intel_dp_init_panel_power_sequencer(struct drm_device *dev, 249 struct intel_dp *intel_dp, 250 struct edp_power_seq *out); 251static void 252intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev, 253 struct intel_dp *intel_dp, 254 struct edp_power_seq *out); 255 256static enum pipe 257vlv_power_sequencer_pipe(struct intel_dp *intel_dp) 258{ 259 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 260 struct drm_crtc *crtc = intel_dig_port->base.base.crtc; 261 struct drm_device *dev = intel_dig_port->base.base.dev; 262 struct drm_i915_private *dev_priv = dev->dev_private; 263 enum port port = intel_dig_port->port; 264 enum pipe pipe; 265 266 /* modeset should have pipe */ 267 if (crtc) 268 return to_intel_crtc(crtc)->pipe; 269 270 /* init time, try to find a pipe with this port selected */ 271 for (pipe = PIPE_A; pipe <= PIPE_B; pipe++) { 272 u32 port_sel = I915_READ(VLV_PIPE_PP_ON_DELAYS(pipe)) & 273 PANEL_PORT_SELECT_MASK; 274 if (port_sel == PANEL_PORT_SELECT_DPB_VLV && port == PORT_B) 275 return pipe; 276 if (port_sel == PANEL_PORT_SELECT_DPC_VLV && port == PORT_C) 277 return pipe; 278 } 279 280 /* shrug */ 281 return PIPE_A; 282} 283 284static u32 _pp_ctrl_reg(struct intel_dp *intel_dp) 285{ 286 struct drm_device *dev = intel_dp_to_dev(intel_dp); 287 288 if (HAS_PCH_SPLIT(dev)) 289 return PCH_PP_CONTROL; 290 else 291 return VLV_PIPE_PP_CONTROL(vlv_power_sequencer_pipe(intel_dp)); 292} 293 294static u32 _pp_stat_reg(struct intel_dp *intel_dp) 295{ 296 struct drm_device *dev = intel_dp_to_dev(intel_dp); 297 298 if (HAS_PCH_SPLIT(dev)) 299 return PCH_PP_STATUS; 300 else 301 return VLV_PIPE_PP_STATUS(vlv_power_sequencer_pipe(intel_dp)); 302} 303 304static bool edp_have_panel_power(struct intel_dp *intel_dp) 305{ 306 struct drm_device *dev = intel_dp_to_dev(intel_dp); 307 struct drm_i915_private *dev_priv = dev->dev_private; 308 309 return (I915_READ(_pp_stat_reg(intel_dp)) & PP_ON) != 0; 310} 311 312static bool edp_have_panel_vdd(struct intel_dp *intel_dp) 313{ 314 struct drm_device *dev = intel_dp_to_dev(intel_dp); 315 struct drm_i915_private *dev_priv = dev->dev_private; 316 317 return !dev_priv->pm.suspended && 318 (I915_READ(_pp_ctrl_reg(intel_dp)) & EDP_FORCE_VDD) != 0; 319} 320 321static void 322intel_dp_check_edp(struct intel_dp *intel_dp) 323{ 324 struct drm_device *dev = intel_dp_to_dev(intel_dp); 325 struct drm_i915_private *dev_priv = dev->dev_private; 326 327 if (!is_edp(intel_dp)) 328 return; 329 330 if (!edp_have_panel_power(intel_dp) && !edp_have_panel_vdd(intel_dp)) { 331 WARN(1, "eDP powered off while attempting aux channel communication.\n"); 332 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n", 333 I915_READ(_pp_stat_reg(intel_dp)), 334 I915_READ(_pp_ctrl_reg(intel_dp))); 335 } 336} 337 338static uint32_t 339intel_dp_aux_wait_done(struct intel_dp *intel_dp, bool has_aux_irq) 340{ 341 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 342 struct drm_device *dev = intel_dig_port->base.base.dev; 343 struct drm_i915_private *dev_priv = dev->dev_private; 344 uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg; 345 uint32_t status; 346 bool done; 347 348#define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0) 349 if (has_aux_irq) 350 done = wait_event_timeout(dev_priv->gmbus_wait_queue, C, 351 msecs_to_jiffies_timeout(10)); 352 else 353 done = wait_for_atomic(C, 10) == 0; 354 if (!done) 355 DRM_ERROR("dp aux hw did not signal timeout (has irq: %i)!\n", 356 has_aux_irq); 357#undef C 358 359 return status; 360} 361 362static uint32_t i9xx_get_aux_clock_divider(struct intel_dp *intel_dp, int index) 363{ 364 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 365 struct drm_device *dev = intel_dig_port->base.base.dev; 366 367 /* 368 * The clock divider is based off the hrawclk, and would like to run at 369 * 2MHz. So, take the hrawclk value and divide by 2 and use that 370 */ 371 return index ? 0 : intel_hrawclk(dev) / 2; 372} 373 374static uint32_t ilk_get_aux_clock_divider(struct intel_dp *intel_dp, int index) 375{ 376 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 377 struct drm_device *dev = intel_dig_port->base.base.dev; 378 379 if (index) 380 return 0; 381 382 if (intel_dig_port->port == PORT_A) { 383 if (IS_GEN6(dev) || IS_GEN7(dev)) 384 return 200; /* SNB & IVB eDP input clock at 400Mhz */ 385 else 386 return 225; /* eDP input clock at 450Mhz */ 387 } else { 388 return DIV_ROUND_UP(intel_pch_rawclk(dev), 2); 389 } 390} 391 392static uint32_t hsw_get_aux_clock_divider(struct intel_dp *intel_dp, int index) 393{ 394 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 395 struct drm_device *dev = intel_dig_port->base.base.dev; 396 struct drm_i915_private *dev_priv = dev->dev_private; 397 398 if (intel_dig_port->port == PORT_A) { 399 if (index) 400 return 0; 401 return DIV_ROUND_CLOSEST(intel_ddi_get_cdclk_freq(dev_priv), 2000); 402 } else if (dev_priv->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE) { 403 /* Workaround for non-ULT HSW */ 404 switch (index) { 405 case 0: return 63; 406 case 1: return 72; 407 default: return 0; 408 } 409 } else { 410 return index ? 0 : DIV_ROUND_UP(intel_pch_rawclk(dev), 2); 411 } 412} 413 414static uint32_t vlv_get_aux_clock_divider(struct intel_dp *intel_dp, int index) 415{ 416 return index ? 0 : 100; 417} 418 419static uint32_t i9xx_get_aux_send_ctl(struct intel_dp *intel_dp, 420 bool has_aux_irq, 421 int send_bytes, 422 uint32_t aux_clock_divider) 423{ 424 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 425 struct drm_device *dev = intel_dig_port->base.base.dev; 426 uint32_t precharge, timeout; 427 428 if (IS_GEN6(dev)) 429 precharge = 3; 430 else 431 precharge = 5; 432 433 if (IS_BROADWELL(dev) && intel_dp->aux_ch_ctl_reg == DPA_AUX_CH_CTL) 434 timeout = DP_AUX_CH_CTL_TIME_OUT_600us; 435 else 436 timeout = DP_AUX_CH_CTL_TIME_OUT_400us; 437 438 return DP_AUX_CH_CTL_SEND_BUSY | 439 DP_AUX_CH_CTL_DONE | 440 (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) | 441 DP_AUX_CH_CTL_TIME_OUT_ERROR | 442 timeout | 443 DP_AUX_CH_CTL_RECEIVE_ERROR | 444 (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) | 445 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) | 446 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT); 447} 448 449static int 450intel_dp_aux_ch(struct intel_dp *intel_dp, 451 uint8_t *send, int send_bytes, 452 uint8_t *recv, int recv_size) 453{ 454 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 455 struct drm_device *dev = intel_dig_port->base.base.dev; 456 struct drm_i915_private *dev_priv = dev->dev_private; 457 uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg; 458 uint32_t ch_data = ch_ctl + 4; 459 uint32_t aux_clock_divider; 460 int i, ret, recv_bytes; 461 uint32_t status; 462 int try, clock = 0; 463 bool has_aux_irq = HAS_AUX_IRQ(dev); 464 bool vdd; 465 466 vdd = _edp_panel_vdd_on(intel_dp); 467 468 /* dp aux is extremely sensitive to irq latency, hence request the 469 * lowest possible wakeup latency and so prevent the cpu from going into 470 * deep sleep states. 471 */ 472 pm_qos_update_request(&dev_priv->pm_qos, 0); 473 474 intel_dp_check_edp(intel_dp); 475 476 intel_aux_display_runtime_get(dev_priv); 477 478 /* Try to wait for any previous AUX channel activity */ 479 for (try = 0; try < 3; try++) { 480 status = I915_READ_NOTRACE(ch_ctl); 481 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0) 482 break; 483 msleep(1); 484 } 485 486 if (try == 3) { 487 WARN(1, "dp_aux_ch not started status 0x%08x\n", 488 I915_READ(ch_ctl)); 489 ret = -EBUSY; 490 goto out; 491 } 492 493 /* Only 5 data registers! */ 494 if (WARN_ON(send_bytes > 20 || recv_size > 20)) { 495 ret = -E2BIG; 496 goto out; 497 } 498 499 while ((aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, clock++))) { 500 u32 send_ctl = intel_dp->get_aux_send_ctl(intel_dp, 501 has_aux_irq, 502 send_bytes, 503 aux_clock_divider); 504 505 /* Must try at least 3 times according to DP spec */ 506 for (try = 0; try < 5; try++) { 507 /* Load the send data into the aux channel data registers */ 508 for (i = 0; i < send_bytes; i += 4) 509 I915_WRITE(ch_data + i, 510 pack_aux(send + i, send_bytes - i)); 511 512 /* Send the command and wait for it to complete */ 513 I915_WRITE(ch_ctl, send_ctl); 514 515 status = intel_dp_aux_wait_done(intel_dp, has_aux_irq); 516 517 /* Clear done status and any errors */ 518 I915_WRITE(ch_ctl, 519 status | 520 DP_AUX_CH_CTL_DONE | 521 DP_AUX_CH_CTL_TIME_OUT_ERROR | 522 DP_AUX_CH_CTL_RECEIVE_ERROR); 523 524 if (status & (DP_AUX_CH_CTL_TIME_OUT_ERROR | 525 DP_AUX_CH_CTL_RECEIVE_ERROR)) 526 continue; 527 if (status & DP_AUX_CH_CTL_DONE) 528 break; 529 } 530 if (status & DP_AUX_CH_CTL_DONE) 531 break; 532 } 533 534 if ((status & DP_AUX_CH_CTL_DONE) == 0) { 535 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status); 536 ret = -EBUSY; 537 goto out; 538 } 539 540 /* Check for timeout or receive error. 541 * Timeouts occur when the sink is not connected 542 */ 543 if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) { 544 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status); 545 ret = -EIO; 546 goto out; 547 } 548 549 /* Timeouts occur when the device isn't connected, so they're 550 * "normal" -- don't fill the kernel log with these */ 551 if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) { 552 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status); 553 ret = -ETIMEDOUT; 554 goto out; 555 } 556 557 /* Unload any bytes sent back from the other side */ 558 recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >> 559 DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT); 560 if (recv_bytes > recv_size) 561 recv_bytes = recv_size; 562 563 for (i = 0; i < recv_bytes; i += 4) 564 unpack_aux(I915_READ(ch_data + i), 565 recv + i, recv_bytes - i); 566 567 ret = recv_bytes; 568out: 569 pm_qos_update_request(&dev_priv->pm_qos, PM_QOS_DEFAULT_VALUE); 570 intel_aux_display_runtime_put(dev_priv); 571 572 if (vdd) 573 edp_panel_vdd_off(intel_dp, false); 574 575 return ret; 576} 577 578#define HEADER_SIZE 4 579static ssize_t 580intel_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg) 581{ 582 struct intel_dp *intel_dp = container_of(aux, struct intel_dp, aux); 583 uint8_t txbuf[20], rxbuf[20]; 584 size_t txsize, rxsize; 585 int ret; 586 587 txbuf[0] = msg->request << 4; 588 txbuf[1] = msg->address >> 8; 589 txbuf[2] = msg->address & 0xff; 590 txbuf[3] = msg->size - 1; 591 592 switch (msg->request & ~DP_AUX_I2C_MOT) { 593 case DP_AUX_NATIVE_WRITE: 594 case DP_AUX_I2C_WRITE: 595 txsize = HEADER_SIZE + msg->size; 596 rxsize = 1; 597 598 if (WARN_ON(txsize > 20)) 599 return -E2BIG; 600 601 memcpy(txbuf + HEADER_SIZE, msg->buffer, msg->size); 602 603 ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize); 604 if (ret > 0) { 605 msg->reply = rxbuf[0] >> 4; 606 607 /* Return payload size. */ 608 ret = msg->size; 609 } 610 break; 611 612 case DP_AUX_NATIVE_READ: 613 case DP_AUX_I2C_READ: 614 txsize = HEADER_SIZE; 615 rxsize = msg->size + 1; 616 617 if (WARN_ON(rxsize > 20)) 618 return -E2BIG; 619 620 ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize); 621 if (ret > 0) { 622 msg->reply = rxbuf[0] >> 4; 623 /* 624 * Assume happy day, and copy the data. The caller is 625 * expected to check msg->reply before touching it. 626 * 627 * Return payload size. 628 */ 629 ret--; 630 memcpy(msg->buffer, rxbuf + 1, ret); 631 } 632 break; 633 634 default: 635 ret = -EINVAL; 636 break; 637 } 638 639 return ret; 640} 641 642static void 643intel_dp_aux_init(struct intel_dp *intel_dp, struct intel_connector *connector) 644{ 645 struct drm_device *dev = intel_dp_to_dev(intel_dp); 646 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 647 enum port port = intel_dig_port->port; 648 const char *name = NULL; 649 int ret; 650 651 switch (port) { 652 case PORT_A: 653 intel_dp->aux_ch_ctl_reg = DPA_AUX_CH_CTL; 654 name = "DPDDC-A"; 655 break; 656 case PORT_B: 657 intel_dp->aux_ch_ctl_reg = PCH_DPB_AUX_CH_CTL; 658 name = "DPDDC-B"; 659 break; 660 case PORT_C: 661 intel_dp->aux_ch_ctl_reg = PCH_DPC_AUX_CH_CTL; 662 name = "DPDDC-C"; 663 break; 664 case PORT_D: 665 intel_dp->aux_ch_ctl_reg = PCH_DPD_AUX_CH_CTL; 666 name = "DPDDC-D"; 667 break; 668 default: 669 BUG(); 670 } 671 672 if (!HAS_DDI(dev)) 673 intel_dp->aux_ch_ctl_reg = intel_dp->output_reg + 0x10; 674 675 intel_dp->aux.name = name; 676 intel_dp->aux.dev = dev->dev; 677 intel_dp->aux.transfer = intel_dp_aux_transfer; 678 679 DRM_DEBUG_KMS("registering %s bus for %s\n", name, 680 connector->base.kdev->kobj.name); 681 682 ret = drm_dp_aux_register_i2c_bus(&intel_dp->aux); 683 if (ret < 0) { 684 DRM_ERROR("drm_dp_aux_register_i2c_bus() for %s failed (%d)\n", 685 name, ret); 686 return; 687 } 688 689 ret = sysfs_create_link(&connector->base.kdev->kobj, 690 &intel_dp->aux.ddc.dev.kobj, 691 intel_dp->aux.ddc.dev.kobj.name); 692 if (ret < 0) { 693 DRM_ERROR("sysfs_create_link() for %s failed (%d)\n", name, ret); 694 drm_dp_aux_unregister_i2c_bus(&intel_dp->aux); 695 } 696} 697 698static void 699intel_dp_connector_unregister(struct intel_connector *intel_connector) 700{ 701 struct intel_dp *intel_dp = intel_attached_dp(&intel_connector->base); 702 703 sysfs_remove_link(&intel_connector->base.kdev->kobj, 704 intel_dp->aux.ddc.dev.kobj.name); 705 intel_connector_unregister(intel_connector); 706} 707 708static void 709intel_dp_set_clock(struct intel_encoder *encoder, 710 struct intel_crtc_config *pipe_config, int link_bw) 711{ 712 struct drm_device *dev = encoder->base.dev; 713 const struct dp_link_dpll *divisor = NULL; 714 int i, count = 0; 715 716 if (IS_G4X(dev)) { 717 divisor = gen4_dpll; 718 count = ARRAY_SIZE(gen4_dpll); 719 } else if (IS_HASWELL(dev)) { 720 /* Haswell has special-purpose DP DDI clocks. */ 721 } else if (HAS_PCH_SPLIT(dev)) { 722 divisor = pch_dpll; 723 count = ARRAY_SIZE(pch_dpll); 724 } else if (IS_VALLEYVIEW(dev)) { 725 divisor = vlv_dpll; 726 count = ARRAY_SIZE(vlv_dpll); 727 } 728 729 if (divisor && count) { 730 for (i = 0; i < count; i++) { 731 if (link_bw == divisor[i].link_bw) { 732 pipe_config->dpll = divisor[i].dpll; 733 pipe_config->clock_set = true; 734 break; 735 } 736 } 737 } 738} 739 740bool 741intel_dp_compute_config(struct intel_encoder *encoder, 742 struct intel_crtc_config *pipe_config) 743{ 744 struct drm_device *dev = encoder->base.dev; 745 struct drm_i915_private *dev_priv = dev->dev_private; 746 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode; 747 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); 748 enum port port = dp_to_dig_port(intel_dp)->port; 749 struct intel_crtc *intel_crtc = encoder->new_crtc; 750 struct intel_connector *intel_connector = intel_dp->attached_connector; 751 int lane_count, clock; 752 int max_lane_count = drm_dp_max_lane_count(intel_dp->dpcd); 753 /* Conveniently, the link BW constants become indices with a shift...*/ 754 int max_clock = intel_dp_max_link_bw(intel_dp) >> 3; 755 int bpp, mode_rate; 756 static int bws[] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7, DP_LINK_BW_5_4 }; 757 int link_avail, link_clock; 758 759 if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev) && port != PORT_A) 760 pipe_config->has_pch_encoder = true; 761 762 pipe_config->has_dp_encoder = true; 763 764 if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) { 765 intel_fixed_panel_mode(intel_connector->panel.fixed_mode, 766 adjusted_mode); 767 if (!HAS_PCH_SPLIT(dev)) 768 intel_gmch_panel_fitting(intel_crtc, pipe_config, 769 intel_connector->panel.fitting_mode); 770 else 771 intel_pch_panel_fitting(intel_crtc, pipe_config, 772 intel_connector->panel.fitting_mode); 773 } 774 775 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK) 776 return false; 777 778 DRM_DEBUG_KMS("DP link computation with max lane count %i " 779 "max bw %02x pixel clock %iKHz\n", 780 max_lane_count, bws[max_clock], 781 adjusted_mode->crtc_clock); 782 783 /* Walk through all bpp values. Luckily they're all nicely spaced with 2 784 * bpc in between. */ 785 bpp = pipe_config->pipe_bpp; 786 if (is_edp(intel_dp) && dev_priv->vbt.edp_bpp && 787 dev_priv->vbt.edp_bpp < bpp) { 788 DRM_DEBUG_KMS("clamping bpp for eDP panel to BIOS-provided %i\n", 789 dev_priv->vbt.edp_bpp); 790 bpp = dev_priv->vbt.edp_bpp; 791 } 792 793 for (; bpp >= 6*3; bpp -= 2*3) { 794 mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock, 795 bpp); 796 797 for (lane_count = 1; lane_count <= max_lane_count; lane_count <<= 1) { 798 for (clock = 0; clock <= max_clock; clock++) { 799 link_clock = drm_dp_bw_code_to_link_rate(bws[clock]); 800 link_avail = intel_dp_max_data_rate(link_clock, 801 lane_count); 802 803 if (mode_rate <= link_avail) { 804 goto found; 805 } 806 } 807 } 808 } 809 810 return false; 811 812found: 813 if (intel_dp->color_range_auto) { 814 /* 815 * See: 816 * CEA-861-E - 5.1 Default Encoding Parameters 817 * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry 818 */ 819 if (bpp != 18 && drm_match_cea_mode(adjusted_mode) > 1) 820 intel_dp->color_range = DP_COLOR_RANGE_16_235; 821 else 822 intel_dp->color_range = 0; 823 } 824 825 if (intel_dp->color_range) 826 pipe_config->limited_color_range = true; 827 828 intel_dp->link_bw = bws[clock]; 829 intel_dp->lane_count = lane_count; 830 pipe_config->pipe_bpp = bpp; 831 pipe_config->port_clock = drm_dp_bw_code_to_link_rate(intel_dp->link_bw); 832 833 DRM_DEBUG_KMS("DP link bw %02x lane count %d clock %d bpp %d\n", 834 intel_dp->link_bw, intel_dp->lane_count, 835 pipe_config->port_clock, bpp); 836 DRM_DEBUG_KMS("DP link bw required %i available %i\n", 837 mode_rate, link_avail); 838 839 intel_link_compute_m_n(bpp, lane_count, 840 adjusted_mode->crtc_clock, 841 pipe_config->port_clock, 842 &pipe_config->dp_m_n); 843 844 intel_dp_set_clock(encoder, pipe_config, intel_dp->link_bw); 845 846 return true; 847} 848 849static void ironlake_set_pll_cpu_edp(struct intel_dp *intel_dp) 850{ 851 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 852 struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc); 853 struct drm_device *dev = crtc->base.dev; 854 struct drm_i915_private *dev_priv = dev->dev_private; 855 u32 dpa_ctl; 856 857 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", crtc->config.port_clock); 858 dpa_ctl = I915_READ(DP_A); 859 dpa_ctl &= ~DP_PLL_FREQ_MASK; 860 861 if (crtc->config.port_clock == 162000) { 862 /* For a long time we've carried around a ILK-DevA w/a for the 863 * 160MHz clock. If we're really unlucky, it's still required. 864 */ 865 DRM_DEBUG_KMS("160MHz cpu eDP clock, might need ilk devA w/a\n"); 866 dpa_ctl |= DP_PLL_FREQ_160MHZ; 867 intel_dp->DP |= DP_PLL_FREQ_160MHZ; 868 } else { 869 dpa_ctl |= DP_PLL_FREQ_270MHZ; 870 intel_dp->DP |= DP_PLL_FREQ_270MHZ; 871 } 872 873 I915_WRITE(DP_A, dpa_ctl); 874 875 POSTING_READ(DP_A); 876 udelay(500); 877} 878 879static void intel_dp_mode_set(struct intel_encoder *encoder) 880{ 881 struct drm_device *dev = encoder->base.dev; 882 struct drm_i915_private *dev_priv = dev->dev_private; 883 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); 884 enum port port = dp_to_dig_port(intel_dp)->port; 885 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); 886 struct drm_display_mode *adjusted_mode = &crtc->config.adjusted_mode; 887 888 /* 889 * There are four kinds of DP registers: 890 * 891 * IBX PCH 892 * SNB CPU 893 * IVB CPU 894 * CPT PCH 895 * 896 * IBX PCH and CPU are the same for almost everything, 897 * except that the CPU DP PLL is configured in this 898 * register 899 * 900 * CPT PCH is quite different, having many bits moved 901 * to the TRANS_DP_CTL register instead. That 902 * configuration happens (oddly) in ironlake_pch_enable 903 */ 904 905 /* Preserve the BIOS-computed detected bit. This is 906 * supposed to be read-only. 907 */ 908 intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED; 909 910 /* Handle DP bits in common between all three register formats */ 911 intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0; 912 intel_dp->DP |= DP_PORT_WIDTH(intel_dp->lane_count); 913 914 if (intel_dp->has_audio) { 915 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n", 916 pipe_name(crtc->pipe)); 917 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE; 918 intel_write_eld(&encoder->base, adjusted_mode); 919 } 920 921 /* Split out the IBX/CPU vs CPT settings */ 922 923 if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) { 924 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) 925 intel_dp->DP |= DP_SYNC_HS_HIGH; 926 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) 927 intel_dp->DP |= DP_SYNC_VS_HIGH; 928 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT; 929 930 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd)) 931 intel_dp->DP |= DP_ENHANCED_FRAMING; 932 933 intel_dp->DP |= crtc->pipe << 29; 934 } else if (!HAS_PCH_CPT(dev) || port == PORT_A) { 935 if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev)) 936 intel_dp->DP |= intel_dp->color_range; 937 938 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) 939 intel_dp->DP |= DP_SYNC_HS_HIGH; 940 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) 941 intel_dp->DP |= DP_SYNC_VS_HIGH; 942 intel_dp->DP |= DP_LINK_TRAIN_OFF; 943 944 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd)) 945 intel_dp->DP |= DP_ENHANCED_FRAMING; 946 947 if (crtc->pipe == 1) 948 intel_dp->DP |= DP_PIPEB_SELECT; 949 } else { 950 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT; 951 } 952 953 if (port == PORT_A && !IS_VALLEYVIEW(dev)) 954 ironlake_set_pll_cpu_edp(intel_dp); 955} 956 957#define IDLE_ON_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK) 958#define IDLE_ON_VALUE (PP_ON | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE) 959 960#define IDLE_OFF_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | 0) 961#define IDLE_OFF_VALUE (0 | PP_SEQUENCE_NONE | 0 | 0) 962 963#define IDLE_CYCLE_MASK (PP_ON | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK) 964#define IDLE_CYCLE_VALUE (0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE) 965 966static void wait_panel_status(struct intel_dp *intel_dp, 967 u32 mask, 968 u32 value) 969{ 970 struct drm_device *dev = intel_dp_to_dev(intel_dp); 971 struct drm_i915_private *dev_priv = dev->dev_private; 972 u32 pp_stat_reg, pp_ctrl_reg; 973 974 pp_stat_reg = _pp_stat_reg(intel_dp); 975 pp_ctrl_reg = _pp_ctrl_reg(intel_dp); 976 977 DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n", 978 mask, value, 979 I915_READ(pp_stat_reg), 980 I915_READ(pp_ctrl_reg)); 981 982 if (_wait_for((I915_READ(pp_stat_reg) & mask) == value, 5000, 10)) { 983 DRM_ERROR("Panel status timeout: status %08x control %08x\n", 984 I915_READ(pp_stat_reg), 985 I915_READ(pp_ctrl_reg)); 986 } 987 988 DRM_DEBUG_KMS("Wait complete\n"); 989} 990 991static void wait_panel_on(struct intel_dp *intel_dp) 992{ 993 DRM_DEBUG_KMS("Wait for panel power on\n"); 994 wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE); 995} 996 997static void wait_panel_off(struct intel_dp *intel_dp) 998{ 999 DRM_DEBUG_KMS("Wait for panel power off time\n"); 1000 wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE); 1001} 1002 1003static void wait_panel_power_cycle(struct intel_dp *intel_dp) 1004{ 1005 DRM_DEBUG_KMS("Wait for panel power cycle\n"); 1006 1007 /* When we disable the VDD override bit last we have to do the manual 1008 * wait. */ 1009 wait_remaining_ms_from_jiffies(intel_dp->last_power_cycle, 1010 intel_dp->panel_power_cycle_delay); 1011 1012 wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE); 1013} 1014 1015static void wait_backlight_on(struct intel_dp *intel_dp) 1016{ 1017 wait_remaining_ms_from_jiffies(intel_dp->last_power_on, 1018 intel_dp->backlight_on_delay); 1019} 1020 1021static void edp_wait_backlight_off(struct intel_dp *intel_dp) 1022{ 1023 wait_remaining_ms_from_jiffies(intel_dp->last_backlight_off, 1024 intel_dp->backlight_off_delay); 1025} 1026 1027/* Read the current pp_control value, unlocking the register if it 1028 * is locked 1029 */ 1030 1031static u32 ironlake_get_pp_control(struct intel_dp *intel_dp) 1032{ 1033 struct drm_device *dev = intel_dp_to_dev(intel_dp); 1034 struct drm_i915_private *dev_priv = dev->dev_private; 1035 u32 control; 1036 1037 control = I915_READ(_pp_ctrl_reg(intel_dp)); 1038 control &= ~PANEL_UNLOCK_MASK; 1039 control |= PANEL_UNLOCK_REGS; 1040 return control; 1041} 1042 1043static bool _edp_panel_vdd_on(struct intel_dp *intel_dp) 1044{ 1045 struct drm_device *dev = intel_dp_to_dev(intel_dp); 1046 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 1047 struct intel_encoder *intel_encoder = &intel_dig_port->base; 1048 struct drm_i915_private *dev_priv = dev->dev_private; 1049 enum intel_display_power_domain power_domain; 1050 u32 pp; 1051 u32 pp_stat_reg, pp_ctrl_reg; 1052 bool need_to_disable = !intel_dp->want_panel_vdd; 1053 1054 if (!is_edp(intel_dp)) 1055 return false; 1056 1057 intel_dp->want_panel_vdd = true; 1058 1059 if (edp_have_panel_vdd(intel_dp)) 1060 return need_to_disable; 1061 1062 power_domain = intel_display_port_power_domain(intel_encoder); 1063 intel_display_power_get(dev_priv, power_domain); 1064 1065 DRM_DEBUG_KMS("Turning eDP VDD on\n"); 1066 1067 if (!edp_have_panel_power(intel_dp)) 1068 wait_panel_power_cycle(intel_dp); 1069 1070 pp = ironlake_get_pp_control(intel_dp); 1071 pp |= EDP_FORCE_VDD; 1072 1073 pp_stat_reg = _pp_stat_reg(intel_dp); 1074 pp_ctrl_reg = _pp_ctrl_reg(intel_dp); 1075 1076 I915_WRITE(pp_ctrl_reg, pp); 1077 POSTING_READ(pp_ctrl_reg); 1078 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n", 1079 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg)); 1080 /* 1081 * If the panel wasn't on, delay before accessing aux channel 1082 */ 1083 if (!edp_have_panel_power(intel_dp)) { 1084 DRM_DEBUG_KMS("eDP was not running\n"); 1085 msleep(intel_dp->panel_power_up_delay); 1086 } 1087 1088 return need_to_disable; 1089} 1090 1091void intel_edp_panel_vdd_on(struct intel_dp *intel_dp) 1092{ 1093 if (is_edp(intel_dp)) { 1094 bool vdd = _edp_panel_vdd_on(intel_dp); 1095 1096 WARN(!vdd, "eDP VDD already requested on\n"); 1097 } 1098} 1099 1100static void edp_panel_vdd_off_sync(struct intel_dp *intel_dp) 1101{ 1102 struct drm_device *dev = intel_dp_to_dev(intel_dp); 1103 struct drm_i915_private *dev_priv = dev->dev_private; 1104 u32 pp; 1105 u32 pp_stat_reg, pp_ctrl_reg; 1106 1107 WARN_ON(!mutex_is_locked(&dev->mode_config.mutex)); 1108 1109 if (!intel_dp->want_panel_vdd && edp_have_panel_vdd(intel_dp)) { 1110 struct intel_digital_port *intel_dig_port = 1111 dp_to_dig_port(intel_dp); 1112 struct intel_encoder *intel_encoder = &intel_dig_port->base; 1113 enum intel_display_power_domain power_domain; 1114 1115 DRM_DEBUG_KMS("Turning eDP VDD off\n"); 1116 1117 pp = ironlake_get_pp_control(intel_dp); 1118 pp &= ~EDP_FORCE_VDD; 1119 1120 pp_ctrl_reg = _pp_ctrl_reg(intel_dp); 1121 pp_stat_reg = _pp_stat_reg(intel_dp); 1122 1123 I915_WRITE(pp_ctrl_reg, pp); 1124 POSTING_READ(pp_ctrl_reg); 1125 1126 /* Make sure sequencer is idle before allowing subsequent activity */ 1127 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n", 1128 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg)); 1129 1130 if ((pp & POWER_TARGET_ON) == 0) 1131 intel_dp->last_power_cycle = jiffies; 1132 1133 power_domain = intel_display_port_power_domain(intel_encoder); 1134 intel_display_power_put(dev_priv, power_domain); 1135 } 1136} 1137 1138static void edp_panel_vdd_work(struct work_struct *__work) 1139{ 1140 struct intel_dp *intel_dp = container_of(to_delayed_work(__work), 1141 struct intel_dp, panel_vdd_work); 1142 struct drm_device *dev = intel_dp_to_dev(intel_dp); 1143 1144 mutex_lock(&dev->mode_config.mutex); 1145 edp_panel_vdd_off_sync(intel_dp); 1146 mutex_unlock(&dev->mode_config.mutex); 1147} 1148 1149static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync) 1150{ 1151 if (!is_edp(intel_dp)) 1152 return; 1153 1154 WARN(!intel_dp->want_panel_vdd, "eDP VDD not forced on"); 1155 1156 intel_dp->want_panel_vdd = false; 1157 1158 if (sync) { 1159 edp_panel_vdd_off_sync(intel_dp); 1160 } else { 1161 /* 1162 * Queue the timer to fire a long 1163 * time from now (relative to the power down delay) 1164 * to keep the panel power up across a sequence of operations 1165 */ 1166 schedule_delayed_work(&intel_dp->panel_vdd_work, 1167 msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5)); 1168 } 1169} 1170 1171void intel_edp_panel_on(struct intel_dp *intel_dp) 1172{ 1173 struct drm_device *dev = intel_dp_to_dev(intel_dp); 1174 struct drm_i915_private *dev_priv = dev->dev_private; 1175 u32 pp; 1176 u32 pp_ctrl_reg; 1177 1178 if (!is_edp(intel_dp)) 1179 return; 1180 1181 DRM_DEBUG_KMS("Turn eDP power on\n"); 1182 1183 if (edp_have_panel_power(intel_dp)) { 1184 DRM_DEBUG_KMS("eDP power already on\n"); 1185 return; 1186 } 1187 1188 wait_panel_power_cycle(intel_dp); 1189 1190 pp_ctrl_reg = _pp_ctrl_reg(intel_dp); 1191 pp = ironlake_get_pp_control(intel_dp); 1192 if (IS_GEN5(dev)) { 1193 /* ILK workaround: disable reset around power sequence */ 1194 pp &= ~PANEL_POWER_RESET; 1195 I915_WRITE(pp_ctrl_reg, pp); 1196 POSTING_READ(pp_ctrl_reg); 1197 } 1198 1199 pp |= POWER_TARGET_ON; 1200 if (!IS_GEN5(dev)) 1201 pp |= PANEL_POWER_RESET; 1202 1203 I915_WRITE(pp_ctrl_reg, pp); 1204 POSTING_READ(pp_ctrl_reg); 1205 1206 wait_panel_on(intel_dp); 1207 intel_dp->last_power_on = jiffies; 1208 1209 if (IS_GEN5(dev)) { 1210 pp |= PANEL_POWER_RESET; /* restore panel reset bit */ 1211 I915_WRITE(pp_ctrl_reg, pp); 1212 POSTING_READ(pp_ctrl_reg); 1213 } 1214} 1215 1216void intel_edp_panel_off(struct intel_dp *intel_dp) 1217{ 1218 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 1219 struct intel_encoder *intel_encoder = &intel_dig_port->base; 1220 struct drm_device *dev = intel_dp_to_dev(intel_dp); 1221 struct drm_i915_private *dev_priv = dev->dev_private; 1222 enum intel_display_power_domain power_domain; 1223 u32 pp; 1224 u32 pp_ctrl_reg; 1225 1226 if (!is_edp(intel_dp)) 1227 return; 1228 1229 DRM_DEBUG_KMS("Turn eDP power off\n"); 1230 1231 edp_wait_backlight_off(intel_dp); 1232 1233 WARN(!intel_dp->want_panel_vdd, "Need VDD to turn off panel\n"); 1234 1235 pp = ironlake_get_pp_control(intel_dp); 1236 /* We need to switch off panel power _and_ force vdd, for otherwise some 1237 * panels get very unhappy and cease to work. */ 1238 pp &= ~(POWER_TARGET_ON | PANEL_POWER_RESET | EDP_FORCE_VDD | 1239 EDP_BLC_ENABLE); 1240 1241 pp_ctrl_reg = _pp_ctrl_reg(intel_dp); 1242 1243 intel_dp->want_panel_vdd = false; 1244 1245 I915_WRITE(pp_ctrl_reg, pp); 1246 POSTING_READ(pp_ctrl_reg); 1247 1248 intel_dp->last_power_cycle = jiffies; 1249 wait_panel_off(intel_dp); 1250 1251 /* We got a reference when we enabled the VDD. */ 1252 power_domain = intel_display_port_power_domain(intel_encoder); 1253 intel_display_power_put(dev_priv, power_domain); 1254} 1255 1256void intel_edp_backlight_on(struct intel_dp *intel_dp) 1257{ 1258 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 1259 struct drm_device *dev = intel_dig_port->base.base.dev; 1260 struct drm_i915_private *dev_priv = dev->dev_private; 1261 u32 pp; 1262 u32 pp_ctrl_reg; 1263 1264 if (!is_edp(intel_dp)) 1265 return; 1266 1267 DRM_DEBUG_KMS("\n"); 1268 /* 1269 * If we enable the backlight right away following a panel power 1270 * on, we may see slight flicker as the panel syncs with the eDP 1271 * link. So delay a bit to make sure the image is solid before 1272 * allowing it to appear. 1273 */ 1274 wait_backlight_on(intel_dp); 1275 pp = ironlake_get_pp_control(intel_dp); 1276 pp |= EDP_BLC_ENABLE; 1277 1278 pp_ctrl_reg = _pp_ctrl_reg(intel_dp); 1279 1280 I915_WRITE(pp_ctrl_reg, pp); 1281 POSTING_READ(pp_ctrl_reg); 1282 1283 intel_panel_enable_backlight(intel_dp->attached_connector); 1284} 1285 1286void intel_edp_backlight_off(struct intel_dp *intel_dp) 1287{ 1288 struct drm_device *dev = intel_dp_to_dev(intel_dp); 1289 struct drm_i915_private *dev_priv = dev->dev_private; 1290 u32 pp; 1291 u32 pp_ctrl_reg; 1292 1293 if (!is_edp(intel_dp)) 1294 return; 1295 1296 intel_panel_disable_backlight(intel_dp->attached_connector); 1297 1298 DRM_DEBUG_KMS("\n"); 1299 pp = ironlake_get_pp_control(intel_dp); 1300 pp &= ~EDP_BLC_ENABLE; 1301 1302 pp_ctrl_reg = _pp_ctrl_reg(intel_dp); 1303 1304 I915_WRITE(pp_ctrl_reg, pp); 1305 POSTING_READ(pp_ctrl_reg); 1306 intel_dp->last_backlight_off = jiffies; 1307} 1308 1309static void ironlake_edp_pll_on(struct intel_dp *intel_dp) 1310{ 1311 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 1312 struct drm_crtc *crtc = intel_dig_port->base.base.crtc; 1313 struct drm_device *dev = crtc->dev; 1314 struct drm_i915_private *dev_priv = dev->dev_private; 1315 u32 dpa_ctl; 1316 1317 assert_pipe_disabled(dev_priv, 1318 to_intel_crtc(crtc)->pipe); 1319 1320 DRM_DEBUG_KMS("\n"); 1321 dpa_ctl = I915_READ(DP_A); 1322 WARN(dpa_ctl & DP_PLL_ENABLE, "dp pll on, should be off\n"); 1323 WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n"); 1324 1325 /* We don't adjust intel_dp->DP while tearing down the link, to 1326 * facilitate link retraining (e.g. after hotplug). Hence clear all 1327 * enable bits here to ensure that we don't enable too much. */ 1328 intel_dp->DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE); 1329 intel_dp->DP |= DP_PLL_ENABLE; 1330 I915_WRITE(DP_A, intel_dp->DP); 1331 POSTING_READ(DP_A); 1332 udelay(200); 1333} 1334 1335static void ironlake_edp_pll_off(struct intel_dp *intel_dp) 1336{ 1337 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 1338 struct drm_crtc *crtc = intel_dig_port->base.base.crtc; 1339 struct drm_device *dev = crtc->dev; 1340 struct drm_i915_private *dev_priv = dev->dev_private; 1341 u32 dpa_ctl; 1342 1343 assert_pipe_disabled(dev_priv, 1344 to_intel_crtc(crtc)->pipe); 1345 1346 dpa_ctl = I915_READ(DP_A); 1347 WARN((dpa_ctl & DP_PLL_ENABLE) == 0, 1348 "dp pll off, should be on\n"); 1349 WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n"); 1350 1351 /* We can't rely on the value tracked for the DP register in 1352 * intel_dp->DP because link_down must not change that (otherwise link 1353 * re-training will fail. */ 1354 dpa_ctl &= ~DP_PLL_ENABLE; 1355 I915_WRITE(DP_A, dpa_ctl); 1356 POSTING_READ(DP_A); 1357 udelay(200); 1358} 1359 1360/* If the sink supports it, try to set the power state appropriately */ 1361void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode) 1362{ 1363 int ret, i; 1364 1365 /* Should have a valid DPCD by this point */ 1366 if (intel_dp->dpcd[DP_DPCD_REV] < 0x11) 1367 return; 1368 1369 if (mode != DRM_MODE_DPMS_ON) { 1370 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER, 1371 DP_SET_POWER_D3); 1372 if (ret != 1) 1373 DRM_DEBUG_DRIVER("failed to write sink power state\n"); 1374 } else { 1375 /* 1376 * When turning on, we need to retry for 1ms to give the sink 1377 * time to wake up. 1378 */ 1379 for (i = 0; i < 3; i++) { 1380 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER, 1381 DP_SET_POWER_D0); 1382 if (ret == 1) 1383 break; 1384 msleep(1); 1385 } 1386 } 1387} 1388 1389static bool intel_dp_get_hw_state(struct intel_encoder *encoder, 1390 enum pipe *pipe) 1391{ 1392 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); 1393 enum port port = dp_to_dig_port(intel_dp)->port; 1394 struct drm_device *dev = encoder->base.dev; 1395 struct drm_i915_private *dev_priv = dev->dev_private; 1396 enum intel_display_power_domain power_domain; 1397 u32 tmp; 1398 1399 power_domain = intel_display_port_power_domain(encoder); 1400 if (!intel_display_power_enabled(dev_priv, power_domain)) 1401 return false; 1402 1403 tmp = I915_READ(intel_dp->output_reg); 1404 1405 if (!(tmp & DP_PORT_EN)) 1406 return false; 1407 1408 if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) { 1409 *pipe = PORT_TO_PIPE_CPT(tmp); 1410 } else if (!HAS_PCH_CPT(dev) || port == PORT_A) { 1411 *pipe = PORT_TO_PIPE(tmp); 1412 } else { 1413 u32 trans_sel; 1414 u32 trans_dp; 1415 int i; 1416 1417 switch (intel_dp->output_reg) { 1418 case PCH_DP_B: 1419 trans_sel = TRANS_DP_PORT_SEL_B; 1420 break; 1421 case PCH_DP_C: 1422 trans_sel = TRANS_DP_PORT_SEL_C; 1423 break; 1424 case PCH_DP_D: 1425 trans_sel = TRANS_DP_PORT_SEL_D; 1426 break; 1427 default: 1428 return true; 1429 } 1430 1431 for_each_pipe(i) { 1432 trans_dp = I915_READ(TRANS_DP_CTL(i)); 1433 if ((trans_dp & TRANS_DP_PORT_SEL_MASK) == trans_sel) { 1434 *pipe = i; 1435 return true; 1436 } 1437 } 1438 1439 DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n", 1440 intel_dp->output_reg); 1441 } 1442 1443 return true; 1444} 1445 1446static void intel_dp_get_config(struct intel_encoder *encoder, 1447 struct intel_crtc_config *pipe_config) 1448{ 1449 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); 1450 u32 tmp, flags = 0; 1451 struct drm_device *dev = encoder->base.dev; 1452 struct drm_i915_private *dev_priv = dev->dev_private; 1453 enum port port = dp_to_dig_port(intel_dp)->port; 1454 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); 1455 int dotclock; 1456 1457 if ((port == PORT_A) || !HAS_PCH_CPT(dev)) { 1458 tmp = I915_READ(intel_dp->output_reg); 1459 if (tmp & DP_SYNC_HS_HIGH) 1460 flags |= DRM_MODE_FLAG_PHSYNC; 1461 else 1462 flags |= DRM_MODE_FLAG_NHSYNC; 1463 1464 if (tmp & DP_SYNC_VS_HIGH) 1465 flags |= DRM_MODE_FLAG_PVSYNC; 1466 else 1467 flags |= DRM_MODE_FLAG_NVSYNC; 1468 } else { 1469 tmp = I915_READ(TRANS_DP_CTL(crtc->pipe)); 1470 if (tmp & TRANS_DP_HSYNC_ACTIVE_HIGH) 1471 flags |= DRM_MODE_FLAG_PHSYNC; 1472 else 1473 flags |= DRM_MODE_FLAG_NHSYNC; 1474 1475 if (tmp & TRANS_DP_VSYNC_ACTIVE_HIGH) 1476 flags |= DRM_MODE_FLAG_PVSYNC; 1477 else 1478 flags |= DRM_MODE_FLAG_NVSYNC; 1479 } 1480 1481 pipe_config->adjusted_mode.flags |= flags; 1482 1483 pipe_config->has_dp_encoder = true; 1484 1485 intel_dp_get_m_n(crtc, pipe_config); 1486 1487 if (port == PORT_A) { 1488 if ((I915_READ(DP_A) & DP_PLL_FREQ_MASK) == DP_PLL_FREQ_160MHZ) 1489 pipe_config->port_clock = 162000; 1490 else 1491 pipe_config->port_clock = 270000; 1492 } 1493 1494 dotclock = intel_dotclock_calculate(pipe_config->port_clock, 1495 &pipe_config->dp_m_n); 1496 1497 if (HAS_PCH_SPLIT(dev_priv->dev) && port != PORT_A) 1498 ironlake_check_encoder_dotclock(pipe_config, dotclock); 1499 1500 pipe_config->adjusted_mode.crtc_clock = dotclock; 1501 1502 if (is_edp(intel_dp) && dev_priv->vbt.edp_bpp && 1503 pipe_config->pipe_bpp > dev_priv->vbt.edp_bpp) { 1504 /* 1505 * This is a big fat ugly hack. 1506 * 1507 * Some machines in UEFI boot mode provide us a VBT that has 18 1508 * bpp and 1.62 GHz link bandwidth for eDP, which for reasons 1509 * unknown we fail to light up. Yet the same BIOS boots up with 1510 * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as 1511 * max, not what it tells us to use. 1512 * 1513 * Note: This will still be broken if the eDP panel is not lit 1514 * up by the BIOS, and thus we can't get the mode at module 1515 * load. 1516 */ 1517 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n", 1518 pipe_config->pipe_bpp, dev_priv->vbt.edp_bpp); 1519 dev_priv->vbt.edp_bpp = pipe_config->pipe_bpp; 1520 } 1521} 1522 1523static bool is_edp_psr(struct drm_device *dev) 1524{ 1525 struct drm_i915_private *dev_priv = dev->dev_private; 1526 1527 return dev_priv->psr.sink_support; 1528} 1529 1530static bool intel_edp_is_psr_enabled(struct drm_device *dev) 1531{ 1532 struct drm_i915_private *dev_priv = dev->dev_private; 1533 1534 if (!HAS_PSR(dev)) 1535 return false; 1536 1537 return I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE; 1538} 1539 1540static void intel_edp_psr_write_vsc(struct intel_dp *intel_dp, 1541 struct edp_vsc_psr *vsc_psr) 1542{ 1543 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 1544 struct drm_device *dev = dig_port->base.base.dev; 1545 struct drm_i915_private *dev_priv = dev->dev_private; 1546 struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc); 1547 u32 ctl_reg = HSW_TVIDEO_DIP_CTL(crtc->config.cpu_transcoder); 1548 u32 data_reg = HSW_TVIDEO_DIP_VSC_DATA(crtc->config.cpu_transcoder); 1549 uint32_t *data = (uint32_t *) vsc_psr; 1550 unsigned int i; 1551 1552 /* As per BSPec (Pipe Video Data Island Packet), we need to disable 1553 the video DIP being updated before program video DIP data buffer 1554 registers for DIP being updated. */ 1555 I915_WRITE(ctl_reg, 0); 1556 POSTING_READ(ctl_reg); 1557 1558 for (i = 0; i < VIDEO_DIP_VSC_DATA_SIZE; i += 4) { 1559 if (i < sizeof(struct edp_vsc_psr)) 1560 I915_WRITE(data_reg + i, *data++); 1561 else 1562 I915_WRITE(data_reg + i, 0); 1563 } 1564 1565 I915_WRITE(ctl_reg, VIDEO_DIP_ENABLE_VSC_HSW); 1566 POSTING_READ(ctl_reg); 1567} 1568 1569static void intel_edp_psr_setup(struct intel_dp *intel_dp) 1570{ 1571 struct drm_device *dev = intel_dp_to_dev(intel_dp); 1572 struct drm_i915_private *dev_priv = dev->dev_private; 1573 struct edp_vsc_psr psr_vsc; 1574 1575 if (intel_dp->psr_setup_done) 1576 return; 1577 1578 /* Prepare VSC packet as per EDP 1.3 spec, Table 3.10 */ 1579 memset(&psr_vsc, 0, sizeof(psr_vsc)); 1580 psr_vsc.sdp_header.HB0 = 0; 1581 psr_vsc.sdp_header.HB1 = 0x7; 1582 psr_vsc.sdp_header.HB2 = 0x2; 1583 psr_vsc.sdp_header.HB3 = 0x8; 1584 intel_edp_psr_write_vsc(intel_dp, &psr_vsc); 1585 1586 /* Avoid continuous PSR exit by masking memup and hpd */ 1587 I915_WRITE(EDP_PSR_DEBUG_CTL(dev), EDP_PSR_DEBUG_MASK_MEMUP | 1588 EDP_PSR_DEBUG_MASK_HPD | EDP_PSR_DEBUG_MASK_LPSP); 1589 1590 intel_dp->psr_setup_done = true; 1591} 1592 1593static void intel_edp_psr_enable_sink(struct intel_dp *intel_dp) 1594{ 1595 struct drm_device *dev = intel_dp_to_dev(intel_dp); 1596 struct drm_i915_private *dev_priv = dev->dev_private; 1597 uint32_t aux_clock_divider; 1598 int precharge = 0x3; 1599 int msg_size = 5; /* Header(4) + Message(1) */ 1600 1601 aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, 0); 1602 1603 /* Enable PSR in sink */ 1604 if (intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT) 1605 drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG, 1606 DP_PSR_ENABLE & ~DP_PSR_MAIN_LINK_ACTIVE); 1607 else 1608 drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG, 1609 DP_PSR_ENABLE | DP_PSR_MAIN_LINK_ACTIVE); 1610 1611 /* Setup AUX registers */ 1612 I915_WRITE(EDP_PSR_AUX_DATA1(dev), EDP_PSR_DPCD_COMMAND); 1613 I915_WRITE(EDP_PSR_AUX_DATA2(dev), EDP_PSR_DPCD_NORMAL_OPERATION); 1614 I915_WRITE(EDP_PSR_AUX_CTL(dev), 1615 DP_AUX_CH_CTL_TIME_OUT_400us | 1616 (msg_size << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) | 1617 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) | 1618 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT)); 1619} 1620 1621static void intel_edp_psr_enable_source(struct intel_dp *intel_dp) 1622{ 1623 struct drm_device *dev = intel_dp_to_dev(intel_dp); 1624 struct drm_i915_private *dev_priv = dev->dev_private; 1625 uint32_t max_sleep_time = 0x1f; 1626 uint32_t idle_frames = 1; 1627 uint32_t val = 0x0; 1628 const uint32_t link_entry_time = EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES; 1629 1630 if (intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT) { 1631 val |= EDP_PSR_LINK_STANDBY; 1632 val |= EDP_PSR_TP2_TP3_TIME_0us; 1633 val |= EDP_PSR_TP1_TIME_0us; 1634 val |= EDP_PSR_SKIP_AUX_EXIT; 1635 } else 1636 val |= EDP_PSR_LINK_DISABLE; 1637 1638 I915_WRITE(EDP_PSR_CTL(dev), val | 1639 (IS_BROADWELL(dev) ? 0 : link_entry_time) | 1640 max_sleep_time << EDP_PSR_MAX_SLEEP_TIME_SHIFT | 1641 idle_frames << EDP_PSR_IDLE_FRAME_SHIFT | 1642 EDP_PSR_ENABLE); 1643} 1644 1645static bool intel_edp_psr_match_conditions(struct intel_dp *intel_dp) 1646{ 1647 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 1648 struct drm_device *dev = dig_port->base.base.dev; 1649 struct drm_i915_private *dev_priv = dev->dev_private; 1650 struct drm_crtc *crtc = dig_port->base.base.crtc; 1651 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 1652 struct drm_i915_gem_object *obj = to_intel_framebuffer(crtc->primary->fb)->obj; 1653 struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base; 1654 1655 dev_priv->psr.source_ok = false; 1656 1657 if (!HAS_PSR(dev)) { 1658 DRM_DEBUG_KMS("PSR not supported on this platform\n"); 1659 return false; 1660 } 1661 1662 if ((intel_encoder->type != INTEL_OUTPUT_EDP) || 1663 (dig_port->port != PORT_A)) { 1664 DRM_DEBUG_KMS("HSW ties PSR to DDI A (eDP)\n"); 1665 return false; 1666 } 1667 1668 if (!i915.enable_psr) { 1669 DRM_DEBUG_KMS("PSR disable by flag\n"); 1670 return false; 1671 } 1672 1673 crtc = dig_port->base.base.crtc; 1674 if (crtc == NULL) { 1675 DRM_DEBUG_KMS("crtc not active for PSR\n"); 1676 return false; 1677 } 1678 1679 intel_crtc = to_intel_crtc(crtc); 1680 if (!intel_crtc_active(crtc)) { 1681 DRM_DEBUG_KMS("crtc not active for PSR\n"); 1682 return false; 1683 } 1684 1685 obj = to_intel_framebuffer(crtc->primary->fb)->obj; 1686 if (obj->tiling_mode != I915_TILING_X || 1687 obj->fence_reg == I915_FENCE_REG_NONE) { 1688 DRM_DEBUG_KMS("PSR condition failed: fb not tiled or fenced\n"); 1689 return false; 1690 } 1691 1692 if (I915_READ(SPRCTL(intel_crtc->pipe)) & SPRITE_ENABLE) { 1693 DRM_DEBUG_KMS("PSR condition failed: Sprite is Enabled\n"); 1694 return false; 1695 } 1696 1697 if (I915_READ(HSW_STEREO_3D_CTL(intel_crtc->config.cpu_transcoder)) & 1698 S3D_ENABLE) { 1699 DRM_DEBUG_KMS("PSR condition failed: Stereo 3D is Enabled\n"); 1700 return false; 1701 } 1702 1703 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) { 1704 DRM_DEBUG_KMS("PSR condition failed: Interlaced is Enabled\n"); 1705 return false; 1706 } 1707 1708 dev_priv->psr.source_ok = true; 1709 return true; 1710} 1711 1712static void intel_edp_psr_do_enable(struct intel_dp *intel_dp) 1713{ 1714 struct drm_device *dev = intel_dp_to_dev(intel_dp); 1715 1716 if (!intel_edp_psr_match_conditions(intel_dp) || 1717 intel_edp_is_psr_enabled(dev)) 1718 return; 1719 1720 /* Setup PSR once */ 1721 intel_edp_psr_setup(intel_dp); 1722 1723 /* Enable PSR on the panel */ 1724 intel_edp_psr_enable_sink(intel_dp); 1725 1726 /* Enable PSR on the host */ 1727 intel_edp_psr_enable_source(intel_dp); 1728} 1729 1730void intel_edp_psr_enable(struct intel_dp *intel_dp) 1731{ 1732 struct drm_device *dev = intel_dp_to_dev(intel_dp); 1733 1734 if (intel_edp_psr_match_conditions(intel_dp) && 1735 !intel_edp_is_psr_enabled(dev)) 1736 intel_edp_psr_do_enable(intel_dp); 1737} 1738 1739void intel_edp_psr_disable(struct intel_dp *intel_dp) 1740{ 1741 struct drm_device *dev = intel_dp_to_dev(intel_dp); 1742 struct drm_i915_private *dev_priv = dev->dev_private; 1743 1744 if (!intel_edp_is_psr_enabled(dev)) 1745 return; 1746 1747 I915_WRITE(EDP_PSR_CTL(dev), 1748 I915_READ(EDP_PSR_CTL(dev)) & ~EDP_PSR_ENABLE); 1749 1750 /* Wait till PSR is idle */ 1751 if (_wait_for((I915_READ(EDP_PSR_STATUS_CTL(dev)) & 1752 EDP_PSR_STATUS_STATE_MASK) == 0, 2000, 10)) 1753 DRM_ERROR("Timed out waiting for PSR Idle State\n"); 1754} 1755 1756void intel_edp_psr_update(struct drm_device *dev) 1757{ 1758 struct intel_encoder *encoder; 1759 struct intel_dp *intel_dp = NULL; 1760 1761 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) 1762 if (encoder->type == INTEL_OUTPUT_EDP) { 1763 intel_dp = enc_to_intel_dp(&encoder->base); 1764 1765 if (!is_edp_psr(dev)) 1766 return; 1767 1768 if (!intel_edp_psr_match_conditions(intel_dp)) 1769 intel_edp_psr_disable(intel_dp); 1770 else 1771 if (!intel_edp_is_psr_enabled(dev)) 1772 intel_edp_psr_do_enable(intel_dp); 1773 } 1774} 1775 1776static void intel_disable_dp(struct intel_encoder *encoder) 1777{ 1778 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); 1779 enum port port = dp_to_dig_port(intel_dp)->port; 1780 struct drm_device *dev = encoder->base.dev; 1781 1782 /* Make sure the panel is off before trying to change the mode. But also 1783 * ensure that we have vdd while we switch off the panel. */ 1784 intel_edp_panel_vdd_on(intel_dp); 1785 intel_edp_backlight_off(intel_dp); 1786 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF); 1787 intel_edp_panel_off(intel_dp); 1788 1789 /* cpu edp my only be disable _after_ the cpu pipe/plane is disabled. */ 1790 if (!(port == PORT_A || IS_VALLEYVIEW(dev))) 1791 intel_dp_link_down(intel_dp); 1792} 1793 1794static void g4x_post_disable_dp(struct intel_encoder *encoder) 1795{ 1796 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); 1797 enum port port = dp_to_dig_port(intel_dp)->port; 1798 1799 if (port != PORT_A) 1800 return; 1801 1802 intel_dp_link_down(intel_dp); 1803 ironlake_edp_pll_off(intel_dp); 1804} 1805 1806static void vlv_post_disable_dp(struct intel_encoder *encoder) 1807{ 1808 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); 1809 1810 intel_dp_link_down(intel_dp); 1811} 1812 1813static void intel_enable_dp(struct intel_encoder *encoder) 1814{ 1815 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); 1816 struct drm_device *dev = encoder->base.dev; 1817 struct drm_i915_private *dev_priv = dev->dev_private; 1818 uint32_t dp_reg = I915_READ(intel_dp->output_reg); 1819 1820 if (WARN_ON(dp_reg & DP_PORT_EN)) 1821 return; 1822 1823 intel_edp_panel_vdd_on(intel_dp); 1824 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON); 1825 intel_dp_start_link_train(intel_dp); 1826 intel_edp_panel_on(intel_dp); 1827 edp_panel_vdd_off(intel_dp, true); 1828 intel_dp_complete_link_train(intel_dp); 1829 intel_dp_stop_link_train(intel_dp); 1830} 1831 1832static void g4x_enable_dp(struct intel_encoder *encoder) 1833{ 1834 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); 1835 1836 intel_enable_dp(encoder); 1837 intel_edp_backlight_on(intel_dp); 1838} 1839 1840static void vlv_enable_dp(struct intel_encoder *encoder) 1841{ 1842 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); 1843 1844 intel_edp_backlight_on(intel_dp); 1845} 1846 1847static void g4x_pre_enable_dp(struct intel_encoder *encoder) 1848{ 1849 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); 1850 struct intel_digital_port *dport = dp_to_dig_port(intel_dp); 1851 1852 if (dport->port == PORT_A) 1853 ironlake_edp_pll_on(intel_dp); 1854} 1855 1856static void vlv_pre_enable_dp(struct intel_encoder *encoder) 1857{ 1858 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); 1859 struct intel_digital_port *dport = dp_to_dig_port(intel_dp); 1860 struct drm_device *dev = encoder->base.dev; 1861 struct drm_i915_private *dev_priv = dev->dev_private; 1862 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc); 1863 enum dpio_channel port = vlv_dport_to_channel(dport); 1864 int pipe = intel_crtc->pipe; 1865 struct edp_power_seq power_seq; 1866 u32 val; 1867 1868 mutex_lock(&dev_priv->dpio_lock); 1869 1870 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(port)); 1871 val = 0; 1872 if (pipe) 1873 val |= (1<<21); 1874 else 1875 val &= ~(1<<21); 1876 val |= 0x001000c4; 1877 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW8(port), val); 1878 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW14(port), 0x00760018); 1879 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW23(port), 0x00400888); 1880 1881 mutex_unlock(&dev_priv->dpio_lock); 1882 1883 if (is_edp(intel_dp)) { 1884 /* init power sequencer on this pipe and port */ 1885 intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq); 1886 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp, 1887 &power_seq); 1888 } 1889 1890 intel_enable_dp(encoder); 1891 1892 vlv_wait_port_ready(dev_priv, dport); 1893} 1894 1895static void vlv_dp_pre_pll_enable(struct intel_encoder *encoder) 1896{ 1897 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base); 1898 struct drm_device *dev = encoder->base.dev; 1899 struct drm_i915_private *dev_priv = dev->dev_private; 1900 struct intel_crtc *intel_crtc = 1901 to_intel_crtc(encoder->base.crtc); 1902 enum dpio_channel port = vlv_dport_to_channel(dport); 1903 int pipe = intel_crtc->pipe; 1904 1905 /* Program Tx lane resets to default */ 1906 mutex_lock(&dev_priv->dpio_lock); 1907 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port), 1908 DPIO_PCS_TX_LANE2_RESET | 1909 DPIO_PCS_TX_LANE1_RESET); 1910 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port), 1911 DPIO_PCS_CLK_CRI_RXEB_EIOS_EN | 1912 DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN | 1913 (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT) | 1914 DPIO_PCS_CLK_SOFT_RESET); 1915 1916 /* Fix up inter-pair skew failure */ 1917 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW12(port), 0x00750f00); 1918 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW11(port), 0x00001500); 1919 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW14(port), 0x40400000); 1920 mutex_unlock(&dev_priv->dpio_lock); 1921} 1922 1923/* 1924 * Native read with retry for link status and receiver capability reads for 1925 * cases where the sink may still be asleep. 1926 * 1927 * Sinks are *supposed* to come up within 1ms from an off state, but we're also 1928 * supposed to retry 3 times per the spec. 1929 */ 1930static ssize_t 1931intel_dp_dpcd_read_wake(struct drm_dp_aux *aux, unsigned int offset, 1932 void *buffer, size_t size) 1933{ 1934 ssize_t ret; 1935 int i; 1936 1937 for (i = 0; i < 3; i++) { 1938 ret = drm_dp_dpcd_read(aux, offset, buffer, size); 1939 if (ret == size) 1940 return ret; 1941 msleep(1); 1942 } 1943 1944 return ret; 1945} 1946 1947/* 1948 * Fetch AUX CH registers 0x202 - 0x207 which contain 1949 * link status information 1950 */ 1951static bool 1952intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE]) 1953{ 1954 return intel_dp_dpcd_read_wake(&intel_dp->aux, 1955 DP_LANE0_1_STATUS, 1956 link_status, 1957 DP_LINK_STATUS_SIZE) == DP_LINK_STATUS_SIZE; 1958} 1959 1960/* 1961 * These are source-specific values; current Intel hardware supports 1962 * a maximum voltage of 800mV and a maximum pre-emphasis of 6dB 1963 */ 1964 1965static uint8_t 1966intel_dp_voltage_max(struct intel_dp *intel_dp) 1967{ 1968 struct drm_device *dev = intel_dp_to_dev(intel_dp); 1969 enum port port = dp_to_dig_port(intel_dp)->port; 1970 1971 if (IS_VALLEYVIEW(dev) || IS_BROADWELL(dev)) 1972 return DP_TRAIN_VOLTAGE_SWING_1200; 1973 else if (IS_GEN7(dev) && port == PORT_A) 1974 return DP_TRAIN_VOLTAGE_SWING_800; 1975 else if (HAS_PCH_CPT(dev) && port != PORT_A) 1976 return DP_TRAIN_VOLTAGE_SWING_1200; 1977 else 1978 return DP_TRAIN_VOLTAGE_SWING_800; 1979} 1980 1981static uint8_t 1982intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing) 1983{ 1984 struct drm_device *dev = intel_dp_to_dev(intel_dp); 1985 enum port port = dp_to_dig_port(intel_dp)->port; 1986 1987 if (IS_BROADWELL(dev)) { 1988 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) { 1989 case DP_TRAIN_VOLTAGE_SWING_400: 1990 case DP_TRAIN_VOLTAGE_SWING_600: 1991 return DP_TRAIN_PRE_EMPHASIS_6; 1992 case DP_TRAIN_VOLTAGE_SWING_800: 1993 return DP_TRAIN_PRE_EMPHASIS_3_5; 1994 case DP_TRAIN_VOLTAGE_SWING_1200: 1995 default: 1996 return DP_TRAIN_PRE_EMPHASIS_0; 1997 } 1998 } else if (IS_HASWELL(dev)) { 1999 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) { 2000 case DP_TRAIN_VOLTAGE_SWING_400: 2001 return DP_TRAIN_PRE_EMPHASIS_9_5; 2002 case DP_TRAIN_VOLTAGE_SWING_600: 2003 return DP_TRAIN_PRE_EMPHASIS_6; 2004 case DP_TRAIN_VOLTAGE_SWING_800: 2005 return DP_TRAIN_PRE_EMPHASIS_3_5; 2006 case DP_TRAIN_VOLTAGE_SWING_1200: 2007 default: 2008 return DP_TRAIN_PRE_EMPHASIS_0; 2009 } 2010 } else if (IS_VALLEYVIEW(dev)) { 2011 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) { 2012 case DP_TRAIN_VOLTAGE_SWING_400: 2013 return DP_TRAIN_PRE_EMPHASIS_9_5; 2014 case DP_TRAIN_VOLTAGE_SWING_600: 2015 return DP_TRAIN_PRE_EMPHASIS_6; 2016 case DP_TRAIN_VOLTAGE_SWING_800: 2017 return DP_TRAIN_PRE_EMPHASIS_3_5; 2018 case DP_TRAIN_VOLTAGE_SWING_1200: 2019 default: 2020 return DP_TRAIN_PRE_EMPHASIS_0; 2021 } 2022 } else if (IS_GEN7(dev) && port == PORT_A) { 2023 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) { 2024 case DP_TRAIN_VOLTAGE_SWING_400: 2025 return DP_TRAIN_PRE_EMPHASIS_6; 2026 case DP_TRAIN_VOLTAGE_SWING_600: 2027 case DP_TRAIN_VOLTAGE_SWING_800: 2028 return DP_TRAIN_PRE_EMPHASIS_3_5; 2029 default: 2030 return DP_TRAIN_PRE_EMPHASIS_0; 2031 } 2032 } else { 2033 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) { 2034 case DP_TRAIN_VOLTAGE_SWING_400: 2035 return DP_TRAIN_PRE_EMPHASIS_6; 2036 case DP_TRAIN_VOLTAGE_SWING_600: 2037 return DP_TRAIN_PRE_EMPHASIS_6; 2038 case DP_TRAIN_VOLTAGE_SWING_800: 2039 return DP_TRAIN_PRE_EMPHASIS_3_5; 2040 case DP_TRAIN_VOLTAGE_SWING_1200: 2041 default: 2042 return DP_TRAIN_PRE_EMPHASIS_0; 2043 } 2044 } 2045} 2046 2047static uint32_t intel_vlv_signal_levels(struct intel_dp *intel_dp) 2048{ 2049 struct drm_device *dev = intel_dp_to_dev(intel_dp); 2050 struct drm_i915_private *dev_priv = dev->dev_private; 2051 struct intel_digital_port *dport = dp_to_dig_port(intel_dp); 2052 struct intel_crtc *intel_crtc = 2053 to_intel_crtc(dport->base.base.crtc); 2054 unsigned long demph_reg_value, preemph_reg_value, 2055 uniqtranscale_reg_value; 2056 uint8_t train_set = intel_dp->train_set[0]; 2057 enum dpio_channel port = vlv_dport_to_channel(dport); 2058 int pipe = intel_crtc->pipe; 2059 2060 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) { 2061 case DP_TRAIN_PRE_EMPHASIS_0: 2062 preemph_reg_value = 0x0004000; 2063 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { 2064 case DP_TRAIN_VOLTAGE_SWING_400: 2065 demph_reg_value = 0x2B405555; 2066 uniqtranscale_reg_value = 0x552AB83A; 2067 break; 2068 case DP_TRAIN_VOLTAGE_SWING_600: 2069 demph_reg_value = 0x2B404040; 2070 uniqtranscale_reg_value = 0x5548B83A; 2071 break; 2072 case DP_TRAIN_VOLTAGE_SWING_800: 2073 demph_reg_value = 0x2B245555; 2074 uniqtranscale_reg_value = 0x5560B83A; 2075 break; 2076 case DP_TRAIN_VOLTAGE_SWING_1200: 2077 demph_reg_value = 0x2B405555; 2078 uniqtranscale_reg_value = 0x5598DA3A; 2079 break; 2080 default: 2081 return 0; 2082 } 2083 break; 2084 case DP_TRAIN_PRE_EMPHASIS_3_5: 2085 preemph_reg_value = 0x0002000; 2086 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { 2087 case DP_TRAIN_VOLTAGE_SWING_400: 2088 demph_reg_value = 0x2B404040; 2089 uniqtranscale_reg_value = 0x5552B83A; 2090 break; 2091 case DP_TRAIN_VOLTAGE_SWING_600: 2092 demph_reg_value = 0x2B404848; 2093 uniqtranscale_reg_value = 0x5580B83A; 2094 break; 2095 case DP_TRAIN_VOLTAGE_SWING_800: 2096 demph_reg_value = 0x2B404040; 2097 uniqtranscale_reg_value = 0x55ADDA3A; 2098 break; 2099 default: 2100 return 0; 2101 } 2102 break; 2103 case DP_TRAIN_PRE_EMPHASIS_6: 2104 preemph_reg_value = 0x0000000; 2105 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { 2106 case DP_TRAIN_VOLTAGE_SWING_400: 2107 demph_reg_value = 0x2B305555; 2108 uniqtranscale_reg_value = 0x5570B83A; 2109 break; 2110 case DP_TRAIN_VOLTAGE_SWING_600: 2111 demph_reg_value = 0x2B2B4040; 2112 uniqtranscale_reg_value = 0x55ADDA3A; 2113 break; 2114 default: 2115 return 0; 2116 } 2117 break; 2118 case DP_TRAIN_PRE_EMPHASIS_9_5: 2119 preemph_reg_value = 0x0006000; 2120 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { 2121 case DP_TRAIN_VOLTAGE_SWING_400: 2122 demph_reg_value = 0x1B405555; 2123 uniqtranscale_reg_value = 0x55ADDA3A; 2124 break; 2125 default: 2126 return 0; 2127 } 2128 break; 2129 default: 2130 return 0; 2131 } 2132 2133 mutex_lock(&dev_priv->dpio_lock); 2134 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x00000000); 2135 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW4(port), demph_reg_value); 2136 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(port), 2137 uniqtranscale_reg_value); 2138 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(port), 0x0C782040); 2139 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW11(port), 0x00030000); 2140 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), preemph_reg_value); 2141 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x80000000); 2142 mutex_unlock(&dev_priv->dpio_lock); 2143 2144 return 0; 2145} 2146 2147static void 2148intel_get_adjust_train(struct intel_dp *intel_dp, 2149 const uint8_t link_status[DP_LINK_STATUS_SIZE]) 2150{ 2151 uint8_t v = 0; 2152 uint8_t p = 0; 2153 int lane; 2154 uint8_t voltage_max; 2155 uint8_t preemph_max; 2156 2157 for (lane = 0; lane < intel_dp->lane_count; lane++) { 2158 uint8_t this_v = drm_dp_get_adjust_request_voltage(link_status, lane); 2159 uint8_t this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane); 2160 2161 if (this_v > v) 2162 v = this_v; 2163 if (this_p > p) 2164 p = this_p; 2165 } 2166 2167 voltage_max = intel_dp_voltage_max(intel_dp); 2168 if (v >= voltage_max) 2169 v = voltage_max | DP_TRAIN_MAX_SWING_REACHED; 2170 2171 preemph_max = intel_dp_pre_emphasis_max(intel_dp, v); 2172 if (p >= preemph_max) 2173 p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED; 2174 2175 for (lane = 0; lane < 4; lane++) 2176 intel_dp->train_set[lane] = v | p; 2177} 2178 2179static uint32_t 2180intel_gen4_signal_levels(uint8_t train_set) 2181{ 2182 uint32_t signal_levels = 0; 2183 2184 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { 2185 case DP_TRAIN_VOLTAGE_SWING_400: 2186 default: 2187 signal_levels |= DP_VOLTAGE_0_4; 2188 break; 2189 case DP_TRAIN_VOLTAGE_SWING_600: 2190 signal_levels |= DP_VOLTAGE_0_6; 2191 break; 2192 case DP_TRAIN_VOLTAGE_SWING_800: 2193 signal_levels |= DP_VOLTAGE_0_8; 2194 break; 2195 case DP_TRAIN_VOLTAGE_SWING_1200: 2196 signal_levels |= DP_VOLTAGE_1_2; 2197 break; 2198 } 2199 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) { 2200 case DP_TRAIN_PRE_EMPHASIS_0: 2201 default: 2202 signal_levels |= DP_PRE_EMPHASIS_0; 2203 break; 2204 case DP_TRAIN_PRE_EMPHASIS_3_5: 2205 signal_levels |= DP_PRE_EMPHASIS_3_5; 2206 break; 2207 case DP_TRAIN_PRE_EMPHASIS_6: 2208 signal_levels |= DP_PRE_EMPHASIS_6; 2209 break; 2210 case DP_TRAIN_PRE_EMPHASIS_9_5: 2211 signal_levels |= DP_PRE_EMPHASIS_9_5; 2212 break; 2213 } 2214 return signal_levels; 2215} 2216 2217/* Gen6's DP voltage swing and pre-emphasis control */ 2218static uint32_t 2219intel_gen6_edp_signal_levels(uint8_t train_set) 2220{ 2221 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK | 2222 DP_TRAIN_PRE_EMPHASIS_MASK); 2223 switch (signal_levels) { 2224 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0: 2225 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0: 2226 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B; 2227 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5: 2228 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B; 2229 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6: 2230 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6: 2231 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B; 2232 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5: 2233 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5: 2234 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B; 2235 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0: 2236 case DP_TRAIN_VOLTAGE_SWING_1200 | DP_TRAIN_PRE_EMPHASIS_0: 2237 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B; 2238 default: 2239 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:" 2240 "0x%x\n", signal_levels); 2241 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B; 2242 } 2243} 2244 2245/* Gen7's DP voltage swing and pre-emphasis control */ 2246static uint32_t 2247intel_gen7_edp_signal_levels(uint8_t train_set) 2248{ 2249 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK | 2250 DP_TRAIN_PRE_EMPHASIS_MASK); 2251 switch (signal_levels) { 2252 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0: 2253 return EDP_LINK_TRAIN_400MV_0DB_IVB; 2254 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5: 2255 return EDP_LINK_TRAIN_400MV_3_5DB_IVB; 2256 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6: 2257 return EDP_LINK_TRAIN_400MV_6DB_IVB; 2258 2259 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0: 2260 return EDP_LINK_TRAIN_600MV_0DB_IVB; 2261 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5: 2262 return EDP_LINK_TRAIN_600MV_3_5DB_IVB; 2263 2264 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0: 2265 return EDP_LINK_TRAIN_800MV_0DB_IVB; 2266 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5: 2267 return EDP_LINK_TRAIN_800MV_3_5DB_IVB; 2268 2269 default: 2270 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:" 2271 "0x%x\n", signal_levels); 2272 return EDP_LINK_TRAIN_500MV_0DB_IVB; 2273 } 2274} 2275 2276/* Gen7.5's (HSW) DP voltage swing and pre-emphasis control */ 2277static uint32_t 2278intel_hsw_signal_levels(uint8_t train_set) 2279{ 2280 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK | 2281 DP_TRAIN_PRE_EMPHASIS_MASK); 2282 switch (signal_levels) { 2283 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0: 2284 return DDI_BUF_EMP_400MV_0DB_HSW; 2285 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5: 2286 return DDI_BUF_EMP_400MV_3_5DB_HSW; 2287 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6: 2288 return DDI_BUF_EMP_400MV_6DB_HSW; 2289 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_9_5: 2290 return DDI_BUF_EMP_400MV_9_5DB_HSW; 2291 2292 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0: 2293 return DDI_BUF_EMP_600MV_0DB_HSW; 2294 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5: 2295 return DDI_BUF_EMP_600MV_3_5DB_HSW; 2296 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6: 2297 return DDI_BUF_EMP_600MV_6DB_HSW; 2298 2299 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0: 2300 return DDI_BUF_EMP_800MV_0DB_HSW; 2301 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5: 2302 return DDI_BUF_EMP_800MV_3_5DB_HSW; 2303 default: 2304 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:" 2305 "0x%x\n", signal_levels); 2306 return DDI_BUF_EMP_400MV_0DB_HSW; 2307 } 2308} 2309 2310static uint32_t 2311intel_bdw_signal_levels(uint8_t train_set) 2312{ 2313 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK | 2314 DP_TRAIN_PRE_EMPHASIS_MASK); 2315 switch (signal_levels) { 2316 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0: 2317 return DDI_BUF_EMP_400MV_0DB_BDW; /* Sel0 */ 2318 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5: 2319 return DDI_BUF_EMP_400MV_3_5DB_BDW; /* Sel1 */ 2320 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6: 2321 return DDI_BUF_EMP_400MV_6DB_BDW; /* Sel2 */ 2322 2323 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0: 2324 return DDI_BUF_EMP_600MV_0DB_BDW; /* Sel3 */ 2325 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5: 2326 return DDI_BUF_EMP_600MV_3_5DB_BDW; /* Sel4 */ 2327 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6: 2328 return DDI_BUF_EMP_600MV_6DB_BDW; /* Sel5 */ 2329 2330 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0: 2331 return DDI_BUF_EMP_800MV_0DB_BDW; /* Sel6 */ 2332 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5: 2333 return DDI_BUF_EMP_800MV_3_5DB_BDW; /* Sel7 */ 2334 2335 case DP_TRAIN_VOLTAGE_SWING_1200 | DP_TRAIN_PRE_EMPHASIS_0: 2336 return DDI_BUF_EMP_1200MV_0DB_BDW; /* Sel8 */ 2337 2338 default: 2339 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:" 2340 "0x%x\n", signal_levels); 2341 return DDI_BUF_EMP_400MV_0DB_BDW; /* Sel0 */ 2342 } 2343} 2344 2345/* Properly updates "DP" with the correct signal levels. */ 2346static void 2347intel_dp_set_signal_levels(struct intel_dp *intel_dp, uint32_t *DP) 2348{ 2349 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 2350 enum port port = intel_dig_port->port; 2351 struct drm_device *dev = intel_dig_port->base.base.dev; 2352 uint32_t signal_levels, mask; 2353 uint8_t train_set = intel_dp->train_set[0]; 2354 2355 if (IS_BROADWELL(dev)) { 2356 signal_levels = intel_bdw_signal_levels(train_set); 2357 mask = DDI_BUF_EMP_MASK; 2358 } else if (IS_HASWELL(dev)) { 2359 signal_levels = intel_hsw_signal_levels(train_set); 2360 mask = DDI_BUF_EMP_MASK; 2361 } else if (IS_VALLEYVIEW(dev)) { 2362 signal_levels = intel_vlv_signal_levels(intel_dp); 2363 mask = 0; 2364 } else if (IS_GEN7(dev) && port == PORT_A) { 2365 signal_levels = intel_gen7_edp_signal_levels(train_set); 2366 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_IVB; 2367 } else if (IS_GEN6(dev) && port == PORT_A) { 2368 signal_levels = intel_gen6_edp_signal_levels(train_set); 2369 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB; 2370 } else { 2371 signal_levels = intel_gen4_signal_levels(train_set); 2372 mask = DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK; 2373 } 2374 2375 DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels); 2376 2377 *DP = (*DP & ~mask) | signal_levels; 2378} 2379 2380static bool 2381intel_dp_set_link_train(struct intel_dp *intel_dp, 2382 uint32_t *DP, 2383 uint8_t dp_train_pat) 2384{ 2385 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 2386 struct drm_device *dev = intel_dig_port->base.base.dev; 2387 struct drm_i915_private *dev_priv = dev->dev_private; 2388 enum port port = intel_dig_port->port; 2389 uint8_t buf[sizeof(intel_dp->train_set) + 1]; 2390 int ret, len; 2391 2392 if (HAS_DDI(dev)) { 2393 uint32_t temp = I915_READ(DP_TP_CTL(port)); 2394 2395 if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE) 2396 temp |= DP_TP_CTL_SCRAMBLE_DISABLE; 2397 else 2398 temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE; 2399 2400 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK; 2401 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) { 2402 case DP_TRAINING_PATTERN_DISABLE: 2403 temp |= DP_TP_CTL_LINK_TRAIN_NORMAL; 2404 2405 break; 2406 case DP_TRAINING_PATTERN_1: 2407 temp |= DP_TP_CTL_LINK_TRAIN_PAT1; 2408 break; 2409 case DP_TRAINING_PATTERN_2: 2410 temp |= DP_TP_CTL_LINK_TRAIN_PAT2; 2411 break; 2412 case DP_TRAINING_PATTERN_3: 2413 temp |= DP_TP_CTL_LINK_TRAIN_PAT3; 2414 break; 2415 } 2416 I915_WRITE(DP_TP_CTL(port), temp); 2417 2418 } else if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) { 2419 *DP &= ~DP_LINK_TRAIN_MASK_CPT; 2420 2421 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) { 2422 case DP_TRAINING_PATTERN_DISABLE: 2423 *DP |= DP_LINK_TRAIN_OFF_CPT; 2424 break; 2425 case DP_TRAINING_PATTERN_1: 2426 *DP |= DP_LINK_TRAIN_PAT_1_CPT; 2427 break; 2428 case DP_TRAINING_PATTERN_2: 2429 *DP |= DP_LINK_TRAIN_PAT_2_CPT; 2430 break; 2431 case DP_TRAINING_PATTERN_3: 2432 DRM_ERROR("DP training pattern 3 not supported\n"); 2433 *DP |= DP_LINK_TRAIN_PAT_2_CPT; 2434 break; 2435 } 2436 2437 } else { 2438 *DP &= ~DP_LINK_TRAIN_MASK; 2439 2440 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) { 2441 case DP_TRAINING_PATTERN_DISABLE: 2442 *DP |= DP_LINK_TRAIN_OFF; 2443 break; 2444 case DP_TRAINING_PATTERN_1: 2445 *DP |= DP_LINK_TRAIN_PAT_1; 2446 break; 2447 case DP_TRAINING_PATTERN_2: 2448 *DP |= DP_LINK_TRAIN_PAT_2; 2449 break; 2450 case DP_TRAINING_PATTERN_3: 2451 DRM_ERROR("DP training pattern 3 not supported\n"); 2452 *DP |= DP_LINK_TRAIN_PAT_2; 2453 break; 2454 } 2455 } 2456 2457 I915_WRITE(intel_dp->output_reg, *DP); 2458 POSTING_READ(intel_dp->output_reg); 2459 2460 buf[0] = dp_train_pat; 2461 if ((dp_train_pat & DP_TRAINING_PATTERN_MASK) == 2462 DP_TRAINING_PATTERN_DISABLE) { 2463 /* don't write DP_TRAINING_LANEx_SET on disable */ 2464 len = 1; 2465 } else { 2466 /* DP_TRAINING_LANEx_SET follow DP_TRAINING_PATTERN_SET */ 2467 memcpy(buf + 1, intel_dp->train_set, intel_dp->lane_count); 2468 len = intel_dp->lane_count + 1; 2469 } 2470 2471 ret = drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_PATTERN_SET, 2472 buf, len); 2473 2474 return ret == len; 2475} 2476 2477static bool 2478intel_dp_reset_link_train(struct intel_dp *intel_dp, uint32_t *DP, 2479 uint8_t dp_train_pat) 2480{ 2481 memset(intel_dp->train_set, 0, sizeof(intel_dp->train_set)); 2482 intel_dp_set_signal_levels(intel_dp, DP); 2483 return intel_dp_set_link_train(intel_dp, DP, dp_train_pat); 2484} 2485 2486static bool 2487intel_dp_update_link_train(struct intel_dp *intel_dp, uint32_t *DP, 2488 const uint8_t link_status[DP_LINK_STATUS_SIZE]) 2489{ 2490 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 2491 struct drm_device *dev = intel_dig_port->base.base.dev; 2492 struct drm_i915_private *dev_priv = dev->dev_private; 2493 int ret; 2494 2495 intel_get_adjust_train(intel_dp, link_status); 2496 intel_dp_set_signal_levels(intel_dp, DP); 2497 2498 I915_WRITE(intel_dp->output_reg, *DP); 2499 POSTING_READ(intel_dp->output_reg); 2500 2501 ret = drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_LANE0_SET, 2502 intel_dp->train_set, intel_dp->lane_count); 2503 2504 return ret == intel_dp->lane_count; 2505} 2506 2507static void intel_dp_set_idle_link_train(struct intel_dp *intel_dp) 2508{ 2509 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 2510 struct drm_device *dev = intel_dig_port->base.base.dev; 2511 struct drm_i915_private *dev_priv = dev->dev_private; 2512 enum port port = intel_dig_port->port; 2513 uint32_t val; 2514 2515 if (!HAS_DDI(dev)) 2516 return; 2517 2518 val = I915_READ(DP_TP_CTL(port)); 2519 val &= ~DP_TP_CTL_LINK_TRAIN_MASK; 2520 val |= DP_TP_CTL_LINK_TRAIN_IDLE; 2521 I915_WRITE(DP_TP_CTL(port), val); 2522 2523 /* 2524 * On PORT_A we can have only eDP in SST mode. There the only reason 2525 * we need to set idle transmission mode is to work around a HW issue 2526 * where we enable the pipe while not in idle link-training mode. 2527 * In this case there is requirement to wait for a minimum number of 2528 * idle patterns to be sent. 2529 */ 2530 if (port == PORT_A) 2531 return; 2532 2533 if (wait_for((I915_READ(DP_TP_STATUS(port)) & DP_TP_STATUS_IDLE_DONE), 2534 1)) 2535 DRM_ERROR("Timed out waiting for DP idle patterns\n"); 2536} 2537 2538/* Enable corresponding port and start training pattern 1 */ 2539void 2540intel_dp_start_link_train(struct intel_dp *intel_dp) 2541{ 2542 struct drm_encoder *encoder = &dp_to_dig_port(intel_dp)->base.base; 2543 struct drm_device *dev = encoder->dev; 2544 int i; 2545 uint8_t voltage; 2546 int voltage_tries, loop_tries; 2547 uint32_t DP = intel_dp->DP; 2548 uint8_t link_config[2]; 2549 2550 if (HAS_DDI(dev)) 2551 intel_ddi_prepare_link_retrain(encoder); 2552 2553 /* Write the link configuration data */ 2554 link_config[0] = intel_dp->link_bw; 2555 link_config[1] = intel_dp->lane_count; 2556 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd)) 2557 link_config[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN; 2558 drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_BW_SET, link_config, 2); 2559 2560 link_config[0] = 0; 2561 link_config[1] = DP_SET_ANSI_8B10B; 2562 drm_dp_dpcd_write(&intel_dp->aux, DP_DOWNSPREAD_CTRL, link_config, 2); 2563 2564 DP |= DP_PORT_EN; 2565 2566 /* clock recovery */ 2567 if (!intel_dp_reset_link_train(intel_dp, &DP, 2568 DP_TRAINING_PATTERN_1 | 2569 DP_LINK_SCRAMBLING_DISABLE)) { 2570 DRM_ERROR("failed to enable link training\n"); 2571 return; 2572 } 2573 2574 voltage = 0xff; 2575 voltage_tries = 0; 2576 loop_tries = 0; 2577 for (;;) { 2578 uint8_t link_status[DP_LINK_STATUS_SIZE]; 2579 2580 drm_dp_link_train_clock_recovery_delay(intel_dp->dpcd); 2581 if (!intel_dp_get_link_status(intel_dp, link_status)) { 2582 DRM_ERROR("failed to get link status\n"); 2583 break; 2584 } 2585 2586 if (drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) { 2587 DRM_DEBUG_KMS("clock recovery OK\n"); 2588 break; 2589 } 2590 2591 /* Check to see if we've tried the max voltage */ 2592 for (i = 0; i < intel_dp->lane_count; i++) 2593 if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0) 2594 break; 2595 if (i == intel_dp->lane_count) { 2596 ++loop_tries; 2597 if (loop_tries == 5) { 2598 DRM_ERROR("too many full retries, give up\n"); 2599 break; 2600 } 2601 intel_dp_reset_link_train(intel_dp, &DP, 2602 DP_TRAINING_PATTERN_1 | 2603 DP_LINK_SCRAMBLING_DISABLE); 2604 voltage_tries = 0; 2605 continue; 2606 } 2607 2608 /* Check to see if we've tried the same voltage 5 times */ 2609 if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) { 2610 ++voltage_tries; 2611 if (voltage_tries == 5) { 2612 DRM_ERROR("too many voltage retries, give up\n"); 2613 break; 2614 } 2615 } else 2616 voltage_tries = 0; 2617 voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK; 2618 2619 /* Update training set as requested by target */ 2620 if (!intel_dp_update_link_train(intel_dp, &DP, link_status)) { 2621 DRM_ERROR("failed to update link training\n"); 2622 break; 2623 } 2624 } 2625 2626 intel_dp->DP = DP; 2627} 2628 2629void 2630intel_dp_complete_link_train(struct intel_dp *intel_dp) 2631{ 2632 bool channel_eq = false; 2633 int tries, cr_tries; 2634 uint32_t DP = intel_dp->DP; 2635 uint32_t training_pattern = DP_TRAINING_PATTERN_2; 2636 2637 /* Training Pattern 3 for HBR2 ot 1.2 devices that support it*/ 2638 if (intel_dp->link_bw == DP_LINK_BW_5_4 || intel_dp->use_tps3) 2639 training_pattern = DP_TRAINING_PATTERN_3; 2640 2641 /* channel equalization */ 2642 if (!intel_dp_set_link_train(intel_dp, &DP, 2643 training_pattern | 2644 DP_LINK_SCRAMBLING_DISABLE)) { 2645 DRM_ERROR("failed to start channel equalization\n"); 2646 return; 2647 } 2648 2649 tries = 0; 2650 cr_tries = 0; 2651 channel_eq = false; 2652 for (;;) { 2653 uint8_t link_status[DP_LINK_STATUS_SIZE]; 2654 2655 if (cr_tries > 5) { 2656 DRM_ERROR("failed to train DP, aborting\n"); 2657 break; 2658 } 2659 2660 drm_dp_link_train_channel_eq_delay(intel_dp->dpcd); 2661 if (!intel_dp_get_link_status(intel_dp, link_status)) { 2662 DRM_ERROR("failed to get link status\n"); 2663 break; 2664 } 2665 2666 /* Make sure clock is still ok */ 2667 if (!drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) { 2668 intel_dp_start_link_train(intel_dp); 2669 intel_dp_set_link_train(intel_dp, &DP, 2670 training_pattern | 2671 DP_LINK_SCRAMBLING_DISABLE); 2672 cr_tries++; 2673 continue; 2674 } 2675 2676 if (drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) { 2677 channel_eq = true; 2678 break; 2679 } 2680 2681 /* Try 5 times, then try clock recovery if that fails */ 2682 if (tries > 5) { 2683 intel_dp_link_down(intel_dp); 2684 intel_dp_start_link_train(intel_dp); 2685 intel_dp_set_link_train(intel_dp, &DP, 2686 training_pattern | 2687 DP_LINK_SCRAMBLING_DISABLE); 2688 tries = 0; 2689 cr_tries++; 2690 continue; 2691 } 2692 2693 /* Update training set as requested by target */ 2694 if (!intel_dp_update_link_train(intel_dp, &DP, link_status)) { 2695 DRM_ERROR("failed to update link training\n"); 2696 break; 2697 } 2698 ++tries; 2699 } 2700 2701 intel_dp_set_idle_link_train(intel_dp); 2702 2703 intel_dp->DP = DP; 2704 2705 if (channel_eq) 2706 DRM_DEBUG_KMS("Channel EQ done. DP Training successful\n"); 2707 2708} 2709 2710void intel_dp_stop_link_train(struct intel_dp *intel_dp) 2711{ 2712 intel_dp_set_link_train(intel_dp, &intel_dp->DP, 2713 DP_TRAINING_PATTERN_DISABLE); 2714} 2715 2716static void 2717intel_dp_link_down(struct intel_dp *intel_dp) 2718{ 2719 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 2720 enum port port = intel_dig_port->port; 2721 struct drm_device *dev = intel_dig_port->base.base.dev; 2722 struct drm_i915_private *dev_priv = dev->dev_private; 2723 struct intel_crtc *intel_crtc = 2724 to_intel_crtc(intel_dig_port->base.base.crtc); 2725 uint32_t DP = intel_dp->DP; 2726 2727 /* 2728 * DDI code has a strict mode set sequence and we should try to respect 2729 * it, otherwise we might hang the machine in many different ways. So we 2730 * really should be disabling the port only on a complete crtc_disable 2731 * sequence. This function is just called under two conditions on DDI 2732 * code: 2733 * - Link train failed while doing crtc_enable, and on this case we 2734 * really should respect the mode set sequence and wait for a 2735 * crtc_disable. 2736 * - Someone turned the monitor off and intel_dp_check_link_status 2737 * called us. We don't need to disable the whole port on this case, so 2738 * when someone turns the monitor on again, 2739 * intel_ddi_prepare_link_retrain will take care of redoing the link 2740 * train. 2741 */ 2742 if (HAS_DDI(dev)) 2743 return; 2744 2745 if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0)) 2746 return; 2747 2748 DRM_DEBUG_KMS("\n"); 2749 2750 if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) { 2751 DP &= ~DP_LINK_TRAIN_MASK_CPT; 2752 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT); 2753 } else { 2754 DP &= ~DP_LINK_TRAIN_MASK; 2755 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE); 2756 } 2757 POSTING_READ(intel_dp->output_reg); 2758 2759 /* We don't really know why we're doing this */ 2760 intel_wait_for_vblank(dev, intel_crtc->pipe); 2761 2762 if (HAS_PCH_IBX(dev) && 2763 I915_READ(intel_dp->output_reg) & DP_PIPEB_SELECT) { 2764 struct drm_crtc *crtc = intel_dig_port->base.base.crtc; 2765 2766 /* Hardware workaround: leaving our transcoder select 2767 * set to transcoder B while it's off will prevent the 2768 * corresponding HDMI output on transcoder A. 2769 * 2770 * Combine this with another hardware workaround: 2771 * transcoder select bit can only be cleared while the 2772 * port is enabled. 2773 */ 2774 DP &= ~DP_PIPEB_SELECT; 2775 I915_WRITE(intel_dp->output_reg, DP); 2776 2777 /* Changes to enable or select take place the vblank 2778 * after being written. 2779 */ 2780 if (WARN_ON(crtc == NULL)) { 2781 /* We should never try to disable a port without a crtc 2782 * attached. For paranoia keep the code around for a 2783 * bit. */ 2784 POSTING_READ(intel_dp->output_reg); 2785 msleep(50); 2786 } else 2787 intel_wait_for_vblank(dev, intel_crtc->pipe); 2788 } 2789 2790 DP &= ~DP_AUDIO_OUTPUT_ENABLE; 2791 I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN); 2792 POSTING_READ(intel_dp->output_reg); 2793 msleep(intel_dp->panel_power_down_delay); 2794} 2795 2796static bool 2797intel_dp_get_dpcd(struct intel_dp *intel_dp) 2798{ 2799 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 2800 struct drm_device *dev = dig_port->base.base.dev; 2801 struct drm_i915_private *dev_priv = dev->dev_private; 2802 2803 char dpcd_hex_dump[sizeof(intel_dp->dpcd) * 3]; 2804 2805 if (intel_dp_dpcd_read_wake(&intel_dp->aux, 0x000, intel_dp->dpcd, 2806 sizeof(intel_dp->dpcd)) < 0) 2807 return false; /* aux transfer failed */ 2808 2809 hex_dump_to_buffer(intel_dp->dpcd, sizeof(intel_dp->dpcd), 2810 32, 1, dpcd_hex_dump, sizeof(dpcd_hex_dump), false); 2811 DRM_DEBUG_KMS("DPCD: %s\n", dpcd_hex_dump); 2812 2813 if (intel_dp->dpcd[DP_DPCD_REV] == 0) 2814 return false; /* DPCD not present */ 2815 2816 /* Check if the panel supports PSR */ 2817 memset(intel_dp->psr_dpcd, 0, sizeof(intel_dp->psr_dpcd)); 2818 if (is_edp(intel_dp)) { 2819 intel_dp_dpcd_read_wake(&intel_dp->aux, DP_PSR_SUPPORT, 2820 intel_dp->psr_dpcd, 2821 sizeof(intel_dp->psr_dpcd)); 2822 if (intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED) { 2823 dev_priv->psr.sink_support = true; 2824 DRM_DEBUG_KMS("Detected EDP PSR Panel.\n"); 2825 } 2826 } 2827 2828 /* Training Pattern 3 support */ 2829 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x12 && 2830 intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_TPS3_SUPPORTED) { 2831 intel_dp->use_tps3 = true; 2832 DRM_DEBUG_KMS("Displayport TPS3 supported"); 2833 } else 2834 intel_dp->use_tps3 = false; 2835 2836 if (!(intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] & 2837 DP_DWN_STRM_PORT_PRESENT)) 2838 return true; /* native DP sink */ 2839 2840 if (intel_dp->dpcd[DP_DPCD_REV] == 0x10) 2841 return true; /* no per-port downstream info */ 2842 2843 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_DOWNSTREAM_PORT_0, 2844 intel_dp->downstream_ports, 2845 DP_MAX_DOWNSTREAM_PORTS) < 0) 2846 return false; /* downstream port status fetch failed */ 2847 2848 return true; 2849} 2850 2851static void 2852intel_dp_probe_oui(struct intel_dp *intel_dp) 2853{ 2854 u8 buf[3]; 2855 2856 if (!(intel_dp->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT)) 2857 return; 2858 2859 intel_edp_panel_vdd_on(intel_dp); 2860 2861 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_SINK_OUI, buf, 3) == 3) 2862 DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n", 2863 buf[0], buf[1], buf[2]); 2864 2865 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_BRANCH_OUI, buf, 3) == 3) 2866 DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n", 2867 buf[0], buf[1], buf[2]); 2868 2869 edp_panel_vdd_off(intel_dp, false); 2870} 2871 2872int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc) 2873{ 2874 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 2875 struct drm_device *dev = intel_dig_port->base.base.dev; 2876 struct intel_crtc *intel_crtc = 2877 to_intel_crtc(intel_dig_port->base.base.crtc); 2878 u8 buf[1]; 2879 2880 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK_MISC, buf) < 0) 2881 return -EAGAIN; 2882 2883 if (!(buf[0] & DP_TEST_CRC_SUPPORTED)) 2884 return -ENOTTY; 2885 2886 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK, 2887 DP_TEST_SINK_START) < 0) 2888 return -EAGAIN; 2889 2890 /* Wait 2 vblanks to be sure we will have the correct CRC value */ 2891 intel_wait_for_vblank(dev, intel_crtc->pipe); 2892 intel_wait_for_vblank(dev, intel_crtc->pipe); 2893 2894 if (drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_CRC_R_CR, crc, 6) < 0) 2895 return -EAGAIN; 2896 2897 drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK, 0); 2898 return 0; 2899} 2900 2901static bool 2902intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector) 2903{ 2904 return intel_dp_dpcd_read_wake(&intel_dp->aux, 2905 DP_DEVICE_SERVICE_IRQ_VECTOR, 2906 sink_irq_vector, 1) == 1; 2907} 2908 2909static void 2910intel_dp_handle_test_request(struct intel_dp *intel_dp) 2911{ 2912 /* NAK by default */ 2913 drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_RESPONSE, DP_TEST_NAK); 2914} 2915 2916/* 2917 * According to DP spec 2918 * 5.1.2: 2919 * 1. Read DPCD 2920 * 2. Configure link according to Receiver Capabilities 2921 * 3. Use Link Training from 2.5.3.3 and 3.5.1.3 2922 * 4. Check link status on receipt of hot-plug interrupt 2923 */ 2924 2925void 2926intel_dp_check_link_status(struct intel_dp *intel_dp) 2927{ 2928 struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base; 2929 u8 sink_irq_vector; 2930 u8 link_status[DP_LINK_STATUS_SIZE]; 2931 2932 if (!intel_encoder->connectors_active) 2933 return; 2934 2935 if (WARN_ON(!intel_encoder->base.crtc)) 2936 return; 2937 2938 /* Try to read receiver status if the link appears to be up */ 2939 if (!intel_dp_get_link_status(intel_dp, link_status)) { 2940 return; 2941 } 2942 2943 /* Now read the DPCD to see if it's actually running */ 2944 if (!intel_dp_get_dpcd(intel_dp)) { 2945 return; 2946 } 2947 2948 /* Try to read the source of the interrupt */ 2949 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 && 2950 intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) { 2951 /* Clear interrupt source */ 2952 drm_dp_dpcd_writeb(&intel_dp->aux, 2953 DP_DEVICE_SERVICE_IRQ_VECTOR, 2954 sink_irq_vector); 2955 2956 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST) 2957 intel_dp_handle_test_request(intel_dp); 2958 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ)) 2959 DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n"); 2960 } 2961 2962 if (!drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) { 2963 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n", 2964 drm_get_encoder_name(&intel_encoder->base)); 2965 intel_dp_start_link_train(intel_dp); 2966 intel_dp_complete_link_train(intel_dp); 2967 intel_dp_stop_link_train(intel_dp); 2968 } 2969} 2970 2971/* XXX this is probably wrong for multiple downstream ports */ 2972static enum drm_connector_status 2973intel_dp_detect_dpcd(struct intel_dp *intel_dp) 2974{ 2975 uint8_t *dpcd = intel_dp->dpcd; 2976 uint8_t type; 2977 2978 if (!intel_dp_get_dpcd(intel_dp)) 2979 return connector_status_disconnected; 2980 2981 /* if there's no downstream port, we're done */ 2982 if (!(dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT)) 2983 return connector_status_connected; 2984 2985 /* If we're HPD-aware, SINK_COUNT changes dynamically */ 2986 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 && 2987 intel_dp->downstream_ports[0] & DP_DS_PORT_HPD) { 2988 uint8_t reg; 2989 2990 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_SINK_COUNT, 2991 ®, 1) < 0) 2992 return connector_status_unknown; 2993 2994 return DP_GET_SINK_COUNT(reg) ? connector_status_connected 2995 : connector_status_disconnected; 2996 } 2997 2998 /* If no HPD, poke DDC gently */ 2999 if (drm_probe_ddc(&intel_dp->aux.ddc)) 3000 return connector_status_connected; 3001 3002 /* Well we tried, say unknown for unreliable port types */ 3003 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) { 3004 type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK; 3005 if (type == DP_DS_PORT_TYPE_VGA || 3006 type == DP_DS_PORT_TYPE_NON_EDID) 3007 return connector_status_unknown; 3008 } else { 3009 type = intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] & 3010 DP_DWN_STRM_PORT_TYPE_MASK; 3011 if (type == DP_DWN_STRM_PORT_TYPE_ANALOG || 3012 type == DP_DWN_STRM_PORT_TYPE_OTHER) 3013 return connector_status_unknown; 3014 } 3015 3016 /* Anything else is out of spec, warn and ignore */ 3017 DRM_DEBUG_KMS("Broken DP branch device, ignoring\n"); 3018 return connector_status_disconnected; 3019} 3020 3021static enum drm_connector_status 3022ironlake_dp_detect(struct intel_dp *intel_dp) 3023{ 3024 struct drm_device *dev = intel_dp_to_dev(intel_dp); 3025 struct drm_i915_private *dev_priv = dev->dev_private; 3026 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 3027 enum drm_connector_status status; 3028 3029 /* Can't disconnect eDP, but you can close the lid... */ 3030 if (is_edp(intel_dp)) { 3031 status = intel_panel_detect(dev); 3032 if (status == connector_status_unknown) 3033 status = connector_status_connected; 3034 return status; 3035 } 3036 3037 if (!ibx_digital_port_connected(dev_priv, intel_dig_port)) 3038 return connector_status_disconnected; 3039 3040 return intel_dp_detect_dpcd(intel_dp); 3041} 3042 3043static enum drm_connector_status 3044g4x_dp_detect(struct intel_dp *intel_dp) 3045{ 3046 struct drm_device *dev = intel_dp_to_dev(intel_dp); 3047 struct drm_i915_private *dev_priv = dev->dev_private; 3048 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 3049 uint32_t bit; 3050 3051 /* Can't disconnect eDP, but you can close the lid... */ 3052 if (is_edp(intel_dp)) { 3053 enum drm_connector_status status; 3054 3055 status = intel_panel_detect(dev); 3056 if (status == connector_status_unknown) 3057 status = connector_status_connected; 3058 return status; 3059 } 3060 3061 if (IS_VALLEYVIEW(dev)) { 3062 switch (intel_dig_port->port) { 3063 case PORT_B: 3064 bit = PORTB_HOTPLUG_LIVE_STATUS_VLV; 3065 break; 3066 case PORT_C: 3067 bit = PORTC_HOTPLUG_LIVE_STATUS_VLV; 3068 break; 3069 case PORT_D: 3070 bit = PORTD_HOTPLUG_LIVE_STATUS_VLV; 3071 break; 3072 default: 3073 return connector_status_unknown; 3074 } 3075 } else { 3076 switch (intel_dig_port->port) { 3077 case PORT_B: 3078 bit = PORTB_HOTPLUG_LIVE_STATUS_G4X; 3079 break; 3080 case PORT_C: 3081 bit = PORTC_HOTPLUG_LIVE_STATUS_G4X; 3082 break; 3083 case PORT_D: 3084 bit = PORTD_HOTPLUG_LIVE_STATUS_G4X; 3085 break; 3086 default: 3087 return connector_status_unknown; 3088 } 3089 } 3090 3091 if ((I915_READ(PORT_HOTPLUG_STAT) & bit) == 0) 3092 return connector_status_disconnected; 3093 3094 return intel_dp_detect_dpcd(intel_dp); 3095} 3096 3097static struct edid * 3098intel_dp_get_edid(struct drm_connector *connector, struct i2c_adapter *adapter) 3099{ 3100 struct intel_connector *intel_connector = to_intel_connector(connector); 3101 3102 /* use cached edid if we have one */ 3103 if (intel_connector->edid) { 3104 /* invalid edid */ 3105 if (IS_ERR(intel_connector->edid)) 3106 return NULL; 3107 3108 return drm_edid_duplicate(intel_connector->edid); 3109 } 3110 3111 return drm_get_edid(connector, adapter); 3112} 3113 3114static int 3115intel_dp_get_edid_modes(struct drm_connector *connector, struct i2c_adapter *adapter) 3116{ 3117 struct intel_connector *intel_connector = to_intel_connector(connector); 3118 3119 /* use cached edid if we have one */ 3120 if (intel_connector->edid) { 3121 /* invalid edid */ 3122 if (IS_ERR(intel_connector->edid)) 3123 return 0; 3124 3125 return intel_connector_update_modes(connector, 3126 intel_connector->edid); 3127 } 3128 3129 return intel_ddc_get_modes(connector, adapter); 3130} 3131 3132static enum drm_connector_status 3133intel_dp_detect(struct drm_connector *connector, bool force) 3134{ 3135 struct intel_dp *intel_dp = intel_attached_dp(connector); 3136 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 3137 struct intel_encoder *intel_encoder = &intel_dig_port->base; 3138 struct drm_device *dev = connector->dev; 3139 struct drm_i915_private *dev_priv = dev->dev_private; 3140 enum drm_connector_status status; 3141 enum intel_display_power_domain power_domain; 3142 struct edid *edid = NULL; 3143 3144 intel_runtime_pm_get(dev_priv); 3145 3146 power_domain = intel_display_port_power_domain(intel_encoder); 3147 intel_display_power_get(dev_priv, power_domain); 3148 3149 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", 3150 connector->base.id, drm_get_connector_name(connector)); 3151 3152 intel_dp->has_audio = false; 3153 3154 if (HAS_PCH_SPLIT(dev)) 3155 status = ironlake_dp_detect(intel_dp); 3156 else 3157 status = g4x_dp_detect(intel_dp); 3158 3159 if (status != connector_status_connected) 3160 goto out; 3161 3162 intel_dp_probe_oui(intel_dp); 3163 3164 if (intel_dp->force_audio != HDMI_AUDIO_AUTO) { 3165 intel_dp->has_audio = (intel_dp->force_audio == HDMI_AUDIO_ON); 3166 } else { 3167 edid = intel_dp_get_edid(connector, &intel_dp->aux.ddc); 3168 if (edid) { 3169 intel_dp->has_audio = drm_detect_monitor_audio(edid); 3170 kfree(edid); 3171 } 3172 } 3173 3174 if (intel_encoder->type != INTEL_OUTPUT_EDP) 3175 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT; 3176 status = connector_status_connected; 3177 3178out: 3179 intel_display_power_put(dev_priv, power_domain); 3180 3181 intel_runtime_pm_put(dev_priv); 3182 3183 return status; 3184} 3185 3186static int intel_dp_get_modes(struct drm_connector *connector) 3187{ 3188 struct intel_dp *intel_dp = intel_attached_dp(connector); 3189 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 3190 struct intel_encoder *intel_encoder = &intel_dig_port->base; 3191 struct intel_connector *intel_connector = to_intel_connector(connector); 3192 struct drm_device *dev = connector->dev; 3193 struct drm_i915_private *dev_priv = dev->dev_private; 3194 enum intel_display_power_domain power_domain; 3195 int ret; 3196 3197 /* We should parse the EDID data and find out if it has an audio sink 3198 */ 3199 3200 power_domain = intel_display_port_power_domain(intel_encoder); 3201 intel_display_power_get(dev_priv, power_domain); 3202 3203 ret = intel_dp_get_edid_modes(connector, &intel_dp->aux.ddc); 3204 intel_display_power_put(dev_priv, power_domain); 3205 if (ret) 3206 return ret; 3207 3208 /* if eDP has no EDID, fall back to fixed mode */ 3209 if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) { 3210 struct drm_display_mode *mode; 3211 mode = drm_mode_duplicate(dev, 3212 intel_connector->panel.fixed_mode); 3213 if (mode) { 3214 drm_mode_probed_add(connector, mode); 3215 return 1; 3216 } 3217 } 3218 return 0; 3219} 3220 3221static bool 3222intel_dp_detect_audio(struct drm_connector *connector) 3223{ 3224 struct intel_dp *intel_dp = intel_attached_dp(connector); 3225 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 3226 struct intel_encoder *intel_encoder = &intel_dig_port->base; 3227 struct drm_device *dev = connector->dev; 3228 struct drm_i915_private *dev_priv = dev->dev_private; 3229 enum intel_display_power_domain power_domain; 3230 struct edid *edid; 3231 bool has_audio = false; 3232 3233 power_domain = intel_display_port_power_domain(intel_encoder); 3234 intel_display_power_get(dev_priv, power_domain); 3235 3236 edid = intel_dp_get_edid(connector, &intel_dp->aux.ddc); 3237 if (edid) { 3238 has_audio = drm_detect_monitor_audio(edid); 3239 kfree(edid); 3240 } 3241 3242 intel_display_power_put(dev_priv, power_domain); 3243 3244 return has_audio; 3245} 3246 3247static int 3248intel_dp_set_property(struct drm_connector *connector, 3249 struct drm_property *property, 3250 uint64_t val) 3251{ 3252 struct drm_i915_private *dev_priv = connector->dev->dev_private; 3253 struct intel_connector *intel_connector = to_intel_connector(connector); 3254 struct intel_encoder *intel_encoder = intel_attached_encoder(connector); 3255 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base); 3256 int ret; 3257 3258 ret = drm_object_property_set_value(&connector->base, property, val); 3259 if (ret) 3260 return ret; 3261 3262 if (property == dev_priv->force_audio_property) { 3263 int i = val; 3264 bool has_audio; 3265 3266 if (i == intel_dp->force_audio) 3267 return 0; 3268 3269 intel_dp->force_audio = i; 3270 3271 if (i == HDMI_AUDIO_AUTO) 3272 has_audio = intel_dp_detect_audio(connector); 3273 else 3274 has_audio = (i == HDMI_AUDIO_ON); 3275 3276 if (has_audio == intel_dp->has_audio) 3277 return 0; 3278 3279 intel_dp->has_audio = has_audio; 3280 goto done; 3281 } 3282 3283 if (property == dev_priv->broadcast_rgb_property) { 3284 bool old_auto = intel_dp->color_range_auto; 3285 uint32_t old_range = intel_dp->color_range; 3286 3287 switch (val) { 3288 case INTEL_BROADCAST_RGB_AUTO: 3289 intel_dp->color_range_auto = true; 3290 break; 3291 case INTEL_BROADCAST_RGB_FULL: 3292 intel_dp->color_range_auto = false; 3293 intel_dp->color_range = 0; 3294 break; 3295 case INTEL_BROADCAST_RGB_LIMITED: 3296 intel_dp->color_range_auto = false; 3297 intel_dp->color_range = DP_COLOR_RANGE_16_235; 3298 break; 3299 default: 3300 return -EINVAL; 3301 } 3302 3303 if (old_auto == intel_dp->color_range_auto && 3304 old_range == intel_dp->color_range) 3305 return 0; 3306 3307 goto done; 3308 } 3309 3310 if (is_edp(intel_dp) && 3311 property == connector->dev->mode_config.scaling_mode_property) { 3312 if (val == DRM_MODE_SCALE_NONE) { 3313 DRM_DEBUG_KMS("no scaling not supported\n"); 3314 return -EINVAL; 3315 } 3316 3317 if (intel_connector->panel.fitting_mode == val) { 3318 /* the eDP scaling property is not changed */ 3319 return 0; 3320 } 3321 intel_connector->panel.fitting_mode = val; 3322 3323 goto done; 3324 } 3325 3326 return -EINVAL; 3327 3328done: 3329 if (intel_encoder->base.crtc) 3330 intel_crtc_restore_mode(intel_encoder->base.crtc); 3331 3332 return 0; 3333} 3334 3335static void 3336intel_dp_connector_destroy(struct drm_connector *connector) 3337{ 3338 struct intel_connector *intel_connector = to_intel_connector(connector); 3339 3340 if (!IS_ERR_OR_NULL(intel_connector->edid)) 3341 kfree(intel_connector->edid); 3342 3343 /* Can't call is_edp() since the encoder may have been destroyed 3344 * already. */ 3345 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) 3346 intel_panel_fini(&intel_connector->panel); 3347 3348 drm_connector_cleanup(connector); 3349 kfree(connector); 3350} 3351 3352void intel_dp_encoder_destroy(struct drm_encoder *encoder) 3353{ 3354 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); 3355 struct intel_dp *intel_dp = &intel_dig_port->dp; 3356 struct drm_device *dev = intel_dp_to_dev(intel_dp); 3357 3358 drm_dp_aux_unregister_i2c_bus(&intel_dp->aux); 3359 drm_encoder_cleanup(encoder); 3360 if (is_edp(intel_dp)) { 3361 cancel_delayed_work_sync(&intel_dp->panel_vdd_work); 3362 mutex_lock(&dev->mode_config.mutex); 3363 edp_panel_vdd_off_sync(intel_dp); 3364 mutex_unlock(&dev->mode_config.mutex); 3365 } 3366 kfree(intel_dig_port); 3367} 3368 3369static const struct drm_connector_funcs intel_dp_connector_funcs = { 3370 .dpms = intel_connector_dpms, 3371 .detect = intel_dp_detect, 3372 .fill_modes = drm_helper_probe_single_connector_modes, 3373 .set_property = intel_dp_set_property, 3374 .destroy = intel_dp_connector_destroy, 3375}; 3376 3377static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = { 3378 .get_modes = intel_dp_get_modes, 3379 .mode_valid = intel_dp_mode_valid, 3380 .best_encoder = intel_best_encoder, 3381}; 3382 3383static const struct drm_encoder_funcs intel_dp_enc_funcs = { 3384 .destroy = intel_dp_encoder_destroy, 3385}; 3386 3387static void 3388intel_dp_hot_plug(struct intel_encoder *intel_encoder) 3389{ 3390 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base); 3391 3392 intel_dp_check_link_status(intel_dp); 3393} 3394 3395/* Return which DP Port should be selected for Transcoder DP control */ 3396int 3397intel_trans_dp_port_sel(struct drm_crtc *crtc) 3398{ 3399 struct drm_device *dev = crtc->dev; 3400 struct intel_encoder *intel_encoder; 3401 struct intel_dp *intel_dp; 3402 3403 for_each_encoder_on_crtc(dev, crtc, intel_encoder) { 3404 intel_dp = enc_to_intel_dp(&intel_encoder->base); 3405 3406 if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT || 3407 intel_encoder->type == INTEL_OUTPUT_EDP) 3408 return intel_dp->output_reg; 3409 } 3410 3411 return -1; 3412} 3413 3414/* check the VBT to see whether the eDP is on DP-D port */ 3415bool intel_dp_is_edp(struct drm_device *dev, enum port port) 3416{ 3417 struct drm_i915_private *dev_priv = dev->dev_private; 3418 union child_device_config *p_child; 3419 int i; 3420 static const short port_mapping[] = { 3421 [PORT_B] = PORT_IDPB, 3422 [PORT_C] = PORT_IDPC, 3423 [PORT_D] = PORT_IDPD, 3424 }; 3425 3426 if (port == PORT_A) 3427 return true; 3428 3429 if (!dev_priv->vbt.child_dev_num) 3430 return false; 3431 3432 for (i = 0; i < dev_priv->vbt.child_dev_num; i++) { 3433 p_child = dev_priv->vbt.child_dev + i; 3434 3435 if (p_child->common.dvo_port == port_mapping[port] && 3436 (p_child->common.device_type & DEVICE_TYPE_eDP_BITS) == 3437 (DEVICE_TYPE_eDP & DEVICE_TYPE_eDP_BITS)) 3438 return true; 3439 } 3440 return false; 3441} 3442 3443static void 3444intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector) 3445{ 3446 struct intel_connector *intel_connector = to_intel_connector(connector); 3447 3448 intel_attach_force_audio_property(connector); 3449 intel_attach_broadcast_rgb_property(connector); 3450 intel_dp->color_range_auto = true; 3451 3452 if (is_edp(intel_dp)) { 3453 drm_mode_create_scaling_mode_property(connector->dev); 3454 drm_object_attach_property( 3455 &connector->base, 3456 connector->dev->mode_config.scaling_mode_property, 3457 DRM_MODE_SCALE_ASPECT); 3458 intel_connector->panel.fitting_mode = DRM_MODE_SCALE_ASPECT; 3459 } 3460} 3461 3462static void intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp) 3463{ 3464 intel_dp->last_power_cycle = jiffies; 3465 intel_dp->last_power_on = jiffies; 3466 intel_dp->last_backlight_off = jiffies; 3467} 3468 3469static void 3470intel_dp_init_panel_power_sequencer(struct drm_device *dev, 3471 struct intel_dp *intel_dp, 3472 struct edp_power_seq *out) 3473{ 3474 struct drm_i915_private *dev_priv = dev->dev_private; 3475 struct edp_power_seq cur, vbt, spec, final; 3476 u32 pp_on, pp_off, pp_div, pp; 3477 int pp_ctrl_reg, pp_on_reg, pp_off_reg, pp_div_reg; 3478 3479 if (HAS_PCH_SPLIT(dev)) { 3480 pp_ctrl_reg = PCH_PP_CONTROL; 3481 pp_on_reg = PCH_PP_ON_DELAYS; 3482 pp_off_reg = PCH_PP_OFF_DELAYS; 3483 pp_div_reg = PCH_PP_DIVISOR; 3484 } else { 3485 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp); 3486 3487 pp_ctrl_reg = VLV_PIPE_PP_CONTROL(pipe); 3488 pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe); 3489 pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe); 3490 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe); 3491 } 3492 3493 /* Workaround: Need to write PP_CONTROL with the unlock key as 3494 * the very first thing. */ 3495 pp = ironlake_get_pp_control(intel_dp); 3496 I915_WRITE(pp_ctrl_reg, pp); 3497 3498 pp_on = I915_READ(pp_on_reg); 3499 pp_off = I915_READ(pp_off_reg); 3500 pp_div = I915_READ(pp_div_reg); 3501 3502 /* Pull timing values out of registers */ 3503 cur.t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >> 3504 PANEL_POWER_UP_DELAY_SHIFT; 3505 3506 cur.t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >> 3507 PANEL_LIGHT_ON_DELAY_SHIFT; 3508 3509 cur.t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >> 3510 PANEL_LIGHT_OFF_DELAY_SHIFT; 3511 3512 cur.t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >> 3513 PANEL_POWER_DOWN_DELAY_SHIFT; 3514 3515 cur.t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >> 3516 PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000; 3517 3518 DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n", 3519 cur.t1_t3, cur.t8, cur.t9, cur.t10, cur.t11_t12); 3520 3521 vbt = dev_priv->vbt.edp_pps; 3522 3523 /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of 3524 * our hw here, which are all in 100usec. */ 3525 spec.t1_t3 = 210 * 10; 3526 spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */ 3527 spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */ 3528 spec.t10 = 500 * 10; 3529 /* This one is special and actually in units of 100ms, but zero 3530 * based in the hw (so we need to add 100 ms). But the sw vbt 3531 * table multiplies it with 1000 to make it in units of 100usec, 3532 * too. */ 3533 spec.t11_t12 = (510 + 100) * 10; 3534 3535 DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n", 3536 vbt.t1_t3, vbt.t8, vbt.t9, vbt.t10, vbt.t11_t12); 3537 3538 /* Use the max of the register settings and vbt. If both are 3539 * unset, fall back to the spec limits. */ 3540#define assign_final(field) final.field = (max(cur.field, vbt.field) == 0 ? \ 3541 spec.field : \ 3542 max(cur.field, vbt.field)) 3543 assign_final(t1_t3); 3544 assign_final(t8); 3545 assign_final(t9); 3546 assign_final(t10); 3547 assign_final(t11_t12); 3548#undef assign_final 3549 3550#define get_delay(field) (DIV_ROUND_UP(final.field, 10)) 3551 intel_dp->panel_power_up_delay = get_delay(t1_t3); 3552 intel_dp->backlight_on_delay = get_delay(t8); 3553 intel_dp->backlight_off_delay = get_delay(t9); 3554 intel_dp->panel_power_down_delay = get_delay(t10); 3555 intel_dp->panel_power_cycle_delay = get_delay(t11_t12); 3556#undef get_delay 3557 3558 DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n", 3559 intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay, 3560 intel_dp->panel_power_cycle_delay); 3561 3562 DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n", 3563 intel_dp->backlight_on_delay, intel_dp->backlight_off_delay); 3564 3565 if (out) 3566 *out = final; 3567} 3568 3569static void 3570intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev, 3571 struct intel_dp *intel_dp, 3572 struct edp_power_seq *seq) 3573{ 3574 struct drm_i915_private *dev_priv = dev->dev_private; 3575 u32 pp_on, pp_off, pp_div, port_sel = 0; 3576 int div = HAS_PCH_SPLIT(dev) ? intel_pch_rawclk(dev) : intel_hrawclk(dev); 3577 int pp_on_reg, pp_off_reg, pp_div_reg; 3578 3579 if (HAS_PCH_SPLIT(dev)) { 3580 pp_on_reg = PCH_PP_ON_DELAYS; 3581 pp_off_reg = PCH_PP_OFF_DELAYS; 3582 pp_div_reg = PCH_PP_DIVISOR; 3583 } else { 3584 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp); 3585 3586 pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe); 3587 pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe); 3588 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe); 3589 } 3590 3591 /* 3592 * And finally store the new values in the power sequencer. The 3593 * backlight delays are set to 1 because we do manual waits on them. For 3594 * T8, even BSpec recommends doing it. For T9, if we don't do this, 3595 * we'll end up waiting for the backlight off delay twice: once when we 3596 * do the manual sleep, and once when we disable the panel and wait for 3597 * the PP_STATUS bit to become zero. 3598 */ 3599 pp_on = (seq->t1_t3 << PANEL_POWER_UP_DELAY_SHIFT) | 3600 (1 << PANEL_LIGHT_ON_DELAY_SHIFT); 3601 pp_off = (1 << PANEL_LIGHT_OFF_DELAY_SHIFT) | 3602 (seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT); 3603 /* Compute the divisor for the pp clock, simply match the Bspec 3604 * formula. */ 3605 pp_div = ((100 * div)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT; 3606 pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000) 3607 << PANEL_POWER_CYCLE_DELAY_SHIFT); 3608 3609 /* Haswell doesn't have any port selection bits for the panel 3610 * power sequencer any more. */ 3611 if (IS_VALLEYVIEW(dev)) { 3612 if (dp_to_dig_port(intel_dp)->port == PORT_B) 3613 port_sel = PANEL_PORT_SELECT_DPB_VLV; 3614 else 3615 port_sel = PANEL_PORT_SELECT_DPC_VLV; 3616 } else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) { 3617 if (dp_to_dig_port(intel_dp)->port == PORT_A) 3618 port_sel = PANEL_PORT_SELECT_DPA; 3619 else 3620 port_sel = PANEL_PORT_SELECT_DPD; 3621 } 3622 3623 pp_on |= port_sel; 3624 3625 I915_WRITE(pp_on_reg, pp_on); 3626 I915_WRITE(pp_off_reg, pp_off); 3627 I915_WRITE(pp_div_reg, pp_div); 3628 3629 DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n", 3630 I915_READ(pp_on_reg), 3631 I915_READ(pp_off_reg), 3632 I915_READ(pp_div_reg)); 3633} 3634 3635static struct drm_display_mode * 3636intel_dp_drrs_init(struct intel_digital_port *intel_dig_port, 3637 struct intel_connector *intel_connector, 3638 struct drm_display_mode *fixed_mode) 3639{ 3640 struct drm_connector *connector = &intel_connector->base; 3641 struct intel_dp *intel_dp = &intel_dig_port->dp; 3642 struct drm_device *dev = intel_dig_port->base.base.dev; 3643 struct drm_i915_private *dev_priv = dev->dev_private; 3644 struct drm_display_mode *downclock_mode = NULL; 3645 3646 if (INTEL_INFO(dev)->gen <= 6) { 3647 DRM_DEBUG_KMS("DRRS supported for Gen7 and above\n"); 3648 return NULL; 3649 } 3650 3651 if (dev_priv->vbt.drrs_type != SEAMLESS_DRRS_SUPPORT) { 3652 DRM_INFO("VBT doesn't support DRRS\n"); 3653 return NULL; 3654 } 3655 3656 downclock_mode = intel_find_panel_downclock 3657 (dev, fixed_mode, connector); 3658 3659 if (!downclock_mode) { 3660 DRM_INFO("DRRS not supported\n"); 3661 return NULL; 3662 } 3663 3664 intel_dp->drrs_state.type = dev_priv->vbt.drrs_type; 3665 3666 intel_dp->drrs_state.refresh_rate_type = DRRS_HIGH_RR; 3667 DRM_INFO("seamless DRRS supported for eDP panel.\n"); 3668 return downclock_mode; 3669} 3670 3671static bool intel_edp_init_connector(struct intel_dp *intel_dp, 3672 struct intel_connector *intel_connector, 3673 struct edp_power_seq *power_seq) 3674{ 3675 struct drm_connector *connector = &intel_connector->base; 3676 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 3677 struct drm_device *dev = intel_dig_port->base.base.dev; 3678 struct drm_i915_private *dev_priv = dev->dev_private; 3679 struct drm_display_mode *fixed_mode = NULL; 3680 struct drm_display_mode *downclock_mode = NULL; 3681 bool has_dpcd; 3682 struct drm_display_mode *scan; 3683 struct edid *edid; 3684 3685 intel_dp->drrs_state.type = DRRS_NOT_SUPPORTED; 3686 3687 if (!is_edp(intel_dp)) 3688 return true; 3689 3690 /* Cache DPCD and EDID for edp. */ 3691 intel_edp_panel_vdd_on(intel_dp); 3692 has_dpcd = intel_dp_get_dpcd(intel_dp); 3693 edp_panel_vdd_off(intel_dp, false); 3694 3695 if (has_dpcd) { 3696 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) 3697 dev_priv->no_aux_handshake = 3698 intel_dp->dpcd[DP_MAX_DOWNSPREAD] & 3699 DP_NO_AUX_HANDSHAKE_LINK_TRAINING; 3700 } else { 3701 /* if this fails, presume the device is a ghost */ 3702 DRM_INFO("failed to retrieve link info, disabling eDP\n"); 3703 return false; 3704 } 3705 3706 /* We now know it's not a ghost, init power sequence regs. */ 3707 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp, power_seq); 3708 3709 mutex_lock(&dev->mode_config.mutex); 3710 edid = drm_get_edid(connector, &intel_dp->aux.ddc); 3711 if (edid) { 3712 if (drm_add_edid_modes(connector, edid)) { 3713 drm_mode_connector_update_edid_property(connector, 3714 edid); 3715 drm_edid_to_eld(connector, edid); 3716 } else { 3717 kfree(edid); 3718 edid = ERR_PTR(-EINVAL); 3719 } 3720 } else { 3721 edid = ERR_PTR(-ENOENT); 3722 } 3723 intel_connector->edid = edid; 3724 3725 /* prefer fixed mode from EDID if available */ 3726 list_for_each_entry(scan, &connector->probed_modes, head) { 3727 if ((scan->type & DRM_MODE_TYPE_PREFERRED)) { 3728 fixed_mode = drm_mode_duplicate(dev, scan); 3729 downclock_mode = intel_dp_drrs_init( 3730 intel_dig_port, 3731 intel_connector, fixed_mode); 3732 break; 3733 } 3734 } 3735 3736 /* fallback to VBT if available for eDP */ 3737 if (!fixed_mode && dev_priv->vbt.lfp_lvds_vbt_mode) { 3738 fixed_mode = drm_mode_duplicate(dev, 3739 dev_priv->vbt.lfp_lvds_vbt_mode); 3740 if (fixed_mode) 3741 fixed_mode->type |= DRM_MODE_TYPE_PREFERRED; 3742 } 3743 mutex_unlock(&dev->mode_config.mutex); 3744 3745 intel_panel_init(&intel_connector->panel, fixed_mode, downclock_mode); 3746 intel_panel_setup_backlight(connector); 3747 3748 return true; 3749} 3750 3751bool 3752intel_dp_init_connector(struct intel_digital_port *intel_dig_port, 3753 struct intel_connector *intel_connector) 3754{ 3755 struct drm_connector *connector = &intel_connector->base; 3756 struct intel_dp *intel_dp = &intel_dig_port->dp; 3757 struct intel_encoder *intel_encoder = &intel_dig_port->base; 3758 struct drm_device *dev = intel_encoder->base.dev; 3759 struct drm_i915_private *dev_priv = dev->dev_private; 3760 enum port port = intel_dig_port->port; 3761 struct edp_power_seq power_seq = { 0 }; 3762 int type; 3763 3764 /* intel_dp vfuncs */ 3765 if (IS_VALLEYVIEW(dev)) 3766 intel_dp->get_aux_clock_divider = vlv_get_aux_clock_divider; 3767 else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) 3768 intel_dp->get_aux_clock_divider = hsw_get_aux_clock_divider; 3769 else if (HAS_PCH_SPLIT(dev)) 3770 intel_dp->get_aux_clock_divider = ilk_get_aux_clock_divider; 3771 else 3772 intel_dp->get_aux_clock_divider = i9xx_get_aux_clock_divider; 3773 3774 intel_dp->get_aux_send_ctl = i9xx_get_aux_send_ctl; 3775 3776 /* Preserve the current hw state. */ 3777 intel_dp->DP = I915_READ(intel_dp->output_reg); 3778 intel_dp->attached_connector = intel_connector; 3779 3780 if (intel_dp_is_edp(dev, port)) 3781 type = DRM_MODE_CONNECTOR_eDP; 3782 else 3783 type = DRM_MODE_CONNECTOR_DisplayPort; 3784 3785 /* 3786 * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but 3787 * for DP the encoder type can be set by the caller to 3788 * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it. 3789 */ 3790 if (type == DRM_MODE_CONNECTOR_eDP) 3791 intel_encoder->type = INTEL_OUTPUT_EDP; 3792 3793 DRM_DEBUG_KMS("Adding %s connector on port %c\n", 3794 type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP", 3795 port_name(port)); 3796 3797 drm_connector_init(dev, connector, &intel_dp_connector_funcs, type); 3798 drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs); 3799 3800 connector->interlace_allowed = true; 3801 connector->doublescan_allowed = 0; 3802 3803 INIT_DELAYED_WORK(&intel_dp->panel_vdd_work, 3804 edp_panel_vdd_work); 3805 3806 intel_connector_attach_encoder(intel_connector, intel_encoder); 3807 drm_sysfs_connector_add(connector); 3808 3809 if (HAS_DDI(dev)) 3810 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state; 3811 else 3812 intel_connector->get_hw_state = intel_connector_get_hw_state; 3813 intel_connector->unregister = intel_dp_connector_unregister; 3814 3815 /* Set up the hotplug pin. */ 3816 switch (port) { 3817 case PORT_A: 3818 intel_encoder->hpd_pin = HPD_PORT_A; 3819 break; 3820 case PORT_B: 3821 intel_encoder->hpd_pin = HPD_PORT_B; 3822 break; 3823 case PORT_C: 3824 intel_encoder->hpd_pin = HPD_PORT_C; 3825 break; 3826 case PORT_D: 3827 intel_encoder->hpd_pin = HPD_PORT_D; 3828 break; 3829 default: 3830 BUG(); 3831 } 3832 3833 if (is_edp(intel_dp)) { 3834 intel_dp_init_panel_power_timestamps(intel_dp); 3835 intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq); 3836 } 3837 3838 intel_dp_aux_init(intel_dp, intel_connector); 3839 3840 intel_dp->psr_setup_done = false; 3841 3842 if (!intel_edp_init_connector(intel_dp, intel_connector, &power_seq)) { 3843 drm_dp_aux_unregister_i2c_bus(&intel_dp->aux); 3844 if (is_edp(intel_dp)) { 3845 cancel_delayed_work_sync(&intel_dp->panel_vdd_work); 3846 mutex_lock(&dev->mode_config.mutex); 3847 edp_panel_vdd_off_sync(intel_dp); 3848 mutex_unlock(&dev->mode_config.mutex); 3849 } 3850 drm_sysfs_connector_remove(connector); 3851 drm_connector_cleanup(connector); 3852 return false; 3853 } 3854 3855 intel_dp_add_properties(intel_dp, connector); 3856 3857 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written 3858 * 0xd. Failure to do so will result in spurious interrupts being 3859 * generated on the port when a cable is not attached. 3860 */ 3861 if (IS_G4X(dev) && !IS_GM45(dev)) { 3862 u32 temp = I915_READ(PEG_BAND_GAP_DATA); 3863 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd); 3864 } 3865 3866 return true; 3867} 3868 3869void 3870intel_dp_init(struct drm_device *dev, int output_reg, enum port port) 3871{ 3872 struct intel_digital_port *intel_dig_port; 3873 struct intel_encoder *intel_encoder; 3874 struct drm_encoder *encoder; 3875 struct intel_connector *intel_connector; 3876 3877 intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL); 3878 if (!intel_dig_port) 3879 return; 3880 3881 intel_connector = kzalloc(sizeof(*intel_connector), GFP_KERNEL); 3882 if (!intel_connector) { 3883 kfree(intel_dig_port); 3884 return; 3885 } 3886 3887 intel_encoder = &intel_dig_port->base; 3888 encoder = &intel_encoder->base; 3889 3890 drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs, 3891 DRM_MODE_ENCODER_TMDS); 3892 3893 intel_encoder->compute_config = intel_dp_compute_config; 3894 intel_encoder->mode_set = intel_dp_mode_set; 3895 intel_encoder->disable = intel_disable_dp; 3896 intel_encoder->get_hw_state = intel_dp_get_hw_state; 3897 intel_encoder->get_config = intel_dp_get_config; 3898 if (IS_VALLEYVIEW(dev)) { 3899 intel_encoder->pre_pll_enable = vlv_dp_pre_pll_enable; 3900 intel_encoder->pre_enable = vlv_pre_enable_dp; 3901 intel_encoder->enable = vlv_enable_dp; 3902 intel_encoder->post_disable = vlv_post_disable_dp; 3903 } else { 3904 intel_encoder->pre_enable = g4x_pre_enable_dp; 3905 intel_encoder->enable = g4x_enable_dp; 3906 intel_encoder->post_disable = g4x_post_disable_dp; 3907 } 3908 3909 intel_dig_port->port = port; 3910 intel_dig_port->dp.output_reg = output_reg; 3911 3912 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT; 3913 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2); 3914 intel_encoder->cloneable = 0; 3915 intel_encoder->hot_plug = intel_dp_hot_plug; 3916 3917 if (!intel_dp_init_connector(intel_dig_port, intel_connector)) { 3918 drm_encoder_cleanup(encoder); 3919 kfree(intel_dig_port); 3920 kfree(intel_connector); 3921 } 3922} 3923