intel_dp.c revision 6b27f7f0e97b2819f5e272ffc2dda24881caebd6
1/* 2 * Copyright © 2008 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 * Authors: 24 * Keith Packard <keithp@keithp.com> 25 * 26 */ 27 28#include <linux/i2c.h> 29#include <linux/slab.h> 30#include <linux/export.h> 31#include <drm/drmP.h> 32#include <drm/drm_crtc.h> 33#include <drm/drm_crtc_helper.h> 34#include <drm/drm_edid.h> 35#include "intel_drv.h" 36#include <drm/i915_drm.h> 37#include "i915_drv.h" 38 39#define DP_LINK_CHECK_TIMEOUT (10 * 1000) 40 41struct dp_link_dpll { 42 int link_bw; 43 struct dpll dpll; 44}; 45 46static const struct dp_link_dpll gen4_dpll[] = { 47 { DP_LINK_BW_1_62, 48 { .p1 = 2, .p2 = 10, .n = 2, .m1 = 23, .m2 = 8 } }, 49 { DP_LINK_BW_2_7, 50 { .p1 = 1, .p2 = 10, .n = 1, .m1 = 14, .m2 = 2 } } 51}; 52 53static const struct dp_link_dpll pch_dpll[] = { 54 { DP_LINK_BW_1_62, 55 { .p1 = 2, .p2 = 10, .n = 1, .m1 = 12, .m2 = 9 } }, 56 { DP_LINK_BW_2_7, 57 { .p1 = 1, .p2 = 10, .n = 2, .m1 = 14, .m2 = 8 } } 58}; 59 60static const struct dp_link_dpll vlv_dpll[] = { 61 { DP_LINK_BW_1_62, 62 { .p1 = 3, .p2 = 2, .n = 5, .m1 = 3, .m2 = 81 } }, 63 { DP_LINK_BW_2_7, 64 { .p1 = 2, .p2 = 2, .n = 1, .m1 = 2, .m2 = 27 } } 65}; 66 67/** 68 * is_edp - is the given port attached to an eDP panel (either CPU or PCH) 69 * @intel_dp: DP struct 70 * 71 * If a CPU or PCH DP output is attached to an eDP panel, this function 72 * will return true, and false otherwise. 73 */ 74static bool is_edp(struct intel_dp *intel_dp) 75{ 76 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 77 78 return intel_dig_port->base.type == INTEL_OUTPUT_EDP; 79} 80 81static struct drm_device *intel_dp_to_dev(struct intel_dp *intel_dp) 82{ 83 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 84 85 return intel_dig_port->base.base.dev; 86} 87 88static struct intel_dp *intel_attached_dp(struct drm_connector *connector) 89{ 90 return enc_to_intel_dp(&intel_attached_encoder(connector)->base); 91} 92 93static void intel_dp_link_down(struct intel_dp *intel_dp); 94 95static int 96intel_dp_max_link_bw(struct intel_dp *intel_dp) 97{ 98 int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE]; 99 100 switch (max_link_bw) { 101 case DP_LINK_BW_1_62: 102 case DP_LINK_BW_2_7: 103 break; 104 case DP_LINK_BW_5_4: /* 1.2 capable displays may advertise higher bw */ 105 max_link_bw = DP_LINK_BW_2_7; 106 break; 107 default: 108 WARN(1, "invalid max DP link bw val %x, using 1.62Gbps\n", 109 max_link_bw); 110 max_link_bw = DP_LINK_BW_1_62; 111 break; 112 } 113 return max_link_bw; 114} 115 116/* 117 * The units on the numbers in the next two are... bizarre. Examples will 118 * make it clearer; this one parallels an example in the eDP spec. 119 * 120 * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as: 121 * 122 * 270000 * 1 * 8 / 10 == 216000 123 * 124 * The actual data capacity of that configuration is 2.16Gbit/s, so the 125 * units are decakilobits. ->clock in a drm_display_mode is in kilohertz - 126 * or equivalently, kilopixels per second - so for 1680x1050R it'd be 127 * 119000. At 18bpp that's 2142000 kilobits per second. 128 * 129 * Thus the strange-looking division by 10 in intel_dp_link_required, to 130 * get the result in decakilobits instead of kilobits. 131 */ 132 133static int 134intel_dp_link_required(int pixel_clock, int bpp) 135{ 136 return (pixel_clock * bpp + 9) / 10; 137} 138 139static int 140intel_dp_max_data_rate(int max_link_clock, int max_lanes) 141{ 142 return (max_link_clock * max_lanes * 8) / 10; 143} 144 145static enum drm_mode_status 146intel_dp_mode_valid(struct drm_connector *connector, 147 struct drm_display_mode *mode) 148{ 149 struct intel_dp *intel_dp = intel_attached_dp(connector); 150 struct intel_connector *intel_connector = to_intel_connector(connector); 151 struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode; 152 int target_clock = mode->clock; 153 int max_rate, mode_rate, max_lanes, max_link_clock; 154 155 if (is_edp(intel_dp) && fixed_mode) { 156 if (mode->hdisplay > fixed_mode->hdisplay) 157 return MODE_PANEL; 158 159 if (mode->vdisplay > fixed_mode->vdisplay) 160 return MODE_PANEL; 161 162 target_clock = fixed_mode->clock; 163 } 164 165 max_link_clock = drm_dp_bw_code_to_link_rate(intel_dp_max_link_bw(intel_dp)); 166 max_lanes = drm_dp_max_lane_count(intel_dp->dpcd); 167 168 max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes); 169 mode_rate = intel_dp_link_required(target_clock, 18); 170 171 if (mode_rate > max_rate) 172 return MODE_CLOCK_HIGH; 173 174 if (mode->clock < 10000) 175 return MODE_CLOCK_LOW; 176 177 if (mode->flags & DRM_MODE_FLAG_DBLCLK) 178 return MODE_H_ILLEGAL; 179 180 return MODE_OK; 181} 182 183static uint32_t 184pack_aux(uint8_t *src, int src_bytes) 185{ 186 int i; 187 uint32_t v = 0; 188 189 if (src_bytes > 4) 190 src_bytes = 4; 191 for (i = 0; i < src_bytes; i++) 192 v |= ((uint32_t) src[i]) << ((3-i) * 8); 193 return v; 194} 195 196static void 197unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes) 198{ 199 int i; 200 if (dst_bytes > 4) 201 dst_bytes = 4; 202 for (i = 0; i < dst_bytes; i++) 203 dst[i] = src >> ((3-i) * 8); 204} 205 206/* hrawclock is 1/4 the FSB frequency */ 207static int 208intel_hrawclk(struct drm_device *dev) 209{ 210 struct drm_i915_private *dev_priv = dev->dev_private; 211 uint32_t clkcfg; 212 213 /* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */ 214 if (IS_VALLEYVIEW(dev)) 215 return 200; 216 217 clkcfg = I915_READ(CLKCFG); 218 switch (clkcfg & CLKCFG_FSB_MASK) { 219 case CLKCFG_FSB_400: 220 return 100; 221 case CLKCFG_FSB_533: 222 return 133; 223 case CLKCFG_FSB_667: 224 return 166; 225 case CLKCFG_FSB_800: 226 return 200; 227 case CLKCFG_FSB_1067: 228 return 266; 229 case CLKCFG_FSB_1333: 230 return 333; 231 /* these two are just a guess; one of them might be right */ 232 case CLKCFG_FSB_1600: 233 case CLKCFG_FSB_1600_ALT: 234 return 400; 235 default: 236 return 133; 237 } 238} 239 240static void 241intel_dp_init_panel_power_sequencer(struct drm_device *dev, 242 struct intel_dp *intel_dp, 243 struct edp_power_seq *out); 244static void 245intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev, 246 struct intel_dp *intel_dp, 247 struct edp_power_seq *out); 248 249static enum pipe 250vlv_power_sequencer_pipe(struct intel_dp *intel_dp) 251{ 252 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 253 struct drm_crtc *crtc = intel_dig_port->base.base.crtc; 254 struct drm_device *dev = intel_dig_port->base.base.dev; 255 struct drm_i915_private *dev_priv = dev->dev_private; 256 enum port port = intel_dig_port->port; 257 enum pipe pipe; 258 259 /* modeset should have pipe */ 260 if (crtc) 261 return to_intel_crtc(crtc)->pipe; 262 263 /* init time, try to find a pipe with this port selected */ 264 for (pipe = PIPE_A; pipe <= PIPE_B; pipe++) { 265 u32 port_sel = I915_READ(VLV_PIPE_PP_ON_DELAYS(pipe)) & 266 PANEL_PORT_SELECT_MASK; 267 if (port_sel == PANEL_PORT_SELECT_DPB_VLV && port == PORT_B) 268 return pipe; 269 if (port_sel == PANEL_PORT_SELECT_DPC_VLV && port == PORT_C) 270 return pipe; 271 } 272 273 /* shrug */ 274 return PIPE_A; 275} 276 277static u32 _pp_ctrl_reg(struct intel_dp *intel_dp) 278{ 279 struct drm_device *dev = intel_dp_to_dev(intel_dp); 280 281 if (HAS_PCH_SPLIT(dev)) 282 return PCH_PP_CONTROL; 283 else 284 return VLV_PIPE_PP_CONTROL(vlv_power_sequencer_pipe(intel_dp)); 285} 286 287static u32 _pp_stat_reg(struct intel_dp *intel_dp) 288{ 289 struct drm_device *dev = intel_dp_to_dev(intel_dp); 290 291 if (HAS_PCH_SPLIT(dev)) 292 return PCH_PP_STATUS; 293 else 294 return VLV_PIPE_PP_STATUS(vlv_power_sequencer_pipe(intel_dp)); 295} 296 297static bool ironlake_edp_have_panel_power(struct intel_dp *intel_dp) 298{ 299 struct drm_device *dev = intel_dp_to_dev(intel_dp); 300 struct drm_i915_private *dev_priv = dev->dev_private; 301 302 return (I915_READ(_pp_stat_reg(intel_dp)) & PP_ON) != 0; 303} 304 305static bool ironlake_edp_have_panel_vdd(struct intel_dp *intel_dp) 306{ 307 struct drm_device *dev = intel_dp_to_dev(intel_dp); 308 struct drm_i915_private *dev_priv = dev->dev_private; 309 310 return (I915_READ(_pp_ctrl_reg(intel_dp)) & EDP_FORCE_VDD) != 0; 311} 312 313static void 314intel_dp_check_edp(struct intel_dp *intel_dp) 315{ 316 struct drm_device *dev = intel_dp_to_dev(intel_dp); 317 struct drm_i915_private *dev_priv = dev->dev_private; 318 319 if (!is_edp(intel_dp)) 320 return; 321 322 if (!ironlake_edp_have_panel_power(intel_dp) && !ironlake_edp_have_panel_vdd(intel_dp)) { 323 WARN(1, "eDP powered off while attempting aux channel communication.\n"); 324 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n", 325 I915_READ(_pp_stat_reg(intel_dp)), 326 I915_READ(_pp_ctrl_reg(intel_dp))); 327 } 328} 329 330static uint32_t 331intel_dp_aux_wait_done(struct intel_dp *intel_dp, bool has_aux_irq) 332{ 333 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 334 struct drm_device *dev = intel_dig_port->base.base.dev; 335 struct drm_i915_private *dev_priv = dev->dev_private; 336 uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg; 337 uint32_t status; 338 bool done; 339 340#define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0) 341 if (has_aux_irq) 342 done = wait_event_timeout(dev_priv->gmbus_wait_queue, C, 343 msecs_to_jiffies_timeout(10)); 344 else 345 done = wait_for_atomic(C, 10) == 0; 346 if (!done) 347 DRM_ERROR("dp aux hw did not signal timeout (has irq: %i)!\n", 348 has_aux_irq); 349#undef C 350 351 return status; 352} 353 354static uint32_t get_aux_clock_divider(struct intel_dp *intel_dp, 355 int index) 356{ 357 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 358 struct drm_device *dev = intel_dig_port->base.base.dev; 359 struct drm_i915_private *dev_priv = dev->dev_private; 360 361 /* The clock divider is based off the hrawclk, 362 * and would like to run at 2MHz. So, take the 363 * hrawclk value and divide by 2 and use that 364 * 365 * Note that PCH attached eDP panels should use a 125MHz input 366 * clock divider. 367 */ 368 if (IS_VALLEYVIEW(dev)) { 369 return index ? 0 : 100; 370 } else if (intel_dig_port->port == PORT_A) { 371 if (index) 372 return 0; 373 if (HAS_DDI(dev)) 374 return DIV_ROUND_CLOSEST(intel_ddi_get_cdclk_freq(dev_priv), 2000); 375 else if (IS_GEN6(dev) || IS_GEN7(dev)) 376 return 200; /* SNB & IVB eDP input clock at 400Mhz */ 377 else 378 return 225; /* eDP input clock at 450Mhz */ 379 } else if (dev_priv->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE) { 380 /* Workaround for non-ULT HSW */ 381 switch (index) { 382 case 0: return 63; 383 case 1: return 72; 384 default: return 0; 385 } 386 } else if (HAS_PCH_SPLIT(dev)) { 387 return index ? 0 : DIV_ROUND_UP(intel_pch_rawclk(dev), 2); 388 } else { 389 return index ? 0 :intel_hrawclk(dev) / 2; 390 } 391} 392 393static int 394intel_dp_aux_ch(struct intel_dp *intel_dp, 395 uint8_t *send, int send_bytes, 396 uint8_t *recv, int recv_size) 397{ 398 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 399 struct drm_device *dev = intel_dig_port->base.base.dev; 400 struct drm_i915_private *dev_priv = dev->dev_private; 401 uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg; 402 uint32_t ch_data = ch_ctl + 4; 403 uint32_t aux_clock_divider; 404 int i, ret, recv_bytes; 405 uint32_t status; 406 int try, precharge, clock = 0; 407 bool has_aux_irq = true; 408 uint32_t timeout; 409 410 /* dp aux is extremely sensitive to irq latency, hence request the 411 * lowest possible wakeup latency and so prevent the cpu from going into 412 * deep sleep states. 413 */ 414 pm_qos_update_request(&dev_priv->pm_qos, 0); 415 416 intel_dp_check_edp(intel_dp); 417 418 if (IS_GEN6(dev)) 419 precharge = 3; 420 else 421 precharge = 5; 422 423 if (IS_BROADWELL(dev) && ch_ctl == DPA_AUX_CH_CTL) 424 timeout = DP_AUX_CH_CTL_TIME_OUT_600us; 425 else 426 timeout = DP_AUX_CH_CTL_TIME_OUT_400us; 427 428 intel_aux_display_runtime_get(dev_priv); 429 430 /* Try to wait for any previous AUX channel activity */ 431 for (try = 0; try < 3; try++) { 432 status = I915_READ_NOTRACE(ch_ctl); 433 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0) 434 break; 435 msleep(1); 436 } 437 438 if (try == 3) { 439 WARN(1, "dp_aux_ch not started status 0x%08x\n", 440 I915_READ(ch_ctl)); 441 ret = -EBUSY; 442 goto out; 443 } 444 445 /* Only 5 data registers! */ 446 if (WARN_ON(send_bytes > 20 || recv_size > 20)) { 447 ret = -E2BIG; 448 goto out; 449 } 450 451 while ((aux_clock_divider = get_aux_clock_divider(intel_dp, clock++))) { 452 /* Must try at least 3 times according to DP spec */ 453 for (try = 0; try < 5; try++) { 454 /* Load the send data into the aux channel data registers */ 455 for (i = 0; i < send_bytes; i += 4) 456 I915_WRITE(ch_data + i, 457 pack_aux(send + i, send_bytes - i)); 458 459 /* Send the command and wait for it to complete */ 460 I915_WRITE(ch_ctl, 461 DP_AUX_CH_CTL_SEND_BUSY | 462 (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) | 463 timeout | 464 (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) | 465 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) | 466 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT) | 467 DP_AUX_CH_CTL_DONE | 468 DP_AUX_CH_CTL_TIME_OUT_ERROR | 469 DP_AUX_CH_CTL_RECEIVE_ERROR); 470 471 status = intel_dp_aux_wait_done(intel_dp, has_aux_irq); 472 473 /* Clear done status and any errors */ 474 I915_WRITE(ch_ctl, 475 status | 476 DP_AUX_CH_CTL_DONE | 477 DP_AUX_CH_CTL_TIME_OUT_ERROR | 478 DP_AUX_CH_CTL_RECEIVE_ERROR); 479 480 if (status & (DP_AUX_CH_CTL_TIME_OUT_ERROR | 481 DP_AUX_CH_CTL_RECEIVE_ERROR)) 482 continue; 483 if (status & DP_AUX_CH_CTL_DONE) 484 break; 485 } 486 if (status & DP_AUX_CH_CTL_DONE) 487 break; 488 } 489 490 if ((status & DP_AUX_CH_CTL_DONE) == 0) { 491 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status); 492 ret = -EBUSY; 493 goto out; 494 } 495 496 /* Check for timeout or receive error. 497 * Timeouts occur when the sink is not connected 498 */ 499 if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) { 500 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status); 501 ret = -EIO; 502 goto out; 503 } 504 505 /* Timeouts occur when the device isn't connected, so they're 506 * "normal" -- don't fill the kernel log with these */ 507 if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) { 508 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status); 509 ret = -ETIMEDOUT; 510 goto out; 511 } 512 513 /* Unload any bytes sent back from the other side */ 514 recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >> 515 DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT); 516 if (recv_bytes > recv_size) 517 recv_bytes = recv_size; 518 519 for (i = 0; i < recv_bytes; i += 4) 520 unpack_aux(I915_READ(ch_data + i), 521 recv + i, recv_bytes - i); 522 523 ret = recv_bytes; 524out: 525 pm_qos_update_request(&dev_priv->pm_qos, PM_QOS_DEFAULT_VALUE); 526 intel_aux_display_runtime_put(dev_priv); 527 528 return ret; 529} 530 531/* Write data to the aux channel in native mode */ 532static int 533intel_dp_aux_native_write(struct intel_dp *intel_dp, 534 uint16_t address, uint8_t *send, int send_bytes) 535{ 536 int ret; 537 uint8_t msg[20]; 538 int msg_bytes; 539 uint8_t ack; 540 541 if (WARN_ON(send_bytes > 16)) 542 return -E2BIG; 543 544 intel_dp_check_edp(intel_dp); 545 msg[0] = DP_AUX_NATIVE_WRITE << 4; 546 msg[1] = address >> 8; 547 msg[2] = address & 0xff; 548 msg[3] = send_bytes - 1; 549 memcpy(&msg[4], send, send_bytes); 550 msg_bytes = send_bytes + 4; 551 for (;;) { 552 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes, &ack, 1); 553 if (ret < 0) 554 return ret; 555 ack >>= 4; 556 if ((ack & DP_AUX_NATIVE_REPLY_MASK) == DP_AUX_NATIVE_REPLY_ACK) 557 break; 558 else if ((ack & DP_AUX_NATIVE_REPLY_MASK) == DP_AUX_NATIVE_REPLY_DEFER) 559 udelay(100); 560 else 561 return -EIO; 562 } 563 return send_bytes; 564} 565 566/* Write a single byte to the aux channel in native mode */ 567static int 568intel_dp_aux_native_write_1(struct intel_dp *intel_dp, 569 uint16_t address, uint8_t byte) 570{ 571 return intel_dp_aux_native_write(intel_dp, address, &byte, 1); 572} 573 574/* read bytes from a native aux channel */ 575static int 576intel_dp_aux_native_read(struct intel_dp *intel_dp, 577 uint16_t address, uint8_t *recv, int recv_bytes) 578{ 579 uint8_t msg[4]; 580 int msg_bytes; 581 uint8_t reply[20]; 582 int reply_bytes; 583 uint8_t ack; 584 int ret; 585 586 if (WARN_ON(recv_bytes > 19)) 587 return -E2BIG; 588 589 intel_dp_check_edp(intel_dp); 590 msg[0] = DP_AUX_NATIVE_READ << 4; 591 msg[1] = address >> 8; 592 msg[2] = address & 0xff; 593 msg[3] = recv_bytes - 1; 594 595 msg_bytes = 4; 596 reply_bytes = recv_bytes + 1; 597 598 for (;;) { 599 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes, 600 reply, reply_bytes); 601 if (ret == 0) 602 return -EPROTO; 603 if (ret < 0) 604 return ret; 605 ack = reply[0] >> 4; 606 if ((ack & DP_AUX_NATIVE_REPLY_MASK) == DP_AUX_NATIVE_REPLY_ACK) { 607 memcpy(recv, reply + 1, ret - 1); 608 return ret - 1; 609 } 610 else if ((ack & DP_AUX_NATIVE_REPLY_MASK) == DP_AUX_NATIVE_REPLY_DEFER) 611 udelay(100); 612 else 613 return -EIO; 614 } 615} 616 617static int 618intel_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode, 619 uint8_t write_byte, uint8_t *read_byte) 620{ 621 struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data; 622 struct intel_dp *intel_dp = container_of(adapter, 623 struct intel_dp, 624 adapter); 625 uint16_t address = algo_data->address; 626 uint8_t msg[5]; 627 uint8_t reply[2]; 628 unsigned retry; 629 int msg_bytes; 630 int reply_bytes; 631 int ret; 632 633 ironlake_edp_panel_vdd_on(intel_dp); 634 intel_dp_check_edp(intel_dp); 635 /* Set up the command byte */ 636 if (mode & MODE_I2C_READ) 637 msg[0] = DP_AUX_I2C_READ << 4; 638 else 639 msg[0] = DP_AUX_I2C_WRITE << 4; 640 641 if (!(mode & MODE_I2C_STOP)) 642 msg[0] |= DP_AUX_I2C_MOT << 4; 643 644 msg[1] = address >> 8; 645 msg[2] = address; 646 647 switch (mode) { 648 case MODE_I2C_WRITE: 649 msg[3] = 0; 650 msg[4] = write_byte; 651 msg_bytes = 5; 652 reply_bytes = 1; 653 break; 654 case MODE_I2C_READ: 655 msg[3] = 0; 656 msg_bytes = 4; 657 reply_bytes = 2; 658 break; 659 default: 660 msg_bytes = 3; 661 reply_bytes = 1; 662 break; 663 } 664 665 /* 666 * DP1.2 sections 2.7.7.1.5.6.1 and 2.7.7.1.6.6.1: A DP Source device is 667 * required to retry at least seven times upon receiving AUX_DEFER 668 * before giving up the AUX transaction. 669 */ 670 for (retry = 0; retry < 7; retry++) { 671 ret = intel_dp_aux_ch(intel_dp, 672 msg, msg_bytes, 673 reply, reply_bytes); 674 if (ret < 0) { 675 DRM_DEBUG_KMS("aux_ch failed %d\n", ret); 676 goto out; 677 } 678 679 switch ((reply[0] >> 4) & DP_AUX_NATIVE_REPLY_MASK) { 680 case DP_AUX_NATIVE_REPLY_ACK: 681 /* I2C-over-AUX Reply field is only valid 682 * when paired with AUX ACK. 683 */ 684 break; 685 case DP_AUX_NATIVE_REPLY_NACK: 686 DRM_DEBUG_KMS("aux_ch native nack\n"); 687 ret = -EREMOTEIO; 688 goto out; 689 case DP_AUX_NATIVE_REPLY_DEFER: 690 /* 691 * For now, just give more slack to branch devices. We 692 * could check the DPCD for I2C bit rate capabilities, 693 * and if available, adjust the interval. We could also 694 * be more careful with DP-to-Legacy adapters where a 695 * long legacy cable may force very low I2C bit rates. 696 */ 697 if (intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] & 698 DP_DWN_STRM_PORT_PRESENT) 699 usleep_range(500, 600); 700 else 701 usleep_range(300, 400); 702 continue; 703 default: 704 DRM_ERROR("aux_ch invalid native reply 0x%02x\n", 705 reply[0]); 706 ret = -EREMOTEIO; 707 goto out; 708 } 709 710 switch ((reply[0] >> 4) & DP_AUX_I2C_REPLY_MASK) { 711 case DP_AUX_I2C_REPLY_ACK: 712 if (mode == MODE_I2C_READ) { 713 *read_byte = reply[1]; 714 } 715 ret = reply_bytes - 1; 716 goto out; 717 case DP_AUX_I2C_REPLY_NACK: 718 DRM_DEBUG_KMS("aux_i2c nack\n"); 719 ret = -EREMOTEIO; 720 goto out; 721 case DP_AUX_I2C_REPLY_DEFER: 722 DRM_DEBUG_KMS("aux_i2c defer\n"); 723 udelay(100); 724 break; 725 default: 726 DRM_ERROR("aux_i2c invalid reply 0x%02x\n", reply[0]); 727 ret = -EREMOTEIO; 728 goto out; 729 } 730 } 731 732 DRM_ERROR("too many retries, giving up\n"); 733 ret = -EREMOTEIO; 734 735out: 736 ironlake_edp_panel_vdd_off(intel_dp, false); 737 return ret; 738} 739 740static int 741intel_dp_i2c_init(struct intel_dp *intel_dp, 742 struct intel_connector *intel_connector, const char *name) 743{ 744 int ret; 745 746 DRM_DEBUG_KMS("i2c_init %s\n", name); 747 intel_dp->algo.running = false; 748 intel_dp->algo.address = 0; 749 intel_dp->algo.aux_ch = intel_dp_i2c_aux_ch; 750 751 memset(&intel_dp->adapter, '\0', sizeof(intel_dp->adapter)); 752 intel_dp->adapter.owner = THIS_MODULE; 753 intel_dp->adapter.class = I2C_CLASS_DDC; 754 strncpy(intel_dp->adapter.name, name, sizeof(intel_dp->adapter.name) - 1); 755 intel_dp->adapter.name[sizeof(intel_dp->adapter.name) - 1] = '\0'; 756 intel_dp->adapter.algo_data = &intel_dp->algo; 757 intel_dp->adapter.dev.parent = intel_connector->base.kdev; 758 759 ret = i2c_dp_aux_add_bus(&intel_dp->adapter); 760 return ret; 761} 762 763static void 764intel_dp_set_clock(struct intel_encoder *encoder, 765 struct intel_crtc_config *pipe_config, int link_bw) 766{ 767 struct drm_device *dev = encoder->base.dev; 768 const struct dp_link_dpll *divisor = NULL; 769 int i, count = 0; 770 771 if (IS_G4X(dev)) { 772 divisor = gen4_dpll; 773 count = ARRAY_SIZE(gen4_dpll); 774 } else if (IS_HASWELL(dev)) { 775 /* Haswell has special-purpose DP DDI clocks. */ 776 } else if (HAS_PCH_SPLIT(dev)) { 777 divisor = pch_dpll; 778 count = ARRAY_SIZE(pch_dpll); 779 } else if (IS_VALLEYVIEW(dev)) { 780 divisor = vlv_dpll; 781 count = ARRAY_SIZE(vlv_dpll); 782 } 783 784 if (divisor && count) { 785 for (i = 0; i < count; i++) { 786 if (link_bw == divisor[i].link_bw) { 787 pipe_config->dpll = divisor[i].dpll; 788 pipe_config->clock_set = true; 789 break; 790 } 791 } 792 } 793} 794 795bool 796intel_dp_compute_config(struct intel_encoder *encoder, 797 struct intel_crtc_config *pipe_config) 798{ 799 struct drm_device *dev = encoder->base.dev; 800 struct drm_i915_private *dev_priv = dev->dev_private; 801 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode; 802 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); 803 enum port port = dp_to_dig_port(intel_dp)->port; 804 struct intel_crtc *intel_crtc = encoder->new_crtc; 805 struct intel_connector *intel_connector = intel_dp->attached_connector; 806 int lane_count, clock; 807 int max_lane_count = drm_dp_max_lane_count(intel_dp->dpcd); 808 int max_clock = intel_dp_max_link_bw(intel_dp) == DP_LINK_BW_2_7 ? 1 : 0; 809 int bpp, mode_rate; 810 static int bws[2] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7 }; 811 int link_avail, link_clock; 812 813 if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev) && port != PORT_A) 814 pipe_config->has_pch_encoder = true; 815 816 pipe_config->has_dp_encoder = true; 817 818 if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) { 819 intel_fixed_panel_mode(intel_connector->panel.fixed_mode, 820 adjusted_mode); 821 if (!HAS_PCH_SPLIT(dev)) 822 intel_gmch_panel_fitting(intel_crtc, pipe_config, 823 intel_connector->panel.fitting_mode); 824 else 825 intel_pch_panel_fitting(intel_crtc, pipe_config, 826 intel_connector->panel.fitting_mode); 827 } 828 829 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK) 830 return false; 831 832 DRM_DEBUG_KMS("DP link computation with max lane count %i " 833 "max bw %02x pixel clock %iKHz\n", 834 max_lane_count, bws[max_clock], 835 adjusted_mode->crtc_clock); 836 837 /* Walk through all bpp values. Luckily they're all nicely spaced with 2 838 * bpc in between. */ 839 bpp = pipe_config->pipe_bpp; 840 if (is_edp(intel_dp) && dev_priv->vbt.edp_bpp && 841 dev_priv->vbt.edp_bpp < bpp) { 842 DRM_DEBUG_KMS("clamping bpp for eDP panel to BIOS-provided %i\n", 843 dev_priv->vbt.edp_bpp); 844 bpp = dev_priv->vbt.edp_bpp; 845 } 846 847 for (; bpp >= 6*3; bpp -= 2*3) { 848 mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock, 849 bpp); 850 851 for (clock = 0; clock <= max_clock; clock++) { 852 for (lane_count = 1; lane_count <= max_lane_count; lane_count <<= 1) { 853 link_clock = drm_dp_bw_code_to_link_rate(bws[clock]); 854 link_avail = intel_dp_max_data_rate(link_clock, 855 lane_count); 856 857 if (mode_rate <= link_avail) { 858 goto found; 859 } 860 } 861 } 862 } 863 864 return false; 865 866found: 867 if (intel_dp->color_range_auto) { 868 /* 869 * See: 870 * CEA-861-E - 5.1 Default Encoding Parameters 871 * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry 872 */ 873 if (bpp != 18 && drm_match_cea_mode(adjusted_mode) > 1) 874 intel_dp->color_range = DP_COLOR_RANGE_16_235; 875 else 876 intel_dp->color_range = 0; 877 } 878 879 if (intel_dp->color_range) 880 pipe_config->limited_color_range = true; 881 882 intel_dp->link_bw = bws[clock]; 883 intel_dp->lane_count = lane_count; 884 pipe_config->pipe_bpp = bpp; 885 pipe_config->port_clock = drm_dp_bw_code_to_link_rate(intel_dp->link_bw); 886 887 DRM_DEBUG_KMS("DP link bw %02x lane count %d clock %d bpp %d\n", 888 intel_dp->link_bw, intel_dp->lane_count, 889 pipe_config->port_clock, bpp); 890 DRM_DEBUG_KMS("DP link bw required %i available %i\n", 891 mode_rate, link_avail); 892 893 intel_link_compute_m_n(bpp, lane_count, 894 adjusted_mode->crtc_clock, 895 pipe_config->port_clock, 896 &pipe_config->dp_m_n); 897 898 intel_dp_set_clock(encoder, pipe_config, intel_dp->link_bw); 899 900 return true; 901} 902 903static void ironlake_set_pll_cpu_edp(struct intel_dp *intel_dp) 904{ 905 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 906 struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc); 907 struct drm_device *dev = crtc->base.dev; 908 struct drm_i915_private *dev_priv = dev->dev_private; 909 u32 dpa_ctl; 910 911 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", crtc->config.port_clock); 912 dpa_ctl = I915_READ(DP_A); 913 dpa_ctl &= ~DP_PLL_FREQ_MASK; 914 915 if (crtc->config.port_clock == 162000) { 916 /* For a long time we've carried around a ILK-DevA w/a for the 917 * 160MHz clock. If we're really unlucky, it's still required. 918 */ 919 DRM_DEBUG_KMS("160MHz cpu eDP clock, might need ilk devA w/a\n"); 920 dpa_ctl |= DP_PLL_FREQ_160MHZ; 921 intel_dp->DP |= DP_PLL_FREQ_160MHZ; 922 } else { 923 dpa_ctl |= DP_PLL_FREQ_270MHZ; 924 intel_dp->DP |= DP_PLL_FREQ_270MHZ; 925 } 926 927 I915_WRITE(DP_A, dpa_ctl); 928 929 POSTING_READ(DP_A); 930 udelay(500); 931} 932 933static void intel_dp_mode_set(struct intel_encoder *encoder) 934{ 935 struct drm_device *dev = encoder->base.dev; 936 struct drm_i915_private *dev_priv = dev->dev_private; 937 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); 938 enum port port = dp_to_dig_port(intel_dp)->port; 939 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); 940 struct drm_display_mode *adjusted_mode = &crtc->config.adjusted_mode; 941 942 /* 943 * There are four kinds of DP registers: 944 * 945 * IBX PCH 946 * SNB CPU 947 * IVB CPU 948 * CPT PCH 949 * 950 * IBX PCH and CPU are the same for almost everything, 951 * except that the CPU DP PLL is configured in this 952 * register 953 * 954 * CPT PCH is quite different, having many bits moved 955 * to the TRANS_DP_CTL register instead. That 956 * configuration happens (oddly) in ironlake_pch_enable 957 */ 958 959 /* Preserve the BIOS-computed detected bit. This is 960 * supposed to be read-only. 961 */ 962 intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED; 963 964 /* Handle DP bits in common between all three register formats */ 965 intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0; 966 intel_dp->DP |= DP_PORT_WIDTH(intel_dp->lane_count); 967 968 if (intel_dp->has_audio) { 969 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n", 970 pipe_name(crtc->pipe)); 971 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE; 972 intel_write_eld(&encoder->base, adjusted_mode); 973 } 974 975 /* Split out the IBX/CPU vs CPT settings */ 976 977 if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) { 978 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) 979 intel_dp->DP |= DP_SYNC_HS_HIGH; 980 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) 981 intel_dp->DP |= DP_SYNC_VS_HIGH; 982 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT; 983 984 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd)) 985 intel_dp->DP |= DP_ENHANCED_FRAMING; 986 987 intel_dp->DP |= crtc->pipe << 29; 988 } else if (!HAS_PCH_CPT(dev) || port == PORT_A) { 989 if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev)) 990 intel_dp->DP |= intel_dp->color_range; 991 992 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) 993 intel_dp->DP |= DP_SYNC_HS_HIGH; 994 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) 995 intel_dp->DP |= DP_SYNC_VS_HIGH; 996 intel_dp->DP |= DP_LINK_TRAIN_OFF; 997 998 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd)) 999 intel_dp->DP |= DP_ENHANCED_FRAMING; 1000 1001 if (crtc->pipe == 1) 1002 intel_dp->DP |= DP_PIPEB_SELECT; 1003 } else { 1004 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT; 1005 } 1006 1007 if (port == PORT_A && !IS_VALLEYVIEW(dev)) 1008 ironlake_set_pll_cpu_edp(intel_dp); 1009} 1010 1011#define IDLE_ON_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK) 1012#define IDLE_ON_VALUE (PP_ON | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE) 1013 1014#define IDLE_OFF_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK) 1015#define IDLE_OFF_VALUE (0 | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE) 1016 1017#define IDLE_CYCLE_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK) 1018#define IDLE_CYCLE_VALUE (0 | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE) 1019 1020static void ironlake_wait_panel_status(struct intel_dp *intel_dp, 1021 u32 mask, 1022 u32 value) 1023{ 1024 struct drm_device *dev = intel_dp_to_dev(intel_dp); 1025 struct drm_i915_private *dev_priv = dev->dev_private; 1026 u32 pp_stat_reg, pp_ctrl_reg; 1027 1028 pp_stat_reg = _pp_stat_reg(intel_dp); 1029 pp_ctrl_reg = _pp_ctrl_reg(intel_dp); 1030 1031 DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n", 1032 mask, value, 1033 I915_READ(pp_stat_reg), 1034 I915_READ(pp_ctrl_reg)); 1035 1036 if (_wait_for((I915_READ(pp_stat_reg) & mask) == value, 5000, 10)) { 1037 DRM_ERROR("Panel status timeout: status %08x control %08x\n", 1038 I915_READ(pp_stat_reg), 1039 I915_READ(pp_ctrl_reg)); 1040 } 1041} 1042 1043static void ironlake_wait_panel_on(struct intel_dp *intel_dp) 1044{ 1045 DRM_DEBUG_KMS("Wait for panel power on\n"); 1046 ironlake_wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE); 1047} 1048 1049static void ironlake_wait_panel_off(struct intel_dp *intel_dp) 1050{ 1051 DRM_DEBUG_KMS("Wait for panel power off time\n"); 1052 ironlake_wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE); 1053} 1054 1055static void ironlake_wait_panel_power_cycle(struct intel_dp *intel_dp) 1056{ 1057 DRM_DEBUG_KMS("Wait for panel power cycle\n"); 1058 ironlake_wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE); 1059} 1060 1061 1062/* Read the current pp_control value, unlocking the register if it 1063 * is locked 1064 */ 1065 1066static u32 ironlake_get_pp_control(struct intel_dp *intel_dp) 1067{ 1068 struct drm_device *dev = intel_dp_to_dev(intel_dp); 1069 struct drm_i915_private *dev_priv = dev->dev_private; 1070 u32 control; 1071 1072 control = I915_READ(_pp_ctrl_reg(intel_dp)); 1073 control &= ~PANEL_UNLOCK_MASK; 1074 control |= PANEL_UNLOCK_REGS; 1075 return control; 1076} 1077 1078void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp) 1079{ 1080 struct drm_device *dev = intel_dp_to_dev(intel_dp); 1081 struct drm_i915_private *dev_priv = dev->dev_private; 1082 u32 pp; 1083 u32 pp_stat_reg, pp_ctrl_reg; 1084 1085 if (!is_edp(intel_dp)) 1086 return; 1087 1088 WARN(intel_dp->want_panel_vdd, 1089 "eDP VDD already requested on\n"); 1090 1091 intel_dp->want_panel_vdd = true; 1092 1093 if (ironlake_edp_have_panel_vdd(intel_dp)) 1094 return; 1095 1096 DRM_DEBUG_KMS("Turning eDP VDD on\n"); 1097 1098 if (!ironlake_edp_have_panel_power(intel_dp)) 1099 ironlake_wait_panel_power_cycle(intel_dp); 1100 1101 pp = ironlake_get_pp_control(intel_dp); 1102 pp |= EDP_FORCE_VDD; 1103 1104 pp_stat_reg = _pp_stat_reg(intel_dp); 1105 pp_ctrl_reg = _pp_ctrl_reg(intel_dp); 1106 1107 I915_WRITE(pp_ctrl_reg, pp); 1108 POSTING_READ(pp_ctrl_reg); 1109 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n", 1110 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg)); 1111 /* 1112 * If the panel wasn't on, delay before accessing aux channel 1113 */ 1114 if (!ironlake_edp_have_panel_power(intel_dp)) { 1115 DRM_DEBUG_KMS("eDP was not running\n"); 1116 msleep(intel_dp->panel_power_up_delay); 1117 } 1118} 1119 1120static void ironlake_panel_vdd_off_sync(struct intel_dp *intel_dp) 1121{ 1122 struct drm_device *dev = intel_dp_to_dev(intel_dp); 1123 struct drm_i915_private *dev_priv = dev->dev_private; 1124 u32 pp; 1125 u32 pp_stat_reg, pp_ctrl_reg; 1126 1127 WARN_ON(!mutex_is_locked(&dev->mode_config.mutex)); 1128 1129 if (!intel_dp->want_panel_vdd && ironlake_edp_have_panel_vdd(intel_dp)) { 1130 DRM_DEBUG_KMS("Turning eDP VDD off\n"); 1131 1132 pp = ironlake_get_pp_control(intel_dp); 1133 pp &= ~EDP_FORCE_VDD; 1134 1135 pp_ctrl_reg = _pp_ctrl_reg(intel_dp); 1136 pp_stat_reg = _pp_stat_reg(intel_dp); 1137 1138 I915_WRITE(pp_ctrl_reg, pp); 1139 POSTING_READ(pp_ctrl_reg); 1140 1141 /* Make sure sequencer is idle before allowing subsequent activity */ 1142 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n", 1143 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg)); 1144 msleep(intel_dp->panel_power_down_delay); 1145 } 1146} 1147 1148static void ironlake_panel_vdd_work(struct work_struct *__work) 1149{ 1150 struct intel_dp *intel_dp = container_of(to_delayed_work(__work), 1151 struct intel_dp, panel_vdd_work); 1152 struct drm_device *dev = intel_dp_to_dev(intel_dp); 1153 1154 mutex_lock(&dev->mode_config.mutex); 1155 ironlake_panel_vdd_off_sync(intel_dp); 1156 mutex_unlock(&dev->mode_config.mutex); 1157} 1158 1159void ironlake_edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync) 1160{ 1161 if (!is_edp(intel_dp)) 1162 return; 1163 1164 WARN(!intel_dp->want_panel_vdd, "eDP VDD not forced on"); 1165 1166 intel_dp->want_panel_vdd = false; 1167 1168 if (sync) { 1169 ironlake_panel_vdd_off_sync(intel_dp); 1170 } else { 1171 /* 1172 * Queue the timer to fire a long 1173 * time from now (relative to the power down delay) 1174 * to keep the panel power up across a sequence of operations 1175 */ 1176 schedule_delayed_work(&intel_dp->panel_vdd_work, 1177 msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5)); 1178 } 1179} 1180 1181void ironlake_edp_panel_on(struct intel_dp *intel_dp) 1182{ 1183 struct drm_device *dev = intel_dp_to_dev(intel_dp); 1184 struct drm_i915_private *dev_priv = dev->dev_private; 1185 u32 pp; 1186 u32 pp_ctrl_reg; 1187 1188 if (!is_edp(intel_dp)) 1189 return; 1190 1191 DRM_DEBUG_KMS("Turn eDP power on\n"); 1192 1193 if (ironlake_edp_have_panel_power(intel_dp)) { 1194 DRM_DEBUG_KMS("eDP power already on\n"); 1195 return; 1196 } 1197 1198 ironlake_wait_panel_power_cycle(intel_dp); 1199 1200 pp_ctrl_reg = _pp_ctrl_reg(intel_dp); 1201 pp = ironlake_get_pp_control(intel_dp); 1202 if (IS_GEN5(dev)) { 1203 /* ILK workaround: disable reset around power sequence */ 1204 pp &= ~PANEL_POWER_RESET; 1205 I915_WRITE(pp_ctrl_reg, pp); 1206 POSTING_READ(pp_ctrl_reg); 1207 } 1208 1209 pp |= POWER_TARGET_ON; 1210 if (!IS_GEN5(dev)) 1211 pp |= PANEL_POWER_RESET; 1212 1213 I915_WRITE(pp_ctrl_reg, pp); 1214 POSTING_READ(pp_ctrl_reg); 1215 1216 ironlake_wait_panel_on(intel_dp); 1217 1218 if (IS_GEN5(dev)) { 1219 pp |= PANEL_POWER_RESET; /* restore panel reset bit */ 1220 I915_WRITE(pp_ctrl_reg, pp); 1221 POSTING_READ(pp_ctrl_reg); 1222 } 1223} 1224 1225void ironlake_edp_panel_off(struct intel_dp *intel_dp) 1226{ 1227 struct drm_device *dev = intel_dp_to_dev(intel_dp); 1228 struct drm_i915_private *dev_priv = dev->dev_private; 1229 u32 pp; 1230 u32 pp_ctrl_reg; 1231 1232 if (!is_edp(intel_dp)) 1233 return; 1234 1235 DRM_DEBUG_KMS("Turn eDP power off\n"); 1236 1237 WARN(!intel_dp->want_panel_vdd, "Need VDD to turn off panel\n"); 1238 1239 pp = ironlake_get_pp_control(intel_dp); 1240 /* We need to switch off panel power _and_ force vdd, for otherwise some 1241 * panels get very unhappy and cease to work. */ 1242 pp &= ~(POWER_TARGET_ON | EDP_FORCE_VDD | PANEL_POWER_RESET | EDP_BLC_ENABLE); 1243 1244 pp_ctrl_reg = _pp_ctrl_reg(intel_dp); 1245 1246 I915_WRITE(pp_ctrl_reg, pp); 1247 POSTING_READ(pp_ctrl_reg); 1248 1249 intel_dp->want_panel_vdd = false; 1250 1251 ironlake_wait_panel_off(intel_dp); 1252} 1253 1254void ironlake_edp_backlight_on(struct intel_dp *intel_dp) 1255{ 1256 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 1257 struct drm_device *dev = intel_dig_port->base.base.dev; 1258 struct drm_i915_private *dev_priv = dev->dev_private; 1259 u32 pp; 1260 u32 pp_ctrl_reg; 1261 1262 if (!is_edp(intel_dp)) 1263 return; 1264 1265 DRM_DEBUG_KMS("\n"); 1266 /* 1267 * If we enable the backlight right away following a panel power 1268 * on, we may see slight flicker as the panel syncs with the eDP 1269 * link. So delay a bit to make sure the image is solid before 1270 * allowing it to appear. 1271 */ 1272 msleep(intel_dp->backlight_on_delay); 1273 pp = ironlake_get_pp_control(intel_dp); 1274 pp |= EDP_BLC_ENABLE; 1275 1276 pp_ctrl_reg = _pp_ctrl_reg(intel_dp); 1277 1278 I915_WRITE(pp_ctrl_reg, pp); 1279 POSTING_READ(pp_ctrl_reg); 1280 1281 intel_panel_enable_backlight(intel_dp->attached_connector); 1282} 1283 1284void ironlake_edp_backlight_off(struct intel_dp *intel_dp) 1285{ 1286 struct drm_device *dev = intel_dp_to_dev(intel_dp); 1287 struct drm_i915_private *dev_priv = dev->dev_private; 1288 u32 pp; 1289 u32 pp_ctrl_reg; 1290 1291 if (!is_edp(intel_dp)) 1292 return; 1293 1294 intel_panel_disable_backlight(intel_dp->attached_connector); 1295 1296 DRM_DEBUG_KMS("\n"); 1297 pp = ironlake_get_pp_control(intel_dp); 1298 pp &= ~EDP_BLC_ENABLE; 1299 1300 pp_ctrl_reg = _pp_ctrl_reg(intel_dp); 1301 1302 I915_WRITE(pp_ctrl_reg, pp); 1303 POSTING_READ(pp_ctrl_reg); 1304 msleep(intel_dp->backlight_off_delay); 1305} 1306 1307static void ironlake_edp_pll_on(struct intel_dp *intel_dp) 1308{ 1309 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 1310 struct drm_crtc *crtc = intel_dig_port->base.base.crtc; 1311 struct drm_device *dev = crtc->dev; 1312 struct drm_i915_private *dev_priv = dev->dev_private; 1313 u32 dpa_ctl; 1314 1315 assert_pipe_disabled(dev_priv, 1316 to_intel_crtc(crtc)->pipe); 1317 1318 DRM_DEBUG_KMS("\n"); 1319 dpa_ctl = I915_READ(DP_A); 1320 WARN(dpa_ctl & DP_PLL_ENABLE, "dp pll on, should be off\n"); 1321 WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n"); 1322 1323 /* We don't adjust intel_dp->DP while tearing down the link, to 1324 * facilitate link retraining (e.g. after hotplug). Hence clear all 1325 * enable bits here to ensure that we don't enable too much. */ 1326 intel_dp->DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE); 1327 intel_dp->DP |= DP_PLL_ENABLE; 1328 I915_WRITE(DP_A, intel_dp->DP); 1329 POSTING_READ(DP_A); 1330 udelay(200); 1331} 1332 1333static void ironlake_edp_pll_off(struct intel_dp *intel_dp) 1334{ 1335 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 1336 struct drm_crtc *crtc = intel_dig_port->base.base.crtc; 1337 struct drm_device *dev = crtc->dev; 1338 struct drm_i915_private *dev_priv = dev->dev_private; 1339 u32 dpa_ctl; 1340 1341 assert_pipe_disabled(dev_priv, 1342 to_intel_crtc(crtc)->pipe); 1343 1344 dpa_ctl = I915_READ(DP_A); 1345 WARN((dpa_ctl & DP_PLL_ENABLE) == 0, 1346 "dp pll off, should be on\n"); 1347 WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n"); 1348 1349 /* We can't rely on the value tracked for the DP register in 1350 * intel_dp->DP because link_down must not change that (otherwise link 1351 * re-training will fail. */ 1352 dpa_ctl &= ~DP_PLL_ENABLE; 1353 I915_WRITE(DP_A, dpa_ctl); 1354 POSTING_READ(DP_A); 1355 udelay(200); 1356} 1357 1358/* If the sink supports it, try to set the power state appropriately */ 1359void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode) 1360{ 1361 int ret, i; 1362 1363 /* Should have a valid DPCD by this point */ 1364 if (intel_dp->dpcd[DP_DPCD_REV] < 0x11) 1365 return; 1366 1367 if (mode != DRM_MODE_DPMS_ON) { 1368 ret = intel_dp_aux_native_write_1(intel_dp, DP_SET_POWER, 1369 DP_SET_POWER_D3); 1370 if (ret != 1) 1371 DRM_DEBUG_DRIVER("failed to write sink power state\n"); 1372 } else { 1373 /* 1374 * When turning on, we need to retry for 1ms to give the sink 1375 * time to wake up. 1376 */ 1377 for (i = 0; i < 3; i++) { 1378 ret = intel_dp_aux_native_write_1(intel_dp, 1379 DP_SET_POWER, 1380 DP_SET_POWER_D0); 1381 if (ret == 1) 1382 break; 1383 msleep(1); 1384 } 1385 } 1386} 1387 1388static bool intel_dp_get_hw_state(struct intel_encoder *encoder, 1389 enum pipe *pipe) 1390{ 1391 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); 1392 enum port port = dp_to_dig_port(intel_dp)->port; 1393 struct drm_device *dev = encoder->base.dev; 1394 struct drm_i915_private *dev_priv = dev->dev_private; 1395 u32 tmp = I915_READ(intel_dp->output_reg); 1396 1397 if (!(tmp & DP_PORT_EN)) 1398 return false; 1399 1400 if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) { 1401 *pipe = PORT_TO_PIPE_CPT(tmp); 1402 } else if (!HAS_PCH_CPT(dev) || port == PORT_A) { 1403 *pipe = PORT_TO_PIPE(tmp); 1404 } else { 1405 u32 trans_sel; 1406 u32 trans_dp; 1407 int i; 1408 1409 switch (intel_dp->output_reg) { 1410 case PCH_DP_B: 1411 trans_sel = TRANS_DP_PORT_SEL_B; 1412 break; 1413 case PCH_DP_C: 1414 trans_sel = TRANS_DP_PORT_SEL_C; 1415 break; 1416 case PCH_DP_D: 1417 trans_sel = TRANS_DP_PORT_SEL_D; 1418 break; 1419 default: 1420 return true; 1421 } 1422 1423 for_each_pipe(i) { 1424 trans_dp = I915_READ(TRANS_DP_CTL(i)); 1425 if ((trans_dp & TRANS_DP_PORT_SEL_MASK) == trans_sel) { 1426 *pipe = i; 1427 return true; 1428 } 1429 } 1430 1431 DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n", 1432 intel_dp->output_reg); 1433 } 1434 1435 return true; 1436} 1437 1438static void intel_dp_get_config(struct intel_encoder *encoder, 1439 struct intel_crtc_config *pipe_config) 1440{ 1441 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); 1442 u32 tmp, flags = 0; 1443 struct drm_device *dev = encoder->base.dev; 1444 struct drm_i915_private *dev_priv = dev->dev_private; 1445 enum port port = dp_to_dig_port(intel_dp)->port; 1446 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); 1447 int dotclock; 1448 1449 if ((port == PORT_A) || !HAS_PCH_CPT(dev)) { 1450 tmp = I915_READ(intel_dp->output_reg); 1451 if (tmp & DP_SYNC_HS_HIGH) 1452 flags |= DRM_MODE_FLAG_PHSYNC; 1453 else 1454 flags |= DRM_MODE_FLAG_NHSYNC; 1455 1456 if (tmp & DP_SYNC_VS_HIGH) 1457 flags |= DRM_MODE_FLAG_PVSYNC; 1458 else 1459 flags |= DRM_MODE_FLAG_NVSYNC; 1460 } else { 1461 tmp = I915_READ(TRANS_DP_CTL(crtc->pipe)); 1462 if (tmp & TRANS_DP_HSYNC_ACTIVE_HIGH) 1463 flags |= DRM_MODE_FLAG_PHSYNC; 1464 else 1465 flags |= DRM_MODE_FLAG_NHSYNC; 1466 1467 if (tmp & TRANS_DP_VSYNC_ACTIVE_HIGH) 1468 flags |= DRM_MODE_FLAG_PVSYNC; 1469 else 1470 flags |= DRM_MODE_FLAG_NVSYNC; 1471 } 1472 1473 pipe_config->adjusted_mode.flags |= flags; 1474 1475 pipe_config->has_dp_encoder = true; 1476 1477 intel_dp_get_m_n(crtc, pipe_config); 1478 1479 if (port == PORT_A) { 1480 if ((I915_READ(DP_A) & DP_PLL_FREQ_MASK) == DP_PLL_FREQ_160MHZ) 1481 pipe_config->port_clock = 162000; 1482 else 1483 pipe_config->port_clock = 270000; 1484 } 1485 1486 dotclock = intel_dotclock_calculate(pipe_config->port_clock, 1487 &pipe_config->dp_m_n); 1488 1489 if (HAS_PCH_SPLIT(dev_priv->dev) && port != PORT_A) 1490 ironlake_check_encoder_dotclock(pipe_config, dotclock); 1491 1492 pipe_config->adjusted_mode.crtc_clock = dotclock; 1493 1494 if (is_edp(intel_dp) && dev_priv->vbt.edp_bpp && 1495 pipe_config->pipe_bpp > dev_priv->vbt.edp_bpp) { 1496 /* 1497 * This is a big fat ugly hack. 1498 * 1499 * Some machines in UEFI boot mode provide us a VBT that has 18 1500 * bpp and 1.62 GHz link bandwidth for eDP, which for reasons 1501 * unknown we fail to light up. Yet the same BIOS boots up with 1502 * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as 1503 * max, not what it tells us to use. 1504 * 1505 * Note: This will still be broken if the eDP panel is not lit 1506 * up by the BIOS, and thus we can't get the mode at module 1507 * load. 1508 */ 1509 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n", 1510 pipe_config->pipe_bpp, dev_priv->vbt.edp_bpp); 1511 dev_priv->vbt.edp_bpp = pipe_config->pipe_bpp; 1512 } 1513} 1514 1515static bool is_edp_psr(struct drm_device *dev) 1516{ 1517 struct drm_i915_private *dev_priv = dev->dev_private; 1518 1519 return dev_priv->psr.sink_support; 1520} 1521 1522static bool intel_edp_is_psr_enabled(struct drm_device *dev) 1523{ 1524 struct drm_i915_private *dev_priv = dev->dev_private; 1525 1526 if (!HAS_PSR(dev)) 1527 return false; 1528 1529 return I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE; 1530} 1531 1532static void intel_edp_psr_write_vsc(struct intel_dp *intel_dp, 1533 struct edp_vsc_psr *vsc_psr) 1534{ 1535 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 1536 struct drm_device *dev = dig_port->base.base.dev; 1537 struct drm_i915_private *dev_priv = dev->dev_private; 1538 struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc); 1539 u32 ctl_reg = HSW_TVIDEO_DIP_CTL(crtc->config.cpu_transcoder); 1540 u32 data_reg = HSW_TVIDEO_DIP_VSC_DATA(crtc->config.cpu_transcoder); 1541 uint32_t *data = (uint32_t *) vsc_psr; 1542 unsigned int i; 1543 1544 /* As per BSPec (Pipe Video Data Island Packet), we need to disable 1545 the video DIP being updated before program video DIP data buffer 1546 registers for DIP being updated. */ 1547 I915_WRITE(ctl_reg, 0); 1548 POSTING_READ(ctl_reg); 1549 1550 for (i = 0; i < VIDEO_DIP_VSC_DATA_SIZE; i += 4) { 1551 if (i < sizeof(struct edp_vsc_psr)) 1552 I915_WRITE(data_reg + i, *data++); 1553 else 1554 I915_WRITE(data_reg + i, 0); 1555 } 1556 1557 I915_WRITE(ctl_reg, VIDEO_DIP_ENABLE_VSC_HSW); 1558 POSTING_READ(ctl_reg); 1559} 1560 1561static void intel_edp_psr_setup(struct intel_dp *intel_dp) 1562{ 1563 struct drm_device *dev = intel_dp_to_dev(intel_dp); 1564 struct drm_i915_private *dev_priv = dev->dev_private; 1565 struct edp_vsc_psr psr_vsc; 1566 1567 if (intel_dp->psr_setup_done) 1568 return; 1569 1570 /* Prepare VSC packet as per EDP 1.3 spec, Table 3.10 */ 1571 memset(&psr_vsc, 0, sizeof(psr_vsc)); 1572 psr_vsc.sdp_header.HB0 = 0; 1573 psr_vsc.sdp_header.HB1 = 0x7; 1574 psr_vsc.sdp_header.HB2 = 0x2; 1575 psr_vsc.sdp_header.HB3 = 0x8; 1576 intel_edp_psr_write_vsc(intel_dp, &psr_vsc); 1577 1578 /* Avoid continuous PSR exit by masking memup and hpd */ 1579 I915_WRITE(EDP_PSR_DEBUG_CTL(dev), EDP_PSR_DEBUG_MASK_MEMUP | 1580 EDP_PSR_DEBUG_MASK_HPD | EDP_PSR_DEBUG_MASK_LPSP); 1581 1582 intel_dp->psr_setup_done = true; 1583} 1584 1585static void intel_edp_psr_enable_sink(struct intel_dp *intel_dp) 1586{ 1587 struct drm_device *dev = intel_dp_to_dev(intel_dp); 1588 struct drm_i915_private *dev_priv = dev->dev_private; 1589 uint32_t aux_clock_divider = get_aux_clock_divider(intel_dp, 0); 1590 int precharge = 0x3; 1591 int msg_size = 5; /* Header(4) + Message(1) */ 1592 1593 /* Enable PSR in sink */ 1594 if (intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT) 1595 intel_dp_aux_native_write_1(intel_dp, DP_PSR_EN_CFG, 1596 DP_PSR_ENABLE & 1597 ~DP_PSR_MAIN_LINK_ACTIVE); 1598 else 1599 intel_dp_aux_native_write_1(intel_dp, DP_PSR_EN_CFG, 1600 DP_PSR_ENABLE | 1601 DP_PSR_MAIN_LINK_ACTIVE); 1602 1603 /* Setup AUX registers */ 1604 I915_WRITE(EDP_PSR_AUX_DATA1(dev), EDP_PSR_DPCD_COMMAND); 1605 I915_WRITE(EDP_PSR_AUX_DATA2(dev), EDP_PSR_DPCD_NORMAL_OPERATION); 1606 I915_WRITE(EDP_PSR_AUX_CTL(dev), 1607 DP_AUX_CH_CTL_TIME_OUT_400us | 1608 (msg_size << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) | 1609 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) | 1610 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT)); 1611} 1612 1613static void intel_edp_psr_enable_source(struct intel_dp *intel_dp) 1614{ 1615 struct drm_device *dev = intel_dp_to_dev(intel_dp); 1616 struct drm_i915_private *dev_priv = dev->dev_private; 1617 uint32_t max_sleep_time = 0x1f; 1618 uint32_t idle_frames = 1; 1619 uint32_t val = 0x0; 1620 const uint32_t link_entry_time = EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES; 1621 1622 if (intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT) { 1623 val |= EDP_PSR_LINK_STANDBY; 1624 val |= EDP_PSR_TP2_TP3_TIME_0us; 1625 val |= EDP_PSR_TP1_TIME_0us; 1626 val |= EDP_PSR_SKIP_AUX_EXIT; 1627 } else 1628 val |= EDP_PSR_LINK_DISABLE; 1629 1630 I915_WRITE(EDP_PSR_CTL(dev), val | 1631 IS_BROADWELL(dev) ? 0 : link_entry_time | 1632 max_sleep_time << EDP_PSR_MAX_SLEEP_TIME_SHIFT | 1633 idle_frames << EDP_PSR_IDLE_FRAME_SHIFT | 1634 EDP_PSR_ENABLE); 1635} 1636 1637static bool intel_edp_psr_match_conditions(struct intel_dp *intel_dp) 1638{ 1639 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 1640 struct drm_device *dev = dig_port->base.base.dev; 1641 struct drm_i915_private *dev_priv = dev->dev_private; 1642 struct drm_crtc *crtc = dig_port->base.base.crtc; 1643 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 1644 struct drm_i915_gem_object *obj = to_intel_framebuffer(crtc->fb)->obj; 1645 struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base; 1646 1647 dev_priv->psr.source_ok = false; 1648 1649 if (!HAS_PSR(dev)) { 1650 DRM_DEBUG_KMS("PSR not supported on this platform\n"); 1651 return false; 1652 } 1653 1654 if ((intel_encoder->type != INTEL_OUTPUT_EDP) || 1655 (dig_port->port != PORT_A)) { 1656 DRM_DEBUG_KMS("HSW ties PSR to DDI A (eDP)\n"); 1657 return false; 1658 } 1659 1660 if (!i915_enable_psr) { 1661 DRM_DEBUG_KMS("PSR disable by flag\n"); 1662 return false; 1663 } 1664 1665 crtc = dig_port->base.base.crtc; 1666 if (crtc == NULL) { 1667 DRM_DEBUG_KMS("crtc not active for PSR\n"); 1668 return false; 1669 } 1670 1671 intel_crtc = to_intel_crtc(crtc); 1672 if (!intel_crtc_active(crtc)) { 1673 DRM_DEBUG_KMS("crtc not active for PSR\n"); 1674 return false; 1675 } 1676 1677 obj = to_intel_framebuffer(crtc->fb)->obj; 1678 if (obj->tiling_mode != I915_TILING_X || 1679 obj->fence_reg == I915_FENCE_REG_NONE) { 1680 DRM_DEBUG_KMS("PSR condition failed: fb not tiled or fenced\n"); 1681 return false; 1682 } 1683 1684 if (I915_READ(SPRCTL(intel_crtc->pipe)) & SPRITE_ENABLE) { 1685 DRM_DEBUG_KMS("PSR condition failed: Sprite is Enabled\n"); 1686 return false; 1687 } 1688 1689 if (I915_READ(HSW_STEREO_3D_CTL(intel_crtc->config.cpu_transcoder)) & 1690 S3D_ENABLE) { 1691 DRM_DEBUG_KMS("PSR condition failed: Stereo 3D is Enabled\n"); 1692 return false; 1693 } 1694 1695 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) { 1696 DRM_DEBUG_KMS("PSR condition failed: Interlaced is Enabled\n"); 1697 return false; 1698 } 1699 1700 dev_priv->psr.source_ok = true; 1701 return true; 1702} 1703 1704static void intel_edp_psr_do_enable(struct intel_dp *intel_dp) 1705{ 1706 struct drm_device *dev = intel_dp_to_dev(intel_dp); 1707 1708 if (!intel_edp_psr_match_conditions(intel_dp) || 1709 intel_edp_is_psr_enabled(dev)) 1710 return; 1711 1712 /* Setup PSR once */ 1713 intel_edp_psr_setup(intel_dp); 1714 1715 /* Enable PSR on the panel */ 1716 intel_edp_psr_enable_sink(intel_dp); 1717 1718 /* Enable PSR on the host */ 1719 intel_edp_psr_enable_source(intel_dp); 1720} 1721 1722void intel_edp_psr_enable(struct intel_dp *intel_dp) 1723{ 1724 struct drm_device *dev = intel_dp_to_dev(intel_dp); 1725 1726 if (intel_edp_psr_match_conditions(intel_dp) && 1727 !intel_edp_is_psr_enabled(dev)) 1728 intel_edp_psr_do_enable(intel_dp); 1729} 1730 1731void intel_edp_psr_disable(struct intel_dp *intel_dp) 1732{ 1733 struct drm_device *dev = intel_dp_to_dev(intel_dp); 1734 struct drm_i915_private *dev_priv = dev->dev_private; 1735 1736 if (!intel_edp_is_psr_enabled(dev)) 1737 return; 1738 1739 I915_WRITE(EDP_PSR_CTL(dev), 1740 I915_READ(EDP_PSR_CTL(dev)) & ~EDP_PSR_ENABLE); 1741 1742 /* Wait till PSR is idle */ 1743 if (_wait_for((I915_READ(EDP_PSR_STATUS_CTL(dev)) & 1744 EDP_PSR_STATUS_STATE_MASK) == 0, 2000, 10)) 1745 DRM_ERROR("Timed out waiting for PSR Idle State\n"); 1746} 1747 1748void intel_edp_psr_update(struct drm_device *dev) 1749{ 1750 struct intel_encoder *encoder; 1751 struct intel_dp *intel_dp = NULL; 1752 1753 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) 1754 if (encoder->type == INTEL_OUTPUT_EDP) { 1755 intel_dp = enc_to_intel_dp(&encoder->base); 1756 1757 if (!is_edp_psr(dev)) 1758 return; 1759 1760 if (!intel_edp_psr_match_conditions(intel_dp)) 1761 intel_edp_psr_disable(intel_dp); 1762 else 1763 if (!intel_edp_is_psr_enabled(dev)) 1764 intel_edp_psr_do_enable(intel_dp); 1765 } 1766} 1767 1768static void intel_disable_dp(struct intel_encoder *encoder) 1769{ 1770 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); 1771 enum port port = dp_to_dig_port(intel_dp)->port; 1772 struct drm_device *dev = encoder->base.dev; 1773 1774 /* Make sure the panel is off before trying to change the mode. But also 1775 * ensure that we have vdd while we switch off the panel. */ 1776 ironlake_edp_panel_vdd_on(intel_dp); 1777 ironlake_edp_backlight_off(intel_dp); 1778 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF); 1779 ironlake_edp_panel_off(intel_dp); 1780 1781 /* cpu edp my only be disable _after_ the cpu pipe/plane is disabled. */ 1782 if (!(port == PORT_A || IS_VALLEYVIEW(dev))) 1783 intel_dp_link_down(intel_dp); 1784} 1785 1786static void intel_post_disable_dp(struct intel_encoder *encoder) 1787{ 1788 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); 1789 enum port port = dp_to_dig_port(intel_dp)->port; 1790 struct drm_device *dev = encoder->base.dev; 1791 1792 if (port == PORT_A || IS_VALLEYVIEW(dev)) { 1793 intel_dp_link_down(intel_dp); 1794 if (!IS_VALLEYVIEW(dev)) 1795 ironlake_edp_pll_off(intel_dp); 1796 } 1797} 1798 1799static void intel_enable_dp(struct intel_encoder *encoder) 1800{ 1801 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); 1802 struct drm_device *dev = encoder->base.dev; 1803 struct drm_i915_private *dev_priv = dev->dev_private; 1804 uint32_t dp_reg = I915_READ(intel_dp->output_reg); 1805 1806 if (WARN_ON(dp_reg & DP_PORT_EN)) 1807 return; 1808 1809 ironlake_edp_panel_vdd_on(intel_dp); 1810 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON); 1811 intel_dp_start_link_train(intel_dp); 1812 ironlake_edp_panel_on(intel_dp); 1813 ironlake_edp_panel_vdd_off(intel_dp, true); 1814 intel_dp_complete_link_train(intel_dp); 1815 intel_dp_stop_link_train(intel_dp); 1816} 1817 1818static void g4x_enable_dp(struct intel_encoder *encoder) 1819{ 1820 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); 1821 1822 intel_enable_dp(encoder); 1823 ironlake_edp_backlight_on(intel_dp); 1824} 1825 1826static void vlv_enable_dp(struct intel_encoder *encoder) 1827{ 1828 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); 1829 1830 ironlake_edp_backlight_on(intel_dp); 1831} 1832 1833static void g4x_pre_enable_dp(struct intel_encoder *encoder) 1834{ 1835 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); 1836 struct intel_digital_port *dport = dp_to_dig_port(intel_dp); 1837 1838 if (dport->port == PORT_A) 1839 ironlake_edp_pll_on(intel_dp); 1840} 1841 1842static void vlv_pre_enable_dp(struct intel_encoder *encoder) 1843{ 1844 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); 1845 struct intel_digital_port *dport = dp_to_dig_port(intel_dp); 1846 struct drm_device *dev = encoder->base.dev; 1847 struct drm_i915_private *dev_priv = dev->dev_private; 1848 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc); 1849 enum dpio_channel port = vlv_dport_to_channel(dport); 1850 int pipe = intel_crtc->pipe; 1851 struct edp_power_seq power_seq; 1852 u32 val; 1853 1854 mutex_lock(&dev_priv->dpio_lock); 1855 1856 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(port)); 1857 val = 0; 1858 if (pipe) 1859 val |= (1<<21); 1860 else 1861 val &= ~(1<<21); 1862 val |= 0x001000c4; 1863 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW8(port), val); 1864 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW14(port), 0x00760018); 1865 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW23(port), 0x00400888); 1866 1867 mutex_unlock(&dev_priv->dpio_lock); 1868 1869 /* init power sequencer on this pipe and port */ 1870 intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq); 1871 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp, 1872 &power_seq); 1873 1874 intel_enable_dp(encoder); 1875 1876 vlv_wait_port_ready(dev_priv, dport); 1877} 1878 1879static void vlv_dp_pre_pll_enable(struct intel_encoder *encoder) 1880{ 1881 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base); 1882 struct drm_device *dev = encoder->base.dev; 1883 struct drm_i915_private *dev_priv = dev->dev_private; 1884 struct intel_crtc *intel_crtc = 1885 to_intel_crtc(encoder->base.crtc); 1886 enum dpio_channel port = vlv_dport_to_channel(dport); 1887 int pipe = intel_crtc->pipe; 1888 1889 /* Program Tx lane resets to default */ 1890 mutex_lock(&dev_priv->dpio_lock); 1891 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port), 1892 DPIO_PCS_TX_LANE2_RESET | 1893 DPIO_PCS_TX_LANE1_RESET); 1894 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port), 1895 DPIO_PCS_CLK_CRI_RXEB_EIOS_EN | 1896 DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN | 1897 (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT) | 1898 DPIO_PCS_CLK_SOFT_RESET); 1899 1900 /* Fix up inter-pair skew failure */ 1901 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW12(port), 0x00750f00); 1902 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW11(port), 0x00001500); 1903 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW14(port), 0x40400000); 1904 mutex_unlock(&dev_priv->dpio_lock); 1905} 1906 1907/* 1908 * Native read with retry for link status and receiver capability reads for 1909 * cases where the sink may still be asleep. 1910 */ 1911static bool 1912intel_dp_aux_native_read_retry(struct intel_dp *intel_dp, uint16_t address, 1913 uint8_t *recv, int recv_bytes) 1914{ 1915 int ret, i; 1916 1917 /* 1918 * Sinks are *supposed* to come up within 1ms from an off state, 1919 * but we're also supposed to retry 3 times per the spec. 1920 */ 1921 for (i = 0; i < 3; i++) { 1922 ret = intel_dp_aux_native_read(intel_dp, address, recv, 1923 recv_bytes); 1924 if (ret == recv_bytes) 1925 return true; 1926 msleep(1); 1927 } 1928 1929 return false; 1930} 1931 1932/* 1933 * Fetch AUX CH registers 0x202 - 0x207 which contain 1934 * link status information 1935 */ 1936static bool 1937intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE]) 1938{ 1939 return intel_dp_aux_native_read_retry(intel_dp, 1940 DP_LANE0_1_STATUS, 1941 link_status, 1942 DP_LINK_STATUS_SIZE); 1943} 1944 1945#if 0 1946static char *voltage_names[] = { 1947 "0.4V", "0.6V", "0.8V", "1.2V" 1948}; 1949static char *pre_emph_names[] = { 1950 "0dB", "3.5dB", "6dB", "9.5dB" 1951}; 1952static char *link_train_names[] = { 1953 "pattern 1", "pattern 2", "idle", "off" 1954}; 1955#endif 1956 1957/* 1958 * These are source-specific values; current Intel hardware supports 1959 * a maximum voltage of 800mV and a maximum pre-emphasis of 6dB 1960 */ 1961 1962static uint8_t 1963intel_dp_voltage_max(struct intel_dp *intel_dp) 1964{ 1965 struct drm_device *dev = intel_dp_to_dev(intel_dp); 1966 enum port port = dp_to_dig_port(intel_dp)->port; 1967 1968 if (IS_VALLEYVIEW(dev) || IS_BROADWELL(dev)) 1969 return DP_TRAIN_VOLTAGE_SWING_1200; 1970 else if (IS_GEN7(dev) && port == PORT_A) 1971 return DP_TRAIN_VOLTAGE_SWING_800; 1972 else if (HAS_PCH_CPT(dev) && port != PORT_A) 1973 return DP_TRAIN_VOLTAGE_SWING_1200; 1974 else 1975 return DP_TRAIN_VOLTAGE_SWING_800; 1976} 1977 1978static uint8_t 1979intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing) 1980{ 1981 struct drm_device *dev = intel_dp_to_dev(intel_dp); 1982 enum port port = dp_to_dig_port(intel_dp)->port; 1983 1984 if (IS_BROADWELL(dev)) { 1985 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) { 1986 case DP_TRAIN_VOLTAGE_SWING_400: 1987 case DP_TRAIN_VOLTAGE_SWING_600: 1988 return DP_TRAIN_PRE_EMPHASIS_6; 1989 case DP_TRAIN_VOLTAGE_SWING_800: 1990 return DP_TRAIN_PRE_EMPHASIS_3_5; 1991 case DP_TRAIN_VOLTAGE_SWING_1200: 1992 default: 1993 return DP_TRAIN_PRE_EMPHASIS_0; 1994 } 1995 } else if (IS_HASWELL(dev)) { 1996 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) { 1997 case DP_TRAIN_VOLTAGE_SWING_400: 1998 return DP_TRAIN_PRE_EMPHASIS_9_5; 1999 case DP_TRAIN_VOLTAGE_SWING_600: 2000 return DP_TRAIN_PRE_EMPHASIS_6; 2001 case DP_TRAIN_VOLTAGE_SWING_800: 2002 return DP_TRAIN_PRE_EMPHASIS_3_5; 2003 case DP_TRAIN_VOLTAGE_SWING_1200: 2004 default: 2005 return DP_TRAIN_PRE_EMPHASIS_0; 2006 } 2007 } else if (IS_VALLEYVIEW(dev)) { 2008 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) { 2009 case DP_TRAIN_VOLTAGE_SWING_400: 2010 return DP_TRAIN_PRE_EMPHASIS_9_5; 2011 case DP_TRAIN_VOLTAGE_SWING_600: 2012 return DP_TRAIN_PRE_EMPHASIS_6; 2013 case DP_TRAIN_VOLTAGE_SWING_800: 2014 return DP_TRAIN_PRE_EMPHASIS_3_5; 2015 case DP_TRAIN_VOLTAGE_SWING_1200: 2016 default: 2017 return DP_TRAIN_PRE_EMPHASIS_0; 2018 } 2019 } else if (IS_GEN7(dev) && port == PORT_A) { 2020 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) { 2021 case DP_TRAIN_VOLTAGE_SWING_400: 2022 return DP_TRAIN_PRE_EMPHASIS_6; 2023 case DP_TRAIN_VOLTAGE_SWING_600: 2024 case DP_TRAIN_VOLTAGE_SWING_800: 2025 return DP_TRAIN_PRE_EMPHASIS_3_5; 2026 default: 2027 return DP_TRAIN_PRE_EMPHASIS_0; 2028 } 2029 } else { 2030 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) { 2031 case DP_TRAIN_VOLTAGE_SWING_400: 2032 return DP_TRAIN_PRE_EMPHASIS_6; 2033 case DP_TRAIN_VOLTAGE_SWING_600: 2034 return DP_TRAIN_PRE_EMPHASIS_6; 2035 case DP_TRAIN_VOLTAGE_SWING_800: 2036 return DP_TRAIN_PRE_EMPHASIS_3_5; 2037 case DP_TRAIN_VOLTAGE_SWING_1200: 2038 default: 2039 return DP_TRAIN_PRE_EMPHASIS_0; 2040 } 2041 } 2042} 2043 2044static uint32_t intel_vlv_signal_levels(struct intel_dp *intel_dp) 2045{ 2046 struct drm_device *dev = intel_dp_to_dev(intel_dp); 2047 struct drm_i915_private *dev_priv = dev->dev_private; 2048 struct intel_digital_port *dport = dp_to_dig_port(intel_dp); 2049 struct intel_crtc *intel_crtc = 2050 to_intel_crtc(dport->base.base.crtc); 2051 unsigned long demph_reg_value, preemph_reg_value, 2052 uniqtranscale_reg_value; 2053 uint8_t train_set = intel_dp->train_set[0]; 2054 enum dpio_channel port = vlv_dport_to_channel(dport); 2055 int pipe = intel_crtc->pipe; 2056 2057 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) { 2058 case DP_TRAIN_PRE_EMPHASIS_0: 2059 preemph_reg_value = 0x0004000; 2060 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { 2061 case DP_TRAIN_VOLTAGE_SWING_400: 2062 demph_reg_value = 0x2B405555; 2063 uniqtranscale_reg_value = 0x552AB83A; 2064 break; 2065 case DP_TRAIN_VOLTAGE_SWING_600: 2066 demph_reg_value = 0x2B404040; 2067 uniqtranscale_reg_value = 0x5548B83A; 2068 break; 2069 case DP_TRAIN_VOLTAGE_SWING_800: 2070 demph_reg_value = 0x2B245555; 2071 uniqtranscale_reg_value = 0x5560B83A; 2072 break; 2073 case DP_TRAIN_VOLTAGE_SWING_1200: 2074 demph_reg_value = 0x2B405555; 2075 uniqtranscale_reg_value = 0x5598DA3A; 2076 break; 2077 default: 2078 return 0; 2079 } 2080 break; 2081 case DP_TRAIN_PRE_EMPHASIS_3_5: 2082 preemph_reg_value = 0x0002000; 2083 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { 2084 case DP_TRAIN_VOLTAGE_SWING_400: 2085 demph_reg_value = 0x2B404040; 2086 uniqtranscale_reg_value = 0x5552B83A; 2087 break; 2088 case DP_TRAIN_VOLTAGE_SWING_600: 2089 demph_reg_value = 0x2B404848; 2090 uniqtranscale_reg_value = 0x5580B83A; 2091 break; 2092 case DP_TRAIN_VOLTAGE_SWING_800: 2093 demph_reg_value = 0x2B404040; 2094 uniqtranscale_reg_value = 0x55ADDA3A; 2095 break; 2096 default: 2097 return 0; 2098 } 2099 break; 2100 case DP_TRAIN_PRE_EMPHASIS_6: 2101 preemph_reg_value = 0x0000000; 2102 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { 2103 case DP_TRAIN_VOLTAGE_SWING_400: 2104 demph_reg_value = 0x2B305555; 2105 uniqtranscale_reg_value = 0x5570B83A; 2106 break; 2107 case DP_TRAIN_VOLTAGE_SWING_600: 2108 demph_reg_value = 0x2B2B4040; 2109 uniqtranscale_reg_value = 0x55ADDA3A; 2110 break; 2111 default: 2112 return 0; 2113 } 2114 break; 2115 case DP_TRAIN_PRE_EMPHASIS_9_5: 2116 preemph_reg_value = 0x0006000; 2117 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { 2118 case DP_TRAIN_VOLTAGE_SWING_400: 2119 demph_reg_value = 0x1B405555; 2120 uniqtranscale_reg_value = 0x55ADDA3A; 2121 break; 2122 default: 2123 return 0; 2124 } 2125 break; 2126 default: 2127 return 0; 2128 } 2129 2130 mutex_lock(&dev_priv->dpio_lock); 2131 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x00000000); 2132 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW4(port), demph_reg_value); 2133 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(port), 2134 uniqtranscale_reg_value); 2135 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(port), 0x0C782040); 2136 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW11(port), 0x00030000); 2137 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), preemph_reg_value); 2138 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x80000000); 2139 mutex_unlock(&dev_priv->dpio_lock); 2140 2141 return 0; 2142} 2143 2144static void 2145intel_get_adjust_train(struct intel_dp *intel_dp, 2146 const uint8_t link_status[DP_LINK_STATUS_SIZE]) 2147{ 2148 uint8_t v = 0; 2149 uint8_t p = 0; 2150 int lane; 2151 uint8_t voltage_max; 2152 uint8_t preemph_max; 2153 2154 for (lane = 0; lane < intel_dp->lane_count; lane++) { 2155 uint8_t this_v = drm_dp_get_adjust_request_voltage(link_status, lane); 2156 uint8_t this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane); 2157 2158 if (this_v > v) 2159 v = this_v; 2160 if (this_p > p) 2161 p = this_p; 2162 } 2163 2164 voltage_max = intel_dp_voltage_max(intel_dp); 2165 if (v >= voltage_max) 2166 v = voltage_max | DP_TRAIN_MAX_SWING_REACHED; 2167 2168 preemph_max = intel_dp_pre_emphasis_max(intel_dp, v); 2169 if (p >= preemph_max) 2170 p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED; 2171 2172 for (lane = 0; lane < 4; lane++) 2173 intel_dp->train_set[lane] = v | p; 2174} 2175 2176static uint32_t 2177intel_gen4_signal_levels(uint8_t train_set) 2178{ 2179 uint32_t signal_levels = 0; 2180 2181 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { 2182 case DP_TRAIN_VOLTAGE_SWING_400: 2183 default: 2184 signal_levels |= DP_VOLTAGE_0_4; 2185 break; 2186 case DP_TRAIN_VOLTAGE_SWING_600: 2187 signal_levels |= DP_VOLTAGE_0_6; 2188 break; 2189 case DP_TRAIN_VOLTAGE_SWING_800: 2190 signal_levels |= DP_VOLTAGE_0_8; 2191 break; 2192 case DP_TRAIN_VOLTAGE_SWING_1200: 2193 signal_levels |= DP_VOLTAGE_1_2; 2194 break; 2195 } 2196 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) { 2197 case DP_TRAIN_PRE_EMPHASIS_0: 2198 default: 2199 signal_levels |= DP_PRE_EMPHASIS_0; 2200 break; 2201 case DP_TRAIN_PRE_EMPHASIS_3_5: 2202 signal_levels |= DP_PRE_EMPHASIS_3_5; 2203 break; 2204 case DP_TRAIN_PRE_EMPHASIS_6: 2205 signal_levels |= DP_PRE_EMPHASIS_6; 2206 break; 2207 case DP_TRAIN_PRE_EMPHASIS_9_5: 2208 signal_levels |= DP_PRE_EMPHASIS_9_5; 2209 break; 2210 } 2211 return signal_levels; 2212} 2213 2214/* Gen6's DP voltage swing and pre-emphasis control */ 2215static uint32_t 2216intel_gen6_edp_signal_levels(uint8_t train_set) 2217{ 2218 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK | 2219 DP_TRAIN_PRE_EMPHASIS_MASK); 2220 switch (signal_levels) { 2221 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0: 2222 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0: 2223 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B; 2224 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5: 2225 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B; 2226 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6: 2227 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6: 2228 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B; 2229 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5: 2230 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5: 2231 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B; 2232 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0: 2233 case DP_TRAIN_VOLTAGE_SWING_1200 | DP_TRAIN_PRE_EMPHASIS_0: 2234 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B; 2235 default: 2236 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:" 2237 "0x%x\n", signal_levels); 2238 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B; 2239 } 2240} 2241 2242/* Gen7's DP voltage swing and pre-emphasis control */ 2243static uint32_t 2244intel_gen7_edp_signal_levels(uint8_t train_set) 2245{ 2246 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK | 2247 DP_TRAIN_PRE_EMPHASIS_MASK); 2248 switch (signal_levels) { 2249 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0: 2250 return EDP_LINK_TRAIN_400MV_0DB_IVB; 2251 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5: 2252 return EDP_LINK_TRAIN_400MV_3_5DB_IVB; 2253 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6: 2254 return EDP_LINK_TRAIN_400MV_6DB_IVB; 2255 2256 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0: 2257 return EDP_LINK_TRAIN_600MV_0DB_IVB; 2258 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5: 2259 return EDP_LINK_TRAIN_600MV_3_5DB_IVB; 2260 2261 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0: 2262 return EDP_LINK_TRAIN_800MV_0DB_IVB; 2263 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5: 2264 return EDP_LINK_TRAIN_800MV_3_5DB_IVB; 2265 2266 default: 2267 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:" 2268 "0x%x\n", signal_levels); 2269 return EDP_LINK_TRAIN_500MV_0DB_IVB; 2270 } 2271} 2272 2273/* Gen7.5's (HSW) DP voltage swing and pre-emphasis control */ 2274static uint32_t 2275intel_hsw_signal_levels(uint8_t train_set) 2276{ 2277 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK | 2278 DP_TRAIN_PRE_EMPHASIS_MASK); 2279 switch (signal_levels) { 2280 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0: 2281 return DDI_BUF_EMP_400MV_0DB_HSW; 2282 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5: 2283 return DDI_BUF_EMP_400MV_3_5DB_HSW; 2284 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6: 2285 return DDI_BUF_EMP_400MV_6DB_HSW; 2286 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_9_5: 2287 return DDI_BUF_EMP_400MV_9_5DB_HSW; 2288 2289 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0: 2290 return DDI_BUF_EMP_600MV_0DB_HSW; 2291 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5: 2292 return DDI_BUF_EMP_600MV_3_5DB_HSW; 2293 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6: 2294 return DDI_BUF_EMP_600MV_6DB_HSW; 2295 2296 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0: 2297 return DDI_BUF_EMP_800MV_0DB_HSW; 2298 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5: 2299 return DDI_BUF_EMP_800MV_3_5DB_HSW; 2300 default: 2301 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:" 2302 "0x%x\n", signal_levels); 2303 return DDI_BUF_EMP_400MV_0DB_HSW; 2304 } 2305} 2306 2307static uint32_t 2308intel_bdw_signal_levels(uint8_t train_set) 2309{ 2310 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK | 2311 DP_TRAIN_PRE_EMPHASIS_MASK); 2312 switch (signal_levels) { 2313 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0: 2314 return DDI_BUF_EMP_400MV_0DB_BDW; /* Sel0 */ 2315 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5: 2316 return DDI_BUF_EMP_400MV_3_5DB_BDW; /* Sel1 */ 2317 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6: 2318 return DDI_BUF_EMP_400MV_6DB_BDW; /* Sel2 */ 2319 2320 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0: 2321 return DDI_BUF_EMP_600MV_0DB_BDW; /* Sel3 */ 2322 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5: 2323 return DDI_BUF_EMP_600MV_3_5DB_BDW; /* Sel4 */ 2324 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6: 2325 return DDI_BUF_EMP_600MV_6DB_BDW; /* Sel5 */ 2326 2327 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0: 2328 return DDI_BUF_EMP_800MV_0DB_BDW; /* Sel6 */ 2329 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5: 2330 return DDI_BUF_EMP_800MV_3_5DB_BDW; /* Sel7 */ 2331 2332 case DP_TRAIN_VOLTAGE_SWING_1200 | DP_TRAIN_PRE_EMPHASIS_0: 2333 return DDI_BUF_EMP_1200MV_0DB_BDW; /* Sel8 */ 2334 2335 default: 2336 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:" 2337 "0x%x\n", signal_levels); 2338 return DDI_BUF_EMP_400MV_0DB_BDW; /* Sel0 */ 2339 } 2340} 2341 2342/* Properly updates "DP" with the correct signal levels. */ 2343static void 2344intel_dp_set_signal_levels(struct intel_dp *intel_dp, uint32_t *DP) 2345{ 2346 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 2347 enum port port = intel_dig_port->port; 2348 struct drm_device *dev = intel_dig_port->base.base.dev; 2349 uint32_t signal_levels, mask; 2350 uint8_t train_set = intel_dp->train_set[0]; 2351 2352 if (IS_BROADWELL(dev)) { 2353 signal_levels = intel_bdw_signal_levels(train_set); 2354 mask = DDI_BUF_EMP_MASK; 2355 } else if (IS_HASWELL(dev)) { 2356 signal_levels = intel_hsw_signal_levels(train_set); 2357 mask = DDI_BUF_EMP_MASK; 2358 } else if (IS_VALLEYVIEW(dev)) { 2359 signal_levels = intel_vlv_signal_levels(intel_dp); 2360 mask = 0; 2361 } else if (IS_GEN7(dev) && port == PORT_A) { 2362 signal_levels = intel_gen7_edp_signal_levels(train_set); 2363 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_IVB; 2364 } else if (IS_GEN6(dev) && port == PORT_A) { 2365 signal_levels = intel_gen6_edp_signal_levels(train_set); 2366 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB; 2367 } else { 2368 signal_levels = intel_gen4_signal_levels(train_set); 2369 mask = DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK; 2370 } 2371 2372 DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels); 2373 2374 *DP = (*DP & ~mask) | signal_levels; 2375} 2376 2377static bool 2378intel_dp_set_link_train(struct intel_dp *intel_dp, 2379 uint32_t *DP, 2380 uint8_t dp_train_pat) 2381{ 2382 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 2383 struct drm_device *dev = intel_dig_port->base.base.dev; 2384 struct drm_i915_private *dev_priv = dev->dev_private; 2385 enum port port = intel_dig_port->port; 2386 uint8_t buf[sizeof(intel_dp->train_set) + 1]; 2387 int ret, len; 2388 2389 if (HAS_DDI(dev)) { 2390 uint32_t temp = I915_READ(DP_TP_CTL(port)); 2391 2392 if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE) 2393 temp |= DP_TP_CTL_SCRAMBLE_DISABLE; 2394 else 2395 temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE; 2396 2397 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK; 2398 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) { 2399 case DP_TRAINING_PATTERN_DISABLE: 2400 temp |= DP_TP_CTL_LINK_TRAIN_NORMAL; 2401 2402 break; 2403 case DP_TRAINING_PATTERN_1: 2404 temp |= DP_TP_CTL_LINK_TRAIN_PAT1; 2405 break; 2406 case DP_TRAINING_PATTERN_2: 2407 temp |= DP_TP_CTL_LINK_TRAIN_PAT2; 2408 break; 2409 case DP_TRAINING_PATTERN_3: 2410 temp |= DP_TP_CTL_LINK_TRAIN_PAT3; 2411 break; 2412 } 2413 I915_WRITE(DP_TP_CTL(port), temp); 2414 2415 } else if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) { 2416 *DP &= ~DP_LINK_TRAIN_MASK_CPT; 2417 2418 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) { 2419 case DP_TRAINING_PATTERN_DISABLE: 2420 *DP |= DP_LINK_TRAIN_OFF_CPT; 2421 break; 2422 case DP_TRAINING_PATTERN_1: 2423 *DP |= DP_LINK_TRAIN_PAT_1_CPT; 2424 break; 2425 case DP_TRAINING_PATTERN_2: 2426 *DP |= DP_LINK_TRAIN_PAT_2_CPT; 2427 break; 2428 case DP_TRAINING_PATTERN_3: 2429 DRM_ERROR("DP training pattern 3 not supported\n"); 2430 *DP |= DP_LINK_TRAIN_PAT_2_CPT; 2431 break; 2432 } 2433 2434 } else { 2435 *DP &= ~DP_LINK_TRAIN_MASK; 2436 2437 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) { 2438 case DP_TRAINING_PATTERN_DISABLE: 2439 *DP |= DP_LINK_TRAIN_OFF; 2440 break; 2441 case DP_TRAINING_PATTERN_1: 2442 *DP |= DP_LINK_TRAIN_PAT_1; 2443 break; 2444 case DP_TRAINING_PATTERN_2: 2445 *DP |= DP_LINK_TRAIN_PAT_2; 2446 break; 2447 case DP_TRAINING_PATTERN_3: 2448 DRM_ERROR("DP training pattern 3 not supported\n"); 2449 *DP |= DP_LINK_TRAIN_PAT_2; 2450 break; 2451 } 2452 } 2453 2454 I915_WRITE(intel_dp->output_reg, *DP); 2455 POSTING_READ(intel_dp->output_reg); 2456 2457 buf[0] = dp_train_pat; 2458 if ((dp_train_pat & DP_TRAINING_PATTERN_MASK) == 2459 DP_TRAINING_PATTERN_DISABLE) { 2460 /* don't write DP_TRAINING_LANEx_SET on disable */ 2461 len = 1; 2462 } else { 2463 /* DP_TRAINING_LANEx_SET follow DP_TRAINING_PATTERN_SET */ 2464 memcpy(buf + 1, intel_dp->train_set, intel_dp->lane_count); 2465 len = intel_dp->lane_count + 1; 2466 } 2467 2468 ret = intel_dp_aux_native_write(intel_dp, DP_TRAINING_PATTERN_SET, 2469 buf, len); 2470 2471 return ret == len; 2472} 2473 2474static bool 2475intel_dp_reset_link_train(struct intel_dp *intel_dp, uint32_t *DP, 2476 uint8_t dp_train_pat) 2477{ 2478 memset(intel_dp->train_set, 0, sizeof(intel_dp->train_set)); 2479 intel_dp_set_signal_levels(intel_dp, DP); 2480 return intel_dp_set_link_train(intel_dp, DP, dp_train_pat); 2481} 2482 2483static bool 2484intel_dp_update_link_train(struct intel_dp *intel_dp, uint32_t *DP, 2485 const uint8_t link_status[DP_LINK_STATUS_SIZE]) 2486{ 2487 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 2488 struct drm_device *dev = intel_dig_port->base.base.dev; 2489 struct drm_i915_private *dev_priv = dev->dev_private; 2490 int ret; 2491 2492 intel_get_adjust_train(intel_dp, link_status); 2493 intel_dp_set_signal_levels(intel_dp, DP); 2494 2495 I915_WRITE(intel_dp->output_reg, *DP); 2496 POSTING_READ(intel_dp->output_reg); 2497 2498 ret = intel_dp_aux_native_write(intel_dp, DP_TRAINING_LANE0_SET, 2499 intel_dp->train_set, 2500 intel_dp->lane_count); 2501 2502 return ret == intel_dp->lane_count; 2503} 2504 2505static void intel_dp_set_idle_link_train(struct intel_dp *intel_dp) 2506{ 2507 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 2508 struct drm_device *dev = intel_dig_port->base.base.dev; 2509 struct drm_i915_private *dev_priv = dev->dev_private; 2510 enum port port = intel_dig_port->port; 2511 uint32_t val; 2512 2513 if (!HAS_DDI(dev)) 2514 return; 2515 2516 val = I915_READ(DP_TP_CTL(port)); 2517 val &= ~DP_TP_CTL_LINK_TRAIN_MASK; 2518 val |= DP_TP_CTL_LINK_TRAIN_IDLE; 2519 I915_WRITE(DP_TP_CTL(port), val); 2520 2521 /* 2522 * On PORT_A we can have only eDP in SST mode. There the only reason 2523 * we need to set idle transmission mode is to work around a HW issue 2524 * where we enable the pipe while not in idle link-training mode. 2525 * In this case there is requirement to wait for a minimum number of 2526 * idle patterns to be sent. 2527 */ 2528 if (port == PORT_A) 2529 return; 2530 2531 if (wait_for((I915_READ(DP_TP_STATUS(port)) & DP_TP_STATUS_IDLE_DONE), 2532 1)) 2533 DRM_ERROR("Timed out waiting for DP idle patterns\n"); 2534} 2535 2536/* Enable corresponding port and start training pattern 1 */ 2537void 2538intel_dp_start_link_train(struct intel_dp *intel_dp) 2539{ 2540 struct drm_encoder *encoder = &dp_to_dig_port(intel_dp)->base.base; 2541 struct drm_device *dev = encoder->dev; 2542 int i; 2543 uint8_t voltage; 2544 int voltage_tries, loop_tries; 2545 uint32_t DP = intel_dp->DP; 2546 uint8_t link_config[2]; 2547 2548 if (HAS_DDI(dev)) 2549 intel_ddi_prepare_link_retrain(encoder); 2550 2551 /* Write the link configuration data */ 2552 link_config[0] = intel_dp->link_bw; 2553 link_config[1] = intel_dp->lane_count; 2554 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd)) 2555 link_config[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN; 2556 intel_dp_aux_native_write(intel_dp, DP_LINK_BW_SET, link_config, 2); 2557 2558 link_config[0] = 0; 2559 link_config[1] = DP_SET_ANSI_8B10B; 2560 intel_dp_aux_native_write(intel_dp, DP_DOWNSPREAD_CTRL, link_config, 2); 2561 2562 DP |= DP_PORT_EN; 2563 2564 /* clock recovery */ 2565 if (!intel_dp_reset_link_train(intel_dp, &DP, 2566 DP_TRAINING_PATTERN_1 | 2567 DP_LINK_SCRAMBLING_DISABLE)) { 2568 DRM_ERROR("failed to enable link training\n"); 2569 return; 2570 } 2571 2572 voltage = 0xff; 2573 voltage_tries = 0; 2574 loop_tries = 0; 2575 for (;;) { 2576 uint8_t link_status[DP_LINK_STATUS_SIZE]; 2577 2578 drm_dp_link_train_clock_recovery_delay(intel_dp->dpcd); 2579 if (!intel_dp_get_link_status(intel_dp, link_status)) { 2580 DRM_ERROR("failed to get link status\n"); 2581 break; 2582 } 2583 2584 if (drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) { 2585 DRM_DEBUG_KMS("clock recovery OK\n"); 2586 break; 2587 } 2588 2589 /* Check to see if we've tried the max voltage */ 2590 for (i = 0; i < intel_dp->lane_count; i++) 2591 if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0) 2592 break; 2593 if (i == intel_dp->lane_count) { 2594 ++loop_tries; 2595 if (loop_tries == 5) { 2596 DRM_ERROR("too many full retries, give up\n"); 2597 break; 2598 } 2599 intel_dp_reset_link_train(intel_dp, &DP, 2600 DP_TRAINING_PATTERN_1 | 2601 DP_LINK_SCRAMBLING_DISABLE); 2602 voltage_tries = 0; 2603 continue; 2604 } 2605 2606 /* Check to see if we've tried the same voltage 5 times */ 2607 if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) { 2608 ++voltage_tries; 2609 if (voltage_tries == 5) { 2610 DRM_ERROR("too many voltage retries, give up\n"); 2611 break; 2612 } 2613 } else 2614 voltage_tries = 0; 2615 voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK; 2616 2617 /* Update training set as requested by target */ 2618 if (!intel_dp_update_link_train(intel_dp, &DP, link_status)) { 2619 DRM_ERROR("failed to update link training\n"); 2620 break; 2621 } 2622 } 2623 2624 intel_dp->DP = DP; 2625} 2626 2627void 2628intel_dp_complete_link_train(struct intel_dp *intel_dp) 2629{ 2630 bool channel_eq = false; 2631 int tries, cr_tries; 2632 uint32_t DP = intel_dp->DP; 2633 2634 /* channel equalization */ 2635 if (!intel_dp_set_link_train(intel_dp, &DP, 2636 DP_TRAINING_PATTERN_2 | 2637 DP_LINK_SCRAMBLING_DISABLE)) { 2638 DRM_ERROR("failed to start channel equalization\n"); 2639 return; 2640 } 2641 2642 tries = 0; 2643 cr_tries = 0; 2644 channel_eq = false; 2645 for (;;) { 2646 uint8_t link_status[DP_LINK_STATUS_SIZE]; 2647 2648 if (cr_tries > 5) { 2649 DRM_ERROR("failed to train DP, aborting\n"); 2650 intel_dp_link_down(intel_dp); 2651 break; 2652 } 2653 2654 drm_dp_link_train_channel_eq_delay(intel_dp->dpcd); 2655 if (!intel_dp_get_link_status(intel_dp, link_status)) { 2656 DRM_ERROR("failed to get link status\n"); 2657 break; 2658 } 2659 2660 /* Make sure clock is still ok */ 2661 if (!drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) { 2662 intel_dp_start_link_train(intel_dp); 2663 intel_dp_set_link_train(intel_dp, &DP, 2664 DP_TRAINING_PATTERN_2 | 2665 DP_LINK_SCRAMBLING_DISABLE); 2666 cr_tries++; 2667 continue; 2668 } 2669 2670 if (drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) { 2671 channel_eq = true; 2672 break; 2673 } 2674 2675 /* Try 5 times, then try clock recovery if that fails */ 2676 if (tries > 5) { 2677 intel_dp_link_down(intel_dp); 2678 intel_dp_start_link_train(intel_dp); 2679 intel_dp_set_link_train(intel_dp, &DP, 2680 DP_TRAINING_PATTERN_2 | 2681 DP_LINK_SCRAMBLING_DISABLE); 2682 tries = 0; 2683 cr_tries++; 2684 continue; 2685 } 2686 2687 /* Update training set as requested by target */ 2688 if (!intel_dp_update_link_train(intel_dp, &DP, link_status)) { 2689 DRM_ERROR("failed to update link training\n"); 2690 break; 2691 } 2692 ++tries; 2693 } 2694 2695 intel_dp_set_idle_link_train(intel_dp); 2696 2697 intel_dp->DP = DP; 2698 2699 if (channel_eq) 2700 DRM_DEBUG_KMS("Channel EQ done. DP Training successful\n"); 2701 2702} 2703 2704void intel_dp_stop_link_train(struct intel_dp *intel_dp) 2705{ 2706 intel_dp_set_link_train(intel_dp, &intel_dp->DP, 2707 DP_TRAINING_PATTERN_DISABLE); 2708} 2709 2710static void 2711intel_dp_link_down(struct intel_dp *intel_dp) 2712{ 2713 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 2714 enum port port = intel_dig_port->port; 2715 struct drm_device *dev = intel_dig_port->base.base.dev; 2716 struct drm_i915_private *dev_priv = dev->dev_private; 2717 struct intel_crtc *intel_crtc = 2718 to_intel_crtc(intel_dig_port->base.base.crtc); 2719 uint32_t DP = intel_dp->DP; 2720 2721 /* 2722 * DDI code has a strict mode set sequence and we should try to respect 2723 * it, otherwise we might hang the machine in many different ways. So we 2724 * really should be disabling the port only on a complete crtc_disable 2725 * sequence. This function is just called under two conditions on DDI 2726 * code: 2727 * - Link train failed while doing crtc_enable, and on this case we 2728 * really should respect the mode set sequence and wait for a 2729 * crtc_disable. 2730 * - Someone turned the monitor off and intel_dp_check_link_status 2731 * called us. We don't need to disable the whole port on this case, so 2732 * when someone turns the monitor on again, 2733 * intel_ddi_prepare_link_retrain will take care of redoing the link 2734 * train. 2735 */ 2736 if (HAS_DDI(dev)) 2737 return; 2738 2739 if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0)) 2740 return; 2741 2742 DRM_DEBUG_KMS("\n"); 2743 2744 if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) { 2745 DP &= ~DP_LINK_TRAIN_MASK_CPT; 2746 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT); 2747 } else { 2748 DP &= ~DP_LINK_TRAIN_MASK; 2749 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE); 2750 } 2751 POSTING_READ(intel_dp->output_reg); 2752 2753 /* We don't really know why we're doing this */ 2754 intel_wait_for_vblank(dev, intel_crtc->pipe); 2755 2756 if (HAS_PCH_IBX(dev) && 2757 I915_READ(intel_dp->output_reg) & DP_PIPEB_SELECT) { 2758 struct drm_crtc *crtc = intel_dig_port->base.base.crtc; 2759 2760 /* Hardware workaround: leaving our transcoder select 2761 * set to transcoder B while it's off will prevent the 2762 * corresponding HDMI output on transcoder A. 2763 * 2764 * Combine this with another hardware workaround: 2765 * transcoder select bit can only be cleared while the 2766 * port is enabled. 2767 */ 2768 DP &= ~DP_PIPEB_SELECT; 2769 I915_WRITE(intel_dp->output_reg, DP); 2770 2771 /* Changes to enable or select take place the vblank 2772 * after being written. 2773 */ 2774 if (WARN_ON(crtc == NULL)) { 2775 /* We should never try to disable a port without a crtc 2776 * attached. For paranoia keep the code around for a 2777 * bit. */ 2778 POSTING_READ(intel_dp->output_reg); 2779 msleep(50); 2780 } else 2781 intel_wait_for_vblank(dev, intel_crtc->pipe); 2782 } 2783 2784 DP &= ~DP_AUDIO_OUTPUT_ENABLE; 2785 I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN); 2786 POSTING_READ(intel_dp->output_reg); 2787 msleep(intel_dp->panel_power_down_delay); 2788} 2789 2790static bool 2791intel_dp_get_dpcd(struct intel_dp *intel_dp) 2792{ 2793 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 2794 struct drm_device *dev = dig_port->base.base.dev; 2795 struct drm_i915_private *dev_priv = dev->dev_private; 2796 2797 char dpcd_hex_dump[sizeof(intel_dp->dpcd) * 3]; 2798 2799 if (intel_dp_aux_native_read_retry(intel_dp, 0x000, intel_dp->dpcd, 2800 sizeof(intel_dp->dpcd)) == 0) 2801 return false; /* aux transfer failed */ 2802 2803 hex_dump_to_buffer(intel_dp->dpcd, sizeof(intel_dp->dpcd), 2804 32, 1, dpcd_hex_dump, sizeof(dpcd_hex_dump), false); 2805 DRM_DEBUG_KMS("DPCD: %s\n", dpcd_hex_dump); 2806 2807 if (intel_dp->dpcd[DP_DPCD_REV] == 0) 2808 return false; /* DPCD not present */ 2809 2810 /* Check if the panel supports PSR */ 2811 memset(intel_dp->psr_dpcd, 0, sizeof(intel_dp->psr_dpcd)); 2812 if (is_edp(intel_dp)) { 2813 intel_dp_aux_native_read_retry(intel_dp, DP_PSR_SUPPORT, 2814 intel_dp->psr_dpcd, 2815 sizeof(intel_dp->psr_dpcd)); 2816 if (intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED) { 2817 dev_priv->psr.sink_support = true; 2818 DRM_DEBUG_KMS("Detected EDP PSR Panel.\n"); 2819 } 2820 } 2821 2822 if (!(intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] & 2823 DP_DWN_STRM_PORT_PRESENT)) 2824 return true; /* native DP sink */ 2825 2826 if (intel_dp->dpcd[DP_DPCD_REV] == 0x10) 2827 return true; /* no per-port downstream info */ 2828 2829 if (intel_dp_aux_native_read_retry(intel_dp, DP_DOWNSTREAM_PORT_0, 2830 intel_dp->downstream_ports, 2831 DP_MAX_DOWNSTREAM_PORTS) == 0) 2832 return false; /* downstream port status fetch failed */ 2833 2834 return true; 2835} 2836 2837static void 2838intel_dp_probe_oui(struct intel_dp *intel_dp) 2839{ 2840 u8 buf[3]; 2841 2842 if (!(intel_dp->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT)) 2843 return; 2844 2845 ironlake_edp_panel_vdd_on(intel_dp); 2846 2847 if (intel_dp_aux_native_read_retry(intel_dp, DP_SINK_OUI, buf, 3)) 2848 DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n", 2849 buf[0], buf[1], buf[2]); 2850 2851 if (intel_dp_aux_native_read_retry(intel_dp, DP_BRANCH_OUI, buf, 3)) 2852 DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n", 2853 buf[0], buf[1], buf[2]); 2854 2855 ironlake_edp_panel_vdd_off(intel_dp, false); 2856} 2857 2858static bool 2859intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector) 2860{ 2861 int ret; 2862 2863 ret = intel_dp_aux_native_read_retry(intel_dp, 2864 DP_DEVICE_SERVICE_IRQ_VECTOR, 2865 sink_irq_vector, 1); 2866 if (!ret) 2867 return false; 2868 2869 return true; 2870} 2871 2872static void 2873intel_dp_handle_test_request(struct intel_dp *intel_dp) 2874{ 2875 /* NAK by default */ 2876 intel_dp_aux_native_write_1(intel_dp, DP_TEST_RESPONSE, DP_TEST_NAK); 2877} 2878 2879/* 2880 * According to DP spec 2881 * 5.1.2: 2882 * 1. Read DPCD 2883 * 2. Configure link according to Receiver Capabilities 2884 * 3. Use Link Training from 2.5.3.3 and 3.5.1.3 2885 * 4. Check link status on receipt of hot-plug interrupt 2886 */ 2887 2888void 2889intel_dp_check_link_status(struct intel_dp *intel_dp) 2890{ 2891 struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base; 2892 u8 sink_irq_vector; 2893 u8 link_status[DP_LINK_STATUS_SIZE]; 2894 2895 if (!intel_encoder->connectors_active) 2896 return; 2897 2898 if (WARN_ON(!intel_encoder->base.crtc)) 2899 return; 2900 2901 /* Try to read receiver status if the link appears to be up */ 2902 if (!intel_dp_get_link_status(intel_dp, link_status)) { 2903 intel_dp_link_down(intel_dp); 2904 return; 2905 } 2906 2907 /* Now read the DPCD to see if it's actually running */ 2908 if (!intel_dp_get_dpcd(intel_dp)) { 2909 intel_dp_link_down(intel_dp); 2910 return; 2911 } 2912 2913 /* Try to read the source of the interrupt */ 2914 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 && 2915 intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) { 2916 /* Clear interrupt source */ 2917 intel_dp_aux_native_write_1(intel_dp, 2918 DP_DEVICE_SERVICE_IRQ_VECTOR, 2919 sink_irq_vector); 2920 2921 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST) 2922 intel_dp_handle_test_request(intel_dp); 2923 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ)) 2924 DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n"); 2925 } 2926 2927 if (!drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) { 2928 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n", 2929 drm_get_encoder_name(&intel_encoder->base)); 2930 intel_dp_start_link_train(intel_dp); 2931 intel_dp_complete_link_train(intel_dp); 2932 intel_dp_stop_link_train(intel_dp); 2933 } 2934} 2935 2936/* XXX this is probably wrong for multiple downstream ports */ 2937static enum drm_connector_status 2938intel_dp_detect_dpcd(struct intel_dp *intel_dp) 2939{ 2940 uint8_t *dpcd = intel_dp->dpcd; 2941 uint8_t type; 2942 2943 if (!intel_dp_get_dpcd(intel_dp)) 2944 return connector_status_disconnected; 2945 2946 /* if there's no downstream port, we're done */ 2947 if (!(dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT)) 2948 return connector_status_connected; 2949 2950 /* If we're HPD-aware, SINK_COUNT changes dynamically */ 2951 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 && 2952 intel_dp->downstream_ports[0] & DP_DS_PORT_HPD) { 2953 uint8_t reg; 2954 if (!intel_dp_aux_native_read_retry(intel_dp, DP_SINK_COUNT, 2955 ®, 1)) 2956 return connector_status_unknown; 2957 return DP_GET_SINK_COUNT(reg) ? connector_status_connected 2958 : connector_status_disconnected; 2959 } 2960 2961 /* If no HPD, poke DDC gently */ 2962 if (drm_probe_ddc(&intel_dp->adapter)) 2963 return connector_status_connected; 2964 2965 /* Well we tried, say unknown for unreliable port types */ 2966 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) { 2967 type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK; 2968 if (type == DP_DS_PORT_TYPE_VGA || 2969 type == DP_DS_PORT_TYPE_NON_EDID) 2970 return connector_status_unknown; 2971 } else { 2972 type = intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] & 2973 DP_DWN_STRM_PORT_TYPE_MASK; 2974 if (type == DP_DWN_STRM_PORT_TYPE_ANALOG || 2975 type == DP_DWN_STRM_PORT_TYPE_OTHER) 2976 return connector_status_unknown; 2977 } 2978 2979 /* Anything else is out of spec, warn and ignore */ 2980 DRM_DEBUG_KMS("Broken DP branch device, ignoring\n"); 2981 return connector_status_disconnected; 2982} 2983 2984static enum drm_connector_status 2985ironlake_dp_detect(struct intel_dp *intel_dp) 2986{ 2987 struct drm_device *dev = intel_dp_to_dev(intel_dp); 2988 struct drm_i915_private *dev_priv = dev->dev_private; 2989 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 2990 enum drm_connector_status status; 2991 2992 /* Can't disconnect eDP, but you can close the lid... */ 2993 if (is_edp(intel_dp)) { 2994 status = intel_panel_detect(dev); 2995 if (status == connector_status_unknown) 2996 status = connector_status_connected; 2997 return status; 2998 } 2999 3000 if (!ibx_digital_port_connected(dev_priv, intel_dig_port)) 3001 return connector_status_disconnected; 3002 3003 return intel_dp_detect_dpcd(intel_dp); 3004} 3005 3006static enum drm_connector_status 3007g4x_dp_detect(struct intel_dp *intel_dp) 3008{ 3009 struct drm_device *dev = intel_dp_to_dev(intel_dp); 3010 struct drm_i915_private *dev_priv = dev->dev_private; 3011 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 3012 uint32_t bit; 3013 3014 /* Can't disconnect eDP, but you can close the lid... */ 3015 if (is_edp(intel_dp)) { 3016 enum drm_connector_status status; 3017 3018 status = intel_panel_detect(dev); 3019 if (status == connector_status_unknown) 3020 status = connector_status_connected; 3021 return status; 3022 } 3023 3024 switch (intel_dig_port->port) { 3025 case PORT_B: 3026 bit = PORTB_HOTPLUG_LIVE_STATUS; 3027 break; 3028 case PORT_C: 3029 bit = PORTC_HOTPLUG_LIVE_STATUS; 3030 break; 3031 case PORT_D: 3032 bit = PORTD_HOTPLUG_LIVE_STATUS; 3033 break; 3034 default: 3035 return connector_status_unknown; 3036 } 3037 3038 if ((I915_READ(PORT_HOTPLUG_STAT) & bit) == 0) 3039 return connector_status_disconnected; 3040 3041 return intel_dp_detect_dpcd(intel_dp); 3042} 3043 3044static struct edid * 3045intel_dp_get_edid(struct drm_connector *connector, struct i2c_adapter *adapter) 3046{ 3047 struct intel_connector *intel_connector = to_intel_connector(connector); 3048 3049 /* use cached edid if we have one */ 3050 if (intel_connector->edid) { 3051 /* invalid edid */ 3052 if (IS_ERR(intel_connector->edid)) 3053 return NULL; 3054 3055 return drm_edid_duplicate(intel_connector->edid); 3056 } 3057 3058 return drm_get_edid(connector, adapter); 3059} 3060 3061static int 3062intel_dp_get_edid_modes(struct drm_connector *connector, struct i2c_adapter *adapter) 3063{ 3064 struct intel_connector *intel_connector = to_intel_connector(connector); 3065 3066 /* use cached edid if we have one */ 3067 if (intel_connector->edid) { 3068 /* invalid edid */ 3069 if (IS_ERR(intel_connector->edid)) 3070 return 0; 3071 3072 return intel_connector_update_modes(connector, 3073 intel_connector->edid); 3074 } 3075 3076 return intel_ddc_get_modes(connector, adapter); 3077} 3078 3079static enum drm_connector_status 3080intel_dp_detect(struct drm_connector *connector, bool force) 3081{ 3082 struct intel_dp *intel_dp = intel_attached_dp(connector); 3083 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 3084 struct intel_encoder *intel_encoder = &intel_dig_port->base; 3085 struct drm_device *dev = connector->dev; 3086 enum drm_connector_status status; 3087 struct edid *edid = NULL; 3088 3089 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", 3090 connector->base.id, drm_get_connector_name(connector)); 3091 3092 intel_dp->has_audio = false; 3093 3094 if (HAS_PCH_SPLIT(dev)) 3095 status = ironlake_dp_detect(intel_dp); 3096 else 3097 status = g4x_dp_detect(intel_dp); 3098 3099 if (status != connector_status_connected) 3100 return status; 3101 3102 intel_dp_probe_oui(intel_dp); 3103 3104 if (intel_dp->force_audio != HDMI_AUDIO_AUTO) { 3105 intel_dp->has_audio = (intel_dp->force_audio == HDMI_AUDIO_ON); 3106 } else { 3107 edid = intel_dp_get_edid(connector, &intel_dp->adapter); 3108 if (edid) { 3109 intel_dp->has_audio = drm_detect_monitor_audio(edid); 3110 kfree(edid); 3111 } 3112 } 3113 3114 if (intel_encoder->type != INTEL_OUTPUT_EDP) 3115 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT; 3116 return connector_status_connected; 3117} 3118 3119static int intel_dp_get_modes(struct drm_connector *connector) 3120{ 3121 struct intel_dp *intel_dp = intel_attached_dp(connector); 3122 struct intel_connector *intel_connector = to_intel_connector(connector); 3123 struct drm_device *dev = connector->dev; 3124 int ret; 3125 3126 /* We should parse the EDID data and find out if it has an audio sink 3127 */ 3128 3129 ret = intel_dp_get_edid_modes(connector, &intel_dp->adapter); 3130 if (ret) 3131 return ret; 3132 3133 /* if eDP has no EDID, fall back to fixed mode */ 3134 if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) { 3135 struct drm_display_mode *mode; 3136 mode = drm_mode_duplicate(dev, 3137 intel_connector->panel.fixed_mode); 3138 if (mode) { 3139 drm_mode_probed_add(connector, mode); 3140 return 1; 3141 } 3142 } 3143 return 0; 3144} 3145 3146static bool 3147intel_dp_detect_audio(struct drm_connector *connector) 3148{ 3149 struct intel_dp *intel_dp = intel_attached_dp(connector); 3150 struct edid *edid; 3151 bool has_audio = false; 3152 3153 edid = intel_dp_get_edid(connector, &intel_dp->adapter); 3154 if (edid) { 3155 has_audio = drm_detect_monitor_audio(edid); 3156 kfree(edid); 3157 } 3158 3159 return has_audio; 3160} 3161 3162static int 3163intel_dp_set_property(struct drm_connector *connector, 3164 struct drm_property *property, 3165 uint64_t val) 3166{ 3167 struct drm_i915_private *dev_priv = connector->dev->dev_private; 3168 struct intel_connector *intel_connector = to_intel_connector(connector); 3169 struct intel_encoder *intel_encoder = intel_attached_encoder(connector); 3170 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base); 3171 int ret; 3172 3173 ret = drm_object_property_set_value(&connector->base, property, val); 3174 if (ret) 3175 return ret; 3176 3177 if (property == dev_priv->force_audio_property) { 3178 int i = val; 3179 bool has_audio; 3180 3181 if (i == intel_dp->force_audio) 3182 return 0; 3183 3184 intel_dp->force_audio = i; 3185 3186 if (i == HDMI_AUDIO_AUTO) 3187 has_audio = intel_dp_detect_audio(connector); 3188 else 3189 has_audio = (i == HDMI_AUDIO_ON); 3190 3191 if (has_audio == intel_dp->has_audio) 3192 return 0; 3193 3194 intel_dp->has_audio = has_audio; 3195 goto done; 3196 } 3197 3198 if (property == dev_priv->broadcast_rgb_property) { 3199 bool old_auto = intel_dp->color_range_auto; 3200 uint32_t old_range = intel_dp->color_range; 3201 3202 switch (val) { 3203 case INTEL_BROADCAST_RGB_AUTO: 3204 intel_dp->color_range_auto = true; 3205 break; 3206 case INTEL_BROADCAST_RGB_FULL: 3207 intel_dp->color_range_auto = false; 3208 intel_dp->color_range = 0; 3209 break; 3210 case INTEL_BROADCAST_RGB_LIMITED: 3211 intel_dp->color_range_auto = false; 3212 intel_dp->color_range = DP_COLOR_RANGE_16_235; 3213 break; 3214 default: 3215 return -EINVAL; 3216 } 3217 3218 if (old_auto == intel_dp->color_range_auto && 3219 old_range == intel_dp->color_range) 3220 return 0; 3221 3222 goto done; 3223 } 3224 3225 if (is_edp(intel_dp) && 3226 property == connector->dev->mode_config.scaling_mode_property) { 3227 if (val == DRM_MODE_SCALE_NONE) { 3228 DRM_DEBUG_KMS("no scaling not supported\n"); 3229 return -EINVAL; 3230 } 3231 3232 if (intel_connector->panel.fitting_mode == val) { 3233 /* the eDP scaling property is not changed */ 3234 return 0; 3235 } 3236 intel_connector->panel.fitting_mode = val; 3237 3238 goto done; 3239 } 3240 3241 return -EINVAL; 3242 3243done: 3244 if (intel_encoder->base.crtc) 3245 intel_crtc_restore_mode(intel_encoder->base.crtc); 3246 3247 return 0; 3248} 3249 3250static void 3251intel_dp_connector_destroy(struct drm_connector *connector) 3252{ 3253 struct intel_connector *intel_connector = to_intel_connector(connector); 3254 3255 if (!IS_ERR_OR_NULL(intel_connector->edid)) 3256 kfree(intel_connector->edid); 3257 3258 /* Can't call is_edp() since the encoder may have been destroyed 3259 * already. */ 3260 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) 3261 intel_panel_fini(&intel_connector->panel); 3262 3263 drm_connector_cleanup(connector); 3264 kfree(connector); 3265} 3266 3267void intel_dp_encoder_destroy(struct drm_encoder *encoder) 3268{ 3269 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); 3270 struct intel_dp *intel_dp = &intel_dig_port->dp; 3271 struct drm_device *dev = intel_dp_to_dev(intel_dp); 3272 3273 i2c_del_adapter(&intel_dp->adapter); 3274 drm_encoder_cleanup(encoder); 3275 if (is_edp(intel_dp)) { 3276 cancel_delayed_work_sync(&intel_dp->panel_vdd_work); 3277 mutex_lock(&dev->mode_config.mutex); 3278 ironlake_panel_vdd_off_sync(intel_dp); 3279 mutex_unlock(&dev->mode_config.mutex); 3280 } 3281 kfree(intel_dig_port); 3282} 3283 3284static const struct drm_connector_funcs intel_dp_connector_funcs = { 3285 .dpms = intel_connector_dpms, 3286 .detect = intel_dp_detect, 3287 .fill_modes = drm_helper_probe_single_connector_modes, 3288 .set_property = intel_dp_set_property, 3289 .destroy = intel_dp_connector_destroy, 3290}; 3291 3292static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = { 3293 .get_modes = intel_dp_get_modes, 3294 .mode_valid = intel_dp_mode_valid, 3295 .best_encoder = intel_best_encoder, 3296}; 3297 3298static const struct drm_encoder_funcs intel_dp_enc_funcs = { 3299 .destroy = intel_dp_encoder_destroy, 3300}; 3301 3302static void 3303intel_dp_hot_plug(struct intel_encoder *intel_encoder) 3304{ 3305 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base); 3306 3307 intel_dp_check_link_status(intel_dp); 3308} 3309 3310/* Return which DP Port should be selected for Transcoder DP control */ 3311int 3312intel_trans_dp_port_sel(struct drm_crtc *crtc) 3313{ 3314 struct drm_device *dev = crtc->dev; 3315 struct intel_encoder *intel_encoder; 3316 struct intel_dp *intel_dp; 3317 3318 for_each_encoder_on_crtc(dev, crtc, intel_encoder) { 3319 intel_dp = enc_to_intel_dp(&intel_encoder->base); 3320 3321 if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT || 3322 intel_encoder->type == INTEL_OUTPUT_EDP) 3323 return intel_dp->output_reg; 3324 } 3325 3326 return -1; 3327} 3328 3329/* check the VBT to see whether the eDP is on DP-D port */ 3330bool intel_dp_is_edp(struct drm_device *dev, enum port port) 3331{ 3332 struct drm_i915_private *dev_priv = dev->dev_private; 3333 union child_device_config *p_child; 3334 int i; 3335 static const short port_mapping[] = { 3336 [PORT_B] = PORT_IDPB, 3337 [PORT_C] = PORT_IDPC, 3338 [PORT_D] = PORT_IDPD, 3339 }; 3340 3341 if (port == PORT_A) 3342 return true; 3343 3344 if (!dev_priv->vbt.child_dev_num) 3345 return false; 3346 3347 for (i = 0; i < dev_priv->vbt.child_dev_num; i++) { 3348 p_child = dev_priv->vbt.child_dev + i; 3349 3350 if (p_child->common.dvo_port == port_mapping[port] && 3351 (p_child->common.device_type & DEVICE_TYPE_eDP_BITS) == 3352 (DEVICE_TYPE_eDP & DEVICE_TYPE_eDP_BITS)) 3353 return true; 3354 } 3355 return false; 3356} 3357 3358static void 3359intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector) 3360{ 3361 struct intel_connector *intel_connector = to_intel_connector(connector); 3362 3363 intel_attach_force_audio_property(connector); 3364 intel_attach_broadcast_rgb_property(connector); 3365 intel_dp->color_range_auto = true; 3366 3367 if (is_edp(intel_dp)) { 3368 drm_mode_create_scaling_mode_property(connector->dev); 3369 drm_object_attach_property( 3370 &connector->base, 3371 connector->dev->mode_config.scaling_mode_property, 3372 DRM_MODE_SCALE_ASPECT); 3373 intel_connector->panel.fitting_mode = DRM_MODE_SCALE_ASPECT; 3374 } 3375} 3376 3377static void 3378intel_dp_init_panel_power_sequencer(struct drm_device *dev, 3379 struct intel_dp *intel_dp, 3380 struct edp_power_seq *out) 3381{ 3382 struct drm_i915_private *dev_priv = dev->dev_private; 3383 struct edp_power_seq cur, vbt, spec, final; 3384 u32 pp_on, pp_off, pp_div, pp; 3385 int pp_ctrl_reg, pp_on_reg, pp_off_reg, pp_div_reg; 3386 3387 if (HAS_PCH_SPLIT(dev)) { 3388 pp_ctrl_reg = PCH_PP_CONTROL; 3389 pp_on_reg = PCH_PP_ON_DELAYS; 3390 pp_off_reg = PCH_PP_OFF_DELAYS; 3391 pp_div_reg = PCH_PP_DIVISOR; 3392 } else { 3393 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp); 3394 3395 pp_ctrl_reg = VLV_PIPE_PP_CONTROL(pipe); 3396 pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe); 3397 pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe); 3398 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe); 3399 } 3400 3401 /* Workaround: Need to write PP_CONTROL with the unlock key as 3402 * the very first thing. */ 3403 pp = ironlake_get_pp_control(intel_dp); 3404 I915_WRITE(pp_ctrl_reg, pp); 3405 3406 pp_on = I915_READ(pp_on_reg); 3407 pp_off = I915_READ(pp_off_reg); 3408 pp_div = I915_READ(pp_div_reg); 3409 3410 /* Pull timing values out of registers */ 3411 cur.t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >> 3412 PANEL_POWER_UP_DELAY_SHIFT; 3413 3414 cur.t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >> 3415 PANEL_LIGHT_ON_DELAY_SHIFT; 3416 3417 cur.t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >> 3418 PANEL_LIGHT_OFF_DELAY_SHIFT; 3419 3420 cur.t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >> 3421 PANEL_POWER_DOWN_DELAY_SHIFT; 3422 3423 cur.t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >> 3424 PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000; 3425 3426 DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n", 3427 cur.t1_t3, cur.t8, cur.t9, cur.t10, cur.t11_t12); 3428 3429 vbt = dev_priv->vbt.edp_pps; 3430 3431 /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of 3432 * our hw here, which are all in 100usec. */ 3433 spec.t1_t3 = 210 * 10; 3434 spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */ 3435 spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */ 3436 spec.t10 = 500 * 10; 3437 /* This one is special and actually in units of 100ms, but zero 3438 * based in the hw (so we need to add 100 ms). But the sw vbt 3439 * table multiplies it with 1000 to make it in units of 100usec, 3440 * too. */ 3441 spec.t11_t12 = (510 + 100) * 10; 3442 3443 DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n", 3444 vbt.t1_t3, vbt.t8, vbt.t9, vbt.t10, vbt.t11_t12); 3445 3446 /* Use the max of the register settings and vbt. If both are 3447 * unset, fall back to the spec limits. */ 3448#define assign_final(field) final.field = (max(cur.field, vbt.field) == 0 ? \ 3449 spec.field : \ 3450 max(cur.field, vbt.field)) 3451 assign_final(t1_t3); 3452 assign_final(t8); 3453 assign_final(t9); 3454 assign_final(t10); 3455 assign_final(t11_t12); 3456#undef assign_final 3457 3458#define get_delay(field) (DIV_ROUND_UP(final.field, 10)) 3459 intel_dp->panel_power_up_delay = get_delay(t1_t3); 3460 intel_dp->backlight_on_delay = get_delay(t8); 3461 intel_dp->backlight_off_delay = get_delay(t9); 3462 intel_dp->panel_power_down_delay = get_delay(t10); 3463 intel_dp->panel_power_cycle_delay = get_delay(t11_t12); 3464#undef get_delay 3465 3466 DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n", 3467 intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay, 3468 intel_dp->panel_power_cycle_delay); 3469 3470 DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n", 3471 intel_dp->backlight_on_delay, intel_dp->backlight_off_delay); 3472 3473 if (out) 3474 *out = final; 3475} 3476 3477static void 3478intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev, 3479 struct intel_dp *intel_dp, 3480 struct edp_power_seq *seq) 3481{ 3482 struct drm_i915_private *dev_priv = dev->dev_private; 3483 u32 pp_on, pp_off, pp_div, port_sel = 0; 3484 int div = HAS_PCH_SPLIT(dev) ? intel_pch_rawclk(dev) : intel_hrawclk(dev); 3485 int pp_on_reg, pp_off_reg, pp_div_reg; 3486 3487 if (HAS_PCH_SPLIT(dev)) { 3488 pp_on_reg = PCH_PP_ON_DELAYS; 3489 pp_off_reg = PCH_PP_OFF_DELAYS; 3490 pp_div_reg = PCH_PP_DIVISOR; 3491 } else { 3492 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp); 3493 3494 pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe); 3495 pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe); 3496 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe); 3497 } 3498 3499 /* And finally store the new values in the power sequencer. */ 3500 pp_on = (seq->t1_t3 << PANEL_POWER_UP_DELAY_SHIFT) | 3501 (seq->t8 << PANEL_LIGHT_ON_DELAY_SHIFT); 3502 pp_off = (seq->t9 << PANEL_LIGHT_OFF_DELAY_SHIFT) | 3503 (seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT); 3504 /* Compute the divisor for the pp clock, simply match the Bspec 3505 * formula. */ 3506 pp_div = ((100 * div)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT; 3507 pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000) 3508 << PANEL_POWER_CYCLE_DELAY_SHIFT); 3509 3510 /* Haswell doesn't have any port selection bits for the panel 3511 * power sequencer any more. */ 3512 if (IS_VALLEYVIEW(dev)) { 3513 if (dp_to_dig_port(intel_dp)->port == PORT_B) 3514 port_sel = PANEL_PORT_SELECT_DPB_VLV; 3515 else 3516 port_sel = PANEL_PORT_SELECT_DPC_VLV; 3517 } else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) { 3518 if (dp_to_dig_port(intel_dp)->port == PORT_A) 3519 port_sel = PANEL_PORT_SELECT_DPA; 3520 else 3521 port_sel = PANEL_PORT_SELECT_DPD; 3522 } 3523 3524 pp_on |= port_sel; 3525 3526 I915_WRITE(pp_on_reg, pp_on); 3527 I915_WRITE(pp_off_reg, pp_off); 3528 I915_WRITE(pp_div_reg, pp_div); 3529 3530 DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n", 3531 I915_READ(pp_on_reg), 3532 I915_READ(pp_off_reg), 3533 I915_READ(pp_div_reg)); 3534} 3535 3536static bool intel_edp_init_connector(struct intel_dp *intel_dp, 3537 struct intel_connector *intel_connector) 3538{ 3539 struct drm_connector *connector = &intel_connector->base; 3540 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 3541 struct drm_device *dev = intel_dig_port->base.base.dev; 3542 struct drm_i915_private *dev_priv = dev->dev_private; 3543 struct drm_display_mode *fixed_mode = NULL; 3544 struct edp_power_seq power_seq = { 0 }; 3545 bool has_dpcd; 3546 struct drm_display_mode *scan; 3547 struct edid *edid; 3548 3549 if (!is_edp(intel_dp)) 3550 return true; 3551 3552 intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq); 3553 3554 /* Cache DPCD and EDID for edp. */ 3555 ironlake_edp_panel_vdd_on(intel_dp); 3556 has_dpcd = intel_dp_get_dpcd(intel_dp); 3557 ironlake_edp_panel_vdd_off(intel_dp, false); 3558 3559 if (has_dpcd) { 3560 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) 3561 dev_priv->no_aux_handshake = 3562 intel_dp->dpcd[DP_MAX_DOWNSPREAD] & 3563 DP_NO_AUX_HANDSHAKE_LINK_TRAINING; 3564 } else { 3565 /* if this fails, presume the device is a ghost */ 3566 DRM_INFO("failed to retrieve link info, disabling eDP\n"); 3567 return false; 3568 } 3569 3570 /* We now know it's not a ghost, init power sequence regs. */ 3571 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp, 3572 &power_seq); 3573 3574 edid = drm_get_edid(connector, &intel_dp->adapter); 3575 if (edid) { 3576 if (drm_add_edid_modes(connector, edid)) { 3577 drm_mode_connector_update_edid_property(connector, 3578 edid); 3579 drm_edid_to_eld(connector, edid); 3580 } else { 3581 kfree(edid); 3582 edid = ERR_PTR(-EINVAL); 3583 } 3584 } else { 3585 edid = ERR_PTR(-ENOENT); 3586 } 3587 intel_connector->edid = edid; 3588 3589 /* prefer fixed mode from EDID if available */ 3590 list_for_each_entry(scan, &connector->probed_modes, head) { 3591 if ((scan->type & DRM_MODE_TYPE_PREFERRED)) { 3592 fixed_mode = drm_mode_duplicate(dev, scan); 3593 break; 3594 } 3595 } 3596 3597 /* fallback to VBT if available for eDP */ 3598 if (!fixed_mode && dev_priv->vbt.lfp_lvds_vbt_mode) { 3599 fixed_mode = drm_mode_duplicate(dev, 3600 dev_priv->vbt.lfp_lvds_vbt_mode); 3601 if (fixed_mode) 3602 fixed_mode->type |= DRM_MODE_TYPE_PREFERRED; 3603 } 3604 3605 intel_panel_init(&intel_connector->panel, fixed_mode); 3606 intel_panel_setup_backlight(connector); 3607 3608 return true; 3609} 3610 3611bool 3612intel_dp_init_connector(struct intel_digital_port *intel_dig_port, 3613 struct intel_connector *intel_connector) 3614{ 3615 struct drm_connector *connector = &intel_connector->base; 3616 struct intel_dp *intel_dp = &intel_dig_port->dp; 3617 struct intel_encoder *intel_encoder = &intel_dig_port->base; 3618 struct drm_device *dev = intel_encoder->base.dev; 3619 struct drm_i915_private *dev_priv = dev->dev_private; 3620 enum port port = intel_dig_port->port; 3621 const char *name = NULL; 3622 int type, error; 3623 3624 /* Preserve the current hw state. */ 3625 intel_dp->DP = I915_READ(intel_dp->output_reg); 3626 intel_dp->attached_connector = intel_connector; 3627 3628 if (intel_dp_is_edp(dev, port)) 3629 type = DRM_MODE_CONNECTOR_eDP; 3630 else 3631 type = DRM_MODE_CONNECTOR_DisplayPort; 3632 3633 /* 3634 * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but 3635 * for DP the encoder type can be set by the caller to 3636 * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it. 3637 */ 3638 if (type == DRM_MODE_CONNECTOR_eDP) 3639 intel_encoder->type = INTEL_OUTPUT_EDP; 3640 3641 DRM_DEBUG_KMS("Adding %s connector on port %c\n", 3642 type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP", 3643 port_name(port)); 3644 3645 drm_connector_init(dev, connector, &intel_dp_connector_funcs, type); 3646 drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs); 3647 3648 connector->interlace_allowed = true; 3649 connector->doublescan_allowed = 0; 3650 3651 INIT_DELAYED_WORK(&intel_dp->panel_vdd_work, 3652 ironlake_panel_vdd_work); 3653 3654 intel_connector_attach_encoder(intel_connector, intel_encoder); 3655 drm_sysfs_connector_add(connector); 3656 3657 if (HAS_DDI(dev)) 3658 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state; 3659 else 3660 intel_connector->get_hw_state = intel_connector_get_hw_state; 3661 3662 intel_dp->aux_ch_ctl_reg = intel_dp->output_reg + 0x10; 3663 if (HAS_DDI(dev)) { 3664 switch (intel_dig_port->port) { 3665 case PORT_A: 3666 intel_dp->aux_ch_ctl_reg = DPA_AUX_CH_CTL; 3667 break; 3668 case PORT_B: 3669 intel_dp->aux_ch_ctl_reg = PCH_DPB_AUX_CH_CTL; 3670 break; 3671 case PORT_C: 3672 intel_dp->aux_ch_ctl_reg = PCH_DPC_AUX_CH_CTL; 3673 break; 3674 case PORT_D: 3675 intel_dp->aux_ch_ctl_reg = PCH_DPD_AUX_CH_CTL; 3676 break; 3677 default: 3678 BUG(); 3679 } 3680 } 3681 3682 /* Set up the DDC bus. */ 3683 switch (port) { 3684 case PORT_A: 3685 intel_encoder->hpd_pin = HPD_PORT_A; 3686 name = "DPDDC-A"; 3687 break; 3688 case PORT_B: 3689 intel_encoder->hpd_pin = HPD_PORT_B; 3690 name = "DPDDC-B"; 3691 break; 3692 case PORT_C: 3693 intel_encoder->hpd_pin = HPD_PORT_C; 3694 name = "DPDDC-C"; 3695 break; 3696 case PORT_D: 3697 intel_encoder->hpd_pin = HPD_PORT_D; 3698 name = "DPDDC-D"; 3699 break; 3700 default: 3701 BUG(); 3702 } 3703 3704 error = intel_dp_i2c_init(intel_dp, intel_connector, name); 3705 WARN(error, "intel_dp_i2c_init failed with error %d for port %c\n", 3706 error, port_name(port)); 3707 3708 intel_dp->psr_setup_done = false; 3709 3710 if (!intel_edp_init_connector(intel_dp, intel_connector)) { 3711 i2c_del_adapter(&intel_dp->adapter); 3712 if (is_edp(intel_dp)) { 3713 cancel_delayed_work_sync(&intel_dp->panel_vdd_work); 3714 mutex_lock(&dev->mode_config.mutex); 3715 ironlake_panel_vdd_off_sync(intel_dp); 3716 mutex_unlock(&dev->mode_config.mutex); 3717 } 3718 drm_sysfs_connector_remove(connector); 3719 drm_connector_cleanup(connector); 3720 return false; 3721 } 3722 3723 intel_dp_add_properties(intel_dp, connector); 3724 3725 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written 3726 * 0xd. Failure to do so will result in spurious interrupts being 3727 * generated on the port when a cable is not attached. 3728 */ 3729 if (IS_G4X(dev) && !IS_GM45(dev)) { 3730 u32 temp = I915_READ(PEG_BAND_GAP_DATA); 3731 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd); 3732 } 3733 3734 return true; 3735} 3736 3737void 3738intel_dp_init(struct drm_device *dev, int output_reg, enum port port) 3739{ 3740 struct intel_digital_port *intel_dig_port; 3741 struct intel_encoder *intel_encoder; 3742 struct drm_encoder *encoder; 3743 struct intel_connector *intel_connector; 3744 3745 intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL); 3746 if (!intel_dig_port) 3747 return; 3748 3749 intel_connector = kzalloc(sizeof(*intel_connector), GFP_KERNEL); 3750 if (!intel_connector) { 3751 kfree(intel_dig_port); 3752 return; 3753 } 3754 3755 intel_encoder = &intel_dig_port->base; 3756 encoder = &intel_encoder->base; 3757 3758 drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs, 3759 DRM_MODE_ENCODER_TMDS); 3760 3761 intel_encoder->compute_config = intel_dp_compute_config; 3762 intel_encoder->mode_set = intel_dp_mode_set; 3763 intel_encoder->disable = intel_disable_dp; 3764 intel_encoder->post_disable = intel_post_disable_dp; 3765 intel_encoder->get_hw_state = intel_dp_get_hw_state; 3766 intel_encoder->get_config = intel_dp_get_config; 3767 if (IS_VALLEYVIEW(dev)) { 3768 intel_encoder->pre_pll_enable = vlv_dp_pre_pll_enable; 3769 intel_encoder->pre_enable = vlv_pre_enable_dp; 3770 intel_encoder->enable = vlv_enable_dp; 3771 } else { 3772 intel_encoder->pre_enable = g4x_pre_enable_dp; 3773 intel_encoder->enable = g4x_enable_dp; 3774 } 3775 3776 intel_dig_port->port = port; 3777 intel_dig_port->dp.output_reg = output_reg; 3778 3779 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT; 3780 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2); 3781 intel_encoder->cloneable = false; 3782 intel_encoder->hot_plug = intel_dp_hot_plug; 3783 3784 if (!intel_dp_init_connector(intel_dig_port, intel_connector)) { 3785 drm_encoder_cleanup(encoder); 3786 kfree(intel_dig_port); 3787 kfree(intel_connector); 3788 } 3789} 3790