intel_dp.c revision 6e9f798d91c526982cca0026cd451e8fdbf18aaf
1/* 2 * Copyright © 2008 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 * Authors: 24 * Keith Packard <keithp@keithp.com> 25 * 26 */ 27 28#include <linux/i2c.h> 29#include <linux/slab.h> 30#include <linux/export.h> 31#include <drm/drmP.h> 32#include <drm/drm_crtc.h> 33#include <drm/drm_crtc_helper.h> 34#include <drm/drm_edid.h> 35#include "intel_drv.h" 36#include <drm/i915_drm.h> 37#include "i915_drv.h" 38 39#define DP_LINK_CHECK_TIMEOUT (10 * 1000) 40 41struct dp_link_dpll { 42 int link_bw; 43 struct dpll dpll; 44}; 45 46static const struct dp_link_dpll gen4_dpll[] = { 47 { DP_LINK_BW_1_62, 48 { .p1 = 2, .p2 = 10, .n = 2, .m1 = 23, .m2 = 8 } }, 49 { DP_LINK_BW_2_7, 50 { .p1 = 1, .p2 = 10, .n = 1, .m1 = 14, .m2 = 2 } } 51}; 52 53static const struct dp_link_dpll pch_dpll[] = { 54 { DP_LINK_BW_1_62, 55 { .p1 = 2, .p2 = 10, .n = 1, .m1 = 12, .m2 = 9 } }, 56 { DP_LINK_BW_2_7, 57 { .p1 = 1, .p2 = 10, .n = 2, .m1 = 14, .m2 = 8 } } 58}; 59 60static const struct dp_link_dpll vlv_dpll[] = { 61 { DP_LINK_BW_1_62, 62 { .p1 = 3, .p2 = 2, .n = 5, .m1 = 3, .m2 = 81 } }, 63 { DP_LINK_BW_2_7, 64 { .p1 = 2, .p2 = 2, .n = 1, .m1 = 2, .m2 = 27 } } 65}; 66 67/* 68 * CHV supports eDP 1.4 that have more link rates. 69 * Below only provides the fixed rate but exclude variable rate. 70 */ 71static const struct dp_link_dpll chv_dpll[] = { 72 /* 73 * CHV requires to program fractional division for m2. 74 * m2 is stored in fixed point format using formula below 75 * (m2_int << 22) | m2_fraction 76 */ 77 { DP_LINK_BW_1_62, /* m2_int = 32, m2_fraction = 1677722 */ 78 { .p1 = 4, .p2 = 2, .n = 1, .m1 = 2, .m2 = 0x819999a } }, 79 { DP_LINK_BW_2_7, /* m2_int = 27, m2_fraction = 0 */ 80 { .p1 = 4, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } }, 81 { DP_LINK_BW_5_4, /* m2_int = 27, m2_fraction = 0 */ 82 { .p1 = 2, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } } 83}; 84 85/** 86 * is_edp - is the given port attached to an eDP panel (either CPU or PCH) 87 * @intel_dp: DP struct 88 * 89 * If a CPU or PCH DP output is attached to an eDP panel, this function 90 * will return true, and false otherwise. 91 */ 92static bool is_edp(struct intel_dp *intel_dp) 93{ 94 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 95 96 return intel_dig_port->base.type == INTEL_OUTPUT_EDP; 97} 98 99static struct drm_device *intel_dp_to_dev(struct intel_dp *intel_dp) 100{ 101 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 102 103 return intel_dig_port->base.base.dev; 104} 105 106static struct intel_dp *intel_attached_dp(struct drm_connector *connector) 107{ 108 return enc_to_intel_dp(&intel_attached_encoder(connector)->base); 109} 110 111static void intel_dp_link_down(struct intel_dp *intel_dp); 112static bool _edp_panel_vdd_on(struct intel_dp *intel_dp); 113static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync); 114 115static int 116intel_dp_max_link_bw(struct intel_dp *intel_dp) 117{ 118 int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE]; 119 struct drm_device *dev = intel_dp->attached_connector->base.dev; 120 121 switch (max_link_bw) { 122 case DP_LINK_BW_1_62: 123 case DP_LINK_BW_2_7: 124 break; 125 case DP_LINK_BW_5_4: /* 1.2 capable displays may advertise higher bw */ 126 if ((IS_HASWELL(dev) || INTEL_INFO(dev)->gen >= 8) && 127 intel_dp->dpcd[DP_DPCD_REV] >= 0x12) 128 max_link_bw = DP_LINK_BW_5_4; 129 else 130 max_link_bw = DP_LINK_BW_2_7; 131 break; 132 default: 133 WARN(1, "invalid max DP link bw val %x, using 1.62Gbps\n", 134 max_link_bw); 135 max_link_bw = DP_LINK_BW_1_62; 136 break; 137 } 138 return max_link_bw; 139} 140 141/* 142 * The units on the numbers in the next two are... bizarre. Examples will 143 * make it clearer; this one parallels an example in the eDP spec. 144 * 145 * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as: 146 * 147 * 270000 * 1 * 8 / 10 == 216000 148 * 149 * The actual data capacity of that configuration is 2.16Gbit/s, so the 150 * units are decakilobits. ->clock in a drm_display_mode is in kilohertz - 151 * or equivalently, kilopixels per second - so for 1680x1050R it'd be 152 * 119000. At 18bpp that's 2142000 kilobits per second. 153 * 154 * Thus the strange-looking division by 10 in intel_dp_link_required, to 155 * get the result in decakilobits instead of kilobits. 156 */ 157 158static int 159intel_dp_link_required(int pixel_clock, int bpp) 160{ 161 return (pixel_clock * bpp + 9) / 10; 162} 163 164static int 165intel_dp_max_data_rate(int max_link_clock, int max_lanes) 166{ 167 return (max_link_clock * max_lanes * 8) / 10; 168} 169 170static enum drm_mode_status 171intel_dp_mode_valid(struct drm_connector *connector, 172 struct drm_display_mode *mode) 173{ 174 struct intel_dp *intel_dp = intel_attached_dp(connector); 175 struct intel_connector *intel_connector = to_intel_connector(connector); 176 struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode; 177 int target_clock = mode->clock; 178 int max_rate, mode_rate, max_lanes, max_link_clock; 179 180 if (is_edp(intel_dp) && fixed_mode) { 181 if (mode->hdisplay > fixed_mode->hdisplay) 182 return MODE_PANEL; 183 184 if (mode->vdisplay > fixed_mode->vdisplay) 185 return MODE_PANEL; 186 187 target_clock = fixed_mode->clock; 188 } 189 190 max_link_clock = drm_dp_bw_code_to_link_rate(intel_dp_max_link_bw(intel_dp)); 191 max_lanes = drm_dp_max_lane_count(intel_dp->dpcd); 192 193 max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes); 194 mode_rate = intel_dp_link_required(target_clock, 18); 195 196 if (mode_rate > max_rate) 197 return MODE_CLOCK_HIGH; 198 199 if (mode->clock < 10000) 200 return MODE_CLOCK_LOW; 201 202 if (mode->flags & DRM_MODE_FLAG_DBLCLK) 203 return MODE_H_ILLEGAL; 204 205 return MODE_OK; 206} 207 208static uint32_t 209pack_aux(uint8_t *src, int src_bytes) 210{ 211 int i; 212 uint32_t v = 0; 213 214 if (src_bytes > 4) 215 src_bytes = 4; 216 for (i = 0; i < src_bytes; i++) 217 v |= ((uint32_t) src[i]) << ((3-i) * 8); 218 return v; 219} 220 221static void 222unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes) 223{ 224 int i; 225 if (dst_bytes > 4) 226 dst_bytes = 4; 227 for (i = 0; i < dst_bytes; i++) 228 dst[i] = src >> ((3-i) * 8); 229} 230 231/* hrawclock is 1/4 the FSB frequency */ 232static int 233intel_hrawclk(struct drm_device *dev) 234{ 235 struct drm_i915_private *dev_priv = dev->dev_private; 236 uint32_t clkcfg; 237 238 /* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */ 239 if (IS_VALLEYVIEW(dev)) 240 return 200; 241 242 clkcfg = I915_READ(CLKCFG); 243 switch (clkcfg & CLKCFG_FSB_MASK) { 244 case CLKCFG_FSB_400: 245 return 100; 246 case CLKCFG_FSB_533: 247 return 133; 248 case CLKCFG_FSB_667: 249 return 166; 250 case CLKCFG_FSB_800: 251 return 200; 252 case CLKCFG_FSB_1067: 253 return 266; 254 case CLKCFG_FSB_1333: 255 return 333; 256 /* these two are just a guess; one of them might be right */ 257 case CLKCFG_FSB_1600: 258 case CLKCFG_FSB_1600_ALT: 259 return 400; 260 default: 261 return 133; 262 } 263} 264 265static void 266intel_dp_init_panel_power_sequencer(struct drm_device *dev, 267 struct intel_dp *intel_dp, 268 struct edp_power_seq *out); 269static void 270intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev, 271 struct intel_dp *intel_dp, 272 struct edp_power_seq *out); 273 274static enum pipe 275vlv_power_sequencer_pipe(struct intel_dp *intel_dp) 276{ 277 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 278 struct drm_crtc *crtc = intel_dig_port->base.base.crtc; 279 struct drm_device *dev = intel_dig_port->base.base.dev; 280 struct drm_i915_private *dev_priv = dev->dev_private; 281 enum port port = intel_dig_port->port; 282 enum pipe pipe; 283 284 /* modeset should have pipe */ 285 if (crtc) 286 return to_intel_crtc(crtc)->pipe; 287 288 /* init time, try to find a pipe with this port selected */ 289 for (pipe = PIPE_A; pipe <= PIPE_B; pipe++) { 290 u32 port_sel = I915_READ(VLV_PIPE_PP_ON_DELAYS(pipe)) & 291 PANEL_PORT_SELECT_MASK; 292 if (port_sel == PANEL_PORT_SELECT_DPB_VLV && port == PORT_B) 293 return pipe; 294 if (port_sel == PANEL_PORT_SELECT_DPC_VLV && port == PORT_C) 295 return pipe; 296 } 297 298 /* shrug */ 299 return PIPE_A; 300} 301 302static u32 _pp_ctrl_reg(struct intel_dp *intel_dp) 303{ 304 struct drm_device *dev = intel_dp_to_dev(intel_dp); 305 306 if (HAS_PCH_SPLIT(dev)) 307 return PCH_PP_CONTROL; 308 else 309 return VLV_PIPE_PP_CONTROL(vlv_power_sequencer_pipe(intel_dp)); 310} 311 312static u32 _pp_stat_reg(struct intel_dp *intel_dp) 313{ 314 struct drm_device *dev = intel_dp_to_dev(intel_dp); 315 316 if (HAS_PCH_SPLIT(dev)) 317 return PCH_PP_STATUS; 318 else 319 return VLV_PIPE_PP_STATUS(vlv_power_sequencer_pipe(intel_dp)); 320} 321 322static bool edp_have_panel_power(struct intel_dp *intel_dp) 323{ 324 struct drm_device *dev = intel_dp_to_dev(intel_dp); 325 struct drm_i915_private *dev_priv = dev->dev_private; 326 327 return (I915_READ(_pp_stat_reg(intel_dp)) & PP_ON) != 0; 328} 329 330static bool edp_have_panel_vdd(struct intel_dp *intel_dp) 331{ 332 struct drm_device *dev = intel_dp_to_dev(intel_dp); 333 struct drm_i915_private *dev_priv = dev->dev_private; 334 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 335 struct intel_encoder *intel_encoder = &intel_dig_port->base; 336 enum intel_display_power_domain power_domain; 337 338 power_domain = intel_display_port_power_domain(intel_encoder); 339 return intel_display_power_enabled(dev_priv, power_domain) && 340 (I915_READ(_pp_ctrl_reg(intel_dp)) & EDP_FORCE_VDD) != 0; 341} 342 343static void 344intel_dp_check_edp(struct intel_dp *intel_dp) 345{ 346 struct drm_device *dev = intel_dp_to_dev(intel_dp); 347 struct drm_i915_private *dev_priv = dev->dev_private; 348 349 if (!is_edp(intel_dp)) 350 return; 351 352 if (!edp_have_panel_power(intel_dp) && !edp_have_panel_vdd(intel_dp)) { 353 WARN(1, "eDP powered off while attempting aux channel communication.\n"); 354 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n", 355 I915_READ(_pp_stat_reg(intel_dp)), 356 I915_READ(_pp_ctrl_reg(intel_dp))); 357 } 358} 359 360static uint32_t 361intel_dp_aux_wait_done(struct intel_dp *intel_dp, bool has_aux_irq) 362{ 363 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 364 struct drm_device *dev = intel_dig_port->base.base.dev; 365 struct drm_i915_private *dev_priv = dev->dev_private; 366 uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg; 367 uint32_t status; 368 bool done; 369 370#define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0) 371 if (has_aux_irq) 372 done = wait_event_timeout(dev_priv->gmbus_wait_queue, C, 373 msecs_to_jiffies_timeout(10)); 374 else 375 done = wait_for_atomic(C, 10) == 0; 376 if (!done) 377 DRM_ERROR("dp aux hw did not signal timeout (has irq: %i)!\n", 378 has_aux_irq); 379#undef C 380 381 return status; 382} 383 384static uint32_t i9xx_get_aux_clock_divider(struct intel_dp *intel_dp, int index) 385{ 386 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 387 struct drm_device *dev = intel_dig_port->base.base.dev; 388 389 /* 390 * The clock divider is based off the hrawclk, and would like to run at 391 * 2MHz. So, take the hrawclk value and divide by 2 and use that 392 */ 393 return index ? 0 : intel_hrawclk(dev) / 2; 394} 395 396static uint32_t ilk_get_aux_clock_divider(struct intel_dp *intel_dp, int index) 397{ 398 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 399 struct drm_device *dev = intel_dig_port->base.base.dev; 400 401 if (index) 402 return 0; 403 404 if (intel_dig_port->port == PORT_A) { 405 if (IS_GEN6(dev) || IS_GEN7(dev)) 406 return 200; /* SNB & IVB eDP input clock at 400Mhz */ 407 else 408 return 225; /* eDP input clock at 450Mhz */ 409 } else { 410 return DIV_ROUND_UP(intel_pch_rawclk(dev), 2); 411 } 412} 413 414static uint32_t hsw_get_aux_clock_divider(struct intel_dp *intel_dp, int index) 415{ 416 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 417 struct drm_device *dev = intel_dig_port->base.base.dev; 418 struct drm_i915_private *dev_priv = dev->dev_private; 419 420 if (intel_dig_port->port == PORT_A) { 421 if (index) 422 return 0; 423 return DIV_ROUND_CLOSEST(intel_ddi_get_cdclk_freq(dev_priv), 2000); 424 } else if (dev_priv->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE) { 425 /* Workaround for non-ULT HSW */ 426 switch (index) { 427 case 0: return 63; 428 case 1: return 72; 429 default: return 0; 430 } 431 } else { 432 return index ? 0 : DIV_ROUND_UP(intel_pch_rawclk(dev), 2); 433 } 434} 435 436static uint32_t vlv_get_aux_clock_divider(struct intel_dp *intel_dp, int index) 437{ 438 return index ? 0 : 100; 439} 440 441static uint32_t i9xx_get_aux_send_ctl(struct intel_dp *intel_dp, 442 bool has_aux_irq, 443 int send_bytes, 444 uint32_t aux_clock_divider) 445{ 446 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 447 struct drm_device *dev = intel_dig_port->base.base.dev; 448 uint32_t precharge, timeout; 449 450 if (IS_GEN6(dev)) 451 precharge = 3; 452 else 453 precharge = 5; 454 455 if (IS_BROADWELL(dev) && intel_dp->aux_ch_ctl_reg == DPA_AUX_CH_CTL) 456 timeout = DP_AUX_CH_CTL_TIME_OUT_600us; 457 else 458 timeout = DP_AUX_CH_CTL_TIME_OUT_400us; 459 460 return DP_AUX_CH_CTL_SEND_BUSY | 461 DP_AUX_CH_CTL_DONE | 462 (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) | 463 DP_AUX_CH_CTL_TIME_OUT_ERROR | 464 timeout | 465 DP_AUX_CH_CTL_RECEIVE_ERROR | 466 (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) | 467 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) | 468 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT); 469} 470 471static int 472intel_dp_aux_ch(struct intel_dp *intel_dp, 473 uint8_t *send, int send_bytes, 474 uint8_t *recv, int recv_size) 475{ 476 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 477 struct drm_device *dev = intel_dig_port->base.base.dev; 478 struct drm_i915_private *dev_priv = dev->dev_private; 479 uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg; 480 uint32_t ch_data = ch_ctl + 4; 481 uint32_t aux_clock_divider; 482 int i, ret, recv_bytes; 483 uint32_t status; 484 int try, clock = 0; 485 bool has_aux_irq = HAS_AUX_IRQ(dev); 486 bool vdd; 487 488 vdd = _edp_panel_vdd_on(intel_dp); 489 490 /* dp aux is extremely sensitive to irq latency, hence request the 491 * lowest possible wakeup latency and so prevent the cpu from going into 492 * deep sleep states. 493 */ 494 pm_qos_update_request(&dev_priv->pm_qos, 0); 495 496 intel_dp_check_edp(intel_dp); 497 498 intel_aux_display_runtime_get(dev_priv); 499 500 /* Try to wait for any previous AUX channel activity */ 501 for (try = 0; try < 3; try++) { 502 status = I915_READ_NOTRACE(ch_ctl); 503 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0) 504 break; 505 msleep(1); 506 } 507 508 if (try == 3) { 509 WARN(1, "dp_aux_ch not started status 0x%08x\n", 510 I915_READ(ch_ctl)); 511 ret = -EBUSY; 512 goto out; 513 } 514 515 /* Only 5 data registers! */ 516 if (WARN_ON(send_bytes > 20 || recv_size > 20)) { 517 ret = -E2BIG; 518 goto out; 519 } 520 521 while ((aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, clock++))) { 522 u32 send_ctl = intel_dp->get_aux_send_ctl(intel_dp, 523 has_aux_irq, 524 send_bytes, 525 aux_clock_divider); 526 527 /* Must try at least 3 times according to DP spec */ 528 for (try = 0; try < 5; try++) { 529 /* Load the send data into the aux channel data registers */ 530 for (i = 0; i < send_bytes; i += 4) 531 I915_WRITE(ch_data + i, 532 pack_aux(send + i, send_bytes - i)); 533 534 /* Send the command and wait for it to complete */ 535 I915_WRITE(ch_ctl, send_ctl); 536 537 status = intel_dp_aux_wait_done(intel_dp, has_aux_irq); 538 539 /* Clear done status and any errors */ 540 I915_WRITE(ch_ctl, 541 status | 542 DP_AUX_CH_CTL_DONE | 543 DP_AUX_CH_CTL_TIME_OUT_ERROR | 544 DP_AUX_CH_CTL_RECEIVE_ERROR); 545 546 if (status & (DP_AUX_CH_CTL_TIME_OUT_ERROR | 547 DP_AUX_CH_CTL_RECEIVE_ERROR)) 548 continue; 549 if (status & DP_AUX_CH_CTL_DONE) 550 break; 551 } 552 if (status & DP_AUX_CH_CTL_DONE) 553 break; 554 } 555 556 if ((status & DP_AUX_CH_CTL_DONE) == 0) { 557 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status); 558 ret = -EBUSY; 559 goto out; 560 } 561 562 /* Check for timeout or receive error. 563 * Timeouts occur when the sink is not connected 564 */ 565 if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) { 566 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status); 567 ret = -EIO; 568 goto out; 569 } 570 571 /* Timeouts occur when the device isn't connected, so they're 572 * "normal" -- don't fill the kernel log with these */ 573 if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) { 574 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status); 575 ret = -ETIMEDOUT; 576 goto out; 577 } 578 579 /* Unload any bytes sent back from the other side */ 580 recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >> 581 DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT); 582 if (recv_bytes > recv_size) 583 recv_bytes = recv_size; 584 585 for (i = 0; i < recv_bytes; i += 4) 586 unpack_aux(I915_READ(ch_data + i), 587 recv + i, recv_bytes - i); 588 589 ret = recv_bytes; 590out: 591 pm_qos_update_request(&dev_priv->pm_qos, PM_QOS_DEFAULT_VALUE); 592 intel_aux_display_runtime_put(dev_priv); 593 594 if (vdd) 595 edp_panel_vdd_off(intel_dp, false); 596 597 return ret; 598} 599 600#define BARE_ADDRESS_SIZE 3 601#define HEADER_SIZE (BARE_ADDRESS_SIZE + 1) 602static ssize_t 603intel_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg) 604{ 605 struct intel_dp *intel_dp = container_of(aux, struct intel_dp, aux); 606 uint8_t txbuf[20], rxbuf[20]; 607 size_t txsize, rxsize; 608 int ret; 609 610 txbuf[0] = msg->request << 4; 611 txbuf[1] = msg->address >> 8; 612 txbuf[2] = msg->address & 0xff; 613 txbuf[3] = msg->size - 1; 614 615 switch (msg->request & ~DP_AUX_I2C_MOT) { 616 case DP_AUX_NATIVE_WRITE: 617 case DP_AUX_I2C_WRITE: 618 txsize = msg->size ? HEADER_SIZE + msg->size : BARE_ADDRESS_SIZE; 619 rxsize = 1; 620 621 if (WARN_ON(txsize > 20)) 622 return -E2BIG; 623 624 memcpy(txbuf + HEADER_SIZE, msg->buffer, msg->size); 625 626 ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize); 627 if (ret > 0) { 628 msg->reply = rxbuf[0] >> 4; 629 630 /* Return payload size. */ 631 ret = msg->size; 632 } 633 break; 634 635 case DP_AUX_NATIVE_READ: 636 case DP_AUX_I2C_READ: 637 txsize = msg->size ? HEADER_SIZE : BARE_ADDRESS_SIZE; 638 rxsize = msg->size + 1; 639 640 if (WARN_ON(rxsize > 20)) 641 return -E2BIG; 642 643 ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize); 644 if (ret > 0) { 645 msg->reply = rxbuf[0] >> 4; 646 /* 647 * Assume happy day, and copy the data. The caller is 648 * expected to check msg->reply before touching it. 649 * 650 * Return payload size. 651 */ 652 ret--; 653 memcpy(msg->buffer, rxbuf + 1, ret); 654 } 655 break; 656 657 default: 658 ret = -EINVAL; 659 break; 660 } 661 662 return ret; 663} 664 665static void 666intel_dp_aux_init(struct intel_dp *intel_dp, struct intel_connector *connector) 667{ 668 struct drm_device *dev = intel_dp_to_dev(intel_dp); 669 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 670 enum port port = intel_dig_port->port; 671 const char *name = NULL; 672 int ret; 673 674 switch (port) { 675 case PORT_A: 676 intel_dp->aux_ch_ctl_reg = DPA_AUX_CH_CTL; 677 name = "DPDDC-A"; 678 break; 679 case PORT_B: 680 intel_dp->aux_ch_ctl_reg = PCH_DPB_AUX_CH_CTL; 681 name = "DPDDC-B"; 682 break; 683 case PORT_C: 684 intel_dp->aux_ch_ctl_reg = PCH_DPC_AUX_CH_CTL; 685 name = "DPDDC-C"; 686 break; 687 case PORT_D: 688 intel_dp->aux_ch_ctl_reg = PCH_DPD_AUX_CH_CTL; 689 name = "DPDDC-D"; 690 break; 691 default: 692 BUG(); 693 } 694 695 if (!HAS_DDI(dev)) 696 intel_dp->aux_ch_ctl_reg = intel_dp->output_reg + 0x10; 697 698 intel_dp->aux.name = name; 699 intel_dp->aux.dev = dev->dev; 700 intel_dp->aux.transfer = intel_dp_aux_transfer; 701 702 DRM_DEBUG_KMS("registering %s bus for %s\n", name, 703 connector->base.kdev->kobj.name); 704 705 ret = drm_dp_aux_register_i2c_bus(&intel_dp->aux); 706 if (ret < 0) { 707 DRM_ERROR("drm_dp_aux_register_i2c_bus() for %s failed (%d)\n", 708 name, ret); 709 return; 710 } 711 712 ret = sysfs_create_link(&connector->base.kdev->kobj, 713 &intel_dp->aux.ddc.dev.kobj, 714 intel_dp->aux.ddc.dev.kobj.name); 715 if (ret < 0) { 716 DRM_ERROR("sysfs_create_link() for %s failed (%d)\n", name, ret); 717 drm_dp_aux_unregister_i2c_bus(&intel_dp->aux); 718 } 719} 720 721static void 722intel_dp_connector_unregister(struct intel_connector *intel_connector) 723{ 724 struct intel_dp *intel_dp = intel_attached_dp(&intel_connector->base); 725 726 sysfs_remove_link(&intel_connector->base.kdev->kobj, 727 intel_dp->aux.ddc.dev.kobj.name); 728 intel_connector_unregister(intel_connector); 729} 730 731static void 732intel_dp_set_clock(struct intel_encoder *encoder, 733 struct intel_crtc_config *pipe_config, int link_bw) 734{ 735 struct drm_device *dev = encoder->base.dev; 736 const struct dp_link_dpll *divisor = NULL; 737 int i, count = 0; 738 739 if (IS_G4X(dev)) { 740 divisor = gen4_dpll; 741 count = ARRAY_SIZE(gen4_dpll); 742 } else if (IS_HASWELL(dev)) { 743 /* Haswell has special-purpose DP DDI clocks. */ 744 } else if (HAS_PCH_SPLIT(dev)) { 745 divisor = pch_dpll; 746 count = ARRAY_SIZE(pch_dpll); 747 } else if (IS_CHERRYVIEW(dev)) { 748 divisor = chv_dpll; 749 count = ARRAY_SIZE(chv_dpll); 750 } else if (IS_VALLEYVIEW(dev)) { 751 divisor = vlv_dpll; 752 count = ARRAY_SIZE(vlv_dpll); 753 } 754 755 if (divisor && count) { 756 for (i = 0; i < count; i++) { 757 if (link_bw == divisor[i].link_bw) { 758 pipe_config->dpll = divisor[i].dpll; 759 pipe_config->clock_set = true; 760 break; 761 } 762 } 763 } 764} 765 766static void 767intel_dp_set_m2_n2(struct intel_crtc *crtc, struct intel_link_m_n *m_n) 768{ 769 struct drm_device *dev = crtc->base.dev; 770 struct drm_i915_private *dev_priv = dev->dev_private; 771 enum transcoder transcoder = crtc->config.cpu_transcoder; 772 773 I915_WRITE(PIPE_DATA_M2(transcoder), 774 TU_SIZE(m_n->tu) | m_n->gmch_m); 775 I915_WRITE(PIPE_DATA_N2(transcoder), m_n->gmch_n); 776 I915_WRITE(PIPE_LINK_M2(transcoder), m_n->link_m); 777 I915_WRITE(PIPE_LINK_N2(transcoder), m_n->link_n); 778} 779 780bool 781intel_dp_compute_config(struct intel_encoder *encoder, 782 struct intel_crtc_config *pipe_config) 783{ 784 struct drm_device *dev = encoder->base.dev; 785 struct drm_i915_private *dev_priv = dev->dev_private; 786 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode; 787 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); 788 enum port port = dp_to_dig_port(intel_dp)->port; 789 struct intel_crtc *intel_crtc = encoder->new_crtc; 790 struct intel_connector *intel_connector = intel_dp->attached_connector; 791 int lane_count, clock; 792 int max_lane_count = drm_dp_max_lane_count(intel_dp->dpcd); 793 /* Conveniently, the link BW constants become indices with a shift...*/ 794 int max_clock = intel_dp_max_link_bw(intel_dp) >> 3; 795 int bpp, mode_rate; 796 static int bws[] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7, DP_LINK_BW_5_4 }; 797 int link_avail, link_clock; 798 799 if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev) && port != PORT_A) 800 pipe_config->has_pch_encoder = true; 801 802 pipe_config->has_dp_encoder = true; 803 pipe_config->has_audio = intel_dp->has_audio; 804 805 if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) { 806 intel_fixed_panel_mode(intel_connector->panel.fixed_mode, 807 adjusted_mode); 808 if (!HAS_PCH_SPLIT(dev)) 809 intel_gmch_panel_fitting(intel_crtc, pipe_config, 810 intel_connector->panel.fitting_mode); 811 else 812 intel_pch_panel_fitting(intel_crtc, pipe_config, 813 intel_connector->panel.fitting_mode); 814 } 815 816 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK) 817 return false; 818 819 DRM_DEBUG_KMS("DP link computation with max lane count %i " 820 "max bw %02x pixel clock %iKHz\n", 821 max_lane_count, bws[max_clock], 822 adjusted_mode->crtc_clock); 823 824 /* Walk through all bpp values. Luckily they're all nicely spaced with 2 825 * bpc in between. */ 826 bpp = pipe_config->pipe_bpp; 827 if (is_edp(intel_dp) && dev_priv->vbt.edp_bpp && 828 dev_priv->vbt.edp_bpp < bpp) { 829 DRM_DEBUG_KMS("clamping bpp for eDP panel to BIOS-provided %i\n", 830 dev_priv->vbt.edp_bpp); 831 bpp = dev_priv->vbt.edp_bpp; 832 } 833 834 for (; bpp >= 6*3; bpp -= 2*3) { 835 mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock, 836 bpp); 837 838 for (lane_count = 1; lane_count <= max_lane_count; lane_count <<= 1) { 839 for (clock = 0; clock <= max_clock; clock++) { 840 link_clock = drm_dp_bw_code_to_link_rate(bws[clock]); 841 link_avail = intel_dp_max_data_rate(link_clock, 842 lane_count); 843 844 if (mode_rate <= link_avail) { 845 goto found; 846 } 847 } 848 } 849 } 850 851 return false; 852 853found: 854 if (intel_dp->color_range_auto) { 855 /* 856 * See: 857 * CEA-861-E - 5.1 Default Encoding Parameters 858 * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry 859 */ 860 if (bpp != 18 && drm_match_cea_mode(adjusted_mode) > 1) 861 intel_dp->color_range = DP_COLOR_RANGE_16_235; 862 else 863 intel_dp->color_range = 0; 864 } 865 866 if (intel_dp->color_range) 867 pipe_config->limited_color_range = true; 868 869 intel_dp->link_bw = bws[clock]; 870 intel_dp->lane_count = lane_count; 871 pipe_config->pipe_bpp = bpp; 872 pipe_config->port_clock = drm_dp_bw_code_to_link_rate(intel_dp->link_bw); 873 874 DRM_DEBUG_KMS("DP link bw %02x lane count %d clock %d bpp %d\n", 875 intel_dp->link_bw, intel_dp->lane_count, 876 pipe_config->port_clock, bpp); 877 DRM_DEBUG_KMS("DP link bw required %i available %i\n", 878 mode_rate, link_avail); 879 880 intel_link_compute_m_n(bpp, lane_count, 881 adjusted_mode->crtc_clock, 882 pipe_config->port_clock, 883 &pipe_config->dp_m_n); 884 885 if (intel_connector->panel.downclock_mode != NULL && 886 intel_dp->drrs_state.type == SEAMLESS_DRRS_SUPPORT) { 887 intel_link_compute_m_n(bpp, lane_count, 888 intel_connector->panel.downclock_mode->clock, 889 pipe_config->port_clock, 890 &pipe_config->dp_m2_n2); 891 } 892 893 intel_dp_set_clock(encoder, pipe_config, intel_dp->link_bw); 894 895 return true; 896} 897 898static void ironlake_set_pll_cpu_edp(struct intel_dp *intel_dp) 899{ 900 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 901 struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc); 902 struct drm_device *dev = crtc->base.dev; 903 struct drm_i915_private *dev_priv = dev->dev_private; 904 u32 dpa_ctl; 905 906 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", crtc->config.port_clock); 907 dpa_ctl = I915_READ(DP_A); 908 dpa_ctl &= ~DP_PLL_FREQ_MASK; 909 910 if (crtc->config.port_clock == 162000) { 911 /* For a long time we've carried around a ILK-DevA w/a for the 912 * 160MHz clock. If we're really unlucky, it's still required. 913 */ 914 DRM_DEBUG_KMS("160MHz cpu eDP clock, might need ilk devA w/a\n"); 915 dpa_ctl |= DP_PLL_FREQ_160MHZ; 916 intel_dp->DP |= DP_PLL_FREQ_160MHZ; 917 } else { 918 dpa_ctl |= DP_PLL_FREQ_270MHZ; 919 intel_dp->DP |= DP_PLL_FREQ_270MHZ; 920 } 921 922 I915_WRITE(DP_A, dpa_ctl); 923 924 POSTING_READ(DP_A); 925 udelay(500); 926} 927 928static void intel_dp_prepare(struct intel_encoder *encoder) 929{ 930 struct drm_device *dev = encoder->base.dev; 931 struct drm_i915_private *dev_priv = dev->dev_private; 932 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); 933 enum port port = dp_to_dig_port(intel_dp)->port; 934 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); 935 struct drm_display_mode *adjusted_mode = &crtc->config.adjusted_mode; 936 937 /* 938 * There are four kinds of DP registers: 939 * 940 * IBX PCH 941 * SNB CPU 942 * IVB CPU 943 * CPT PCH 944 * 945 * IBX PCH and CPU are the same for almost everything, 946 * except that the CPU DP PLL is configured in this 947 * register 948 * 949 * CPT PCH is quite different, having many bits moved 950 * to the TRANS_DP_CTL register instead. That 951 * configuration happens (oddly) in ironlake_pch_enable 952 */ 953 954 /* Preserve the BIOS-computed detected bit. This is 955 * supposed to be read-only. 956 */ 957 intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED; 958 959 /* Handle DP bits in common between all three register formats */ 960 intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0; 961 intel_dp->DP |= DP_PORT_WIDTH(intel_dp->lane_count); 962 963 if (crtc->config.has_audio) { 964 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n", 965 pipe_name(crtc->pipe)); 966 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE; 967 intel_write_eld(&encoder->base, adjusted_mode); 968 } 969 970 /* Split out the IBX/CPU vs CPT settings */ 971 972 if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) { 973 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) 974 intel_dp->DP |= DP_SYNC_HS_HIGH; 975 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) 976 intel_dp->DP |= DP_SYNC_VS_HIGH; 977 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT; 978 979 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd)) 980 intel_dp->DP |= DP_ENHANCED_FRAMING; 981 982 intel_dp->DP |= crtc->pipe << 29; 983 } else if (!HAS_PCH_CPT(dev) || port == PORT_A) { 984 if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev)) 985 intel_dp->DP |= intel_dp->color_range; 986 987 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) 988 intel_dp->DP |= DP_SYNC_HS_HIGH; 989 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) 990 intel_dp->DP |= DP_SYNC_VS_HIGH; 991 intel_dp->DP |= DP_LINK_TRAIN_OFF; 992 993 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd)) 994 intel_dp->DP |= DP_ENHANCED_FRAMING; 995 996 if (!IS_CHERRYVIEW(dev)) { 997 if (crtc->pipe == 1) 998 intel_dp->DP |= DP_PIPEB_SELECT; 999 } else { 1000 intel_dp->DP |= DP_PIPE_SELECT_CHV(crtc->pipe); 1001 } 1002 } else { 1003 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT; 1004 } 1005} 1006 1007#define IDLE_ON_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK) 1008#define IDLE_ON_VALUE (PP_ON | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE) 1009 1010#define IDLE_OFF_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | 0) 1011#define IDLE_OFF_VALUE (0 | PP_SEQUENCE_NONE | 0 | 0) 1012 1013#define IDLE_CYCLE_MASK (PP_ON | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK) 1014#define IDLE_CYCLE_VALUE (0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE) 1015 1016static void wait_panel_status(struct intel_dp *intel_dp, 1017 u32 mask, 1018 u32 value) 1019{ 1020 struct drm_device *dev = intel_dp_to_dev(intel_dp); 1021 struct drm_i915_private *dev_priv = dev->dev_private; 1022 u32 pp_stat_reg, pp_ctrl_reg; 1023 1024 pp_stat_reg = _pp_stat_reg(intel_dp); 1025 pp_ctrl_reg = _pp_ctrl_reg(intel_dp); 1026 1027 DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n", 1028 mask, value, 1029 I915_READ(pp_stat_reg), 1030 I915_READ(pp_ctrl_reg)); 1031 1032 if (_wait_for((I915_READ(pp_stat_reg) & mask) == value, 5000, 10)) { 1033 DRM_ERROR("Panel status timeout: status %08x control %08x\n", 1034 I915_READ(pp_stat_reg), 1035 I915_READ(pp_ctrl_reg)); 1036 } 1037 1038 DRM_DEBUG_KMS("Wait complete\n"); 1039} 1040 1041static void wait_panel_on(struct intel_dp *intel_dp) 1042{ 1043 DRM_DEBUG_KMS("Wait for panel power on\n"); 1044 wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE); 1045} 1046 1047static void wait_panel_off(struct intel_dp *intel_dp) 1048{ 1049 DRM_DEBUG_KMS("Wait for panel power off time\n"); 1050 wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE); 1051} 1052 1053static void wait_panel_power_cycle(struct intel_dp *intel_dp) 1054{ 1055 DRM_DEBUG_KMS("Wait for panel power cycle\n"); 1056 1057 /* When we disable the VDD override bit last we have to do the manual 1058 * wait. */ 1059 wait_remaining_ms_from_jiffies(intel_dp->last_power_cycle, 1060 intel_dp->panel_power_cycle_delay); 1061 1062 wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE); 1063} 1064 1065static void wait_backlight_on(struct intel_dp *intel_dp) 1066{ 1067 wait_remaining_ms_from_jiffies(intel_dp->last_power_on, 1068 intel_dp->backlight_on_delay); 1069} 1070 1071static void edp_wait_backlight_off(struct intel_dp *intel_dp) 1072{ 1073 wait_remaining_ms_from_jiffies(intel_dp->last_backlight_off, 1074 intel_dp->backlight_off_delay); 1075} 1076 1077/* Read the current pp_control value, unlocking the register if it 1078 * is locked 1079 */ 1080 1081static u32 ironlake_get_pp_control(struct intel_dp *intel_dp) 1082{ 1083 struct drm_device *dev = intel_dp_to_dev(intel_dp); 1084 struct drm_i915_private *dev_priv = dev->dev_private; 1085 u32 control; 1086 1087 control = I915_READ(_pp_ctrl_reg(intel_dp)); 1088 control &= ~PANEL_UNLOCK_MASK; 1089 control |= PANEL_UNLOCK_REGS; 1090 return control; 1091} 1092 1093static bool _edp_panel_vdd_on(struct intel_dp *intel_dp) 1094{ 1095 struct drm_device *dev = intel_dp_to_dev(intel_dp); 1096 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 1097 struct intel_encoder *intel_encoder = &intel_dig_port->base; 1098 struct drm_i915_private *dev_priv = dev->dev_private; 1099 enum intel_display_power_domain power_domain; 1100 u32 pp; 1101 u32 pp_stat_reg, pp_ctrl_reg; 1102 bool need_to_disable = !intel_dp->want_panel_vdd; 1103 1104 if (!is_edp(intel_dp)) 1105 return false; 1106 1107 intel_dp->want_panel_vdd = true; 1108 1109 if (edp_have_panel_vdd(intel_dp)) 1110 return need_to_disable; 1111 1112 power_domain = intel_display_port_power_domain(intel_encoder); 1113 intel_display_power_get(dev_priv, power_domain); 1114 1115 DRM_DEBUG_KMS("Turning eDP VDD on\n"); 1116 1117 if (!edp_have_panel_power(intel_dp)) 1118 wait_panel_power_cycle(intel_dp); 1119 1120 pp = ironlake_get_pp_control(intel_dp); 1121 pp |= EDP_FORCE_VDD; 1122 1123 pp_stat_reg = _pp_stat_reg(intel_dp); 1124 pp_ctrl_reg = _pp_ctrl_reg(intel_dp); 1125 1126 I915_WRITE(pp_ctrl_reg, pp); 1127 POSTING_READ(pp_ctrl_reg); 1128 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n", 1129 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg)); 1130 /* 1131 * If the panel wasn't on, delay before accessing aux channel 1132 */ 1133 if (!edp_have_panel_power(intel_dp)) { 1134 DRM_DEBUG_KMS("eDP was not running\n"); 1135 msleep(intel_dp->panel_power_up_delay); 1136 } 1137 1138 return need_to_disable; 1139} 1140 1141void intel_edp_panel_vdd_on(struct intel_dp *intel_dp) 1142{ 1143 if (is_edp(intel_dp)) { 1144 bool vdd = _edp_panel_vdd_on(intel_dp); 1145 1146 WARN(!vdd, "eDP VDD already requested on\n"); 1147 } 1148} 1149 1150static void edp_panel_vdd_off_sync(struct intel_dp *intel_dp) 1151{ 1152 struct drm_device *dev = intel_dp_to_dev(intel_dp); 1153 struct drm_i915_private *dev_priv = dev->dev_private; 1154 u32 pp; 1155 u32 pp_stat_reg, pp_ctrl_reg; 1156 1157 WARN_ON(!mutex_is_locked(&dev->mode_config.connection_mutex)); 1158 1159 if (!intel_dp->want_panel_vdd && edp_have_panel_vdd(intel_dp)) { 1160 struct intel_digital_port *intel_dig_port = 1161 dp_to_dig_port(intel_dp); 1162 struct intel_encoder *intel_encoder = &intel_dig_port->base; 1163 enum intel_display_power_domain power_domain; 1164 1165 DRM_DEBUG_KMS("Turning eDP VDD off\n"); 1166 1167 pp = ironlake_get_pp_control(intel_dp); 1168 pp &= ~EDP_FORCE_VDD; 1169 1170 pp_ctrl_reg = _pp_ctrl_reg(intel_dp); 1171 pp_stat_reg = _pp_stat_reg(intel_dp); 1172 1173 I915_WRITE(pp_ctrl_reg, pp); 1174 POSTING_READ(pp_ctrl_reg); 1175 1176 /* Make sure sequencer is idle before allowing subsequent activity */ 1177 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n", 1178 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg)); 1179 1180 if ((pp & POWER_TARGET_ON) == 0) 1181 intel_dp->last_power_cycle = jiffies; 1182 1183 power_domain = intel_display_port_power_domain(intel_encoder); 1184 intel_display_power_put(dev_priv, power_domain); 1185 } 1186} 1187 1188static void edp_panel_vdd_work(struct work_struct *__work) 1189{ 1190 struct intel_dp *intel_dp = container_of(to_delayed_work(__work), 1191 struct intel_dp, panel_vdd_work); 1192 struct drm_device *dev = intel_dp_to_dev(intel_dp); 1193 1194 mutex_lock(&dev->mode_config.connection_mutex); 1195 edp_panel_vdd_off_sync(intel_dp); 1196 mutex_unlock(&dev->mode_config.connection_mutex); 1197} 1198 1199static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync) 1200{ 1201 if (!is_edp(intel_dp)) 1202 return; 1203 1204 WARN(!intel_dp->want_panel_vdd, "eDP VDD not forced on"); 1205 1206 intel_dp->want_panel_vdd = false; 1207 1208 if (sync) { 1209 edp_panel_vdd_off_sync(intel_dp); 1210 } else { 1211 /* 1212 * Queue the timer to fire a long 1213 * time from now (relative to the power down delay) 1214 * to keep the panel power up across a sequence of operations 1215 */ 1216 schedule_delayed_work(&intel_dp->panel_vdd_work, 1217 msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5)); 1218 } 1219} 1220 1221void intel_edp_panel_on(struct intel_dp *intel_dp) 1222{ 1223 struct drm_device *dev = intel_dp_to_dev(intel_dp); 1224 struct drm_i915_private *dev_priv = dev->dev_private; 1225 u32 pp; 1226 u32 pp_ctrl_reg; 1227 1228 if (!is_edp(intel_dp)) 1229 return; 1230 1231 DRM_DEBUG_KMS("Turn eDP power on\n"); 1232 1233 if (edp_have_panel_power(intel_dp)) { 1234 DRM_DEBUG_KMS("eDP power already on\n"); 1235 return; 1236 } 1237 1238 wait_panel_power_cycle(intel_dp); 1239 1240 pp_ctrl_reg = _pp_ctrl_reg(intel_dp); 1241 pp = ironlake_get_pp_control(intel_dp); 1242 if (IS_GEN5(dev)) { 1243 /* ILK workaround: disable reset around power sequence */ 1244 pp &= ~PANEL_POWER_RESET; 1245 I915_WRITE(pp_ctrl_reg, pp); 1246 POSTING_READ(pp_ctrl_reg); 1247 } 1248 1249 pp |= POWER_TARGET_ON; 1250 if (!IS_GEN5(dev)) 1251 pp |= PANEL_POWER_RESET; 1252 1253 I915_WRITE(pp_ctrl_reg, pp); 1254 POSTING_READ(pp_ctrl_reg); 1255 1256 wait_panel_on(intel_dp); 1257 intel_dp->last_power_on = jiffies; 1258 1259 if (IS_GEN5(dev)) { 1260 pp |= PANEL_POWER_RESET; /* restore panel reset bit */ 1261 I915_WRITE(pp_ctrl_reg, pp); 1262 POSTING_READ(pp_ctrl_reg); 1263 } 1264} 1265 1266void intel_edp_panel_off(struct intel_dp *intel_dp) 1267{ 1268 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 1269 struct intel_encoder *intel_encoder = &intel_dig_port->base; 1270 struct drm_device *dev = intel_dp_to_dev(intel_dp); 1271 struct drm_i915_private *dev_priv = dev->dev_private; 1272 enum intel_display_power_domain power_domain; 1273 u32 pp; 1274 u32 pp_ctrl_reg; 1275 1276 if (!is_edp(intel_dp)) 1277 return; 1278 1279 DRM_DEBUG_KMS("Turn eDP power off\n"); 1280 1281 edp_wait_backlight_off(intel_dp); 1282 1283 WARN(!intel_dp->want_panel_vdd, "Need VDD to turn off panel\n"); 1284 1285 pp = ironlake_get_pp_control(intel_dp); 1286 /* We need to switch off panel power _and_ force vdd, for otherwise some 1287 * panels get very unhappy and cease to work. */ 1288 pp &= ~(POWER_TARGET_ON | PANEL_POWER_RESET | EDP_FORCE_VDD | 1289 EDP_BLC_ENABLE); 1290 1291 pp_ctrl_reg = _pp_ctrl_reg(intel_dp); 1292 1293 intel_dp->want_panel_vdd = false; 1294 1295 I915_WRITE(pp_ctrl_reg, pp); 1296 POSTING_READ(pp_ctrl_reg); 1297 1298 intel_dp->last_power_cycle = jiffies; 1299 wait_panel_off(intel_dp); 1300 1301 /* We got a reference when we enabled the VDD. */ 1302 power_domain = intel_display_port_power_domain(intel_encoder); 1303 intel_display_power_put(dev_priv, power_domain); 1304} 1305 1306void intel_edp_backlight_on(struct intel_dp *intel_dp) 1307{ 1308 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 1309 struct drm_device *dev = intel_dig_port->base.base.dev; 1310 struct drm_i915_private *dev_priv = dev->dev_private; 1311 u32 pp; 1312 u32 pp_ctrl_reg; 1313 1314 if (!is_edp(intel_dp)) 1315 return; 1316 1317 DRM_DEBUG_KMS("\n"); 1318 /* 1319 * If we enable the backlight right away following a panel power 1320 * on, we may see slight flicker as the panel syncs with the eDP 1321 * link. So delay a bit to make sure the image is solid before 1322 * allowing it to appear. 1323 */ 1324 wait_backlight_on(intel_dp); 1325 pp = ironlake_get_pp_control(intel_dp); 1326 pp |= EDP_BLC_ENABLE; 1327 1328 pp_ctrl_reg = _pp_ctrl_reg(intel_dp); 1329 1330 I915_WRITE(pp_ctrl_reg, pp); 1331 POSTING_READ(pp_ctrl_reg); 1332 1333 intel_panel_enable_backlight(intel_dp->attached_connector); 1334} 1335 1336void intel_edp_backlight_off(struct intel_dp *intel_dp) 1337{ 1338 struct drm_device *dev = intel_dp_to_dev(intel_dp); 1339 struct drm_i915_private *dev_priv = dev->dev_private; 1340 u32 pp; 1341 u32 pp_ctrl_reg; 1342 1343 if (!is_edp(intel_dp)) 1344 return; 1345 1346 intel_panel_disable_backlight(intel_dp->attached_connector); 1347 1348 DRM_DEBUG_KMS("\n"); 1349 pp = ironlake_get_pp_control(intel_dp); 1350 pp &= ~EDP_BLC_ENABLE; 1351 1352 pp_ctrl_reg = _pp_ctrl_reg(intel_dp); 1353 1354 I915_WRITE(pp_ctrl_reg, pp); 1355 POSTING_READ(pp_ctrl_reg); 1356 intel_dp->last_backlight_off = jiffies; 1357} 1358 1359static void ironlake_edp_pll_on(struct intel_dp *intel_dp) 1360{ 1361 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 1362 struct drm_crtc *crtc = intel_dig_port->base.base.crtc; 1363 struct drm_device *dev = crtc->dev; 1364 struct drm_i915_private *dev_priv = dev->dev_private; 1365 u32 dpa_ctl; 1366 1367 assert_pipe_disabled(dev_priv, 1368 to_intel_crtc(crtc)->pipe); 1369 1370 DRM_DEBUG_KMS("\n"); 1371 dpa_ctl = I915_READ(DP_A); 1372 WARN(dpa_ctl & DP_PLL_ENABLE, "dp pll on, should be off\n"); 1373 WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n"); 1374 1375 /* We don't adjust intel_dp->DP while tearing down the link, to 1376 * facilitate link retraining (e.g. after hotplug). Hence clear all 1377 * enable bits here to ensure that we don't enable too much. */ 1378 intel_dp->DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE); 1379 intel_dp->DP |= DP_PLL_ENABLE; 1380 I915_WRITE(DP_A, intel_dp->DP); 1381 POSTING_READ(DP_A); 1382 udelay(200); 1383} 1384 1385static void ironlake_edp_pll_off(struct intel_dp *intel_dp) 1386{ 1387 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 1388 struct drm_crtc *crtc = intel_dig_port->base.base.crtc; 1389 struct drm_device *dev = crtc->dev; 1390 struct drm_i915_private *dev_priv = dev->dev_private; 1391 u32 dpa_ctl; 1392 1393 assert_pipe_disabled(dev_priv, 1394 to_intel_crtc(crtc)->pipe); 1395 1396 dpa_ctl = I915_READ(DP_A); 1397 WARN((dpa_ctl & DP_PLL_ENABLE) == 0, 1398 "dp pll off, should be on\n"); 1399 WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n"); 1400 1401 /* We can't rely on the value tracked for the DP register in 1402 * intel_dp->DP because link_down must not change that (otherwise link 1403 * re-training will fail. */ 1404 dpa_ctl &= ~DP_PLL_ENABLE; 1405 I915_WRITE(DP_A, dpa_ctl); 1406 POSTING_READ(DP_A); 1407 udelay(200); 1408} 1409 1410/* If the sink supports it, try to set the power state appropriately */ 1411void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode) 1412{ 1413 int ret, i; 1414 1415 /* Should have a valid DPCD by this point */ 1416 if (intel_dp->dpcd[DP_DPCD_REV] < 0x11) 1417 return; 1418 1419 if (mode != DRM_MODE_DPMS_ON) { 1420 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER, 1421 DP_SET_POWER_D3); 1422 if (ret != 1) 1423 DRM_DEBUG_DRIVER("failed to write sink power state\n"); 1424 } else { 1425 /* 1426 * When turning on, we need to retry for 1ms to give the sink 1427 * time to wake up. 1428 */ 1429 for (i = 0; i < 3; i++) { 1430 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER, 1431 DP_SET_POWER_D0); 1432 if (ret == 1) 1433 break; 1434 msleep(1); 1435 } 1436 } 1437} 1438 1439static bool intel_dp_get_hw_state(struct intel_encoder *encoder, 1440 enum pipe *pipe) 1441{ 1442 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); 1443 enum port port = dp_to_dig_port(intel_dp)->port; 1444 struct drm_device *dev = encoder->base.dev; 1445 struct drm_i915_private *dev_priv = dev->dev_private; 1446 enum intel_display_power_domain power_domain; 1447 u32 tmp; 1448 1449 power_domain = intel_display_port_power_domain(encoder); 1450 if (!intel_display_power_enabled(dev_priv, power_domain)) 1451 return false; 1452 1453 tmp = I915_READ(intel_dp->output_reg); 1454 1455 if (!(tmp & DP_PORT_EN)) 1456 return false; 1457 1458 if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) { 1459 *pipe = PORT_TO_PIPE_CPT(tmp); 1460 } else if (IS_CHERRYVIEW(dev)) { 1461 *pipe = DP_PORT_TO_PIPE_CHV(tmp); 1462 } else if (!HAS_PCH_CPT(dev) || port == PORT_A) { 1463 *pipe = PORT_TO_PIPE(tmp); 1464 } else { 1465 u32 trans_sel; 1466 u32 trans_dp; 1467 int i; 1468 1469 switch (intel_dp->output_reg) { 1470 case PCH_DP_B: 1471 trans_sel = TRANS_DP_PORT_SEL_B; 1472 break; 1473 case PCH_DP_C: 1474 trans_sel = TRANS_DP_PORT_SEL_C; 1475 break; 1476 case PCH_DP_D: 1477 trans_sel = TRANS_DP_PORT_SEL_D; 1478 break; 1479 default: 1480 return true; 1481 } 1482 1483 for_each_pipe(i) { 1484 trans_dp = I915_READ(TRANS_DP_CTL(i)); 1485 if ((trans_dp & TRANS_DP_PORT_SEL_MASK) == trans_sel) { 1486 *pipe = i; 1487 return true; 1488 } 1489 } 1490 1491 DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n", 1492 intel_dp->output_reg); 1493 } 1494 1495 return true; 1496} 1497 1498static void intel_dp_get_config(struct intel_encoder *encoder, 1499 struct intel_crtc_config *pipe_config) 1500{ 1501 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); 1502 u32 tmp, flags = 0; 1503 struct drm_device *dev = encoder->base.dev; 1504 struct drm_i915_private *dev_priv = dev->dev_private; 1505 enum port port = dp_to_dig_port(intel_dp)->port; 1506 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); 1507 int dotclock; 1508 1509 tmp = I915_READ(intel_dp->output_reg); 1510 if (tmp & DP_AUDIO_OUTPUT_ENABLE) 1511 pipe_config->has_audio = true; 1512 1513 if ((port == PORT_A) || !HAS_PCH_CPT(dev)) { 1514 if (tmp & DP_SYNC_HS_HIGH) 1515 flags |= DRM_MODE_FLAG_PHSYNC; 1516 else 1517 flags |= DRM_MODE_FLAG_NHSYNC; 1518 1519 if (tmp & DP_SYNC_VS_HIGH) 1520 flags |= DRM_MODE_FLAG_PVSYNC; 1521 else 1522 flags |= DRM_MODE_FLAG_NVSYNC; 1523 } else { 1524 tmp = I915_READ(TRANS_DP_CTL(crtc->pipe)); 1525 if (tmp & TRANS_DP_HSYNC_ACTIVE_HIGH) 1526 flags |= DRM_MODE_FLAG_PHSYNC; 1527 else 1528 flags |= DRM_MODE_FLAG_NHSYNC; 1529 1530 if (tmp & TRANS_DP_VSYNC_ACTIVE_HIGH) 1531 flags |= DRM_MODE_FLAG_PVSYNC; 1532 else 1533 flags |= DRM_MODE_FLAG_NVSYNC; 1534 } 1535 1536 pipe_config->adjusted_mode.flags |= flags; 1537 1538 pipe_config->has_dp_encoder = true; 1539 1540 intel_dp_get_m_n(crtc, pipe_config); 1541 1542 if (port == PORT_A) { 1543 if ((I915_READ(DP_A) & DP_PLL_FREQ_MASK) == DP_PLL_FREQ_160MHZ) 1544 pipe_config->port_clock = 162000; 1545 else 1546 pipe_config->port_clock = 270000; 1547 } 1548 1549 dotclock = intel_dotclock_calculate(pipe_config->port_clock, 1550 &pipe_config->dp_m_n); 1551 1552 if (HAS_PCH_SPLIT(dev_priv->dev) && port != PORT_A) 1553 ironlake_check_encoder_dotclock(pipe_config, dotclock); 1554 1555 pipe_config->adjusted_mode.crtc_clock = dotclock; 1556 1557 if (is_edp(intel_dp) && dev_priv->vbt.edp_bpp && 1558 pipe_config->pipe_bpp > dev_priv->vbt.edp_bpp) { 1559 /* 1560 * This is a big fat ugly hack. 1561 * 1562 * Some machines in UEFI boot mode provide us a VBT that has 18 1563 * bpp and 1.62 GHz link bandwidth for eDP, which for reasons 1564 * unknown we fail to light up. Yet the same BIOS boots up with 1565 * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as 1566 * max, not what it tells us to use. 1567 * 1568 * Note: This will still be broken if the eDP panel is not lit 1569 * up by the BIOS, and thus we can't get the mode at module 1570 * load. 1571 */ 1572 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n", 1573 pipe_config->pipe_bpp, dev_priv->vbt.edp_bpp); 1574 dev_priv->vbt.edp_bpp = pipe_config->pipe_bpp; 1575 } 1576} 1577 1578static bool is_edp_psr(struct drm_device *dev) 1579{ 1580 struct drm_i915_private *dev_priv = dev->dev_private; 1581 1582 return dev_priv->psr.sink_support; 1583} 1584 1585static bool intel_edp_is_psr_enabled(struct drm_device *dev) 1586{ 1587 struct drm_i915_private *dev_priv = dev->dev_private; 1588 1589 if (!HAS_PSR(dev)) 1590 return false; 1591 1592 return I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE; 1593} 1594 1595static void intel_edp_psr_write_vsc(struct intel_dp *intel_dp, 1596 struct edp_vsc_psr *vsc_psr) 1597{ 1598 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 1599 struct drm_device *dev = dig_port->base.base.dev; 1600 struct drm_i915_private *dev_priv = dev->dev_private; 1601 struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc); 1602 u32 ctl_reg = HSW_TVIDEO_DIP_CTL(crtc->config.cpu_transcoder); 1603 u32 data_reg = HSW_TVIDEO_DIP_VSC_DATA(crtc->config.cpu_transcoder); 1604 uint32_t *data = (uint32_t *) vsc_psr; 1605 unsigned int i; 1606 1607 /* As per BSPec (Pipe Video Data Island Packet), we need to disable 1608 the video DIP being updated before program video DIP data buffer 1609 registers for DIP being updated. */ 1610 I915_WRITE(ctl_reg, 0); 1611 POSTING_READ(ctl_reg); 1612 1613 for (i = 0; i < VIDEO_DIP_VSC_DATA_SIZE; i += 4) { 1614 if (i < sizeof(struct edp_vsc_psr)) 1615 I915_WRITE(data_reg + i, *data++); 1616 else 1617 I915_WRITE(data_reg + i, 0); 1618 } 1619 1620 I915_WRITE(ctl_reg, VIDEO_DIP_ENABLE_VSC_HSW); 1621 POSTING_READ(ctl_reg); 1622} 1623 1624static void intel_edp_psr_setup(struct intel_dp *intel_dp) 1625{ 1626 struct drm_device *dev = intel_dp_to_dev(intel_dp); 1627 struct drm_i915_private *dev_priv = dev->dev_private; 1628 struct edp_vsc_psr psr_vsc; 1629 1630 if (intel_dp->psr_setup_done) 1631 return; 1632 1633 /* Prepare VSC packet as per EDP 1.3 spec, Table 3.10 */ 1634 memset(&psr_vsc, 0, sizeof(psr_vsc)); 1635 psr_vsc.sdp_header.HB0 = 0; 1636 psr_vsc.sdp_header.HB1 = 0x7; 1637 psr_vsc.sdp_header.HB2 = 0x2; 1638 psr_vsc.sdp_header.HB3 = 0x8; 1639 intel_edp_psr_write_vsc(intel_dp, &psr_vsc); 1640 1641 /* Avoid continuous PSR exit by masking memup and hpd */ 1642 I915_WRITE(EDP_PSR_DEBUG_CTL(dev), EDP_PSR_DEBUG_MASK_MEMUP | 1643 EDP_PSR_DEBUG_MASK_HPD | EDP_PSR_DEBUG_MASK_LPSP); 1644 1645 intel_dp->psr_setup_done = true; 1646} 1647 1648static void intel_edp_psr_enable_sink(struct intel_dp *intel_dp) 1649{ 1650 struct drm_device *dev = intel_dp_to_dev(intel_dp); 1651 struct drm_i915_private *dev_priv = dev->dev_private; 1652 uint32_t aux_clock_divider; 1653 int precharge = 0x3; 1654 int msg_size = 5; /* Header(4) + Message(1) */ 1655 1656 aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, 0); 1657 1658 /* Enable PSR in sink */ 1659 if (intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT) 1660 drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG, 1661 DP_PSR_ENABLE & ~DP_PSR_MAIN_LINK_ACTIVE); 1662 else 1663 drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG, 1664 DP_PSR_ENABLE | DP_PSR_MAIN_LINK_ACTIVE); 1665 1666 /* Setup AUX registers */ 1667 I915_WRITE(EDP_PSR_AUX_DATA1(dev), EDP_PSR_DPCD_COMMAND); 1668 I915_WRITE(EDP_PSR_AUX_DATA2(dev), EDP_PSR_DPCD_NORMAL_OPERATION); 1669 I915_WRITE(EDP_PSR_AUX_CTL(dev), 1670 DP_AUX_CH_CTL_TIME_OUT_400us | 1671 (msg_size << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) | 1672 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) | 1673 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT)); 1674} 1675 1676static void intel_edp_psr_enable_source(struct intel_dp *intel_dp) 1677{ 1678 struct drm_device *dev = intel_dp_to_dev(intel_dp); 1679 struct drm_i915_private *dev_priv = dev->dev_private; 1680 uint32_t max_sleep_time = 0x1f; 1681 uint32_t idle_frames = 1; 1682 uint32_t val = 0x0; 1683 const uint32_t link_entry_time = EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES; 1684 1685 if (intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT) { 1686 val |= EDP_PSR_LINK_STANDBY; 1687 val |= EDP_PSR_TP2_TP3_TIME_0us; 1688 val |= EDP_PSR_TP1_TIME_0us; 1689 val |= EDP_PSR_SKIP_AUX_EXIT; 1690 } else 1691 val |= EDP_PSR_LINK_DISABLE; 1692 1693 I915_WRITE(EDP_PSR_CTL(dev), val | 1694 (IS_BROADWELL(dev) ? 0 : link_entry_time) | 1695 max_sleep_time << EDP_PSR_MAX_SLEEP_TIME_SHIFT | 1696 idle_frames << EDP_PSR_IDLE_FRAME_SHIFT | 1697 EDP_PSR_ENABLE); 1698} 1699 1700static bool intel_edp_psr_match_conditions(struct intel_dp *intel_dp) 1701{ 1702 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 1703 struct drm_device *dev = dig_port->base.base.dev; 1704 struct drm_i915_private *dev_priv = dev->dev_private; 1705 struct drm_crtc *crtc = dig_port->base.base.crtc; 1706 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 1707 struct drm_i915_gem_object *obj = to_intel_framebuffer(crtc->primary->fb)->obj; 1708 struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base; 1709 1710 dev_priv->psr.source_ok = false; 1711 1712 if (!HAS_PSR(dev)) { 1713 DRM_DEBUG_KMS("PSR not supported on this platform\n"); 1714 return false; 1715 } 1716 1717 if ((intel_encoder->type != INTEL_OUTPUT_EDP) || 1718 (dig_port->port != PORT_A)) { 1719 DRM_DEBUG_KMS("HSW ties PSR to DDI A (eDP)\n"); 1720 return false; 1721 } 1722 1723 if (!i915.enable_psr) { 1724 DRM_DEBUG_KMS("PSR disable by flag\n"); 1725 return false; 1726 } 1727 1728 crtc = dig_port->base.base.crtc; 1729 if (crtc == NULL) { 1730 DRM_DEBUG_KMS("crtc not active for PSR\n"); 1731 return false; 1732 } 1733 1734 intel_crtc = to_intel_crtc(crtc); 1735 if (!intel_crtc_active(crtc)) { 1736 DRM_DEBUG_KMS("crtc not active for PSR\n"); 1737 return false; 1738 } 1739 1740 obj = to_intel_framebuffer(crtc->primary->fb)->obj; 1741 if (obj->tiling_mode != I915_TILING_X || 1742 obj->fence_reg == I915_FENCE_REG_NONE) { 1743 DRM_DEBUG_KMS("PSR condition failed: fb not tiled or fenced\n"); 1744 return false; 1745 } 1746 1747 if (I915_READ(SPRCTL(intel_crtc->pipe)) & SPRITE_ENABLE) { 1748 DRM_DEBUG_KMS("PSR condition failed: Sprite is Enabled\n"); 1749 return false; 1750 } 1751 1752 if (I915_READ(HSW_STEREO_3D_CTL(intel_crtc->config.cpu_transcoder)) & 1753 S3D_ENABLE) { 1754 DRM_DEBUG_KMS("PSR condition failed: Stereo 3D is Enabled\n"); 1755 return false; 1756 } 1757 1758 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) { 1759 DRM_DEBUG_KMS("PSR condition failed: Interlaced is Enabled\n"); 1760 return false; 1761 } 1762 1763 dev_priv->psr.source_ok = true; 1764 return true; 1765} 1766 1767static void intel_edp_psr_do_enable(struct intel_dp *intel_dp) 1768{ 1769 struct drm_device *dev = intel_dp_to_dev(intel_dp); 1770 1771 if (!intel_edp_psr_match_conditions(intel_dp) || 1772 intel_edp_is_psr_enabled(dev)) 1773 return; 1774 1775 /* Setup PSR once */ 1776 intel_edp_psr_setup(intel_dp); 1777 1778 /* Enable PSR on the panel */ 1779 intel_edp_psr_enable_sink(intel_dp); 1780 1781 /* Enable PSR on the host */ 1782 intel_edp_psr_enable_source(intel_dp); 1783} 1784 1785void intel_edp_psr_enable(struct intel_dp *intel_dp) 1786{ 1787 struct drm_device *dev = intel_dp_to_dev(intel_dp); 1788 1789 if (intel_edp_psr_match_conditions(intel_dp) && 1790 !intel_edp_is_psr_enabled(dev)) 1791 intel_edp_psr_do_enable(intel_dp); 1792} 1793 1794void intel_edp_psr_disable(struct intel_dp *intel_dp) 1795{ 1796 struct drm_device *dev = intel_dp_to_dev(intel_dp); 1797 struct drm_i915_private *dev_priv = dev->dev_private; 1798 1799 if (!intel_edp_is_psr_enabled(dev)) 1800 return; 1801 1802 I915_WRITE(EDP_PSR_CTL(dev), 1803 I915_READ(EDP_PSR_CTL(dev)) & ~EDP_PSR_ENABLE); 1804 1805 /* Wait till PSR is idle */ 1806 if (_wait_for((I915_READ(EDP_PSR_STATUS_CTL(dev)) & 1807 EDP_PSR_STATUS_STATE_MASK) == 0, 2000, 10)) 1808 DRM_ERROR("Timed out waiting for PSR Idle State\n"); 1809} 1810 1811void intel_edp_psr_update(struct drm_device *dev) 1812{ 1813 struct intel_encoder *encoder; 1814 struct intel_dp *intel_dp = NULL; 1815 1816 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) 1817 if (encoder->type == INTEL_OUTPUT_EDP) { 1818 intel_dp = enc_to_intel_dp(&encoder->base); 1819 1820 if (!is_edp_psr(dev)) 1821 return; 1822 1823 if (!intel_edp_psr_match_conditions(intel_dp)) 1824 intel_edp_psr_disable(intel_dp); 1825 else 1826 if (!intel_edp_is_psr_enabled(dev)) 1827 intel_edp_psr_do_enable(intel_dp); 1828 } 1829} 1830 1831static void intel_disable_dp(struct intel_encoder *encoder) 1832{ 1833 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); 1834 enum port port = dp_to_dig_port(intel_dp)->port; 1835 struct drm_device *dev = encoder->base.dev; 1836 1837 /* Make sure the panel is off before trying to change the mode. But also 1838 * ensure that we have vdd while we switch off the panel. */ 1839 intel_edp_panel_vdd_on(intel_dp); 1840 intel_edp_backlight_off(intel_dp); 1841 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF); 1842 intel_edp_panel_off(intel_dp); 1843 1844 /* cpu edp my only be disable _after_ the cpu pipe/plane is disabled. */ 1845 if (!(port == PORT_A || IS_VALLEYVIEW(dev))) 1846 intel_dp_link_down(intel_dp); 1847} 1848 1849static void g4x_post_disable_dp(struct intel_encoder *encoder) 1850{ 1851 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); 1852 enum port port = dp_to_dig_port(intel_dp)->port; 1853 1854 if (port != PORT_A) 1855 return; 1856 1857 intel_dp_link_down(intel_dp); 1858 ironlake_edp_pll_off(intel_dp); 1859} 1860 1861static void vlv_post_disable_dp(struct intel_encoder *encoder) 1862{ 1863 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); 1864 1865 intel_dp_link_down(intel_dp); 1866} 1867 1868static void chv_post_disable_dp(struct intel_encoder *encoder) 1869{ 1870 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); 1871 struct intel_digital_port *dport = dp_to_dig_port(intel_dp); 1872 struct drm_device *dev = encoder->base.dev; 1873 struct drm_i915_private *dev_priv = dev->dev_private; 1874 struct intel_crtc *intel_crtc = 1875 to_intel_crtc(encoder->base.crtc); 1876 enum dpio_channel ch = vlv_dport_to_channel(dport); 1877 enum pipe pipe = intel_crtc->pipe; 1878 u32 val; 1879 1880 intel_dp_link_down(intel_dp); 1881 1882 mutex_lock(&dev_priv->dpio_lock); 1883 1884 /* Propagate soft reset to data lane reset */ 1885 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch)); 1886 val |= CHV_PCS_REQ_SOFTRESET_EN; 1887 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val); 1888 1889 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch)); 1890 val |= CHV_PCS_REQ_SOFTRESET_EN; 1891 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val); 1892 1893 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch)); 1894 val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET); 1895 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val); 1896 1897 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch)); 1898 val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET); 1899 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val); 1900 1901 mutex_unlock(&dev_priv->dpio_lock); 1902} 1903 1904static void intel_enable_dp(struct intel_encoder *encoder) 1905{ 1906 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); 1907 struct drm_device *dev = encoder->base.dev; 1908 struct drm_i915_private *dev_priv = dev->dev_private; 1909 uint32_t dp_reg = I915_READ(intel_dp->output_reg); 1910 1911 if (WARN_ON(dp_reg & DP_PORT_EN)) 1912 return; 1913 1914 intel_edp_panel_vdd_on(intel_dp); 1915 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON); 1916 intel_dp_start_link_train(intel_dp); 1917 intel_edp_panel_on(intel_dp); 1918 edp_panel_vdd_off(intel_dp, true); 1919 intel_dp_complete_link_train(intel_dp); 1920 intel_dp_stop_link_train(intel_dp); 1921} 1922 1923static void g4x_enable_dp(struct intel_encoder *encoder) 1924{ 1925 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); 1926 1927 intel_enable_dp(encoder); 1928 intel_edp_backlight_on(intel_dp); 1929} 1930 1931static void vlv_enable_dp(struct intel_encoder *encoder) 1932{ 1933 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); 1934 1935 intel_edp_backlight_on(intel_dp); 1936} 1937 1938static void g4x_pre_enable_dp(struct intel_encoder *encoder) 1939{ 1940 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); 1941 struct intel_digital_port *dport = dp_to_dig_port(intel_dp); 1942 1943 intel_dp_prepare(encoder); 1944 1945 /* Only ilk+ has port A */ 1946 if (dport->port == PORT_A) { 1947 ironlake_set_pll_cpu_edp(intel_dp); 1948 ironlake_edp_pll_on(intel_dp); 1949 } 1950} 1951 1952static void vlv_pre_enable_dp(struct intel_encoder *encoder) 1953{ 1954 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); 1955 struct intel_digital_port *dport = dp_to_dig_port(intel_dp); 1956 struct drm_device *dev = encoder->base.dev; 1957 struct drm_i915_private *dev_priv = dev->dev_private; 1958 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc); 1959 enum dpio_channel port = vlv_dport_to_channel(dport); 1960 int pipe = intel_crtc->pipe; 1961 struct edp_power_seq power_seq; 1962 u32 val; 1963 1964 mutex_lock(&dev_priv->dpio_lock); 1965 1966 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(port)); 1967 val = 0; 1968 if (pipe) 1969 val |= (1<<21); 1970 else 1971 val &= ~(1<<21); 1972 val |= 0x001000c4; 1973 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW8(port), val); 1974 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW14(port), 0x00760018); 1975 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW23(port), 0x00400888); 1976 1977 mutex_unlock(&dev_priv->dpio_lock); 1978 1979 if (is_edp(intel_dp)) { 1980 /* init power sequencer on this pipe and port */ 1981 intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq); 1982 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp, 1983 &power_seq); 1984 } 1985 1986 intel_enable_dp(encoder); 1987 1988 vlv_wait_port_ready(dev_priv, dport); 1989} 1990 1991static void vlv_dp_pre_pll_enable(struct intel_encoder *encoder) 1992{ 1993 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base); 1994 struct drm_device *dev = encoder->base.dev; 1995 struct drm_i915_private *dev_priv = dev->dev_private; 1996 struct intel_crtc *intel_crtc = 1997 to_intel_crtc(encoder->base.crtc); 1998 enum dpio_channel port = vlv_dport_to_channel(dport); 1999 int pipe = intel_crtc->pipe; 2000 2001 intel_dp_prepare(encoder); 2002 2003 /* Program Tx lane resets to default */ 2004 mutex_lock(&dev_priv->dpio_lock); 2005 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port), 2006 DPIO_PCS_TX_LANE2_RESET | 2007 DPIO_PCS_TX_LANE1_RESET); 2008 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port), 2009 DPIO_PCS_CLK_CRI_RXEB_EIOS_EN | 2010 DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN | 2011 (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT) | 2012 DPIO_PCS_CLK_SOFT_RESET); 2013 2014 /* Fix up inter-pair skew failure */ 2015 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW12(port), 0x00750f00); 2016 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW11(port), 0x00001500); 2017 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW14(port), 0x40400000); 2018 mutex_unlock(&dev_priv->dpio_lock); 2019} 2020 2021static void chv_pre_enable_dp(struct intel_encoder *encoder) 2022{ 2023 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); 2024 struct intel_digital_port *dport = dp_to_dig_port(intel_dp); 2025 struct drm_device *dev = encoder->base.dev; 2026 struct drm_i915_private *dev_priv = dev->dev_private; 2027 struct edp_power_seq power_seq; 2028 struct intel_crtc *intel_crtc = 2029 to_intel_crtc(encoder->base.crtc); 2030 enum dpio_channel ch = vlv_dport_to_channel(dport); 2031 int pipe = intel_crtc->pipe; 2032 int data, i; 2033 u32 val; 2034 2035 mutex_lock(&dev_priv->dpio_lock); 2036 2037 /* Deassert soft data lane reset*/ 2038 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch)); 2039 val |= CHV_PCS_REQ_SOFTRESET_EN; 2040 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val); 2041 2042 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch)); 2043 val |= CHV_PCS_REQ_SOFTRESET_EN; 2044 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val); 2045 2046 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch)); 2047 val |= (DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET); 2048 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val); 2049 2050 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch)); 2051 val |= (DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET); 2052 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val); 2053 2054 /* Program Tx lane latency optimal setting*/ 2055 for (i = 0; i < 4; i++) { 2056 /* Set the latency optimal bit */ 2057 data = (i == 1) ? 0x0 : 0x6; 2058 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW11(ch, i), 2059 data << DPIO_FRC_LATENCY_SHFIT); 2060 2061 /* Set the upar bit */ 2062 data = (i == 1) ? 0x0 : 0x1; 2063 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW14(ch, i), 2064 data << DPIO_UPAR_SHIFT); 2065 } 2066 2067 /* Data lane stagger programming */ 2068 /* FIXME: Fix up value only after power analysis */ 2069 2070 mutex_unlock(&dev_priv->dpio_lock); 2071 2072 if (is_edp(intel_dp)) { 2073 /* init power sequencer on this pipe and port */ 2074 intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq); 2075 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp, 2076 &power_seq); 2077 } 2078 2079 intel_enable_dp(encoder); 2080 2081 vlv_wait_port_ready(dev_priv, dport); 2082} 2083 2084/* 2085 * Native read with retry for link status and receiver capability reads for 2086 * cases where the sink may still be asleep. 2087 * 2088 * Sinks are *supposed* to come up within 1ms from an off state, but we're also 2089 * supposed to retry 3 times per the spec. 2090 */ 2091static ssize_t 2092intel_dp_dpcd_read_wake(struct drm_dp_aux *aux, unsigned int offset, 2093 void *buffer, size_t size) 2094{ 2095 ssize_t ret; 2096 int i; 2097 2098 for (i = 0; i < 3; i++) { 2099 ret = drm_dp_dpcd_read(aux, offset, buffer, size); 2100 if (ret == size) 2101 return ret; 2102 msleep(1); 2103 } 2104 2105 return ret; 2106} 2107 2108/* 2109 * Fetch AUX CH registers 0x202 - 0x207 which contain 2110 * link status information 2111 */ 2112static bool 2113intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE]) 2114{ 2115 return intel_dp_dpcd_read_wake(&intel_dp->aux, 2116 DP_LANE0_1_STATUS, 2117 link_status, 2118 DP_LINK_STATUS_SIZE) == DP_LINK_STATUS_SIZE; 2119} 2120 2121/* 2122 * These are source-specific values; current Intel hardware supports 2123 * a maximum voltage of 800mV and a maximum pre-emphasis of 6dB 2124 */ 2125 2126static uint8_t 2127intel_dp_voltage_max(struct intel_dp *intel_dp) 2128{ 2129 struct drm_device *dev = intel_dp_to_dev(intel_dp); 2130 enum port port = dp_to_dig_port(intel_dp)->port; 2131 2132 if (IS_VALLEYVIEW(dev) || IS_BROADWELL(dev)) 2133 return DP_TRAIN_VOLTAGE_SWING_1200; 2134 else if (IS_GEN7(dev) && port == PORT_A) 2135 return DP_TRAIN_VOLTAGE_SWING_800; 2136 else if (HAS_PCH_CPT(dev) && port != PORT_A) 2137 return DP_TRAIN_VOLTAGE_SWING_1200; 2138 else 2139 return DP_TRAIN_VOLTAGE_SWING_800; 2140} 2141 2142static uint8_t 2143intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing) 2144{ 2145 struct drm_device *dev = intel_dp_to_dev(intel_dp); 2146 enum port port = dp_to_dig_port(intel_dp)->port; 2147 2148 if (IS_BROADWELL(dev)) { 2149 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) { 2150 case DP_TRAIN_VOLTAGE_SWING_400: 2151 case DP_TRAIN_VOLTAGE_SWING_600: 2152 return DP_TRAIN_PRE_EMPHASIS_6; 2153 case DP_TRAIN_VOLTAGE_SWING_800: 2154 return DP_TRAIN_PRE_EMPHASIS_3_5; 2155 case DP_TRAIN_VOLTAGE_SWING_1200: 2156 default: 2157 return DP_TRAIN_PRE_EMPHASIS_0; 2158 } 2159 } else if (IS_HASWELL(dev)) { 2160 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) { 2161 case DP_TRAIN_VOLTAGE_SWING_400: 2162 return DP_TRAIN_PRE_EMPHASIS_9_5; 2163 case DP_TRAIN_VOLTAGE_SWING_600: 2164 return DP_TRAIN_PRE_EMPHASIS_6; 2165 case DP_TRAIN_VOLTAGE_SWING_800: 2166 return DP_TRAIN_PRE_EMPHASIS_3_5; 2167 case DP_TRAIN_VOLTAGE_SWING_1200: 2168 default: 2169 return DP_TRAIN_PRE_EMPHASIS_0; 2170 } 2171 } else if (IS_VALLEYVIEW(dev)) { 2172 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) { 2173 case DP_TRAIN_VOLTAGE_SWING_400: 2174 return DP_TRAIN_PRE_EMPHASIS_9_5; 2175 case DP_TRAIN_VOLTAGE_SWING_600: 2176 return DP_TRAIN_PRE_EMPHASIS_6; 2177 case DP_TRAIN_VOLTAGE_SWING_800: 2178 return DP_TRAIN_PRE_EMPHASIS_3_5; 2179 case DP_TRAIN_VOLTAGE_SWING_1200: 2180 default: 2181 return DP_TRAIN_PRE_EMPHASIS_0; 2182 } 2183 } else if (IS_GEN7(dev) && port == PORT_A) { 2184 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) { 2185 case DP_TRAIN_VOLTAGE_SWING_400: 2186 return DP_TRAIN_PRE_EMPHASIS_6; 2187 case DP_TRAIN_VOLTAGE_SWING_600: 2188 case DP_TRAIN_VOLTAGE_SWING_800: 2189 return DP_TRAIN_PRE_EMPHASIS_3_5; 2190 default: 2191 return DP_TRAIN_PRE_EMPHASIS_0; 2192 } 2193 } else { 2194 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) { 2195 case DP_TRAIN_VOLTAGE_SWING_400: 2196 return DP_TRAIN_PRE_EMPHASIS_6; 2197 case DP_TRAIN_VOLTAGE_SWING_600: 2198 return DP_TRAIN_PRE_EMPHASIS_6; 2199 case DP_TRAIN_VOLTAGE_SWING_800: 2200 return DP_TRAIN_PRE_EMPHASIS_3_5; 2201 case DP_TRAIN_VOLTAGE_SWING_1200: 2202 default: 2203 return DP_TRAIN_PRE_EMPHASIS_0; 2204 } 2205 } 2206} 2207 2208static uint32_t intel_vlv_signal_levels(struct intel_dp *intel_dp) 2209{ 2210 struct drm_device *dev = intel_dp_to_dev(intel_dp); 2211 struct drm_i915_private *dev_priv = dev->dev_private; 2212 struct intel_digital_port *dport = dp_to_dig_port(intel_dp); 2213 struct intel_crtc *intel_crtc = 2214 to_intel_crtc(dport->base.base.crtc); 2215 unsigned long demph_reg_value, preemph_reg_value, 2216 uniqtranscale_reg_value; 2217 uint8_t train_set = intel_dp->train_set[0]; 2218 enum dpio_channel port = vlv_dport_to_channel(dport); 2219 int pipe = intel_crtc->pipe; 2220 2221 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) { 2222 case DP_TRAIN_PRE_EMPHASIS_0: 2223 preemph_reg_value = 0x0004000; 2224 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { 2225 case DP_TRAIN_VOLTAGE_SWING_400: 2226 demph_reg_value = 0x2B405555; 2227 uniqtranscale_reg_value = 0x552AB83A; 2228 break; 2229 case DP_TRAIN_VOLTAGE_SWING_600: 2230 demph_reg_value = 0x2B404040; 2231 uniqtranscale_reg_value = 0x5548B83A; 2232 break; 2233 case DP_TRAIN_VOLTAGE_SWING_800: 2234 demph_reg_value = 0x2B245555; 2235 uniqtranscale_reg_value = 0x5560B83A; 2236 break; 2237 case DP_TRAIN_VOLTAGE_SWING_1200: 2238 demph_reg_value = 0x2B405555; 2239 uniqtranscale_reg_value = 0x5598DA3A; 2240 break; 2241 default: 2242 return 0; 2243 } 2244 break; 2245 case DP_TRAIN_PRE_EMPHASIS_3_5: 2246 preemph_reg_value = 0x0002000; 2247 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { 2248 case DP_TRAIN_VOLTAGE_SWING_400: 2249 demph_reg_value = 0x2B404040; 2250 uniqtranscale_reg_value = 0x5552B83A; 2251 break; 2252 case DP_TRAIN_VOLTAGE_SWING_600: 2253 demph_reg_value = 0x2B404848; 2254 uniqtranscale_reg_value = 0x5580B83A; 2255 break; 2256 case DP_TRAIN_VOLTAGE_SWING_800: 2257 demph_reg_value = 0x2B404040; 2258 uniqtranscale_reg_value = 0x55ADDA3A; 2259 break; 2260 default: 2261 return 0; 2262 } 2263 break; 2264 case DP_TRAIN_PRE_EMPHASIS_6: 2265 preemph_reg_value = 0x0000000; 2266 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { 2267 case DP_TRAIN_VOLTAGE_SWING_400: 2268 demph_reg_value = 0x2B305555; 2269 uniqtranscale_reg_value = 0x5570B83A; 2270 break; 2271 case DP_TRAIN_VOLTAGE_SWING_600: 2272 demph_reg_value = 0x2B2B4040; 2273 uniqtranscale_reg_value = 0x55ADDA3A; 2274 break; 2275 default: 2276 return 0; 2277 } 2278 break; 2279 case DP_TRAIN_PRE_EMPHASIS_9_5: 2280 preemph_reg_value = 0x0006000; 2281 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { 2282 case DP_TRAIN_VOLTAGE_SWING_400: 2283 demph_reg_value = 0x1B405555; 2284 uniqtranscale_reg_value = 0x55ADDA3A; 2285 break; 2286 default: 2287 return 0; 2288 } 2289 break; 2290 default: 2291 return 0; 2292 } 2293 2294 mutex_lock(&dev_priv->dpio_lock); 2295 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x00000000); 2296 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW4(port), demph_reg_value); 2297 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(port), 2298 uniqtranscale_reg_value); 2299 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(port), 0x0C782040); 2300 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW11(port), 0x00030000); 2301 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), preemph_reg_value); 2302 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x80000000); 2303 mutex_unlock(&dev_priv->dpio_lock); 2304 2305 return 0; 2306} 2307 2308static uint32_t intel_chv_signal_levels(struct intel_dp *intel_dp) 2309{ 2310 struct drm_device *dev = intel_dp_to_dev(intel_dp); 2311 struct drm_i915_private *dev_priv = dev->dev_private; 2312 struct intel_digital_port *dport = dp_to_dig_port(intel_dp); 2313 struct intel_crtc *intel_crtc = to_intel_crtc(dport->base.base.crtc); 2314 u32 deemph_reg_value, margin_reg_value, val; 2315 uint8_t train_set = intel_dp->train_set[0]; 2316 enum dpio_channel ch = vlv_dport_to_channel(dport); 2317 enum pipe pipe = intel_crtc->pipe; 2318 int i; 2319 2320 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) { 2321 case DP_TRAIN_PRE_EMPHASIS_0: 2322 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { 2323 case DP_TRAIN_VOLTAGE_SWING_400: 2324 deemph_reg_value = 128; 2325 margin_reg_value = 52; 2326 break; 2327 case DP_TRAIN_VOLTAGE_SWING_600: 2328 deemph_reg_value = 128; 2329 margin_reg_value = 77; 2330 break; 2331 case DP_TRAIN_VOLTAGE_SWING_800: 2332 deemph_reg_value = 128; 2333 margin_reg_value = 102; 2334 break; 2335 case DP_TRAIN_VOLTAGE_SWING_1200: 2336 deemph_reg_value = 128; 2337 margin_reg_value = 154; 2338 /* FIXME extra to set for 1200 */ 2339 break; 2340 default: 2341 return 0; 2342 } 2343 break; 2344 case DP_TRAIN_PRE_EMPHASIS_3_5: 2345 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { 2346 case DP_TRAIN_VOLTAGE_SWING_400: 2347 deemph_reg_value = 85; 2348 margin_reg_value = 78; 2349 break; 2350 case DP_TRAIN_VOLTAGE_SWING_600: 2351 deemph_reg_value = 85; 2352 margin_reg_value = 116; 2353 break; 2354 case DP_TRAIN_VOLTAGE_SWING_800: 2355 deemph_reg_value = 85; 2356 margin_reg_value = 154; 2357 break; 2358 default: 2359 return 0; 2360 } 2361 break; 2362 case DP_TRAIN_PRE_EMPHASIS_6: 2363 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { 2364 case DP_TRAIN_VOLTAGE_SWING_400: 2365 deemph_reg_value = 64; 2366 margin_reg_value = 104; 2367 break; 2368 case DP_TRAIN_VOLTAGE_SWING_600: 2369 deemph_reg_value = 64; 2370 margin_reg_value = 154; 2371 break; 2372 default: 2373 return 0; 2374 } 2375 break; 2376 case DP_TRAIN_PRE_EMPHASIS_9_5: 2377 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { 2378 case DP_TRAIN_VOLTAGE_SWING_400: 2379 deemph_reg_value = 43; 2380 margin_reg_value = 154; 2381 break; 2382 default: 2383 return 0; 2384 } 2385 break; 2386 default: 2387 return 0; 2388 } 2389 2390 mutex_lock(&dev_priv->dpio_lock); 2391 2392 /* Clear calc init */ 2393 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch)); 2394 val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3); 2395 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val); 2396 2397 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch)); 2398 val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3); 2399 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val); 2400 2401 /* Program swing deemph */ 2402 for (i = 0; i < 4; i++) { 2403 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW4(ch, i)); 2404 val &= ~DPIO_SWING_DEEMPH9P5_MASK; 2405 val |= deemph_reg_value << DPIO_SWING_DEEMPH9P5_SHIFT; 2406 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW4(ch, i), val); 2407 } 2408 2409 /* Program swing margin */ 2410 for (i = 0; i < 4; i++) { 2411 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW2(ch, i)); 2412 val &= ~DPIO_SWING_MARGIN_MASK; 2413 val |= margin_reg_value << DPIO_SWING_MARGIN_SHIFT; 2414 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW2(ch, i), val); 2415 } 2416 2417 /* Disable unique transition scale */ 2418 for (i = 0; i < 4; i++) { 2419 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW3(ch, i)); 2420 val &= ~DPIO_TX_UNIQ_TRANS_SCALE_EN; 2421 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW3(ch, i), val); 2422 } 2423 2424 if (((train_set & DP_TRAIN_PRE_EMPHASIS_MASK) 2425 == DP_TRAIN_PRE_EMPHASIS_0) && 2426 ((train_set & DP_TRAIN_VOLTAGE_SWING_MASK) 2427 == DP_TRAIN_VOLTAGE_SWING_1200)) { 2428 2429 /* 2430 * The document said it needs to set bit 27 for ch0 and bit 26 2431 * for ch1. Might be a typo in the doc. 2432 * For now, for this unique transition scale selection, set bit 2433 * 27 for ch0 and ch1. 2434 */ 2435 for (i = 0; i < 4; i++) { 2436 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW3(ch, i)); 2437 val |= DPIO_TX_UNIQ_TRANS_SCALE_EN; 2438 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW3(ch, i), val); 2439 } 2440 2441 for (i = 0; i < 4; i++) { 2442 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW2(ch, i)); 2443 val &= ~(0xff << DPIO_UNIQ_TRANS_SCALE_SHIFT); 2444 val |= (0x9a << DPIO_UNIQ_TRANS_SCALE_SHIFT); 2445 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW2(ch, i), val); 2446 } 2447 } 2448 2449 /* Start swing calculation */ 2450 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch)); 2451 val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3; 2452 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val); 2453 2454 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch)); 2455 val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3; 2456 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val); 2457 2458 /* LRC Bypass */ 2459 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW30); 2460 val |= DPIO_LRC_BYPASS; 2461 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW30, val); 2462 2463 mutex_unlock(&dev_priv->dpio_lock); 2464 2465 return 0; 2466} 2467 2468static void 2469intel_get_adjust_train(struct intel_dp *intel_dp, 2470 const uint8_t link_status[DP_LINK_STATUS_SIZE]) 2471{ 2472 uint8_t v = 0; 2473 uint8_t p = 0; 2474 int lane; 2475 uint8_t voltage_max; 2476 uint8_t preemph_max; 2477 2478 for (lane = 0; lane < intel_dp->lane_count; lane++) { 2479 uint8_t this_v = drm_dp_get_adjust_request_voltage(link_status, lane); 2480 uint8_t this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane); 2481 2482 if (this_v > v) 2483 v = this_v; 2484 if (this_p > p) 2485 p = this_p; 2486 } 2487 2488 voltage_max = intel_dp_voltage_max(intel_dp); 2489 if (v >= voltage_max) 2490 v = voltage_max | DP_TRAIN_MAX_SWING_REACHED; 2491 2492 preemph_max = intel_dp_pre_emphasis_max(intel_dp, v); 2493 if (p >= preemph_max) 2494 p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED; 2495 2496 for (lane = 0; lane < 4; lane++) 2497 intel_dp->train_set[lane] = v | p; 2498} 2499 2500static uint32_t 2501intel_gen4_signal_levels(uint8_t train_set) 2502{ 2503 uint32_t signal_levels = 0; 2504 2505 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { 2506 case DP_TRAIN_VOLTAGE_SWING_400: 2507 default: 2508 signal_levels |= DP_VOLTAGE_0_4; 2509 break; 2510 case DP_TRAIN_VOLTAGE_SWING_600: 2511 signal_levels |= DP_VOLTAGE_0_6; 2512 break; 2513 case DP_TRAIN_VOLTAGE_SWING_800: 2514 signal_levels |= DP_VOLTAGE_0_8; 2515 break; 2516 case DP_TRAIN_VOLTAGE_SWING_1200: 2517 signal_levels |= DP_VOLTAGE_1_2; 2518 break; 2519 } 2520 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) { 2521 case DP_TRAIN_PRE_EMPHASIS_0: 2522 default: 2523 signal_levels |= DP_PRE_EMPHASIS_0; 2524 break; 2525 case DP_TRAIN_PRE_EMPHASIS_3_5: 2526 signal_levels |= DP_PRE_EMPHASIS_3_5; 2527 break; 2528 case DP_TRAIN_PRE_EMPHASIS_6: 2529 signal_levels |= DP_PRE_EMPHASIS_6; 2530 break; 2531 case DP_TRAIN_PRE_EMPHASIS_9_5: 2532 signal_levels |= DP_PRE_EMPHASIS_9_5; 2533 break; 2534 } 2535 return signal_levels; 2536} 2537 2538/* Gen6's DP voltage swing and pre-emphasis control */ 2539static uint32_t 2540intel_gen6_edp_signal_levels(uint8_t train_set) 2541{ 2542 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK | 2543 DP_TRAIN_PRE_EMPHASIS_MASK); 2544 switch (signal_levels) { 2545 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0: 2546 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0: 2547 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B; 2548 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5: 2549 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B; 2550 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6: 2551 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6: 2552 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B; 2553 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5: 2554 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5: 2555 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B; 2556 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0: 2557 case DP_TRAIN_VOLTAGE_SWING_1200 | DP_TRAIN_PRE_EMPHASIS_0: 2558 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B; 2559 default: 2560 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:" 2561 "0x%x\n", signal_levels); 2562 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B; 2563 } 2564} 2565 2566/* Gen7's DP voltage swing and pre-emphasis control */ 2567static uint32_t 2568intel_gen7_edp_signal_levels(uint8_t train_set) 2569{ 2570 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK | 2571 DP_TRAIN_PRE_EMPHASIS_MASK); 2572 switch (signal_levels) { 2573 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0: 2574 return EDP_LINK_TRAIN_400MV_0DB_IVB; 2575 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5: 2576 return EDP_LINK_TRAIN_400MV_3_5DB_IVB; 2577 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6: 2578 return EDP_LINK_TRAIN_400MV_6DB_IVB; 2579 2580 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0: 2581 return EDP_LINK_TRAIN_600MV_0DB_IVB; 2582 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5: 2583 return EDP_LINK_TRAIN_600MV_3_5DB_IVB; 2584 2585 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0: 2586 return EDP_LINK_TRAIN_800MV_0DB_IVB; 2587 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5: 2588 return EDP_LINK_TRAIN_800MV_3_5DB_IVB; 2589 2590 default: 2591 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:" 2592 "0x%x\n", signal_levels); 2593 return EDP_LINK_TRAIN_500MV_0DB_IVB; 2594 } 2595} 2596 2597/* Gen7.5's (HSW) DP voltage swing and pre-emphasis control */ 2598static uint32_t 2599intel_hsw_signal_levels(uint8_t train_set) 2600{ 2601 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK | 2602 DP_TRAIN_PRE_EMPHASIS_MASK); 2603 switch (signal_levels) { 2604 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0: 2605 return DDI_BUF_EMP_400MV_0DB_HSW; 2606 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5: 2607 return DDI_BUF_EMP_400MV_3_5DB_HSW; 2608 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6: 2609 return DDI_BUF_EMP_400MV_6DB_HSW; 2610 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_9_5: 2611 return DDI_BUF_EMP_400MV_9_5DB_HSW; 2612 2613 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0: 2614 return DDI_BUF_EMP_600MV_0DB_HSW; 2615 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5: 2616 return DDI_BUF_EMP_600MV_3_5DB_HSW; 2617 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6: 2618 return DDI_BUF_EMP_600MV_6DB_HSW; 2619 2620 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0: 2621 return DDI_BUF_EMP_800MV_0DB_HSW; 2622 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5: 2623 return DDI_BUF_EMP_800MV_3_5DB_HSW; 2624 default: 2625 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:" 2626 "0x%x\n", signal_levels); 2627 return DDI_BUF_EMP_400MV_0DB_HSW; 2628 } 2629} 2630 2631static uint32_t 2632intel_bdw_signal_levels(uint8_t train_set) 2633{ 2634 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK | 2635 DP_TRAIN_PRE_EMPHASIS_MASK); 2636 switch (signal_levels) { 2637 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0: 2638 return DDI_BUF_EMP_400MV_0DB_BDW; /* Sel0 */ 2639 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5: 2640 return DDI_BUF_EMP_400MV_3_5DB_BDW; /* Sel1 */ 2641 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6: 2642 return DDI_BUF_EMP_400MV_6DB_BDW; /* Sel2 */ 2643 2644 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0: 2645 return DDI_BUF_EMP_600MV_0DB_BDW; /* Sel3 */ 2646 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5: 2647 return DDI_BUF_EMP_600MV_3_5DB_BDW; /* Sel4 */ 2648 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6: 2649 return DDI_BUF_EMP_600MV_6DB_BDW; /* Sel5 */ 2650 2651 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0: 2652 return DDI_BUF_EMP_800MV_0DB_BDW; /* Sel6 */ 2653 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5: 2654 return DDI_BUF_EMP_800MV_3_5DB_BDW; /* Sel7 */ 2655 2656 case DP_TRAIN_VOLTAGE_SWING_1200 | DP_TRAIN_PRE_EMPHASIS_0: 2657 return DDI_BUF_EMP_1200MV_0DB_BDW; /* Sel8 */ 2658 2659 default: 2660 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:" 2661 "0x%x\n", signal_levels); 2662 return DDI_BUF_EMP_400MV_0DB_BDW; /* Sel0 */ 2663 } 2664} 2665 2666/* Properly updates "DP" with the correct signal levels. */ 2667static void 2668intel_dp_set_signal_levels(struct intel_dp *intel_dp, uint32_t *DP) 2669{ 2670 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 2671 enum port port = intel_dig_port->port; 2672 struct drm_device *dev = intel_dig_port->base.base.dev; 2673 uint32_t signal_levels, mask; 2674 uint8_t train_set = intel_dp->train_set[0]; 2675 2676 if (IS_BROADWELL(dev)) { 2677 signal_levels = intel_bdw_signal_levels(train_set); 2678 mask = DDI_BUF_EMP_MASK; 2679 } else if (IS_HASWELL(dev)) { 2680 signal_levels = intel_hsw_signal_levels(train_set); 2681 mask = DDI_BUF_EMP_MASK; 2682 } else if (IS_CHERRYVIEW(dev)) { 2683 signal_levels = intel_chv_signal_levels(intel_dp); 2684 mask = 0; 2685 } else if (IS_VALLEYVIEW(dev)) { 2686 signal_levels = intel_vlv_signal_levels(intel_dp); 2687 mask = 0; 2688 } else if (IS_GEN7(dev) && port == PORT_A) { 2689 signal_levels = intel_gen7_edp_signal_levels(train_set); 2690 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_IVB; 2691 } else if (IS_GEN6(dev) && port == PORT_A) { 2692 signal_levels = intel_gen6_edp_signal_levels(train_set); 2693 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB; 2694 } else { 2695 signal_levels = intel_gen4_signal_levels(train_set); 2696 mask = DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK; 2697 } 2698 2699 DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels); 2700 2701 *DP = (*DP & ~mask) | signal_levels; 2702} 2703 2704static bool 2705intel_dp_set_link_train(struct intel_dp *intel_dp, 2706 uint32_t *DP, 2707 uint8_t dp_train_pat) 2708{ 2709 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 2710 struct drm_device *dev = intel_dig_port->base.base.dev; 2711 struct drm_i915_private *dev_priv = dev->dev_private; 2712 enum port port = intel_dig_port->port; 2713 uint8_t buf[sizeof(intel_dp->train_set) + 1]; 2714 int ret, len; 2715 2716 if (HAS_DDI(dev)) { 2717 uint32_t temp = I915_READ(DP_TP_CTL(port)); 2718 2719 if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE) 2720 temp |= DP_TP_CTL_SCRAMBLE_DISABLE; 2721 else 2722 temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE; 2723 2724 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK; 2725 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) { 2726 case DP_TRAINING_PATTERN_DISABLE: 2727 temp |= DP_TP_CTL_LINK_TRAIN_NORMAL; 2728 2729 break; 2730 case DP_TRAINING_PATTERN_1: 2731 temp |= DP_TP_CTL_LINK_TRAIN_PAT1; 2732 break; 2733 case DP_TRAINING_PATTERN_2: 2734 temp |= DP_TP_CTL_LINK_TRAIN_PAT2; 2735 break; 2736 case DP_TRAINING_PATTERN_3: 2737 temp |= DP_TP_CTL_LINK_TRAIN_PAT3; 2738 break; 2739 } 2740 I915_WRITE(DP_TP_CTL(port), temp); 2741 2742 } else if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) { 2743 *DP &= ~DP_LINK_TRAIN_MASK_CPT; 2744 2745 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) { 2746 case DP_TRAINING_PATTERN_DISABLE: 2747 *DP |= DP_LINK_TRAIN_OFF_CPT; 2748 break; 2749 case DP_TRAINING_PATTERN_1: 2750 *DP |= DP_LINK_TRAIN_PAT_1_CPT; 2751 break; 2752 case DP_TRAINING_PATTERN_2: 2753 *DP |= DP_LINK_TRAIN_PAT_2_CPT; 2754 break; 2755 case DP_TRAINING_PATTERN_3: 2756 DRM_ERROR("DP training pattern 3 not supported\n"); 2757 *DP |= DP_LINK_TRAIN_PAT_2_CPT; 2758 break; 2759 } 2760 2761 } else { 2762 *DP &= ~DP_LINK_TRAIN_MASK; 2763 2764 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) { 2765 case DP_TRAINING_PATTERN_DISABLE: 2766 *DP |= DP_LINK_TRAIN_OFF; 2767 break; 2768 case DP_TRAINING_PATTERN_1: 2769 *DP |= DP_LINK_TRAIN_PAT_1; 2770 break; 2771 case DP_TRAINING_PATTERN_2: 2772 *DP |= DP_LINK_TRAIN_PAT_2; 2773 break; 2774 case DP_TRAINING_PATTERN_3: 2775 DRM_ERROR("DP training pattern 3 not supported\n"); 2776 *DP |= DP_LINK_TRAIN_PAT_2; 2777 break; 2778 } 2779 } 2780 2781 I915_WRITE(intel_dp->output_reg, *DP); 2782 POSTING_READ(intel_dp->output_reg); 2783 2784 buf[0] = dp_train_pat; 2785 if ((dp_train_pat & DP_TRAINING_PATTERN_MASK) == 2786 DP_TRAINING_PATTERN_DISABLE) { 2787 /* don't write DP_TRAINING_LANEx_SET on disable */ 2788 len = 1; 2789 } else { 2790 /* DP_TRAINING_LANEx_SET follow DP_TRAINING_PATTERN_SET */ 2791 memcpy(buf + 1, intel_dp->train_set, intel_dp->lane_count); 2792 len = intel_dp->lane_count + 1; 2793 } 2794 2795 ret = drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_PATTERN_SET, 2796 buf, len); 2797 2798 return ret == len; 2799} 2800 2801static bool 2802intel_dp_reset_link_train(struct intel_dp *intel_dp, uint32_t *DP, 2803 uint8_t dp_train_pat) 2804{ 2805 memset(intel_dp->train_set, 0, sizeof(intel_dp->train_set)); 2806 intel_dp_set_signal_levels(intel_dp, DP); 2807 return intel_dp_set_link_train(intel_dp, DP, dp_train_pat); 2808} 2809 2810static bool 2811intel_dp_update_link_train(struct intel_dp *intel_dp, uint32_t *DP, 2812 const uint8_t link_status[DP_LINK_STATUS_SIZE]) 2813{ 2814 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 2815 struct drm_device *dev = intel_dig_port->base.base.dev; 2816 struct drm_i915_private *dev_priv = dev->dev_private; 2817 int ret; 2818 2819 intel_get_adjust_train(intel_dp, link_status); 2820 intel_dp_set_signal_levels(intel_dp, DP); 2821 2822 I915_WRITE(intel_dp->output_reg, *DP); 2823 POSTING_READ(intel_dp->output_reg); 2824 2825 ret = drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_LANE0_SET, 2826 intel_dp->train_set, intel_dp->lane_count); 2827 2828 return ret == intel_dp->lane_count; 2829} 2830 2831static void intel_dp_set_idle_link_train(struct intel_dp *intel_dp) 2832{ 2833 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 2834 struct drm_device *dev = intel_dig_port->base.base.dev; 2835 struct drm_i915_private *dev_priv = dev->dev_private; 2836 enum port port = intel_dig_port->port; 2837 uint32_t val; 2838 2839 if (!HAS_DDI(dev)) 2840 return; 2841 2842 val = I915_READ(DP_TP_CTL(port)); 2843 val &= ~DP_TP_CTL_LINK_TRAIN_MASK; 2844 val |= DP_TP_CTL_LINK_TRAIN_IDLE; 2845 I915_WRITE(DP_TP_CTL(port), val); 2846 2847 /* 2848 * On PORT_A we can have only eDP in SST mode. There the only reason 2849 * we need to set idle transmission mode is to work around a HW issue 2850 * where we enable the pipe while not in idle link-training mode. 2851 * In this case there is requirement to wait for a minimum number of 2852 * idle patterns to be sent. 2853 */ 2854 if (port == PORT_A) 2855 return; 2856 2857 if (wait_for((I915_READ(DP_TP_STATUS(port)) & DP_TP_STATUS_IDLE_DONE), 2858 1)) 2859 DRM_ERROR("Timed out waiting for DP idle patterns\n"); 2860} 2861 2862/* Enable corresponding port and start training pattern 1 */ 2863void 2864intel_dp_start_link_train(struct intel_dp *intel_dp) 2865{ 2866 struct drm_encoder *encoder = &dp_to_dig_port(intel_dp)->base.base; 2867 struct drm_device *dev = encoder->dev; 2868 int i; 2869 uint8_t voltage; 2870 int voltage_tries, loop_tries; 2871 uint32_t DP = intel_dp->DP; 2872 uint8_t link_config[2]; 2873 2874 if (HAS_DDI(dev)) 2875 intel_ddi_prepare_link_retrain(encoder); 2876 2877 /* Write the link configuration data */ 2878 link_config[0] = intel_dp->link_bw; 2879 link_config[1] = intel_dp->lane_count; 2880 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd)) 2881 link_config[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN; 2882 drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_BW_SET, link_config, 2); 2883 2884 link_config[0] = 0; 2885 link_config[1] = DP_SET_ANSI_8B10B; 2886 drm_dp_dpcd_write(&intel_dp->aux, DP_DOWNSPREAD_CTRL, link_config, 2); 2887 2888 DP |= DP_PORT_EN; 2889 2890 /* clock recovery */ 2891 if (!intel_dp_reset_link_train(intel_dp, &DP, 2892 DP_TRAINING_PATTERN_1 | 2893 DP_LINK_SCRAMBLING_DISABLE)) { 2894 DRM_ERROR("failed to enable link training\n"); 2895 return; 2896 } 2897 2898 voltage = 0xff; 2899 voltage_tries = 0; 2900 loop_tries = 0; 2901 for (;;) { 2902 uint8_t link_status[DP_LINK_STATUS_SIZE]; 2903 2904 drm_dp_link_train_clock_recovery_delay(intel_dp->dpcd); 2905 if (!intel_dp_get_link_status(intel_dp, link_status)) { 2906 DRM_ERROR("failed to get link status\n"); 2907 break; 2908 } 2909 2910 if (drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) { 2911 DRM_DEBUG_KMS("clock recovery OK\n"); 2912 break; 2913 } 2914 2915 /* Check to see if we've tried the max voltage */ 2916 for (i = 0; i < intel_dp->lane_count; i++) 2917 if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0) 2918 break; 2919 if (i == intel_dp->lane_count) { 2920 ++loop_tries; 2921 if (loop_tries == 5) { 2922 DRM_ERROR("too many full retries, give up\n"); 2923 break; 2924 } 2925 intel_dp_reset_link_train(intel_dp, &DP, 2926 DP_TRAINING_PATTERN_1 | 2927 DP_LINK_SCRAMBLING_DISABLE); 2928 voltage_tries = 0; 2929 continue; 2930 } 2931 2932 /* Check to see if we've tried the same voltage 5 times */ 2933 if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) { 2934 ++voltage_tries; 2935 if (voltage_tries == 5) { 2936 DRM_ERROR("too many voltage retries, give up\n"); 2937 break; 2938 } 2939 } else 2940 voltage_tries = 0; 2941 voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK; 2942 2943 /* Update training set as requested by target */ 2944 if (!intel_dp_update_link_train(intel_dp, &DP, link_status)) { 2945 DRM_ERROR("failed to update link training\n"); 2946 break; 2947 } 2948 } 2949 2950 intel_dp->DP = DP; 2951} 2952 2953void 2954intel_dp_complete_link_train(struct intel_dp *intel_dp) 2955{ 2956 bool channel_eq = false; 2957 int tries, cr_tries; 2958 uint32_t DP = intel_dp->DP; 2959 uint32_t training_pattern = DP_TRAINING_PATTERN_2; 2960 2961 /* Training Pattern 3 for HBR2 ot 1.2 devices that support it*/ 2962 if (intel_dp->link_bw == DP_LINK_BW_5_4 || intel_dp->use_tps3) 2963 training_pattern = DP_TRAINING_PATTERN_3; 2964 2965 /* channel equalization */ 2966 if (!intel_dp_set_link_train(intel_dp, &DP, 2967 training_pattern | 2968 DP_LINK_SCRAMBLING_DISABLE)) { 2969 DRM_ERROR("failed to start channel equalization\n"); 2970 return; 2971 } 2972 2973 tries = 0; 2974 cr_tries = 0; 2975 channel_eq = false; 2976 for (;;) { 2977 uint8_t link_status[DP_LINK_STATUS_SIZE]; 2978 2979 if (cr_tries > 5) { 2980 DRM_ERROR("failed to train DP, aborting\n"); 2981 break; 2982 } 2983 2984 drm_dp_link_train_channel_eq_delay(intel_dp->dpcd); 2985 if (!intel_dp_get_link_status(intel_dp, link_status)) { 2986 DRM_ERROR("failed to get link status\n"); 2987 break; 2988 } 2989 2990 /* Make sure clock is still ok */ 2991 if (!drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) { 2992 intel_dp_start_link_train(intel_dp); 2993 intel_dp_set_link_train(intel_dp, &DP, 2994 training_pattern | 2995 DP_LINK_SCRAMBLING_DISABLE); 2996 cr_tries++; 2997 continue; 2998 } 2999 3000 if (drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) { 3001 channel_eq = true; 3002 break; 3003 } 3004 3005 /* Try 5 times, then try clock recovery if that fails */ 3006 if (tries > 5) { 3007 intel_dp_link_down(intel_dp); 3008 intel_dp_start_link_train(intel_dp); 3009 intel_dp_set_link_train(intel_dp, &DP, 3010 training_pattern | 3011 DP_LINK_SCRAMBLING_DISABLE); 3012 tries = 0; 3013 cr_tries++; 3014 continue; 3015 } 3016 3017 /* Update training set as requested by target */ 3018 if (!intel_dp_update_link_train(intel_dp, &DP, link_status)) { 3019 DRM_ERROR("failed to update link training\n"); 3020 break; 3021 } 3022 ++tries; 3023 } 3024 3025 intel_dp_set_idle_link_train(intel_dp); 3026 3027 intel_dp->DP = DP; 3028 3029 if (channel_eq) 3030 DRM_DEBUG_KMS("Channel EQ done. DP Training successful\n"); 3031 3032} 3033 3034void intel_dp_stop_link_train(struct intel_dp *intel_dp) 3035{ 3036 intel_dp_set_link_train(intel_dp, &intel_dp->DP, 3037 DP_TRAINING_PATTERN_DISABLE); 3038} 3039 3040static void 3041intel_dp_link_down(struct intel_dp *intel_dp) 3042{ 3043 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 3044 enum port port = intel_dig_port->port; 3045 struct drm_device *dev = intel_dig_port->base.base.dev; 3046 struct drm_i915_private *dev_priv = dev->dev_private; 3047 struct intel_crtc *intel_crtc = 3048 to_intel_crtc(intel_dig_port->base.base.crtc); 3049 uint32_t DP = intel_dp->DP; 3050 3051 if (WARN_ON(HAS_DDI(dev))) 3052 return; 3053 3054 if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0)) 3055 return; 3056 3057 DRM_DEBUG_KMS("\n"); 3058 3059 if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) { 3060 DP &= ~DP_LINK_TRAIN_MASK_CPT; 3061 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT); 3062 } else { 3063 DP &= ~DP_LINK_TRAIN_MASK; 3064 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE); 3065 } 3066 POSTING_READ(intel_dp->output_reg); 3067 3068 if (HAS_PCH_IBX(dev) && 3069 I915_READ(intel_dp->output_reg) & DP_PIPEB_SELECT) { 3070 struct drm_crtc *crtc = intel_dig_port->base.base.crtc; 3071 3072 /* Hardware workaround: leaving our transcoder select 3073 * set to transcoder B while it's off will prevent the 3074 * corresponding HDMI output on transcoder A. 3075 * 3076 * Combine this with another hardware workaround: 3077 * transcoder select bit can only be cleared while the 3078 * port is enabled. 3079 */ 3080 DP &= ~DP_PIPEB_SELECT; 3081 I915_WRITE(intel_dp->output_reg, DP); 3082 3083 /* Changes to enable or select take place the vblank 3084 * after being written. 3085 */ 3086 if (WARN_ON(crtc == NULL)) { 3087 /* We should never try to disable a port without a crtc 3088 * attached. For paranoia keep the code around for a 3089 * bit. */ 3090 POSTING_READ(intel_dp->output_reg); 3091 msleep(50); 3092 } else 3093 intel_wait_for_vblank(dev, intel_crtc->pipe); 3094 } 3095 3096 DP &= ~DP_AUDIO_OUTPUT_ENABLE; 3097 I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN); 3098 POSTING_READ(intel_dp->output_reg); 3099 msleep(intel_dp->panel_power_down_delay); 3100} 3101 3102static bool 3103intel_dp_get_dpcd(struct intel_dp *intel_dp) 3104{ 3105 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 3106 struct drm_device *dev = dig_port->base.base.dev; 3107 struct drm_i915_private *dev_priv = dev->dev_private; 3108 3109 char dpcd_hex_dump[sizeof(intel_dp->dpcd) * 3]; 3110 3111 if (intel_dp_dpcd_read_wake(&intel_dp->aux, 0x000, intel_dp->dpcd, 3112 sizeof(intel_dp->dpcd)) < 0) 3113 return false; /* aux transfer failed */ 3114 3115 hex_dump_to_buffer(intel_dp->dpcd, sizeof(intel_dp->dpcd), 3116 32, 1, dpcd_hex_dump, sizeof(dpcd_hex_dump), false); 3117 DRM_DEBUG_KMS("DPCD: %s\n", dpcd_hex_dump); 3118 3119 if (intel_dp->dpcd[DP_DPCD_REV] == 0) 3120 return false; /* DPCD not present */ 3121 3122 /* Check if the panel supports PSR */ 3123 memset(intel_dp->psr_dpcd, 0, sizeof(intel_dp->psr_dpcd)); 3124 if (is_edp(intel_dp)) { 3125 intel_dp_dpcd_read_wake(&intel_dp->aux, DP_PSR_SUPPORT, 3126 intel_dp->psr_dpcd, 3127 sizeof(intel_dp->psr_dpcd)); 3128 if (intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED) { 3129 dev_priv->psr.sink_support = true; 3130 DRM_DEBUG_KMS("Detected EDP PSR Panel.\n"); 3131 } 3132 } 3133 3134 /* Training Pattern 3 support */ 3135 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x12 && 3136 intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_TPS3_SUPPORTED) { 3137 intel_dp->use_tps3 = true; 3138 DRM_DEBUG_KMS("Displayport TPS3 supported"); 3139 } else 3140 intel_dp->use_tps3 = false; 3141 3142 if (!(intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] & 3143 DP_DWN_STRM_PORT_PRESENT)) 3144 return true; /* native DP sink */ 3145 3146 if (intel_dp->dpcd[DP_DPCD_REV] == 0x10) 3147 return true; /* no per-port downstream info */ 3148 3149 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_DOWNSTREAM_PORT_0, 3150 intel_dp->downstream_ports, 3151 DP_MAX_DOWNSTREAM_PORTS) < 0) 3152 return false; /* downstream port status fetch failed */ 3153 3154 return true; 3155} 3156 3157static void 3158intel_dp_probe_oui(struct intel_dp *intel_dp) 3159{ 3160 u8 buf[3]; 3161 3162 if (!(intel_dp->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT)) 3163 return; 3164 3165 intel_edp_panel_vdd_on(intel_dp); 3166 3167 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_SINK_OUI, buf, 3) == 3) 3168 DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n", 3169 buf[0], buf[1], buf[2]); 3170 3171 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_BRANCH_OUI, buf, 3) == 3) 3172 DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n", 3173 buf[0], buf[1], buf[2]); 3174 3175 edp_panel_vdd_off(intel_dp, false); 3176} 3177 3178int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc) 3179{ 3180 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 3181 struct drm_device *dev = intel_dig_port->base.base.dev; 3182 struct intel_crtc *intel_crtc = 3183 to_intel_crtc(intel_dig_port->base.base.crtc); 3184 u8 buf[1]; 3185 3186 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK_MISC, buf) < 0) 3187 return -EAGAIN; 3188 3189 if (!(buf[0] & DP_TEST_CRC_SUPPORTED)) 3190 return -ENOTTY; 3191 3192 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK, 3193 DP_TEST_SINK_START) < 0) 3194 return -EAGAIN; 3195 3196 /* Wait 2 vblanks to be sure we will have the correct CRC value */ 3197 intel_wait_for_vblank(dev, intel_crtc->pipe); 3198 intel_wait_for_vblank(dev, intel_crtc->pipe); 3199 3200 if (drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_CRC_R_CR, crc, 6) < 0) 3201 return -EAGAIN; 3202 3203 drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK, 0); 3204 return 0; 3205} 3206 3207static bool 3208intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector) 3209{ 3210 return intel_dp_dpcd_read_wake(&intel_dp->aux, 3211 DP_DEVICE_SERVICE_IRQ_VECTOR, 3212 sink_irq_vector, 1) == 1; 3213} 3214 3215static void 3216intel_dp_handle_test_request(struct intel_dp *intel_dp) 3217{ 3218 /* NAK by default */ 3219 drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_RESPONSE, DP_TEST_NAK); 3220} 3221 3222/* 3223 * According to DP spec 3224 * 5.1.2: 3225 * 1. Read DPCD 3226 * 2. Configure link according to Receiver Capabilities 3227 * 3. Use Link Training from 2.5.3.3 and 3.5.1.3 3228 * 4. Check link status on receipt of hot-plug interrupt 3229 */ 3230 3231void 3232intel_dp_check_link_status(struct intel_dp *intel_dp) 3233{ 3234 struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base; 3235 u8 sink_irq_vector; 3236 u8 link_status[DP_LINK_STATUS_SIZE]; 3237 3238 /* FIXME: This access isn't protected by any locks. */ 3239 if (!intel_encoder->connectors_active) 3240 return; 3241 3242 if (WARN_ON(!intel_encoder->base.crtc)) 3243 return; 3244 3245 /* Try to read receiver status if the link appears to be up */ 3246 if (!intel_dp_get_link_status(intel_dp, link_status)) { 3247 return; 3248 } 3249 3250 /* Now read the DPCD to see if it's actually running */ 3251 if (!intel_dp_get_dpcd(intel_dp)) { 3252 return; 3253 } 3254 3255 /* Try to read the source of the interrupt */ 3256 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 && 3257 intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) { 3258 /* Clear interrupt source */ 3259 drm_dp_dpcd_writeb(&intel_dp->aux, 3260 DP_DEVICE_SERVICE_IRQ_VECTOR, 3261 sink_irq_vector); 3262 3263 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST) 3264 intel_dp_handle_test_request(intel_dp); 3265 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ)) 3266 DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n"); 3267 } 3268 3269 if (!drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) { 3270 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n", 3271 intel_encoder->base.name); 3272 intel_dp_start_link_train(intel_dp); 3273 intel_dp_complete_link_train(intel_dp); 3274 intel_dp_stop_link_train(intel_dp); 3275 } 3276} 3277 3278/* XXX this is probably wrong for multiple downstream ports */ 3279static enum drm_connector_status 3280intel_dp_detect_dpcd(struct intel_dp *intel_dp) 3281{ 3282 uint8_t *dpcd = intel_dp->dpcd; 3283 uint8_t type; 3284 3285 if (!intel_dp_get_dpcd(intel_dp)) 3286 return connector_status_disconnected; 3287 3288 /* if there's no downstream port, we're done */ 3289 if (!(dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT)) 3290 return connector_status_connected; 3291 3292 /* If we're HPD-aware, SINK_COUNT changes dynamically */ 3293 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 && 3294 intel_dp->downstream_ports[0] & DP_DS_PORT_HPD) { 3295 uint8_t reg; 3296 3297 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_SINK_COUNT, 3298 ®, 1) < 0) 3299 return connector_status_unknown; 3300 3301 return DP_GET_SINK_COUNT(reg) ? connector_status_connected 3302 : connector_status_disconnected; 3303 } 3304 3305 /* If no HPD, poke DDC gently */ 3306 if (drm_probe_ddc(&intel_dp->aux.ddc)) 3307 return connector_status_connected; 3308 3309 /* Well we tried, say unknown for unreliable port types */ 3310 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) { 3311 type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK; 3312 if (type == DP_DS_PORT_TYPE_VGA || 3313 type == DP_DS_PORT_TYPE_NON_EDID) 3314 return connector_status_unknown; 3315 } else { 3316 type = intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] & 3317 DP_DWN_STRM_PORT_TYPE_MASK; 3318 if (type == DP_DWN_STRM_PORT_TYPE_ANALOG || 3319 type == DP_DWN_STRM_PORT_TYPE_OTHER) 3320 return connector_status_unknown; 3321 } 3322 3323 /* Anything else is out of spec, warn and ignore */ 3324 DRM_DEBUG_KMS("Broken DP branch device, ignoring\n"); 3325 return connector_status_disconnected; 3326} 3327 3328static enum drm_connector_status 3329ironlake_dp_detect(struct intel_dp *intel_dp) 3330{ 3331 struct drm_device *dev = intel_dp_to_dev(intel_dp); 3332 struct drm_i915_private *dev_priv = dev->dev_private; 3333 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 3334 enum drm_connector_status status; 3335 3336 /* Can't disconnect eDP, but you can close the lid... */ 3337 if (is_edp(intel_dp)) { 3338 status = intel_panel_detect(dev); 3339 if (status == connector_status_unknown) 3340 status = connector_status_connected; 3341 return status; 3342 } 3343 3344 if (!ibx_digital_port_connected(dev_priv, intel_dig_port)) 3345 return connector_status_disconnected; 3346 3347 return intel_dp_detect_dpcd(intel_dp); 3348} 3349 3350static enum drm_connector_status 3351g4x_dp_detect(struct intel_dp *intel_dp) 3352{ 3353 struct drm_device *dev = intel_dp_to_dev(intel_dp); 3354 struct drm_i915_private *dev_priv = dev->dev_private; 3355 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 3356 uint32_t bit; 3357 3358 /* Can't disconnect eDP, but you can close the lid... */ 3359 if (is_edp(intel_dp)) { 3360 enum drm_connector_status status; 3361 3362 status = intel_panel_detect(dev); 3363 if (status == connector_status_unknown) 3364 status = connector_status_connected; 3365 return status; 3366 } 3367 3368 if (IS_VALLEYVIEW(dev)) { 3369 switch (intel_dig_port->port) { 3370 case PORT_B: 3371 bit = PORTB_HOTPLUG_LIVE_STATUS_VLV; 3372 break; 3373 case PORT_C: 3374 bit = PORTC_HOTPLUG_LIVE_STATUS_VLV; 3375 break; 3376 case PORT_D: 3377 bit = PORTD_HOTPLUG_LIVE_STATUS_VLV; 3378 break; 3379 default: 3380 return connector_status_unknown; 3381 } 3382 } else { 3383 switch (intel_dig_port->port) { 3384 case PORT_B: 3385 bit = PORTB_HOTPLUG_LIVE_STATUS_G4X; 3386 break; 3387 case PORT_C: 3388 bit = PORTC_HOTPLUG_LIVE_STATUS_G4X; 3389 break; 3390 case PORT_D: 3391 bit = PORTD_HOTPLUG_LIVE_STATUS_G4X; 3392 break; 3393 default: 3394 return connector_status_unknown; 3395 } 3396 } 3397 3398 if ((I915_READ(PORT_HOTPLUG_STAT) & bit) == 0) 3399 return connector_status_disconnected; 3400 3401 return intel_dp_detect_dpcd(intel_dp); 3402} 3403 3404static struct edid * 3405intel_dp_get_edid(struct drm_connector *connector, struct i2c_adapter *adapter) 3406{ 3407 struct intel_connector *intel_connector = to_intel_connector(connector); 3408 3409 /* use cached edid if we have one */ 3410 if (intel_connector->edid) { 3411 /* invalid edid */ 3412 if (IS_ERR(intel_connector->edid)) 3413 return NULL; 3414 3415 return drm_edid_duplicate(intel_connector->edid); 3416 } 3417 3418 return drm_get_edid(connector, adapter); 3419} 3420 3421static int 3422intel_dp_get_edid_modes(struct drm_connector *connector, struct i2c_adapter *adapter) 3423{ 3424 struct intel_connector *intel_connector = to_intel_connector(connector); 3425 3426 /* use cached edid if we have one */ 3427 if (intel_connector->edid) { 3428 /* invalid edid */ 3429 if (IS_ERR(intel_connector->edid)) 3430 return 0; 3431 3432 return intel_connector_update_modes(connector, 3433 intel_connector->edid); 3434 } 3435 3436 return intel_ddc_get_modes(connector, adapter); 3437} 3438 3439static enum drm_connector_status 3440intel_dp_detect(struct drm_connector *connector, bool force) 3441{ 3442 struct intel_dp *intel_dp = intel_attached_dp(connector); 3443 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 3444 struct intel_encoder *intel_encoder = &intel_dig_port->base; 3445 struct drm_device *dev = connector->dev; 3446 struct drm_i915_private *dev_priv = dev->dev_private; 3447 enum drm_connector_status status; 3448 enum intel_display_power_domain power_domain; 3449 struct edid *edid = NULL; 3450 3451 intel_runtime_pm_get(dev_priv); 3452 3453 power_domain = intel_display_port_power_domain(intel_encoder); 3454 intel_display_power_get(dev_priv, power_domain); 3455 3456 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", 3457 connector->base.id, connector->name); 3458 3459 intel_dp->has_audio = false; 3460 3461 if (HAS_PCH_SPLIT(dev)) 3462 status = ironlake_dp_detect(intel_dp); 3463 else 3464 status = g4x_dp_detect(intel_dp); 3465 3466 if (status != connector_status_connected) 3467 goto out; 3468 3469 intel_dp_probe_oui(intel_dp); 3470 3471 if (intel_dp->force_audio != HDMI_AUDIO_AUTO) { 3472 intel_dp->has_audio = (intel_dp->force_audio == HDMI_AUDIO_ON); 3473 } else { 3474 edid = intel_dp_get_edid(connector, &intel_dp->aux.ddc); 3475 if (edid) { 3476 intel_dp->has_audio = drm_detect_monitor_audio(edid); 3477 kfree(edid); 3478 } 3479 } 3480 3481 if (intel_encoder->type != INTEL_OUTPUT_EDP) 3482 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT; 3483 status = connector_status_connected; 3484 3485out: 3486 intel_display_power_put(dev_priv, power_domain); 3487 3488 intel_runtime_pm_put(dev_priv); 3489 3490 return status; 3491} 3492 3493static int intel_dp_get_modes(struct drm_connector *connector) 3494{ 3495 struct intel_dp *intel_dp = intel_attached_dp(connector); 3496 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 3497 struct intel_encoder *intel_encoder = &intel_dig_port->base; 3498 struct intel_connector *intel_connector = to_intel_connector(connector); 3499 struct drm_device *dev = connector->dev; 3500 struct drm_i915_private *dev_priv = dev->dev_private; 3501 enum intel_display_power_domain power_domain; 3502 int ret; 3503 3504 /* We should parse the EDID data and find out if it has an audio sink 3505 */ 3506 3507 power_domain = intel_display_port_power_domain(intel_encoder); 3508 intel_display_power_get(dev_priv, power_domain); 3509 3510 ret = intel_dp_get_edid_modes(connector, &intel_dp->aux.ddc); 3511 intel_display_power_put(dev_priv, power_domain); 3512 if (ret) 3513 return ret; 3514 3515 /* if eDP has no EDID, fall back to fixed mode */ 3516 if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) { 3517 struct drm_display_mode *mode; 3518 mode = drm_mode_duplicate(dev, 3519 intel_connector->panel.fixed_mode); 3520 if (mode) { 3521 drm_mode_probed_add(connector, mode); 3522 return 1; 3523 } 3524 } 3525 return 0; 3526} 3527 3528static bool 3529intel_dp_detect_audio(struct drm_connector *connector) 3530{ 3531 struct intel_dp *intel_dp = intel_attached_dp(connector); 3532 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 3533 struct intel_encoder *intel_encoder = &intel_dig_port->base; 3534 struct drm_device *dev = connector->dev; 3535 struct drm_i915_private *dev_priv = dev->dev_private; 3536 enum intel_display_power_domain power_domain; 3537 struct edid *edid; 3538 bool has_audio = false; 3539 3540 power_domain = intel_display_port_power_domain(intel_encoder); 3541 intel_display_power_get(dev_priv, power_domain); 3542 3543 edid = intel_dp_get_edid(connector, &intel_dp->aux.ddc); 3544 if (edid) { 3545 has_audio = drm_detect_monitor_audio(edid); 3546 kfree(edid); 3547 } 3548 3549 intel_display_power_put(dev_priv, power_domain); 3550 3551 return has_audio; 3552} 3553 3554static int 3555intel_dp_set_property(struct drm_connector *connector, 3556 struct drm_property *property, 3557 uint64_t val) 3558{ 3559 struct drm_i915_private *dev_priv = connector->dev->dev_private; 3560 struct intel_connector *intel_connector = to_intel_connector(connector); 3561 struct intel_encoder *intel_encoder = intel_attached_encoder(connector); 3562 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base); 3563 int ret; 3564 3565 ret = drm_object_property_set_value(&connector->base, property, val); 3566 if (ret) 3567 return ret; 3568 3569 if (property == dev_priv->force_audio_property) { 3570 int i = val; 3571 bool has_audio; 3572 3573 if (i == intel_dp->force_audio) 3574 return 0; 3575 3576 intel_dp->force_audio = i; 3577 3578 if (i == HDMI_AUDIO_AUTO) 3579 has_audio = intel_dp_detect_audio(connector); 3580 else 3581 has_audio = (i == HDMI_AUDIO_ON); 3582 3583 if (has_audio == intel_dp->has_audio) 3584 return 0; 3585 3586 intel_dp->has_audio = has_audio; 3587 goto done; 3588 } 3589 3590 if (property == dev_priv->broadcast_rgb_property) { 3591 bool old_auto = intel_dp->color_range_auto; 3592 uint32_t old_range = intel_dp->color_range; 3593 3594 switch (val) { 3595 case INTEL_BROADCAST_RGB_AUTO: 3596 intel_dp->color_range_auto = true; 3597 break; 3598 case INTEL_BROADCAST_RGB_FULL: 3599 intel_dp->color_range_auto = false; 3600 intel_dp->color_range = 0; 3601 break; 3602 case INTEL_BROADCAST_RGB_LIMITED: 3603 intel_dp->color_range_auto = false; 3604 intel_dp->color_range = DP_COLOR_RANGE_16_235; 3605 break; 3606 default: 3607 return -EINVAL; 3608 } 3609 3610 if (old_auto == intel_dp->color_range_auto && 3611 old_range == intel_dp->color_range) 3612 return 0; 3613 3614 goto done; 3615 } 3616 3617 if (is_edp(intel_dp) && 3618 property == connector->dev->mode_config.scaling_mode_property) { 3619 if (val == DRM_MODE_SCALE_NONE) { 3620 DRM_DEBUG_KMS("no scaling not supported\n"); 3621 return -EINVAL; 3622 } 3623 3624 if (intel_connector->panel.fitting_mode == val) { 3625 /* the eDP scaling property is not changed */ 3626 return 0; 3627 } 3628 intel_connector->panel.fitting_mode = val; 3629 3630 goto done; 3631 } 3632 3633 return -EINVAL; 3634 3635done: 3636 if (intel_encoder->base.crtc) 3637 intel_crtc_restore_mode(intel_encoder->base.crtc); 3638 3639 return 0; 3640} 3641 3642static void 3643intel_dp_connector_destroy(struct drm_connector *connector) 3644{ 3645 struct intel_connector *intel_connector = to_intel_connector(connector); 3646 3647 if (!IS_ERR_OR_NULL(intel_connector->edid)) 3648 kfree(intel_connector->edid); 3649 3650 /* Can't call is_edp() since the encoder may have been destroyed 3651 * already. */ 3652 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) 3653 intel_panel_fini(&intel_connector->panel); 3654 3655 drm_connector_cleanup(connector); 3656 kfree(connector); 3657} 3658 3659void intel_dp_encoder_destroy(struct drm_encoder *encoder) 3660{ 3661 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); 3662 struct intel_dp *intel_dp = &intel_dig_port->dp; 3663 struct drm_device *dev = intel_dp_to_dev(intel_dp); 3664 3665 drm_dp_aux_unregister_i2c_bus(&intel_dp->aux); 3666 drm_encoder_cleanup(encoder); 3667 if (is_edp(intel_dp)) { 3668 cancel_delayed_work_sync(&intel_dp->panel_vdd_work); 3669 mutex_lock(&dev->mode_config.connection_mutex); 3670 edp_panel_vdd_off_sync(intel_dp); 3671 mutex_unlock(&dev->mode_config.connection_mutex); 3672 } 3673 kfree(intel_dig_port); 3674} 3675 3676static const struct drm_connector_funcs intel_dp_connector_funcs = { 3677 .dpms = intel_connector_dpms, 3678 .detect = intel_dp_detect, 3679 .fill_modes = drm_helper_probe_single_connector_modes, 3680 .set_property = intel_dp_set_property, 3681 .destroy = intel_dp_connector_destroy, 3682}; 3683 3684static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = { 3685 .get_modes = intel_dp_get_modes, 3686 .mode_valid = intel_dp_mode_valid, 3687 .best_encoder = intel_best_encoder, 3688}; 3689 3690static const struct drm_encoder_funcs intel_dp_enc_funcs = { 3691 .destroy = intel_dp_encoder_destroy, 3692}; 3693 3694static void 3695intel_dp_hot_plug(struct intel_encoder *intel_encoder) 3696{ 3697 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base); 3698 3699 intel_dp_check_link_status(intel_dp); 3700} 3701 3702/* Return which DP Port should be selected for Transcoder DP control */ 3703int 3704intel_trans_dp_port_sel(struct drm_crtc *crtc) 3705{ 3706 struct drm_device *dev = crtc->dev; 3707 struct intel_encoder *intel_encoder; 3708 struct intel_dp *intel_dp; 3709 3710 for_each_encoder_on_crtc(dev, crtc, intel_encoder) { 3711 intel_dp = enc_to_intel_dp(&intel_encoder->base); 3712 3713 if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT || 3714 intel_encoder->type == INTEL_OUTPUT_EDP) 3715 return intel_dp->output_reg; 3716 } 3717 3718 return -1; 3719} 3720 3721/* check the VBT to see whether the eDP is on DP-D port */ 3722bool intel_dp_is_edp(struct drm_device *dev, enum port port) 3723{ 3724 struct drm_i915_private *dev_priv = dev->dev_private; 3725 union child_device_config *p_child; 3726 int i; 3727 static const short port_mapping[] = { 3728 [PORT_B] = PORT_IDPB, 3729 [PORT_C] = PORT_IDPC, 3730 [PORT_D] = PORT_IDPD, 3731 }; 3732 3733 if (port == PORT_A) 3734 return true; 3735 3736 if (!dev_priv->vbt.child_dev_num) 3737 return false; 3738 3739 for (i = 0; i < dev_priv->vbt.child_dev_num; i++) { 3740 p_child = dev_priv->vbt.child_dev + i; 3741 3742 if (p_child->common.dvo_port == port_mapping[port] && 3743 (p_child->common.device_type & DEVICE_TYPE_eDP_BITS) == 3744 (DEVICE_TYPE_eDP & DEVICE_TYPE_eDP_BITS)) 3745 return true; 3746 } 3747 return false; 3748} 3749 3750static void 3751intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector) 3752{ 3753 struct intel_connector *intel_connector = to_intel_connector(connector); 3754 3755 intel_attach_force_audio_property(connector); 3756 intel_attach_broadcast_rgb_property(connector); 3757 intel_dp->color_range_auto = true; 3758 3759 if (is_edp(intel_dp)) { 3760 drm_mode_create_scaling_mode_property(connector->dev); 3761 drm_object_attach_property( 3762 &connector->base, 3763 connector->dev->mode_config.scaling_mode_property, 3764 DRM_MODE_SCALE_ASPECT); 3765 intel_connector->panel.fitting_mode = DRM_MODE_SCALE_ASPECT; 3766 } 3767} 3768 3769static void intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp) 3770{ 3771 intel_dp->last_power_cycle = jiffies; 3772 intel_dp->last_power_on = jiffies; 3773 intel_dp->last_backlight_off = jiffies; 3774} 3775 3776static void 3777intel_dp_init_panel_power_sequencer(struct drm_device *dev, 3778 struct intel_dp *intel_dp, 3779 struct edp_power_seq *out) 3780{ 3781 struct drm_i915_private *dev_priv = dev->dev_private; 3782 struct edp_power_seq cur, vbt, spec, final; 3783 u32 pp_on, pp_off, pp_div, pp; 3784 int pp_ctrl_reg, pp_on_reg, pp_off_reg, pp_div_reg; 3785 3786 if (HAS_PCH_SPLIT(dev)) { 3787 pp_ctrl_reg = PCH_PP_CONTROL; 3788 pp_on_reg = PCH_PP_ON_DELAYS; 3789 pp_off_reg = PCH_PP_OFF_DELAYS; 3790 pp_div_reg = PCH_PP_DIVISOR; 3791 } else { 3792 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp); 3793 3794 pp_ctrl_reg = VLV_PIPE_PP_CONTROL(pipe); 3795 pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe); 3796 pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe); 3797 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe); 3798 } 3799 3800 /* Workaround: Need to write PP_CONTROL with the unlock key as 3801 * the very first thing. */ 3802 pp = ironlake_get_pp_control(intel_dp); 3803 I915_WRITE(pp_ctrl_reg, pp); 3804 3805 pp_on = I915_READ(pp_on_reg); 3806 pp_off = I915_READ(pp_off_reg); 3807 pp_div = I915_READ(pp_div_reg); 3808 3809 /* Pull timing values out of registers */ 3810 cur.t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >> 3811 PANEL_POWER_UP_DELAY_SHIFT; 3812 3813 cur.t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >> 3814 PANEL_LIGHT_ON_DELAY_SHIFT; 3815 3816 cur.t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >> 3817 PANEL_LIGHT_OFF_DELAY_SHIFT; 3818 3819 cur.t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >> 3820 PANEL_POWER_DOWN_DELAY_SHIFT; 3821 3822 cur.t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >> 3823 PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000; 3824 3825 DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n", 3826 cur.t1_t3, cur.t8, cur.t9, cur.t10, cur.t11_t12); 3827 3828 vbt = dev_priv->vbt.edp_pps; 3829 3830 /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of 3831 * our hw here, which are all in 100usec. */ 3832 spec.t1_t3 = 210 * 10; 3833 spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */ 3834 spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */ 3835 spec.t10 = 500 * 10; 3836 /* This one is special and actually in units of 100ms, but zero 3837 * based in the hw (so we need to add 100 ms). But the sw vbt 3838 * table multiplies it with 1000 to make it in units of 100usec, 3839 * too. */ 3840 spec.t11_t12 = (510 + 100) * 10; 3841 3842 DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n", 3843 vbt.t1_t3, vbt.t8, vbt.t9, vbt.t10, vbt.t11_t12); 3844 3845 /* Use the max of the register settings and vbt. If both are 3846 * unset, fall back to the spec limits. */ 3847#define assign_final(field) final.field = (max(cur.field, vbt.field) == 0 ? \ 3848 spec.field : \ 3849 max(cur.field, vbt.field)) 3850 assign_final(t1_t3); 3851 assign_final(t8); 3852 assign_final(t9); 3853 assign_final(t10); 3854 assign_final(t11_t12); 3855#undef assign_final 3856 3857#define get_delay(field) (DIV_ROUND_UP(final.field, 10)) 3858 intel_dp->panel_power_up_delay = get_delay(t1_t3); 3859 intel_dp->backlight_on_delay = get_delay(t8); 3860 intel_dp->backlight_off_delay = get_delay(t9); 3861 intel_dp->panel_power_down_delay = get_delay(t10); 3862 intel_dp->panel_power_cycle_delay = get_delay(t11_t12); 3863#undef get_delay 3864 3865 DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n", 3866 intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay, 3867 intel_dp->panel_power_cycle_delay); 3868 3869 DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n", 3870 intel_dp->backlight_on_delay, intel_dp->backlight_off_delay); 3871 3872 if (out) 3873 *out = final; 3874} 3875 3876static void 3877intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev, 3878 struct intel_dp *intel_dp, 3879 struct edp_power_seq *seq) 3880{ 3881 struct drm_i915_private *dev_priv = dev->dev_private; 3882 u32 pp_on, pp_off, pp_div, port_sel = 0; 3883 int div = HAS_PCH_SPLIT(dev) ? intel_pch_rawclk(dev) : intel_hrawclk(dev); 3884 int pp_on_reg, pp_off_reg, pp_div_reg; 3885 3886 if (HAS_PCH_SPLIT(dev)) { 3887 pp_on_reg = PCH_PP_ON_DELAYS; 3888 pp_off_reg = PCH_PP_OFF_DELAYS; 3889 pp_div_reg = PCH_PP_DIVISOR; 3890 } else { 3891 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp); 3892 3893 pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe); 3894 pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe); 3895 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe); 3896 } 3897 3898 /* 3899 * And finally store the new values in the power sequencer. The 3900 * backlight delays are set to 1 because we do manual waits on them. For 3901 * T8, even BSpec recommends doing it. For T9, if we don't do this, 3902 * we'll end up waiting for the backlight off delay twice: once when we 3903 * do the manual sleep, and once when we disable the panel and wait for 3904 * the PP_STATUS bit to become zero. 3905 */ 3906 pp_on = (seq->t1_t3 << PANEL_POWER_UP_DELAY_SHIFT) | 3907 (1 << PANEL_LIGHT_ON_DELAY_SHIFT); 3908 pp_off = (1 << PANEL_LIGHT_OFF_DELAY_SHIFT) | 3909 (seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT); 3910 /* Compute the divisor for the pp clock, simply match the Bspec 3911 * formula. */ 3912 pp_div = ((100 * div)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT; 3913 pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000) 3914 << PANEL_POWER_CYCLE_DELAY_SHIFT); 3915 3916 /* Haswell doesn't have any port selection bits for the panel 3917 * power sequencer any more. */ 3918 if (IS_VALLEYVIEW(dev)) { 3919 if (dp_to_dig_port(intel_dp)->port == PORT_B) 3920 port_sel = PANEL_PORT_SELECT_DPB_VLV; 3921 else 3922 port_sel = PANEL_PORT_SELECT_DPC_VLV; 3923 } else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) { 3924 if (dp_to_dig_port(intel_dp)->port == PORT_A) 3925 port_sel = PANEL_PORT_SELECT_DPA; 3926 else 3927 port_sel = PANEL_PORT_SELECT_DPD; 3928 } 3929 3930 pp_on |= port_sel; 3931 3932 I915_WRITE(pp_on_reg, pp_on); 3933 I915_WRITE(pp_off_reg, pp_off); 3934 I915_WRITE(pp_div_reg, pp_div); 3935 3936 DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n", 3937 I915_READ(pp_on_reg), 3938 I915_READ(pp_off_reg), 3939 I915_READ(pp_div_reg)); 3940} 3941 3942void intel_dp_set_drrs_state(struct drm_device *dev, int refresh_rate) 3943{ 3944 struct drm_i915_private *dev_priv = dev->dev_private; 3945 struct intel_encoder *encoder; 3946 struct intel_dp *intel_dp = NULL; 3947 struct intel_crtc_config *config = NULL; 3948 struct intel_crtc *intel_crtc = NULL; 3949 struct intel_connector *intel_connector = dev_priv->drrs.connector; 3950 u32 reg, val; 3951 enum edp_drrs_refresh_rate_type index = DRRS_HIGH_RR; 3952 3953 if (refresh_rate <= 0) { 3954 DRM_DEBUG_KMS("Refresh rate should be positive non-zero.\n"); 3955 return; 3956 } 3957 3958 if (intel_connector == NULL) { 3959 DRM_DEBUG_KMS("DRRS supported for eDP only.\n"); 3960 return; 3961 } 3962 3963 if (INTEL_INFO(dev)->gen < 8 && intel_edp_is_psr_enabled(dev)) { 3964 DRM_DEBUG_KMS("DRRS is disabled as PSR is enabled\n"); 3965 return; 3966 } 3967 3968 encoder = intel_attached_encoder(&intel_connector->base); 3969 intel_dp = enc_to_intel_dp(&encoder->base); 3970 intel_crtc = encoder->new_crtc; 3971 3972 if (!intel_crtc) { 3973 DRM_DEBUG_KMS("DRRS: intel_crtc not initialized\n"); 3974 return; 3975 } 3976 3977 config = &intel_crtc->config; 3978 3979 if (intel_dp->drrs_state.type < SEAMLESS_DRRS_SUPPORT) { 3980 DRM_DEBUG_KMS("Only Seamless DRRS supported.\n"); 3981 return; 3982 } 3983 3984 if (intel_connector->panel.downclock_mode->vrefresh == refresh_rate) 3985 index = DRRS_LOW_RR; 3986 3987 if (index == intel_dp->drrs_state.refresh_rate_type) { 3988 DRM_DEBUG_KMS( 3989 "DRRS requested for previously set RR...ignoring\n"); 3990 return; 3991 } 3992 3993 if (!intel_crtc->active) { 3994 DRM_DEBUG_KMS("eDP encoder disabled. CRTC not Active\n"); 3995 return; 3996 } 3997 3998 if (INTEL_INFO(dev)->gen > 6 && INTEL_INFO(dev)->gen < 8) { 3999 reg = PIPECONF(intel_crtc->config.cpu_transcoder); 4000 val = I915_READ(reg); 4001 if (index > DRRS_HIGH_RR) { 4002 val |= PIPECONF_EDP_RR_MODE_SWITCH; 4003 intel_dp_set_m2_n2(intel_crtc, &config->dp_m2_n2); 4004 } else { 4005 val &= ~PIPECONF_EDP_RR_MODE_SWITCH; 4006 } 4007 I915_WRITE(reg, val); 4008 } 4009 4010 /* 4011 * mutex taken to ensure that there is no race between differnt 4012 * drrs calls trying to update refresh rate. This scenario may occur 4013 * in future when idleness detection based DRRS in kernel and 4014 * possible calls from user space to set differnt RR are made. 4015 */ 4016 4017 mutex_lock(&intel_dp->drrs_state.mutex); 4018 4019 intel_dp->drrs_state.refresh_rate_type = index; 4020 4021 mutex_unlock(&intel_dp->drrs_state.mutex); 4022 4023 DRM_DEBUG_KMS("eDP Refresh Rate set to : %dHz\n", refresh_rate); 4024} 4025 4026static struct drm_display_mode * 4027intel_dp_drrs_init(struct intel_digital_port *intel_dig_port, 4028 struct intel_connector *intel_connector, 4029 struct drm_display_mode *fixed_mode) 4030{ 4031 struct drm_connector *connector = &intel_connector->base; 4032 struct intel_dp *intel_dp = &intel_dig_port->dp; 4033 struct drm_device *dev = intel_dig_port->base.base.dev; 4034 struct drm_i915_private *dev_priv = dev->dev_private; 4035 struct drm_display_mode *downclock_mode = NULL; 4036 4037 if (INTEL_INFO(dev)->gen <= 6) { 4038 DRM_DEBUG_KMS("DRRS supported for Gen7 and above\n"); 4039 return NULL; 4040 } 4041 4042 if (dev_priv->vbt.drrs_type != SEAMLESS_DRRS_SUPPORT) { 4043 DRM_INFO("VBT doesn't support DRRS\n"); 4044 return NULL; 4045 } 4046 4047 downclock_mode = intel_find_panel_downclock 4048 (dev, fixed_mode, connector); 4049 4050 if (!downclock_mode) { 4051 DRM_INFO("DRRS not supported\n"); 4052 return NULL; 4053 } 4054 4055 dev_priv->drrs.connector = intel_connector; 4056 4057 mutex_init(&intel_dp->drrs_state.mutex); 4058 4059 intel_dp->drrs_state.type = dev_priv->vbt.drrs_type; 4060 4061 intel_dp->drrs_state.refresh_rate_type = DRRS_HIGH_RR; 4062 DRM_INFO("seamless DRRS supported for eDP panel.\n"); 4063 return downclock_mode; 4064} 4065 4066static bool intel_edp_init_connector(struct intel_dp *intel_dp, 4067 struct intel_connector *intel_connector, 4068 struct edp_power_seq *power_seq) 4069{ 4070 struct drm_connector *connector = &intel_connector->base; 4071 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 4072 struct intel_encoder *intel_encoder = &intel_dig_port->base; 4073 struct drm_device *dev = intel_encoder->base.dev; 4074 struct drm_i915_private *dev_priv = dev->dev_private; 4075 struct drm_display_mode *fixed_mode = NULL; 4076 struct drm_display_mode *downclock_mode = NULL; 4077 bool has_dpcd; 4078 struct drm_display_mode *scan; 4079 struct edid *edid; 4080 4081 intel_dp->drrs_state.type = DRRS_NOT_SUPPORTED; 4082 4083 if (!is_edp(intel_dp)) 4084 return true; 4085 4086 /* The VDD bit needs a power domain reference, so if the bit is already 4087 * enabled when we boot, grab this reference. */ 4088 if (edp_have_panel_vdd(intel_dp)) { 4089 enum intel_display_power_domain power_domain; 4090 power_domain = intel_display_port_power_domain(intel_encoder); 4091 intel_display_power_get(dev_priv, power_domain); 4092 } 4093 4094 /* Cache DPCD and EDID for edp. */ 4095 intel_edp_panel_vdd_on(intel_dp); 4096 has_dpcd = intel_dp_get_dpcd(intel_dp); 4097 edp_panel_vdd_off(intel_dp, false); 4098 4099 if (has_dpcd) { 4100 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) 4101 dev_priv->no_aux_handshake = 4102 intel_dp->dpcd[DP_MAX_DOWNSPREAD] & 4103 DP_NO_AUX_HANDSHAKE_LINK_TRAINING; 4104 } else { 4105 /* if this fails, presume the device is a ghost */ 4106 DRM_INFO("failed to retrieve link info, disabling eDP\n"); 4107 return false; 4108 } 4109 4110 /* We now know it's not a ghost, init power sequence regs. */ 4111 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp, power_seq); 4112 4113 mutex_lock(&dev->mode_config.mutex); 4114 edid = drm_get_edid(connector, &intel_dp->aux.ddc); 4115 if (edid) { 4116 if (drm_add_edid_modes(connector, edid)) { 4117 drm_mode_connector_update_edid_property(connector, 4118 edid); 4119 drm_edid_to_eld(connector, edid); 4120 } else { 4121 kfree(edid); 4122 edid = ERR_PTR(-EINVAL); 4123 } 4124 } else { 4125 edid = ERR_PTR(-ENOENT); 4126 } 4127 intel_connector->edid = edid; 4128 4129 /* prefer fixed mode from EDID if available */ 4130 list_for_each_entry(scan, &connector->probed_modes, head) { 4131 if ((scan->type & DRM_MODE_TYPE_PREFERRED)) { 4132 fixed_mode = drm_mode_duplicate(dev, scan); 4133 downclock_mode = intel_dp_drrs_init( 4134 intel_dig_port, 4135 intel_connector, fixed_mode); 4136 break; 4137 } 4138 } 4139 4140 /* fallback to VBT if available for eDP */ 4141 if (!fixed_mode && dev_priv->vbt.lfp_lvds_vbt_mode) { 4142 fixed_mode = drm_mode_duplicate(dev, 4143 dev_priv->vbt.lfp_lvds_vbt_mode); 4144 if (fixed_mode) 4145 fixed_mode->type |= DRM_MODE_TYPE_PREFERRED; 4146 } 4147 mutex_unlock(&dev->mode_config.mutex); 4148 4149 intel_panel_init(&intel_connector->panel, fixed_mode, downclock_mode); 4150 intel_panel_setup_backlight(connector); 4151 4152 return true; 4153} 4154 4155bool 4156intel_dp_init_connector(struct intel_digital_port *intel_dig_port, 4157 struct intel_connector *intel_connector) 4158{ 4159 struct drm_connector *connector = &intel_connector->base; 4160 struct intel_dp *intel_dp = &intel_dig_port->dp; 4161 struct intel_encoder *intel_encoder = &intel_dig_port->base; 4162 struct drm_device *dev = intel_encoder->base.dev; 4163 struct drm_i915_private *dev_priv = dev->dev_private; 4164 enum port port = intel_dig_port->port; 4165 struct edp_power_seq power_seq = { 0 }; 4166 int type; 4167 4168 /* intel_dp vfuncs */ 4169 if (IS_VALLEYVIEW(dev)) 4170 intel_dp->get_aux_clock_divider = vlv_get_aux_clock_divider; 4171 else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) 4172 intel_dp->get_aux_clock_divider = hsw_get_aux_clock_divider; 4173 else if (HAS_PCH_SPLIT(dev)) 4174 intel_dp->get_aux_clock_divider = ilk_get_aux_clock_divider; 4175 else 4176 intel_dp->get_aux_clock_divider = i9xx_get_aux_clock_divider; 4177 4178 intel_dp->get_aux_send_ctl = i9xx_get_aux_send_ctl; 4179 4180 /* Preserve the current hw state. */ 4181 intel_dp->DP = I915_READ(intel_dp->output_reg); 4182 intel_dp->attached_connector = intel_connector; 4183 4184 if (intel_dp_is_edp(dev, port)) 4185 type = DRM_MODE_CONNECTOR_eDP; 4186 else 4187 type = DRM_MODE_CONNECTOR_DisplayPort; 4188 4189 /* 4190 * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but 4191 * for DP the encoder type can be set by the caller to 4192 * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it. 4193 */ 4194 if (type == DRM_MODE_CONNECTOR_eDP) 4195 intel_encoder->type = INTEL_OUTPUT_EDP; 4196 4197 DRM_DEBUG_KMS("Adding %s connector on port %c\n", 4198 type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP", 4199 port_name(port)); 4200 4201 drm_connector_init(dev, connector, &intel_dp_connector_funcs, type); 4202 drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs); 4203 4204 connector->interlace_allowed = true; 4205 connector->doublescan_allowed = 0; 4206 4207 INIT_DELAYED_WORK(&intel_dp->panel_vdd_work, 4208 edp_panel_vdd_work); 4209 4210 intel_connector_attach_encoder(intel_connector, intel_encoder); 4211 drm_sysfs_connector_add(connector); 4212 4213 if (HAS_DDI(dev)) 4214 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state; 4215 else 4216 intel_connector->get_hw_state = intel_connector_get_hw_state; 4217 intel_connector->unregister = intel_dp_connector_unregister; 4218 4219 /* Set up the hotplug pin. */ 4220 switch (port) { 4221 case PORT_A: 4222 intel_encoder->hpd_pin = HPD_PORT_A; 4223 break; 4224 case PORT_B: 4225 intel_encoder->hpd_pin = HPD_PORT_B; 4226 break; 4227 case PORT_C: 4228 intel_encoder->hpd_pin = HPD_PORT_C; 4229 break; 4230 case PORT_D: 4231 intel_encoder->hpd_pin = HPD_PORT_D; 4232 break; 4233 default: 4234 BUG(); 4235 } 4236 4237 if (is_edp(intel_dp)) { 4238 intel_dp_init_panel_power_timestamps(intel_dp); 4239 intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq); 4240 } 4241 4242 intel_dp_aux_init(intel_dp, intel_connector); 4243 4244 intel_dp->psr_setup_done = false; 4245 4246 if (!intel_edp_init_connector(intel_dp, intel_connector, &power_seq)) { 4247 drm_dp_aux_unregister_i2c_bus(&intel_dp->aux); 4248 if (is_edp(intel_dp)) { 4249 cancel_delayed_work_sync(&intel_dp->panel_vdd_work); 4250 mutex_lock(&dev->mode_config.connection_mutex); 4251 edp_panel_vdd_off_sync(intel_dp); 4252 mutex_unlock(&dev->mode_config.connection_mutex); 4253 } 4254 drm_sysfs_connector_remove(connector); 4255 drm_connector_cleanup(connector); 4256 return false; 4257 } 4258 4259 intel_dp_add_properties(intel_dp, connector); 4260 4261 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written 4262 * 0xd. Failure to do so will result in spurious interrupts being 4263 * generated on the port when a cable is not attached. 4264 */ 4265 if (IS_G4X(dev) && !IS_GM45(dev)) { 4266 u32 temp = I915_READ(PEG_BAND_GAP_DATA); 4267 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd); 4268 } 4269 4270 return true; 4271} 4272 4273void 4274intel_dp_init(struct drm_device *dev, int output_reg, enum port port) 4275{ 4276 struct intel_digital_port *intel_dig_port; 4277 struct intel_encoder *intel_encoder; 4278 struct drm_encoder *encoder; 4279 struct intel_connector *intel_connector; 4280 4281 intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL); 4282 if (!intel_dig_port) 4283 return; 4284 4285 intel_connector = kzalloc(sizeof(*intel_connector), GFP_KERNEL); 4286 if (!intel_connector) { 4287 kfree(intel_dig_port); 4288 return; 4289 } 4290 4291 intel_encoder = &intel_dig_port->base; 4292 encoder = &intel_encoder->base; 4293 4294 drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs, 4295 DRM_MODE_ENCODER_TMDS); 4296 4297 intel_encoder->compute_config = intel_dp_compute_config; 4298 intel_encoder->disable = intel_disable_dp; 4299 intel_encoder->get_hw_state = intel_dp_get_hw_state; 4300 intel_encoder->get_config = intel_dp_get_config; 4301 if (IS_CHERRYVIEW(dev)) { 4302 intel_encoder->pre_enable = chv_pre_enable_dp; 4303 intel_encoder->enable = vlv_enable_dp; 4304 intel_encoder->post_disable = chv_post_disable_dp; 4305 } else if (IS_VALLEYVIEW(dev)) { 4306 intel_encoder->pre_pll_enable = vlv_dp_pre_pll_enable; 4307 intel_encoder->pre_enable = vlv_pre_enable_dp; 4308 intel_encoder->enable = vlv_enable_dp; 4309 intel_encoder->post_disable = vlv_post_disable_dp; 4310 } else { 4311 intel_encoder->pre_enable = g4x_pre_enable_dp; 4312 intel_encoder->enable = g4x_enable_dp; 4313 intel_encoder->post_disable = g4x_post_disable_dp; 4314 } 4315 4316 intel_dig_port->port = port; 4317 intel_dig_port->dp.output_reg = output_reg; 4318 4319 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT; 4320 if (IS_CHERRYVIEW(dev)) { 4321 if (port == PORT_D) 4322 intel_encoder->crtc_mask = 1 << 2; 4323 else 4324 intel_encoder->crtc_mask = (1 << 0) | (1 << 1); 4325 } else { 4326 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2); 4327 } 4328 intel_encoder->cloneable = 0; 4329 intel_encoder->hot_plug = intel_dp_hot_plug; 4330 4331 if (!intel_dp_init_connector(intel_dig_port, intel_connector)) { 4332 drm_encoder_cleanup(encoder); 4333 kfree(intel_dig_port); 4334 kfree(intel_connector); 4335 } 4336} 4337