intel_dp.c revision 752aa88a1e784c22d514db3b440e49427b58259e
1/* 2 * Copyright © 2008 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 * Authors: 24 * Keith Packard <keithp@keithp.com> 25 * 26 */ 27 28#include <linux/i2c.h> 29#include <linux/slab.h> 30#include <linux/export.h> 31#include <drm/drmP.h> 32#include <drm/drm_crtc.h> 33#include <drm/drm_crtc_helper.h> 34#include <drm/drm_edid.h> 35#include "intel_drv.h" 36#include <drm/i915_drm.h> 37#include "i915_drv.h" 38 39#define DP_LINK_CHECK_TIMEOUT (10 * 1000) 40 41struct dp_link_dpll { 42 int link_bw; 43 struct dpll dpll; 44}; 45 46static const struct dp_link_dpll gen4_dpll[] = { 47 { DP_LINK_BW_1_62, 48 { .p1 = 2, .p2 = 10, .n = 2, .m1 = 23, .m2 = 8 } }, 49 { DP_LINK_BW_2_7, 50 { .p1 = 1, .p2 = 10, .n = 1, .m1 = 14, .m2 = 2 } } 51}; 52 53static const struct dp_link_dpll pch_dpll[] = { 54 { DP_LINK_BW_1_62, 55 { .p1 = 2, .p2 = 10, .n = 1, .m1 = 12, .m2 = 9 } }, 56 { DP_LINK_BW_2_7, 57 { .p1 = 1, .p2 = 10, .n = 2, .m1 = 14, .m2 = 8 } } 58}; 59 60static const struct dp_link_dpll vlv_dpll[] = { 61 { DP_LINK_BW_1_62, 62 { .p1 = 3, .p2 = 2, .n = 5, .m1 = 3, .m2 = 81 } }, 63 { DP_LINK_BW_2_7, 64 { .p1 = 2, .p2 = 2, .n = 1, .m1 = 2, .m2 = 27 } } 65}; 66 67/** 68 * is_edp - is the given port attached to an eDP panel (either CPU or PCH) 69 * @intel_dp: DP struct 70 * 71 * If a CPU or PCH DP output is attached to an eDP panel, this function 72 * will return true, and false otherwise. 73 */ 74static bool is_edp(struct intel_dp *intel_dp) 75{ 76 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 77 78 return intel_dig_port->base.type == INTEL_OUTPUT_EDP; 79} 80 81static struct drm_device *intel_dp_to_dev(struct intel_dp *intel_dp) 82{ 83 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 84 85 return intel_dig_port->base.base.dev; 86} 87 88static struct intel_dp *intel_attached_dp(struct drm_connector *connector) 89{ 90 return enc_to_intel_dp(&intel_attached_encoder(connector)->base); 91} 92 93static void intel_dp_link_down(struct intel_dp *intel_dp); 94 95static int 96intel_dp_max_link_bw(struct intel_dp *intel_dp) 97{ 98 int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE]; 99 100 switch (max_link_bw) { 101 case DP_LINK_BW_1_62: 102 case DP_LINK_BW_2_7: 103 break; 104 case DP_LINK_BW_5_4: /* 1.2 capable displays may advertise higher bw */ 105 max_link_bw = DP_LINK_BW_2_7; 106 break; 107 default: 108 WARN(1, "invalid max DP link bw val %x, using 1.62Gbps\n", 109 max_link_bw); 110 max_link_bw = DP_LINK_BW_1_62; 111 break; 112 } 113 return max_link_bw; 114} 115 116/* 117 * The units on the numbers in the next two are... bizarre. Examples will 118 * make it clearer; this one parallels an example in the eDP spec. 119 * 120 * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as: 121 * 122 * 270000 * 1 * 8 / 10 == 216000 123 * 124 * The actual data capacity of that configuration is 2.16Gbit/s, so the 125 * units are decakilobits. ->clock in a drm_display_mode is in kilohertz - 126 * or equivalently, kilopixels per second - so for 1680x1050R it'd be 127 * 119000. At 18bpp that's 2142000 kilobits per second. 128 * 129 * Thus the strange-looking division by 10 in intel_dp_link_required, to 130 * get the result in decakilobits instead of kilobits. 131 */ 132 133static int 134intel_dp_link_required(int pixel_clock, int bpp) 135{ 136 return (pixel_clock * bpp + 9) / 10; 137} 138 139static int 140intel_dp_max_data_rate(int max_link_clock, int max_lanes) 141{ 142 return (max_link_clock * max_lanes * 8) / 10; 143} 144 145static int 146intel_dp_mode_valid(struct drm_connector *connector, 147 struct drm_display_mode *mode) 148{ 149 struct intel_dp *intel_dp = intel_attached_dp(connector); 150 struct intel_connector *intel_connector = to_intel_connector(connector); 151 struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode; 152 int target_clock = mode->clock; 153 int max_rate, mode_rate, max_lanes, max_link_clock; 154 155 if (is_edp(intel_dp) && fixed_mode) { 156 if (mode->hdisplay > fixed_mode->hdisplay) 157 return MODE_PANEL; 158 159 if (mode->vdisplay > fixed_mode->vdisplay) 160 return MODE_PANEL; 161 162 target_clock = fixed_mode->clock; 163 } 164 165 max_link_clock = drm_dp_bw_code_to_link_rate(intel_dp_max_link_bw(intel_dp)); 166 max_lanes = drm_dp_max_lane_count(intel_dp->dpcd); 167 168 max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes); 169 mode_rate = intel_dp_link_required(target_clock, 18); 170 171 if (mode_rate > max_rate) 172 return MODE_CLOCK_HIGH; 173 174 if (mode->clock < 10000) 175 return MODE_CLOCK_LOW; 176 177 if (mode->flags & DRM_MODE_FLAG_DBLCLK) 178 return MODE_H_ILLEGAL; 179 180 return MODE_OK; 181} 182 183static uint32_t 184pack_aux(uint8_t *src, int src_bytes) 185{ 186 int i; 187 uint32_t v = 0; 188 189 if (src_bytes > 4) 190 src_bytes = 4; 191 for (i = 0; i < src_bytes; i++) 192 v |= ((uint32_t) src[i]) << ((3-i) * 8); 193 return v; 194} 195 196static void 197unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes) 198{ 199 int i; 200 if (dst_bytes > 4) 201 dst_bytes = 4; 202 for (i = 0; i < dst_bytes; i++) 203 dst[i] = src >> ((3-i) * 8); 204} 205 206/* hrawclock is 1/4 the FSB frequency */ 207static int 208intel_hrawclk(struct drm_device *dev) 209{ 210 struct drm_i915_private *dev_priv = dev->dev_private; 211 uint32_t clkcfg; 212 213 /* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */ 214 if (IS_VALLEYVIEW(dev)) 215 return 200; 216 217 clkcfg = I915_READ(CLKCFG); 218 switch (clkcfg & CLKCFG_FSB_MASK) { 219 case CLKCFG_FSB_400: 220 return 100; 221 case CLKCFG_FSB_533: 222 return 133; 223 case CLKCFG_FSB_667: 224 return 166; 225 case CLKCFG_FSB_800: 226 return 200; 227 case CLKCFG_FSB_1067: 228 return 266; 229 case CLKCFG_FSB_1333: 230 return 333; 231 /* these two are just a guess; one of them might be right */ 232 case CLKCFG_FSB_1600: 233 case CLKCFG_FSB_1600_ALT: 234 return 400; 235 default: 236 return 133; 237 } 238} 239 240static void 241intel_dp_init_panel_power_sequencer(struct drm_device *dev, 242 struct intel_dp *intel_dp, 243 struct edp_power_seq *out); 244static void 245intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev, 246 struct intel_dp *intel_dp, 247 struct edp_power_seq *out); 248 249static enum pipe 250vlv_power_sequencer_pipe(struct intel_dp *intel_dp) 251{ 252 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 253 struct drm_crtc *crtc = intel_dig_port->base.base.crtc; 254 struct drm_device *dev = intel_dig_port->base.base.dev; 255 struct drm_i915_private *dev_priv = dev->dev_private; 256 enum port port = intel_dig_port->port; 257 enum pipe pipe; 258 259 /* modeset should have pipe */ 260 if (crtc) 261 return to_intel_crtc(crtc)->pipe; 262 263 /* init time, try to find a pipe with this port selected */ 264 for (pipe = PIPE_A; pipe <= PIPE_B; pipe++) { 265 u32 port_sel = I915_READ(VLV_PIPE_PP_ON_DELAYS(pipe)) & 266 PANEL_PORT_SELECT_MASK; 267 if (port_sel == PANEL_PORT_SELECT_DPB_VLV && port == PORT_B) 268 return pipe; 269 if (port_sel == PANEL_PORT_SELECT_DPC_VLV && port == PORT_C) 270 return pipe; 271 } 272 273 /* shrug */ 274 return PIPE_A; 275} 276 277static u32 _pp_ctrl_reg(struct intel_dp *intel_dp) 278{ 279 struct drm_device *dev = intel_dp_to_dev(intel_dp); 280 281 if (HAS_PCH_SPLIT(dev)) 282 return PCH_PP_CONTROL; 283 else 284 return VLV_PIPE_PP_CONTROL(vlv_power_sequencer_pipe(intel_dp)); 285} 286 287static u32 _pp_stat_reg(struct intel_dp *intel_dp) 288{ 289 struct drm_device *dev = intel_dp_to_dev(intel_dp); 290 291 if (HAS_PCH_SPLIT(dev)) 292 return PCH_PP_STATUS; 293 else 294 return VLV_PIPE_PP_STATUS(vlv_power_sequencer_pipe(intel_dp)); 295} 296 297static bool ironlake_edp_have_panel_power(struct intel_dp *intel_dp) 298{ 299 struct drm_device *dev = intel_dp_to_dev(intel_dp); 300 struct drm_i915_private *dev_priv = dev->dev_private; 301 302 return (I915_READ(_pp_stat_reg(intel_dp)) & PP_ON) != 0; 303} 304 305static bool ironlake_edp_have_panel_vdd(struct intel_dp *intel_dp) 306{ 307 struct drm_device *dev = intel_dp_to_dev(intel_dp); 308 struct drm_i915_private *dev_priv = dev->dev_private; 309 310 return (I915_READ(_pp_ctrl_reg(intel_dp)) & EDP_FORCE_VDD) != 0; 311} 312 313static void 314intel_dp_check_edp(struct intel_dp *intel_dp) 315{ 316 struct drm_device *dev = intel_dp_to_dev(intel_dp); 317 struct drm_i915_private *dev_priv = dev->dev_private; 318 319 if (!is_edp(intel_dp)) 320 return; 321 322 if (!ironlake_edp_have_panel_power(intel_dp) && !ironlake_edp_have_panel_vdd(intel_dp)) { 323 WARN(1, "eDP powered off while attempting aux channel communication.\n"); 324 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n", 325 I915_READ(_pp_stat_reg(intel_dp)), 326 I915_READ(_pp_ctrl_reg(intel_dp))); 327 } 328} 329 330static uint32_t 331intel_dp_aux_wait_done(struct intel_dp *intel_dp, bool has_aux_irq) 332{ 333 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 334 struct drm_device *dev = intel_dig_port->base.base.dev; 335 struct drm_i915_private *dev_priv = dev->dev_private; 336 uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg; 337 uint32_t status; 338 bool done; 339 340#define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0) 341 if (has_aux_irq) 342 done = wait_event_timeout(dev_priv->gmbus_wait_queue, C, 343 msecs_to_jiffies_timeout(10)); 344 else 345 done = wait_for_atomic(C, 10) == 0; 346 if (!done) 347 DRM_ERROR("dp aux hw did not signal timeout (has irq: %i)!\n", 348 has_aux_irq); 349#undef C 350 351 return status; 352} 353 354static uint32_t get_aux_clock_divider(struct intel_dp *intel_dp, 355 int index) 356{ 357 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 358 struct drm_device *dev = intel_dig_port->base.base.dev; 359 struct drm_i915_private *dev_priv = dev->dev_private; 360 361 /* The clock divider is based off the hrawclk, 362 * and would like to run at 2MHz. So, take the 363 * hrawclk value and divide by 2 and use that 364 * 365 * Note that PCH attached eDP panels should use a 125MHz input 366 * clock divider. 367 */ 368 if (IS_VALLEYVIEW(dev)) { 369 return index ? 0 : 100; 370 } else if (intel_dig_port->port == PORT_A) { 371 if (index) 372 return 0; 373 if (HAS_DDI(dev)) 374 return DIV_ROUND_CLOSEST(intel_ddi_get_cdclk_freq(dev_priv), 2000); 375 else if (IS_GEN6(dev) || IS_GEN7(dev)) 376 return 200; /* SNB & IVB eDP input clock at 400Mhz */ 377 else 378 return 225; /* eDP input clock at 450Mhz */ 379 } else if (dev_priv->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE) { 380 /* Workaround for non-ULT HSW */ 381 switch (index) { 382 case 0: return 63; 383 case 1: return 72; 384 default: return 0; 385 } 386 } else if (HAS_PCH_SPLIT(dev)) { 387 return index ? 0 : DIV_ROUND_UP(intel_pch_rawclk(dev), 2); 388 } else { 389 return index ? 0 :intel_hrawclk(dev) / 2; 390 } 391} 392 393static int 394intel_dp_aux_ch(struct intel_dp *intel_dp, 395 uint8_t *send, int send_bytes, 396 uint8_t *recv, int recv_size) 397{ 398 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 399 struct drm_device *dev = intel_dig_port->base.base.dev; 400 struct drm_i915_private *dev_priv = dev->dev_private; 401 uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg; 402 uint32_t ch_data = ch_ctl + 4; 403 uint32_t aux_clock_divider; 404 int i, ret, recv_bytes; 405 uint32_t status; 406 int try, precharge, clock = 0; 407 bool has_aux_irq = INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev); 408 409 /* dp aux is extremely sensitive to irq latency, hence request the 410 * lowest possible wakeup latency and so prevent the cpu from going into 411 * deep sleep states. 412 */ 413 pm_qos_update_request(&dev_priv->pm_qos, 0); 414 415 intel_dp_check_edp(intel_dp); 416 417 if (IS_GEN6(dev)) 418 precharge = 3; 419 else 420 precharge = 5; 421 422 intel_aux_display_runtime_get(dev_priv); 423 424 /* Try to wait for any previous AUX channel activity */ 425 for (try = 0; try < 3; try++) { 426 status = I915_READ_NOTRACE(ch_ctl); 427 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0) 428 break; 429 msleep(1); 430 } 431 432 if (try == 3) { 433 WARN(1, "dp_aux_ch not started status 0x%08x\n", 434 I915_READ(ch_ctl)); 435 ret = -EBUSY; 436 goto out; 437 } 438 439 /* Only 5 data registers! */ 440 if (WARN_ON(send_bytes > 20 || recv_size > 20)) { 441 ret = -E2BIG; 442 goto out; 443 } 444 445 while ((aux_clock_divider = get_aux_clock_divider(intel_dp, clock++))) { 446 /* Must try at least 3 times according to DP spec */ 447 for (try = 0; try < 5; try++) { 448 /* Load the send data into the aux channel data registers */ 449 for (i = 0; i < send_bytes; i += 4) 450 I915_WRITE(ch_data + i, 451 pack_aux(send + i, send_bytes - i)); 452 453 /* Send the command and wait for it to complete */ 454 I915_WRITE(ch_ctl, 455 DP_AUX_CH_CTL_SEND_BUSY | 456 (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) | 457 DP_AUX_CH_CTL_TIME_OUT_400us | 458 (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) | 459 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) | 460 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT) | 461 DP_AUX_CH_CTL_DONE | 462 DP_AUX_CH_CTL_TIME_OUT_ERROR | 463 DP_AUX_CH_CTL_RECEIVE_ERROR); 464 465 status = intel_dp_aux_wait_done(intel_dp, has_aux_irq); 466 467 /* Clear done status and any errors */ 468 I915_WRITE(ch_ctl, 469 status | 470 DP_AUX_CH_CTL_DONE | 471 DP_AUX_CH_CTL_TIME_OUT_ERROR | 472 DP_AUX_CH_CTL_RECEIVE_ERROR); 473 474 if (status & (DP_AUX_CH_CTL_TIME_OUT_ERROR | 475 DP_AUX_CH_CTL_RECEIVE_ERROR)) 476 continue; 477 if (status & DP_AUX_CH_CTL_DONE) 478 break; 479 } 480 if (status & DP_AUX_CH_CTL_DONE) 481 break; 482 } 483 484 if ((status & DP_AUX_CH_CTL_DONE) == 0) { 485 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status); 486 ret = -EBUSY; 487 goto out; 488 } 489 490 /* Check for timeout or receive error. 491 * Timeouts occur when the sink is not connected 492 */ 493 if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) { 494 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status); 495 ret = -EIO; 496 goto out; 497 } 498 499 /* Timeouts occur when the device isn't connected, so they're 500 * "normal" -- don't fill the kernel log with these */ 501 if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) { 502 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status); 503 ret = -ETIMEDOUT; 504 goto out; 505 } 506 507 /* Unload any bytes sent back from the other side */ 508 recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >> 509 DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT); 510 if (recv_bytes > recv_size) 511 recv_bytes = recv_size; 512 513 for (i = 0; i < recv_bytes; i += 4) 514 unpack_aux(I915_READ(ch_data + i), 515 recv + i, recv_bytes - i); 516 517 ret = recv_bytes; 518out: 519 pm_qos_update_request(&dev_priv->pm_qos, PM_QOS_DEFAULT_VALUE); 520 intel_aux_display_runtime_put(dev_priv); 521 522 return ret; 523} 524 525/* Write data to the aux channel in native mode */ 526static int 527intel_dp_aux_native_write(struct intel_dp *intel_dp, 528 uint16_t address, uint8_t *send, int send_bytes) 529{ 530 int ret; 531 uint8_t msg[20]; 532 int msg_bytes; 533 uint8_t ack; 534 535 if (WARN_ON(send_bytes > 16)) 536 return -E2BIG; 537 538 intel_dp_check_edp(intel_dp); 539 msg[0] = AUX_NATIVE_WRITE << 4; 540 msg[1] = address >> 8; 541 msg[2] = address & 0xff; 542 msg[3] = send_bytes - 1; 543 memcpy(&msg[4], send, send_bytes); 544 msg_bytes = send_bytes + 4; 545 for (;;) { 546 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes, &ack, 1); 547 if (ret < 0) 548 return ret; 549 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK) 550 break; 551 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER) 552 udelay(100); 553 else 554 return -EIO; 555 } 556 return send_bytes; 557} 558 559/* Write a single byte to the aux channel in native mode */ 560static int 561intel_dp_aux_native_write_1(struct intel_dp *intel_dp, 562 uint16_t address, uint8_t byte) 563{ 564 return intel_dp_aux_native_write(intel_dp, address, &byte, 1); 565} 566 567/* read bytes from a native aux channel */ 568static int 569intel_dp_aux_native_read(struct intel_dp *intel_dp, 570 uint16_t address, uint8_t *recv, int recv_bytes) 571{ 572 uint8_t msg[4]; 573 int msg_bytes; 574 uint8_t reply[20]; 575 int reply_bytes; 576 uint8_t ack; 577 int ret; 578 579 if (WARN_ON(recv_bytes > 19)) 580 return -E2BIG; 581 582 intel_dp_check_edp(intel_dp); 583 msg[0] = AUX_NATIVE_READ << 4; 584 msg[1] = address >> 8; 585 msg[2] = address & 0xff; 586 msg[3] = recv_bytes - 1; 587 588 msg_bytes = 4; 589 reply_bytes = recv_bytes + 1; 590 591 for (;;) { 592 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes, 593 reply, reply_bytes); 594 if (ret == 0) 595 return -EPROTO; 596 if (ret < 0) 597 return ret; 598 ack = reply[0]; 599 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK) { 600 memcpy(recv, reply + 1, ret - 1); 601 return ret - 1; 602 } 603 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER) 604 udelay(100); 605 else 606 return -EIO; 607 } 608} 609 610static int 611intel_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode, 612 uint8_t write_byte, uint8_t *read_byte) 613{ 614 struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data; 615 struct intel_dp *intel_dp = container_of(adapter, 616 struct intel_dp, 617 adapter); 618 uint16_t address = algo_data->address; 619 uint8_t msg[5]; 620 uint8_t reply[2]; 621 unsigned retry; 622 int msg_bytes; 623 int reply_bytes; 624 int ret; 625 626 ironlake_edp_panel_vdd_on(intel_dp); 627 intel_dp_check_edp(intel_dp); 628 /* Set up the command byte */ 629 if (mode & MODE_I2C_READ) 630 msg[0] = AUX_I2C_READ << 4; 631 else 632 msg[0] = AUX_I2C_WRITE << 4; 633 634 if (!(mode & MODE_I2C_STOP)) 635 msg[0] |= AUX_I2C_MOT << 4; 636 637 msg[1] = address >> 8; 638 msg[2] = address; 639 640 switch (mode) { 641 case MODE_I2C_WRITE: 642 msg[3] = 0; 643 msg[4] = write_byte; 644 msg_bytes = 5; 645 reply_bytes = 1; 646 break; 647 case MODE_I2C_READ: 648 msg[3] = 0; 649 msg_bytes = 4; 650 reply_bytes = 2; 651 break; 652 default: 653 msg_bytes = 3; 654 reply_bytes = 1; 655 break; 656 } 657 658 /* 659 * DP1.2 sections 2.7.7.1.5.6.1 and 2.7.7.1.6.6.1: A DP Source device is 660 * required to retry at least seven times upon receiving AUX_DEFER 661 * before giving up the AUX transaction. 662 */ 663 for (retry = 0; retry < 7; retry++) { 664 ret = intel_dp_aux_ch(intel_dp, 665 msg, msg_bytes, 666 reply, reply_bytes); 667 if (ret < 0) { 668 DRM_DEBUG_KMS("aux_ch failed %d\n", ret); 669 goto out; 670 } 671 672 switch (reply[0] & AUX_NATIVE_REPLY_MASK) { 673 case AUX_NATIVE_REPLY_ACK: 674 /* I2C-over-AUX Reply field is only valid 675 * when paired with AUX ACK. 676 */ 677 break; 678 case AUX_NATIVE_REPLY_NACK: 679 DRM_DEBUG_KMS("aux_ch native nack\n"); 680 ret = -EREMOTEIO; 681 goto out; 682 case AUX_NATIVE_REPLY_DEFER: 683 /* 684 * For now, just give more slack to branch devices. We 685 * could check the DPCD for I2C bit rate capabilities, 686 * and if available, adjust the interval. We could also 687 * be more careful with DP-to-Legacy adapters where a 688 * long legacy cable may force very low I2C bit rates. 689 */ 690 if (intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] & 691 DP_DWN_STRM_PORT_PRESENT) 692 usleep_range(500, 600); 693 else 694 usleep_range(300, 400); 695 continue; 696 default: 697 DRM_ERROR("aux_ch invalid native reply 0x%02x\n", 698 reply[0]); 699 ret = -EREMOTEIO; 700 goto out; 701 } 702 703 switch (reply[0] & AUX_I2C_REPLY_MASK) { 704 case AUX_I2C_REPLY_ACK: 705 if (mode == MODE_I2C_READ) { 706 *read_byte = reply[1]; 707 } 708 ret = reply_bytes - 1; 709 goto out; 710 case AUX_I2C_REPLY_NACK: 711 DRM_DEBUG_KMS("aux_i2c nack\n"); 712 ret = -EREMOTEIO; 713 goto out; 714 case AUX_I2C_REPLY_DEFER: 715 DRM_DEBUG_KMS("aux_i2c defer\n"); 716 udelay(100); 717 break; 718 default: 719 DRM_ERROR("aux_i2c invalid reply 0x%02x\n", reply[0]); 720 ret = -EREMOTEIO; 721 goto out; 722 } 723 } 724 725 DRM_ERROR("too many retries, giving up\n"); 726 ret = -EREMOTEIO; 727 728out: 729 ironlake_edp_panel_vdd_off(intel_dp, false); 730 return ret; 731} 732 733static int 734intel_dp_i2c_init(struct intel_dp *intel_dp, 735 struct intel_connector *intel_connector, const char *name) 736{ 737 int ret; 738 739 DRM_DEBUG_KMS("i2c_init %s\n", name); 740 intel_dp->algo.running = false; 741 intel_dp->algo.address = 0; 742 intel_dp->algo.aux_ch = intel_dp_i2c_aux_ch; 743 744 memset(&intel_dp->adapter, '\0', sizeof(intel_dp->adapter)); 745 intel_dp->adapter.owner = THIS_MODULE; 746 intel_dp->adapter.class = I2C_CLASS_DDC; 747 strncpy(intel_dp->adapter.name, name, sizeof(intel_dp->adapter.name) - 1); 748 intel_dp->adapter.name[sizeof(intel_dp->adapter.name) - 1] = '\0'; 749 intel_dp->adapter.algo_data = &intel_dp->algo; 750 intel_dp->adapter.dev.parent = &intel_connector->base.kdev; 751 752 ret = i2c_dp_aux_add_bus(&intel_dp->adapter); 753 return ret; 754} 755 756static void 757intel_dp_set_clock(struct intel_encoder *encoder, 758 struct intel_crtc_config *pipe_config, int link_bw) 759{ 760 struct drm_device *dev = encoder->base.dev; 761 const struct dp_link_dpll *divisor = NULL; 762 int i, count = 0; 763 764 if (IS_G4X(dev)) { 765 divisor = gen4_dpll; 766 count = ARRAY_SIZE(gen4_dpll); 767 } else if (IS_HASWELL(dev)) { 768 /* Haswell has special-purpose DP DDI clocks. */ 769 } else if (HAS_PCH_SPLIT(dev)) { 770 divisor = pch_dpll; 771 count = ARRAY_SIZE(pch_dpll); 772 } else if (IS_VALLEYVIEW(dev)) { 773 divisor = vlv_dpll; 774 count = ARRAY_SIZE(vlv_dpll); 775 } 776 777 if (divisor && count) { 778 for (i = 0; i < count; i++) { 779 if (link_bw == divisor[i].link_bw) { 780 pipe_config->dpll = divisor[i].dpll; 781 pipe_config->clock_set = true; 782 break; 783 } 784 } 785 } 786} 787 788bool 789intel_dp_compute_config(struct intel_encoder *encoder, 790 struct intel_crtc_config *pipe_config) 791{ 792 struct drm_device *dev = encoder->base.dev; 793 struct drm_i915_private *dev_priv = dev->dev_private; 794 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode; 795 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); 796 enum port port = dp_to_dig_port(intel_dp)->port; 797 struct intel_crtc *intel_crtc = encoder->new_crtc; 798 struct intel_connector *intel_connector = intel_dp->attached_connector; 799 int lane_count, clock; 800 int max_lane_count = drm_dp_max_lane_count(intel_dp->dpcd); 801 int max_clock = intel_dp_max_link_bw(intel_dp) == DP_LINK_BW_2_7 ? 1 : 0; 802 int bpp, mode_rate; 803 static int bws[2] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7 }; 804 int link_avail, link_clock; 805 806 if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev) && port != PORT_A) 807 pipe_config->has_pch_encoder = true; 808 809 pipe_config->has_dp_encoder = true; 810 811 if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) { 812 intel_fixed_panel_mode(intel_connector->panel.fixed_mode, 813 adjusted_mode); 814 if (!HAS_PCH_SPLIT(dev)) 815 intel_gmch_panel_fitting(intel_crtc, pipe_config, 816 intel_connector->panel.fitting_mode); 817 else 818 intel_pch_panel_fitting(intel_crtc, pipe_config, 819 intel_connector->panel.fitting_mode); 820 } 821 822 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK) 823 return false; 824 825 DRM_DEBUG_KMS("DP link computation with max lane count %i " 826 "max bw %02x pixel clock %iKHz\n", 827 max_lane_count, bws[max_clock], 828 adjusted_mode->crtc_clock); 829 830 /* Walk through all bpp values. Luckily they're all nicely spaced with 2 831 * bpc in between. */ 832 bpp = pipe_config->pipe_bpp; 833 if (is_edp(intel_dp) && dev_priv->vbt.edp_bpp && 834 dev_priv->vbt.edp_bpp < bpp) { 835 DRM_DEBUG_KMS("clamping bpp for eDP panel to BIOS-provided %i\n", 836 dev_priv->vbt.edp_bpp); 837 bpp = dev_priv->vbt.edp_bpp; 838 } 839 840 for (; bpp >= 6*3; bpp -= 2*3) { 841 mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock, 842 bpp); 843 844 for (clock = 0; clock <= max_clock; clock++) { 845 for (lane_count = 1; lane_count <= max_lane_count; lane_count <<= 1) { 846 link_clock = drm_dp_bw_code_to_link_rate(bws[clock]); 847 link_avail = intel_dp_max_data_rate(link_clock, 848 lane_count); 849 850 if (mode_rate <= link_avail) { 851 goto found; 852 } 853 } 854 } 855 } 856 857 return false; 858 859found: 860 if (intel_dp->color_range_auto) { 861 /* 862 * See: 863 * CEA-861-E - 5.1 Default Encoding Parameters 864 * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry 865 */ 866 if (bpp != 18 && drm_match_cea_mode(adjusted_mode) > 1) 867 intel_dp->color_range = DP_COLOR_RANGE_16_235; 868 else 869 intel_dp->color_range = 0; 870 } 871 872 if (intel_dp->color_range) 873 pipe_config->limited_color_range = true; 874 875 intel_dp->link_bw = bws[clock]; 876 intel_dp->lane_count = lane_count; 877 pipe_config->pipe_bpp = bpp; 878 pipe_config->port_clock = drm_dp_bw_code_to_link_rate(intel_dp->link_bw); 879 880 DRM_DEBUG_KMS("DP link bw %02x lane count %d clock %d bpp %d\n", 881 intel_dp->link_bw, intel_dp->lane_count, 882 pipe_config->port_clock, bpp); 883 DRM_DEBUG_KMS("DP link bw required %i available %i\n", 884 mode_rate, link_avail); 885 886 intel_link_compute_m_n(bpp, lane_count, 887 adjusted_mode->crtc_clock, 888 pipe_config->port_clock, 889 &pipe_config->dp_m_n); 890 891 intel_dp_set_clock(encoder, pipe_config, intel_dp->link_bw); 892 893 return true; 894} 895 896static void ironlake_set_pll_cpu_edp(struct intel_dp *intel_dp) 897{ 898 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 899 struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc); 900 struct drm_device *dev = crtc->base.dev; 901 struct drm_i915_private *dev_priv = dev->dev_private; 902 u32 dpa_ctl; 903 904 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", crtc->config.port_clock); 905 dpa_ctl = I915_READ(DP_A); 906 dpa_ctl &= ~DP_PLL_FREQ_MASK; 907 908 if (crtc->config.port_clock == 162000) { 909 /* For a long time we've carried around a ILK-DevA w/a for the 910 * 160MHz clock. If we're really unlucky, it's still required. 911 */ 912 DRM_DEBUG_KMS("160MHz cpu eDP clock, might need ilk devA w/a\n"); 913 dpa_ctl |= DP_PLL_FREQ_160MHZ; 914 intel_dp->DP |= DP_PLL_FREQ_160MHZ; 915 } else { 916 dpa_ctl |= DP_PLL_FREQ_270MHZ; 917 intel_dp->DP |= DP_PLL_FREQ_270MHZ; 918 } 919 920 I915_WRITE(DP_A, dpa_ctl); 921 922 POSTING_READ(DP_A); 923 udelay(500); 924} 925 926static void intel_dp_mode_set(struct intel_encoder *encoder) 927{ 928 struct drm_device *dev = encoder->base.dev; 929 struct drm_i915_private *dev_priv = dev->dev_private; 930 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); 931 enum port port = dp_to_dig_port(intel_dp)->port; 932 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); 933 struct drm_display_mode *adjusted_mode = &crtc->config.adjusted_mode; 934 935 /* 936 * There are four kinds of DP registers: 937 * 938 * IBX PCH 939 * SNB CPU 940 * IVB CPU 941 * CPT PCH 942 * 943 * IBX PCH and CPU are the same for almost everything, 944 * except that the CPU DP PLL is configured in this 945 * register 946 * 947 * CPT PCH is quite different, having many bits moved 948 * to the TRANS_DP_CTL register instead. That 949 * configuration happens (oddly) in ironlake_pch_enable 950 */ 951 952 /* Preserve the BIOS-computed detected bit. This is 953 * supposed to be read-only. 954 */ 955 intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED; 956 957 /* Handle DP bits in common between all three register formats */ 958 intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0; 959 intel_dp->DP |= DP_PORT_WIDTH(intel_dp->lane_count); 960 961 if (intel_dp->has_audio) { 962 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n", 963 pipe_name(crtc->pipe)); 964 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE; 965 intel_write_eld(&encoder->base, adjusted_mode); 966 } 967 968 /* Split out the IBX/CPU vs CPT settings */ 969 970 if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) { 971 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) 972 intel_dp->DP |= DP_SYNC_HS_HIGH; 973 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) 974 intel_dp->DP |= DP_SYNC_VS_HIGH; 975 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT; 976 977 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd)) 978 intel_dp->DP |= DP_ENHANCED_FRAMING; 979 980 intel_dp->DP |= crtc->pipe << 29; 981 } else if (!HAS_PCH_CPT(dev) || port == PORT_A) { 982 if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev)) 983 intel_dp->DP |= intel_dp->color_range; 984 985 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) 986 intel_dp->DP |= DP_SYNC_HS_HIGH; 987 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) 988 intel_dp->DP |= DP_SYNC_VS_HIGH; 989 intel_dp->DP |= DP_LINK_TRAIN_OFF; 990 991 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd)) 992 intel_dp->DP |= DP_ENHANCED_FRAMING; 993 994 if (crtc->pipe == 1) 995 intel_dp->DP |= DP_PIPEB_SELECT; 996 } else { 997 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT; 998 } 999 1000 if (port == PORT_A && !IS_VALLEYVIEW(dev)) 1001 ironlake_set_pll_cpu_edp(intel_dp); 1002} 1003 1004#define IDLE_ON_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK) 1005#define IDLE_ON_VALUE (PP_ON | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE) 1006 1007#define IDLE_OFF_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK) 1008#define IDLE_OFF_VALUE (0 | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE) 1009 1010#define IDLE_CYCLE_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK) 1011#define IDLE_CYCLE_VALUE (0 | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE) 1012 1013static void ironlake_wait_panel_status(struct intel_dp *intel_dp, 1014 u32 mask, 1015 u32 value) 1016{ 1017 struct drm_device *dev = intel_dp_to_dev(intel_dp); 1018 struct drm_i915_private *dev_priv = dev->dev_private; 1019 u32 pp_stat_reg, pp_ctrl_reg; 1020 1021 pp_stat_reg = _pp_stat_reg(intel_dp); 1022 pp_ctrl_reg = _pp_ctrl_reg(intel_dp); 1023 1024 DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n", 1025 mask, value, 1026 I915_READ(pp_stat_reg), 1027 I915_READ(pp_ctrl_reg)); 1028 1029 if (_wait_for((I915_READ(pp_stat_reg) & mask) == value, 5000, 10)) { 1030 DRM_ERROR("Panel status timeout: status %08x control %08x\n", 1031 I915_READ(pp_stat_reg), 1032 I915_READ(pp_ctrl_reg)); 1033 } 1034} 1035 1036static void ironlake_wait_panel_on(struct intel_dp *intel_dp) 1037{ 1038 DRM_DEBUG_KMS("Wait for panel power on\n"); 1039 ironlake_wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE); 1040} 1041 1042static void ironlake_wait_panel_off(struct intel_dp *intel_dp) 1043{ 1044 DRM_DEBUG_KMS("Wait for panel power off time\n"); 1045 ironlake_wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE); 1046} 1047 1048static void ironlake_wait_panel_power_cycle(struct intel_dp *intel_dp) 1049{ 1050 DRM_DEBUG_KMS("Wait for panel power cycle\n"); 1051 ironlake_wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE); 1052} 1053 1054 1055/* Read the current pp_control value, unlocking the register if it 1056 * is locked 1057 */ 1058 1059static u32 ironlake_get_pp_control(struct intel_dp *intel_dp) 1060{ 1061 struct drm_device *dev = intel_dp_to_dev(intel_dp); 1062 struct drm_i915_private *dev_priv = dev->dev_private; 1063 u32 control; 1064 1065 control = I915_READ(_pp_ctrl_reg(intel_dp)); 1066 control &= ~PANEL_UNLOCK_MASK; 1067 control |= PANEL_UNLOCK_REGS; 1068 return control; 1069} 1070 1071void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp) 1072{ 1073 struct drm_device *dev = intel_dp_to_dev(intel_dp); 1074 struct drm_i915_private *dev_priv = dev->dev_private; 1075 u32 pp; 1076 u32 pp_stat_reg, pp_ctrl_reg; 1077 1078 if (!is_edp(intel_dp)) 1079 return; 1080 1081 WARN(intel_dp->want_panel_vdd, 1082 "eDP VDD already requested on\n"); 1083 1084 intel_dp->want_panel_vdd = true; 1085 1086 if (ironlake_edp_have_panel_vdd(intel_dp)) 1087 return; 1088 1089 DRM_DEBUG_KMS("Turning eDP VDD on\n"); 1090 1091 if (!ironlake_edp_have_panel_power(intel_dp)) 1092 ironlake_wait_panel_power_cycle(intel_dp); 1093 1094 pp = ironlake_get_pp_control(intel_dp); 1095 pp |= EDP_FORCE_VDD; 1096 1097 pp_stat_reg = _pp_stat_reg(intel_dp); 1098 pp_ctrl_reg = _pp_ctrl_reg(intel_dp); 1099 1100 I915_WRITE(pp_ctrl_reg, pp); 1101 POSTING_READ(pp_ctrl_reg); 1102 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n", 1103 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg)); 1104 /* 1105 * If the panel wasn't on, delay before accessing aux channel 1106 */ 1107 if (!ironlake_edp_have_panel_power(intel_dp)) { 1108 DRM_DEBUG_KMS("eDP was not running\n"); 1109 msleep(intel_dp->panel_power_up_delay); 1110 } 1111} 1112 1113static void ironlake_panel_vdd_off_sync(struct intel_dp *intel_dp) 1114{ 1115 struct drm_device *dev = intel_dp_to_dev(intel_dp); 1116 struct drm_i915_private *dev_priv = dev->dev_private; 1117 u32 pp; 1118 u32 pp_stat_reg, pp_ctrl_reg; 1119 1120 WARN_ON(!mutex_is_locked(&dev->mode_config.mutex)); 1121 1122 if (!intel_dp->want_panel_vdd && ironlake_edp_have_panel_vdd(intel_dp)) { 1123 DRM_DEBUG_KMS("Turning eDP VDD off\n"); 1124 1125 pp = ironlake_get_pp_control(intel_dp); 1126 pp &= ~EDP_FORCE_VDD; 1127 1128 pp_ctrl_reg = _pp_ctrl_reg(intel_dp); 1129 pp_stat_reg = _pp_stat_reg(intel_dp); 1130 1131 I915_WRITE(pp_ctrl_reg, pp); 1132 POSTING_READ(pp_ctrl_reg); 1133 1134 /* Make sure sequencer is idle before allowing subsequent activity */ 1135 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n", 1136 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg)); 1137 msleep(intel_dp->panel_power_down_delay); 1138 } 1139} 1140 1141static void ironlake_panel_vdd_work(struct work_struct *__work) 1142{ 1143 struct intel_dp *intel_dp = container_of(to_delayed_work(__work), 1144 struct intel_dp, panel_vdd_work); 1145 struct drm_device *dev = intel_dp_to_dev(intel_dp); 1146 1147 mutex_lock(&dev->mode_config.mutex); 1148 ironlake_panel_vdd_off_sync(intel_dp); 1149 mutex_unlock(&dev->mode_config.mutex); 1150} 1151 1152void ironlake_edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync) 1153{ 1154 if (!is_edp(intel_dp)) 1155 return; 1156 1157 WARN(!intel_dp->want_panel_vdd, "eDP VDD not forced on"); 1158 1159 intel_dp->want_panel_vdd = false; 1160 1161 if (sync) { 1162 ironlake_panel_vdd_off_sync(intel_dp); 1163 } else { 1164 /* 1165 * Queue the timer to fire a long 1166 * time from now (relative to the power down delay) 1167 * to keep the panel power up across a sequence of operations 1168 */ 1169 schedule_delayed_work(&intel_dp->panel_vdd_work, 1170 msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5)); 1171 } 1172} 1173 1174void ironlake_edp_panel_on(struct intel_dp *intel_dp) 1175{ 1176 struct drm_device *dev = intel_dp_to_dev(intel_dp); 1177 struct drm_i915_private *dev_priv = dev->dev_private; 1178 u32 pp; 1179 u32 pp_ctrl_reg; 1180 1181 if (!is_edp(intel_dp)) 1182 return; 1183 1184 DRM_DEBUG_KMS("Turn eDP power on\n"); 1185 1186 if (ironlake_edp_have_panel_power(intel_dp)) { 1187 DRM_DEBUG_KMS("eDP power already on\n"); 1188 return; 1189 } 1190 1191 ironlake_wait_panel_power_cycle(intel_dp); 1192 1193 pp_ctrl_reg = _pp_ctrl_reg(intel_dp); 1194 pp = ironlake_get_pp_control(intel_dp); 1195 if (IS_GEN5(dev)) { 1196 /* ILK workaround: disable reset around power sequence */ 1197 pp &= ~PANEL_POWER_RESET; 1198 I915_WRITE(pp_ctrl_reg, pp); 1199 POSTING_READ(pp_ctrl_reg); 1200 } 1201 1202 pp |= POWER_TARGET_ON; 1203 if (!IS_GEN5(dev)) 1204 pp |= PANEL_POWER_RESET; 1205 1206 I915_WRITE(pp_ctrl_reg, pp); 1207 POSTING_READ(pp_ctrl_reg); 1208 1209 ironlake_wait_panel_on(intel_dp); 1210 1211 if (IS_GEN5(dev)) { 1212 pp |= PANEL_POWER_RESET; /* restore panel reset bit */ 1213 I915_WRITE(pp_ctrl_reg, pp); 1214 POSTING_READ(pp_ctrl_reg); 1215 } 1216} 1217 1218void ironlake_edp_panel_off(struct intel_dp *intel_dp) 1219{ 1220 struct drm_device *dev = intel_dp_to_dev(intel_dp); 1221 struct drm_i915_private *dev_priv = dev->dev_private; 1222 u32 pp; 1223 u32 pp_ctrl_reg; 1224 1225 if (!is_edp(intel_dp)) 1226 return; 1227 1228 DRM_DEBUG_KMS("Turn eDP power off\n"); 1229 1230 WARN(!intel_dp->want_panel_vdd, "Need VDD to turn off panel\n"); 1231 1232 pp = ironlake_get_pp_control(intel_dp); 1233 /* We need to switch off panel power _and_ force vdd, for otherwise some 1234 * panels get very unhappy and cease to work. */ 1235 pp &= ~(POWER_TARGET_ON | EDP_FORCE_VDD | PANEL_POWER_RESET | EDP_BLC_ENABLE); 1236 1237 pp_ctrl_reg = _pp_ctrl_reg(intel_dp); 1238 1239 I915_WRITE(pp_ctrl_reg, pp); 1240 POSTING_READ(pp_ctrl_reg); 1241 1242 intel_dp->want_panel_vdd = false; 1243 1244 ironlake_wait_panel_off(intel_dp); 1245} 1246 1247void ironlake_edp_backlight_on(struct intel_dp *intel_dp) 1248{ 1249 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 1250 struct drm_device *dev = intel_dig_port->base.base.dev; 1251 struct drm_i915_private *dev_priv = dev->dev_private; 1252 u32 pp; 1253 u32 pp_ctrl_reg; 1254 1255 if (!is_edp(intel_dp)) 1256 return; 1257 1258 DRM_DEBUG_KMS("\n"); 1259 /* 1260 * If we enable the backlight right away following a panel power 1261 * on, we may see slight flicker as the panel syncs with the eDP 1262 * link. So delay a bit to make sure the image is solid before 1263 * allowing it to appear. 1264 */ 1265 msleep(intel_dp->backlight_on_delay); 1266 pp = ironlake_get_pp_control(intel_dp); 1267 pp |= EDP_BLC_ENABLE; 1268 1269 pp_ctrl_reg = _pp_ctrl_reg(intel_dp); 1270 1271 I915_WRITE(pp_ctrl_reg, pp); 1272 POSTING_READ(pp_ctrl_reg); 1273 1274 intel_panel_enable_backlight(intel_dp->attached_connector); 1275} 1276 1277void ironlake_edp_backlight_off(struct intel_dp *intel_dp) 1278{ 1279 struct drm_device *dev = intel_dp_to_dev(intel_dp); 1280 struct drm_i915_private *dev_priv = dev->dev_private; 1281 u32 pp; 1282 u32 pp_ctrl_reg; 1283 1284 if (!is_edp(intel_dp)) 1285 return; 1286 1287 intel_panel_disable_backlight(intel_dp->attached_connector); 1288 1289 DRM_DEBUG_KMS("\n"); 1290 pp = ironlake_get_pp_control(intel_dp); 1291 pp &= ~EDP_BLC_ENABLE; 1292 1293 pp_ctrl_reg = _pp_ctrl_reg(intel_dp); 1294 1295 I915_WRITE(pp_ctrl_reg, pp); 1296 POSTING_READ(pp_ctrl_reg); 1297 msleep(intel_dp->backlight_off_delay); 1298} 1299 1300static void ironlake_edp_pll_on(struct intel_dp *intel_dp) 1301{ 1302 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 1303 struct drm_crtc *crtc = intel_dig_port->base.base.crtc; 1304 struct drm_device *dev = crtc->dev; 1305 struct drm_i915_private *dev_priv = dev->dev_private; 1306 u32 dpa_ctl; 1307 1308 assert_pipe_disabled(dev_priv, 1309 to_intel_crtc(crtc)->pipe); 1310 1311 DRM_DEBUG_KMS("\n"); 1312 dpa_ctl = I915_READ(DP_A); 1313 WARN(dpa_ctl & DP_PLL_ENABLE, "dp pll on, should be off\n"); 1314 WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n"); 1315 1316 /* We don't adjust intel_dp->DP while tearing down the link, to 1317 * facilitate link retraining (e.g. after hotplug). Hence clear all 1318 * enable bits here to ensure that we don't enable too much. */ 1319 intel_dp->DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE); 1320 intel_dp->DP |= DP_PLL_ENABLE; 1321 I915_WRITE(DP_A, intel_dp->DP); 1322 POSTING_READ(DP_A); 1323 udelay(200); 1324} 1325 1326static void ironlake_edp_pll_off(struct intel_dp *intel_dp) 1327{ 1328 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 1329 struct drm_crtc *crtc = intel_dig_port->base.base.crtc; 1330 struct drm_device *dev = crtc->dev; 1331 struct drm_i915_private *dev_priv = dev->dev_private; 1332 u32 dpa_ctl; 1333 1334 assert_pipe_disabled(dev_priv, 1335 to_intel_crtc(crtc)->pipe); 1336 1337 dpa_ctl = I915_READ(DP_A); 1338 WARN((dpa_ctl & DP_PLL_ENABLE) == 0, 1339 "dp pll off, should be on\n"); 1340 WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n"); 1341 1342 /* We can't rely on the value tracked for the DP register in 1343 * intel_dp->DP because link_down must not change that (otherwise link 1344 * re-training will fail. */ 1345 dpa_ctl &= ~DP_PLL_ENABLE; 1346 I915_WRITE(DP_A, dpa_ctl); 1347 POSTING_READ(DP_A); 1348 udelay(200); 1349} 1350 1351/* If the sink supports it, try to set the power state appropriately */ 1352void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode) 1353{ 1354 int ret, i; 1355 1356 /* Should have a valid DPCD by this point */ 1357 if (intel_dp->dpcd[DP_DPCD_REV] < 0x11) 1358 return; 1359 1360 if (mode != DRM_MODE_DPMS_ON) { 1361 ret = intel_dp_aux_native_write_1(intel_dp, DP_SET_POWER, 1362 DP_SET_POWER_D3); 1363 if (ret != 1) 1364 DRM_DEBUG_DRIVER("failed to write sink power state\n"); 1365 } else { 1366 /* 1367 * When turning on, we need to retry for 1ms to give the sink 1368 * time to wake up. 1369 */ 1370 for (i = 0; i < 3; i++) { 1371 ret = intel_dp_aux_native_write_1(intel_dp, 1372 DP_SET_POWER, 1373 DP_SET_POWER_D0); 1374 if (ret == 1) 1375 break; 1376 msleep(1); 1377 } 1378 } 1379} 1380 1381static bool intel_dp_get_hw_state(struct intel_encoder *encoder, 1382 enum pipe *pipe) 1383{ 1384 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); 1385 enum port port = dp_to_dig_port(intel_dp)->port; 1386 struct drm_device *dev = encoder->base.dev; 1387 struct drm_i915_private *dev_priv = dev->dev_private; 1388 u32 tmp = I915_READ(intel_dp->output_reg); 1389 1390 if (!(tmp & DP_PORT_EN)) 1391 return false; 1392 1393 if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) { 1394 *pipe = PORT_TO_PIPE_CPT(tmp); 1395 } else if (!HAS_PCH_CPT(dev) || port == PORT_A) { 1396 *pipe = PORT_TO_PIPE(tmp); 1397 } else { 1398 u32 trans_sel; 1399 u32 trans_dp; 1400 int i; 1401 1402 switch (intel_dp->output_reg) { 1403 case PCH_DP_B: 1404 trans_sel = TRANS_DP_PORT_SEL_B; 1405 break; 1406 case PCH_DP_C: 1407 trans_sel = TRANS_DP_PORT_SEL_C; 1408 break; 1409 case PCH_DP_D: 1410 trans_sel = TRANS_DP_PORT_SEL_D; 1411 break; 1412 default: 1413 return true; 1414 } 1415 1416 for_each_pipe(i) { 1417 trans_dp = I915_READ(TRANS_DP_CTL(i)); 1418 if ((trans_dp & TRANS_DP_PORT_SEL_MASK) == trans_sel) { 1419 *pipe = i; 1420 return true; 1421 } 1422 } 1423 1424 DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n", 1425 intel_dp->output_reg); 1426 } 1427 1428 return true; 1429} 1430 1431static void intel_dp_get_config(struct intel_encoder *encoder, 1432 struct intel_crtc_config *pipe_config) 1433{ 1434 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); 1435 u32 tmp, flags = 0; 1436 struct drm_device *dev = encoder->base.dev; 1437 struct drm_i915_private *dev_priv = dev->dev_private; 1438 enum port port = dp_to_dig_port(intel_dp)->port; 1439 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); 1440 int dotclock; 1441 1442 if ((port == PORT_A) || !HAS_PCH_CPT(dev)) { 1443 tmp = I915_READ(intel_dp->output_reg); 1444 if (tmp & DP_SYNC_HS_HIGH) 1445 flags |= DRM_MODE_FLAG_PHSYNC; 1446 else 1447 flags |= DRM_MODE_FLAG_NHSYNC; 1448 1449 if (tmp & DP_SYNC_VS_HIGH) 1450 flags |= DRM_MODE_FLAG_PVSYNC; 1451 else 1452 flags |= DRM_MODE_FLAG_NVSYNC; 1453 } else { 1454 tmp = I915_READ(TRANS_DP_CTL(crtc->pipe)); 1455 if (tmp & TRANS_DP_HSYNC_ACTIVE_HIGH) 1456 flags |= DRM_MODE_FLAG_PHSYNC; 1457 else 1458 flags |= DRM_MODE_FLAG_NHSYNC; 1459 1460 if (tmp & TRANS_DP_VSYNC_ACTIVE_HIGH) 1461 flags |= DRM_MODE_FLAG_PVSYNC; 1462 else 1463 flags |= DRM_MODE_FLAG_NVSYNC; 1464 } 1465 1466 pipe_config->adjusted_mode.flags |= flags; 1467 1468 pipe_config->has_dp_encoder = true; 1469 1470 intel_dp_get_m_n(crtc, pipe_config); 1471 1472 if (port == PORT_A) { 1473 if ((I915_READ(DP_A) & DP_PLL_FREQ_MASK) == DP_PLL_FREQ_160MHZ) 1474 pipe_config->port_clock = 162000; 1475 else 1476 pipe_config->port_clock = 270000; 1477 } 1478 1479 dotclock = intel_dotclock_calculate(pipe_config->port_clock, 1480 &pipe_config->dp_m_n); 1481 1482 if (HAS_PCH_SPLIT(dev_priv->dev) && port != PORT_A) 1483 ironlake_check_encoder_dotclock(pipe_config, dotclock); 1484 1485 pipe_config->adjusted_mode.crtc_clock = dotclock; 1486 1487 if (is_edp(intel_dp) && dev_priv->vbt.edp_bpp && 1488 pipe_config->pipe_bpp > dev_priv->vbt.edp_bpp) { 1489 /* 1490 * This is a big fat ugly hack. 1491 * 1492 * Some machines in UEFI boot mode provide us a VBT that has 18 1493 * bpp and 1.62 GHz link bandwidth for eDP, which for reasons 1494 * unknown we fail to light up. Yet the same BIOS boots up with 1495 * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as 1496 * max, not what it tells us to use. 1497 * 1498 * Note: This will still be broken if the eDP panel is not lit 1499 * up by the BIOS, and thus we can't get the mode at module 1500 * load. 1501 */ 1502 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n", 1503 pipe_config->pipe_bpp, dev_priv->vbt.edp_bpp); 1504 dev_priv->vbt.edp_bpp = pipe_config->pipe_bpp; 1505 } 1506} 1507 1508static bool is_edp_psr(struct drm_device *dev) 1509{ 1510 struct drm_i915_private *dev_priv = dev->dev_private; 1511 1512 return dev_priv->psr.sink_support; 1513} 1514 1515static bool intel_edp_is_psr_enabled(struct drm_device *dev) 1516{ 1517 struct drm_i915_private *dev_priv = dev->dev_private; 1518 1519 if (!HAS_PSR(dev)) 1520 return false; 1521 1522 return I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE; 1523} 1524 1525static void intel_edp_psr_write_vsc(struct intel_dp *intel_dp, 1526 struct edp_vsc_psr *vsc_psr) 1527{ 1528 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 1529 struct drm_device *dev = dig_port->base.base.dev; 1530 struct drm_i915_private *dev_priv = dev->dev_private; 1531 struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc); 1532 u32 ctl_reg = HSW_TVIDEO_DIP_CTL(crtc->config.cpu_transcoder); 1533 u32 data_reg = HSW_TVIDEO_DIP_VSC_DATA(crtc->config.cpu_transcoder); 1534 uint32_t *data = (uint32_t *) vsc_psr; 1535 unsigned int i; 1536 1537 /* As per BSPec (Pipe Video Data Island Packet), we need to disable 1538 the video DIP being updated before program video DIP data buffer 1539 registers for DIP being updated. */ 1540 I915_WRITE(ctl_reg, 0); 1541 POSTING_READ(ctl_reg); 1542 1543 for (i = 0; i < VIDEO_DIP_VSC_DATA_SIZE; i += 4) { 1544 if (i < sizeof(struct edp_vsc_psr)) 1545 I915_WRITE(data_reg + i, *data++); 1546 else 1547 I915_WRITE(data_reg + i, 0); 1548 } 1549 1550 I915_WRITE(ctl_reg, VIDEO_DIP_ENABLE_VSC_HSW); 1551 POSTING_READ(ctl_reg); 1552} 1553 1554static void intel_edp_psr_setup(struct intel_dp *intel_dp) 1555{ 1556 struct drm_device *dev = intel_dp_to_dev(intel_dp); 1557 struct drm_i915_private *dev_priv = dev->dev_private; 1558 struct edp_vsc_psr psr_vsc; 1559 1560 if (intel_dp->psr_setup_done) 1561 return; 1562 1563 /* Prepare VSC packet as per EDP 1.3 spec, Table 3.10 */ 1564 memset(&psr_vsc, 0, sizeof(psr_vsc)); 1565 psr_vsc.sdp_header.HB0 = 0; 1566 psr_vsc.sdp_header.HB1 = 0x7; 1567 psr_vsc.sdp_header.HB2 = 0x2; 1568 psr_vsc.sdp_header.HB3 = 0x8; 1569 intel_edp_psr_write_vsc(intel_dp, &psr_vsc); 1570 1571 /* Avoid continuous PSR exit by masking memup and hpd */ 1572 I915_WRITE(EDP_PSR_DEBUG_CTL(dev), EDP_PSR_DEBUG_MASK_MEMUP | 1573 EDP_PSR_DEBUG_MASK_HPD | EDP_PSR_DEBUG_MASK_LPSP); 1574 1575 intel_dp->psr_setup_done = true; 1576} 1577 1578static void intel_edp_psr_enable_sink(struct intel_dp *intel_dp) 1579{ 1580 struct drm_device *dev = intel_dp_to_dev(intel_dp); 1581 struct drm_i915_private *dev_priv = dev->dev_private; 1582 uint32_t aux_clock_divider = get_aux_clock_divider(intel_dp, 0); 1583 int precharge = 0x3; 1584 int msg_size = 5; /* Header(4) + Message(1) */ 1585 1586 /* Enable PSR in sink */ 1587 if (intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT) 1588 intel_dp_aux_native_write_1(intel_dp, DP_PSR_EN_CFG, 1589 DP_PSR_ENABLE & 1590 ~DP_PSR_MAIN_LINK_ACTIVE); 1591 else 1592 intel_dp_aux_native_write_1(intel_dp, DP_PSR_EN_CFG, 1593 DP_PSR_ENABLE | 1594 DP_PSR_MAIN_LINK_ACTIVE); 1595 1596 /* Setup AUX registers */ 1597 I915_WRITE(EDP_PSR_AUX_DATA1(dev), EDP_PSR_DPCD_COMMAND); 1598 I915_WRITE(EDP_PSR_AUX_DATA2(dev), EDP_PSR_DPCD_NORMAL_OPERATION); 1599 I915_WRITE(EDP_PSR_AUX_CTL(dev), 1600 DP_AUX_CH_CTL_TIME_OUT_400us | 1601 (msg_size << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) | 1602 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) | 1603 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT)); 1604} 1605 1606static void intel_edp_psr_enable_source(struct intel_dp *intel_dp) 1607{ 1608 struct drm_device *dev = intel_dp_to_dev(intel_dp); 1609 struct drm_i915_private *dev_priv = dev->dev_private; 1610 uint32_t max_sleep_time = 0x1f; 1611 uint32_t idle_frames = 1; 1612 uint32_t val = 0x0; 1613 1614 if (intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT) { 1615 val |= EDP_PSR_LINK_STANDBY; 1616 val |= EDP_PSR_TP2_TP3_TIME_0us; 1617 val |= EDP_PSR_TP1_TIME_0us; 1618 val |= EDP_PSR_SKIP_AUX_EXIT; 1619 } else 1620 val |= EDP_PSR_LINK_DISABLE; 1621 1622 I915_WRITE(EDP_PSR_CTL(dev), val | 1623 EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES | 1624 max_sleep_time << EDP_PSR_MAX_SLEEP_TIME_SHIFT | 1625 idle_frames << EDP_PSR_IDLE_FRAME_SHIFT | 1626 EDP_PSR_ENABLE); 1627} 1628 1629static bool intel_edp_psr_match_conditions(struct intel_dp *intel_dp) 1630{ 1631 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 1632 struct drm_device *dev = dig_port->base.base.dev; 1633 struct drm_i915_private *dev_priv = dev->dev_private; 1634 struct drm_crtc *crtc = dig_port->base.base.crtc; 1635 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 1636 struct drm_i915_gem_object *obj = to_intel_framebuffer(crtc->fb)->obj; 1637 struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base; 1638 1639 dev_priv->psr.source_ok = false; 1640 1641 if (!HAS_PSR(dev)) { 1642 DRM_DEBUG_KMS("PSR not supported on this platform\n"); 1643 return false; 1644 } 1645 1646 if ((intel_encoder->type != INTEL_OUTPUT_EDP) || 1647 (dig_port->port != PORT_A)) { 1648 DRM_DEBUG_KMS("HSW ties PSR to DDI A (eDP)\n"); 1649 return false; 1650 } 1651 1652 if (!i915_enable_psr) { 1653 DRM_DEBUG_KMS("PSR disable by flag\n"); 1654 return false; 1655 } 1656 1657 crtc = dig_port->base.base.crtc; 1658 if (crtc == NULL) { 1659 DRM_DEBUG_KMS("crtc not active for PSR\n"); 1660 return false; 1661 } 1662 1663 intel_crtc = to_intel_crtc(crtc); 1664 if (!intel_crtc_active(crtc)) { 1665 DRM_DEBUG_KMS("crtc not active for PSR\n"); 1666 return false; 1667 } 1668 1669 obj = to_intel_framebuffer(crtc->fb)->obj; 1670 if (obj->tiling_mode != I915_TILING_X || 1671 obj->fence_reg == I915_FENCE_REG_NONE) { 1672 DRM_DEBUG_KMS("PSR condition failed: fb not tiled or fenced\n"); 1673 return false; 1674 } 1675 1676 if (I915_READ(SPRCTL(intel_crtc->pipe)) & SPRITE_ENABLE) { 1677 DRM_DEBUG_KMS("PSR condition failed: Sprite is Enabled\n"); 1678 return false; 1679 } 1680 1681 if (I915_READ(HSW_STEREO_3D_CTL(intel_crtc->config.cpu_transcoder)) & 1682 S3D_ENABLE) { 1683 DRM_DEBUG_KMS("PSR condition failed: Stereo 3D is Enabled\n"); 1684 return false; 1685 } 1686 1687 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) { 1688 DRM_DEBUG_KMS("PSR condition failed: Interlaced is Enabled\n"); 1689 return false; 1690 } 1691 1692 dev_priv->psr.source_ok = true; 1693 return true; 1694} 1695 1696static void intel_edp_psr_do_enable(struct intel_dp *intel_dp) 1697{ 1698 struct drm_device *dev = intel_dp_to_dev(intel_dp); 1699 1700 if (!intel_edp_psr_match_conditions(intel_dp) || 1701 intel_edp_is_psr_enabled(dev)) 1702 return; 1703 1704 /* Setup PSR once */ 1705 intel_edp_psr_setup(intel_dp); 1706 1707 /* Enable PSR on the panel */ 1708 intel_edp_psr_enable_sink(intel_dp); 1709 1710 /* Enable PSR on the host */ 1711 intel_edp_psr_enable_source(intel_dp); 1712} 1713 1714void intel_edp_psr_enable(struct intel_dp *intel_dp) 1715{ 1716 struct drm_device *dev = intel_dp_to_dev(intel_dp); 1717 1718 if (intel_edp_psr_match_conditions(intel_dp) && 1719 !intel_edp_is_psr_enabled(dev)) 1720 intel_edp_psr_do_enable(intel_dp); 1721} 1722 1723void intel_edp_psr_disable(struct intel_dp *intel_dp) 1724{ 1725 struct drm_device *dev = intel_dp_to_dev(intel_dp); 1726 struct drm_i915_private *dev_priv = dev->dev_private; 1727 1728 if (!intel_edp_is_psr_enabled(dev)) 1729 return; 1730 1731 I915_WRITE(EDP_PSR_CTL(dev), 1732 I915_READ(EDP_PSR_CTL(dev)) & ~EDP_PSR_ENABLE); 1733 1734 /* Wait till PSR is idle */ 1735 if (_wait_for((I915_READ(EDP_PSR_STATUS_CTL(dev)) & 1736 EDP_PSR_STATUS_STATE_MASK) == 0, 2000, 10)) 1737 DRM_ERROR("Timed out waiting for PSR Idle State\n"); 1738} 1739 1740void intel_edp_psr_update(struct drm_device *dev) 1741{ 1742 struct intel_encoder *encoder; 1743 struct intel_dp *intel_dp = NULL; 1744 1745 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) 1746 if (encoder->type == INTEL_OUTPUT_EDP) { 1747 intel_dp = enc_to_intel_dp(&encoder->base); 1748 1749 if (!is_edp_psr(dev)) 1750 return; 1751 1752 if (!intel_edp_psr_match_conditions(intel_dp)) 1753 intel_edp_psr_disable(intel_dp); 1754 else 1755 if (!intel_edp_is_psr_enabled(dev)) 1756 intel_edp_psr_do_enable(intel_dp); 1757 } 1758} 1759 1760static void intel_disable_dp(struct intel_encoder *encoder) 1761{ 1762 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); 1763 enum port port = dp_to_dig_port(intel_dp)->port; 1764 struct drm_device *dev = encoder->base.dev; 1765 1766 /* Make sure the panel is off before trying to change the mode. But also 1767 * ensure that we have vdd while we switch off the panel. */ 1768 ironlake_edp_panel_vdd_on(intel_dp); 1769 ironlake_edp_backlight_off(intel_dp); 1770 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON); 1771 ironlake_edp_panel_off(intel_dp); 1772 1773 /* cpu edp my only be disable _after_ the cpu pipe/plane is disabled. */ 1774 if (!(port == PORT_A || IS_VALLEYVIEW(dev))) 1775 intel_dp_link_down(intel_dp); 1776} 1777 1778static void intel_post_disable_dp(struct intel_encoder *encoder) 1779{ 1780 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); 1781 enum port port = dp_to_dig_port(intel_dp)->port; 1782 struct drm_device *dev = encoder->base.dev; 1783 1784 if (port == PORT_A || IS_VALLEYVIEW(dev)) { 1785 intel_dp_link_down(intel_dp); 1786 if (!IS_VALLEYVIEW(dev)) 1787 ironlake_edp_pll_off(intel_dp); 1788 } 1789} 1790 1791static void intel_enable_dp(struct intel_encoder *encoder) 1792{ 1793 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); 1794 struct drm_device *dev = encoder->base.dev; 1795 struct drm_i915_private *dev_priv = dev->dev_private; 1796 uint32_t dp_reg = I915_READ(intel_dp->output_reg); 1797 1798 if (WARN_ON(dp_reg & DP_PORT_EN)) 1799 return; 1800 1801 ironlake_edp_panel_vdd_on(intel_dp); 1802 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON); 1803 intel_dp_start_link_train(intel_dp); 1804 ironlake_edp_panel_on(intel_dp); 1805 ironlake_edp_panel_vdd_off(intel_dp, true); 1806 intel_dp_complete_link_train(intel_dp); 1807 intel_dp_stop_link_train(intel_dp); 1808} 1809 1810static void g4x_enable_dp(struct intel_encoder *encoder) 1811{ 1812 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); 1813 1814 intel_enable_dp(encoder); 1815 ironlake_edp_backlight_on(intel_dp); 1816} 1817 1818static void vlv_enable_dp(struct intel_encoder *encoder) 1819{ 1820 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); 1821 1822 ironlake_edp_backlight_on(intel_dp); 1823} 1824 1825static void g4x_pre_enable_dp(struct intel_encoder *encoder) 1826{ 1827 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); 1828 struct intel_digital_port *dport = dp_to_dig_port(intel_dp); 1829 1830 if (dport->port == PORT_A) 1831 ironlake_edp_pll_on(intel_dp); 1832} 1833 1834static void vlv_pre_enable_dp(struct intel_encoder *encoder) 1835{ 1836 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); 1837 struct intel_digital_port *dport = dp_to_dig_port(intel_dp); 1838 struct drm_device *dev = encoder->base.dev; 1839 struct drm_i915_private *dev_priv = dev->dev_private; 1840 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc); 1841 int port = vlv_dport_to_channel(dport); 1842 int pipe = intel_crtc->pipe; 1843 struct edp_power_seq power_seq; 1844 u32 val; 1845 1846 mutex_lock(&dev_priv->dpio_lock); 1847 1848 val = vlv_dpio_read(dev_priv, pipe, DPIO_DATA_LANE_A(port)); 1849 val = 0; 1850 if (pipe) 1851 val |= (1<<21); 1852 else 1853 val &= ~(1<<21); 1854 val |= 0x001000c4; 1855 vlv_dpio_write(dev_priv, pipe, DPIO_DATA_CHANNEL(port), val); 1856 vlv_dpio_write(dev_priv, pipe, DPIO_PCS_CLOCKBUF0(port), 0x00760018); 1857 vlv_dpio_write(dev_priv, pipe, DPIO_PCS_CLOCKBUF8(port), 0x00400888); 1858 1859 mutex_unlock(&dev_priv->dpio_lock); 1860 1861 /* init power sequencer on this pipe and port */ 1862 intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq); 1863 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp, 1864 &power_seq); 1865 1866 intel_enable_dp(encoder); 1867 1868 vlv_wait_port_ready(dev_priv, port); 1869} 1870 1871static void vlv_dp_pre_pll_enable(struct intel_encoder *encoder) 1872{ 1873 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base); 1874 struct drm_device *dev = encoder->base.dev; 1875 struct drm_i915_private *dev_priv = dev->dev_private; 1876 struct intel_crtc *intel_crtc = 1877 to_intel_crtc(encoder->base.crtc); 1878 int port = vlv_dport_to_channel(dport); 1879 int pipe = intel_crtc->pipe; 1880 1881 /* Program Tx lane resets to default */ 1882 mutex_lock(&dev_priv->dpio_lock); 1883 vlv_dpio_write(dev_priv, pipe, DPIO_PCS_TX(port), 1884 DPIO_PCS_TX_LANE2_RESET | 1885 DPIO_PCS_TX_LANE1_RESET); 1886 vlv_dpio_write(dev_priv, pipe, DPIO_PCS_CLK(port), 1887 DPIO_PCS_CLK_CRI_RXEB_EIOS_EN | 1888 DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN | 1889 (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT) | 1890 DPIO_PCS_CLK_SOFT_RESET); 1891 1892 /* Fix up inter-pair skew failure */ 1893 vlv_dpio_write(dev_priv, pipe, DPIO_PCS_STAGGER1(port), 0x00750f00); 1894 vlv_dpio_write(dev_priv, pipe, DPIO_TX_CTL(port), 0x00001500); 1895 vlv_dpio_write(dev_priv, pipe, DPIO_TX_LANE(port), 0x40400000); 1896 mutex_unlock(&dev_priv->dpio_lock); 1897} 1898 1899/* 1900 * Native read with retry for link status and receiver capability reads for 1901 * cases where the sink may still be asleep. 1902 */ 1903static bool 1904intel_dp_aux_native_read_retry(struct intel_dp *intel_dp, uint16_t address, 1905 uint8_t *recv, int recv_bytes) 1906{ 1907 int ret, i; 1908 1909 /* 1910 * Sinks are *supposed* to come up within 1ms from an off state, 1911 * but we're also supposed to retry 3 times per the spec. 1912 */ 1913 for (i = 0; i < 3; i++) { 1914 ret = intel_dp_aux_native_read(intel_dp, address, recv, 1915 recv_bytes); 1916 if (ret == recv_bytes) 1917 return true; 1918 msleep(1); 1919 } 1920 1921 return false; 1922} 1923 1924/* 1925 * Fetch AUX CH registers 0x202 - 0x207 which contain 1926 * link status information 1927 */ 1928static bool 1929intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE]) 1930{ 1931 return intel_dp_aux_native_read_retry(intel_dp, 1932 DP_LANE0_1_STATUS, 1933 link_status, 1934 DP_LINK_STATUS_SIZE); 1935} 1936 1937#if 0 1938static char *voltage_names[] = { 1939 "0.4V", "0.6V", "0.8V", "1.2V" 1940}; 1941static char *pre_emph_names[] = { 1942 "0dB", "3.5dB", "6dB", "9.5dB" 1943}; 1944static char *link_train_names[] = { 1945 "pattern 1", "pattern 2", "idle", "off" 1946}; 1947#endif 1948 1949/* 1950 * These are source-specific values; current Intel hardware supports 1951 * a maximum voltage of 800mV and a maximum pre-emphasis of 6dB 1952 */ 1953 1954static uint8_t 1955intel_dp_voltage_max(struct intel_dp *intel_dp) 1956{ 1957 struct drm_device *dev = intel_dp_to_dev(intel_dp); 1958 enum port port = dp_to_dig_port(intel_dp)->port; 1959 1960 if (IS_VALLEYVIEW(dev)) 1961 return DP_TRAIN_VOLTAGE_SWING_1200; 1962 else if (IS_GEN7(dev) && port == PORT_A) 1963 return DP_TRAIN_VOLTAGE_SWING_800; 1964 else if (HAS_PCH_CPT(dev) && port != PORT_A) 1965 return DP_TRAIN_VOLTAGE_SWING_1200; 1966 else 1967 return DP_TRAIN_VOLTAGE_SWING_800; 1968} 1969 1970static uint8_t 1971intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing) 1972{ 1973 struct drm_device *dev = intel_dp_to_dev(intel_dp); 1974 enum port port = dp_to_dig_port(intel_dp)->port; 1975 1976 if (HAS_DDI(dev)) { 1977 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) { 1978 case DP_TRAIN_VOLTAGE_SWING_400: 1979 return DP_TRAIN_PRE_EMPHASIS_9_5; 1980 case DP_TRAIN_VOLTAGE_SWING_600: 1981 return DP_TRAIN_PRE_EMPHASIS_6; 1982 case DP_TRAIN_VOLTAGE_SWING_800: 1983 return DP_TRAIN_PRE_EMPHASIS_3_5; 1984 case DP_TRAIN_VOLTAGE_SWING_1200: 1985 default: 1986 return DP_TRAIN_PRE_EMPHASIS_0; 1987 } 1988 } else if (IS_VALLEYVIEW(dev)) { 1989 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) { 1990 case DP_TRAIN_VOLTAGE_SWING_400: 1991 return DP_TRAIN_PRE_EMPHASIS_9_5; 1992 case DP_TRAIN_VOLTAGE_SWING_600: 1993 return DP_TRAIN_PRE_EMPHASIS_6; 1994 case DP_TRAIN_VOLTAGE_SWING_800: 1995 return DP_TRAIN_PRE_EMPHASIS_3_5; 1996 case DP_TRAIN_VOLTAGE_SWING_1200: 1997 default: 1998 return DP_TRAIN_PRE_EMPHASIS_0; 1999 } 2000 } else if (IS_GEN7(dev) && port == PORT_A) { 2001 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) { 2002 case DP_TRAIN_VOLTAGE_SWING_400: 2003 return DP_TRAIN_PRE_EMPHASIS_6; 2004 case DP_TRAIN_VOLTAGE_SWING_600: 2005 case DP_TRAIN_VOLTAGE_SWING_800: 2006 return DP_TRAIN_PRE_EMPHASIS_3_5; 2007 default: 2008 return DP_TRAIN_PRE_EMPHASIS_0; 2009 } 2010 } else { 2011 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) { 2012 case DP_TRAIN_VOLTAGE_SWING_400: 2013 return DP_TRAIN_PRE_EMPHASIS_6; 2014 case DP_TRAIN_VOLTAGE_SWING_600: 2015 return DP_TRAIN_PRE_EMPHASIS_6; 2016 case DP_TRAIN_VOLTAGE_SWING_800: 2017 return DP_TRAIN_PRE_EMPHASIS_3_5; 2018 case DP_TRAIN_VOLTAGE_SWING_1200: 2019 default: 2020 return DP_TRAIN_PRE_EMPHASIS_0; 2021 } 2022 } 2023} 2024 2025static uint32_t intel_vlv_signal_levels(struct intel_dp *intel_dp) 2026{ 2027 struct drm_device *dev = intel_dp_to_dev(intel_dp); 2028 struct drm_i915_private *dev_priv = dev->dev_private; 2029 struct intel_digital_port *dport = dp_to_dig_port(intel_dp); 2030 struct intel_crtc *intel_crtc = 2031 to_intel_crtc(dport->base.base.crtc); 2032 unsigned long demph_reg_value, preemph_reg_value, 2033 uniqtranscale_reg_value; 2034 uint8_t train_set = intel_dp->train_set[0]; 2035 int port = vlv_dport_to_channel(dport); 2036 int pipe = intel_crtc->pipe; 2037 2038 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) { 2039 case DP_TRAIN_PRE_EMPHASIS_0: 2040 preemph_reg_value = 0x0004000; 2041 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { 2042 case DP_TRAIN_VOLTAGE_SWING_400: 2043 demph_reg_value = 0x2B405555; 2044 uniqtranscale_reg_value = 0x552AB83A; 2045 break; 2046 case DP_TRAIN_VOLTAGE_SWING_600: 2047 demph_reg_value = 0x2B404040; 2048 uniqtranscale_reg_value = 0x5548B83A; 2049 break; 2050 case DP_TRAIN_VOLTAGE_SWING_800: 2051 demph_reg_value = 0x2B245555; 2052 uniqtranscale_reg_value = 0x5560B83A; 2053 break; 2054 case DP_TRAIN_VOLTAGE_SWING_1200: 2055 demph_reg_value = 0x2B405555; 2056 uniqtranscale_reg_value = 0x5598DA3A; 2057 break; 2058 default: 2059 return 0; 2060 } 2061 break; 2062 case DP_TRAIN_PRE_EMPHASIS_3_5: 2063 preemph_reg_value = 0x0002000; 2064 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { 2065 case DP_TRAIN_VOLTAGE_SWING_400: 2066 demph_reg_value = 0x2B404040; 2067 uniqtranscale_reg_value = 0x5552B83A; 2068 break; 2069 case DP_TRAIN_VOLTAGE_SWING_600: 2070 demph_reg_value = 0x2B404848; 2071 uniqtranscale_reg_value = 0x5580B83A; 2072 break; 2073 case DP_TRAIN_VOLTAGE_SWING_800: 2074 demph_reg_value = 0x2B404040; 2075 uniqtranscale_reg_value = 0x55ADDA3A; 2076 break; 2077 default: 2078 return 0; 2079 } 2080 break; 2081 case DP_TRAIN_PRE_EMPHASIS_6: 2082 preemph_reg_value = 0x0000000; 2083 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { 2084 case DP_TRAIN_VOLTAGE_SWING_400: 2085 demph_reg_value = 0x2B305555; 2086 uniqtranscale_reg_value = 0x5570B83A; 2087 break; 2088 case DP_TRAIN_VOLTAGE_SWING_600: 2089 demph_reg_value = 0x2B2B4040; 2090 uniqtranscale_reg_value = 0x55ADDA3A; 2091 break; 2092 default: 2093 return 0; 2094 } 2095 break; 2096 case DP_TRAIN_PRE_EMPHASIS_9_5: 2097 preemph_reg_value = 0x0006000; 2098 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { 2099 case DP_TRAIN_VOLTAGE_SWING_400: 2100 demph_reg_value = 0x1B405555; 2101 uniqtranscale_reg_value = 0x55ADDA3A; 2102 break; 2103 default: 2104 return 0; 2105 } 2106 break; 2107 default: 2108 return 0; 2109 } 2110 2111 mutex_lock(&dev_priv->dpio_lock); 2112 vlv_dpio_write(dev_priv, pipe, DPIO_TX_OCALINIT(port), 0x00000000); 2113 vlv_dpio_write(dev_priv, pipe, DPIO_TX_SWING_CTL4(port), demph_reg_value); 2114 vlv_dpio_write(dev_priv, pipe, DPIO_TX_SWING_CTL2(port), 2115 uniqtranscale_reg_value); 2116 vlv_dpio_write(dev_priv, pipe, DPIO_TX_SWING_CTL3(port), 0x0C782040); 2117 vlv_dpio_write(dev_priv, pipe, DPIO_PCS_STAGGER0(port), 0x00030000); 2118 vlv_dpio_write(dev_priv, pipe, DPIO_PCS_CTL_OVER1(port), preemph_reg_value); 2119 vlv_dpio_write(dev_priv, pipe, DPIO_TX_OCALINIT(port), 0x80000000); 2120 mutex_unlock(&dev_priv->dpio_lock); 2121 2122 return 0; 2123} 2124 2125static void 2126intel_get_adjust_train(struct intel_dp *intel_dp, 2127 const uint8_t link_status[DP_LINK_STATUS_SIZE]) 2128{ 2129 uint8_t v = 0; 2130 uint8_t p = 0; 2131 int lane; 2132 uint8_t voltage_max; 2133 uint8_t preemph_max; 2134 2135 for (lane = 0; lane < intel_dp->lane_count; lane++) { 2136 uint8_t this_v = drm_dp_get_adjust_request_voltage(link_status, lane); 2137 uint8_t this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane); 2138 2139 if (this_v > v) 2140 v = this_v; 2141 if (this_p > p) 2142 p = this_p; 2143 } 2144 2145 voltage_max = intel_dp_voltage_max(intel_dp); 2146 if (v >= voltage_max) 2147 v = voltage_max | DP_TRAIN_MAX_SWING_REACHED; 2148 2149 preemph_max = intel_dp_pre_emphasis_max(intel_dp, v); 2150 if (p >= preemph_max) 2151 p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED; 2152 2153 for (lane = 0; lane < 4; lane++) 2154 intel_dp->train_set[lane] = v | p; 2155} 2156 2157static uint32_t 2158intel_gen4_signal_levels(uint8_t train_set) 2159{ 2160 uint32_t signal_levels = 0; 2161 2162 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { 2163 case DP_TRAIN_VOLTAGE_SWING_400: 2164 default: 2165 signal_levels |= DP_VOLTAGE_0_4; 2166 break; 2167 case DP_TRAIN_VOLTAGE_SWING_600: 2168 signal_levels |= DP_VOLTAGE_0_6; 2169 break; 2170 case DP_TRAIN_VOLTAGE_SWING_800: 2171 signal_levels |= DP_VOLTAGE_0_8; 2172 break; 2173 case DP_TRAIN_VOLTAGE_SWING_1200: 2174 signal_levels |= DP_VOLTAGE_1_2; 2175 break; 2176 } 2177 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) { 2178 case DP_TRAIN_PRE_EMPHASIS_0: 2179 default: 2180 signal_levels |= DP_PRE_EMPHASIS_0; 2181 break; 2182 case DP_TRAIN_PRE_EMPHASIS_3_5: 2183 signal_levels |= DP_PRE_EMPHASIS_3_5; 2184 break; 2185 case DP_TRAIN_PRE_EMPHASIS_6: 2186 signal_levels |= DP_PRE_EMPHASIS_6; 2187 break; 2188 case DP_TRAIN_PRE_EMPHASIS_9_5: 2189 signal_levels |= DP_PRE_EMPHASIS_9_5; 2190 break; 2191 } 2192 return signal_levels; 2193} 2194 2195/* Gen6's DP voltage swing and pre-emphasis control */ 2196static uint32_t 2197intel_gen6_edp_signal_levels(uint8_t train_set) 2198{ 2199 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK | 2200 DP_TRAIN_PRE_EMPHASIS_MASK); 2201 switch (signal_levels) { 2202 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0: 2203 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0: 2204 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B; 2205 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5: 2206 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B; 2207 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6: 2208 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6: 2209 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B; 2210 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5: 2211 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5: 2212 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B; 2213 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0: 2214 case DP_TRAIN_VOLTAGE_SWING_1200 | DP_TRAIN_PRE_EMPHASIS_0: 2215 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B; 2216 default: 2217 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:" 2218 "0x%x\n", signal_levels); 2219 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B; 2220 } 2221} 2222 2223/* Gen7's DP voltage swing and pre-emphasis control */ 2224static uint32_t 2225intel_gen7_edp_signal_levels(uint8_t train_set) 2226{ 2227 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK | 2228 DP_TRAIN_PRE_EMPHASIS_MASK); 2229 switch (signal_levels) { 2230 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0: 2231 return EDP_LINK_TRAIN_400MV_0DB_IVB; 2232 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5: 2233 return EDP_LINK_TRAIN_400MV_3_5DB_IVB; 2234 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6: 2235 return EDP_LINK_TRAIN_400MV_6DB_IVB; 2236 2237 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0: 2238 return EDP_LINK_TRAIN_600MV_0DB_IVB; 2239 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5: 2240 return EDP_LINK_TRAIN_600MV_3_5DB_IVB; 2241 2242 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0: 2243 return EDP_LINK_TRAIN_800MV_0DB_IVB; 2244 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5: 2245 return EDP_LINK_TRAIN_800MV_3_5DB_IVB; 2246 2247 default: 2248 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:" 2249 "0x%x\n", signal_levels); 2250 return EDP_LINK_TRAIN_500MV_0DB_IVB; 2251 } 2252} 2253 2254/* Gen7.5's (HSW) DP voltage swing and pre-emphasis control */ 2255static uint32_t 2256intel_hsw_signal_levels(uint8_t train_set) 2257{ 2258 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK | 2259 DP_TRAIN_PRE_EMPHASIS_MASK); 2260 switch (signal_levels) { 2261 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0: 2262 return DDI_BUF_EMP_400MV_0DB_HSW; 2263 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5: 2264 return DDI_BUF_EMP_400MV_3_5DB_HSW; 2265 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6: 2266 return DDI_BUF_EMP_400MV_6DB_HSW; 2267 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_9_5: 2268 return DDI_BUF_EMP_400MV_9_5DB_HSW; 2269 2270 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0: 2271 return DDI_BUF_EMP_600MV_0DB_HSW; 2272 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5: 2273 return DDI_BUF_EMP_600MV_3_5DB_HSW; 2274 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6: 2275 return DDI_BUF_EMP_600MV_6DB_HSW; 2276 2277 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0: 2278 return DDI_BUF_EMP_800MV_0DB_HSW; 2279 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5: 2280 return DDI_BUF_EMP_800MV_3_5DB_HSW; 2281 default: 2282 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:" 2283 "0x%x\n", signal_levels); 2284 return DDI_BUF_EMP_400MV_0DB_HSW; 2285 } 2286} 2287 2288/* Properly updates "DP" with the correct signal levels. */ 2289static void 2290intel_dp_set_signal_levels(struct intel_dp *intel_dp, uint32_t *DP) 2291{ 2292 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 2293 enum port port = intel_dig_port->port; 2294 struct drm_device *dev = intel_dig_port->base.base.dev; 2295 uint32_t signal_levels, mask; 2296 uint8_t train_set = intel_dp->train_set[0]; 2297 2298 if (HAS_DDI(dev)) { 2299 signal_levels = intel_hsw_signal_levels(train_set); 2300 mask = DDI_BUF_EMP_MASK; 2301 } else if (IS_VALLEYVIEW(dev)) { 2302 signal_levels = intel_vlv_signal_levels(intel_dp); 2303 mask = 0; 2304 } else if (IS_GEN7(dev) && port == PORT_A) { 2305 signal_levels = intel_gen7_edp_signal_levels(train_set); 2306 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_IVB; 2307 } else if (IS_GEN6(dev) && port == PORT_A) { 2308 signal_levels = intel_gen6_edp_signal_levels(train_set); 2309 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB; 2310 } else { 2311 signal_levels = intel_gen4_signal_levels(train_set); 2312 mask = DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK; 2313 } 2314 2315 DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels); 2316 2317 *DP = (*DP & ~mask) | signal_levels; 2318} 2319 2320static bool 2321intel_dp_set_link_train(struct intel_dp *intel_dp, 2322 uint32_t *DP, 2323 uint8_t dp_train_pat) 2324{ 2325 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 2326 struct drm_device *dev = intel_dig_port->base.base.dev; 2327 struct drm_i915_private *dev_priv = dev->dev_private; 2328 enum port port = intel_dig_port->port; 2329 uint8_t buf[sizeof(intel_dp->train_set) + 1]; 2330 int ret, len; 2331 2332 if (HAS_DDI(dev)) { 2333 uint32_t temp = I915_READ(DP_TP_CTL(port)); 2334 2335 if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE) 2336 temp |= DP_TP_CTL_SCRAMBLE_DISABLE; 2337 else 2338 temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE; 2339 2340 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK; 2341 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) { 2342 case DP_TRAINING_PATTERN_DISABLE: 2343 temp |= DP_TP_CTL_LINK_TRAIN_NORMAL; 2344 2345 break; 2346 case DP_TRAINING_PATTERN_1: 2347 temp |= DP_TP_CTL_LINK_TRAIN_PAT1; 2348 break; 2349 case DP_TRAINING_PATTERN_2: 2350 temp |= DP_TP_CTL_LINK_TRAIN_PAT2; 2351 break; 2352 case DP_TRAINING_PATTERN_3: 2353 temp |= DP_TP_CTL_LINK_TRAIN_PAT3; 2354 break; 2355 } 2356 I915_WRITE(DP_TP_CTL(port), temp); 2357 2358 } else if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) { 2359 *DP &= ~DP_LINK_TRAIN_MASK_CPT; 2360 2361 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) { 2362 case DP_TRAINING_PATTERN_DISABLE: 2363 *DP |= DP_LINK_TRAIN_OFF_CPT; 2364 break; 2365 case DP_TRAINING_PATTERN_1: 2366 *DP |= DP_LINK_TRAIN_PAT_1_CPT; 2367 break; 2368 case DP_TRAINING_PATTERN_2: 2369 *DP |= DP_LINK_TRAIN_PAT_2_CPT; 2370 break; 2371 case DP_TRAINING_PATTERN_3: 2372 DRM_ERROR("DP training pattern 3 not supported\n"); 2373 *DP |= DP_LINK_TRAIN_PAT_2_CPT; 2374 break; 2375 } 2376 2377 } else { 2378 *DP &= ~DP_LINK_TRAIN_MASK; 2379 2380 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) { 2381 case DP_TRAINING_PATTERN_DISABLE: 2382 *DP |= DP_LINK_TRAIN_OFF; 2383 break; 2384 case DP_TRAINING_PATTERN_1: 2385 *DP |= DP_LINK_TRAIN_PAT_1; 2386 break; 2387 case DP_TRAINING_PATTERN_2: 2388 *DP |= DP_LINK_TRAIN_PAT_2; 2389 break; 2390 case DP_TRAINING_PATTERN_3: 2391 DRM_ERROR("DP training pattern 3 not supported\n"); 2392 *DP |= DP_LINK_TRAIN_PAT_2; 2393 break; 2394 } 2395 } 2396 2397 I915_WRITE(intel_dp->output_reg, *DP); 2398 POSTING_READ(intel_dp->output_reg); 2399 2400 buf[0] = dp_train_pat; 2401 if ((dp_train_pat & DP_TRAINING_PATTERN_MASK) == 2402 DP_TRAINING_PATTERN_DISABLE) { 2403 /* don't write DP_TRAINING_LANEx_SET on disable */ 2404 len = 1; 2405 } else { 2406 /* DP_TRAINING_LANEx_SET follow DP_TRAINING_PATTERN_SET */ 2407 memcpy(buf + 1, intel_dp->train_set, intel_dp->lane_count); 2408 len = intel_dp->lane_count + 1; 2409 } 2410 2411 ret = intel_dp_aux_native_write(intel_dp, DP_TRAINING_PATTERN_SET, 2412 buf, len); 2413 2414 return ret == len; 2415} 2416 2417static bool 2418intel_dp_reset_link_train(struct intel_dp *intel_dp, uint32_t *DP, 2419 uint8_t dp_train_pat) 2420{ 2421 memset(intel_dp->train_set, 0, sizeof(intel_dp->train_set)); 2422 intel_dp_set_signal_levels(intel_dp, DP); 2423 return intel_dp_set_link_train(intel_dp, DP, dp_train_pat); 2424} 2425 2426static bool 2427intel_dp_update_link_train(struct intel_dp *intel_dp, uint32_t *DP, 2428 const uint8_t link_status[DP_LINK_STATUS_SIZE]) 2429{ 2430 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 2431 struct drm_device *dev = intel_dig_port->base.base.dev; 2432 struct drm_i915_private *dev_priv = dev->dev_private; 2433 int ret; 2434 2435 intel_get_adjust_train(intel_dp, link_status); 2436 intel_dp_set_signal_levels(intel_dp, DP); 2437 2438 I915_WRITE(intel_dp->output_reg, *DP); 2439 POSTING_READ(intel_dp->output_reg); 2440 2441 ret = intel_dp_aux_native_write(intel_dp, DP_TRAINING_LANE0_SET, 2442 intel_dp->train_set, 2443 intel_dp->lane_count); 2444 2445 return ret == intel_dp->lane_count; 2446} 2447 2448static void intel_dp_set_idle_link_train(struct intel_dp *intel_dp) 2449{ 2450 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 2451 struct drm_device *dev = intel_dig_port->base.base.dev; 2452 struct drm_i915_private *dev_priv = dev->dev_private; 2453 enum port port = intel_dig_port->port; 2454 uint32_t val; 2455 2456 if (!HAS_DDI(dev)) 2457 return; 2458 2459 val = I915_READ(DP_TP_CTL(port)); 2460 val &= ~DP_TP_CTL_LINK_TRAIN_MASK; 2461 val |= DP_TP_CTL_LINK_TRAIN_IDLE; 2462 I915_WRITE(DP_TP_CTL(port), val); 2463 2464 /* 2465 * On PORT_A we can have only eDP in SST mode. There the only reason 2466 * we need to set idle transmission mode is to work around a HW issue 2467 * where we enable the pipe while not in idle link-training mode. 2468 * In this case there is requirement to wait for a minimum number of 2469 * idle patterns to be sent. 2470 */ 2471 if (port == PORT_A) 2472 return; 2473 2474 if (wait_for((I915_READ(DP_TP_STATUS(port)) & DP_TP_STATUS_IDLE_DONE), 2475 1)) 2476 DRM_ERROR("Timed out waiting for DP idle patterns\n"); 2477} 2478 2479/* Enable corresponding port and start training pattern 1 */ 2480void 2481intel_dp_start_link_train(struct intel_dp *intel_dp) 2482{ 2483 struct drm_encoder *encoder = &dp_to_dig_port(intel_dp)->base.base; 2484 struct drm_device *dev = encoder->dev; 2485 int i; 2486 uint8_t voltage; 2487 int voltage_tries, loop_tries; 2488 uint32_t DP = intel_dp->DP; 2489 uint8_t link_config[2]; 2490 2491 if (HAS_DDI(dev)) 2492 intel_ddi_prepare_link_retrain(encoder); 2493 2494 /* Write the link configuration data */ 2495 link_config[0] = intel_dp->link_bw; 2496 link_config[1] = intel_dp->lane_count; 2497 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd)) 2498 link_config[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN; 2499 intel_dp_aux_native_write(intel_dp, DP_LINK_BW_SET, link_config, 2); 2500 2501 link_config[0] = 0; 2502 link_config[1] = DP_SET_ANSI_8B10B; 2503 intel_dp_aux_native_write(intel_dp, DP_DOWNSPREAD_CTRL, link_config, 2); 2504 2505 DP |= DP_PORT_EN; 2506 2507 /* clock recovery */ 2508 if (!intel_dp_reset_link_train(intel_dp, &DP, 2509 DP_TRAINING_PATTERN_1 | 2510 DP_LINK_SCRAMBLING_DISABLE)) { 2511 DRM_ERROR("failed to enable link training\n"); 2512 return; 2513 } 2514 2515 voltage = 0xff; 2516 voltage_tries = 0; 2517 loop_tries = 0; 2518 for (;;) { 2519 uint8_t link_status[DP_LINK_STATUS_SIZE]; 2520 2521 drm_dp_link_train_clock_recovery_delay(intel_dp->dpcd); 2522 if (!intel_dp_get_link_status(intel_dp, link_status)) { 2523 DRM_ERROR("failed to get link status\n"); 2524 break; 2525 } 2526 2527 if (drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) { 2528 DRM_DEBUG_KMS("clock recovery OK\n"); 2529 break; 2530 } 2531 2532 /* Check to see if we've tried the max voltage */ 2533 for (i = 0; i < intel_dp->lane_count; i++) 2534 if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0) 2535 break; 2536 if (i == intel_dp->lane_count) { 2537 ++loop_tries; 2538 if (loop_tries == 5) { 2539 DRM_ERROR("too many full retries, give up\n"); 2540 break; 2541 } 2542 intel_dp_reset_link_train(intel_dp, &DP, 2543 DP_TRAINING_PATTERN_1 | 2544 DP_LINK_SCRAMBLING_DISABLE); 2545 voltage_tries = 0; 2546 continue; 2547 } 2548 2549 /* Check to see if we've tried the same voltage 5 times */ 2550 if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) { 2551 ++voltage_tries; 2552 if (voltage_tries == 5) { 2553 DRM_ERROR("too many voltage retries, give up\n"); 2554 break; 2555 } 2556 } else 2557 voltage_tries = 0; 2558 voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK; 2559 2560 /* Update training set as requested by target */ 2561 if (!intel_dp_update_link_train(intel_dp, &DP, link_status)) { 2562 DRM_ERROR("failed to update link training\n"); 2563 break; 2564 } 2565 } 2566 2567 intel_dp->DP = DP; 2568} 2569 2570void 2571intel_dp_complete_link_train(struct intel_dp *intel_dp) 2572{ 2573 bool channel_eq = false; 2574 int tries, cr_tries; 2575 uint32_t DP = intel_dp->DP; 2576 2577 /* channel equalization */ 2578 if (!intel_dp_set_link_train(intel_dp, &DP, 2579 DP_TRAINING_PATTERN_2 | 2580 DP_LINK_SCRAMBLING_DISABLE)) { 2581 DRM_ERROR("failed to start channel equalization\n"); 2582 return; 2583 } 2584 2585 tries = 0; 2586 cr_tries = 0; 2587 channel_eq = false; 2588 for (;;) { 2589 uint8_t link_status[DP_LINK_STATUS_SIZE]; 2590 2591 if (cr_tries > 5) { 2592 DRM_ERROR("failed to train DP, aborting\n"); 2593 intel_dp_link_down(intel_dp); 2594 break; 2595 } 2596 2597 drm_dp_link_train_channel_eq_delay(intel_dp->dpcd); 2598 if (!intel_dp_get_link_status(intel_dp, link_status)) { 2599 DRM_ERROR("failed to get link status\n"); 2600 break; 2601 } 2602 2603 /* Make sure clock is still ok */ 2604 if (!drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) { 2605 intel_dp_start_link_train(intel_dp); 2606 intel_dp_set_link_train(intel_dp, &DP, 2607 DP_TRAINING_PATTERN_2 | 2608 DP_LINK_SCRAMBLING_DISABLE); 2609 cr_tries++; 2610 continue; 2611 } 2612 2613 if (drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) { 2614 channel_eq = true; 2615 break; 2616 } 2617 2618 /* Try 5 times, then try clock recovery if that fails */ 2619 if (tries > 5) { 2620 intel_dp_link_down(intel_dp); 2621 intel_dp_start_link_train(intel_dp); 2622 intel_dp_set_link_train(intel_dp, &DP, 2623 DP_TRAINING_PATTERN_2 | 2624 DP_LINK_SCRAMBLING_DISABLE); 2625 tries = 0; 2626 cr_tries++; 2627 continue; 2628 } 2629 2630 /* Update training set as requested by target */ 2631 if (!intel_dp_update_link_train(intel_dp, &DP, link_status)) { 2632 DRM_ERROR("failed to update link training\n"); 2633 break; 2634 } 2635 ++tries; 2636 } 2637 2638 intel_dp_set_idle_link_train(intel_dp); 2639 2640 intel_dp->DP = DP; 2641 2642 if (channel_eq) 2643 DRM_DEBUG_KMS("Channel EQ done. DP Training successful\n"); 2644 2645} 2646 2647void intel_dp_stop_link_train(struct intel_dp *intel_dp) 2648{ 2649 intel_dp_set_link_train(intel_dp, &intel_dp->DP, 2650 DP_TRAINING_PATTERN_DISABLE); 2651} 2652 2653static void 2654intel_dp_link_down(struct intel_dp *intel_dp) 2655{ 2656 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 2657 enum port port = intel_dig_port->port; 2658 struct drm_device *dev = intel_dig_port->base.base.dev; 2659 struct drm_i915_private *dev_priv = dev->dev_private; 2660 struct intel_crtc *intel_crtc = 2661 to_intel_crtc(intel_dig_port->base.base.crtc); 2662 uint32_t DP = intel_dp->DP; 2663 2664 /* 2665 * DDI code has a strict mode set sequence and we should try to respect 2666 * it, otherwise we might hang the machine in many different ways. So we 2667 * really should be disabling the port only on a complete crtc_disable 2668 * sequence. This function is just called under two conditions on DDI 2669 * code: 2670 * - Link train failed while doing crtc_enable, and on this case we 2671 * really should respect the mode set sequence and wait for a 2672 * crtc_disable. 2673 * - Someone turned the monitor off and intel_dp_check_link_status 2674 * called us. We don't need to disable the whole port on this case, so 2675 * when someone turns the monitor on again, 2676 * intel_ddi_prepare_link_retrain will take care of redoing the link 2677 * train. 2678 */ 2679 if (HAS_DDI(dev)) 2680 return; 2681 2682 if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0)) 2683 return; 2684 2685 DRM_DEBUG_KMS("\n"); 2686 2687 if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) { 2688 DP &= ~DP_LINK_TRAIN_MASK_CPT; 2689 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT); 2690 } else { 2691 DP &= ~DP_LINK_TRAIN_MASK; 2692 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE); 2693 } 2694 POSTING_READ(intel_dp->output_reg); 2695 2696 /* We don't really know why we're doing this */ 2697 intel_wait_for_vblank(dev, intel_crtc->pipe); 2698 2699 if (HAS_PCH_IBX(dev) && 2700 I915_READ(intel_dp->output_reg) & DP_PIPEB_SELECT) { 2701 struct drm_crtc *crtc = intel_dig_port->base.base.crtc; 2702 2703 /* Hardware workaround: leaving our transcoder select 2704 * set to transcoder B while it's off will prevent the 2705 * corresponding HDMI output on transcoder A. 2706 * 2707 * Combine this with another hardware workaround: 2708 * transcoder select bit can only be cleared while the 2709 * port is enabled. 2710 */ 2711 DP &= ~DP_PIPEB_SELECT; 2712 I915_WRITE(intel_dp->output_reg, DP); 2713 2714 /* Changes to enable or select take place the vblank 2715 * after being written. 2716 */ 2717 if (WARN_ON(crtc == NULL)) { 2718 /* We should never try to disable a port without a crtc 2719 * attached. For paranoia keep the code around for a 2720 * bit. */ 2721 POSTING_READ(intel_dp->output_reg); 2722 msleep(50); 2723 } else 2724 intel_wait_for_vblank(dev, intel_crtc->pipe); 2725 } 2726 2727 DP &= ~DP_AUDIO_OUTPUT_ENABLE; 2728 I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN); 2729 POSTING_READ(intel_dp->output_reg); 2730 msleep(intel_dp->panel_power_down_delay); 2731} 2732 2733static bool 2734intel_dp_get_dpcd(struct intel_dp *intel_dp) 2735{ 2736 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 2737 struct drm_device *dev = dig_port->base.base.dev; 2738 struct drm_i915_private *dev_priv = dev->dev_private; 2739 2740 char dpcd_hex_dump[sizeof(intel_dp->dpcd) * 3]; 2741 2742 if (intel_dp_aux_native_read_retry(intel_dp, 0x000, intel_dp->dpcd, 2743 sizeof(intel_dp->dpcd)) == 0) 2744 return false; /* aux transfer failed */ 2745 2746 hex_dump_to_buffer(intel_dp->dpcd, sizeof(intel_dp->dpcd), 2747 32, 1, dpcd_hex_dump, sizeof(dpcd_hex_dump), false); 2748 DRM_DEBUG_KMS("DPCD: %s\n", dpcd_hex_dump); 2749 2750 if (intel_dp->dpcd[DP_DPCD_REV] == 0) 2751 return false; /* DPCD not present */ 2752 2753 /* Check if the panel supports PSR */ 2754 memset(intel_dp->psr_dpcd, 0, sizeof(intel_dp->psr_dpcd)); 2755 if (is_edp(intel_dp)) { 2756 intel_dp_aux_native_read_retry(intel_dp, DP_PSR_SUPPORT, 2757 intel_dp->psr_dpcd, 2758 sizeof(intel_dp->psr_dpcd)); 2759 if (intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED) { 2760 dev_priv->psr.sink_support = true; 2761 DRM_DEBUG_KMS("Detected EDP PSR Panel.\n"); 2762 } 2763 } 2764 2765 if (!(intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] & 2766 DP_DWN_STRM_PORT_PRESENT)) 2767 return true; /* native DP sink */ 2768 2769 if (intel_dp->dpcd[DP_DPCD_REV] == 0x10) 2770 return true; /* no per-port downstream info */ 2771 2772 if (intel_dp_aux_native_read_retry(intel_dp, DP_DOWNSTREAM_PORT_0, 2773 intel_dp->downstream_ports, 2774 DP_MAX_DOWNSTREAM_PORTS) == 0) 2775 return false; /* downstream port status fetch failed */ 2776 2777 return true; 2778} 2779 2780static void 2781intel_dp_probe_oui(struct intel_dp *intel_dp) 2782{ 2783 u8 buf[3]; 2784 2785 if (!(intel_dp->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT)) 2786 return; 2787 2788 ironlake_edp_panel_vdd_on(intel_dp); 2789 2790 if (intel_dp_aux_native_read_retry(intel_dp, DP_SINK_OUI, buf, 3)) 2791 DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n", 2792 buf[0], buf[1], buf[2]); 2793 2794 if (intel_dp_aux_native_read_retry(intel_dp, DP_BRANCH_OUI, buf, 3)) 2795 DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n", 2796 buf[0], buf[1], buf[2]); 2797 2798 ironlake_edp_panel_vdd_off(intel_dp, false); 2799} 2800 2801static bool 2802intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector) 2803{ 2804 int ret; 2805 2806 ret = intel_dp_aux_native_read_retry(intel_dp, 2807 DP_DEVICE_SERVICE_IRQ_VECTOR, 2808 sink_irq_vector, 1); 2809 if (!ret) 2810 return false; 2811 2812 return true; 2813} 2814 2815static void 2816intel_dp_handle_test_request(struct intel_dp *intel_dp) 2817{ 2818 /* NAK by default */ 2819 intel_dp_aux_native_write_1(intel_dp, DP_TEST_RESPONSE, DP_TEST_NAK); 2820} 2821 2822/* 2823 * According to DP spec 2824 * 5.1.2: 2825 * 1. Read DPCD 2826 * 2. Configure link according to Receiver Capabilities 2827 * 3. Use Link Training from 2.5.3.3 and 3.5.1.3 2828 * 4. Check link status on receipt of hot-plug interrupt 2829 */ 2830 2831void 2832intel_dp_check_link_status(struct intel_dp *intel_dp) 2833{ 2834 struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base; 2835 u8 sink_irq_vector; 2836 u8 link_status[DP_LINK_STATUS_SIZE]; 2837 2838 if (!intel_encoder->connectors_active) 2839 return; 2840 2841 if (WARN_ON(!intel_encoder->base.crtc)) 2842 return; 2843 2844 /* Try to read receiver status if the link appears to be up */ 2845 if (!intel_dp_get_link_status(intel_dp, link_status)) { 2846 intel_dp_link_down(intel_dp); 2847 return; 2848 } 2849 2850 /* Now read the DPCD to see if it's actually running */ 2851 if (!intel_dp_get_dpcd(intel_dp)) { 2852 intel_dp_link_down(intel_dp); 2853 return; 2854 } 2855 2856 /* Try to read the source of the interrupt */ 2857 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 && 2858 intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) { 2859 /* Clear interrupt source */ 2860 intel_dp_aux_native_write_1(intel_dp, 2861 DP_DEVICE_SERVICE_IRQ_VECTOR, 2862 sink_irq_vector); 2863 2864 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST) 2865 intel_dp_handle_test_request(intel_dp); 2866 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ)) 2867 DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n"); 2868 } 2869 2870 if (!drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) { 2871 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n", 2872 drm_get_encoder_name(&intel_encoder->base)); 2873 intel_dp_start_link_train(intel_dp); 2874 intel_dp_complete_link_train(intel_dp); 2875 intel_dp_stop_link_train(intel_dp); 2876 } 2877} 2878 2879/* XXX this is probably wrong for multiple downstream ports */ 2880static enum drm_connector_status 2881intel_dp_detect_dpcd(struct intel_dp *intel_dp) 2882{ 2883 uint8_t *dpcd = intel_dp->dpcd; 2884 uint8_t type; 2885 2886 if (!intel_dp_get_dpcd(intel_dp)) 2887 return connector_status_disconnected; 2888 2889 /* if there's no downstream port, we're done */ 2890 if (!(dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT)) 2891 return connector_status_connected; 2892 2893 /* If we're HPD-aware, SINK_COUNT changes dynamically */ 2894 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 && 2895 intel_dp->downstream_ports[0] & DP_DS_PORT_HPD) { 2896 uint8_t reg; 2897 if (!intel_dp_aux_native_read_retry(intel_dp, DP_SINK_COUNT, 2898 ®, 1)) 2899 return connector_status_unknown; 2900 return DP_GET_SINK_COUNT(reg) ? connector_status_connected 2901 : connector_status_disconnected; 2902 } 2903 2904 /* If no HPD, poke DDC gently */ 2905 if (drm_probe_ddc(&intel_dp->adapter)) 2906 return connector_status_connected; 2907 2908 /* Well we tried, say unknown for unreliable port types */ 2909 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) { 2910 type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK; 2911 if (type == DP_DS_PORT_TYPE_VGA || 2912 type == DP_DS_PORT_TYPE_NON_EDID) 2913 return connector_status_unknown; 2914 } else { 2915 type = intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] & 2916 DP_DWN_STRM_PORT_TYPE_MASK; 2917 if (type == DP_DWN_STRM_PORT_TYPE_ANALOG || 2918 type == DP_DWN_STRM_PORT_TYPE_OTHER) 2919 return connector_status_unknown; 2920 } 2921 2922 /* Anything else is out of spec, warn and ignore */ 2923 DRM_DEBUG_KMS("Broken DP branch device, ignoring\n"); 2924 return connector_status_disconnected; 2925} 2926 2927static enum drm_connector_status 2928ironlake_dp_detect(struct intel_dp *intel_dp) 2929{ 2930 struct drm_device *dev = intel_dp_to_dev(intel_dp); 2931 struct drm_i915_private *dev_priv = dev->dev_private; 2932 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 2933 enum drm_connector_status status; 2934 2935 /* Can't disconnect eDP, but you can close the lid... */ 2936 if (is_edp(intel_dp)) { 2937 status = intel_panel_detect(dev); 2938 if (status == connector_status_unknown) 2939 status = connector_status_connected; 2940 return status; 2941 } 2942 2943 if (!ibx_digital_port_connected(dev_priv, intel_dig_port)) 2944 return connector_status_disconnected; 2945 2946 return intel_dp_detect_dpcd(intel_dp); 2947} 2948 2949static enum drm_connector_status 2950g4x_dp_detect(struct intel_dp *intel_dp) 2951{ 2952 struct drm_device *dev = intel_dp_to_dev(intel_dp); 2953 struct drm_i915_private *dev_priv = dev->dev_private; 2954 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 2955 uint32_t bit; 2956 2957 /* Can't disconnect eDP, but you can close the lid... */ 2958 if (is_edp(intel_dp)) { 2959 enum drm_connector_status status; 2960 2961 status = intel_panel_detect(dev); 2962 if (status == connector_status_unknown) 2963 status = connector_status_connected; 2964 return status; 2965 } 2966 2967 switch (intel_dig_port->port) { 2968 case PORT_B: 2969 bit = PORTB_HOTPLUG_LIVE_STATUS; 2970 break; 2971 case PORT_C: 2972 bit = PORTC_HOTPLUG_LIVE_STATUS; 2973 break; 2974 case PORT_D: 2975 bit = PORTD_HOTPLUG_LIVE_STATUS; 2976 break; 2977 default: 2978 return connector_status_unknown; 2979 } 2980 2981 if ((I915_READ(PORT_HOTPLUG_STAT) & bit) == 0) 2982 return connector_status_disconnected; 2983 2984 return intel_dp_detect_dpcd(intel_dp); 2985} 2986 2987static struct edid * 2988intel_dp_get_edid(struct drm_connector *connector, struct i2c_adapter *adapter) 2989{ 2990 struct intel_connector *intel_connector = to_intel_connector(connector); 2991 2992 /* use cached edid if we have one */ 2993 if (intel_connector->edid) { 2994 /* invalid edid */ 2995 if (IS_ERR(intel_connector->edid)) 2996 return NULL; 2997 2998 return drm_edid_duplicate(intel_connector->edid); 2999 } 3000 3001 return drm_get_edid(connector, adapter); 3002} 3003 3004static int 3005intel_dp_get_edid_modes(struct drm_connector *connector, struct i2c_adapter *adapter) 3006{ 3007 struct intel_connector *intel_connector = to_intel_connector(connector); 3008 3009 /* use cached edid if we have one */ 3010 if (intel_connector->edid) { 3011 /* invalid edid */ 3012 if (IS_ERR(intel_connector->edid)) 3013 return 0; 3014 3015 return intel_connector_update_modes(connector, 3016 intel_connector->edid); 3017 } 3018 3019 return intel_ddc_get_modes(connector, adapter); 3020} 3021 3022static enum drm_connector_status 3023intel_dp_detect(struct drm_connector *connector, bool force) 3024{ 3025 struct intel_dp *intel_dp = intel_attached_dp(connector); 3026 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 3027 struct intel_encoder *intel_encoder = &intel_dig_port->base; 3028 struct drm_device *dev = connector->dev; 3029 enum drm_connector_status status; 3030 struct edid *edid = NULL; 3031 3032 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", 3033 connector->base.id, drm_get_connector_name(connector)); 3034 3035 intel_dp->has_audio = false; 3036 3037 if (HAS_PCH_SPLIT(dev)) 3038 status = ironlake_dp_detect(intel_dp); 3039 else 3040 status = g4x_dp_detect(intel_dp); 3041 3042 if (status != connector_status_connected) 3043 return status; 3044 3045 intel_dp_probe_oui(intel_dp); 3046 3047 if (intel_dp->force_audio != HDMI_AUDIO_AUTO) { 3048 intel_dp->has_audio = (intel_dp->force_audio == HDMI_AUDIO_ON); 3049 } else { 3050 edid = intel_dp_get_edid(connector, &intel_dp->adapter); 3051 if (edid) { 3052 intel_dp->has_audio = drm_detect_monitor_audio(edid); 3053 kfree(edid); 3054 } 3055 } 3056 3057 if (intel_encoder->type != INTEL_OUTPUT_EDP) 3058 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT; 3059 return connector_status_connected; 3060} 3061 3062static int intel_dp_get_modes(struct drm_connector *connector) 3063{ 3064 struct intel_dp *intel_dp = intel_attached_dp(connector); 3065 struct intel_connector *intel_connector = to_intel_connector(connector); 3066 struct drm_device *dev = connector->dev; 3067 int ret; 3068 3069 /* We should parse the EDID data and find out if it has an audio sink 3070 */ 3071 3072 ret = intel_dp_get_edid_modes(connector, &intel_dp->adapter); 3073 if (ret) 3074 return ret; 3075 3076 /* if eDP has no EDID, fall back to fixed mode */ 3077 if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) { 3078 struct drm_display_mode *mode; 3079 mode = drm_mode_duplicate(dev, 3080 intel_connector->panel.fixed_mode); 3081 if (mode) { 3082 drm_mode_probed_add(connector, mode); 3083 return 1; 3084 } 3085 } 3086 return 0; 3087} 3088 3089static bool 3090intel_dp_detect_audio(struct drm_connector *connector) 3091{ 3092 struct intel_dp *intel_dp = intel_attached_dp(connector); 3093 struct edid *edid; 3094 bool has_audio = false; 3095 3096 edid = intel_dp_get_edid(connector, &intel_dp->adapter); 3097 if (edid) { 3098 has_audio = drm_detect_monitor_audio(edid); 3099 kfree(edid); 3100 } 3101 3102 return has_audio; 3103} 3104 3105static int 3106intel_dp_set_property(struct drm_connector *connector, 3107 struct drm_property *property, 3108 uint64_t val) 3109{ 3110 struct drm_i915_private *dev_priv = connector->dev->dev_private; 3111 struct intel_connector *intel_connector = to_intel_connector(connector); 3112 struct intel_encoder *intel_encoder = intel_attached_encoder(connector); 3113 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base); 3114 int ret; 3115 3116 ret = drm_object_property_set_value(&connector->base, property, val); 3117 if (ret) 3118 return ret; 3119 3120 if (property == dev_priv->force_audio_property) { 3121 int i = val; 3122 bool has_audio; 3123 3124 if (i == intel_dp->force_audio) 3125 return 0; 3126 3127 intel_dp->force_audio = i; 3128 3129 if (i == HDMI_AUDIO_AUTO) 3130 has_audio = intel_dp_detect_audio(connector); 3131 else 3132 has_audio = (i == HDMI_AUDIO_ON); 3133 3134 if (has_audio == intel_dp->has_audio) 3135 return 0; 3136 3137 intel_dp->has_audio = has_audio; 3138 goto done; 3139 } 3140 3141 if (property == dev_priv->broadcast_rgb_property) { 3142 bool old_auto = intel_dp->color_range_auto; 3143 uint32_t old_range = intel_dp->color_range; 3144 3145 switch (val) { 3146 case INTEL_BROADCAST_RGB_AUTO: 3147 intel_dp->color_range_auto = true; 3148 break; 3149 case INTEL_BROADCAST_RGB_FULL: 3150 intel_dp->color_range_auto = false; 3151 intel_dp->color_range = 0; 3152 break; 3153 case INTEL_BROADCAST_RGB_LIMITED: 3154 intel_dp->color_range_auto = false; 3155 intel_dp->color_range = DP_COLOR_RANGE_16_235; 3156 break; 3157 default: 3158 return -EINVAL; 3159 } 3160 3161 if (old_auto == intel_dp->color_range_auto && 3162 old_range == intel_dp->color_range) 3163 return 0; 3164 3165 goto done; 3166 } 3167 3168 if (is_edp(intel_dp) && 3169 property == connector->dev->mode_config.scaling_mode_property) { 3170 if (val == DRM_MODE_SCALE_NONE) { 3171 DRM_DEBUG_KMS("no scaling not supported\n"); 3172 return -EINVAL; 3173 } 3174 3175 if (intel_connector->panel.fitting_mode == val) { 3176 /* the eDP scaling property is not changed */ 3177 return 0; 3178 } 3179 intel_connector->panel.fitting_mode = val; 3180 3181 goto done; 3182 } 3183 3184 return -EINVAL; 3185 3186done: 3187 if (intel_encoder->base.crtc) 3188 intel_crtc_restore_mode(intel_encoder->base.crtc); 3189 3190 return 0; 3191} 3192 3193static void 3194intel_dp_connector_destroy(struct drm_connector *connector) 3195{ 3196 struct intel_connector *intel_connector = to_intel_connector(connector); 3197 3198 if (!IS_ERR_OR_NULL(intel_connector->edid)) 3199 kfree(intel_connector->edid); 3200 3201 /* Can't call is_edp() since the encoder may have been destroyed 3202 * already. */ 3203 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) 3204 intel_panel_fini(&intel_connector->panel); 3205 3206 drm_connector_cleanup(connector); 3207 kfree(connector); 3208} 3209 3210void intel_dp_encoder_destroy(struct drm_encoder *encoder) 3211{ 3212 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); 3213 struct intel_dp *intel_dp = &intel_dig_port->dp; 3214 struct drm_device *dev = intel_dp_to_dev(intel_dp); 3215 3216 i2c_del_adapter(&intel_dp->adapter); 3217 drm_encoder_cleanup(encoder); 3218 if (is_edp(intel_dp)) { 3219 cancel_delayed_work_sync(&intel_dp->panel_vdd_work); 3220 mutex_lock(&dev->mode_config.mutex); 3221 ironlake_panel_vdd_off_sync(intel_dp); 3222 mutex_unlock(&dev->mode_config.mutex); 3223 } 3224 kfree(intel_dig_port); 3225} 3226 3227static const struct drm_connector_funcs intel_dp_connector_funcs = { 3228 .dpms = intel_connector_dpms, 3229 .detect = intel_dp_detect, 3230 .fill_modes = drm_helper_probe_single_connector_modes, 3231 .set_property = intel_dp_set_property, 3232 .destroy = intel_dp_connector_destroy, 3233}; 3234 3235static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = { 3236 .get_modes = intel_dp_get_modes, 3237 .mode_valid = intel_dp_mode_valid, 3238 .best_encoder = intel_best_encoder, 3239}; 3240 3241static const struct drm_encoder_funcs intel_dp_enc_funcs = { 3242 .destroy = intel_dp_encoder_destroy, 3243}; 3244 3245static void 3246intel_dp_hot_plug(struct intel_encoder *intel_encoder) 3247{ 3248 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base); 3249 3250 intel_dp_check_link_status(intel_dp); 3251} 3252 3253/* Return which DP Port should be selected for Transcoder DP control */ 3254int 3255intel_trans_dp_port_sel(struct drm_crtc *crtc) 3256{ 3257 struct drm_device *dev = crtc->dev; 3258 struct intel_encoder *intel_encoder; 3259 struct intel_dp *intel_dp; 3260 3261 for_each_encoder_on_crtc(dev, crtc, intel_encoder) { 3262 intel_dp = enc_to_intel_dp(&intel_encoder->base); 3263 3264 if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT || 3265 intel_encoder->type == INTEL_OUTPUT_EDP) 3266 return intel_dp->output_reg; 3267 } 3268 3269 return -1; 3270} 3271 3272/* check the VBT to see whether the eDP is on DP-D port */ 3273bool intel_dpd_is_edp(struct drm_device *dev) 3274{ 3275 struct drm_i915_private *dev_priv = dev->dev_private; 3276 union child_device_config *p_child; 3277 int i; 3278 3279 if (!dev_priv->vbt.child_dev_num) 3280 return false; 3281 3282 for (i = 0; i < dev_priv->vbt.child_dev_num; i++) { 3283 p_child = dev_priv->vbt.child_dev + i; 3284 3285 if (p_child->common.dvo_port == PORT_IDPD && 3286 (p_child->common.device_type & DEVICE_TYPE_eDP_BITS) == 3287 (DEVICE_TYPE_eDP & DEVICE_TYPE_eDP_BITS)) 3288 return true; 3289 } 3290 return false; 3291} 3292 3293static void 3294intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector) 3295{ 3296 struct intel_connector *intel_connector = to_intel_connector(connector); 3297 3298 intel_attach_force_audio_property(connector); 3299 intel_attach_broadcast_rgb_property(connector); 3300 intel_dp->color_range_auto = true; 3301 3302 if (is_edp(intel_dp)) { 3303 drm_mode_create_scaling_mode_property(connector->dev); 3304 drm_object_attach_property( 3305 &connector->base, 3306 connector->dev->mode_config.scaling_mode_property, 3307 DRM_MODE_SCALE_ASPECT); 3308 intel_connector->panel.fitting_mode = DRM_MODE_SCALE_ASPECT; 3309 } 3310} 3311 3312static void 3313intel_dp_init_panel_power_sequencer(struct drm_device *dev, 3314 struct intel_dp *intel_dp, 3315 struct edp_power_seq *out) 3316{ 3317 struct drm_i915_private *dev_priv = dev->dev_private; 3318 struct edp_power_seq cur, vbt, spec, final; 3319 u32 pp_on, pp_off, pp_div, pp; 3320 int pp_ctrl_reg, pp_on_reg, pp_off_reg, pp_div_reg; 3321 3322 if (HAS_PCH_SPLIT(dev)) { 3323 pp_ctrl_reg = PCH_PP_CONTROL; 3324 pp_on_reg = PCH_PP_ON_DELAYS; 3325 pp_off_reg = PCH_PP_OFF_DELAYS; 3326 pp_div_reg = PCH_PP_DIVISOR; 3327 } else { 3328 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp); 3329 3330 pp_ctrl_reg = VLV_PIPE_PP_CONTROL(pipe); 3331 pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe); 3332 pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe); 3333 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe); 3334 } 3335 3336 /* Workaround: Need to write PP_CONTROL with the unlock key as 3337 * the very first thing. */ 3338 pp = ironlake_get_pp_control(intel_dp); 3339 I915_WRITE(pp_ctrl_reg, pp); 3340 3341 pp_on = I915_READ(pp_on_reg); 3342 pp_off = I915_READ(pp_off_reg); 3343 pp_div = I915_READ(pp_div_reg); 3344 3345 /* Pull timing values out of registers */ 3346 cur.t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >> 3347 PANEL_POWER_UP_DELAY_SHIFT; 3348 3349 cur.t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >> 3350 PANEL_LIGHT_ON_DELAY_SHIFT; 3351 3352 cur.t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >> 3353 PANEL_LIGHT_OFF_DELAY_SHIFT; 3354 3355 cur.t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >> 3356 PANEL_POWER_DOWN_DELAY_SHIFT; 3357 3358 cur.t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >> 3359 PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000; 3360 3361 DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n", 3362 cur.t1_t3, cur.t8, cur.t9, cur.t10, cur.t11_t12); 3363 3364 vbt = dev_priv->vbt.edp_pps; 3365 3366 /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of 3367 * our hw here, which are all in 100usec. */ 3368 spec.t1_t3 = 210 * 10; 3369 spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */ 3370 spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */ 3371 spec.t10 = 500 * 10; 3372 /* This one is special and actually in units of 100ms, but zero 3373 * based in the hw (so we need to add 100 ms). But the sw vbt 3374 * table multiplies it with 1000 to make it in units of 100usec, 3375 * too. */ 3376 spec.t11_t12 = (510 + 100) * 10; 3377 3378 DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n", 3379 vbt.t1_t3, vbt.t8, vbt.t9, vbt.t10, vbt.t11_t12); 3380 3381 /* Use the max of the register settings and vbt. If both are 3382 * unset, fall back to the spec limits. */ 3383#define assign_final(field) final.field = (max(cur.field, vbt.field) == 0 ? \ 3384 spec.field : \ 3385 max(cur.field, vbt.field)) 3386 assign_final(t1_t3); 3387 assign_final(t8); 3388 assign_final(t9); 3389 assign_final(t10); 3390 assign_final(t11_t12); 3391#undef assign_final 3392 3393#define get_delay(field) (DIV_ROUND_UP(final.field, 10)) 3394 intel_dp->panel_power_up_delay = get_delay(t1_t3); 3395 intel_dp->backlight_on_delay = get_delay(t8); 3396 intel_dp->backlight_off_delay = get_delay(t9); 3397 intel_dp->panel_power_down_delay = get_delay(t10); 3398 intel_dp->panel_power_cycle_delay = get_delay(t11_t12); 3399#undef get_delay 3400 3401 DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n", 3402 intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay, 3403 intel_dp->panel_power_cycle_delay); 3404 3405 DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n", 3406 intel_dp->backlight_on_delay, intel_dp->backlight_off_delay); 3407 3408 if (out) 3409 *out = final; 3410} 3411 3412static void 3413intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev, 3414 struct intel_dp *intel_dp, 3415 struct edp_power_seq *seq) 3416{ 3417 struct drm_i915_private *dev_priv = dev->dev_private; 3418 u32 pp_on, pp_off, pp_div, port_sel = 0; 3419 int div = HAS_PCH_SPLIT(dev) ? intel_pch_rawclk(dev) : intel_hrawclk(dev); 3420 int pp_on_reg, pp_off_reg, pp_div_reg; 3421 3422 if (HAS_PCH_SPLIT(dev)) { 3423 pp_on_reg = PCH_PP_ON_DELAYS; 3424 pp_off_reg = PCH_PP_OFF_DELAYS; 3425 pp_div_reg = PCH_PP_DIVISOR; 3426 } else { 3427 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp); 3428 3429 pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe); 3430 pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe); 3431 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe); 3432 } 3433 3434 /* And finally store the new values in the power sequencer. */ 3435 pp_on = (seq->t1_t3 << PANEL_POWER_UP_DELAY_SHIFT) | 3436 (seq->t8 << PANEL_LIGHT_ON_DELAY_SHIFT); 3437 pp_off = (seq->t9 << PANEL_LIGHT_OFF_DELAY_SHIFT) | 3438 (seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT); 3439 /* Compute the divisor for the pp clock, simply match the Bspec 3440 * formula. */ 3441 pp_div = ((100 * div)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT; 3442 pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000) 3443 << PANEL_POWER_CYCLE_DELAY_SHIFT); 3444 3445 /* Haswell doesn't have any port selection bits for the panel 3446 * power sequencer any more. */ 3447 if (IS_VALLEYVIEW(dev)) { 3448 if (dp_to_dig_port(intel_dp)->port == PORT_B) 3449 port_sel = PANEL_PORT_SELECT_DPB_VLV; 3450 else 3451 port_sel = PANEL_PORT_SELECT_DPC_VLV; 3452 } else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) { 3453 if (dp_to_dig_port(intel_dp)->port == PORT_A) 3454 port_sel = PANEL_PORT_SELECT_DPA; 3455 else 3456 port_sel = PANEL_PORT_SELECT_DPD; 3457 } 3458 3459 pp_on |= port_sel; 3460 3461 I915_WRITE(pp_on_reg, pp_on); 3462 I915_WRITE(pp_off_reg, pp_off); 3463 I915_WRITE(pp_div_reg, pp_div); 3464 3465 DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n", 3466 I915_READ(pp_on_reg), 3467 I915_READ(pp_off_reg), 3468 I915_READ(pp_div_reg)); 3469} 3470 3471static bool intel_edp_init_connector(struct intel_dp *intel_dp, 3472 struct intel_connector *intel_connector) 3473{ 3474 struct drm_connector *connector = &intel_connector->base; 3475 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 3476 struct drm_device *dev = intel_dig_port->base.base.dev; 3477 struct drm_i915_private *dev_priv = dev->dev_private; 3478 struct drm_display_mode *fixed_mode = NULL; 3479 struct edp_power_seq power_seq = { 0 }; 3480 bool has_dpcd; 3481 struct drm_display_mode *scan; 3482 struct edid *edid; 3483 3484 if (!is_edp(intel_dp)) 3485 return true; 3486 3487 intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq); 3488 3489 /* Cache DPCD and EDID for edp. */ 3490 ironlake_edp_panel_vdd_on(intel_dp); 3491 has_dpcd = intel_dp_get_dpcd(intel_dp); 3492 ironlake_edp_panel_vdd_off(intel_dp, false); 3493 3494 if (has_dpcd) { 3495 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) 3496 dev_priv->no_aux_handshake = 3497 intel_dp->dpcd[DP_MAX_DOWNSPREAD] & 3498 DP_NO_AUX_HANDSHAKE_LINK_TRAINING; 3499 } else { 3500 /* if this fails, presume the device is a ghost */ 3501 DRM_INFO("failed to retrieve link info, disabling eDP\n"); 3502 return false; 3503 } 3504 3505 /* We now know it's not a ghost, init power sequence regs. */ 3506 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp, 3507 &power_seq); 3508 3509 edid = drm_get_edid(connector, &intel_dp->adapter); 3510 if (edid) { 3511 if (drm_add_edid_modes(connector, edid)) { 3512 drm_mode_connector_update_edid_property(connector, 3513 edid); 3514 drm_edid_to_eld(connector, edid); 3515 } else { 3516 kfree(edid); 3517 edid = ERR_PTR(-EINVAL); 3518 } 3519 } else { 3520 edid = ERR_PTR(-ENOENT); 3521 } 3522 intel_connector->edid = edid; 3523 3524 /* prefer fixed mode from EDID if available */ 3525 list_for_each_entry(scan, &connector->probed_modes, head) { 3526 if ((scan->type & DRM_MODE_TYPE_PREFERRED)) { 3527 fixed_mode = drm_mode_duplicate(dev, scan); 3528 break; 3529 } 3530 } 3531 3532 /* fallback to VBT if available for eDP */ 3533 if (!fixed_mode && dev_priv->vbt.lfp_lvds_vbt_mode) { 3534 fixed_mode = drm_mode_duplicate(dev, 3535 dev_priv->vbt.lfp_lvds_vbt_mode); 3536 if (fixed_mode) 3537 fixed_mode->type |= DRM_MODE_TYPE_PREFERRED; 3538 } 3539 3540 intel_panel_init(&intel_connector->panel, fixed_mode); 3541 intel_panel_setup_backlight(connector); 3542 3543 return true; 3544} 3545 3546bool 3547intel_dp_init_connector(struct intel_digital_port *intel_dig_port, 3548 struct intel_connector *intel_connector) 3549{ 3550 struct drm_connector *connector = &intel_connector->base; 3551 struct intel_dp *intel_dp = &intel_dig_port->dp; 3552 struct intel_encoder *intel_encoder = &intel_dig_port->base; 3553 struct drm_device *dev = intel_encoder->base.dev; 3554 struct drm_i915_private *dev_priv = dev->dev_private; 3555 enum port port = intel_dig_port->port; 3556 const char *name = NULL; 3557 int type, error; 3558 3559 /* Preserve the current hw state. */ 3560 intel_dp->DP = I915_READ(intel_dp->output_reg); 3561 intel_dp->attached_connector = intel_connector; 3562 3563 type = DRM_MODE_CONNECTOR_DisplayPort; 3564 /* 3565 * FIXME : We need to initialize built-in panels before external panels. 3566 * For X0, DP_C is fixed as eDP. Revisit this as part of VLV eDP cleanup 3567 */ 3568 switch (port) { 3569 case PORT_A: 3570 type = DRM_MODE_CONNECTOR_eDP; 3571 break; 3572 case PORT_C: 3573 if (IS_VALLEYVIEW(dev)) 3574 type = DRM_MODE_CONNECTOR_eDP; 3575 break; 3576 case PORT_D: 3577 if (HAS_PCH_SPLIT(dev) && intel_dpd_is_edp(dev)) 3578 type = DRM_MODE_CONNECTOR_eDP; 3579 break; 3580 default: /* silence GCC warning */ 3581 break; 3582 } 3583 3584 /* 3585 * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but 3586 * for DP the encoder type can be set by the caller to 3587 * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it. 3588 */ 3589 if (type == DRM_MODE_CONNECTOR_eDP) 3590 intel_encoder->type = INTEL_OUTPUT_EDP; 3591 3592 DRM_DEBUG_KMS("Adding %s connector on port %c\n", 3593 type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP", 3594 port_name(port)); 3595 3596 drm_connector_init(dev, connector, &intel_dp_connector_funcs, type); 3597 drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs); 3598 3599 connector->interlace_allowed = true; 3600 connector->doublescan_allowed = 0; 3601 3602 INIT_DELAYED_WORK(&intel_dp->panel_vdd_work, 3603 ironlake_panel_vdd_work); 3604 3605 intel_connector_attach_encoder(intel_connector, intel_encoder); 3606 drm_sysfs_connector_add(connector); 3607 3608 if (HAS_DDI(dev)) 3609 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state; 3610 else 3611 intel_connector->get_hw_state = intel_connector_get_hw_state; 3612 3613 intel_dp->aux_ch_ctl_reg = intel_dp->output_reg + 0x10; 3614 if (HAS_DDI(dev)) { 3615 switch (intel_dig_port->port) { 3616 case PORT_A: 3617 intel_dp->aux_ch_ctl_reg = DPA_AUX_CH_CTL; 3618 break; 3619 case PORT_B: 3620 intel_dp->aux_ch_ctl_reg = PCH_DPB_AUX_CH_CTL; 3621 break; 3622 case PORT_C: 3623 intel_dp->aux_ch_ctl_reg = PCH_DPC_AUX_CH_CTL; 3624 break; 3625 case PORT_D: 3626 intel_dp->aux_ch_ctl_reg = PCH_DPD_AUX_CH_CTL; 3627 break; 3628 default: 3629 BUG(); 3630 } 3631 } 3632 3633 /* Set up the DDC bus. */ 3634 switch (port) { 3635 case PORT_A: 3636 intel_encoder->hpd_pin = HPD_PORT_A; 3637 name = "DPDDC-A"; 3638 break; 3639 case PORT_B: 3640 intel_encoder->hpd_pin = HPD_PORT_B; 3641 name = "DPDDC-B"; 3642 break; 3643 case PORT_C: 3644 intel_encoder->hpd_pin = HPD_PORT_C; 3645 name = "DPDDC-C"; 3646 break; 3647 case PORT_D: 3648 intel_encoder->hpd_pin = HPD_PORT_D; 3649 name = "DPDDC-D"; 3650 break; 3651 default: 3652 BUG(); 3653 } 3654 3655 error = intel_dp_i2c_init(intel_dp, intel_connector, name); 3656 WARN(error, "intel_dp_i2c_init failed with error %d for port %c\n", 3657 error, port_name(port)); 3658 3659 intel_dp->psr_setup_done = false; 3660 3661 if (!intel_edp_init_connector(intel_dp, intel_connector)) { 3662 i2c_del_adapter(&intel_dp->adapter); 3663 if (is_edp(intel_dp)) { 3664 cancel_delayed_work_sync(&intel_dp->panel_vdd_work); 3665 mutex_lock(&dev->mode_config.mutex); 3666 ironlake_panel_vdd_off_sync(intel_dp); 3667 mutex_unlock(&dev->mode_config.mutex); 3668 } 3669 drm_sysfs_connector_remove(connector); 3670 drm_connector_cleanup(connector); 3671 return false; 3672 } 3673 3674 intel_dp_add_properties(intel_dp, connector); 3675 3676 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written 3677 * 0xd. Failure to do so will result in spurious interrupts being 3678 * generated on the port when a cable is not attached. 3679 */ 3680 if (IS_G4X(dev) && !IS_GM45(dev)) { 3681 u32 temp = I915_READ(PEG_BAND_GAP_DATA); 3682 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd); 3683 } 3684 3685 return true; 3686} 3687 3688void 3689intel_dp_init(struct drm_device *dev, int output_reg, enum port port) 3690{ 3691 struct intel_digital_port *intel_dig_port; 3692 struct intel_encoder *intel_encoder; 3693 struct drm_encoder *encoder; 3694 struct intel_connector *intel_connector; 3695 3696 intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL); 3697 if (!intel_dig_port) 3698 return; 3699 3700 intel_connector = kzalloc(sizeof(*intel_connector), GFP_KERNEL); 3701 if (!intel_connector) { 3702 kfree(intel_dig_port); 3703 return; 3704 } 3705 3706 intel_encoder = &intel_dig_port->base; 3707 encoder = &intel_encoder->base; 3708 3709 drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs, 3710 DRM_MODE_ENCODER_TMDS); 3711 3712 intel_encoder->compute_config = intel_dp_compute_config; 3713 intel_encoder->mode_set = intel_dp_mode_set; 3714 intel_encoder->disable = intel_disable_dp; 3715 intel_encoder->post_disable = intel_post_disable_dp; 3716 intel_encoder->get_hw_state = intel_dp_get_hw_state; 3717 intel_encoder->get_config = intel_dp_get_config; 3718 if (IS_VALLEYVIEW(dev)) { 3719 intel_encoder->pre_pll_enable = vlv_dp_pre_pll_enable; 3720 intel_encoder->pre_enable = vlv_pre_enable_dp; 3721 intel_encoder->enable = vlv_enable_dp; 3722 } else { 3723 intel_encoder->pre_enable = g4x_pre_enable_dp; 3724 intel_encoder->enable = g4x_enable_dp; 3725 } 3726 3727 intel_dig_port->port = port; 3728 intel_dig_port->dp.output_reg = output_reg; 3729 3730 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT; 3731 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2); 3732 intel_encoder->cloneable = false; 3733 intel_encoder->hot_plug = intel_dp_hot_plug; 3734 3735 if (!intel_dp_init_connector(intel_dig_port, intel_connector)) { 3736 drm_encoder_cleanup(encoder); 3737 kfree(intel_dig_port); 3738 kfree(intel_connector); 3739 } 3740} 3741