intel_dp.c revision 89c6143263ef8e14e42e17324a234418d8030b10
1/* 2 * Copyright © 2008 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 * Authors: 24 * Keith Packard <keithp@keithp.com> 25 * 26 */ 27 28#include <linux/i2c.h> 29#include <linux/slab.h> 30#include "drmP.h" 31#include "drm.h" 32#include "drm_crtc.h" 33#include "drm_crtc_helper.h" 34#include "intel_drv.h" 35#include "i915_drm.h" 36#include "i915_drv.h" 37#include "drm_dp_helper.h" 38 39 40#define DP_LINK_STATUS_SIZE 6 41#define DP_LINK_CHECK_TIMEOUT (10 * 1000) 42 43#define DP_LINK_CONFIGURATION_SIZE 9 44 45struct intel_dp { 46 struct intel_encoder base; 47 uint32_t output_reg; 48 uint32_t DP; 49 uint8_t link_configuration[DP_LINK_CONFIGURATION_SIZE]; 50 bool has_audio; 51 int force_audio; 52 uint32_t color_range; 53 int dpms_mode; 54 uint8_t link_bw; 55 uint8_t lane_count; 56 uint8_t dpcd[4]; 57 struct i2c_adapter adapter; 58 struct i2c_algo_dp_aux_data algo; 59 bool is_pch_edp; 60 uint8_t train_set[4]; 61 uint8_t link_status[DP_LINK_STATUS_SIZE]; 62}; 63 64/** 65 * is_edp - is the given port attached to an eDP panel (either CPU or PCH) 66 * @intel_dp: DP struct 67 * 68 * If a CPU or PCH DP output is attached to an eDP panel, this function 69 * will return true, and false otherwise. 70 */ 71static bool is_edp(struct intel_dp *intel_dp) 72{ 73 return intel_dp->base.type == INTEL_OUTPUT_EDP; 74} 75 76/** 77 * is_pch_edp - is the port on the PCH and attached to an eDP panel? 78 * @intel_dp: DP struct 79 * 80 * Returns true if the given DP struct corresponds to a PCH DP port attached 81 * to an eDP panel, false otherwise. Helpful for determining whether we 82 * may need FDI resources for a given DP output or not. 83 */ 84static bool is_pch_edp(struct intel_dp *intel_dp) 85{ 86 return intel_dp->is_pch_edp; 87} 88 89static struct intel_dp *enc_to_intel_dp(struct drm_encoder *encoder) 90{ 91 return container_of(encoder, struct intel_dp, base.base); 92} 93 94static struct intel_dp *intel_attached_dp(struct drm_connector *connector) 95{ 96 return container_of(intel_attached_encoder(connector), 97 struct intel_dp, base); 98} 99 100/** 101 * intel_encoder_is_pch_edp - is the given encoder a PCH attached eDP? 102 * @encoder: DRM encoder 103 * 104 * Return true if @encoder corresponds to a PCH attached eDP panel. Needed 105 * by intel_display.c. 106 */ 107bool intel_encoder_is_pch_edp(struct drm_encoder *encoder) 108{ 109 struct intel_dp *intel_dp; 110 111 if (!encoder) 112 return false; 113 114 intel_dp = enc_to_intel_dp(encoder); 115 116 return is_pch_edp(intel_dp); 117} 118 119static void intel_dp_start_link_train(struct intel_dp *intel_dp); 120static void intel_dp_complete_link_train(struct intel_dp *intel_dp); 121static void intel_dp_link_down(struct intel_dp *intel_dp); 122 123void 124intel_edp_link_config (struct intel_encoder *intel_encoder, 125 int *lane_num, int *link_bw) 126{ 127 struct intel_dp *intel_dp = container_of(intel_encoder, struct intel_dp, base); 128 129 *lane_num = intel_dp->lane_count; 130 if (intel_dp->link_bw == DP_LINK_BW_1_62) 131 *link_bw = 162000; 132 else if (intel_dp->link_bw == DP_LINK_BW_2_7) 133 *link_bw = 270000; 134} 135 136static int 137intel_dp_max_lane_count(struct intel_dp *intel_dp) 138{ 139 int max_lane_count = 4; 140 141 if (intel_dp->dpcd[0] >= 0x11) { 142 max_lane_count = intel_dp->dpcd[2] & 0x1f; 143 switch (max_lane_count) { 144 case 1: case 2: case 4: 145 break; 146 default: 147 max_lane_count = 4; 148 } 149 } 150 return max_lane_count; 151} 152 153static int 154intel_dp_max_link_bw(struct intel_dp *intel_dp) 155{ 156 int max_link_bw = intel_dp->dpcd[1]; 157 158 switch (max_link_bw) { 159 case DP_LINK_BW_1_62: 160 case DP_LINK_BW_2_7: 161 break; 162 default: 163 max_link_bw = DP_LINK_BW_1_62; 164 break; 165 } 166 return max_link_bw; 167} 168 169static int 170intel_dp_link_clock(uint8_t link_bw) 171{ 172 if (link_bw == DP_LINK_BW_2_7) 173 return 270000; 174 else 175 return 162000; 176} 177 178/* I think this is a fiction */ 179static int 180intel_dp_link_required(struct drm_device *dev, struct intel_dp *intel_dp, int pixel_clock) 181{ 182 struct drm_crtc *crtc = intel_dp->base.base.crtc; 183 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 184 int bpp = 24; 185 186 if (intel_crtc) 187 bpp = intel_crtc->bpp; 188 189 return (pixel_clock * bpp + 7) / 8; 190} 191 192static int 193intel_dp_max_data_rate(int max_link_clock, int max_lanes) 194{ 195 return (max_link_clock * max_lanes * 8) / 10; 196} 197 198static int 199intel_dp_mode_valid(struct drm_connector *connector, 200 struct drm_display_mode *mode) 201{ 202 struct intel_dp *intel_dp = intel_attached_dp(connector); 203 struct drm_device *dev = connector->dev; 204 struct drm_i915_private *dev_priv = dev->dev_private; 205 int max_link_clock = intel_dp_link_clock(intel_dp_max_link_bw(intel_dp)); 206 int max_lanes = intel_dp_max_lane_count(intel_dp); 207 208 if (is_edp(intel_dp) && dev_priv->panel_fixed_mode) { 209 if (mode->hdisplay > dev_priv->panel_fixed_mode->hdisplay) 210 return MODE_PANEL; 211 212 if (mode->vdisplay > dev_priv->panel_fixed_mode->vdisplay) 213 return MODE_PANEL; 214 } 215 216 /* only refuse the mode on non eDP since we have seen some weird eDP panels 217 which are outside spec tolerances but somehow work by magic */ 218 if (!is_edp(intel_dp) && 219 (intel_dp_link_required(connector->dev, intel_dp, mode->clock) 220 > intel_dp_max_data_rate(max_link_clock, max_lanes))) 221 return MODE_CLOCK_HIGH; 222 223 if (mode->clock < 10000) 224 return MODE_CLOCK_LOW; 225 226 return MODE_OK; 227} 228 229static uint32_t 230pack_aux(uint8_t *src, int src_bytes) 231{ 232 int i; 233 uint32_t v = 0; 234 235 if (src_bytes > 4) 236 src_bytes = 4; 237 for (i = 0; i < src_bytes; i++) 238 v |= ((uint32_t) src[i]) << ((3-i) * 8); 239 return v; 240} 241 242static void 243unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes) 244{ 245 int i; 246 if (dst_bytes > 4) 247 dst_bytes = 4; 248 for (i = 0; i < dst_bytes; i++) 249 dst[i] = src >> ((3-i) * 8); 250} 251 252/* hrawclock is 1/4 the FSB frequency */ 253static int 254intel_hrawclk(struct drm_device *dev) 255{ 256 struct drm_i915_private *dev_priv = dev->dev_private; 257 uint32_t clkcfg; 258 259 clkcfg = I915_READ(CLKCFG); 260 switch (clkcfg & CLKCFG_FSB_MASK) { 261 case CLKCFG_FSB_400: 262 return 100; 263 case CLKCFG_FSB_533: 264 return 133; 265 case CLKCFG_FSB_667: 266 return 166; 267 case CLKCFG_FSB_800: 268 return 200; 269 case CLKCFG_FSB_1067: 270 return 266; 271 case CLKCFG_FSB_1333: 272 return 333; 273 /* these two are just a guess; one of them might be right */ 274 case CLKCFG_FSB_1600: 275 case CLKCFG_FSB_1600_ALT: 276 return 400; 277 default: 278 return 133; 279 } 280} 281 282static int 283intel_dp_aux_ch(struct intel_dp *intel_dp, 284 uint8_t *send, int send_bytes, 285 uint8_t *recv, int recv_size) 286{ 287 uint32_t output_reg = intel_dp->output_reg; 288 struct drm_device *dev = intel_dp->base.base.dev; 289 struct drm_i915_private *dev_priv = dev->dev_private; 290 uint32_t ch_ctl = output_reg + 0x10; 291 uint32_t ch_data = ch_ctl + 4; 292 int i; 293 int recv_bytes; 294 uint32_t status; 295 uint32_t aux_clock_divider; 296 int try, precharge; 297 298 /* The clock divider is based off the hrawclk, 299 * and would like to run at 2MHz. So, take the 300 * hrawclk value and divide by 2 and use that 301 * 302 * Note that PCH attached eDP panels should use a 125MHz input 303 * clock divider. 304 */ 305 if (is_edp(intel_dp) && !is_pch_edp(intel_dp)) { 306 if (IS_GEN6(dev)) 307 aux_clock_divider = 200; /* SNB eDP input clock at 400Mhz */ 308 else 309 aux_clock_divider = 225; /* eDP input clock at 450Mhz */ 310 } else if (HAS_PCH_SPLIT(dev)) 311 aux_clock_divider = 62; /* IRL input clock fixed at 125Mhz */ 312 else 313 aux_clock_divider = intel_hrawclk(dev) / 2; 314 315 if (IS_GEN6(dev)) 316 precharge = 3; 317 else 318 precharge = 5; 319 320 if (I915_READ(ch_ctl) & DP_AUX_CH_CTL_SEND_BUSY) { 321 DRM_ERROR("dp_aux_ch not started status 0x%08x\n", 322 I915_READ(ch_ctl)); 323 return -EBUSY; 324 } 325 326 /* Must try at least 3 times according to DP spec */ 327 for (try = 0; try < 5; try++) { 328 /* Load the send data into the aux channel data registers */ 329 for (i = 0; i < send_bytes; i += 4) 330 I915_WRITE(ch_data + i, 331 pack_aux(send + i, send_bytes - i)); 332 333 /* Send the command and wait for it to complete */ 334 I915_WRITE(ch_ctl, 335 DP_AUX_CH_CTL_SEND_BUSY | 336 DP_AUX_CH_CTL_TIME_OUT_400us | 337 (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) | 338 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) | 339 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT) | 340 DP_AUX_CH_CTL_DONE | 341 DP_AUX_CH_CTL_TIME_OUT_ERROR | 342 DP_AUX_CH_CTL_RECEIVE_ERROR); 343 for (;;) { 344 status = I915_READ(ch_ctl); 345 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0) 346 break; 347 udelay(100); 348 } 349 350 /* Clear done status and any errors */ 351 I915_WRITE(ch_ctl, 352 status | 353 DP_AUX_CH_CTL_DONE | 354 DP_AUX_CH_CTL_TIME_OUT_ERROR | 355 DP_AUX_CH_CTL_RECEIVE_ERROR); 356 if (status & DP_AUX_CH_CTL_DONE) 357 break; 358 } 359 360 if ((status & DP_AUX_CH_CTL_DONE) == 0) { 361 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status); 362 return -EBUSY; 363 } 364 365 /* Check for timeout or receive error. 366 * Timeouts occur when the sink is not connected 367 */ 368 if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) { 369 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status); 370 return -EIO; 371 } 372 373 /* Timeouts occur when the device isn't connected, so they're 374 * "normal" -- don't fill the kernel log with these */ 375 if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) { 376 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status); 377 return -ETIMEDOUT; 378 } 379 380 /* Unload any bytes sent back from the other side */ 381 recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >> 382 DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT); 383 if (recv_bytes > recv_size) 384 recv_bytes = recv_size; 385 386 for (i = 0; i < recv_bytes; i += 4) 387 unpack_aux(I915_READ(ch_data + i), 388 recv + i, recv_bytes - i); 389 390 return recv_bytes; 391} 392 393/* Write data to the aux channel in native mode */ 394static int 395intel_dp_aux_native_write(struct intel_dp *intel_dp, 396 uint16_t address, uint8_t *send, int send_bytes) 397{ 398 int ret; 399 uint8_t msg[20]; 400 int msg_bytes; 401 uint8_t ack; 402 403 if (send_bytes > 16) 404 return -1; 405 msg[0] = AUX_NATIVE_WRITE << 4; 406 msg[1] = address >> 8; 407 msg[2] = address & 0xff; 408 msg[3] = send_bytes - 1; 409 memcpy(&msg[4], send, send_bytes); 410 msg_bytes = send_bytes + 4; 411 for (;;) { 412 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes, &ack, 1); 413 if (ret < 0) 414 return ret; 415 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK) 416 break; 417 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER) 418 udelay(100); 419 else 420 return -EIO; 421 } 422 return send_bytes; 423} 424 425/* Write a single byte to the aux channel in native mode */ 426static int 427intel_dp_aux_native_write_1(struct intel_dp *intel_dp, 428 uint16_t address, uint8_t byte) 429{ 430 return intel_dp_aux_native_write(intel_dp, address, &byte, 1); 431} 432 433/* read bytes from a native aux channel */ 434static int 435intel_dp_aux_native_read(struct intel_dp *intel_dp, 436 uint16_t address, uint8_t *recv, int recv_bytes) 437{ 438 uint8_t msg[4]; 439 int msg_bytes; 440 uint8_t reply[20]; 441 int reply_bytes; 442 uint8_t ack; 443 int ret; 444 445 msg[0] = AUX_NATIVE_READ << 4; 446 msg[1] = address >> 8; 447 msg[2] = address & 0xff; 448 msg[3] = recv_bytes - 1; 449 450 msg_bytes = 4; 451 reply_bytes = recv_bytes + 1; 452 453 for (;;) { 454 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes, 455 reply, reply_bytes); 456 if (ret == 0) 457 return -EPROTO; 458 if (ret < 0) 459 return ret; 460 ack = reply[0]; 461 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK) { 462 memcpy(recv, reply + 1, ret - 1); 463 return ret - 1; 464 } 465 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER) 466 udelay(100); 467 else 468 return -EIO; 469 } 470} 471 472static int 473intel_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode, 474 uint8_t write_byte, uint8_t *read_byte) 475{ 476 struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data; 477 struct intel_dp *intel_dp = container_of(adapter, 478 struct intel_dp, 479 adapter); 480 uint16_t address = algo_data->address; 481 uint8_t msg[5]; 482 uint8_t reply[2]; 483 unsigned retry; 484 int msg_bytes; 485 int reply_bytes; 486 int ret; 487 488 /* Set up the command byte */ 489 if (mode & MODE_I2C_READ) 490 msg[0] = AUX_I2C_READ << 4; 491 else 492 msg[0] = AUX_I2C_WRITE << 4; 493 494 if (!(mode & MODE_I2C_STOP)) 495 msg[0] |= AUX_I2C_MOT << 4; 496 497 msg[1] = address >> 8; 498 msg[2] = address; 499 500 switch (mode) { 501 case MODE_I2C_WRITE: 502 msg[3] = 0; 503 msg[4] = write_byte; 504 msg_bytes = 5; 505 reply_bytes = 1; 506 break; 507 case MODE_I2C_READ: 508 msg[3] = 0; 509 msg_bytes = 4; 510 reply_bytes = 2; 511 break; 512 default: 513 msg_bytes = 3; 514 reply_bytes = 1; 515 break; 516 } 517 518 for (retry = 0; retry < 5; retry++) { 519 ret = intel_dp_aux_ch(intel_dp, 520 msg, msg_bytes, 521 reply, reply_bytes); 522 if (ret < 0) { 523 DRM_DEBUG_KMS("aux_ch failed %d\n", ret); 524 return ret; 525 } 526 527 switch (reply[0] & AUX_NATIVE_REPLY_MASK) { 528 case AUX_NATIVE_REPLY_ACK: 529 /* I2C-over-AUX Reply field is only valid 530 * when paired with AUX ACK. 531 */ 532 break; 533 case AUX_NATIVE_REPLY_NACK: 534 DRM_DEBUG_KMS("aux_ch native nack\n"); 535 return -EREMOTEIO; 536 case AUX_NATIVE_REPLY_DEFER: 537 udelay(100); 538 continue; 539 default: 540 DRM_ERROR("aux_ch invalid native reply 0x%02x\n", 541 reply[0]); 542 return -EREMOTEIO; 543 } 544 545 switch (reply[0] & AUX_I2C_REPLY_MASK) { 546 case AUX_I2C_REPLY_ACK: 547 if (mode == MODE_I2C_READ) { 548 *read_byte = reply[1]; 549 } 550 return reply_bytes - 1; 551 case AUX_I2C_REPLY_NACK: 552 DRM_DEBUG_KMS("aux_i2c nack\n"); 553 return -EREMOTEIO; 554 case AUX_I2C_REPLY_DEFER: 555 DRM_DEBUG_KMS("aux_i2c defer\n"); 556 udelay(100); 557 break; 558 default: 559 DRM_ERROR("aux_i2c invalid reply 0x%02x\n", reply[0]); 560 return -EREMOTEIO; 561 } 562 } 563 564 DRM_ERROR("too many retries, giving up\n"); 565 return -EREMOTEIO; 566} 567 568static int 569intel_dp_i2c_init(struct intel_dp *intel_dp, 570 struct intel_connector *intel_connector, const char *name) 571{ 572 DRM_DEBUG_KMS("i2c_init %s\n", name); 573 intel_dp->algo.running = false; 574 intel_dp->algo.address = 0; 575 intel_dp->algo.aux_ch = intel_dp_i2c_aux_ch; 576 577 memset(&intel_dp->adapter, '\0', sizeof (intel_dp->adapter)); 578 intel_dp->adapter.owner = THIS_MODULE; 579 intel_dp->adapter.class = I2C_CLASS_DDC; 580 strncpy (intel_dp->adapter.name, name, sizeof(intel_dp->adapter.name) - 1); 581 intel_dp->adapter.name[sizeof(intel_dp->adapter.name) - 1] = '\0'; 582 intel_dp->adapter.algo_data = &intel_dp->algo; 583 intel_dp->adapter.dev.parent = &intel_connector->base.kdev; 584 585 return i2c_dp_aux_add_bus(&intel_dp->adapter); 586} 587 588static bool 589intel_dp_mode_fixup(struct drm_encoder *encoder, struct drm_display_mode *mode, 590 struct drm_display_mode *adjusted_mode) 591{ 592 struct drm_device *dev = encoder->dev; 593 struct drm_i915_private *dev_priv = dev->dev_private; 594 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 595 int lane_count, clock; 596 int max_lane_count = intel_dp_max_lane_count(intel_dp); 597 int max_clock = intel_dp_max_link_bw(intel_dp) == DP_LINK_BW_2_7 ? 1 : 0; 598 static int bws[2] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7 }; 599 600 if (is_edp(intel_dp) && dev_priv->panel_fixed_mode) { 601 intel_fixed_panel_mode(dev_priv->panel_fixed_mode, adjusted_mode); 602 intel_pch_panel_fitting(dev, DRM_MODE_SCALE_FULLSCREEN, 603 mode, adjusted_mode); 604 /* 605 * the mode->clock is used to calculate the Data&Link M/N 606 * of the pipe. For the eDP the fixed clock should be used. 607 */ 608 mode->clock = dev_priv->panel_fixed_mode->clock; 609 } 610 611 for (lane_count = 1; lane_count <= max_lane_count; lane_count <<= 1) { 612 for (clock = 0; clock <= max_clock; clock++) { 613 int link_avail = intel_dp_max_data_rate(intel_dp_link_clock(bws[clock]), lane_count); 614 615 if (intel_dp_link_required(encoder->dev, intel_dp, mode->clock) 616 <= link_avail) { 617 intel_dp->link_bw = bws[clock]; 618 intel_dp->lane_count = lane_count; 619 adjusted_mode->clock = intel_dp_link_clock(intel_dp->link_bw); 620 DRM_DEBUG_KMS("Display port link bw %02x lane " 621 "count %d clock %d\n", 622 intel_dp->link_bw, intel_dp->lane_count, 623 adjusted_mode->clock); 624 return true; 625 } 626 } 627 } 628 629 if (is_edp(intel_dp)) { 630 /* okay we failed just pick the highest */ 631 intel_dp->lane_count = max_lane_count; 632 intel_dp->link_bw = bws[max_clock]; 633 adjusted_mode->clock = intel_dp_link_clock(intel_dp->link_bw); 634 DRM_DEBUG_KMS("Force picking display port link bw %02x lane " 635 "count %d clock %d\n", 636 intel_dp->link_bw, intel_dp->lane_count, 637 adjusted_mode->clock); 638 639 return true; 640 } 641 642 return false; 643} 644 645struct intel_dp_m_n { 646 uint32_t tu; 647 uint32_t gmch_m; 648 uint32_t gmch_n; 649 uint32_t link_m; 650 uint32_t link_n; 651}; 652 653static void 654intel_reduce_ratio(uint32_t *num, uint32_t *den) 655{ 656 while (*num > 0xffffff || *den > 0xffffff) { 657 *num >>= 1; 658 *den >>= 1; 659 } 660} 661 662static void 663intel_dp_compute_m_n(int bpp, 664 int nlanes, 665 int pixel_clock, 666 int link_clock, 667 struct intel_dp_m_n *m_n) 668{ 669 m_n->tu = 64; 670 m_n->gmch_m = (pixel_clock * bpp) >> 3; 671 m_n->gmch_n = link_clock * nlanes; 672 intel_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n); 673 m_n->link_m = pixel_clock; 674 m_n->link_n = link_clock; 675 intel_reduce_ratio(&m_n->link_m, &m_n->link_n); 676} 677 678void 679intel_dp_set_m_n(struct drm_crtc *crtc, struct drm_display_mode *mode, 680 struct drm_display_mode *adjusted_mode) 681{ 682 struct drm_device *dev = crtc->dev; 683 struct drm_mode_config *mode_config = &dev->mode_config; 684 struct drm_encoder *encoder; 685 struct drm_i915_private *dev_priv = dev->dev_private; 686 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 687 int lane_count = 4; 688 struct intel_dp_m_n m_n; 689 int pipe = intel_crtc->pipe; 690 691 /* 692 * Find the lane count in the intel_encoder private 693 */ 694 list_for_each_entry(encoder, &mode_config->encoder_list, head) { 695 struct intel_dp *intel_dp; 696 697 if (encoder->crtc != crtc) 698 continue; 699 700 intel_dp = enc_to_intel_dp(encoder); 701 if (intel_dp->base.type == INTEL_OUTPUT_DISPLAYPORT) { 702 lane_count = intel_dp->lane_count; 703 break; 704 } else if (is_edp(intel_dp)) { 705 lane_count = dev_priv->edp.lanes; 706 break; 707 } 708 } 709 710 /* 711 * Compute the GMCH and Link ratios. The '3' here is 712 * the number of bytes_per_pixel post-LUT, which we always 713 * set up for 8-bits of R/G/B, or 3 bytes total. 714 */ 715 intel_dp_compute_m_n(intel_crtc->bpp, lane_count, 716 mode->clock, adjusted_mode->clock, &m_n); 717 718 if (HAS_PCH_SPLIT(dev)) { 719 I915_WRITE(TRANSDATA_M1(pipe), 720 ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) | 721 m_n.gmch_m); 722 I915_WRITE(TRANSDATA_N1(pipe), m_n.gmch_n); 723 I915_WRITE(TRANSDPLINK_M1(pipe), m_n.link_m); 724 I915_WRITE(TRANSDPLINK_N1(pipe), m_n.link_n); 725 } else { 726 I915_WRITE(PIPE_GMCH_DATA_M(pipe), 727 ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) | 728 m_n.gmch_m); 729 I915_WRITE(PIPE_GMCH_DATA_N(pipe), m_n.gmch_n); 730 I915_WRITE(PIPE_DP_LINK_M(pipe), m_n.link_m); 731 I915_WRITE(PIPE_DP_LINK_N(pipe), m_n.link_n); 732 } 733} 734 735static void 736intel_dp_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode, 737 struct drm_display_mode *adjusted_mode) 738{ 739 struct drm_device *dev = encoder->dev; 740 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 741 struct drm_crtc *crtc = intel_dp->base.base.crtc; 742 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 743 744 intel_dp->DP = DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0; 745 intel_dp->DP |= intel_dp->color_range; 746 747 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) 748 intel_dp->DP |= DP_SYNC_HS_HIGH; 749 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) 750 intel_dp->DP |= DP_SYNC_VS_HIGH; 751 752 if (HAS_PCH_CPT(dev) && !is_edp(intel_dp)) 753 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT; 754 else 755 intel_dp->DP |= DP_LINK_TRAIN_OFF; 756 757 switch (intel_dp->lane_count) { 758 case 1: 759 intel_dp->DP |= DP_PORT_WIDTH_1; 760 break; 761 case 2: 762 intel_dp->DP |= DP_PORT_WIDTH_2; 763 break; 764 case 4: 765 intel_dp->DP |= DP_PORT_WIDTH_4; 766 break; 767 } 768 if (intel_dp->has_audio) 769 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE; 770 771 memset(intel_dp->link_configuration, 0, DP_LINK_CONFIGURATION_SIZE); 772 intel_dp->link_configuration[0] = intel_dp->link_bw; 773 intel_dp->link_configuration[1] = intel_dp->lane_count; 774 775 /* 776 * Check for DPCD version > 1.1 and enhanced framing support 777 */ 778 if (intel_dp->dpcd[0] >= 0x11 && (intel_dp->dpcd[2] & DP_ENHANCED_FRAME_CAP)) { 779 intel_dp->link_configuration[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN; 780 intel_dp->DP |= DP_ENHANCED_FRAMING; 781 } 782 783 /* CPT DP's pipe select is decided in TRANS_DP_CTL */ 784 if (intel_crtc->pipe == 1 && !HAS_PCH_CPT(dev)) 785 intel_dp->DP |= DP_PIPEB_SELECT; 786 787 if (is_edp(intel_dp) && !is_pch_edp(intel_dp)) { 788 /* don't miss out required setting for eDP */ 789 intel_dp->DP |= DP_PLL_ENABLE; 790 if (adjusted_mode->clock < 200000) 791 intel_dp->DP |= DP_PLL_FREQ_160MHZ; 792 else 793 intel_dp->DP |= DP_PLL_FREQ_270MHZ; 794 } 795} 796 797static void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp) 798{ 799 struct drm_device *dev = intel_dp->base.base.dev; 800 struct drm_i915_private *dev_priv = dev->dev_private; 801 u32 pp; 802 803 /* 804 * If the panel wasn't on, make sure there's not a currently 805 * active PP sequence before enabling AUX VDD. 806 */ 807 if (!(I915_READ(PCH_PP_STATUS) & PP_ON)) 808 msleep(dev_priv->panel_t3); 809 810 pp = I915_READ(PCH_PP_CONTROL); 811 pp |= EDP_FORCE_VDD; 812 I915_WRITE(PCH_PP_CONTROL, pp); 813 POSTING_READ(PCH_PP_CONTROL); 814} 815 816static void ironlake_edp_panel_vdd_off(struct intel_dp *intel_dp) 817{ 818 struct drm_device *dev = intel_dp->base.base.dev; 819 struct drm_i915_private *dev_priv = dev->dev_private; 820 u32 pp; 821 822 pp = I915_READ(PCH_PP_CONTROL); 823 pp &= ~EDP_FORCE_VDD; 824 I915_WRITE(PCH_PP_CONTROL, pp); 825 POSTING_READ(PCH_PP_CONTROL); 826 827 /* Make sure sequencer is idle before allowing subsequent activity */ 828 msleep(dev_priv->panel_t12); 829} 830 831/* Returns true if the panel was already on when called */ 832static bool ironlake_edp_panel_on (struct intel_dp *intel_dp) 833{ 834 struct drm_device *dev = intel_dp->base.base.dev; 835 struct drm_i915_private *dev_priv = dev->dev_private; 836 u32 pp, idle_on_mask = PP_ON | PP_SEQUENCE_STATE_ON_IDLE; 837 838 if (I915_READ(PCH_PP_STATUS) & PP_ON) 839 return true; 840 841 pp = I915_READ(PCH_PP_CONTROL); 842 843 /* ILK workaround: disable reset around power sequence */ 844 pp &= ~PANEL_POWER_RESET; 845 I915_WRITE(PCH_PP_CONTROL, pp); 846 POSTING_READ(PCH_PP_CONTROL); 847 848 pp |= PANEL_UNLOCK_REGS | POWER_TARGET_ON; 849 I915_WRITE(PCH_PP_CONTROL, pp); 850 POSTING_READ(PCH_PP_CONTROL); 851 852 if (wait_for((I915_READ(PCH_PP_STATUS) & idle_on_mask) == idle_on_mask, 853 5000)) 854 DRM_ERROR("panel on wait timed out: 0x%08x\n", 855 I915_READ(PCH_PP_STATUS)); 856 857 pp |= PANEL_POWER_RESET; /* restore panel reset bit */ 858 I915_WRITE(PCH_PP_CONTROL, pp); 859 POSTING_READ(PCH_PP_CONTROL); 860 861 return false; 862} 863 864static void ironlake_edp_panel_off (struct drm_device *dev) 865{ 866 struct drm_i915_private *dev_priv = dev->dev_private; 867 u32 pp, idle_off_mask = PP_ON | PP_SEQUENCE_MASK | 868 PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK; 869 870 pp = I915_READ(PCH_PP_CONTROL); 871 872 /* ILK workaround: disable reset around power sequence */ 873 pp &= ~PANEL_POWER_RESET; 874 I915_WRITE(PCH_PP_CONTROL, pp); 875 POSTING_READ(PCH_PP_CONTROL); 876 877 pp &= ~POWER_TARGET_ON; 878 I915_WRITE(PCH_PP_CONTROL, pp); 879 POSTING_READ(PCH_PP_CONTROL); 880 881 if (wait_for((I915_READ(PCH_PP_STATUS) & idle_off_mask) == 0, 5000)) 882 DRM_ERROR("panel off wait timed out: 0x%08x\n", 883 I915_READ(PCH_PP_STATUS)); 884 885 pp |= PANEL_POWER_RESET; /* restore panel reset bit */ 886 I915_WRITE(PCH_PP_CONTROL, pp); 887 POSTING_READ(PCH_PP_CONTROL); 888} 889 890static void ironlake_edp_backlight_on (struct drm_device *dev) 891{ 892 struct drm_i915_private *dev_priv = dev->dev_private; 893 u32 pp; 894 895 DRM_DEBUG_KMS("\n"); 896 /* 897 * If we enable the backlight right away following a panel power 898 * on, we may see slight flicker as the panel syncs with the eDP 899 * link. So delay a bit to make sure the image is solid before 900 * allowing it to appear. 901 */ 902 msleep(300); 903 pp = I915_READ(PCH_PP_CONTROL); 904 pp |= EDP_BLC_ENABLE; 905 I915_WRITE(PCH_PP_CONTROL, pp); 906} 907 908static void ironlake_edp_backlight_off (struct drm_device *dev) 909{ 910 struct drm_i915_private *dev_priv = dev->dev_private; 911 u32 pp; 912 913 DRM_DEBUG_KMS("\n"); 914 pp = I915_READ(PCH_PP_CONTROL); 915 pp &= ~EDP_BLC_ENABLE; 916 I915_WRITE(PCH_PP_CONTROL, pp); 917} 918 919static void ironlake_edp_pll_on(struct drm_encoder *encoder) 920{ 921 struct drm_device *dev = encoder->dev; 922 struct drm_i915_private *dev_priv = dev->dev_private; 923 u32 dpa_ctl; 924 925 DRM_DEBUG_KMS("\n"); 926 dpa_ctl = I915_READ(DP_A); 927 dpa_ctl |= DP_PLL_ENABLE; 928 I915_WRITE(DP_A, dpa_ctl); 929 POSTING_READ(DP_A); 930 udelay(200); 931} 932 933static void ironlake_edp_pll_off(struct drm_encoder *encoder) 934{ 935 struct drm_device *dev = encoder->dev; 936 struct drm_i915_private *dev_priv = dev->dev_private; 937 u32 dpa_ctl; 938 939 dpa_ctl = I915_READ(DP_A); 940 dpa_ctl &= ~DP_PLL_ENABLE; 941 I915_WRITE(DP_A, dpa_ctl); 942 POSTING_READ(DP_A); 943 udelay(200); 944} 945 946static void intel_dp_prepare(struct drm_encoder *encoder) 947{ 948 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 949 struct drm_device *dev = encoder->dev; 950 951 if (is_edp(intel_dp)) { 952 ironlake_edp_backlight_off(dev); 953 ironlake_edp_panel_off(dev); 954 if (!is_pch_edp(intel_dp)) 955 ironlake_edp_pll_on(encoder); 956 else 957 ironlake_edp_pll_off(encoder); 958 } 959 intel_dp_link_down(intel_dp); 960} 961 962static void intel_dp_commit(struct drm_encoder *encoder) 963{ 964 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 965 struct drm_device *dev = encoder->dev; 966 967 if (is_edp(intel_dp)) 968 ironlake_edp_panel_vdd_on(intel_dp); 969 970 intel_dp_start_link_train(intel_dp); 971 972 if (is_edp(intel_dp)) { 973 ironlake_edp_panel_on(intel_dp); 974 ironlake_edp_panel_vdd_off(intel_dp); 975 } 976 977 intel_dp_complete_link_train(intel_dp); 978 979 if (is_edp(intel_dp)) 980 ironlake_edp_backlight_on(dev); 981} 982 983static void 984intel_dp_dpms(struct drm_encoder *encoder, int mode) 985{ 986 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 987 struct drm_device *dev = encoder->dev; 988 struct drm_i915_private *dev_priv = dev->dev_private; 989 uint32_t dp_reg = I915_READ(intel_dp->output_reg); 990 991 if (mode != DRM_MODE_DPMS_ON) { 992 if (is_edp(intel_dp)) 993 ironlake_edp_backlight_off(dev); 994 intel_dp_link_down(intel_dp); 995 if (is_edp(intel_dp)) 996 ironlake_edp_panel_off(dev); 997 if (is_edp(intel_dp) && !is_pch_edp(intel_dp)) 998 ironlake_edp_pll_off(encoder); 999 } else { 1000 if (is_edp(intel_dp)) 1001 ironlake_edp_panel_vdd_on(intel_dp); 1002 if (!(dp_reg & DP_PORT_EN)) { 1003 intel_dp_start_link_train(intel_dp); 1004 if (is_edp(intel_dp)) { 1005 ironlake_edp_panel_on(intel_dp); 1006 ironlake_edp_panel_vdd_off(intel_dp); 1007 } 1008 intel_dp_complete_link_train(intel_dp); 1009 } 1010 if (is_edp(intel_dp)) 1011 ironlake_edp_backlight_on(dev); 1012 } 1013 intel_dp->dpms_mode = mode; 1014} 1015 1016/* 1017 * Fetch AUX CH registers 0x202 - 0x207 which contain 1018 * link status information 1019 */ 1020static bool 1021intel_dp_get_link_status(struct intel_dp *intel_dp) 1022{ 1023 int ret; 1024 1025 ret = intel_dp_aux_native_read(intel_dp, 1026 DP_LANE0_1_STATUS, 1027 intel_dp->link_status, DP_LINK_STATUS_SIZE); 1028 if (ret != DP_LINK_STATUS_SIZE) 1029 return false; 1030 return true; 1031} 1032 1033static uint8_t 1034intel_dp_link_status(uint8_t link_status[DP_LINK_STATUS_SIZE], 1035 int r) 1036{ 1037 return link_status[r - DP_LANE0_1_STATUS]; 1038} 1039 1040static uint8_t 1041intel_get_adjust_request_voltage(uint8_t link_status[DP_LINK_STATUS_SIZE], 1042 int lane) 1043{ 1044 int i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1); 1045 int s = ((lane & 1) ? 1046 DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT : 1047 DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT); 1048 uint8_t l = intel_dp_link_status(link_status, i); 1049 1050 return ((l >> s) & 3) << DP_TRAIN_VOLTAGE_SWING_SHIFT; 1051} 1052 1053static uint8_t 1054intel_get_adjust_request_pre_emphasis(uint8_t link_status[DP_LINK_STATUS_SIZE], 1055 int lane) 1056{ 1057 int i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1); 1058 int s = ((lane & 1) ? 1059 DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT : 1060 DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT); 1061 uint8_t l = intel_dp_link_status(link_status, i); 1062 1063 return ((l >> s) & 3) << DP_TRAIN_PRE_EMPHASIS_SHIFT; 1064} 1065 1066 1067#if 0 1068static char *voltage_names[] = { 1069 "0.4V", "0.6V", "0.8V", "1.2V" 1070}; 1071static char *pre_emph_names[] = { 1072 "0dB", "3.5dB", "6dB", "9.5dB" 1073}; 1074static char *link_train_names[] = { 1075 "pattern 1", "pattern 2", "idle", "off" 1076}; 1077#endif 1078 1079/* 1080 * These are source-specific values; current Intel hardware supports 1081 * a maximum voltage of 800mV and a maximum pre-emphasis of 6dB 1082 */ 1083#define I830_DP_VOLTAGE_MAX DP_TRAIN_VOLTAGE_SWING_800 1084 1085static uint8_t 1086intel_dp_pre_emphasis_max(uint8_t voltage_swing) 1087{ 1088 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) { 1089 case DP_TRAIN_VOLTAGE_SWING_400: 1090 return DP_TRAIN_PRE_EMPHASIS_6; 1091 case DP_TRAIN_VOLTAGE_SWING_600: 1092 return DP_TRAIN_PRE_EMPHASIS_6; 1093 case DP_TRAIN_VOLTAGE_SWING_800: 1094 return DP_TRAIN_PRE_EMPHASIS_3_5; 1095 case DP_TRAIN_VOLTAGE_SWING_1200: 1096 default: 1097 return DP_TRAIN_PRE_EMPHASIS_0; 1098 } 1099} 1100 1101static void 1102intel_get_adjust_train(struct intel_dp *intel_dp) 1103{ 1104 uint8_t v = 0; 1105 uint8_t p = 0; 1106 int lane; 1107 1108 for (lane = 0; lane < intel_dp->lane_count; lane++) { 1109 uint8_t this_v = intel_get_adjust_request_voltage(intel_dp->link_status, lane); 1110 uint8_t this_p = intel_get_adjust_request_pre_emphasis(intel_dp->link_status, lane); 1111 1112 if (this_v > v) 1113 v = this_v; 1114 if (this_p > p) 1115 p = this_p; 1116 } 1117 1118 if (v >= I830_DP_VOLTAGE_MAX) 1119 v = I830_DP_VOLTAGE_MAX | DP_TRAIN_MAX_SWING_REACHED; 1120 1121 if (p >= intel_dp_pre_emphasis_max(v)) 1122 p = intel_dp_pre_emphasis_max(v) | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED; 1123 1124 for (lane = 0; lane < 4; lane++) 1125 intel_dp->train_set[lane] = v | p; 1126} 1127 1128static uint32_t 1129intel_dp_signal_levels(uint8_t train_set, int lane_count) 1130{ 1131 uint32_t signal_levels = 0; 1132 1133 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { 1134 case DP_TRAIN_VOLTAGE_SWING_400: 1135 default: 1136 signal_levels |= DP_VOLTAGE_0_4; 1137 break; 1138 case DP_TRAIN_VOLTAGE_SWING_600: 1139 signal_levels |= DP_VOLTAGE_0_6; 1140 break; 1141 case DP_TRAIN_VOLTAGE_SWING_800: 1142 signal_levels |= DP_VOLTAGE_0_8; 1143 break; 1144 case DP_TRAIN_VOLTAGE_SWING_1200: 1145 signal_levels |= DP_VOLTAGE_1_2; 1146 break; 1147 } 1148 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) { 1149 case DP_TRAIN_PRE_EMPHASIS_0: 1150 default: 1151 signal_levels |= DP_PRE_EMPHASIS_0; 1152 break; 1153 case DP_TRAIN_PRE_EMPHASIS_3_5: 1154 signal_levels |= DP_PRE_EMPHASIS_3_5; 1155 break; 1156 case DP_TRAIN_PRE_EMPHASIS_6: 1157 signal_levels |= DP_PRE_EMPHASIS_6; 1158 break; 1159 case DP_TRAIN_PRE_EMPHASIS_9_5: 1160 signal_levels |= DP_PRE_EMPHASIS_9_5; 1161 break; 1162 } 1163 return signal_levels; 1164} 1165 1166/* Gen6's DP voltage swing and pre-emphasis control */ 1167static uint32_t 1168intel_gen6_edp_signal_levels(uint8_t train_set) 1169{ 1170 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK | 1171 DP_TRAIN_PRE_EMPHASIS_MASK); 1172 switch (signal_levels) { 1173 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0: 1174 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0: 1175 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B; 1176 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5: 1177 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B; 1178 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6: 1179 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6: 1180 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B; 1181 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5: 1182 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5: 1183 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B; 1184 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0: 1185 case DP_TRAIN_VOLTAGE_SWING_1200 | DP_TRAIN_PRE_EMPHASIS_0: 1186 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B; 1187 default: 1188 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:" 1189 "0x%x\n", signal_levels); 1190 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B; 1191 } 1192} 1193 1194static uint8_t 1195intel_get_lane_status(uint8_t link_status[DP_LINK_STATUS_SIZE], 1196 int lane) 1197{ 1198 int i = DP_LANE0_1_STATUS + (lane >> 1); 1199 int s = (lane & 1) * 4; 1200 uint8_t l = intel_dp_link_status(link_status, i); 1201 1202 return (l >> s) & 0xf; 1203} 1204 1205/* Check for clock recovery is done on all channels */ 1206static bool 1207intel_clock_recovery_ok(uint8_t link_status[DP_LINK_STATUS_SIZE], int lane_count) 1208{ 1209 int lane; 1210 uint8_t lane_status; 1211 1212 for (lane = 0; lane < lane_count; lane++) { 1213 lane_status = intel_get_lane_status(link_status, lane); 1214 if ((lane_status & DP_LANE_CR_DONE) == 0) 1215 return false; 1216 } 1217 return true; 1218} 1219 1220/* Check to see if channel eq is done on all channels */ 1221#define CHANNEL_EQ_BITS (DP_LANE_CR_DONE|\ 1222 DP_LANE_CHANNEL_EQ_DONE|\ 1223 DP_LANE_SYMBOL_LOCKED) 1224static bool 1225intel_channel_eq_ok(struct intel_dp *intel_dp) 1226{ 1227 uint8_t lane_align; 1228 uint8_t lane_status; 1229 int lane; 1230 1231 lane_align = intel_dp_link_status(intel_dp->link_status, 1232 DP_LANE_ALIGN_STATUS_UPDATED); 1233 if ((lane_align & DP_INTERLANE_ALIGN_DONE) == 0) 1234 return false; 1235 for (lane = 0; lane < intel_dp->lane_count; lane++) { 1236 lane_status = intel_get_lane_status(intel_dp->link_status, lane); 1237 if ((lane_status & CHANNEL_EQ_BITS) != CHANNEL_EQ_BITS) 1238 return false; 1239 } 1240 return true; 1241} 1242 1243static bool 1244intel_dp_set_link_train(struct intel_dp *intel_dp, 1245 uint32_t dp_reg_value, 1246 uint8_t dp_train_pat) 1247{ 1248 struct drm_device *dev = intel_dp->base.base.dev; 1249 struct drm_i915_private *dev_priv = dev->dev_private; 1250 int ret; 1251 1252 I915_WRITE(intel_dp->output_reg, dp_reg_value); 1253 POSTING_READ(intel_dp->output_reg); 1254 1255 intel_dp_aux_native_write_1(intel_dp, 1256 DP_TRAINING_PATTERN_SET, 1257 dp_train_pat); 1258 1259 ret = intel_dp_aux_native_write(intel_dp, 1260 DP_TRAINING_LANE0_SET, 1261 intel_dp->train_set, 4); 1262 if (ret != 4) 1263 return false; 1264 1265 return true; 1266} 1267 1268/* Enable corresponding port and start training pattern 1 */ 1269static void 1270intel_dp_start_link_train(struct intel_dp *intel_dp) 1271{ 1272 struct drm_device *dev = intel_dp->base.base.dev; 1273 struct drm_i915_private *dev_priv = dev->dev_private; 1274 struct intel_crtc *intel_crtc = to_intel_crtc(intel_dp->base.base.crtc); 1275 int i; 1276 uint8_t voltage; 1277 bool clock_recovery = false; 1278 int tries; 1279 u32 reg; 1280 uint32_t DP = intel_dp->DP; 1281 1282 /* Enable output, wait for it to become active */ 1283 I915_WRITE(intel_dp->output_reg, intel_dp->DP); 1284 POSTING_READ(intel_dp->output_reg); 1285 intel_wait_for_vblank(dev, intel_crtc->pipe); 1286 1287 /* Write the link configuration data */ 1288 intel_dp_aux_native_write(intel_dp, DP_LINK_BW_SET, 1289 intel_dp->link_configuration, 1290 DP_LINK_CONFIGURATION_SIZE); 1291 1292 DP |= DP_PORT_EN; 1293 if (HAS_PCH_CPT(dev) && !is_edp(intel_dp)) 1294 DP &= ~DP_LINK_TRAIN_MASK_CPT; 1295 else 1296 DP &= ~DP_LINK_TRAIN_MASK; 1297 memset(intel_dp->train_set, 0, 4); 1298 voltage = 0xff; 1299 tries = 0; 1300 clock_recovery = false; 1301 for (;;) { 1302 /* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */ 1303 uint32_t signal_levels; 1304 if (IS_GEN6(dev) && is_edp(intel_dp)) { 1305 signal_levels = intel_gen6_edp_signal_levels(intel_dp->train_set[0]); 1306 DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB) | signal_levels; 1307 } else { 1308 signal_levels = intel_dp_signal_levels(intel_dp->train_set[0], intel_dp->lane_count); 1309 DP = (DP & ~(DP_VOLTAGE_MASK|DP_PRE_EMPHASIS_MASK)) | signal_levels; 1310 } 1311 1312 if (HAS_PCH_CPT(dev) && !is_edp(intel_dp)) 1313 reg = DP | DP_LINK_TRAIN_PAT_1_CPT; 1314 else 1315 reg = DP | DP_LINK_TRAIN_PAT_1; 1316 1317 if (!intel_dp_set_link_train(intel_dp, reg, 1318 DP_TRAINING_PATTERN_1)) 1319 break; 1320 /* Set training pattern 1 */ 1321 1322 udelay(100); 1323 if (!intel_dp_get_link_status(intel_dp)) 1324 break; 1325 1326 if (intel_clock_recovery_ok(intel_dp->link_status, intel_dp->lane_count)) { 1327 clock_recovery = true; 1328 break; 1329 } 1330 1331 /* Check to see if we've tried the max voltage */ 1332 for (i = 0; i < intel_dp->lane_count; i++) 1333 if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0) 1334 break; 1335 if (i == intel_dp->lane_count) 1336 break; 1337 1338 /* Check to see if we've tried the same voltage 5 times */ 1339 if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) { 1340 ++tries; 1341 if (tries == 5) 1342 break; 1343 } else 1344 tries = 0; 1345 voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK; 1346 1347 /* Compute new intel_dp->train_set as requested by target */ 1348 intel_get_adjust_train(intel_dp); 1349 } 1350 1351 intel_dp->DP = DP; 1352} 1353 1354static void 1355intel_dp_complete_link_train(struct intel_dp *intel_dp) 1356{ 1357 struct drm_device *dev = intel_dp->base.base.dev; 1358 struct drm_i915_private *dev_priv = dev->dev_private; 1359 bool channel_eq = false; 1360 int tries, cr_tries; 1361 u32 reg; 1362 uint32_t DP = intel_dp->DP; 1363 1364 /* channel equalization */ 1365 tries = 0; 1366 cr_tries = 0; 1367 channel_eq = false; 1368 for (;;) { 1369 /* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */ 1370 uint32_t signal_levels; 1371 1372 if (cr_tries > 5) { 1373 DRM_ERROR("failed to train DP, aborting\n"); 1374 intel_dp_link_down(intel_dp); 1375 break; 1376 } 1377 1378 if (IS_GEN6(dev) && is_edp(intel_dp)) { 1379 signal_levels = intel_gen6_edp_signal_levels(intel_dp->train_set[0]); 1380 DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB) | signal_levels; 1381 } else { 1382 signal_levels = intel_dp_signal_levels(intel_dp->train_set[0], intel_dp->lane_count); 1383 DP = (DP & ~(DP_VOLTAGE_MASK|DP_PRE_EMPHASIS_MASK)) | signal_levels; 1384 } 1385 1386 if (HAS_PCH_CPT(dev) && !is_edp(intel_dp)) 1387 reg = DP | DP_LINK_TRAIN_PAT_2_CPT; 1388 else 1389 reg = DP | DP_LINK_TRAIN_PAT_2; 1390 1391 /* channel eq pattern */ 1392 if (!intel_dp_set_link_train(intel_dp, reg, 1393 DP_TRAINING_PATTERN_2)) 1394 break; 1395 1396 udelay(400); 1397 if (!intel_dp_get_link_status(intel_dp)) 1398 break; 1399 1400 /* Make sure clock is still ok */ 1401 if (!intel_clock_recovery_ok(intel_dp->link_status, intel_dp->lane_count)) { 1402 intel_dp_start_link_train(intel_dp); 1403 cr_tries++; 1404 continue; 1405 } 1406 1407 if (intel_channel_eq_ok(intel_dp)) { 1408 channel_eq = true; 1409 break; 1410 } 1411 1412 /* Try 5 times, then try clock recovery if that fails */ 1413 if (tries > 5) { 1414 intel_dp_link_down(intel_dp); 1415 intel_dp_start_link_train(intel_dp); 1416 tries = 0; 1417 cr_tries++; 1418 continue; 1419 } 1420 1421 /* Compute new intel_dp->train_set as requested by target */ 1422 intel_get_adjust_train(intel_dp); 1423 ++tries; 1424 } 1425 1426 if (HAS_PCH_CPT(dev) && !is_edp(intel_dp)) 1427 reg = DP | DP_LINK_TRAIN_OFF_CPT; 1428 else 1429 reg = DP | DP_LINK_TRAIN_OFF; 1430 1431 I915_WRITE(intel_dp->output_reg, reg); 1432 POSTING_READ(intel_dp->output_reg); 1433 intel_dp_aux_native_write_1(intel_dp, 1434 DP_TRAINING_PATTERN_SET, DP_TRAINING_PATTERN_DISABLE); 1435} 1436 1437static void 1438intel_dp_link_down(struct intel_dp *intel_dp) 1439{ 1440 struct drm_device *dev = intel_dp->base.base.dev; 1441 struct drm_i915_private *dev_priv = dev->dev_private; 1442 uint32_t DP = intel_dp->DP; 1443 1444 if ((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0) 1445 return; 1446 1447 DRM_DEBUG_KMS("\n"); 1448 1449 if (is_edp(intel_dp)) { 1450 DP &= ~DP_PLL_ENABLE; 1451 I915_WRITE(intel_dp->output_reg, DP); 1452 POSTING_READ(intel_dp->output_reg); 1453 udelay(100); 1454 } 1455 1456 if (HAS_PCH_CPT(dev) && !is_edp(intel_dp)) { 1457 DP &= ~DP_LINK_TRAIN_MASK_CPT; 1458 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT); 1459 } else { 1460 DP &= ~DP_LINK_TRAIN_MASK; 1461 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE); 1462 } 1463 POSTING_READ(intel_dp->output_reg); 1464 1465 msleep(17); 1466 1467 if (is_edp(intel_dp)) 1468 DP |= DP_LINK_TRAIN_OFF; 1469 1470 if (!HAS_PCH_CPT(dev) && 1471 I915_READ(intel_dp->output_reg) & DP_PIPEB_SELECT) { 1472 struct drm_crtc *crtc = intel_dp->base.base.crtc; 1473 1474 /* Hardware workaround: leaving our transcoder select 1475 * set to transcoder B while it's off will prevent the 1476 * corresponding HDMI output on transcoder A. 1477 * 1478 * Combine this with another hardware workaround: 1479 * transcoder select bit can only be cleared while the 1480 * port is enabled. 1481 */ 1482 DP &= ~DP_PIPEB_SELECT; 1483 I915_WRITE(intel_dp->output_reg, DP); 1484 1485 /* Changes to enable or select take place the vblank 1486 * after being written. 1487 */ 1488 if (crtc == NULL) { 1489 /* We can arrive here never having been attached 1490 * to a CRTC, for instance, due to inheriting 1491 * random state from the BIOS. 1492 * 1493 * If the pipe is not running, play safe and 1494 * wait for the clocks to stabilise before 1495 * continuing. 1496 */ 1497 POSTING_READ(intel_dp->output_reg); 1498 msleep(50); 1499 } else 1500 intel_wait_for_vblank(dev, to_intel_crtc(crtc)->pipe); 1501 } 1502 1503 I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN); 1504 POSTING_READ(intel_dp->output_reg); 1505} 1506 1507/* 1508 * According to DP spec 1509 * 5.1.2: 1510 * 1. Read DPCD 1511 * 2. Configure link according to Receiver Capabilities 1512 * 3. Use Link Training from 2.5.3.3 and 3.5.1.3 1513 * 4. Check link status on receipt of hot-plug interrupt 1514 */ 1515 1516static void 1517intel_dp_check_link_status(struct intel_dp *intel_dp) 1518{ 1519 if (!intel_dp->base.base.crtc) 1520 return; 1521 1522 if (!intel_dp_get_link_status(intel_dp)) { 1523 intel_dp_link_down(intel_dp); 1524 return; 1525 } 1526 1527 if (!intel_channel_eq_ok(intel_dp)) { 1528 intel_dp_start_link_train(intel_dp); 1529 intel_dp_complete_link_train(intel_dp); 1530 } 1531} 1532 1533static enum drm_connector_status 1534ironlake_dp_detect(struct intel_dp *intel_dp) 1535{ 1536 enum drm_connector_status status; 1537 1538 /* Can't disconnect eDP, but you can close the lid... */ 1539 if (is_edp(intel_dp)) { 1540 status = intel_panel_detect(intel_dp->base.base.dev); 1541 if (status == connector_status_unknown) 1542 status = connector_status_connected; 1543 return status; 1544 } 1545 1546 status = connector_status_disconnected; 1547 if (intel_dp_aux_native_read(intel_dp, 1548 0x000, intel_dp->dpcd, 1549 sizeof (intel_dp->dpcd)) 1550 == sizeof(intel_dp->dpcd)) { 1551 if (intel_dp->dpcd[0] != 0) 1552 status = connector_status_connected; 1553 } 1554 DRM_DEBUG_KMS("DPCD: %hx%hx%hx%hx\n", intel_dp->dpcd[0], 1555 intel_dp->dpcd[1], intel_dp->dpcd[2], intel_dp->dpcd[3]); 1556 return status; 1557} 1558 1559static enum drm_connector_status 1560g4x_dp_detect(struct intel_dp *intel_dp) 1561{ 1562 struct drm_device *dev = intel_dp->base.base.dev; 1563 struct drm_i915_private *dev_priv = dev->dev_private; 1564 enum drm_connector_status status; 1565 uint32_t temp, bit; 1566 1567 switch (intel_dp->output_reg) { 1568 case DP_B: 1569 bit = DPB_HOTPLUG_INT_STATUS; 1570 break; 1571 case DP_C: 1572 bit = DPC_HOTPLUG_INT_STATUS; 1573 break; 1574 case DP_D: 1575 bit = DPD_HOTPLUG_INT_STATUS; 1576 break; 1577 default: 1578 return connector_status_unknown; 1579 } 1580 1581 temp = I915_READ(PORT_HOTPLUG_STAT); 1582 1583 if ((temp & bit) == 0) 1584 return connector_status_disconnected; 1585 1586 status = connector_status_disconnected; 1587 if (intel_dp_aux_native_read(intel_dp, 0x000, intel_dp->dpcd, 1588 sizeof (intel_dp->dpcd)) == sizeof (intel_dp->dpcd)) 1589 { 1590 if (intel_dp->dpcd[0] != 0) 1591 status = connector_status_connected; 1592 } 1593 1594 return status; 1595} 1596 1597/** 1598 * Uses CRT_HOTPLUG_EN and CRT_HOTPLUG_STAT to detect DP connection. 1599 * 1600 * \return true if DP port is connected. 1601 * \return false if DP port is disconnected. 1602 */ 1603static enum drm_connector_status 1604intel_dp_detect(struct drm_connector *connector, bool force) 1605{ 1606 struct intel_dp *intel_dp = intel_attached_dp(connector); 1607 struct drm_device *dev = intel_dp->base.base.dev; 1608 enum drm_connector_status status; 1609 struct edid *edid = NULL; 1610 1611 intel_dp->has_audio = false; 1612 1613 if (HAS_PCH_SPLIT(dev)) 1614 status = ironlake_dp_detect(intel_dp); 1615 else 1616 status = g4x_dp_detect(intel_dp); 1617 if (status != connector_status_connected) 1618 return status; 1619 1620 if (intel_dp->force_audio) { 1621 intel_dp->has_audio = intel_dp->force_audio > 0; 1622 } else { 1623 edid = drm_get_edid(connector, &intel_dp->adapter); 1624 if (edid) { 1625 intel_dp->has_audio = drm_detect_monitor_audio(edid); 1626 connector->display_info.raw_edid = NULL; 1627 kfree(edid); 1628 } 1629 } 1630 1631 return connector_status_connected; 1632} 1633 1634static int intel_dp_get_modes(struct drm_connector *connector) 1635{ 1636 struct intel_dp *intel_dp = intel_attached_dp(connector); 1637 struct drm_device *dev = intel_dp->base.base.dev; 1638 struct drm_i915_private *dev_priv = dev->dev_private; 1639 int ret; 1640 1641 /* We should parse the EDID data and find out if it has an audio sink 1642 */ 1643 1644 ret = intel_ddc_get_modes(connector, &intel_dp->adapter); 1645 if (ret) { 1646 if (is_edp(intel_dp) && !dev_priv->panel_fixed_mode) { 1647 struct drm_display_mode *newmode; 1648 list_for_each_entry(newmode, &connector->probed_modes, 1649 head) { 1650 if (newmode->type & DRM_MODE_TYPE_PREFERRED) { 1651 dev_priv->panel_fixed_mode = 1652 drm_mode_duplicate(dev, newmode); 1653 break; 1654 } 1655 } 1656 } 1657 1658 return ret; 1659 } 1660 1661 /* if eDP has no EDID, try to use fixed panel mode from VBT */ 1662 if (is_edp(intel_dp)) { 1663 if (dev_priv->panel_fixed_mode != NULL) { 1664 struct drm_display_mode *mode; 1665 mode = drm_mode_duplicate(dev, dev_priv->panel_fixed_mode); 1666 drm_mode_probed_add(connector, mode); 1667 return 1; 1668 } 1669 } 1670 return 0; 1671} 1672 1673static bool 1674intel_dp_detect_audio(struct drm_connector *connector) 1675{ 1676 struct intel_dp *intel_dp = intel_attached_dp(connector); 1677 struct edid *edid; 1678 bool has_audio = false; 1679 1680 edid = drm_get_edid(connector, &intel_dp->adapter); 1681 if (edid) { 1682 has_audio = drm_detect_monitor_audio(edid); 1683 1684 connector->display_info.raw_edid = NULL; 1685 kfree(edid); 1686 } 1687 1688 return has_audio; 1689} 1690 1691static int 1692intel_dp_set_property(struct drm_connector *connector, 1693 struct drm_property *property, 1694 uint64_t val) 1695{ 1696 struct drm_i915_private *dev_priv = connector->dev->dev_private; 1697 struct intel_dp *intel_dp = intel_attached_dp(connector); 1698 int ret; 1699 1700 ret = drm_connector_property_set_value(connector, property, val); 1701 if (ret) 1702 return ret; 1703 1704 if (property == dev_priv->force_audio_property) { 1705 int i = val; 1706 bool has_audio; 1707 1708 if (i == intel_dp->force_audio) 1709 return 0; 1710 1711 intel_dp->force_audio = i; 1712 1713 if (i == 0) 1714 has_audio = intel_dp_detect_audio(connector); 1715 else 1716 has_audio = i > 0; 1717 1718 if (has_audio == intel_dp->has_audio) 1719 return 0; 1720 1721 intel_dp->has_audio = has_audio; 1722 goto done; 1723 } 1724 1725 if (property == dev_priv->broadcast_rgb_property) { 1726 if (val == !!intel_dp->color_range) 1727 return 0; 1728 1729 intel_dp->color_range = val ? DP_COLOR_RANGE_16_235 : 0; 1730 goto done; 1731 } 1732 1733 return -EINVAL; 1734 1735done: 1736 if (intel_dp->base.base.crtc) { 1737 struct drm_crtc *crtc = intel_dp->base.base.crtc; 1738 drm_crtc_helper_set_mode(crtc, &crtc->mode, 1739 crtc->x, crtc->y, 1740 crtc->fb); 1741 } 1742 1743 return 0; 1744} 1745 1746static void 1747intel_dp_destroy (struct drm_connector *connector) 1748{ 1749 drm_sysfs_connector_remove(connector); 1750 drm_connector_cleanup(connector); 1751 kfree(connector); 1752} 1753 1754static void intel_dp_encoder_destroy(struct drm_encoder *encoder) 1755{ 1756 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 1757 1758 i2c_del_adapter(&intel_dp->adapter); 1759 drm_encoder_cleanup(encoder); 1760 kfree(intel_dp); 1761} 1762 1763static const struct drm_encoder_helper_funcs intel_dp_helper_funcs = { 1764 .dpms = intel_dp_dpms, 1765 .mode_fixup = intel_dp_mode_fixup, 1766 .prepare = intel_dp_prepare, 1767 .mode_set = intel_dp_mode_set, 1768 .commit = intel_dp_commit, 1769}; 1770 1771static const struct drm_connector_funcs intel_dp_connector_funcs = { 1772 .dpms = drm_helper_connector_dpms, 1773 .detect = intel_dp_detect, 1774 .fill_modes = drm_helper_probe_single_connector_modes, 1775 .set_property = intel_dp_set_property, 1776 .destroy = intel_dp_destroy, 1777}; 1778 1779static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = { 1780 .get_modes = intel_dp_get_modes, 1781 .mode_valid = intel_dp_mode_valid, 1782 .best_encoder = intel_best_encoder, 1783}; 1784 1785static const struct drm_encoder_funcs intel_dp_enc_funcs = { 1786 .destroy = intel_dp_encoder_destroy, 1787}; 1788 1789static void 1790intel_dp_hot_plug(struct intel_encoder *intel_encoder) 1791{ 1792 struct intel_dp *intel_dp = container_of(intel_encoder, struct intel_dp, base); 1793 1794 if (intel_dp->dpms_mode == DRM_MODE_DPMS_ON) 1795 intel_dp_check_link_status(intel_dp); 1796} 1797 1798/* Return which DP Port should be selected for Transcoder DP control */ 1799int 1800intel_trans_dp_port_sel (struct drm_crtc *crtc) 1801{ 1802 struct drm_device *dev = crtc->dev; 1803 struct drm_mode_config *mode_config = &dev->mode_config; 1804 struct drm_encoder *encoder; 1805 1806 list_for_each_entry(encoder, &mode_config->encoder_list, head) { 1807 struct intel_dp *intel_dp; 1808 1809 if (encoder->crtc != crtc) 1810 continue; 1811 1812 intel_dp = enc_to_intel_dp(encoder); 1813 if (intel_dp->base.type == INTEL_OUTPUT_DISPLAYPORT) 1814 return intel_dp->output_reg; 1815 } 1816 1817 return -1; 1818} 1819 1820/* check the VBT to see whether the eDP is on DP-D port */ 1821bool intel_dpd_is_edp(struct drm_device *dev) 1822{ 1823 struct drm_i915_private *dev_priv = dev->dev_private; 1824 struct child_device_config *p_child; 1825 int i; 1826 1827 if (!dev_priv->child_dev_num) 1828 return false; 1829 1830 for (i = 0; i < dev_priv->child_dev_num; i++) { 1831 p_child = dev_priv->child_dev + i; 1832 1833 if (p_child->dvo_port == PORT_IDPD && 1834 p_child->device_type == DEVICE_TYPE_eDP) 1835 return true; 1836 } 1837 return false; 1838} 1839 1840static void 1841intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector) 1842{ 1843 intel_attach_force_audio_property(connector); 1844 intel_attach_broadcast_rgb_property(connector); 1845} 1846 1847void 1848intel_dp_init(struct drm_device *dev, int output_reg) 1849{ 1850 struct drm_i915_private *dev_priv = dev->dev_private; 1851 struct drm_connector *connector; 1852 struct intel_dp *intel_dp; 1853 struct intel_encoder *intel_encoder; 1854 struct intel_connector *intel_connector; 1855 const char *name = NULL; 1856 int type; 1857 1858 intel_dp = kzalloc(sizeof(struct intel_dp), GFP_KERNEL); 1859 if (!intel_dp) 1860 return; 1861 1862 intel_dp->output_reg = output_reg; 1863 intel_dp->dpms_mode = -1; 1864 1865 intel_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL); 1866 if (!intel_connector) { 1867 kfree(intel_dp); 1868 return; 1869 } 1870 intel_encoder = &intel_dp->base; 1871 1872 if (HAS_PCH_SPLIT(dev) && output_reg == PCH_DP_D) 1873 if (intel_dpd_is_edp(dev)) 1874 intel_dp->is_pch_edp = true; 1875 1876 if (output_reg == DP_A || is_pch_edp(intel_dp)) { 1877 type = DRM_MODE_CONNECTOR_eDP; 1878 intel_encoder->type = INTEL_OUTPUT_EDP; 1879 } else { 1880 type = DRM_MODE_CONNECTOR_DisplayPort; 1881 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT; 1882 } 1883 1884 connector = &intel_connector->base; 1885 drm_connector_init(dev, connector, &intel_dp_connector_funcs, type); 1886 drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs); 1887 1888 connector->polled = DRM_CONNECTOR_POLL_HPD; 1889 1890 if (output_reg == DP_B || output_reg == PCH_DP_B) 1891 intel_encoder->clone_mask = (1 << INTEL_DP_B_CLONE_BIT); 1892 else if (output_reg == DP_C || output_reg == PCH_DP_C) 1893 intel_encoder->clone_mask = (1 << INTEL_DP_C_CLONE_BIT); 1894 else if (output_reg == DP_D || output_reg == PCH_DP_D) 1895 intel_encoder->clone_mask = (1 << INTEL_DP_D_CLONE_BIT); 1896 1897 if (is_edp(intel_dp)) 1898 intel_encoder->clone_mask = (1 << INTEL_EDP_CLONE_BIT); 1899 1900 intel_encoder->crtc_mask = (1 << 0) | (1 << 1); 1901 connector->interlace_allowed = true; 1902 connector->doublescan_allowed = 0; 1903 1904 drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs, 1905 DRM_MODE_ENCODER_TMDS); 1906 drm_encoder_helper_add(&intel_encoder->base, &intel_dp_helper_funcs); 1907 1908 intel_connector_attach_encoder(intel_connector, intel_encoder); 1909 drm_sysfs_connector_add(connector); 1910 1911 /* Set up the DDC bus. */ 1912 switch (output_reg) { 1913 case DP_A: 1914 name = "DPDDC-A"; 1915 break; 1916 case DP_B: 1917 case PCH_DP_B: 1918 dev_priv->hotplug_supported_mask |= 1919 HDMIB_HOTPLUG_INT_STATUS; 1920 name = "DPDDC-B"; 1921 break; 1922 case DP_C: 1923 case PCH_DP_C: 1924 dev_priv->hotplug_supported_mask |= 1925 HDMIC_HOTPLUG_INT_STATUS; 1926 name = "DPDDC-C"; 1927 break; 1928 case DP_D: 1929 case PCH_DP_D: 1930 dev_priv->hotplug_supported_mask |= 1931 HDMID_HOTPLUG_INT_STATUS; 1932 name = "DPDDC-D"; 1933 break; 1934 } 1935 1936 intel_dp_i2c_init(intel_dp, intel_connector, name); 1937 1938 /* Cache some DPCD data in the eDP case */ 1939 if (is_edp(intel_dp)) { 1940 int ret; 1941 u32 pp_on, pp_div; 1942 1943 pp_on = I915_READ(PCH_PP_ON_DELAYS); 1944 pp_div = I915_READ(PCH_PP_DIVISOR); 1945 1946 /* Get T3 & T12 values (note: VESA not bspec terminology) */ 1947 dev_priv->panel_t3 = (pp_on & 0x1fff0000) >> 16; 1948 dev_priv->panel_t3 /= 10; /* t3 in 100us units */ 1949 dev_priv->panel_t12 = pp_div & 0xf; 1950 dev_priv->panel_t12 *= 100; /* t12 in 100ms units */ 1951 1952 ironlake_edp_panel_vdd_on(intel_dp); 1953 ret = intel_dp_aux_native_read(intel_dp, DP_DPCD_REV, 1954 intel_dp->dpcd, 1955 sizeof(intel_dp->dpcd)); 1956 ironlake_edp_panel_vdd_off(intel_dp); 1957 if (ret == sizeof(intel_dp->dpcd)) { 1958 if (intel_dp->dpcd[0] >= 0x11) 1959 dev_priv->no_aux_handshake = intel_dp->dpcd[3] & 1960 DP_NO_AUX_HANDSHAKE_LINK_TRAINING; 1961 } else { 1962 /* if this fails, presume the device is a ghost */ 1963 DRM_INFO("failed to retrieve link info, disabling eDP\n"); 1964 intel_dp_encoder_destroy(&intel_dp->base.base); 1965 intel_dp_destroy(&intel_connector->base); 1966 return; 1967 } 1968 } 1969 1970 intel_encoder->hot_plug = intel_dp_hot_plug; 1971 1972 if (is_edp(intel_dp)) { 1973 /* initialize panel mode from VBT if available for eDP */ 1974 if (dev_priv->lfp_lvds_vbt_mode) { 1975 dev_priv->panel_fixed_mode = 1976 drm_mode_duplicate(dev, dev_priv->lfp_lvds_vbt_mode); 1977 if (dev_priv->panel_fixed_mode) { 1978 dev_priv->panel_fixed_mode->type |= 1979 DRM_MODE_TYPE_PREFERRED; 1980 } 1981 } 1982 } 1983 1984 intel_dp_add_properties(intel_dp, connector); 1985 1986 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written 1987 * 0xd. Failure to do so will result in spurious interrupts being 1988 * generated on the port when a cable is not attached. 1989 */ 1990 if (IS_G4X(dev) && !IS_GM45(dev)) { 1991 u32 temp = I915_READ(PEG_BAND_GAP_DATA); 1992 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd); 1993 } 1994} 1995