intel_dp.c revision 987a709e1589cf10e250e04ce9df910b735d4f60
1/* 2 * Copyright © 2008 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 * Authors: 24 * Keith Packard <keithp@keithp.com> 25 * 26 */ 27 28#include <linux/i2c.h> 29#include <linux/slab.h> 30#include "drmP.h" 31#include "drm.h" 32#include "drm_crtc.h" 33#include "drm_crtc_helper.h" 34#include "intel_drv.h" 35#include "i915_drm.h" 36#include "i915_drv.h" 37#include "drm_dp_helper.h" 38 39 40#define DP_LINK_STATUS_SIZE 6 41#define DP_LINK_CHECK_TIMEOUT (10 * 1000) 42 43#define DP_LINK_CONFIGURATION_SIZE 9 44 45struct intel_dp { 46 struct intel_encoder base; 47 uint32_t output_reg; 48 uint32_t DP; 49 uint8_t link_configuration[DP_LINK_CONFIGURATION_SIZE]; 50 bool has_audio; 51 int force_audio; 52 int dpms_mode; 53 uint8_t link_bw; 54 uint8_t lane_count; 55 uint8_t dpcd[4]; 56 struct i2c_adapter adapter; 57 struct i2c_algo_dp_aux_data algo; 58 bool is_pch_edp; 59 uint8_t train_set[4]; 60 uint8_t link_status[DP_LINK_STATUS_SIZE]; 61 62 struct drm_property *force_audio_property; 63}; 64 65/** 66 * is_edp - is the given port attached to an eDP panel (either CPU or PCH) 67 * @intel_dp: DP struct 68 * 69 * If a CPU or PCH DP output is attached to an eDP panel, this function 70 * will return true, and false otherwise. 71 */ 72static bool is_edp(struct intel_dp *intel_dp) 73{ 74 return intel_dp->base.type == INTEL_OUTPUT_EDP; 75} 76 77/** 78 * is_pch_edp - is the port on the PCH and attached to an eDP panel? 79 * @intel_dp: DP struct 80 * 81 * Returns true if the given DP struct corresponds to a PCH DP port attached 82 * to an eDP panel, false otherwise. Helpful for determining whether we 83 * may need FDI resources for a given DP output or not. 84 */ 85static bool is_pch_edp(struct intel_dp *intel_dp) 86{ 87 return intel_dp->is_pch_edp; 88} 89 90static struct intel_dp *enc_to_intel_dp(struct drm_encoder *encoder) 91{ 92 return container_of(encoder, struct intel_dp, base.base); 93} 94 95static struct intel_dp *intel_attached_dp(struct drm_connector *connector) 96{ 97 return container_of(intel_attached_encoder(connector), 98 struct intel_dp, base); 99} 100 101/** 102 * intel_encoder_is_pch_edp - is the given encoder a PCH attached eDP? 103 * @encoder: DRM encoder 104 * 105 * Return true if @encoder corresponds to a PCH attached eDP panel. Needed 106 * by intel_display.c. 107 */ 108bool intel_encoder_is_pch_edp(struct drm_encoder *encoder) 109{ 110 struct intel_dp *intel_dp; 111 112 if (!encoder) 113 return false; 114 115 intel_dp = enc_to_intel_dp(encoder); 116 117 return is_pch_edp(intel_dp); 118} 119 120static void intel_dp_start_link_train(struct intel_dp *intel_dp); 121static void intel_dp_complete_link_train(struct intel_dp *intel_dp); 122static void intel_dp_link_down(struct intel_dp *intel_dp); 123 124void 125intel_edp_link_config (struct intel_encoder *intel_encoder, 126 int *lane_num, int *link_bw) 127{ 128 struct intel_dp *intel_dp = container_of(intel_encoder, struct intel_dp, base); 129 130 *lane_num = intel_dp->lane_count; 131 if (intel_dp->link_bw == DP_LINK_BW_1_62) 132 *link_bw = 162000; 133 else if (intel_dp->link_bw == DP_LINK_BW_2_7) 134 *link_bw = 270000; 135} 136 137static int 138intel_dp_max_lane_count(struct intel_dp *intel_dp) 139{ 140 int max_lane_count = 4; 141 142 if (intel_dp->dpcd[0] >= 0x11) { 143 max_lane_count = intel_dp->dpcd[2] & 0x1f; 144 switch (max_lane_count) { 145 case 1: case 2: case 4: 146 break; 147 default: 148 max_lane_count = 4; 149 } 150 } 151 return max_lane_count; 152} 153 154static int 155intel_dp_max_link_bw(struct intel_dp *intel_dp) 156{ 157 int max_link_bw = intel_dp->dpcd[1]; 158 159 switch (max_link_bw) { 160 case DP_LINK_BW_1_62: 161 case DP_LINK_BW_2_7: 162 break; 163 default: 164 max_link_bw = DP_LINK_BW_1_62; 165 break; 166 } 167 return max_link_bw; 168} 169 170static int 171intel_dp_link_clock(uint8_t link_bw) 172{ 173 if (link_bw == DP_LINK_BW_2_7) 174 return 270000; 175 else 176 return 162000; 177} 178 179/* I think this is a fiction */ 180static int 181intel_dp_link_required(struct drm_device *dev, struct intel_dp *intel_dp, int pixel_clock) 182{ 183 struct drm_i915_private *dev_priv = dev->dev_private; 184 185 if (is_edp(intel_dp)) 186 return (pixel_clock * dev_priv->edp.bpp + 7) / 8; 187 else 188 return pixel_clock * 3; 189} 190 191static int 192intel_dp_max_data_rate(int max_link_clock, int max_lanes) 193{ 194 return (max_link_clock * max_lanes * 8) / 10; 195} 196 197static int 198intel_dp_mode_valid(struct drm_connector *connector, 199 struct drm_display_mode *mode) 200{ 201 struct intel_dp *intel_dp = intel_attached_dp(connector); 202 struct drm_device *dev = connector->dev; 203 struct drm_i915_private *dev_priv = dev->dev_private; 204 int max_link_clock = intel_dp_link_clock(intel_dp_max_link_bw(intel_dp)); 205 int max_lanes = intel_dp_max_lane_count(intel_dp); 206 207 if (is_edp(intel_dp) && dev_priv->panel_fixed_mode) { 208 if (mode->hdisplay > dev_priv->panel_fixed_mode->hdisplay) 209 return MODE_PANEL; 210 211 if (mode->vdisplay > dev_priv->panel_fixed_mode->vdisplay) 212 return MODE_PANEL; 213 } 214 215 /* only refuse the mode on non eDP since we have seen some wierd eDP panels 216 which are outside spec tolerances but somehow work by magic */ 217 if (!is_edp(intel_dp) && 218 (intel_dp_link_required(connector->dev, intel_dp, mode->clock) 219 > intel_dp_max_data_rate(max_link_clock, max_lanes))) 220 return MODE_CLOCK_HIGH; 221 222 if (mode->clock < 10000) 223 return MODE_CLOCK_LOW; 224 225 return MODE_OK; 226} 227 228static uint32_t 229pack_aux(uint8_t *src, int src_bytes) 230{ 231 int i; 232 uint32_t v = 0; 233 234 if (src_bytes > 4) 235 src_bytes = 4; 236 for (i = 0; i < src_bytes; i++) 237 v |= ((uint32_t) src[i]) << ((3-i) * 8); 238 return v; 239} 240 241static void 242unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes) 243{ 244 int i; 245 if (dst_bytes > 4) 246 dst_bytes = 4; 247 for (i = 0; i < dst_bytes; i++) 248 dst[i] = src >> ((3-i) * 8); 249} 250 251/* hrawclock is 1/4 the FSB frequency */ 252static int 253intel_hrawclk(struct drm_device *dev) 254{ 255 struct drm_i915_private *dev_priv = dev->dev_private; 256 uint32_t clkcfg; 257 258 clkcfg = I915_READ(CLKCFG); 259 switch (clkcfg & CLKCFG_FSB_MASK) { 260 case CLKCFG_FSB_400: 261 return 100; 262 case CLKCFG_FSB_533: 263 return 133; 264 case CLKCFG_FSB_667: 265 return 166; 266 case CLKCFG_FSB_800: 267 return 200; 268 case CLKCFG_FSB_1067: 269 return 266; 270 case CLKCFG_FSB_1333: 271 return 333; 272 /* these two are just a guess; one of them might be right */ 273 case CLKCFG_FSB_1600: 274 case CLKCFG_FSB_1600_ALT: 275 return 400; 276 default: 277 return 133; 278 } 279} 280 281static int 282intel_dp_aux_ch(struct intel_dp *intel_dp, 283 uint8_t *send, int send_bytes, 284 uint8_t *recv, int recv_size) 285{ 286 uint32_t output_reg = intel_dp->output_reg; 287 struct drm_device *dev = intel_dp->base.base.dev; 288 struct drm_i915_private *dev_priv = dev->dev_private; 289 uint32_t ch_ctl = output_reg + 0x10; 290 uint32_t ch_data = ch_ctl + 4; 291 int i; 292 int recv_bytes; 293 uint32_t status; 294 uint32_t aux_clock_divider; 295 int try, precharge; 296 297 /* The clock divider is based off the hrawclk, 298 * and would like to run at 2MHz. So, take the 299 * hrawclk value and divide by 2 and use that 300 * 301 * Note that PCH attached eDP panels should use a 125MHz input 302 * clock divider. 303 */ 304 if (is_edp(intel_dp) && !is_pch_edp(intel_dp)) { 305 if (IS_GEN6(dev)) 306 aux_clock_divider = 200; /* SNB eDP input clock at 400Mhz */ 307 else 308 aux_clock_divider = 225; /* eDP input clock at 450Mhz */ 309 } else if (HAS_PCH_SPLIT(dev)) 310 aux_clock_divider = 62; /* IRL input clock fixed at 125Mhz */ 311 else 312 aux_clock_divider = intel_hrawclk(dev) / 2; 313 314 if (IS_GEN6(dev)) 315 precharge = 3; 316 else 317 precharge = 5; 318 319 if (I915_READ(ch_ctl) & DP_AUX_CH_CTL_SEND_BUSY) { 320 DRM_ERROR("dp_aux_ch not started status 0x%08x\n", 321 I915_READ(ch_ctl)); 322 return -EBUSY; 323 } 324 325 /* Must try at least 3 times according to DP spec */ 326 for (try = 0; try < 5; try++) { 327 /* Load the send data into the aux channel data registers */ 328 for (i = 0; i < send_bytes; i += 4) 329 I915_WRITE(ch_data + i, 330 pack_aux(send + i, send_bytes - i)); 331 332 /* Send the command and wait for it to complete */ 333 I915_WRITE(ch_ctl, 334 DP_AUX_CH_CTL_SEND_BUSY | 335 DP_AUX_CH_CTL_TIME_OUT_400us | 336 (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) | 337 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) | 338 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT) | 339 DP_AUX_CH_CTL_DONE | 340 DP_AUX_CH_CTL_TIME_OUT_ERROR | 341 DP_AUX_CH_CTL_RECEIVE_ERROR); 342 for (;;) { 343 status = I915_READ(ch_ctl); 344 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0) 345 break; 346 udelay(100); 347 } 348 349 /* Clear done status and any errors */ 350 I915_WRITE(ch_ctl, 351 status | 352 DP_AUX_CH_CTL_DONE | 353 DP_AUX_CH_CTL_TIME_OUT_ERROR | 354 DP_AUX_CH_CTL_RECEIVE_ERROR); 355 if (status & DP_AUX_CH_CTL_DONE) 356 break; 357 } 358 359 if ((status & DP_AUX_CH_CTL_DONE) == 0) { 360 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status); 361 return -EBUSY; 362 } 363 364 /* Check for timeout or receive error. 365 * Timeouts occur when the sink is not connected 366 */ 367 if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) { 368 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status); 369 return -EIO; 370 } 371 372 /* Timeouts occur when the device isn't connected, so they're 373 * "normal" -- don't fill the kernel log with these */ 374 if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) { 375 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status); 376 return -ETIMEDOUT; 377 } 378 379 /* Unload any bytes sent back from the other side */ 380 recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >> 381 DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT); 382 if (recv_bytes > recv_size) 383 recv_bytes = recv_size; 384 385 for (i = 0; i < recv_bytes; i += 4) 386 unpack_aux(I915_READ(ch_data + i), 387 recv + i, recv_bytes - i); 388 389 return recv_bytes; 390} 391 392/* Write data to the aux channel in native mode */ 393static int 394intel_dp_aux_native_write(struct intel_dp *intel_dp, 395 uint16_t address, uint8_t *send, int send_bytes) 396{ 397 int ret; 398 uint8_t msg[20]; 399 int msg_bytes; 400 uint8_t ack; 401 402 if (send_bytes > 16) 403 return -1; 404 msg[0] = AUX_NATIVE_WRITE << 4; 405 msg[1] = address >> 8; 406 msg[2] = address & 0xff; 407 msg[3] = send_bytes - 1; 408 memcpy(&msg[4], send, send_bytes); 409 msg_bytes = send_bytes + 4; 410 for (;;) { 411 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes, &ack, 1); 412 if (ret < 0) 413 return ret; 414 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK) 415 break; 416 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER) 417 udelay(100); 418 else 419 return -EIO; 420 } 421 return send_bytes; 422} 423 424/* Write a single byte to the aux channel in native mode */ 425static int 426intel_dp_aux_native_write_1(struct intel_dp *intel_dp, 427 uint16_t address, uint8_t byte) 428{ 429 return intel_dp_aux_native_write(intel_dp, address, &byte, 1); 430} 431 432/* read bytes from a native aux channel */ 433static int 434intel_dp_aux_native_read(struct intel_dp *intel_dp, 435 uint16_t address, uint8_t *recv, int recv_bytes) 436{ 437 uint8_t msg[4]; 438 int msg_bytes; 439 uint8_t reply[20]; 440 int reply_bytes; 441 uint8_t ack; 442 int ret; 443 444 msg[0] = AUX_NATIVE_READ << 4; 445 msg[1] = address >> 8; 446 msg[2] = address & 0xff; 447 msg[3] = recv_bytes - 1; 448 449 msg_bytes = 4; 450 reply_bytes = recv_bytes + 1; 451 452 for (;;) { 453 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes, 454 reply, reply_bytes); 455 if (ret == 0) 456 return -EPROTO; 457 if (ret < 0) 458 return ret; 459 ack = reply[0]; 460 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK) { 461 memcpy(recv, reply + 1, ret - 1); 462 return ret - 1; 463 } 464 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER) 465 udelay(100); 466 else 467 return -EIO; 468 } 469} 470 471static int 472intel_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode, 473 uint8_t write_byte, uint8_t *read_byte) 474{ 475 struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data; 476 struct intel_dp *intel_dp = container_of(adapter, 477 struct intel_dp, 478 adapter); 479 uint16_t address = algo_data->address; 480 uint8_t msg[5]; 481 uint8_t reply[2]; 482 unsigned retry; 483 int msg_bytes; 484 int reply_bytes; 485 int ret; 486 487 /* Set up the command byte */ 488 if (mode & MODE_I2C_READ) 489 msg[0] = AUX_I2C_READ << 4; 490 else 491 msg[0] = AUX_I2C_WRITE << 4; 492 493 if (!(mode & MODE_I2C_STOP)) 494 msg[0] |= AUX_I2C_MOT << 4; 495 496 msg[1] = address >> 8; 497 msg[2] = address; 498 499 switch (mode) { 500 case MODE_I2C_WRITE: 501 msg[3] = 0; 502 msg[4] = write_byte; 503 msg_bytes = 5; 504 reply_bytes = 1; 505 break; 506 case MODE_I2C_READ: 507 msg[3] = 0; 508 msg_bytes = 4; 509 reply_bytes = 2; 510 break; 511 default: 512 msg_bytes = 3; 513 reply_bytes = 1; 514 break; 515 } 516 517 for (retry = 0; retry < 5; retry++) { 518 ret = intel_dp_aux_ch(intel_dp, 519 msg, msg_bytes, 520 reply, reply_bytes); 521 if (ret < 0) { 522 DRM_DEBUG_KMS("aux_ch failed %d\n", ret); 523 return ret; 524 } 525 526 switch (reply[0] & AUX_NATIVE_REPLY_MASK) { 527 case AUX_NATIVE_REPLY_ACK: 528 /* I2C-over-AUX Reply field is only valid 529 * when paired with AUX ACK. 530 */ 531 break; 532 case AUX_NATIVE_REPLY_NACK: 533 DRM_DEBUG_KMS("aux_ch native nack\n"); 534 return -EREMOTEIO; 535 case AUX_NATIVE_REPLY_DEFER: 536 udelay(100); 537 continue; 538 default: 539 DRM_ERROR("aux_ch invalid native reply 0x%02x\n", 540 reply[0]); 541 return -EREMOTEIO; 542 } 543 544 switch (reply[0] & AUX_I2C_REPLY_MASK) { 545 case AUX_I2C_REPLY_ACK: 546 if (mode == MODE_I2C_READ) { 547 *read_byte = reply[1]; 548 } 549 return reply_bytes - 1; 550 case AUX_I2C_REPLY_NACK: 551 DRM_DEBUG_KMS("aux_i2c nack\n"); 552 return -EREMOTEIO; 553 case AUX_I2C_REPLY_DEFER: 554 DRM_DEBUG_KMS("aux_i2c defer\n"); 555 udelay(100); 556 break; 557 default: 558 DRM_ERROR("aux_i2c invalid reply 0x%02x\n", reply[0]); 559 return -EREMOTEIO; 560 } 561 } 562 563 DRM_ERROR("too many retries, giving up\n"); 564 return -EREMOTEIO; 565} 566 567static int 568intel_dp_i2c_init(struct intel_dp *intel_dp, 569 struct intel_connector *intel_connector, const char *name) 570{ 571 DRM_DEBUG_KMS("i2c_init %s\n", name); 572 intel_dp->algo.running = false; 573 intel_dp->algo.address = 0; 574 intel_dp->algo.aux_ch = intel_dp_i2c_aux_ch; 575 576 memset(&intel_dp->adapter, '\0', sizeof (intel_dp->adapter)); 577 intel_dp->adapter.owner = THIS_MODULE; 578 intel_dp->adapter.class = I2C_CLASS_DDC; 579 strncpy (intel_dp->adapter.name, name, sizeof(intel_dp->adapter.name) - 1); 580 intel_dp->adapter.name[sizeof(intel_dp->adapter.name) - 1] = '\0'; 581 intel_dp->adapter.algo_data = &intel_dp->algo; 582 intel_dp->adapter.dev.parent = &intel_connector->base.kdev; 583 584 return i2c_dp_aux_add_bus(&intel_dp->adapter); 585} 586 587static bool 588intel_dp_mode_fixup(struct drm_encoder *encoder, struct drm_display_mode *mode, 589 struct drm_display_mode *adjusted_mode) 590{ 591 struct drm_device *dev = encoder->dev; 592 struct drm_i915_private *dev_priv = dev->dev_private; 593 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 594 int lane_count, clock; 595 int max_lane_count = intel_dp_max_lane_count(intel_dp); 596 int max_clock = intel_dp_max_link_bw(intel_dp) == DP_LINK_BW_2_7 ? 1 : 0; 597 static int bws[2] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7 }; 598 599 if (is_edp(intel_dp) && dev_priv->panel_fixed_mode) { 600 intel_fixed_panel_mode(dev_priv->panel_fixed_mode, adjusted_mode); 601 intel_pch_panel_fitting(dev, DRM_MODE_SCALE_FULLSCREEN, 602 mode, adjusted_mode); 603 /* 604 * the mode->clock is used to calculate the Data&Link M/N 605 * of the pipe. For the eDP the fixed clock should be used. 606 */ 607 mode->clock = dev_priv->panel_fixed_mode->clock; 608 } 609 610 for (lane_count = 1; lane_count <= max_lane_count; lane_count <<= 1) { 611 for (clock = 0; clock <= max_clock; clock++) { 612 int link_avail = intel_dp_max_data_rate(intel_dp_link_clock(bws[clock]), lane_count); 613 614 if (intel_dp_link_required(encoder->dev, intel_dp, mode->clock) 615 <= link_avail) { 616 intel_dp->link_bw = bws[clock]; 617 intel_dp->lane_count = lane_count; 618 adjusted_mode->clock = intel_dp_link_clock(intel_dp->link_bw); 619 DRM_DEBUG_KMS("Display port link bw %02x lane " 620 "count %d clock %d\n", 621 intel_dp->link_bw, intel_dp->lane_count, 622 adjusted_mode->clock); 623 return true; 624 } 625 } 626 } 627 628 if (is_edp(intel_dp)) { 629 /* okay we failed just pick the highest */ 630 intel_dp->lane_count = max_lane_count; 631 intel_dp->link_bw = bws[max_clock]; 632 adjusted_mode->clock = intel_dp_link_clock(intel_dp->link_bw); 633 DRM_DEBUG_KMS("Force picking display port link bw %02x lane " 634 "count %d clock %d\n", 635 intel_dp->link_bw, intel_dp->lane_count, 636 adjusted_mode->clock); 637 638 return true; 639 } 640 641 return false; 642} 643 644struct intel_dp_m_n { 645 uint32_t tu; 646 uint32_t gmch_m; 647 uint32_t gmch_n; 648 uint32_t link_m; 649 uint32_t link_n; 650}; 651 652static void 653intel_reduce_ratio(uint32_t *num, uint32_t *den) 654{ 655 while (*num > 0xffffff || *den > 0xffffff) { 656 *num >>= 1; 657 *den >>= 1; 658 } 659} 660 661static void 662intel_dp_compute_m_n(int bpp, 663 int nlanes, 664 int pixel_clock, 665 int link_clock, 666 struct intel_dp_m_n *m_n) 667{ 668 m_n->tu = 64; 669 m_n->gmch_m = (pixel_clock * bpp) >> 3; 670 m_n->gmch_n = link_clock * nlanes; 671 intel_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n); 672 m_n->link_m = pixel_clock; 673 m_n->link_n = link_clock; 674 intel_reduce_ratio(&m_n->link_m, &m_n->link_n); 675} 676 677void 678intel_dp_set_m_n(struct drm_crtc *crtc, struct drm_display_mode *mode, 679 struct drm_display_mode *adjusted_mode) 680{ 681 struct drm_device *dev = crtc->dev; 682 struct drm_mode_config *mode_config = &dev->mode_config; 683 struct drm_encoder *encoder; 684 struct drm_i915_private *dev_priv = dev->dev_private; 685 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 686 int lane_count = 4, bpp = 24; 687 struct intel_dp_m_n m_n; 688 689 /* 690 * Find the lane count in the intel_encoder private 691 */ 692 list_for_each_entry(encoder, &mode_config->encoder_list, head) { 693 struct intel_dp *intel_dp; 694 695 if (encoder->crtc != crtc) 696 continue; 697 698 intel_dp = enc_to_intel_dp(encoder); 699 if (intel_dp->base.type == INTEL_OUTPUT_DISPLAYPORT) { 700 lane_count = intel_dp->lane_count; 701 break; 702 } else if (is_edp(intel_dp)) { 703 lane_count = dev_priv->edp.lanes; 704 bpp = dev_priv->edp.bpp; 705 break; 706 } 707 } 708 709 /* 710 * Compute the GMCH and Link ratios. The '3' here is 711 * the number of bytes_per_pixel post-LUT, which we always 712 * set up for 8-bits of R/G/B, or 3 bytes total. 713 */ 714 intel_dp_compute_m_n(bpp, lane_count, 715 mode->clock, adjusted_mode->clock, &m_n); 716 717 if (HAS_PCH_SPLIT(dev)) { 718 if (intel_crtc->pipe == 0) { 719 I915_WRITE(TRANSA_DATA_M1, 720 ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) | 721 m_n.gmch_m); 722 I915_WRITE(TRANSA_DATA_N1, m_n.gmch_n); 723 I915_WRITE(TRANSA_DP_LINK_M1, m_n.link_m); 724 I915_WRITE(TRANSA_DP_LINK_N1, m_n.link_n); 725 } else { 726 I915_WRITE(TRANSB_DATA_M1, 727 ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) | 728 m_n.gmch_m); 729 I915_WRITE(TRANSB_DATA_N1, m_n.gmch_n); 730 I915_WRITE(TRANSB_DP_LINK_M1, m_n.link_m); 731 I915_WRITE(TRANSB_DP_LINK_N1, m_n.link_n); 732 } 733 } else { 734 if (intel_crtc->pipe == 0) { 735 I915_WRITE(PIPEA_GMCH_DATA_M, 736 ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) | 737 m_n.gmch_m); 738 I915_WRITE(PIPEA_GMCH_DATA_N, 739 m_n.gmch_n); 740 I915_WRITE(PIPEA_DP_LINK_M, m_n.link_m); 741 I915_WRITE(PIPEA_DP_LINK_N, m_n.link_n); 742 } else { 743 I915_WRITE(PIPEB_GMCH_DATA_M, 744 ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) | 745 m_n.gmch_m); 746 I915_WRITE(PIPEB_GMCH_DATA_N, 747 m_n.gmch_n); 748 I915_WRITE(PIPEB_DP_LINK_M, m_n.link_m); 749 I915_WRITE(PIPEB_DP_LINK_N, m_n.link_n); 750 } 751 } 752} 753 754static void 755intel_dp_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode, 756 struct drm_display_mode *adjusted_mode) 757{ 758 struct drm_device *dev = encoder->dev; 759 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 760 struct drm_crtc *crtc = intel_dp->base.base.crtc; 761 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 762 763 intel_dp->DP = (DP_VOLTAGE_0_4 | 764 DP_PRE_EMPHASIS_0); 765 766 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) 767 intel_dp->DP |= DP_SYNC_HS_HIGH; 768 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) 769 intel_dp->DP |= DP_SYNC_VS_HIGH; 770 771 if (HAS_PCH_CPT(dev) && !is_edp(intel_dp)) 772 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT; 773 else 774 intel_dp->DP |= DP_LINK_TRAIN_OFF; 775 776 switch (intel_dp->lane_count) { 777 case 1: 778 intel_dp->DP |= DP_PORT_WIDTH_1; 779 break; 780 case 2: 781 intel_dp->DP |= DP_PORT_WIDTH_2; 782 break; 783 case 4: 784 intel_dp->DP |= DP_PORT_WIDTH_4; 785 break; 786 } 787 if (intel_dp->has_audio) 788 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE; 789 790 memset(intel_dp->link_configuration, 0, DP_LINK_CONFIGURATION_SIZE); 791 intel_dp->link_configuration[0] = intel_dp->link_bw; 792 intel_dp->link_configuration[1] = intel_dp->lane_count; 793 794 /* 795 * Check for DPCD version > 1.1 and enhanced framing support 796 */ 797 if (intel_dp->dpcd[0] >= 0x11 && (intel_dp->dpcd[2] & DP_ENHANCED_FRAME_CAP)) { 798 intel_dp->link_configuration[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN; 799 intel_dp->DP |= DP_ENHANCED_FRAMING; 800 } 801 802 /* CPT DP's pipe select is decided in TRANS_DP_CTL */ 803 if (intel_crtc->pipe == 1 && !HAS_PCH_CPT(dev)) 804 intel_dp->DP |= DP_PIPEB_SELECT; 805 806 if (is_edp(intel_dp) && !is_pch_edp(intel_dp)) { 807 /* don't miss out required setting for eDP */ 808 intel_dp->DP |= DP_PLL_ENABLE; 809 if (adjusted_mode->clock < 200000) 810 intel_dp->DP |= DP_PLL_FREQ_160MHZ; 811 else 812 intel_dp->DP |= DP_PLL_FREQ_270MHZ; 813 } 814} 815 816/* Returns true if the panel was already on when called */ 817static bool ironlake_edp_panel_on (struct intel_dp *intel_dp) 818{ 819 struct drm_device *dev = intel_dp->base.base.dev; 820 struct drm_i915_private *dev_priv = dev->dev_private; 821 u32 pp, idle_on_mask = PP_ON | PP_SEQUENCE_STATE_ON_IDLE; 822 823 if (I915_READ(PCH_PP_STATUS) & PP_ON) 824 return true; 825 826 pp = I915_READ(PCH_PP_CONTROL); 827 828 /* ILK workaround: disable reset around power sequence */ 829 pp &= ~PANEL_POWER_RESET; 830 I915_WRITE(PCH_PP_CONTROL, pp); 831 POSTING_READ(PCH_PP_CONTROL); 832 833 pp |= PANEL_UNLOCK_REGS | POWER_TARGET_ON; 834 I915_WRITE(PCH_PP_CONTROL, pp); 835 POSTING_READ(PCH_PP_CONTROL); 836 837 if (wait_for((I915_READ(PCH_PP_STATUS) & idle_on_mask) == idle_on_mask, 838 5000)) 839 DRM_ERROR("panel on wait timed out: 0x%08x\n", 840 I915_READ(PCH_PP_STATUS)); 841 842 pp |= PANEL_POWER_RESET; /* restore panel reset bit */ 843 I915_WRITE(PCH_PP_CONTROL, pp); 844 POSTING_READ(PCH_PP_CONTROL); 845 846 return false; 847} 848 849static void ironlake_edp_panel_off (struct drm_device *dev) 850{ 851 struct drm_i915_private *dev_priv = dev->dev_private; 852 u32 pp, idle_off_mask = PP_ON | PP_SEQUENCE_MASK | 853 PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK; 854 855 pp = I915_READ(PCH_PP_CONTROL); 856 857 /* ILK workaround: disable reset around power sequence */ 858 pp &= ~PANEL_POWER_RESET; 859 I915_WRITE(PCH_PP_CONTROL, pp); 860 POSTING_READ(PCH_PP_CONTROL); 861 862 pp &= ~POWER_TARGET_ON; 863 I915_WRITE(PCH_PP_CONTROL, pp); 864 POSTING_READ(PCH_PP_CONTROL); 865 866 if (wait_for((I915_READ(PCH_PP_STATUS) & idle_off_mask) == 0, 5000)) 867 DRM_ERROR("panel off wait timed out: 0x%08x\n", 868 I915_READ(PCH_PP_STATUS)); 869 870 pp |= PANEL_POWER_RESET; /* restore panel reset bit */ 871 I915_WRITE(PCH_PP_CONTROL, pp); 872 POSTING_READ(PCH_PP_CONTROL); 873} 874 875static void ironlake_edp_backlight_on (struct drm_device *dev) 876{ 877 struct drm_i915_private *dev_priv = dev->dev_private; 878 u32 pp; 879 880 DRM_DEBUG_KMS("\n"); 881 /* 882 * If we enable the backlight right away following a panel power 883 * on, we may see slight flicker as the panel syncs with the eDP 884 * link. So delay a bit to make sure the image is solid before 885 * allowing it to appear. 886 */ 887 msleep(300); 888 pp = I915_READ(PCH_PP_CONTROL); 889 pp |= EDP_BLC_ENABLE; 890 I915_WRITE(PCH_PP_CONTROL, pp); 891} 892 893static void ironlake_edp_backlight_off (struct drm_device *dev) 894{ 895 struct drm_i915_private *dev_priv = dev->dev_private; 896 u32 pp; 897 898 DRM_DEBUG_KMS("\n"); 899 pp = I915_READ(PCH_PP_CONTROL); 900 pp &= ~EDP_BLC_ENABLE; 901 I915_WRITE(PCH_PP_CONTROL, pp); 902} 903 904static void ironlake_edp_pll_on(struct drm_encoder *encoder) 905{ 906 struct drm_device *dev = encoder->dev; 907 struct drm_i915_private *dev_priv = dev->dev_private; 908 u32 dpa_ctl; 909 910 DRM_DEBUG_KMS("\n"); 911 dpa_ctl = I915_READ(DP_A); 912 dpa_ctl |= DP_PLL_ENABLE; 913 I915_WRITE(DP_A, dpa_ctl); 914 POSTING_READ(DP_A); 915 udelay(200); 916} 917 918static void ironlake_edp_pll_off(struct drm_encoder *encoder) 919{ 920 struct drm_device *dev = encoder->dev; 921 struct drm_i915_private *dev_priv = dev->dev_private; 922 u32 dpa_ctl; 923 924 dpa_ctl = I915_READ(DP_A); 925 dpa_ctl &= ~DP_PLL_ENABLE; 926 I915_WRITE(DP_A, dpa_ctl); 927 POSTING_READ(DP_A); 928 udelay(200); 929} 930 931static void intel_dp_prepare(struct drm_encoder *encoder) 932{ 933 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 934 struct drm_device *dev = encoder->dev; 935 936 if (is_edp(intel_dp)) { 937 ironlake_edp_backlight_off(dev); 938 ironlake_edp_panel_on(intel_dp); 939 if (!is_pch_edp(intel_dp)) 940 ironlake_edp_pll_on(encoder); 941 else 942 ironlake_edp_pll_off(encoder); 943 } 944 intel_dp_link_down(intel_dp); 945} 946 947static void intel_dp_commit(struct drm_encoder *encoder) 948{ 949 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 950 struct drm_device *dev = encoder->dev; 951 952 intel_dp_start_link_train(intel_dp); 953 954 if (is_edp(intel_dp)) 955 ironlake_edp_panel_on(intel_dp); 956 957 intel_dp_complete_link_train(intel_dp); 958 959 if (is_edp(intel_dp)) 960 ironlake_edp_backlight_on(dev); 961} 962 963static void 964intel_dp_dpms(struct drm_encoder *encoder, int mode) 965{ 966 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 967 struct drm_device *dev = encoder->dev; 968 struct drm_i915_private *dev_priv = dev->dev_private; 969 uint32_t dp_reg = I915_READ(intel_dp->output_reg); 970 971 if (mode != DRM_MODE_DPMS_ON) { 972 if (is_edp(intel_dp)) 973 ironlake_edp_backlight_off(dev); 974 intel_dp_link_down(intel_dp); 975 if (is_edp(intel_dp)) 976 ironlake_edp_panel_off(dev); 977 if (is_edp(intel_dp) && !is_pch_edp(intel_dp)) 978 ironlake_edp_pll_off(encoder); 979 } else { 980 if (is_edp(intel_dp)) 981 ironlake_edp_panel_on(intel_dp); 982 if (!(dp_reg & DP_PORT_EN)) { 983 intel_dp_start_link_train(intel_dp); 984 intel_dp_complete_link_train(intel_dp); 985 } 986 if (is_edp(intel_dp)) 987 ironlake_edp_backlight_on(dev); 988 } 989 intel_dp->dpms_mode = mode; 990} 991 992/* 993 * Fetch AUX CH registers 0x202 - 0x207 which contain 994 * link status information 995 */ 996static bool 997intel_dp_get_link_status(struct intel_dp *intel_dp) 998{ 999 int ret; 1000 1001 ret = intel_dp_aux_native_read(intel_dp, 1002 DP_LANE0_1_STATUS, 1003 intel_dp->link_status, DP_LINK_STATUS_SIZE); 1004 if (ret != DP_LINK_STATUS_SIZE) 1005 return false; 1006 return true; 1007} 1008 1009static uint8_t 1010intel_dp_link_status(uint8_t link_status[DP_LINK_STATUS_SIZE], 1011 int r) 1012{ 1013 return link_status[r - DP_LANE0_1_STATUS]; 1014} 1015 1016static uint8_t 1017intel_get_adjust_request_voltage(uint8_t link_status[DP_LINK_STATUS_SIZE], 1018 int lane) 1019{ 1020 int i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1); 1021 int s = ((lane & 1) ? 1022 DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT : 1023 DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT); 1024 uint8_t l = intel_dp_link_status(link_status, i); 1025 1026 return ((l >> s) & 3) << DP_TRAIN_VOLTAGE_SWING_SHIFT; 1027} 1028 1029static uint8_t 1030intel_get_adjust_request_pre_emphasis(uint8_t link_status[DP_LINK_STATUS_SIZE], 1031 int lane) 1032{ 1033 int i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1); 1034 int s = ((lane & 1) ? 1035 DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT : 1036 DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT); 1037 uint8_t l = intel_dp_link_status(link_status, i); 1038 1039 return ((l >> s) & 3) << DP_TRAIN_PRE_EMPHASIS_SHIFT; 1040} 1041 1042 1043#if 0 1044static char *voltage_names[] = { 1045 "0.4V", "0.6V", "0.8V", "1.2V" 1046}; 1047static char *pre_emph_names[] = { 1048 "0dB", "3.5dB", "6dB", "9.5dB" 1049}; 1050static char *link_train_names[] = { 1051 "pattern 1", "pattern 2", "idle", "off" 1052}; 1053#endif 1054 1055/* 1056 * These are source-specific values; current Intel hardware supports 1057 * a maximum voltage of 800mV and a maximum pre-emphasis of 6dB 1058 */ 1059#define I830_DP_VOLTAGE_MAX DP_TRAIN_VOLTAGE_SWING_800 1060 1061static uint8_t 1062intel_dp_pre_emphasis_max(uint8_t voltage_swing) 1063{ 1064 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) { 1065 case DP_TRAIN_VOLTAGE_SWING_400: 1066 return DP_TRAIN_PRE_EMPHASIS_6; 1067 case DP_TRAIN_VOLTAGE_SWING_600: 1068 return DP_TRAIN_PRE_EMPHASIS_6; 1069 case DP_TRAIN_VOLTAGE_SWING_800: 1070 return DP_TRAIN_PRE_EMPHASIS_3_5; 1071 case DP_TRAIN_VOLTAGE_SWING_1200: 1072 default: 1073 return DP_TRAIN_PRE_EMPHASIS_0; 1074 } 1075} 1076 1077static void 1078intel_get_adjust_train(struct intel_dp *intel_dp) 1079{ 1080 uint8_t v = 0; 1081 uint8_t p = 0; 1082 int lane; 1083 1084 for (lane = 0; lane < intel_dp->lane_count; lane++) { 1085 uint8_t this_v = intel_get_adjust_request_voltage(intel_dp->link_status, lane); 1086 uint8_t this_p = intel_get_adjust_request_pre_emphasis(intel_dp->link_status, lane); 1087 1088 if (this_v > v) 1089 v = this_v; 1090 if (this_p > p) 1091 p = this_p; 1092 } 1093 1094 if (v >= I830_DP_VOLTAGE_MAX) 1095 v = I830_DP_VOLTAGE_MAX | DP_TRAIN_MAX_SWING_REACHED; 1096 1097 if (p >= intel_dp_pre_emphasis_max(v)) 1098 p = intel_dp_pre_emphasis_max(v) | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED; 1099 1100 for (lane = 0; lane < 4; lane++) 1101 intel_dp->train_set[lane] = v | p; 1102} 1103 1104static uint32_t 1105intel_dp_signal_levels(uint8_t train_set, int lane_count) 1106{ 1107 uint32_t signal_levels = 0; 1108 1109 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { 1110 case DP_TRAIN_VOLTAGE_SWING_400: 1111 default: 1112 signal_levels |= DP_VOLTAGE_0_4; 1113 break; 1114 case DP_TRAIN_VOLTAGE_SWING_600: 1115 signal_levels |= DP_VOLTAGE_0_6; 1116 break; 1117 case DP_TRAIN_VOLTAGE_SWING_800: 1118 signal_levels |= DP_VOLTAGE_0_8; 1119 break; 1120 case DP_TRAIN_VOLTAGE_SWING_1200: 1121 signal_levels |= DP_VOLTAGE_1_2; 1122 break; 1123 } 1124 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) { 1125 case DP_TRAIN_PRE_EMPHASIS_0: 1126 default: 1127 signal_levels |= DP_PRE_EMPHASIS_0; 1128 break; 1129 case DP_TRAIN_PRE_EMPHASIS_3_5: 1130 signal_levels |= DP_PRE_EMPHASIS_3_5; 1131 break; 1132 case DP_TRAIN_PRE_EMPHASIS_6: 1133 signal_levels |= DP_PRE_EMPHASIS_6; 1134 break; 1135 case DP_TRAIN_PRE_EMPHASIS_9_5: 1136 signal_levels |= DP_PRE_EMPHASIS_9_5; 1137 break; 1138 } 1139 return signal_levels; 1140} 1141 1142/* Gen6's DP voltage swing and pre-emphasis control */ 1143static uint32_t 1144intel_gen6_edp_signal_levels(uint8_t train_set) 1145{ 1146 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK | 1147 DP_TRAIN_PRE_EMPHASIS_MASK); 1148 switch (signal_levels) { 1149 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0: 1150 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0: 1151 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B; 1152 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5: 1153 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B; 1154 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6: 1155 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6: 1156 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B; 1157 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5: 1158 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5: 1159 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B; 1160 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0: 1161 case DP_TRAIN_VOLTAGE_SWING_1200 | DP_TRAIN_PRE_EMPHASIS_0: 1162 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B; 1163 default: 1164 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:" 1165 "0x%x\n", signal_levels); 1166 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B; 1167 } 1168} 1169 1170static uint8_t 1171intel_get_lane_status(uint8_t link_status[DP_LINK_STATUS_SIZE], 1172 int lane) 1173{ 1174 int i = DP_LANE0_1_STATUS + (lane >> 1); 1175 int s = (lane & 1) * 4; 1176 uint8_t l = intel_dp_link_status(link_status, i); 1177 1178 return (l >> s) & 0xf; 1179} 1180 1181/* Check for clock recovery is done on all channels */ 1182static bool 1183intel_clock_recovery_ok(uint8_t link_status[DP_LINK_STATUS_SIZE], int lane_count) 1184{ 1185 int lane; 1186 uint8_t lane_status; 1187 1188 for (lane = 0; lane < lane_count; lane++) { 1189 lane_status = intel_get_lane_status(link_status, lane); 1190 if ((lane_status & DP_LANE_CR_DONE) == 0) 1191 return false; 1192 } 1193 return true; 1194} 1195 1196/* Check to see if channel eq is done on all channels */ 1197#define CHANNEL_EQ_BITS (DP_LANE_CR_DONE|\ 1198 DP_LANE_CHANNEL_EQ_DONE|\ 1199 DP_LANE_SYMBOL_LOCKED) 1200static bool 1201intel_channel_eq_ok(struct intel_dp *intel_dp) 1202{ 1203 uint8_t lane_align; 1204 uint8_t lane_status; 1205 int lane; 1206 1207 lane_align = intel_dp_link_status(intel_dp->link_status, 1208 DP_LANE_ALIGN_STATUS_UPDATED); 1209 if ((lane_align & DP_INTERLANE_ALIGN_DONE) == 0) 1210 return false; 1211 for (lane = 0; lane < intel_dp->lane_count; lane++) { 1212 lane_status = intel_get_lane_status(intel_dp->link_status, lane); 1213 if ((lane_status & CHANNEL_EQ_BITS) != CHANNEL_EQ_BITS) 1214 return false; 1215 } 1216 return true; 1217} 1218 1219static bool 1220intel_dp_set_link_train(struct intel_dp *intel_dp, 1221 uint32_t dp_reg_value, 1222 uint8_t dp_train_pat) 1223{ 1224 struct drm_device *dev = intel_dp->base.base.dev; 1225 struct drm_i915_private *dev_priv = dev->dev_private; 1226 int ret; 1227 1228 I915_WRITE(intel_dp->output_reg, dp_reg_value); 1229 POSTING_READ(intel_dp->output_reg); 1230 1231 intel_dp_aux_native_write_1(intel_dp, 1232 DP_TRAINING_PATTERN_SET, 1233 dp_train_pat); 1234 1235 ret = intel_dp_aux_native_write(intel_dp, 1236 DP_TRAINING_LANE0_SET, 1237 intel_dp->train_set, 4); 1238 if (ret != 4) 1239 return false; 1240 1241 return true; 1242} 1243 1244/* Enable corresponding port and start training pattern 1 */ 1245static void 1246intel_dp_start_link_train(struct intel_dp *intel_dp) 1247{ 1248 struct drm_device *dev = intel_dp->base.base.dev; 1249 struct drm_i915_private *dev_priv = dev->dev_private; 1250 struct intel_crtc *intel_crtc = to_intel_crtc(intel_dp->base.base.crtc); 1251 int i; 1252 uint8_t voltage; 1253 bool clock_recovery = false; 1254 int tries; 1255 u32 reg; 1256 uint32_t DP = intel_dp->DP; 1257 1258 /* Enable output, wait for it to become active */ 1259 I915_WRITE(intel_dp->output_reg, intel_dp->DP); 1260 POSTING_READ(intel_dp->output_reg); 1261 intel_wait_for_vblank(dev, intel_crtc->pipe); 1262 1263 /* Write the link configuration data */ 1264 intel_dp_aux_native_write(intel_dp, DP_LINK_BW_SET, 1265 intel_dp->link_configuration, 1266 DP_LINK_CONFIGURATION_SIZE); 1267 1268 DP |= DP_PORT_EN; 1269 if (HAS_PCH_CPT(dev) && !is_edp(intel_dp)) 1270 DP &= ~DP_LINK_TRAIN_MASK_CPT; 1271 else 1272 DP &= ~DP_LINK_TRAIN_MASK; 1273 memset(intel_dp->train_set, 0, 4); 1274 voltage = 0xff; 1275 tries = 0; 1276 clock_recovery = false; 1277 for (;;) { 1278 /* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */ 1279 uint32_t signal_levels; 1280 if (IS_GEN6(dev) && is_edp(intel_dp)) { 1281 signal_levels = intel_gen6_edp_signal_levels(intel_dp->train_set[0]); 1282 DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB) | signal_levels; 1283 } else { 1284 signal_levels = intel_dp_signal_levels(intel_dp->train_set[0], intel_dp->lane_count); 1285 DP = (DP & ~(DP_VOLTAGE_MASK|DP_PRE_EMPHASIS_MASK)) | signal_levels; 1286 } 1287 1288 if (HAS_PCH_CPT(dev) && !is_edp(intel_dp)) 1289 reg = DP | DP_LINK_TRAIN_PAT_1_CPT; 1290 else 1291 reg = DP | DP_LINK_TRAIN_PAT_1; 1292 1293 if (!intel_dp_set_link_train(intel_dp, reg, 1294 DP_TRAINING_PATTERN_1)) 1295 break; 1296 /* Set training pattern 1 */ 1297 1298 udelay(100); 1299 if (!intel_dp_get_link_status(intel_dp)) 1300 break; 1301 1302 if (intel_clock_recovery_ok(intel_dp->link_status, intel_dp->lane_count)) { 1303 clock_recovery = true; 1304 break; 1305 } 1306 1307 /* Check to see if we've tried the max voltage */ 1308 for (i = 0; i < intel_dp->lane_count; i++) 1309 if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0) 1310 break; 1311 if (i == intel_dp->lane_count) 1312 break; 1313 1314 /* Check to see if we've tried the same voltage 5 times */ 1315 if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) { 1316 ++tries; 1317 if (tries == 5) 1318 break; 1319 } else 1320 tries = 0; 1321 voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK; 1322 1323 /* Compute new intel_dp->train_set as requested by target */ 1324 intel_get_adjust_train(intel_dp); 1325 } 1326 1327 intel_dp->DP = DP; 1328} 1329 1330static void 1331intel_dp_complete_link_train(struct intel_dp *intel_dp) 1332{ 1333 struct drm_device *dev = intel_dp->base.base.dev; 1334 struct drm_i915_private *dev_priv = dev->dev_private; 1335 bool channel_eq = false; 1336 int tries, cr_tries; 1337 u32 reg; 1338 uint32_t DP = intel_dp->DP; 1339 1340 /* channel equalization */ 1341 tries = 0; 1342 cr_tries = 0; 1343 channel_eq = false; 1344 for (;;) { 1345 /* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */ 1346 uint32_t signal_levels; 1347 1348 if (cr_tries > 5) { 1349 DRM_ERROR("failed to train DP, aborting\n"); 1350 intel_dp_link_down(intel_dp); 1351 break; 1352 } 1353 1354 if (IS_GEN6(dev) && is_edp(intel_dp)) { 1355 signal_levels = intel_gen6_edp_signal_levels(intel_dp->train_set[0]); 1356 DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB) | signal_levels; 1357 } else { 1358 signal_levels = intel_dp_signal_levels(intel_dp->train_set[0], intel_dp->lane_count); 1359 DP = (DP & ~(DP_VOLTAGE_MASK|DP_PRE_EMPHASIS_MASK)) | signal_levels; 1360 } 1361 1362 if (HAS_PCH_CPT(dev) && !is_edp(intel_dp)) 1363 reg = DP | DP_LINK_TRAIN_PAT_2_CPT; 1364 else 1365 reg = DP | DP_LINK_TRAIN_PAT_2; 1366 1367 /* channel eq pattern */ 1368 if (!intel_dp_set_link_train(intel_dp, reg, 1369 DP_TRAINING_PATTERN_2)) 1370 break; 1371 1372 udelay(400); 1373 if (!intel_dp_get_link_status(intel_dp)) 1374 break; 1375 1376 /* Make sure clock is still ok */ 1377 if (!intel_clock_recovery_ok(intel_dp->link_status, intel_dp->lane_count)) { 1378 intel_dp_start_link_train(intel_dp); 1379 cr_tries++; 1380 continue; 1381 } 1382 1383 if (intel_channel_eq_ok(intel_dp)) { 1384 channel_eq = true; 1385 break; 1386 } 1387 1388 /* Try 5 times, then try clock recovery if that fails */ 1389 if (tries > 5) { 1390 intel_dp_link_down(intel_dp); 1391 intel_dp_start_link_train(intel_dp); 1392 tries = 0; 1393 cr_tries++; 1394 continue; 1395 } 1396 1397 /* Compute new intel_dp->train_set as requested by target */ 1398 intel_get_adjust_train(intel_dp); 1399 ++tries; 1400 } 1401 1402 if (HAS_PCH_CPT(dev) && !is_edp(intel_dp)) 1403 reg = DP | DP_LINK_TRAIN_OFF_CPT; 1404 else 1405 reg = DP | DP_LINK_TRAIN_OFF; 1406 1407 I915_WRITE(intel_dp->output_reg, reg); 1408 POSTING_READ(intel_dp->output_reg); 1409 intel_dp_aux_native_write_1(intel_dp, 1410 DP_TRAINING_PATTERN_SET, DP_TRAINING_PATTERN_DISABLE); 1411} 1412 1413static void 1414intel_dp_link_down(struct intel_dp *intel_dp) 1415{ 1416 struct drm_device *dev = intel_dp->base.base.dev; 1417 struct drm_i915_private *dev_priv = dev->dev_private; 1418 uint32_t DP = intel_dp->DP; 1419 1420 if ((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0) 1421 return; 1422 1423 DRM_DEBUG_KMS("\n"); 1424 1425 if (is_edp(intel_dp)) { 1426 DP &= ~DP_PLL_ENABLE; 1427 I915_WRITE(intel_dp->output_reg, DP); 1428 POSTING_READ(intel_dp->output_reg); 1429 udelay(100); 1430 } 1431 1432 if (HAS_PCH_CPT(dev) && !is_edp(intel_dp)) { 1433 DP &= ~DP_LINK_TRAIN_MASK_CPT; 1434 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT); 1435 } else { 1436 DP &= ~DP_LINK_TRAIN_MASK; 1437 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE); 1438 } 1439 POSTING_READ(intel_dp->output_reg); 1440 1441 msleep(17); 1442 1443 if (is_edp(intel_dp)) 1444 DP |= DP_LINK_TRAIN_OFF; 1445 1446 if (!HAS_PCH_CPT(dev) && 1447 I915_READ(intel_dp->output_reg) & DP_PIPEB_SELECT) { 1448 struct intel_crtc *intel_crtc = to_intel_crtc(intel_dp->base.base.crtc); 1449 /* Hardware workaround: leaving our transcoder select 1450 * set to transcoder B while it's off will prevent the 1451 * corresponding HDMI output on transcoder A. 1452 * 1453 * Combine this with another hardware workaround: 1454 * transcoder select bit can only be cleared while the 1455 * port is enabled. 1456 */ 1457 DP &= ~DP_PIPEB_SELECT; 1458 I915_WRITE(intel_dp->output_reg, DP); 1459 1460 /* Changes to enable or select take place the vblank 1461 * after being written. 1462 */ 1463 intel_wait_for_vblank(dev, intel_crtc->pipe); 1464 } 1465 1466 I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN); 1467 POSTING_READ(intel_dp->output_reg); 1468} 1469 1470/* 1471 * According to DP spec 1472 * 5.1.2: 1473 * 1. Read DPCD 1474 * 2. Configure link according to Receiver Capabilities 1475 * 3. Use Link Training from 2.5.3.3 and 3.5.1.3 1476 * 4. Check link status on receipt of hot-plug interrupt 1477 */ 1478 1479static void 1480intel_dp_check_link_status(struct intel_dp *intel_dp) 1481{ 1482 if (!intel_dp->base.base.crtc) 1483 return; 1484 1485 if (!intel_dp_get_link_status(intel_dp)) { 1486 intel_dp_link_down(intel_dp); 1487 return; 1488 } 1489 1490 if (!intel_channel_eq_ok(intel_dp)) { 1491 intel_dp_start_link_train(intel_dp); 1492 intel_dp_complete_link_train(intel_dp); 1493 } 1494} 1495 1496static enum drm_connector_status 1497ironlake_dp_detect(struct intel_dp *intel_dp) 1498{ 1499 enum drm_connector_status status; 1500 1501 /* Can't disconnect eDP */ 1502 if (is_edp(intel_dp)) 1503 return connector_status_connected; 1504 1505 status = connector_status_disconnected; 1506 if (intel_dp_aux_native_read(intel_dp, 1507 0x000, intel_dp->dpcd, 1508 sizeof (intel_dp->dpcd)) 1509 == sizeof(intel_dp->dpcd)) { 1510 if (intel_dp->dpcd[0] != 0) 1511 status = connector_status_connected; 1512 } 1513 DRM_DEBUG_KMS("DPCD: %hx%hx%hx%hx\n", intel_dp->dpcd[0], 1514 intel_dp->dpcd[1], intel_dp->dpcd[2], intel_dp->dpcd[3]); 1515 return status; 1516} 1517 1518static enum drm_connector_status 1519g4x_dp_detect(struct intel_dp *intel_dp) 1520{ 1521 struct drm_device *dev = intel_dp->base.base.dev; 1522 struct drm_i915_private *dev_priv = dev->dev_private; 1523 enum drm_connector_status status; 1524 uint32_t temp, bit; 1525 1526 switch (intel_dp->output_reg) { 1527 case DP_B: 1528 bit = DPB_HOTPLUG_INT_STATUS; 1529 break; 1530 case DP_C: 1531 bit = DPC_HOTPLUG_INT_STATUS; 1532 break; 1533 case DP_D: 1534 bit = DPD_HOTPLUG_INT_STATUS; 1535 break; 1536 default: 1537 return connector_status_unknown; 1538 } 1539 1540 temp = I915_READ(PORT_HOTPLUG_STAT); 1541 1542 if ((temp & bit) == 0) 1543 return connector_status_disconnected; 1544 1545 status = connector_status_disconnected; 1546 if (intel_dp_aux_native_read(intel_dp, 0x000, intel_dp->dpcd, 1547 sizeof (intel_dp->dpcd)) == sizeof (intel_dp->dpcd)) 1548 { 1549 if (intel_dp->dpcd[0] != 0) 1550 status = connector_status_connected; 1551 } 1552 1553 return status; 1554} 1555 1556/** 1557 * Uses CRT_HOTPLUG_EN and CRT_HOTPLUG_STAT to detect DP connection. 1558 * 1559 * \return true if DP port is connected. 1560 * \return false if DP port is disconnected. 1561 */ 1562static enum drm_connector_status 1563intel_dp_detect(struct drm_connector *connector, bool force) 1564{ 1565 struct intel_dp *intel_dp = intel_attached_dp(connector); 1566 struct drm_device *dev = intel_dp->base.base.dev; 1567 enum drm_connector_status status; 1568 struct edid *edid = NULL; 1569 1570 intel_dp->has_audio = false; 1571 1572 if (HAS_PCH_SPLIT(dev)) 1573 status = ironlake_dp_detect(intel_dp); 1574 else 1575 status = g4x_dp_detect(intel_dp); 1576 if (status != connector_status_connected) 1577 return status; 1578 1579 if (intel_dp->force_audio) { 1580 intel_dp->has_audio = intel_dp->force_audio > 0; 1581 } else { 1582 edid = drm_get_edid(connector, &intel_dp->adapter); 1583 if (edid) { 1584 intel_dp->has_audio = drm_detect_monitor_audio(edid); 1585 connector->display_info.raw_edid = NULL; 1586 kfree(edid); 1587 } 1588 } 1589 1590 return connector_status_connected; 1591} 1592 1593static int intel_dp_get_modes(struct drm_connector *connector) 1594{ 1595 struct intel_dp *intel_dp = intel_attached_dp(connector); 1596 struct drm_device *dev = intel_dp->base.base.dev; 1597 struct drm_i915_private *dev_priv = dev->dev_private; 1598 int ret; 1599 1600 /* We should parse the EDID data and find out if it has an audio sink 1601 */ 1602 1603 ret = intel_ddc_get_modes(connector, &intel_dp->adapter); 1604 if (ret) { 1605 if (is_edp(intel_dp) && !dev_priv->panel_fixed_mode) { 1606 struct drm_display_mode *newmode; 1607 list_for_each_entry(newmode, &connector->probed_modes, 1608 head) { 1609 if (newmode->type & DRM_MODE_TYPE_PREFERRED) { 1610 dev_priv->panel_fixed_mode = 1611 drm_mode_duplicate(dev, newmode); 1612 break; 1613 } 1614 } 1615 } 1616 1617 return ret; 1618 } 1619 1620 /* if eDP has no EDID, try to use fixed panel mode from VBT */ 1621 if (is_edp(intel_dp)) { 1622 if (dev_priv->panel_fixed_mode != NULL) { 1623 struct drm_display_mode *mode; 1624 mode = drm_mode_duplicate(dev, dev_priv->panel_fixed_mode); 1625 drm_mode_probed_add(connector, mode); 1626 return 1; 1627 } 1628 } 1629 return 0; 1630} 1631 1632static int 1633intel_dp_set_property(struct drm_connector *connector, 1634 struct drm_property *property, 1635 uint64_t val) 1636{ 1637 struct intel_dp *intel_dp = intel_attached_dp(connector); 1638 int ret; 1639 1640 ret = drm_connector_property_set_value(connector, property, val); 1641 if (ret) 1642 return ret; 1643 1644 if (property == intel_dp->force_audio_property) { 1645 if (val == intel_dp->force_audio) 1646 return 0; 1647 1648 intel_dp->force_audio = val; 1649 1650 if (val > 0 && intel_dp->has_audio) 1651 return 0; 1652 if (val < 0 && !intel_dp->has_audio) 1653 return 0; 1654 1655 intel_dp->has_audio = val > 0; 1656 goto done; 1657 } 1658 1659 return -EINVAL; 1660 1661done: 1662 if (intel_dp->base.base.crtc) { 1663 struct drm_crtc *crtc = intel_dp->base.base.crtc; 1664 drm_crtc_helper_set_mode(crtc, &crtc->mode, 1665 crtc->x, crtc->y, 1666 crtc->fb); 1667 } 1668 1669 return 0; 1670} 1671 1672static void 1673intel_dp_destroy (struct drm_connector *connector) 1674{ 1675 drm_sysfs_connector_remove(connector); 1676 drm_connector_cleanup(connector); 1677 kfree(connector); 1678} 1679 1680static void intel_dp_encoder_destroy(struct drm_encoder *encoder) 1681{ 1682 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 1683 1684 i2c_del_adapter(&intel_dp->adapter); 1685 drm_encoder_cleanup(encoder); 1686 kfree(intel_dp); 1687} 1688 1689static const struct drm_encoder_helper_funcs intel_dp_helper_funcs = { 1690 .dpms = intel_dp_dpms, 1691 .mode_fixup = intel_dp_mode_fixup, 1692 .prepare = intel_dp_prepare, 1693 .mode_set = intel_dp_mode_set, 1694 .commit = intel_dp_commit, 1695}; 1696 1697static const struct drm_connector_funcs intel_dp_connector_funcs = { 1698 .dpms = drm_helper_connector_dpms, 1699 .detect = intel_dp_detect, 1700 .fill_modes = drm_helper_probe_single_connector_modes, 1701 .set_property = intel_dp_set_property, 1702 .destroy = intel_dp_destroy, 1703}; 1704 1705static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = { 1706 .get_modes = intel_dp_get_modes, 1707 .mode_valid = intel_dp_mode_valid, 1708 .best_encoder = intel_best_encoder, 1709}; 1710 1711static const struct drm_encoder_funcs intel_dp_enc_funcs = { 1712 .destroy = intel_dp_encoder_destroy, 1713}; 1714 1715static void 1716intel_dp_hot_plug(struct intel_encoder *intel_encoder) 1717{ 1718 struct intel_dp *intel_dp = container_of(intel_encoder, struct intel_dp, base); 1719 1720 if (intel_dp->dpms_mode == DRM_MODE_DPMS_ON) 1721 intel_dp_check_link_status(intel_dp); 1722} 1723 1724/* Return which DP Port should be selected for Transcoder DP control */ 1725int 1726intel_trans_dp_port_sel (struct drm_crtc *crtc) 1727{ 1728 struct drm_device *dev = crtc->dev; 1729 struct drm_mode_config *mode_config = &dev->mode_config; 1730 struct drm_encoder *encoder; 1731 1732 list_for_each_entry(encoder, &mode_config->encoder_list, head) { 1733 struct intel_dp *intel_dp; 1734 1735 if (encoder->crtc != crtc) 1736 continue; 1737 1738 intel_dp = enc_to_intel_dp(encoder); 1739 if (intel_dp->base.type == INTEL_OUTPUT_DISPLAYPORT) 1740 return intel_dp->output_reg; 1741 } 1742 1743 return -1; 1744} 1745 1746/* check the VBT to see whether the eDP is on DP-D port */ 1747bool intel_dpd_is_edp(struct drm_device *dev) 1748{ 1749 struct drm_i915_private *dev_priv = dev->dev_private; 1750 struct child_device_config *p_child; 1751 int i; 1752 1753 if (!dev_priv->child_dev_num) 1754 return false; 1755 1756 for (i = 0; i < dev_priv->child_dev_num; i++) { 1757 p_child = dev_priv->child_dev + i; 1758 1759 if (p_child->dvo_port == PORT_IDPD && 1760 p_child->device_type == DEVICE_TYPE_eDP) 1761 return true; 1762 } 1763 return false; 1764} 1765 1766static void 1767intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector) 1768{ 1769 struct drm_device *dev = connector->dev; 1770 1771 intel_dp->force_audio_property = 1772 drm_property_create(dev, DRM_MODE_PROP_RANGE, "force_audio", 2); 1773 if (intel_dp->force_audio_property) { 1774 intel_dp->force_audio_property->values[0] = -1; 1775 intel_dp->force_audio_property->values[1] = 1; 1776 drm_connector_attach_property(connector, intel_dp->force_audio_property, 0); 1777 } 1778} 1779 1780void 1781intel_dp_init(struct drm_device *dev, int output_reg) 1782{ 1783 struct drm_i915_private *dev_priv = dev->dev_private; 1784 struct drm_connector *connector; 1785 struct intel_dp *intel_dp; 1786 struct intel_encoder *intel_encoder; 1787 struct intel_connector *intel_connector; 1788 const char *name = NULL; 1789 int type; 1790 1791 intel_dp = kzalloc(sizeof(struct intel_dp), GFP_KERNEL); 1792 if (!intel_dp) 1793 return; 1794 1795 intel_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL); 1796 if (!intel_connector) { 1797 kfree(intel_dp); 1798 return; 1799 } 1800 intel_encoder = &intel_dp->base; 1801 1802 if (HAS_PCH_SPLIT(dev) && output_reg == PCH_DP_D) 1803 if (intel_dpd_is_edp(dev)) 1804 intel_dp->is_pch_edp = true; 1805 1806 if (output_reg == DP_A || is_pch_edp(intel_dp)) { 1807 type = DRM_MODE_CONNECTOR_eDP; 1808 intel_encoder->type = INTEL_OUTPUT_EDP; 1809 } else { 1810 type = DRM_MODE_CONNECTOR_DisplayPort; 1811 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT; 1812 } 1813 1814 connector = &intel_connector->base; 1815 drm_connector_init(dev, connector, &intel_dp_connector_funcs, type); 1816 drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs); 1817 1818 connector->polled = DRM_CONNECTOR_POLL_HPD; 1819 1820 if (output_reg == DP_B || output_reg == PCH_DP_B) 1821 intel_encoder->clone_mask = (1 << INTEL_DP_B_CLONE_BIT); 1822 else if (output_reg == DP_C || output_reg == PCH_DP_C) 1823 intel_encoder->clone_mask = (1 << INTEL_DP_C_CLONE_BIT); 1824 else if (output_reg == DP_D || output_reg == PCH_DP_D) 1825 intel_encoder->clone_mask = (1 << INTEL_DP_D_CLONE_BIT); 1826 1827 if (is_edp(intel_dp)) 1828 intel_encoder->clone_mask = (1 << INTEL_EDP_CLONE_BIT); 1829 1830 intel_encoder->crtc_mask = (1 << 0) | (1 << 1); 1831 connector->interlace_allowed = true; 1832 connector->doublescan_allowed = 0; 1833 1834 intel_dp->output_reg = output_reg; 1835 intel_dp->has_audio = false; 1836 intel_dp->dpms_mode = DRM_MODE_DPMS_ON; 1837 1838 drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs, 1839 DRM_MODE_ENCODER_TMDS); 1840 drm_encoder_helper_add(&intel_encoder->base, &intel_dp_helper_funcs); 1841 1842 intel_connector_attach_encoder(intel_connector, intel_encoder); 1843 drm_sysfs_connector_add(connector); 1844 1845 /* Set up the DDC bus. */ 1846 switch (output_reg) { 1847 case DP_A: 1848 name = "DPDDC-A"; 1849 break; 1850 case DP_B: 1851 case PCH_DP_B: 1852 dev_priv->hotplug_supported_mask |= 1853 HDMIB_HOTPLUG_INT_STATUS; 1854 name = "DPDDC-B"; 1855 break; 1856 case DP_C: 1857 case PCH_DP_C: 1858 dev_priv->hotplug_supported_mask |= 1859 HDMIC_HOTPLUG_INT_STATUS; 1860 name = "DPDDC-C"; 1861 break; 1862 case DP_D: 1863 case PCH_DP_D: 1864 dev_priv->hotplug_supported_mask |= 1865 HDMID_HOTPLUG_INT_STATUS; 1866 name = "DPDDC-D"; 1867 break; 1868 } 1869 1870 intel_dp_i2c_init(intel_dp, intel_connector, name); 1871 1872 /* Cache some DPCD data in the eDP case */ 1873 if (is_edp(intel_dp)) { 1874 int ret; 1875 bool was_on; 1876 1877 was_on = ironlake_edp_panel_on(intel_dp); 1878 ret = intel_dp_aux_native_read(intel_dp, DP_DPCD_REV, 1879 intel_dp->dpcd, 1880 sizeof(intel_dp->dpcd)); 1881 if (ret == sizeof(intel_dp->dpcd)) { 1882 if (intel_dp->dpcd[0] >= 0x11) 1883 dev_priv->no_aux_handshake = intel_dp->dpcd[3] & 1884 DP_NO_AUX_HANDSHAKE_LINK_TRAINING; 1885 } else { 1886 DRM_ERROR("failed to retrieve link info\n"); 1887 } 1888 if (!was_on) 1889 ironlake_edp_panel_off(dev); 1890 } 1891 1892 intel_encoder->hot_plug = intel_dp_hot_plug; 1893 1894 if (is_edp(intel_dp)) { 1895 /* initialize panel mode from VBT if available for eDP */ 1896 if (dev_priv->lfp_lvds_vbt_mode) { 1897 dev_priv->panel_fixed_mode = 1898 drm_mode_duplicate(dev, dev_priv->lfp_lvds_vbt_mode); 1899 if (dev_priv->panel_fixed_mode) { 1900 dev_priv->panel_fixed_mode->type |= 1901 DRM_MODE_TYPE_PREFERRED; 1902 } 1903 } 1904 } 1905 1906 intel_dp_add_properties(intel_dp, connector); 1907 1908 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written 1909 * 0xd. Failure to do so will result in spurious interrupts being 1910 * generated on the port when a cable is not attached. 1911 */ 1912 if (IS_G4X(dev) && !IS_GM45(dev)) { 1913 u32 temp = I915_READ(PEG_BAND_GAP_DATA); 1914 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd); 1915 } 1916} 1917