intel_dp.c revision 9bbfd20abe5025adbb0ac75160bd2e41158a9e83
1/* 2 * Copyright © 2008 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 * Authors: 24 * Keith Packard <keithp@keithp.com> 25 * 26 */ 27 28#include <linux/i2c.h> 29#include <linux/slab.h> 30#include <linux/export.h> 31#include <drm/drmP.h> 32#include <drm/drm_crtc.h> 33#include <drm/drm_crtc_helper.h> 34#include <drm/drm_edid.h> 35#include "intel_drv.h" 36#include <drm/i915_drm.h> 37#include "i915_drv.h" 38 39#define DP_LINK_CHECK_TIMEOUT (10 * 1000) 40 41struct dp_link_dpll { 42 int link_bw; 43 struct dpll dpll; 44}; 45 46static const struct dp_link_dpll gen4_dpll[] = { 47 { DP_LINK_BW_1_62, 48 { .p1 = 2, .p2 = 10, .n = 2, .m1 = 23, .m2 = 8 } }, 49 { DP_LINK_BW_2_7, 50 { .p1 = 1, .p2 = 10, .n = 1, .m1 = 14, .m2 = 2 } } 51}; 52 53static const struct dp_link_dpll pch_dpll[] = { 54 { DP_LINK_BW_1_62, 55 { .p1 = 2, .p2 = 10, .n = 1, .m1 = 12, .m2 = 9 } }, 56 { DP_LINK_BW_2_7, 57 { .p1 = 1, .p2 = 10, .n = 2, .m1 = 14, .m2 = 8 } } 58}; 59 60static const struct dp_link_dpll vlv_dpll[] = { 61 { DP_LINK_BW_1_62, 62 { .p1 = 3, .p2 = 2, .n = 5, .m1 = 3, .m2 = 81 } }, 63 { DP_LINK_BW_2_7, 64 { .p1 = 2, .p2 = 2, .n = 1, .m1 = 2, .m2 = 27 } } 65}; 66 67/** 68 * is_edp - is the given port attached to an eDP panel (either CPU or PCH) 69 * @intel_dp: DP struct 70 * 71 * If a CPU or PCH DP output is attached to an eDP panel, this function 72 * will return true, and false otherwise. 73 */ 74static bool is_edp(struct intel_dp *intel_dp) 75{ 76 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 77 78 return intel_dig_port->base.type == INTEL_OUTPUT_EDP; 79} 80 81static struct drm_device *intel_dp_to_dev(struct intel_dp *intel_dp) 82{ 83 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 84 85 return intel_dig_port->base.base.dev; 86} 87 88static struct intel_dp *intel_attached_dp(struct drm_connector *connector) 89{ 90 return enc_to_intel_dp(&intel_attached_encoder(connector)->base); 91} 92 93static void intel_dp_link_down(struct intel_dp *intel_dp); 94static bool _edp_panel_vdd_on(struct intel_dp *intel_dp); 95static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync); 96 97static int 98intel_dp_max_link_bw(struct intel_dp *intel_dp) 99{ 100 int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE]; 101 struct drm_device *dev = intel_dp->attached_connector->base.dev; 102 103 switch (max_link_bw) { 104 case DP_LINK_BW_1_62: 105 case DP_LINK_BW_2_7: 106 break; 107 case DP_LINK_BW_5_4: /* 1.2 capable displays may advertise higher bw */ 108 if (((IS_HASWELL(dev) && !IS_HSW_ULX(dev)) || 109 INTEL_INFO(dev)->gen >= 8) && 110 intel_dp->dpcd[DP_DPCD_REV] >= 0x12) 111 max_link_bw = DP_LINK_BW_5_4; 112 else 113 max_link_bw = DP_LINK_BW_2_7; 114 break; 115 default: 116 WARN(1, "invalid max DP link bw val %x, using 1.62Gbps\n", 117 max_link_bw); 118 max_link_bw = DP_LINK_BW_1_62; 119 break; 120 } 121 return max_link_bw; 122} 123 124/* 125 * The units on the numbers in the next two are... bizarre. Examples will 126 * make it clearer; this one parallels an example in the eDP spec. 127 * 128 * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as: 129 * 130 * 270000 * 1 * 8 / 10 == 216000 131 * 132 * The actual data capacity of that configuration is 2.16Gbit/s, so the 133 * units are decakilobits. ->clock in a drm_display_mode is in kilohertz - 134 * or equivalently, kilopixels per second - so for 1680x1050R it'd be 135 * 119000. At 18bpp that's 2142000 kilobits per second. 136 * 137 * Thus the strange-looking division by 10 in intel_dp_link_required, to 138 * get the result in decakilobits instead of kilobits. 139 */ 140 141static int 142intel_dp_link_required(int pixel_clock, int bpp) 143{ 144 return (pixel_clock * bpp + 9) / 10; 145} 146 147static int 148intel_dp_max_data_rate(int max_link_clock, int max_lanes) 149{ 150 return (max_link_clock * max_lanes * 8) / 10; 151} 152 153static enum drm_mode_status 154intel_dp_mode_valid(struct drm_connector *connector, 155 struct drm_display_mode *mode) 156{ 157 struct intel_dp *intel_dp = intel_attached_dp(connector); 158 struct intel_connector *intel_connector = to_intel_connector(connector); 159 struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode; 160 int target_clock = mode->clock; 161 int max_rate, mode_rate, max_lanes, max_link_clock; 162 163 if (is_edp(intel_dp) && fixed_mode) { 164 if (mode->hdisplay > fixed_mode->hdisplay) 165 return MODE_PANEL; 166 167 if (mode->vdisplay > fixed_mode->vdisplay) 168 return MODE_PANEL; 169 170 target_clock = fixed_mode->clock; 171 } 172 173 max_link_clock = drm_dp_bw_code_to_link_rate(intel_dp_max_link_bw(intel_dp)); 174 max_lanes = drm_dp_max_lane_count(intel_dp->dpcd); 175 176 max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes); 177 mode_rate = intel_dp_link_required(target_clock, 18); 178 179 if (mode_rate > max_rate) 180 return MODE_CLOCK_HIGH; 181 182 if (mode->clock < 10000) 183 return MODE_CLOCK_LOW; 184 185 if (mode->flags & DRM_MODE_FLAG_DBLCLK) 186 return MODE_H_ILLEGAL; 187 188 return MODE_OK; 189} 190 191static uint32_t 192pack_aux(uint8_t *src, int src_bytes) 193{ 194 int i; 195 uint32_t v = 0; 196 197 if (src_bytes > 4) 198 src_bytes = 4; 199 for (i = 0; i < src_bytes; i++) 200 v |= ((uint32_t) src[i]) << ((3-i) * 8); 201 return v; 202} 203 204static void 205unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes) 206{ 207 int i; 208 if (dst_bytes > 4) 209 dst_bytes = 4; 210 for (i = 0; i < dst_bytes; i++) 211 dst[i] = src >> ((3-i) * 8); 212} 213 214/* hrawclock is 1/4 the FSB frequency */ 215static int 216intel_hrawclk(struct drm_device *dev) 217{ 218 struct drm_i915_private *dev_priv = dev->dev_private; 219 uint32_t clkcfg; 220 221 /* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */ 222 if (IS_VALLEYVIEW(dev)) 223 return 200; 224 225 clkcfg = I915_READ(CLKCFG); 226 switch (clkcfg & CLKCFG_FSB_MASK) { 227 case CLKCFG_FSB_400: 228 return 100; 229 case CLKCFG_FSB_533: 230 return 133; 231 case CLKCFG_FSB_667: 232 return 166; 233 case CLKCFG_FSB_800: 234 return 200; 235 case CLKCFG_FSB_1067: 236 return 266; 237 case CLKCFG_FSB_1333: 238 return 333; 239 /* these two are just a guess; one of them might be right */ 240 case CLKCFG_FSB_1600: 241 case CLKCFG_FSB_1600_ALT: 242 return 400; 243 default: 244 return 133; 245 } 246} 247 248static void 249intel_dp_init_panel_power_sequencer(struct drm_device *dev, 250 struct intel_dp *intel_dp, 251 struct edp_power_seq *out); 252static void 253intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev, 254 struct intel_dp *intel_dp, 255 struct edp_power_seq *out); 256 257static enum pipe 258vlv_power_sequencer_pipe(struct intel_dp *intel_dp) 259{ 260 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 261 struct drm_crtc *crtc = intel_dig_port->base.base.crtc; 262 struct drm_device *dev = intel_dig_port->base.base.dev; 263 struct drm_i915_private *dev_priv = dev->dev_private; 264 enum port port = intel_dig_port->port; 265 enum pipe pipe; 266 267 /* modeset should have pipe */ 268 if (crtc) 269 return to_intel_crtc(crtc)->pipe; 270 271 /* init time, try to find a pipe with this port selected */ 272 for (pipe = PIPE_A; pipe <= PIPE_B; pipe++) { 273 u32 port_sel = I915_READ(VLV_PIPE_PP_ON_DELAYS(pipe)) & 274 PANEL_PORT_SELECT_MASK; 275 if (port_sel == PANEL_PORT_SELECT_DPB_VLV && port == PORT_B) 276 return pipe; 277 if (port_sel == PANEL_PORT_SELECT_DPC_VLV && port == PORT_C) 278 return pipe; 279 } 280 281 /* shrug */ 282 return PIPE_A; 283} 284 285static u32 _pp_ctrl_reg(struct intel_dp *intel_dp) 286{ 287 struct drm_device *dev = intel_dp_to_dev(intel_dp); 288 289 if (HAS_PCH_SPLIT(dev)) 290 return PCH_PP_CONTROL; 291 else 292 return VLV_PIPE_PP_CONTROL(vlv_power_sequencer_pipe(intel_dp)); 293} 294 295static u32 _pp_stat_reg(struct intel_dp *intel_dp) 296{ 297 struct drm_device *dev = intel_dp_to_dev(intel_dp); 298 299 if (HAS_PCH_SPLIT(dev)) 300 return PCH_PP_STATUS; 301 else 302 return VLV_PIPE_PP_STATUS(vlv_power_sequencer_pipe(intel_dp)); 303} 304 305static bool edp_have_panel_power(struct intel_dp *intel_dp) 306{ 307 struct drm_device *dev = intel_dp_to_dev(intel_dp); 308 struct drm_i915_private *dev_priv = dev->dev_private; 309 310 return (I915_READ(_pp_stat_reg(intel_dp)) & PP_ON) != 0; 311} 312 313static bool edp_have_panel_vdd(struct intel_dp *intel_dp) 314{ 315 struct drm_device *dev = intel_dp_to_dev(intel_dp); 316 struct drm_i915_private *dev_priv = dev->dev_private; 317 318 return !dev_priv->pm.suspended && 319 (I915_READ(_pp_ctrl_reg(intel_dp)) & EDP_FORCE_VDD) != 0; 320} 321 322static void 323intel_dp_check_edp(struct intel_dp *intel_dp) 324{ 325 struct drm_device *dev = intel_dp_to_dev(intel_dp); 326 struct drm_i915_private *dev_priv = dev->dev_private; 327 328 if (!is_edp(intel_dp)) 329 return; 330 331 if (!edp_have_panel_power(intel_dp) && !edp_have_panel_vdd(intel_dp)) { 332 WARN(1, "eDP powered off while attempting aux channel communication.\n"); 333 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n", 334 I915_READ(_pp_stat_reg(intel_dp)), 335 I915_READ(_pp_ctrl_reg(intel_dp))); 336 } 337} 338 339static uint32_t 340intel_dp_aux_wait_done(struct intel_dp *intel_dp, bool has_aux_irq) 341{ 342 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 343 struct drm_device *dev = intel_dig_port->base.base.dev; 344 struct drm_i915_private *dev_priv = dev->dev_private; 345 uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg; 346 uint32_t status; 347 bool done; 348 349#define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0) 350 if (has_aux_irq) 351 done = wait_event_timeout(dev_priv->gmbus_wait_queue, C, 352 msecs_to_jiffies_timeout(10)); 353 else 354 done = wait_for_atomic(C, 10) == 0; 355 if (!done) 356 DRM_ERROR("dp aux hw did not signal timeout (has irq: %i)!\n", 357 has_aux_irq); 358#undef C 359 360 return status; 361} 362 363static uint32_t i9xx_get_aux_clock_divider(struct intel_dp *intel_dp, int index) 364{ 365 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 366 struct drm_device *dev = intel_dig_port->base.base.dev; 367 368 /* 369 * The clock divider is based off the hrawclk, and would like to run at 370 * 2MHz. So, take the hrawclk value and divide by 2 and use that 371 */ 372 return index ? 0 : intel_hrawclk(dev) / 2; 373} 374 375static uint32_t ilk_get_aux_clock_divider(struct intel_dp *intel_dp, int index) 376{ 377 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 378 struct drm_device *dev = intel_dig_port->base.base.dev; 379 380 if (index) 381 return 0; 382 383 if (intel_dig_port->port == PORT_A) { 384 if (IS_GEN6(dev) || IS_GEN7(dev)) 385 return 200; /* SNB & IVB eDP input clock at 400Mhz */ 386 else 387 return 225; /* eDP input clock at 450Mhz */ 388 } else { 389 return DIV_ROUND_UP(intel_pch_rawclk(dev), 2); 390 } 391} 392 393static uint32_t hsw_get_aux_clock_divider(struct intel_dp *intel_dp, int index) 394{ 395 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 396 struct drm_device *dev = intel_dig_port->base.base.dev; 397 struct drm_i915_private *dev_priv = dev->dev_private; 398 399 if (intel_dig_port->port == PORT_A) { 400 if (index) 401 return 0; 402 return DIV_ROUND_CLOSEST(intel_ddi_get_cdclk_freq(dev_priv), 2000); 403 } else if (dev_priv->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE) { 404 /* Workaround for non-ULT HSW */ 405 switch (index) { 406 case 0: return 63; 407 case 1: return 72; 408 default: return 0; 409 } 410 } else { 411 return index ? 0 : DIV_ROUND_UP(intel_pch_rawclk(dev), 2); 412 } 413} 414 415static uint32_t vlv_get_aux_clock_divider(struct intel_dp *intel_dp, int index) 416{ 417 return index ? 0 : 100; 418} 419 420static uint32_t i9xx_get_aux_send_ctl(struct intel_dp *intel_dp, 421 bool has_aux_irq, 422 int send_bytes, 423 uint32_t aux_clock_divider) 424{ 425 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 426 struct drm_device *dev = intel_dig_port->base.base.dev; 427 uint32_t precharge, timeout; 428 429 if (IS_GEN6(dev)) 430 precharge = 3; 431 else 432 precharge = 5; 433 434 if (IS_BROADWELL(dev) && intel_dp->aux_ch_ctl_reg == DPA_AUX_CH_CTL) 435 timeout = DP_AUX_CH_CTL_TIME_OUT_600us; 436 else 437 timeout = DP_AUX_CH_CTL_TIME_OUT_400us; 438 439 return DP_AUX_CH_CTL_SEND_BUSY | 440 DP_AUX_CH_CTL_DONE | 441 (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) | 442 DP_AUX_CH_CTL_TIME_OUT_ERROR | 443 timeout | 444 DP_AUX_CH_CTL_RECEIVE_ERROR | 445 (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) | 446 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) | 447 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT); 448} 449 450static int 451intel_dp_aux_ch(struct intel_dp *intel_dp, 452 uint8_t *send, int send_bytes, 453 uint8_t *recv, int recv_size) 454{ 455 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 456 struct drm_device *dev = intel_dig_port->base.base.dev; 457 struct drm_i915_private *dev_priv = dev->dev_private; 458 uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg; 459 uint32_t ch_data = ch_ctl + 4; 460 uint32_t aux_clock_divider; 461 int i, ret, recv_bytes; 462 uint32_t status; 463 int try, clock = 0; 464 bool has_aux_irq = HAS_AUX_IRQ(dev); 465 bool vdd; 466 467 vdd = _edp_panel_vdd_on(intel_dp); 468 469 /* dp aux is extremely sensitive to irq latency, hence request the 470 * lowest possible wakeup latency and so prevent the cpu from going into 471 * deep sleep states. 472 */ 473 pm_qos_update_request(&dev_priv->pm_qos, 0); 474 475 intel_dp_check_edp(intel_dp); 476 477 intel_aux_display_runtime_get(dev_priv); 478 479 /* Try to wait for any previous AUX channel activity */ 480 for (try = 0; try < 3; try++) { 481 status = I915_READ_NOTRACE(ch_ctl); 482 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0) 483 break; 484 msleep(1); 485 } 486 487 if (try == 3) { 488 WARN(1, "dp_aux_ch not started status 0x%08x\n", 489 I915_READ(ch_ctl)); 490 ret = -EBUSY; 491 goto out; 492 } 493 494 /* Only 5 data registers! */ 495 if (WARN_ON(send_bytes > 20 || recv_size > 20)) { 496 ret = -E2BIG; 497 goto out; 498 } 499 500 while ((aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, clock++))) { 501 u32 send_ctl = intel_dp->get_aux_send_ctl(intel_dp, 502 has_aux_irq, 503 send_bytes, 504 aux_clock_divider); 505 506 /* Must try at least 3 times according to DP spec */ 507 for (try = 0; try < 5; try++) { 508 /* Load the send data into the aux channel data registers */ 509 for (i = 0; i < send_bytes; i += 4) 510 I915_WRITE(ch_data + i, 511 pack_aux(send + i, send_bytes - i)); 512 513 /* Send the command and wait for it to complete */ 514 I915_WRITE(ch_ctl, send_ctl); 515 516 status = intel_dp_aux_wait_done(intel_dp, has_aux_irq); 517 518 /* Clear done status and any errors */ 519 I915_WRITE(ch_ctl, 520 status | 521 DP_AUX_CH_CTL_DONE | 522 DP_AUX_CH_CTL_TIME_OUT_ERROR | 523 DP_AUX_CH_CTL_RECEIVE_ERROR); 524 525 if (status & (DP_AUX_CH_CTL_TIME_OUT_ERROR | 526 DP_AUX_CH_CTL_RECEIVE_ERROR)) 527 continue; 528 if (status & DP_AUX_CH_CTL_DONE) 529 break; 530 } 531 if (status & DP_AUX_CH_CTL_DONE) 532 break; 533 } 534 535 if ((status & DP_AUX_CH_CTL_DONE) == 0) { 536 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status); 537 ret = -EBUSY; 538 goto out; 539 } 540 541 /* Check for timeout or receive error. 542 * Timeouts occur when the sink is not connected 543 */ 544 if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) { 545 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status); 546 ret = -EIO; 547 goto out; 548 } 549 550 /* Timeouts occur when the device isn't connected, so they're 551 * "normal" -- don't fill the kernel log with these */ 552 if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) { 553 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status); 554 ret = -ETIMEDOUT; 555 goto out; 556 } 557 558 /* Unload any bytes sent back from the other side */ 559 recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >> 560 DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT); 561 if (recv_bytes > recv_size) 562 recv_bytes = recv_size; 563 564 for (i = 0; i < recv_bytes; i += 4) 565 unpack_aux(I915_READ(ch_data + i), 566 recv + i, recv_bytes - i); 567 568 ret = recv_bytes; 569out: 570 pm_qos_update_request(&dev_priv->pm_qos, PM_QOS_DEFAULT_VALUE); 571 intel_aux_display_runtime_put(dev_priv); 572 573 if (vdd) 574 edp_panel_vdd_off(intel_dp, false); 575 576 return ret; 577} 578 579#define BARE_ADDRESS_SIZE 3 580#define HEADER_SIZE (BARE_ADDRESS_SIZE + 1) 581static ssize_t 582intel_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg) 583{ 584 struct intel_dp *intel_dp = container_of(aux, struct intel_dp, aux); 585 uint8_t txbuf[20], rxbuf[20]; 586 size_t txsize, rxsize; 587 int ret; 588 589 txbuf[0] = msg->request << 4; 590 txbuf[1] = msg->address >> 8; 591 txbuf[2] = msg->address & 0xff; 592 txbuf[3] = msg->size - 1; 593 594 switch (msg->request & ~DP_AUX_I2C_MOT) { 595 case DP_AUX_NATIVE_WRITE: 596 case DP_AUX_I2C_WRITE: 597 txsize = msg->size ? HEADER_SIZE + msg->size : BARE_ADDRESS_SIZE; 598 rxsize = 1; 599 600 if (WARN_ON(txsize > 20)) 601 return -E2BIG; 602 603 memcpy(txbuf + HEADER_SIZE, msg->buffer, msg->size); 604 605 ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize); 606 if (ret > 0) { 607 msg->reply = rxbuf[0] >> 4; 608 609 /* Return payload size. */ 610 ret = msg->size; 611 } 612 break; 613 614 case DP_AUX_NATIVE_READ: 615 case DP_AUX_I2C_READ: 616 txsize = msg->size ? HEADER_SIZE : BARE_ADDRESS_SIZE; 617 rxsize = msg->size + 1; 618 619 if (WARN_ON(rxsize > 20)) 620 return -E2BIG; 621 622 ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize); 623 if (ret > 0) { 624 msg->reply = rxbuf[0] >> 4; 625 /* 626 * Assume happy day, and copy the data. The caller is 627 * expected to check msg->reply before touching it. 628 * 629 * Return payload size. 630 */ 631 ret--; 632 memcpy(msg->buffer, rxbuf + 1, ret); 633 } 634 break; 635 636 default: 637 ret = -EINVAL; 638 break; 639 } 640 641 return ret; 642} 643 644static void 645intel_dp_aux_init(struct intel_dp *intel_dp, struct intel_connector *connector) 646{ 647 struct drm_device *dev = intel_dp_to_dev(intel_dp); 648 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 649 enum port port = intel_dig_port->port; 650 const char *name = NULL; 651 int ret; 652 653 switch (port) { 654 case PORT_A: 655 intel_dp->aux_ch_ctl_reg = DPA_AUX_CH_CTL; 656 name = "DPDDC-A"; 657 break; 658 case PORT_B: 659 intel_dp->aux_ch_ctl_reg = PCH_DPB_AUX_CH_CTL; 660 name = "DPDDC-B"; 661 break; 662 case PORT_C: 663 intel_dp->aux_ch_ctl_reg = PCH_DPC_AUX_CH_CTL; 664 name = "DPDDC-C"; 665 break; 666 case PORT_D: 667 intel_dp->aux_ch_ctl_reg = PCH_DPD_AUX_CH_CTL; 668 name = "DPDDC-D"; 669 break; 670 default: 671 BUG(); 672 } 673 674 if (!HAS_DDI(dev)) 675 intel_dp->aux_ch_ctl_reg = intel_dp->output_reg + 0x10; 676 677 intel_dp->aux.name = name; 678 intel_dp->aux.dev = dev->dev; 679 intel_dp->aux.transfer = intel_dp_aux_transfer; 680 681 DRM_DEBUG_KMS("registering %s bus for %s\n", name, 682 connector->base.kdev->kobj.name); 683 684 ret = drm_dp_aux_register_i2c_bus(&intel_dp->aux); 685 if (ret < 0) { 686 DRM_ERROR("drm_dp_aux_register_i2c_bus() for %s failed (%d)\n", 687 name, ret); 688 return; 689 } 690 691 ret = sysfs_create_link(&connector->base.kdev->kobj, 692 &intel_dp->aux.ddc.dev.kobj, 693 intel_dp->aux.ddc.dev.kobj.name); 694 if (ret < 0) { 695 DRM_ERROR("sysfs_create_link() for %s failed (%d)\n", name, ret); 696 drm_dp_aux_unregister_i2c_bus(&intel_dp->aux); 697 } 698} 699 700static void 701intel_dp_connector_unregister(struct intel_connector *intel_connector) 702{ 703 struct intel_dp *intel_dp = intel_attached_dp(&intel_connector->base); 704 705 sysfs_remove_link(&intel_connector->base.kdev->kobj, 706 intel_dp->aux.ddc.dev.kobj.name); 707 intel_connector_unregister(intel_connector); 708} 709 710static void 711intel_dp_set_clock(struct intel_encoder *encoder, 712 struct intel_crtc_config *pipe_config, int link_bw) 713{ 714 struct drm_device *dev = encoder->base.dev; 715 const struct dp_link_dpll *divisor = NULL; 716 int i, count = 0; 717 718 if (IS_G4X(dev)) { 719 divisor = gen4_dpll; 720 count = ARRAY_SIZE(gen4_dpll); 721 } else if (IS_HASWELL(dev)) { 722 /* Haswell has special-purpose DP DDI clocks. */ 723 } else if (HAS_PCH_SPLIT(dev)) { 724 divisor = pch_dpll; 725 count = ARRAY_SIZE(pch_dpll); 726 } else if (IS_VALLEYVIEW(dev)) { 727 divisor = vlv_dpll; 728 count = ARRAY_SIZE(vlv_dpll); 729 } 730 731 if (divisor && count) { 732 for (i = 0; i < count; i++) { 733 if (link_bw == divisor[i].link_bw) { 734 pipe_config->dpll = divisor[i].dpll; 735 pipe_config->clock_set = true; 736 break; 737 } 738 } 739 } 740} 741 742bool 743intel_dp_compute_config(struct intel_encoder *encoder, 744 struct intel_crtc_config *pipe_config) 745{ 746 struct drm_device *dev = encoder->base.dev; 747 struct drm_i915_private *dev_priv = dev->dev_private; 748 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode; 749 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); 750 enum port port = dp_to_dig_port(intel_dp)->port; 751 struct intel_crtc *intel_crtc = encoder->new_crtc; 752 struct intel_connector *intel_connector = intel_dp->attached_connector; 753 int lane_count, clock; 754 int max_lane_count = drm_dp_max_lane_count(intel_dp->dpcd); 755 /* Conveniently, the link BW constants become indices with a shift...*/ 756 int max_clock = intel_dp_max_link_bw(intel_dp) >> 3; 757 int bpp, mode_rate; 758 static int bws[] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7, DP_LINK_BW_5_4 }; 759 int link_avail, link_clock; 760 761 if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev) && port != PORT_A) 762 pipe_config->has_pch_encoder = true; 763 764 pipe_config->has_dp_encoder = true; 765 766 if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) { 767 intel_fixed_panel_mode(intel_connector->panel.fixed_mode, 768 adjusted_mode); 769 if (!HAS_PCH_SPLIT(dev)) 770 intel_gmch_panel_fitting(intel_crtc, pipe_config, 771 intel_connector->panel.fitting_mode); 772 else 773 intel_pch_panel_fitting(intel_crtc, pipe_config, 774 intel_connector->panel.fitting_mode); 775 } 776 777 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK) 778 return false; 779 780 DRM_DEBUG_KMS("DP link computation with max lane count %i " 781 "max bw %02x pixel clock %iKHz\n", 782 max_lane_count, bws[max_clock], 783 adjusted_mode->crtc_clock); 784 785 /* Walk through all bpp values. Luckily they're all nicely spaced with 2 786 * bpc in between. */ 787 bpp = pipe_config->pipe_bpp; 788 if (is_edp(intel_dp) && dev_priv->vbt.edp_bpp && 789 dev_priv->vbt.edp_bpp < bpp) { 790 DRM_DEBUG_KMS("clamping bpp for eDP panel to BIOS-provided %i\n", 791 dev_priv->vbt.edp_bpp); 792 bpp = dev_priv->vbt.edp_bpp; 793 } 794 795 for (; bpp >= 6*3; bpp -= 2*3) { 796 mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock, 797 bpp); 798 799 for (lane_count = 1; lane_count <= max_lane_count; lane_count <<= 1) { 800 for (clock = 0; clock <= max_clock; clock++) { 801 link_clock = drm_dp_bw_code_to_link_rate(bws[clock]); 802 link_avail = intel_dp_max_data_rate(link_clock, 803 lane_count); 804 805 if (mode_rate <= link_avail) { 806 goto found; 807 } 808 } 809 } 810 } 811 812 return false; 813 814found: 815 if (intel_dp->color_range_auto) { 816 /* 817 * See: 818 * CEA-861-E - 5.1 Default Encoding Parameters 819 * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry 820 */ 821 if (bpp != 18 && drm_match_cea_mode(adjusted_mode) > 1) 822 intel_dp->color_range = DP_COLOR_RANGE_16_235; 823 else 824 intel_dp->color_range = 0; 825 } 826 827 if (intel_dp->color_range) 828 pipe_config->limited_color_range = true; 829 830 intel_dp->link_bw = bws[clock]; 831 intel_dp->lane_count = lane_count; 832 pipe_config->pipe_bpp = bpp; 833 pipe_config->port_clock = drm_dp_bw_code_to_link_rate(intel_dp->link_bw); 834 835 DRM_DEBUG_KMS("DP link bw %02x lane count %d clock %d bpp %d\n", 836 intel_dp->link_bw, intel_dp->lane_count, 837 pipe_config->port_clock, bpp); 838 DRM_DEBUG_KMS("DP link bw required %i available %i\n", 839 mode_rate, link_avail); 840 841 intel_link_compute_m_n(bpp, lane_count, 842 adjusted_mode->crtc_clock, 843 pipe_config->port_clock, 844 &pipe_config->dp_m_n); 845 846 intel_dp_set_clock(encoder, pipe_config, intel_dp->link_bw); 847 848 return true; 849} 850 851static void ironlake_set_pll_cpu_edp(struct intel_dp *intel_dp) 852{ 853 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 854 struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc); 855 struct drm_device *dev = crtc->base.dev; 856 struct drm_i915_private *dev_priv = dev->dev_private; 857 u32 dpa_ctl; 858 859 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", crtc->config.port_clock); 860 dpa_ctl = I915_READ(DP_A); 861 dpa_ctl &= ~DP_PLL_FREQ_MASK; 862 863 if (crtc->config.port_clock == 162000) { 864 /* For a long time we've carried around a ILK-DevA w/a for the 865 * 160MHz clock. If we're really unlucky, it's still required. 866 */ 867 DRM_DEBUG_KMS("160MHz cpu eDP clock, might need ilk devA w/a\n"); 868 dpa_ctl |= DP_PLL_FREQ_160MHZ; 869 intel_dp->DP |= DP_PLL_FREQ_160MHZ; 870 } else { 871 dpa_ctl |= DP_PLL_FREQ_270MHZ; 872 intel_dp->DP |= DP_PLL_FREQ_270MHZ; 873 } 874 875 I915_WRITE(DP_A, dpa_ctl); 876 877 POSTING_READ(DP_A); 878 udelay(500); 879} 880 881static void intel_dp_mode_set(struct intel_encoder *encoder) 882{ 883 struct drm_device *dev = encoder->base.dev; 884 struct drm_i915_private *dev_priv = dev->dev_private; 885 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); 886 enum port port = dp_to_dig_port(intel_dp)->port; 887 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); 888 struct drm_display_mode *adjusted_mode = &crtc->config.adjusted_mode; 889 890 /* 891 * There are four kinds of DP registers: 892 * 893 * IBX PCH 894 * SNB CPU 895 * IVB CPU 896 * CPT PCH 897 * 898 * IBX PCH and CPU are the same for almost everything, 899 * except that the CPU DP PLL is configured in this 900 * register 901 * 902 * CPT PCH is quite different, having many bits moved 903 * to the TRANS_DP_CTL register instead. That 904 * configuration happens (oddly) in ironlake_pch_enable 905 */ 906 907 /* Preserve the BIOS-computed detected bit. This is 908 * supposed to be read-only. 909 */ 910 intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED; 911 912 /* Handle DP bits in common between all three register formats */ 913 intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0; 914 intel_dp->DP |= DP_PORT_WIDTH(intel_dp->lane_count); 915 916 if (intel_dp->has_audio) { 917 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n", 918 pipe_name(crtc->pipe)); 919 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE; 920 intel_write_eld(&encoder->base, adjusted_mode); 921 } 922 923 /* Split out the IBX/CPU vs CPT settings */ 924 925 if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) { 926 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) 927 intel_dp->DP |= DP_SYNC_HS_HIGH; 928 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) 929 intel_dp->DP |= DP_SYNC_VS_HIGH; 930 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT; 931 932 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd)) 933 intel_dp->DP |= DP_ENHANCED_FRAMING; 934 935 intel_dp->DP |= crtc->pipe << 29; 936 } else if (!HAS_PCH_CPT(dev) || port == PORT_A) { 937 if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev)) 938 intel_dp->DP |= intel_dp->color_range; 939 940 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) 941 intel_dp->DP |= DP_SYNC_HS_HIGH; 942 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) 943 intel_dp->DP |= DP_SYNC_VS_HIGH; 944 intel_dp->DP |= DP_LINK_TRAIN_OFF; 945 946 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd)) 947 intel_dp->DP |= DP_ENHANCED_FRAMING; 948 949 if (crtc->pipe == 1) 950 intel_dp->DP |= DP_PIPEB_SELECT; 951 } else { 952 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT; 953 } 954 955 if (port == PORT_A && !IS_VALLEYVIEW(dev)) 956 ironlake_set_pll_cpu_edp(intel_dp); 957} 958 959#define IDLE_ON_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK) 960#define IDLE_ON_VALUE (PP_ON | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE) 961 962#define IDLE_OFF_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | 0) 963#define IDLE_OFF_VALUE (0 | PP_SEQUENCE_NONE | 0 | 0) 964 965#define IDLE_CYCLE_MASK (PP_ON | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK) 966#define IDLE_CYCLE_VALUE (0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE) 967 968static void wait_panel_status(struct intel_dp *intel_dp, 969 u32 mask, 970 u32 value) 971{ 972 struct drm_device *dev = intel_dp_to_dev(intel_dp); 973 struct drm_i915_private *dev_priv = dev->dev_private; 974 u32 pp_stat_reg, pp_ctrl_reg; 975 976 pp_stat_reg = _pp_stat_reg(intel_dp); 977 pp_ctrl_reg = _pp_ctrl_reg(intel_dp); 978 979 DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n", 980 mask, value, 981 I915_READ(pp_stat_reg), 982 I915_READ(pp_ctrl_reg)); 983 984 if (_wait_for((I915_READ(pp_stat_reg) & mask) == value, 5000, 10)) { 985 DRM_ERROR("Panel status timeout: status %08x control %08x\n", 986 I915_READ(pp_stat_reg), 987 I915_READ(pp_ctrl_reg)); 988 } 989 990 DRM_DEBUG_KMS("Wait complete\n"); 991} 992 993static void wait_panel_on(struct intel_dp *intel_dp) 994{ 995 DRM_DEBUG_KMS("Wait for panel power on\n"); 996 wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE); 997} 998 999static void wait_panel_off(struct intel_dp *intel_dp) 1000{ 1001 DRM_DEBUG_KMS("Wait for panel power off time\n"); 1002 wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE); 1003} 1004 1005static void wait_panel_power_cycle(struct intel_dp *intel_dp) 1006{ 1007 DRM_DEBUG_KMS("Wait for panel power cycle\n"); 1008 1009 /* When we disable the VDD override bit last we have to do the manual 1010 * wait. */ 1011 wait_remaining_ms_from_jiffies(intel_dp->last_power_cycle, 1012 intel_dp->panel_power_cycle_delay); 1013 1014 wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE); 1015} 1016 1017static void wait_backlight_on(struct intel_dp *intel_dp) 1018{ 1019 wait_remaining_ms_from_jiffies(intel_dp->last_power_on, 1020 intel_dp->backlight_on_delay); 1021} 1022 1023static void edp_wait_backlight_off(struct intel_dp *intel_dp) 1024{ 1025 wait_remaining_ms_from_jiffies(intel_dp->last_backlight_off, 1026 intel_dp->backlight_off_delay); 1027} 1028 1029/* Read the current pp_control value, unlocking the register if it 1030 * is locked 1031 */ 1032 1033static u32 ironlake_get_pp_control(struct intel_dp *intel_dp) 1034{ 1035 struct drm_device *dev = intel_dp_to_dev(intel_dp); 1036 struct drm_i915_private *dev_priv = dev->dev_private; 1037 u32 control; 1038 1039 control = I915_READ(_pp_ctrl_reg(intel_dp)); 1040 control &= ~PANEL_UNLOCK_MASK; 1041 control |= PANEL_UNLOCK_REGS; 1042 return control; 1043} 1044 1045static bool _edp_panel_vdd_on(struct intel_dp *intel_dp) 1046{ 1047 struct drm_device *dev = intel_dp_to_dev(intel_dp); 1048 struct drm_i915_private *dev_priv = dev->dev_private; 1049 u32 pp; 1050 u32 pp_stat_reg, pp_ctrl_reg; 1051 bool need_to_disable = !intel_dp->want_panel_vdd; 1052 1053 if (!is_edp(intel_dp)) 1054 return false; 1055 1056 intel_dp->want_panel_vdd = true; 1057 1058 if (edp_have_panel_vdd(intel_dp)) 1059 return need_to_disable; 1060 1061 intel_runtime_pm_get(dev_priv); 1062 1063 DRM_DEBUG_KMS("Turning eDP VDD on\n"); 1064 1065 if (!edp_have_panel_power(intel_dp)) 1066 wait_panel_power_cycle(intel_dp); 1067 1068 pp = ironlake_get_pp_control(intel_dp); 1069 pp |= EDP_FORCE_VDD; 1070 1071 pp_stat_reg = _pp_stat_reg(intel_dp); 1072 pp_ctrl_reg = _pp_ctrl_reg(intel_dp); 1073 1074 I915_WRITE(pp_ctrl_reg, pp); 1075 POSTING_READ(pp_ctrl_reg); 1076 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n", 1077 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg)); 1078 /* 1079 * If the panel wasn't on, delay before accessing aux channel 1080 */ 1081 if (!edp_have_panel_power(intel_dp)) { 1082 DRM_DEBUG_KMS("eDP was not running\n"); 1083 msleep(intel_dp->panel_power_up_delay); 1084 } 1085 1086 return need_to_disable; 1087} 1088 1089void intel_edp_panel_vdd_on(struct intel_dp *intel_dp) 1090{ 1091 if (is_edp(intel_dp)) { 1092 bool vdd = _edp_panel_vdd_on(intel_dp); 1093 1094 WARN(!vdd, "eDP VDD already requested on\n"); 1095 } 1096} 1097 1098static void edp_panel_vdd_off_sync(struct intel_dp *intel_dp) 1099{ 1100 struct drm_device *dev = intel_dp_to_dev(intel_dp); 1101 struct drm_i915_private *dev_priv = dev->dev_private; 1102 u32 pp; 1103 u32 pp_stat_reg, pp_ctrl_reg; 1104 1105 WARN_ON(!mutex_is_locked(&dev->mode_config.mutex)); 1106 1107 if (!intel_dp->want_panel_vdd && edp_have_panel_vdd(intel_dp)) { 1108 DRM_DEBUG_KMS("Turning eDP VDD off\n"); 1109 1110 pp = ironlake_get_pp_control(intel_dp); 1111 pp &= ~EDP_FORCE_VDD; 1112 1113 pp_ctrl_reg = _pp_ctrl_reg(intel_dp); 1114 pp_stat_reg = _pp_stat_reg(intel_dp); 1115 1116 I915_WRITE(pp_ctrl_reg, pp); 1117 POSTING_READ(pp_ctrl_reg); 1118 1119 /* Make sure sequencer is idle before allowing subsequent activity */ 1120 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n", 1121 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg)); 1122 1123 if ((pp & POWER_TARGET_ON) == 0) 1124 intel_dp->last_power_cycle = jiffies; 1125 1126 intel_runtime_pm_put(dev_priv); 1127 } 1128} 1129 1130static void edp_panel_vdd_work(struct work_struct *__work) 1131{ 1132 struct intel_dp *intel_dp = container_of(to_delayed_work(__work), 1133 struct intel_dp, panel_vdd_work); 1134 struct drm_device *dev = intel_dp_to_dev(intel_dp); 1135 1136 mutex_lock(&dev->mode_config.mutex); 1137 edp_panel_vdd_off_sync(intel_dp); 1138 mutex_unlock(&dev->mode_config.mutex); 1139} 1140 1141static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync) 1142{ 1143 if (!is_edp(intel_dp)) 1144 return; 1145 1146 WARN(!intel_dp->want_panel_vdd, "eDP VDD not forced on"); 1147 1148 intel_dp->want_panel_vdd = false; 1149 1150 if (sync) { 1151 edp_panel_vdd_off_sync(intel_dp); 1152 } else { 1153 /* 1154 * Queue the timer to fire a long 1155 * time from now (relative to the power down delay) 1156 * to keep the panel power up across a sequence of operations 1157 */ 1158 schedule_delayed_work(&intel_dp->panel_vdd_work, 1159 msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5)); 1160 } 1161} 1162 1163void intel_edp_panel_on(struct intel_dp *intel_dp) 1164{ 1165 struct drm_device *dev = intel_dp_to_dev(intel_dp); 1166 struct drm_i915_private *dev_priv = dev->dev_private; 1167 u32 pp; 1168 u32 pp_ctrl_reg; 1169 1170 if (!is_edp(intel_dp)) 1171 return; 1172 1173 DRM_DEBUG_KMS("Turn eDP power on\n"); 1174 1175 if (edp_have_panel_power(intel_dp)) { 1176 DRM_DEBUG_KMS("eDP power already on\n"); 1177 return; 1178 } 1179 1180 wait_panel_power_cycle(intel_dp); 1181 1182 pp_ctrl_reg = _pp_ctrl_reg(intel_dp); 1183 pp = ironlake_get_pp_control(intel_dp); 1184 if (IS_GEN5(dev)) { 1185 /* ILK workaround: disable reset around power sequence */ 1186 pp &= ~PANEL_POWER_RESET; 1187 I915_WRITE(pp_ctrl_reg, pp); 1188 POSTING_READ(pp_ctrl_reg); 1189 } 1190 1191 pp |= POWER_TARGET_ON; 1192 if (!IS_GEN5(dev)) 1193 pp |= PANEL_POWER_RESET; 1194 1195 I915_WRITE(pp_ctrl_reg, pp); 1196 POSTING_READ(pp_ctrl_reg); 1197 1198 wait_panel_on(intel_dp); 1199 intel_dp->last_power_on = jiffies; 1200 1201 if (IS_GEN5(dev)) { 1202 pp |= PANEL_POWER_RESET; /* restore panel reset bit */ 1203 I915_WRITE(pp_ctrl_reg, pp); 1204 POSTING_READ(pp_ctrl_reg); 1205 } 1206} 1207 1208void intel_edp_panel_off(struct intel_dp *intel_dp) 1209{ 1210 struct drm_device *dev = intel_dp_to_dev(intel_dp); 1211 struct drm_i915_private *dev_priv = dev->dev_private; 1212 u32 pp; 1213 u32 pp_ctrl_reg; 1214 1215 if (!is_edp(intel_dp)) 1216 return; 1217 1218 DRM_DEBUG_KMS("Turn eDP power off\n"); 1219 1220 edp_wait_backlight_off(intel_dp); 1221 1222 WARN(!intel_dp->want_panel_vdd, "Need VDD to turn off panel\n"); 1223 1224 pp = ironlake_get_pp_control(intel_dp); 1225 /* We need to switch off panel power _and_ force vdd, for otherwise some 1226 * panels get very unhappy and cease to work. */ 1227 pp &= ~(POWER_TARGET_ON | PANEL_POWER_RESET | EDP_FORCE_VDD | 1228 EDP_BLC_ENABLE); 1229 1230 pp_ctrl_reg = _pp_ctrl_reg(intel_dp); 1231 1232 intel_dp->want_panel_vdd = false; 1233 1234 I915_WRITE(pp_ctrl_reg, pp); 1235 POSTING_READ(pp_ctrl_reg); 1236 1237 intel_dp->last_power_cycle = jiffies; 1238 wait_panel_off(intel_dp); 1239 1240 /* We got a reference when we enabled the VDD. */ 1241 intel_runtime_pm_put(dev_priv); 1242} 1243 1244void intel_edp_backlight_on(struct intel_dp *intel_dp) 1245{ 1246 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 1247 struct drm_device *dev = intel_dig_port->base.base.dev; 1248 struct drm_i915_private *dev_priv = dev->dev_private; 1249 u32 pp; 1250 u32 pp_ctrl_reg; 1251 1252 if (!is_edp(intel_dp)) 1253 return; 1254 1255 DRM_DEBUG_KMS("\n"); 1256 /* 1257 * If we enable the backlight right away following a panel power 1258 * on, we may see slight flicker as the panel syncs with the eDP 1259 * link. So delay a bit to make sure the image is solid before 1260 * allowing it to appear. 1261 */ 1262 wait_backlight_on(intel_dp); 1263 pp = ironlake_get_pp_control(intel_dp); 1264 pp |= EDP_BLC_ENABLE; 1265 1266 pp_ctrl_reg = _pp_ctrl_reg(intel_dp); 1267 1268 I915_WRITE(pp_ctrl_reg, pp); 1269 POSTING_READ(pp_ctrl_reg); 1270 1271 intel_panel_enable_backlight(intel_dp->attached_connector); 1272} 1273 1274void intel_edp_backlight_off(struct intel_dp *intel_dp) 1275{ 1276 struct drm_device *dev = intel_dp_to_dev(intel_dp); 1277 struct drm_i915_private *dev_priv = dev->dev_private; 1278 u32 pp; 1279 u32 pp_ctrl_reg; 1280 1281 if (!is_edp(intel_dp)) 1282 return; 1283 1284 intel_panel_disable_backlight(intel_dp->attached_connector); 1285 1286 DRM_DEBUG_KMS("\n"); 1287 pp = ironlake_get_pp_control(intel_dp); 1288 pp &= ~EDP_BLC_ENABLE; 1289 1290 pp_ctrl_reg = _pp_ctrl_reg(intel_dp); 1291 1292 I915_WRITE(pp_ctrl_reg, pp); 1293 POSTING_READ(pp_ctrl_reg); 1294 intel_dp->last_backlight_off = jiffies; 1295} 1296 1297static void ironlake_edp_pll_on(struct intel_dp *intel_dp) 1298{ 1299 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 1300 struct drm_crtc *crtc = intel_dig_port->base.base.crtc; 1301 struct drm_device *dev = crtc->dev; 1302 struct drm_i915_private *dev_priv = dev->dev_private; 1303 u32 dpa_ctl; 1304 1305 assert_pipe_disabled(dev_priv, 1306 to_intel_crtc(crtc)->pipe); 1307 1308 DRM_DEBUG_KMS("\n"); 1309 dpa_ctl = I915_READ(DP_A); 1310 WARN(dpa_ctl & DP_PLL_ENABLE, "dp pll on, should be off\n"); 1311 WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n"); 1312 1313 /* We don't adjust intel_dp->DP while tearing down the link, to 1314 * facilitate link retraining (e.g. after hotplug). Hence clear all 1315 * enable bits here to ensure that we don't enable too much. */ 1316 intel_dp->DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE); 1317 intel_dp->DP |= DP_PLL_ENABLE; 1318 I915_WRITE(DP_A, intel_dp->DP); 1319 POSTING_READ(DP_A); 1320 udelay(200); 1321} 1322 1323static void ironlake_edp_pll_off(struct intel_dp *intel_dp) 1324{ 1325 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 1326 struct drm_crtc *crtc = intel_dig_port->base.base.crtc; 1327 struct drm_device *dev = crtc->dev; 1328 struct drm_i915_private *dev_priv = dev->dev_private; 1329 u32 dpa_ctl; 1330 1331 assert_pipe_disabled(dev_priv, 1332 to_intel_crtc(crtc)->pipe); 1333 1334 dpa_ctl = I915_READ(DP_A); 1335 WARN((dpa_ctl & DP_PLL_ENABLE) == 0, 1336 "dp pll off, should be on\n"); 1337 WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n"); 1338 1339 /* We can't rely on the value tracked for the DP register in 1340 * intel_dp->DP because link_down must not change that (otherwise link 1341 * re-training will fail. */ 1342 dpa_ctl &= ~DP_PLL_ENABLE; 1343 I915_WRITE(DP_A, dpa_ctl); 1344 POSTING_READ(DP_A); 1345 udelay(200); 1346} 1347 1348/* If the sink supports it, try to set the power state appropriately */ 1349void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode) 1350{ 1351 int ret, i; 1352 1353 /* Should have a valid DPCD by this point */ 1354 if (intel_dp->dpcd[DP_DPCD_REV] < 0x11) 1355 return; 1356 1357 if (mode != DRM_MODE_DPMS_ON) { 1358 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER, 1359 DP_SET_POWER_D3); 1360 if (ret != 1) 1361 DRM_DEBUG_DRIVER("failed to write sink power state\n"); 1362 } else { 1363 /* 1364 * When turning on, we need to retry for 1ms to give the sink 1365 * time to wake up. 1366 */ 1367 for (i = 0; i < 3; i++) { 1368 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER, 1369 DP_SET_POWER_D0); 1370 if (ret == 1) 1371 break; 1372 msleep(1); 1373 } 1374 } 1375} 1376 1377static bool intel_dp_get_hw_state(struct intel_encoder *encoder, 1378 enum pipe *pipe) 1379{ 1380 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); 1381 enum port port = dp_to_dig_port(intel_dp)->port; 1382 struct drm_device *dev = encoder->base.dev; 1383 struct drm_i915_private *dev_priv = dev->dev_private; 1384 enum intel_display_power_domain power_domain; 1385 u32 tmp; 1386 1387 power_domain = intel_display_port_power_domain(encoder); 1388 if (!intel_display_power_enabled(dev_priv, power_domain)) 1389 return false; 1390 1391 tmp = I915_READ(intel_dp->output_reg); 1392 1393 if (!(tmp & DP_PORT_EN)) 1394 return false; 1395 1396 if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) { 1397 *pipe = PORT_TO_PIPE_CPT(tmp); 1398 } else if (!HAS_PCH_CPT(dev) || port == PORT_A) { 1399 *pipe = PORT_TO_PIPE(tmp); 1400 } else { 1401 u32 trans_sel; 1402 u32 trans_dp; 1403 int i; 1404 1405 switch (intel_dp->output_reg) { 1406 case PCH_DP_B: 1407 trans_sel = TRANS_DP_PORT_SEL_B; 1408 break; 1409 case PCH_DP_C: 1410 trans_sel = TRANS_DP_PORT_SEL_C; 1411 break; 1412 case PCH_DP_D: 1413 trans_sel = TRANS_DP_PORT_SEL_D; 1414 break; 1415 default: 1416 return true; 1417 } 1418 1419 for_each_pipe(i) { 1420 trans_dp = I915_READ(TRANS_DP_CTL(i)); 1421 if ((trans_dp & TRANS_DP_PORT_SEL_MASK) == trans_sel) { 1422 *pipe = i; 1423 return true; 1424 } 1425 } 1426 1427 DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n", 1428 intel_dp->output_reg); 1429 } 1430 1431 return true; 1432} 1433 1434static void intel_dp_get_config(struct intel_encoder *encoder, 1435 struct intel_crtc_config *pipe_config) 1436{ 1437 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); 1438 u32 tmp, flags = 0; 1439 struct drm_device *dev = encoder->base.dev; 1440 struct drm_i915_private *dev_priv = dev->dev_private; 1441 enum port port = dp_to_dig_port(intel_dp)->port; 1442 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); 1443 int dotclock; 1444 1445 if ((port == PORT_A) || !HAS_PCH_CPT(dev)) { 1446 tmp = I915_READ(intel_dp->output_reg); 1447 if (tmp & DP_SYNC_HS_HIGH) 1448 flags |= DRM_MODE_FLAG_PHSYNC; 1449 else 1450 flags |= DRM_MODE_FLAG_NHSYNC; 1451 1452 if (tmp & DP_SYNC_VS_HIGH) 1453 flags |= DRM_MODE_FLAG_PVSYNC; 1454 else 1455 flags |= DRM_MODE_FLAG_NVSYNC; 1456 } else { 1457 tmp = I915_READ(TRANS_DP_CTL(crtc->pipe)); 1458 if (tmp & TRANS_DP_HSYNC_ACTIVE_HIGH) 1459 flags |= DRM_MODE_FLAG_PHSYNC; 1460 else 1461 flags |= DRM_MODE_FLAG_NHSYNC; 1462 1463 if (tmp & TRANS_DP_VSYNC_ACTIVE_HIGH) 1464 flags |= DRM_MODE_FLAG_PVSYNC; 1465 else 1466 flags |= DRM_MODE_FLAG_NVSYNC; 1467 } 1468 1469 pipe_config->adjusted_mode.flags |= flags; 1470 1471 pipe_config->has_dp_encoder = true; 1472 1473 intel_dp_get_m_n(crtc, pipe_config); 1474 1475 if (port == PORT_A) { 1476 if ((I915_READ(DP_A) & DP_PLL_FREQ_MASK) == DP_PLL_FREQ_160MHZ) 1477 pipe_config->port_clock = 162000; 1478 else 1479 pipe_config->port_clock = 270000; 1480 } 1481 1482 dotclock = intel_dotclock_calculate(pipe_config->port_clock, 1483 &pipe_config->dp_m_n); 1484 1485 if (HAS_PCH_SPLIT(dev_priv->dev) && port != PORT_A) 1486 ironlake_check_encoder_dotclock(pipe_config, dotclock); 1487 1488 pipe_config->adjusted_mode.crtc_clock = dotclock; 1489 1490 if (is_edp(intel_dp) && dev_priv->vbt.edp_bpp && 1491 pipe_config->pipe_bpp > dev_priv->vbt.edp_bpp) { 1492 /* 1493 * This is a big fat ugly hack. 1494 * 1495 * Some machines in UEFI boot mode provide us a VBT that has 18 1496 * bpp and 1.62 GHz link bandwidth for eDP, which for reasons 1497 * unknown we fail to light up. Yet the same BIOS boots up with 1498 * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as 1499 * max, not what it tells us to use. 1500 * 1501 * Note: This will still be broken if the eDP panel is not lit 1502 * up by the BIOS, and thus we can't get the mode at module 1503 * load. 1504 */ 1505 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n", 1506 pipe_config->pipe_bpp, dev_priv->vbt.edp_bpp); 1507 dev_priv->vbt.edp_bpp = pipe_config->pipe_bpp; 1508 } 1509} 1510 1511static bool is_edp_psr(struct drm_device *dev) 1512{ 1513 struct drm_i915_private *dev_priv = dev->dev_private; 1514 1515 return dev_priv->psr.sink_support; 1516} 1517 1518static bool intel_edp_is_psr_enabled(struct drm_device *dev) 1519{ 1520 struct drm_i915_private *dev_priv = dev->dev_private; 1521 1522 if (!HAS_PSR(dev)) 1523 return false; 1524 1525 return I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE; 1526} 1527 1528static void intel_edp_psr_write_vsc(struct intel_dp *intel_dp, 1529 struct edp_vsc_psr *vsc_psr) 1530{ 1531 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 1532 struct drm_device *dev = dig_port->base.base.dev; 1533 struct drm_i915_private *dev_priv = dev->dev_private; 1534 struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc); 1535 u32 ctl_reg = HSW_TVIDEO_DIP_CTL(crtc->config.cpu_transcoder); 1536 u32 data_reg = HSW_TVIDEO_DIP_VSC_DATA(crtc->config.cpu_transcoder); 1537 uint32_t *data = (uint32_t *) vsc_psr; 1538 unsigned int i; 1539 1540 /* As per BSPec (Pipe Video Data Island Packet), we need to disable 1541 the video DIP being updated before program video DIP data buffer 1542 registers for DIP being updated. */ 1543 I915_WRITE(ctl_reg, 0); 1544 POSTING_READ(ctl_reg); 1545 1546 for (i = 0; i < VIDEO_DIP_VSC_DATA_SIZE; i += 4) { 1547 if (i < sizeof(struct edp_vsc_psr)) 1548 I915_WRITE(data_reg + i, *data++); 1549 else 1550 I915_WRITE(data_reg + i, 0); 1551 } 1552 1553 I915_WRITE(ctl_reg, VIDEO_DIP_ENABLE_VSC_HSW); 1554 POSTING_READ(ctl_reg); 1555} 1556 1557static void intel_edp_psr_setup(struct intel_dp *intel_dp) 1558{ 1559 struct drm_device *dev = intel_dp_to_dev(intel_dp); 1560 struct drm_i915_private *dev_priv = dev->dev_private; 1561 struct edp_vsc_psr psr_vsc; 1562 1563 if (intel_dp->psr_setup_done) 1564 return; 1565 1566 /* Prepare VSC packet as per EDP 1.3 spec, Table 3.10 */ 1567 memset(&psr_vsc, 0, sizeof(psr_vsc)); 1568 psr_vsc.sdp_header.HB0 = 0; 1569 psr_vsc.sdp_header.HB1 = 0x7; 1570 psr_vsc.sdp_header.HB2 = 0x2; 1571 psr_vsc.sdp_header.HB3 = 0x8; 1572 intel_edp_psr_write_vsc(intel_dp, &psr_vsc); 1573 1574 /* Avoid continuous PSR exit by masking memup and hpd */ 1575 I915_WRITE(EDP_PSR_DEBUG_CTL(dev), EDP_PSR_DEBUG_MASK_MEMUP | 1576 EDP_PSR_DEBUG_MASK_HPD | EDP_PSR_DEBUG_MASK_LPSP); 1577 1578 intel_dp->psr_setup_done = true; 1579} 1580 1581static void intel_edp_psr_enable_sink(struct intel_dp *intel_dp) 1582{ 1583 struct drm_device *dev = intel_dp_to_dev(intel_dp); 1584 struct drm_i915_private *dev_priv = dev->dev_private; 1585 uint32_t aux_clock_divider; 1586 int precharge = 0x3; 1587 int msg_size = 5; /* Header(4) + Message(1) */ 1588 1589 aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, 0); 1590 1591 /* Enable PSR in sink */ 1592 if (intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT) 1593 drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG, 1594 DP_PSR_ENABLE & ~DP_PSR_MAIN_LINK_ACTIVE); 1595 else 1596 drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG, 1597 DP_PSR_ENABLE | DP_PSR_MAIN_LINK_ACTIVE); 1598 1599 /* Setup AUX registers */ 1600 I915_WRITE(EDP_PSR_AUX_DATA1(dev), EDP_PSR_DPCD_COMMAND); 1601 I915_WRITE(EDP_PSR_AUX_DATA2(dev), EDP_PSR_DPCD_NORMAL_OPERATION); 1602 I915_WRITE(EDP_PSR_AUX_CTL(dev), 1603 DP_AUX_CH_CTL_TIME_OUT_400us | 1604 (msg_size << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) | 1605 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) | 1606 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT)); 1607} 1608 1609static void intel_edp_psr_enable_source(struct intel_dp *intel_dp) 1610{ 1611 struct drm_device *dev = intel_dp_to_dev(intel_dp); 1612 struct drm_i915_private *dev_priv = dev->dev_private; 1613 uint32_t max_sleep_time = 0x1f; 1614 uint32_t idle_frames = 1; 1615 uint32_t val = 0x0; 1616 const uint32_t link_entry_time = EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES; 1617 1618 if (intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT) { 1619 val |= EDP_PSR_LINK_STANDBY; 1620 val |= EDP_PSR_TP2_TP3_TIME_0us; 1621 val |= EDP_PSR_TP1_TIME_0us; 1622 val |= EDP_PSR_SKIP_AUX_EXIT; 1623 } else 1624 val |= EDP_PSR_LINK_DISABLE; 1625 1626 I915_WRITE(EDP_PSR_CTL(dev), val | 1627 (IS_BROADWELL(dev) ? 0 : link_entry_time) | 1628 max_sleep_time << EDP_PSR_MAX_SLEEP_TIME_SHIFT | 1629 idle_frames << EDP_PSR_IDLE_FRAME_SHIFT | 1630 EDP_PSR_ENABLE); 1631} 1632 1633static bool intel_edp_psr_match_conditions(struct intel_dp *intel_dp) 1634{ 1635 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 1636 struct drm_device *dev = dig_port->base.base.dev; 1637 struct drm_i915_private *dev_priv = dev->dev_private; 1638 struct drm_crtc *crtc = dig_port->base.base.crtc; 1639 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 1640 struct drm_i915_gem_object *obj = to_intel_framebuffer(crtc->primary->fb)->obj; 1641 struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base; 1642 1643 dev_priv->psr.source_ok = false; 1644 1645 if (!HAS_PSR(dev)) { 1646 DRM_DEBUG_KMS("PSR not supported on this platform\n"); 1647 return false; 1648 } 1649 1650 if ((intel_encoder->type != INTEL_OUTPUT_EDP) || 1651 (dig_port->port != PORT_A)) { 1652 DRM_DEBUG_KMS("HSW ties PSR to DDI A (eDP)\n"); 1653 return false; 1654 } 1655 1656 if (!i915.enable_psr) { 1657 DRM_DEBUG_KMS("PSR disable by flag\n"); 1658 return false; 1659 } 1660 1661 crtc = dig_port->base.base.crtc; 1662 if (crtc == NULL) { 1663 DRM_DEBUG_KMS("crtc not active for PSR\n"); 1664 return false; 1665 } 1666 1667 intel_crtc = to_intel_crtc(crtc); 1668 if (!intel_crtc_active(crtc)) { 1669 DRM_DEBUG_KMS("crtc not active for PSR\n"); 1670 return false; 1671 } 1672 1673 obj = to_intel_framebuffer(crtc->primary->fb)->obj; 1674 if (obj->tiling_mode != I915_TILING_X || 1675 obj->fence_reg == I915_FENCE_REG_NONE) { 1676 DRM_DEBUG_KMS("PSR condition failed: fb not tiled or fenced\n"); 1677 return false; 1678 } 1679 1680 if (I915_READ(SPRCTL(intel_crtc->pipe)) & SPRITE_ENABLE) { 1681 DRM_DEBUG_KMS("PSR condition failed: Sprite is Enabled\n"); 1682 return false; 1683 } 1684 1685 if (I915_READ(HSW_STEREO_3D_CTL(intel_crtc->config.cpu_transcoder)) & 1686 S3D_ENABLE) { 1687 DRM_DEBUG_KMS("PSR condition failed: Stereo 3D is Enabled\n"); 1688 return false; 1689 } 1690 1691 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) { 1692 DRM_DEBUG_KMS("PSR condition failed: Interlaced is Enabled\n"); 1693 return false; 1694 } 1695 1696 dev_priv->psr.source_ok = true; 1697 return true; 1698} 1699 1700static void intel_edp_psr_do_enable(struct intel_dp *intel_dp) 1701{ 1702 struct drm_device *dev = intel_dp_to_dev(intel_dp); 1703 1704 if (!intel_edp_psr_match_conditions(intel_dp) || 1705 intel_edp_is_psr_enabled(dev)) 1706 return; 1707 1708 /* Setup PSR once */ 1709 intel_edp_psr_setup(intel_dp); 1710 1711 /* Enable PSR on the panel */ 1712 intel_edp_psr_enable_sink(intel_dp); 1713 1714 /* Enable PSR on the host */ 1715 intel_edp_psr_enable_source(intel_dp); 1716} 1717 1718void intel_edp_psr_enable(struct intel_dp *intel_dp) 1719{ 1720 struct drm_device *dev = intel_dp_to_dev(intel_dp); 1721 1722 if (intel_edp_psr_match_conditions(intel_dp) && 1723 !intel_edp_is_psr_enabled(dev)) 1724 intel_edp_psr_do_enable(intel_dp); 1725} 1726 1727void intel_edp_psr_disable(struct intel_dp *intel_dp) 1728{ 1729 struct drm_device *dev = intel_dp_to_dev(intel_dp); 1730 struct drm_i915_private *dev_priv = dev->dev_private; 1731 1732 if (!intel_edp_is_psr_enabled(dev)) 1733 return; 1734 1735 I915_WRITE(EDP_PSR_CTL(dev), 1736 I915_READ(EDP_PSR_CTL(dev)) & ~EDP_PSR_ENABLE); 1737 1738 /* Wait till PSR is idle */ 1739 if (_wait_for((I915_READ(EDP_PSR_STATUS_CTL(dev)) & 1740 EDP_PSR_STATUS_STATE_MASK) == 0, 2000, 10)) 1741 DRM_ERROR("Timed out waiting for PSR Idle State\n"); 1742} 1743 1744void intel_edp_psr_update(struct drm_device *dev) 1745{ 1746 struct intel_encoder *encoder; 1747 struct intel_dp *intel_dp = NULL; 1748 1749 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) 1750 if (encoder->type == INTEL_OUTPUT_EDP) { 1751 intel_dp = enc_to_intel_dp(&encoder->base); 1752 1753 if (!is_edp_psr(dev)) 1754 return; 1755 1756 if (!intel_edp_psr_match_conditions(intel_dp)) 1757 intel_edp_psr_disable(intel_dp); 1758 else 1759 if (!intel_edp_is_psr_enabled(dev)) 1760 intel_edp_psr_do_enable(intel_dp); 1761 } 1762} 1763 1764static void intel_disable_dp(struct intel_encoder *encoder) 1765{ 1766 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); 1767 enum port port = dp_to_dig_port(intel_dp)->port; 1768 struct drm_device *dev = encoder->base.dev; 1769 1770 /* Make sure the panel is off before trying to change the mode. But also 1771 * ensure that we have vdd while we switch off the panel. */ 1772 intel_edp_panel_vdd_on(intel_dp); 1773 intel_edp_backlight_off(intel_dp); 1774 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF); 1775 intel_edp_panel_off(intel_dp); 1776 1777 /* cpu edp my only be disable _after_ the cpu pipe/plane is disabled. */ 1778 if (!(port == PORT_A || IS_VALLEYVIEW(dev))) 1779 intel_dp_link_down(intel_dp); 1780} 1781 1782static void intel_post_disable_dp(struct intel_encoder *encoder) 1783{ 1784 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); 1785 enum port port = dp_to_dig_port(intel_dp)->port; 1786 struct drm_device *dev = encoder->base.dev; 1787 1788 if (port == PORT_A || IS_VALLEYVIEW(dev)) { 1789 intel_dp_link_down(intel_dp); 1790 if (!IS_VALLEYVIEW(dev)) 1791 ironlake_edp_pll_off(intel_dp); 1792 } 1793} 1794 1795static void intel_enable_dp(struct intel_encoder *encoder) 1796{ 1797 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); 1798 struct drm_device *dev = encoder->base.dev; 1799 struct drm_i915_private *dev_priv = dev->dev_private; 1800 uint32_t dp_reg = I915_READ(intel_dp->output_reg); 1801 1802 if (WARN_ON(dp_reg & DP_PORT_EN)) 1803 return; 1804 1805 intel_edp_panel_vdd_on(intel_dp); 1806 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON); 1807 intel_dp_start_link_train(intel_dp); 1808 intel_edp_panel_on(intel_dp); 1809 edp_panel_vdd_off(intel_dp, true); 1810 intel_dp_complete_link_train(intel_dp); 1811 intel_dp_stop_link_train(intel_dp); 1812} 1813 1814static void g4x_enable_dp(struct intel_encoder *encoder) 1815{ 1816 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); 1817 1818 intel_enable_dp(encoder); 1819 intel_edp_backlight_on(intel_dp); 1820} 1821 1822static void vlv_enable_dp(struct intel_encoder *encoder) 1823{ 1824 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); 1825 1826 intel_edp_backlight_on(intel_dp); 1827} 1828 1829static void g4x_pre_enable_dp(struct intel_encoder *encoder) 1830{ 1831 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); 1832 struct intel_digital_port *dport = dp_to_dig_port(intel_dp); 1833 1834 if (dport->port == PORT_A) 1835 ironlake_edp_pll_on(intel_dp); 1836} 1837 1838static void vlv_pre_enable_dp(struct intel_encoder *encoder) 1839{ 1840 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); 1841 struct intel_digital_port *dport = dp_to_dig_port(intel_dp); 1842 struct drm_device *dev = encoder->base.dev; 1843 struct drm_i915_private *dev_priv = dev->dev_private; 1844 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc); 1845 enum dpio_channel port = vlv_dport_to_channel(dport); 1846 int pipe = intel_crtc->pipe; 1847 struct edp_power_seq power_seq; 1848 u32 val; 1849 1850 mutex_lock(&dev_priv->dpio_lock); 1851 1852 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(port)); 1853 val = 0; 1854 if (pipe) 1855 val |= (1<<21); 1856 else 1857 val &= ~(1<<21); 1858 val |= 0x001000c4; 1859 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW8(port), val); 1860 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW14(port), 0x00760018); 1861 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW23(port), 0x00400888); 1862 1863 mutex_unlock(&dev_priv->dpio_lock); 1864 1865 if (is_edp(intel_dp)) { 1866 /* init power sequencer on this pipe and port */ 1867 intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq); 1868 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp, 1869 &power_seq); 1870 } 1871 1872 intel_enable_dp(encoder); 1873 1874 vlv_wait_port_ready(dev_priv, dport); 1875} 1876 1877static void vlv_dp_pre_pll_enable(struct intel_encoder *encoder) 1878{ 1879 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base); 1880 struct drm_device *dev = encoder->base.dev; 1881 struct drm_i915_private *dev_priv = dev->dev_private; 1882 struct intel_crtc *intel_crtc = 1883 to_intel_crtc(encoder->base.crtc); 1884 enum dpio_channel port = vlv_dport_to_channel(dport); 1885 int pipe = intel_crtc->pipe; 1886 1887 /* Program Tx lane resets to default */ 1888 mutex_lock(&dev_priv->dpio_lock); 1889 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port), 1890 DPIO_PCS_TX_LANE2_RESET | 1891 DPIO_PCS_TX_LANE1_RESET); 1892 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port), 1893 DPIO_PCS_CLK_CRI_RXEB_EIOS_EN | 1894 DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN | 1895 (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT) | 1896 DPIO_PCS_CLK_SOFT_RESET); 1897 1898 /* Fix up inter-pair skew failure */ 1899 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW12(port), 0x00750f00); 1900 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW11(port), 0x00001500); 1901 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW14(port), 0x40400000); 1902 mutex_unlock(&dev_priv->dpio_lock); 1903} 1904 1905/* 1906 * Native read with retry for link status and receiver capability reads for 1907 * cases where the sink may still be asleep. 1908 * 1909 * Sinks are *supposed* to come up within 1ms from an off state, but we're also 1910 * supposed to retry 3 times per the spec. 1911 */ 1912static ssize_t 1913intel_dp_dpcd_read_wake(struct drm_dp_aux *aux, unsigned int offset, 1914 void *buffer, size_t size) 1915{ 1916 ssize_t ret; 1917 int i; 1918 1919 for (i = 0; i < 3; i++) { 1920 ret = drm_dp_dpcd_read(aux, offset, buffer, size); 1921 if (ret == size) 1922 return ret; 1923 msleep(1); 1924 } 1925 1926 return ret; 1927} 1928 1929/* 1930 * Fetch AUX CH registers 0x202 - 0x207 which contain 1931 * link status information 1932 */ 1933static bool 1934intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE]) 1935{ 1936 return intel_dp_dpcd_read_wake(&intel_dp->aux, 1937 DP_LANE0_1_STATUS, 1938 link_status, 1939 DP_LINK_STATUS_SIZE) == DP_LINK_STATUS_SIZE; 1940} 1941 1942/* 1943 * These are source-specific values; current Intel hardware supports 1944 * a maximum voltage of 800mV and a maximum pre-emphasis of 6dB 1945 */ 1946 1947static uint8_t 1948intel_dp_voltage_max(struct intel_dp *intel_dp) 1949{ 1950 struct drm_device *dev = intel_dp_to_dev(intel_dp); 1951 enum port port = dp_to_dig_port(intel_dp)->port; 1952 1953 if (IS_VALLEYVIEW(dev) || IS_BROADWELL(dev)) 1954 return DP_TRAIN_VOLTAGE_SWING_1200; 1955 else if (IS_GEN7(dev) && port == PORT_A) 1956 return DP_TRAIN_VOLTAGE_SWING_800; 1957 else if (HAS_PCH_CPT(dev) && port != PORT_A) 1958 return DP_TRAIN_VOLTAGE_SWING_1200; 1959 else 1960 return DP_TRAIN_VOLTAGE_SWING_800; 1961} 1962 1963static uint8_t 1964intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing) 1965{ 1966 struct drm_device *dev = intel_dp_to_dev(intel_dp); 1967 enum port port = dp_to_dig_port(intel_dp)->port; 1968 1969 if (IS_BROADWELL(dev)) { 1970 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) { 1971 case DP_TRAIN_VOLTAGE_SWING_400: 1972 case DP_TRAIN_VOLTAGE_SWING_600: 1973 return DP_TRAIN_PRE_EMPHASIS_6; 1974 case DP_TRAIN_VOLTAGE_SWING_800: 1975 return DP_TRAIN_PRE_EMPHASIS_3_5; 1976 case DP_TRAIN_VOLTAGE_SWING_1200: 1977 default: 1978 return DP_TRAIN_PRE_EMPHASIS_0; 1979 } 1980 } else if (IS_HASWELL(dev)) { 1981 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) { 1982 case DP_TRAIN_VOLTAGE_SWING_400: 1983 return DP_TRAIN_PRE_EMPHASIS_9_5; 1984 case DP_TRAIN_VOLTAGE_SWING_600: 1985 return DP_TRAIN_PRE_EMPHASIS_6; 1986 case DP_TRAIN_VOLTAGE_SWING_800: 1987 return DP_TRAIN_PRE_EMPHASIS_3_5; 1988 case DP_TRAIN_VOLTAGE_SWING_1200: 1989 default: 1990 return DP_TRAIN_PRE_EMPHASIS_0; 1991 } 1992 } else if (IS_VALLEYVIEW(dev)) { 1993 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) { 1994 case DP_TRAIN_VOLTAGE_SWING_400: 1995 return DP_TRAIN_PRE_EMPHASIS_9_5; 1996 case DP_TRAIN_VOLTAGE_SWING_600: 1997 return DP_TRAIN_PRE_EMPHASIS_6; 1998 case DP_TRAIN_VOLTAGE_SWING_800: 1999 return DP_TRAIN_PRE_EMPHASIS_3_5; 2000 case DP_TRAIN_VOLTAGE_SWING_1200: 2001 default: 2002 return DP_TRAIN_PRE_EMPHASIS_0; 2003 } 2004 } else if (IS_GEN7(dev) && port == PORT_A) { 2005 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) { 2006 case DP_TRAIN_VOLTAGE_SWING_400: 2007 return DP_TRAIN_PRE_EMPHASIS_6; 2008 case DP_TRAIN_VOLTAGE_SWING_600: 2009 case DP_TRAIN_VOLTAGE_SWING_800: 2010 return DP_TRAIN_PRE_EMPHASIS_3_5; 2011 default: 2012 return DP_TRAIN_PRE_EMPHASIS_0; 2013 } 2014 } else { 2015 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) { 2016 case DP_TRAIN_VOLTAGE_SWING_400: 2017 return DP_TRAIN_PRE_EMPHASIS_6; 2018 case DP_TRAIN_VOLTAGE_SWING_600: 2019 return DP_TRAIN_PRE_EMPHASIS_6; 2020 case DP_TRAIN_VOLTAGE_SWING_800: 2021 return DP_TRAIN_PRE_EMPHASIS_3_5; 2022 case DP_TRAIN_VOLTAGE_SWING_1200: 2023 default: 2024 return DP_TRAIN_PRE_EMPHASIS_0; 2025 } 2026 } 2027} 2028 2029static uint32_t intel_vlv_signal_levels(struct intel_dp *intel_dp) 2030{ 2031 struct drm_device *dev = intel_dp_to_dev(intel_dp); 2032 struct drm_i915_private *dev_priv = dev->dev_private; 2033 struct intel_digital_port *dport = dp_to_dig_port(intel_dp); 2034 struct intel_crtc *intel_crtc = 2035 to_intel_crtc(dport->base.base.crtc); 2036 unsigned long demph_reg_value, preemph_reg_value, 2037 uniqtranscale_reg_value; 2038 uint8_t train_set = intel_dp->train_set[0]; 2039 enum dpio_channel port = vlv_dport_to_channel(dport); 2040 int pipe = intel_crtc->pipe; 2041 2042 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) { 2043 case DP_TRAIN_PRE_EMPHASIS_0: 2044 preemph_reg_value = 0x0004000; 2045 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { 2046 case DP_TRAIN_VOLTAGE_SWING_400: 2047 demph_reg_value = 0x2B405555; 2048 uniqtranscale_reg_value = 0x552AB83A; 2049 break; 2050 case DP_TRAIN_VOLTAGE_SWING_600: 2051 demph_reg_value = 0x2B404040; 2052 uniqtranscale_reg_value = 0x5548B83A; 2053 break; 2054 case DP_TRAIN_VOLTAGE_SWING_800: 2055 demph_reg_value = 0x2B245555; 2056 uniqtranscale_reg_value = 0x5560B83A; 2057 break; 2058 case DP_TRAIN_VOLTAGE_SWING_1200: 2059 demph_reg_value = 0x2B405555; 2060 uniqtranscale_reg_value = 0x5598DA3A; 2061 break; 2062 default: 2063 return 0; 2064 } 2065 break; 2066 case DP_TRAIN_PRE_EMPHASIS_3_5: 2067 preemph_reg_value = 0x0002000; 2068 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { 2069 case DP_TRAIN_VOLTAGE_SWING_400: 2070 demph_reg_value = 0x2B404040; 2071 uniqtranscale_reg_value = 0x5552B83A; 2072 break; 2073 case DP_TRAIN_VOLTAGE_SWING_600: 2074 demph_reg_value = 0x2B404848; 2075 uniqtranscale_reg_value = 0x5580B83A; 2076 break; 2077 case DP_TRAIN_VOLTAGE_SWING_800: 2078 demph_reg_value = 0x2B404040; 2079 uniqtranscale_reg_value = 0x55ADDA3A; 2080 break; 2081 default: 2082 return 0; 2083 } 2084 break; 2085 case DP_TRAIN_PRE_EMPHASIS_6: 2086 preemph_reg_value = 0x0000000; 2087 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { 2088 case DP_TRAIN_VOLTAGE_SWING_400: 2089 demph_reg_value = 0x2B305555; 2090 uniqtranscale_reg_value = 0x5570B83A; 2091 break; 2092 case DP_TRAIN_VOLTAGE_SWING_600: 2093 demph_reg_value = 0x2B2B4040; 2094 uniqtranscale_reg_value = 0x55ADDA3A; 2095 break; 2096 default: 2097 return 0; 2098 } 2099 break; 2100 case DP_TRAIN_PRE_EMPHASIS_9_5: 2101 preemph_reg_value = 0x0006000; 2102 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { 2103 case DP_TRAIN_VOLTAGE_SWING_400: 2104 demph_reg_value = 0x1B405555; 2105 uniqtranscale_reg_value = 0x55ADDA3A; 2106 break; 2107 default: 2108 return 0; 2109 } 2110 break; 2111 default: 2112 return 0; 2113 } 2114 2115 mutex_lock(&dev_priv->dpio_lock); 2116 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x00000000); 2117 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW4(port), demph_reg_value); 2118 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(port), 2119 uniqtranscale_reg_value); 2120 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(port), 0x0C782040); 2121 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW11(port), 0x00030000); 2122 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), preemph_reg_value); 2123 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x80000000); 2124 mutex_unlock(&dev_priv->dpio_lock); 2125 2126 return 0; 2127} 2128 2129static void 2130intel_get_adjust_train(struct intel_dp *intel_dp, 2131 const uint8_t link_status[DP_LINK_STATUS_SIZE]) 2132{ 2133 uint8_t v = 0; 2134 uint8_t p = 0; 2135 int lane; 2136 uint8_t voltage_max; 2137 uint8_t preemph_max; 2138 2139 for (lane = 0; lane < intel_dp->lane_count; lane++) { 2140 uint8_t this_v = drm_dp_get_adjust_request_voltage(link_status, lane); 2141 uint8_t this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane); 2142 2143 if (this_v > v) 2144 v = this_v; 2145 if (this_p > p) 2146 p = this_p; 2147 } 2148 2149 voltage_max = intel_dp_voltage_max(intel_dp); 2150 if (v >= voltage_max) 2151 v = voltage_max | DP_TRAIN_MAX_SWING_REACHED; 2152 2153 preemph_max = intel_dp_pre_emphasis_max(intel_dp, v); 2154 if (p >= preemph_max) 2155 p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED; 2156 2157 for (lane = 0; lane < 4; lane++) 2158 intel_dp->train_set[lane] = v | p; 2159} 2160 2161static uint32_t 2162intel_gen4_signal_levels(uint8_t train_set) 2163{ 2164 uint32_t signal_levels = 0; 2165 2166 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { 2167 case DP_TRAIN_VOLTAGE_SWING_400: 2168 default: 2169 signal_levels |= DP_VOLTAGE_0_4; 2170 break; 2171 case DP_TRAIN_VOLTAGE_SWING_600: 2172 signal_levels |= DP_VOLTAGE_0_6; 2173 break; 2174 case DP_TRAIN_VOLTAGE_SWING_800: 2175 signal_levels |= DP_VOLTAGE_0_8; 2176 break; 2177 case DP_TRAIN_VOLTAGE_SWING_1200: 2178 signal_levels |= DP_VOLTAGE_1_2; 2179 break; 2180 } 2181 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) { 2182 case DP_TRAIN_PRE_EMPHASIS_0: 2183 default: 2184 signal_levels |= DP_PRE_EMPHASIS_0; 2185 break; 2186 case DP_TRAIN_PRE_EMPHASIS_3_5: 2187 signal_levels |= DP_PRE_EMPHASIS_3_5; 2188 break; 2189 case DP_TRAIN_PRE_EMPHASIS_6: 2190 signal_levels |= DP_PRE_EMPHASIS_6; 2191 break; 2192 case DP_TRAIN_PRE_EMPHASIS_9_5: 2193 signal_levels |= DP_PRE_EMPHASIS_9_5; 2194 break; 2195 } 2196 return signal_levels; 2197} 2198 2199/* Gen6's DP voltage swing and pre-emphasis control */ 2200static uint32_t 2201intel_gen6_edp_signal_levels(uint8_t train_set) 2202{ 2203 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK | 2204 DP_TRAIN_PRE_EMPHASIS_MASK); 2205 switch (signal_levels) { 2206 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0: 2207 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0: 2208 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B; 2209 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5: 2210 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B; 2211 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6: 2212 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6: 2213 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B; 2214 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5: 2215 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5: 2216 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B; 2217 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0: 2218 case DP_TRAIN_VOLTAGE_SWING_1200 | DP_TRAIN_PRE_EMPHASIS_0: 2219 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B; 2220 default: 2221 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:" 2222 "0x%x\n", signal_levels); 2223 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B; 2224 } 2225} 2226 2227/* Gen7's DP voltage swing and pre-emphasis control */ 2228static uint32_t 2229intel_gen7_edp_signal_levels(uint8_t train_set) 2230{ 2231 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK | 2232 DP_TRAIN_PRE_EMPHASIS_MASK); 2233 switch (signal_levels) { 2234 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0: 2235 return EDP_LINK_TRAIN_400MV_0DB_IVB; 2236 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5: 2237 return EDP_LINK_TRAIN_400MV_3_5DB_IVB; 2238 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6: 2239 return EDP_LINK_TRAIN_400MV_6DB_IVB; 2240 2241 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0: 2242 return EDP_LINK_TRAIN_600MV_0DB_IVB; 2243 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5: 2244 return EDP_LINK_TRAIN_600MV_3_5DB_IVB; 2245 2246 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0: 2247 return EDP_LINK_TRAIN_800MV_0DB_IVB; 2248 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5: 2249 return EDP_LINK_TRAIN_800MV_3_5DB_IVB; 2250 2251 default: 2252 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:" 2253 "0x%x\n", signal_levels); 2254 return EDP_LINK_TRAIN_500MV_0DB_IVB; 2255 } 2256} 2257 2258/* Gen7.5's (HSW) DP voltage swing and pre-emphasis control */ 2259static uint32_t 2260intel_hsw_signal_levels(uint8_t train_set) 2261{ 2262 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK | 2263 DP_TRAIN_PRE_EMPHASIS_MASK); 2264 switch (signal_levels) { 2265 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0: 2266 return DDI_BUF_EMP_400MV_0DB_HSW; 2267 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5: 2268 return DDI_BUF_EMP_400MV_3_5DB_HSW; 2269 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6: 2270 return DDI_BUF_EMP_400MV_6DB_HSW; 2271 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_9_5: 2272 return DDI_BUF_EMP_400MV_9_5DB_HSW; 2273 2274 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0: 2275 return DDI_BUF_EMP_600MV_0DB_HSW; 2276 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5: 2277 return DDI_BUF_EMP_600MV_3_5DB_HSW; 2278 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6: 2279 return DDI_BUF_EMP_600MV_6DB_HSW; 2280 2281 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0: 2282 return DDI_BUF_EMP_800MV_0DB_HSW; 2283 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5: 2284 return DDI_BUF_EMP_800MV_3_5DB_HSW; 2285 default: 2286 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:" 2287 "0x%x\n", signal_levels); 2288 return DDI_BUF_EMP_400MV_0DB_HSW; 2289 } 2290} 2291 2292static uint32_t 2293intel_bdw_signal_levels(uint8_t train_set) 2294{ 2295 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK | 2296 DP_TRAIN_PRE_EMPHASIS_MASK); 2297 switch (signal_levels) { 2298 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0: 2299 return DDI_BUF_EMP_400MV_0DB_BDW; /* Sel0 */ 2300 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5: 2301 return DDI_BUF_EMP_400MV_3_5DB_BDW; /* Sel1 */ 2302 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6: 2303 return DDI_BUF_EMP_400MV_6DB_BDW; /* Sel2 */ 2304 2305 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0: 2306 return DDI_BUF_EMP_600MV_0DB_BDW; /* Sel3 */ 2307 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5: 2308 return DDI_BUF_EMP_600MV_3_5DB_BDW; /* Sel4 */ 2309 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6: 2310 return DDI_BUF_EMP_600MV_6DB_BDW; /* Sel5 */ 2311 2312 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0: 2313 return DDI_BUF_EMP_800MV_0DB_BDW; /* Sel6 */ 2314 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5: 2315 return DDI_BUF_EMP_800MV_3_5DB_BDW; /* Sel7 */ 2316 2317 case DP_TRAIN_VOLTAGE_SWING_1200 | DP_TRAIN_PRE_EMPHASIS_0: 2318 return DDI_BUF_EMP_1200MV_0DB_BDW; /* Sel8 */ 2319 2320 default: 2321 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:" 2322 "0x%x\n", signal_levels); 2323 return DDI_BUF_EMP_400MV_0DB_BDW; /* Sel0 */ 2324 } 2325} 2326 2327/* Properly updates "DP" with the correct signal levels. */ 2328static void 2329intel_dp_set_signal_levels(struct intel_dp *intel_dp, uint32_t *DP) 2330{ 2331 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 2332 enum port port = intel_dig_port->port; 2333 struct drm_device *dev = intel_dig_port->base.base.dev; 2334 uint32_t signal_levels, mask; 2335 uint8_t train_set = intel_dp->train_set[0]; 2336 2337 if (IS_BROADWELL(dev)) { 2338 signal_levels = intel_bdw_signal_levels(train_set); 2339 mask = DDI_BUF_EMP_MASK; 2340 } else if (IS_HASWELL(dev)) { 2341 signal_levels = intel_hsw_signal_levels(train_set); 2342 mask = DDI_BUF_EMP_MASK; 2343 } else if (IS_VALLEYVIEW(dev)) { 2344 signal_levels = intel_vlv_signal_levels(intel_dp); 2345 mask = 0; 2346 } else if (IS_GEN7(dev) && port == PORT_A) { 2347 signal_levels = intel_gen7_edp_signal_levels(train_set); 2348 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_IVB; 2349 } else if (IS_GEN6(dev) && port == PORT_A) { 2350 signal_levels = intel_gen6_edp_signal_levels(train_set); 2351 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB; 2352 } else { 2353 signal_levels = intel_gen4_signal_levels(train_set); 2354 mask = DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK; 2355 } 2356 2357 DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels); 2358 2359 *DP = (*DP & ~mask) | signal_levels; 2360} 2361 2362static bool 2363intel_dp_set_link_train(struct intel_dp *intel_dp, 2364 uint32_t *DP, 2365 uint8_t dp_train_pat) 2366{ 2367 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 2368 struct drm_device *dev = intel_dig_port->base.base.dev; 2369 struct drm_i915_private *dev_priv = dev->dev_private; 2370 enum port port = intel_dig_port->port; 2371 uint8_t buf[sizeof(intel_dp->train_set) + 1]; 2372 int ret, len; 2373 2374 if (HAS_DDI(dev)) { 2375 uint32_t temp = I915_READ(DP_TP_CTL(port)); 2376 2377 if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE) 2378 temp |= DP_TP_CTL_SCRAMBLE_DISABLE; 2379 else 2380 temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE; 2381 2382 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK; 2383 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) { 2384 case DP_TRAINING_PATTERN_DISABLE: 2385 temp |= DP_TP_CTL_LINK_TRAIN_NORMAL; 2386 2387 break; 2388 case DP_TRAINING_PATTERN_1: 2389 temp |= DP_TP_CTL_LINK_TRAIN_PAT1; 2390 break; 2391 case DP_TRAINING_PATTERN_2: 2392 temp |= DP_TP_CTL_LINK_TRAIN_PAT2; 2393 break; 2394 case DP_TRAINING_PATTERN_3: 2395 temp |= DP_TP_CTL_LINK_TRAIN_PAT3; 2396 break; 2397 } 2398 I915_WRITE(DP_TP_CTL(port), temp); 2399 2400 } else if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) { 2401 *DP &= ~DP_LINK_TRAIN_MASK_CPT; 2402 2403 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) { 2404 case DP_TRAINING_PATTERN_DISABLE: 2405 *DP |= DP_LINK_TRAIN_OFF_CPT; 2406 break; 2407 case DP_TRAINING_PATTERN_1: 2408 *DP |= DP_LINK_TRAIN_PAT_1_CPT; 2409 break; 2410 case DP_TRAINING_PATTERN_2: 2411 *DP |= DP_LINK_TRAIN_PAT_2_CPT; 2412 break; 2413 case DP_TRAINING_PATTERN_3: 2414 DRM_ERROR("DP training pattern 3 not supported\n"); 2415 *DP |= DP_LINK_TRAIN_PAT_2_CPT; 2416 break; 2417 } 2418 2419 } else { 2420 *DP &= ~DP_LINK_TRAIN_MASK; 2421 2422 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) { 2423 case DP_TRAINING_PATTERN_DISABLE: 2424 *DP |= DP_LINK_TRAIN_OFF; 2425 break; 2426 case DP_TRAINING_PATTERN_1: 2427 *DP |= DP_LINK_TRAIN_PAT_1; 2428 break; 2429 case DP_TRAINING_PATTERN_2: 2430 *DP |= DP_LINK_TRAIN_PAT_2; 2431 break; 2432 case DP_TRAINING_PATTERN_3: 2433 DRM_ERROR("DP training pattern 3 not supported\n"); 2434 *DP |= DP_LINK_TRAIN_PAT_2; 2435 break; 2436 } 2437 } 2438 2439 I915_WRITE(intel_dp->output_reg, *DP); 2440 POSTING_READ(intel_dp->output_reg); 2441 2442 buf[0] = dp_train_pat; 2443 if ((dp_train_pat & DP_TRAINING_PATTERN_MASK) == 2444 DP_TRAINING_PATTERN_DISABLE) { 2445 /* don't write DP_TRAINING_LANEx_SET on disable */ 2446 len = 1; 2447 } else { 2448 /* DP_TRAINING_LANEx_SET follow DP_TRAINING_PATTERN_SET */ 2449 memcpy(buf + 1, intel_dp->train_set, intel_dp->lane_count); 2450 len = intel_dp->lane_count + 1; 2451 } 2452 2453 ret = drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_PATTERN_SET, 2454 buf, len); 2455 2456 return ret == len; 2457} 2458 2459static bool 2460intel_dp_reset_link_train(struct intel_dp *intel_dp, uint32_t *DP, 2461 uint8_t dp_train_pat) 2462{ 2463 memset(intel_dp->train_set, 0, sizeof(intel_dp->train_set)); 2464 intel_dp_set_signal_levels(intel_dp, DP); 2465 return intel_dp_set_link_train(intel_dp, DP, dp_train_pat); 2466} 2467 2468static bool 2469intel_dp_update_link_train(struct intel_dp *intel_dp, uint32_t *DP, 2470 const uint8_t link_status[DP_LINK_STATUS_SIZE]) 2471{ 2472 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 2473 struct drm_device *dev = intel_dig_port->base.base.dev; 2474 struct drm_i915_private *dev_priv = dev->dev_private; 2475 int ret; 2476 2477 intel_get_adjust_train(intel_dp, link_status); 2478 intel_dp_set_signal_levels(intel_dp, DP); 2479 2480 I915_WRITE(intel_dp->output_reg, *DP); 2481 POSTING_READ(intel_dp->output_reg); 2482 2483 ret = drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_LANE0_SET, 2484 intel_dp->train_set, intel_dp->lane_count); 2485 2486 return ret == intel_dp->lane_count; 2487} 2488 2489static void intel_dp_set_idle_link_train(struct intel_dp *intel_dp) 2490{ 2491 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 2492 struct drm_device *dev = intel_dig_port->base.base.dev; 2493 struct drm_i915_private *dev_priv = dev->dev_private; 2494 enum port port = intel_dig_port->port; 2495 uint32_t val; 2496 2497 if (!HAS_DDI(dev)) 2498 return; 2499 2500 val = I915_READ(DP_TP_CTL(port)); 2501 val &= ~DP_TP_CTL_LINK_TRAIN_MASK; 2502 val |= DP_TP_CTL_LINK_TRAIN_IDLE; 2503 I915_WRITE(DP_TP_CTL(port), val); 2504 2505 /* 2506 * On PORT_A we can have only eDP in SST mode. There the only reason 2507 * we need to set idle transmission mode is to work around a HW issue 2508 * where we enable the pipe while not in idle link-training mode. 2509 * In this case there is requirement to wait for a minimum number of 2510 * idle patterns to be sent. 2511 */ 2512 if (port == PORT_A) 2513 return; 2514 2515 if (wait_for((I915_READ(DP_TP_STATUS(port)) & DP_TP_STATUS_IDLE_DONE), 2516 1)) 2517 DRM_ERROR("Timed out waiting for DP idle patterns\n"); 2518} 2519 2520/* Enable corresponding port and start training pattern 1 */ 2521void 2522intel_dp_start_link_train(struct intel_dp *intel_dp) 2523{ 2524 struct drm_encoder *encoder = &dp_to_dig_port(intel_dp)->base.base; 2525 struct drm_device *dev = encoder->dev; 2526 int i; 2527 uint8_t voltage; 2528 int voltage_tries, loop_tries; 2529 uint32_t DP = intel_dp->DP; 2530 uint8_t link_config[2]; 2531 2532 if (HAS_DDI(dev)) 2533 intel_ddi_prepare_link_retrain(encoder); 2534 2535 /* Write the link configuration data */ 2536 link_config[0] = intel_dp->link_bw; 2537 link_config[1] = intel_dp->lane_count; 2538 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd)) 2539 link_config[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN; 2540 drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_BW_SET, link_config, 2); 2541 2542 link_config[0] = 0; 2543 link_config[1] = DP_SET_ANSI_8B10B; 2544 drm_dp_dpcd_write(&intel_dp->aux, DP_DOWNSPREAD_CTRL, link_config, 2); 2545 2546 DP |= DP_PORT_EN; 2547 2548 /* clock recovery */ 2549 if (!intel_dp_reset_link_train(intel_dp, &DP, 2550 DP_TRAINING_PATTERN_1 | 2551 DP_LINK_SCRAMBLING_DISABLE)) { 2552 DRM_ERROR("failed to enable link training\n"); 2553 return; 2554 } 2555 2556 voltage = 0xff; 2557 voltage_tries = 0; 2558 loop_tries = 0; 2559 for (;;) { 2560 uint8_t link_status[DP_LINK_STATUS_SIZE]; 2561 2562 drm_dp_link_train_clock_recovery_delay(intel_dp->dpcd); 2563 if (!intel_dp_get_link_status(intel_dp, link_status)) { 2564 DRM_ERROR("failed to get link status\n"); 2565 break; 2566 } 2567 2568 if (drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) { 2569 DRM_DEBUG_KMS("clock recovery OK\n"); 2570 break; 2571 } 2572 2573 /* Check to see if we've tried the max voltage */ 2574 for (i = 0; i < intel_dp->lane_count; i++) 2575 if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0) 2576 break; 2577 if (i == intel_dp->lane_count) { 2578 ++loop_tries; 2579 if (loop_tries == 5) { 2580 DRM_ERROR("too many full retries, give up\n"); 2581 break; 2582 } 2583 intel_dp_reset_link_train(intel_dp, &DP, 2584 DP_TRAINING_PATTERN_1 | 2585 DP_LINK_SCRAMBLING_DISABLE); 2586 voltage_tries = 0; 2587 continue; 2588 } 2589 2590 /* Check to see if we've tried the same voltage 5 times */ 2591 if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) { 2592 ++voltage_tries; 2593 if (voltage_tries == 5) { 2594 DRM_ERROR("too many voltage retries, give up\n"); 2595 break; 2596 } 2597 } else 2598 voltage_tries = 0; 2599 voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK; 2600 2601 /* Update training set as requested by target */ 2602 if (!intel_dp_update_link_train(intel_dp, &DP, link_status)) { 2603 DRM_ERROR("failed to update link training\n"); 2604 break; 2605 } 2606 } 2607 2608 intel_dp->DP = DP; 2609} 2610 2611void 2612intel_dp_complete_link_train(struct intel_dp *intel_dp) 2613{ 2614 bool channel_eq = false; 2615 int tries, cr_tries; 2616 uint32_t DP = intel_dp->DP; 2617 uint32_t training_pattern = DP_TRAINING_PATTERN_2; 2618 2619 /* Training Pattern 3 for HBR2 ot 1.2 devices that support it*/ 2620 if (intel_dp->link_bw == DP_LINK_BW_5_4 || intel_dp->use_tps3) 2621 training_pattern = DP_TRAINING_PATTERN_3; 2622 2623 /* channel equalization */ 2624 if (!intel_dp_set_link_train(intel_dp, &DP, 2625 training_pattern | 2626 DP_LINK_SCRAMBLING_DISABLE)) { 2627 DRM_ERROR("failed to start channel equalization\n"); 2628 return; 2629 } 2630 2631 tries = 0; 2632 cr_tries = 0; 2633 channel_eq = false; 2634 for (;;) { 2635 uint8_t link_status[DP_LINK_STATUS_SIZE]; 2636 2637 if (cr_tries > 5) { 2638 DRM_ERROR("failed to train DP, aborting\n"); 2639 break; 2640 } 2641 2642 drm_dp_link_train_channel_eq_delay(intel_dp->dpcd); 2643 if (!intel_dp_get_link_status(intel_dp, link_status)) { 2644 DRM_ERROR("failed to get link status\n"); 2645 break; 2646 } 2647 2648 /* Make sure clock is still ok */ 2649 if (!drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) { 2650 intel_dp_start_link_train(intel_dp); 2651 intel_dp_set_link_train(intel_dp, &DP, 2652 training_pattern | 2653 DP_LINK_SCRAMBLING_DISABLE); 2654 cr_tries++; 2655 continue; 2656 } 2657 2658 if (drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) { 2659 channel_eq = true; 2660 break; 2661 } 2662 2663 /* Try 5 times, then try clock recovery if that fails */ 2664 if (tries > 5) { 2665 intel_dp_link_down(intel_dp); 2666 intel_dp_start_link_train(intel_dp); 2667 intel_dp_set_link_train(intel_dp, &DP, 2668 training_pattern | 2669 DP_LINK_SCRAMBLING_DISABLE); 2670 tries = 0; 2671 cr_tries++; 2672 continue; 2673 } 2674 2675 /* Update training set as requested by target */ 2676 if (!intel_dp_update_link_train(intel_dp, &DP, link_status)) { 2677 DRM_ERROR("failed to update link training\n"); 2678 break; 2679 } 2680 ++tries; 2681 } 2682 2683 intel_dp_set_idle_link_train(intel_dp); 2684 2685 intel_dp->DP = DP; 2686 2687 if (channel_eq) 2688 DRM_DEBUG_KMS("Channel EQ done. DP Training successful\n"); 2689 2690} 2691 2692void intel_dp_stop_link_train(struct intel_dp *intel_dp) 2693{ 2694 intel_dp_set_link_train(intel_dp, &intel_dp->DP, 2695 DP_TRAINING_PATTERN_DISABLE); 2696} 2697 2698static void 2699intel_dp_link_down(struct intel_dp *intel_dp) 2700{ 2701 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 2702 enum port port = intel_dig_port->port; 2703 struct drm_device *dev = intel_dig_port->base.base.dev; 2704 struct drm_i915_private *dev_priv = dev->dev_private; 2705 struct intel_crtc *intel_crtc = 2706 to_intel_crtc(intel_dig_port->base.base.crtc); 2707 uint32_t DP = intel_dp->DP; 2708 2709 /* 2710 * DDI code has a strict mode set sequence and we should try to respect 2711 * it, otherwise we might hang the machine in many different ways. So we 2712 * really should be disabling the port only on a complete crtc_disable 2713 * sequence. This function is just called under two conditions on DDI 2714 * code: 2715 * - Link train failed while doing crtc_enable, and on this case we 2716 * really should respect the mode set sequence and wait for a 2717 * crtc_disable. 2718 * - Someone turned the monitor off and intel_dp_check_link_status 2719 * called us. We don't need to disable the whole port on this case, so 2720 * when someone turns the monitor on again, 2721 * intel_ddi_prepare_link_retrain will take care of redoing the link 2722 * train. 2723 */ 2724 if (HAS_DDI(dev)) 2725 return; 2726 2727 if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0)) 2728 return; 2729 2730 DRM_DEBUG_KMS("\n"); 2731 2732 if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) { 2733 DP &= ~DP_LINK_TRAIN_MASK_CPT; 2734 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT); 2735 } else { 2736 DP &= ~DP_LINK_TRAIN_MASK; 2737 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE); 2738 } 2739 POSTING_READ(intel_dp->output_reg); 2740 2741 /* We don't really know why we're doing this */ 2742 intel_wait_for_vblank(dev, intel_crtc->pipe); 2743 2744 if (HAS_PCH_IBX(dev) && 2745 I915_READ(intel_dp->output_reg) & DP_PIPEB_SELECT) { 2746 struct drm_crtc *crtc = intel_dig_port->base.base.crtc; 2747 2748 /* Hardware workaround: leaving our transcoder select 2749 * set to transcoder B while it's off will prevent the 2750 * corresponding HDMI output on transcoder A. 2751 * 2752 * Combine this with another hardware workaround: 2753 * transcoder select bit can only be cleared while the 2754 * port is enabled. 2755 */ 2756 DP &= ~DP_PIPEB_SELECT; 2757 I915_WRITE(intel_dp->output_reg, DP); 2758 2759 /* Changes to enable or select take place the vblank 2760 * after being written. 2761 */ 2762 if (WARN_ON(crtc == NULL)) { 2763 /* We should never try to disable a port without a crtc 2764 * attached. For paranoia keep the code around for a 2765 * bit. */ 2766 POSTING_READ(intel_dp->output_reg); 2767 msleep(50); 2768 } else 2769 intel_wait_for_vblank(dev, intel_crtc->pipe); 2770 } 2771 2772 DP &= ~DP_AUDIO_OUTPUT_ENABLE; 2773 I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN); 2774 POSTING_READ(intel_dp->output_reg); 2775 msleep(intel_dp->panel_power_down_delay); 2776} 2777 2778static bool 2779intel_dp_get_dpcd(struct intel_dp *intel_dp) 2780{ 2781 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 2782 struct drm_device *dev = dig_port->base.base.dev; 2783 struct drm_i915_private *dev_priv = dev->dev_private; 2784 2785 char dpcd_hex_dump[sizeof(intel_dp->dpcd) * 3]; 2786 2787 if (intel_dp_dpcd_read_wake(&intel_dp->aux, 0x000, intel_dp->dpcd, 2788 sizeof(intel_dp->dpcd)) < 0) 2789 return false; /* aux transfer failed */ 2790 2791 hex_dump_to_buffer(intel_dp->dpcd, sizeof(intel_dp->dpcd), 2792 32, 1, dpcd_hex_dump, sizeof(dpcd_hex_dump), false); 2793 DRM_DEBUG_KMS("DPCD: %s\n", dpcd_hex_dump); 2794 2795 if (intel_dp->dpcd[DP_DPCD_REV] == 0) 2796 return false; /* DPCD not present */ 2797 2798 /* Check if the panel supports PSR */ 2799 memset(intel_dp->psr_dpcd, 0, sizeof(intel_dp->psr_dpcd)); 2800 if (is_edp(intel_dp)) { 2801 intel_dp_dpcd_read_wake(&intel_dp->aux, DP_PSR_SUPPORT, 2802 intel_dp->psr_dpcd, 2803 sizeof(intel_dp->psr_dpcd)); 2804 if (intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED) { 2805 dev_priv->psr.sink_support = true; 2806 DRM_DEBUG_KMS("Detected EDP PSR Panel.\n"); 2807 } 2808 } 2809 2810 /* Training Pattern 3 support */ 2811 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x12 && 2812 intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_TPS3_SUPPORTED) { 2813 intel_dp->use_tps3 = true; 2814 DRM_DEBUG_KMS("Displayport TPS3 supported"); 2815 } else 2816 intel_dp->use_tps3 = false; 2817 2818 if (!(intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] & 2819 DP_DWN_STRM_PORT_PRESENT)) 2820 return true; /* native DP sink */ 2821 2822 if (intel_dp->dpcd[DP_DPCD_REV] == 0x10) 2823 return true; /* no per-port downstream info */ 2824 2825 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_DOWNSTREAM_PORT_0, 2826 intel_dp->downstream_ports, 2827 DP_MAX_DOWNSTREAM_PORTS) < 0) 2828 return false; /* downstream port status fetch failed */ 2829 2830 return true; 2831} 2832 2833static void 2834intel_dp_probe_oui(struct intel_dp *intel_dp) 2835{ 2836 u8 buf[3]; 2837 2838 if (!(intel_dp->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT)) 2839 return; 2840 2841 intel_edp_panel_vdd_on(intel_dp); 2842 2843 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_SINK_OUI, buf, 3) == 3) 2844 DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n", 2845 buf[0], buf[1], buf[2]); 2846 2847 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_BRANCH_OUI, buf, 3) == 3) 2848 DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n", 2849 buf[0], buf[1], buf[2]); 2850 2851 edp_panel_vdd_off(intel_dp, false); 2852} 2853 2854int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc) 2855{ 2856 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 2857 struct drm_device *dev = intel_dig_port->base.base.dev; 2858 struct intel_crtc *intel_crtc = 2859 to_intel_crtc(intel_dig_port->base.base.crtc); 2860 u8 buf[1]; 2861 2862 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK_MISC, buf) < 0) 2863 return -EAGAIN; 2864 2865 if (!(buf[0] & DP_TEST_CRC_SUPPORTED)) 2866 return -ENOTTY; 2867 2868 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK, 2869 DP_TEST_SINK_START) < 0) 2870 return -EAGAIN; 2871 2872 /* Wait 2 vblanks to be sure we will have the correct CRC value */ 2873 intel_wait_for_vblank(dev, intel_crtc->pipe); 2874 intel_wait_for_vblank(dev, intel_crtc->pipe); 2875 2876 if (drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_CRC_R_CR, crc, 6) < 0) 2877 return -EAGAIN; 2878 2879 drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK, 0); 2880 return 0; 2881} 2882 2883static bool 2884intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector) 2885{ 2886 return intel_dp_dpcd_read_wake(&intel_dp->aux, 2887 DP_DEVICE_SERVICE_IRQ_VECTOR, 2888 sink_irq_vector, 1) == 1; 2889} 2890 2891static void 2892intel_dp_handle_test_request(struct intel_dp *intel_dp) 2893{ 2894 /* NAK by default */ 2895 drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_RESPONSE, DP_TEST_NAK); 2896} 2897 2898/* 2899 * According to DP spec 2900 * 5.1.2: 2901 * 1. Read DPCD 2902 * 2. Configure link according to Receiver Capabilities 2903 * 3. Use Link Training from 2.5.3.3 and 3.5.1.3 2904 * 4. Check link status on receipt of hot-plug interrupt 2905 */ 2906 2907void 2908intel_dp_check_link_status(struct intel_dp *intel_dp) 2909{ 2910 struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base; 2911 u8 sink_irq_vector; 2912 u8 link_status[DP_LINK_STATUS_SIZE]; 2913 2914 if (!intel_encoder->connectors_active) 2915 return; 2916 2917 if (WARN_ON(!intel_encoder->base.crtc)) 2918 return; 2919 2920 /* Try to read receiver status if the link appears to be up */ 2921 if (!intel_dp_get_link_status(intel_dp, link_status)) { 2922 return; 2923 } 2924 2925 /* Now read the DPCD to see if it's actually running */ 2926 if (!intel_dp_get_dpcd(intel_dp)) { 2927 return; 2928 } 2929 2930 /* Try to read the source of the interrupt */ 2931 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 && 2932 intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) { 2933 /* Clear interrupt source */ 2934 drm_dp_dpcd_writeb(&intel_dp->aux, 2935 DP_DEVICE_SERVICE_IRQ_VECTOR, 2936 sink_irq_vector); 2937 2938 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST) 2939 intel_dp_handle_test_request(intel_dp); 2940 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ)) 2941 DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n"); 2942 } 2943 2944 if (!drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) { 2945 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n", 2946 drm_get_encoder_name(&intel_encoder->base)); 2947 intel_dp_start_link_train(intel_dp); 2948 intel_dp_complete_link_train(intel_dp); 2949 intel_dp_stop_link_train(intel_dp); 2950 } 2951} 2952 2953/* XXX this is probably wrong for multiple downstream ports */ 2954static enum drm_connector_status 2955intel_dp_detect_dpcd(struct intel_dp *intel_dp) 2956{ 2957 uint8_t *dpcd = intel_dp->dpcd; 2958 uint8_t type; 2959 2960 if (!intel_dp_get_dpcd(intel_dp)) 2961 return connector_status_disconnected; 2962 2963 /* if there's no downstream port, we're done */ 2964 if (!(dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT)) 2965 return connector_status_connected; 2966 2967 /* If we're HPD-aware, SINK_COUNT changes dynamically */ 2968 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 && 2969 intel_dp->downstream_ports[0] & DP_DS_PORT_HPD) { 2970 uint8_t reg; 2971 2972 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_SINK_COUNT, 2973 ®, 1) < 0) 2974 return connector_status_unknown; 2975 2976 return DP_GET_SINK_COUNT(reg) ? connector_status_connected 2977 : connector_status_disconnected; 2978 } 2979 2980 /* If no HPD, poke DDC gently */ 2981 if (drm_probe_ddc(&intel_dp->aux.ddc)) 2982 return connector_status_connected; 2983 2984 /* Well we tried, say unknown for unreliable port types */ 2985 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) { 2986 type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK; 2987 if (type == DP_DS_PORT_TYPE_VGA || 2988 type == DP_DS_PORT_TYPE_NON_EDID) 2989 return connector_status_unknown; 2990 } else { 2991 type = intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] & 2992 DP_DWN_STRM_PORT_TYPE_MASK; 2993 if (type == DP_DWN_STRM_PORT_TYPE_ANALOG || 2994 type == DP_DWN_STRM_PORT_TYPE_OTHER) 2995 return connector_status_unknown; 2996 } 2997 2998 /* Anything else is out of spec, warn and ignore */ 2999 DRM_DEBUG_KMS("Broken DP branch device, ignoring\n"); 3000 return connector_status_disconnected; 3001} 3002 3003static enum drm_connector_status 3004ironlake_dp_detect(struct intel_dp *intel_dp) 3005{ 3006 struct drm_device *dev = intel_dp_to_dev(intel_dp); 3007 struct drm_i915_private *dev_priv = dev->dev_private; 3008 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 3009 enum drm_connector_status status; 3010 3011 /* Can't disconnect eDP, but you can close the lid... */ 3012 if (is_edp(intel_dp)) { 3013 status = intel_panel_detect(dev); 3014 if (status == connector_status_unknown) 3015 status = connector_status_connected; 3016 return status; 3017 } 3018 3019 if (!ibx_digital_port_connected(dev_priv, intel_dig_port)) 3020 return connector_status_disconnected; 3021 3022 return intel_dp_detect_dpcd(intel_dp); 3023} 3024 3025static enum drm_connector_status 3026g4x_dp_detect(struct intel_dp *intel_dp) 3027{ 3028 struct drm_device *dev = intel_dp_to_dev(intel_dp); 3029 struct drm_i915_private *dev_priv = dev->dev_private; 3030 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 3031 uint32_t bit; 3032 3033 /* Can't disconnect eDP, but you can close the lid... */ 3034 if (is_edp(intel_dp)) { 3035 enum drm_connector_status status; 3036 3037 status = intel_panel_detect(dev); 3038 if (status == connector_status_unknown) 3039 status = connector_status_connected; 3040 return status; 3041 } 3042 3043 if (IS_VALLEYVIEW(dev)) { 3044 switch (intel_dig_port->port) { 3045 case PORT_B: 3046 bit = PORTB_HOTPLUG_LIVE_STATUS_VLV; 3047 break; 3048 case PORT_C: 3049 bit = PORTC_HOTPLUG_LIVE_STATUS_VLV; 3050 break; 3051 case PORT_D: 3052 bit = PORTD_HOTPLUG_LIVE_STATUS_VLV; 3053 break; 3054 default: 3055 return connector_status_unknown; 3056 } 3057 } else { 3058 switch (intel_dig_port->port) { 3059 case PORT_B: 3060 bit = PORTB_HOTPLUG_LIVE_STATUS_G4X; 3061 break; 3062 case PORT_C: 3063 bit = PORTC_HOTPLUG_LIVE_STATUS_G4X; 3064 break; 3065 case PORT_D: 3066 bit = PORTD_HOTPLUG_LIVE_STATUS_G4X; 3067 break; 3068 default: 3069 return connector_status_unknown; 3070 } 3071 } 3072 3073 if ((I915_READ(PORT_HOTPLUG_STAT) & bit) == 0) 3074 return connector_status_disconnected; 3075 3076 return intel_dp_detect_dpcd(intel_dp); 3077} 3078 3079static struct edid * 3080intel_dp_get_edid(struct drm_connector *connector, struct i2c_adapter *adapter) 3081{ 3082 struct intel_connector *intel_connector = to_intel_connector(connector); 3083 3084 /* use cached edid if we have one */ 3085 if (intel_connector->edid) { 3086 /* invalid edid */ 3087 if (IS_ERR(intel_connector->edid)) 3088 return NULL; 3089 3090 return drm_edid_duplicate(intel_connector->edid); 3091 } 3092 3093 return drm_get_edid(connector, adapter); 3094} 3095 3096static int 3097intel_dp_get_edid_modes(struct drm_connector *connector, struct i2c_adapter *adapter) 3098{ 3099 struct intel_connector *intel_connector = to_intel_connector(connector); 3100 3101 /* use cached edid if we have one */ 3102 if (intel_connector->edid) { 3103 /* invalid edid */ 3104 if (IS_ERR(intel_connector->edid)) 3105 return 0; 3106 3107 return intel_connector_update_modes(connector, 3108 intel_connector->edid); 3109 } 3110 3111 return intel_ddc_get_modes(connector, adapter); 3112} 3113 3114static enum drm_connector_status 3115intel_dp_detect(struct drm_connector *connector, bool force) 3116{ 3117 struct intel_dp *intel_dp = intel_attached_dp(connector); 3118 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 3119 struct intel_encoder *intel_encoder = &intel_dig_port->base; 3120 struct drm_device *dev = connector->dev; 3121 struct drm_i915_private *dev_priv = dev->dev_private; 3122 enum drm_connector_status status; 3123 enum intel_display_power_domain power_domain; 3124 struct edid *edid = NULL; 3125 3126 intel_runtime_pm_get(dev_priv); 3127 3128 power_domain = intel_display_port_power_domain(intel_encoder); 3129 intel_display_power_get(dev_priv, power_domain); 3130 3131 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", 3132 connector->base.id, drm_get_connector_name(connector)); 3133 3134 intel_dp->has_audio = false; 3135 3136 if (HAS_PCH_SPLIT(dev)) 3137 status = ironlake_dp_detect(intel_dp); 3138 else 3139 status = g4x_dp_detect(intel_dp); 3140 3141 if (status != connector_status_connected) 3142 goto out; 3143 3144 intel_dp_probe_oui(intel_dp); 3145 3146 if (intel_dp->force_audio != HDMI_AUDIO_AUTO) { 3147 intel_dp->has_audio = (intel_dp->force_audio == HDMI_AUDIO_ON); 3148 } else { 3149 edid = intel_dp_get_edid(connector, &intel_dp->aux.ddc); 3150 if (edid) { 3151 intel_dp->has_audio = drm_detect_monitor_audio(edid); 3152 kfree(edid); 3153 } 3154 } 3155 3156 if (intel_encoder->type != INTEL_OUTPUT_EDP) 3157 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT; 3158 status = connector_status_connected; 3159 3160out: 3161 intel_display_power_put(dev_priv, power_domain); 3162 3163 intel_runtime_pm_put(dev_priv); 3164 3165 return status; 3166} 3167 3168static int intel_dp_get_modes(struct drm_connector *connector) 3169{ 3170 struct intel_dp *intel_dp = intel_attached_dp(connector); 3171 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 3172 struct intel_encoder *intel_encoder = &intel_dig_port->base; 3173 struct intel_connector *intel_connector = to_intel_connector(connector); 3174 struct drm_device *dev = connector->dev; 3175 struct drm_i915_private *dev_priv = dev->dev_private; 3176 enum intel_display_power_domain power_domain; 3177 int ret; 3178 3179 /* We should parse the EDID data and find out if it has an audio sink 3180 */ 3181 3182 power_domain = intel_display_port_power_domain(intel_encoder); 3183 intel_display_power_get(dev_priv, power_domain); 3184 3185 ret = intel_dp_get_edid_modes(connector, &intel_dp->aux.ddc); 3186 intel_display_power_put(dev_priv, power_domain); 3187 if (ret) 3188 return ret; 3189 3190 /* if eDP has no EDID, fall back to fixed mode */ 3191 if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) { 3192 struct drm_display_mode *mode; 3193 mode = drm_mode_duplicate(dev, 3194 intel_connector->panel.fixed_mode); 3195 if (mode) { 3196 drm_mode_probed_add(connector, mode); 3197 return 1; 3198 } 3199 } 3200 return 0; 3201} 3202 3203static bool 3204intel_dp_detect_audio(struct drm_connector *connector) 3205{ 3206 struct intel_dp *intel_dp = intel_attached_dp(connector); 3207 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 3208 struct intel_encoder *intel_encoder = &intel_dig_port->base; 3209 struct drm_device *dev = connector->dev; 3210 struct drm_i915_private *dev_priv = dev->dev_private; 3211 enum intel_display_power_domain power_domain; 3212 struct edid *edid; 3213 bool has_audio = false; 3214 3215 power_domain = intel_display_port_power_domain(intel_encoder); 3216 intel_display_power_get(dev_priv, power_domain); 3217 3218 edid = intel_dp_get_edid(connector, &intel_dp->aux.ddc); 3219 if (edid) { 3220 has_audio = drm_detect_monitor_audio(edid); 3221 kfree(edid); 3222 } 3223 3224 intel_display_power_put(dev_priv, power_domain); 3225 3226 return has_audio; 3227} 3228 3229static int 3230intel_dp_set_property(struct drm_connector *connector, 3231 struct drm_property *property, 3232 uint64_t val) 3233{ 3234 struct drm_i915_private *dev_priv = connector->dev->dev_private; 3235 struct intel_connector *intel_connector = to_intel_connector(connector); 3236 struct intel_encoder *intel_encoder = intel_attached_encoder(connector); 3237 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base); 3238 int ret; 3239 3240 ret = drm_object_property_set_value(&connector->base, property, val); 3241 if (ret) 3242 return ret; 3243 3244 if (property == dev_priv->force_audio_property) { 3245 int i = val; 3246 bool has_audio; 3247 3248 if (i == intel_dp->force_audio) 3249 return 0; 3250 3251 intel_dp->force_audio = i; 3252 3253 if (i == HDMI_AUDIO_AUTO) 3254 has_audio = intel_dp_detect_audio(connector); 3255 else 3256 has_audio = (i == HDMI_AUDIO_ON); 3257 3258 if (has_audio == intel_dp->has_audio) 3259 return 0; 3260 3261 intel_dp->has_audio = has_audio; 3262 goto done; 3263 } 3264 3265 if (property == dev_priv->broadcast_rgb_property) { 3266 bool old_auto = intel_dp->color_range_auto; 3267 uint32_t old_range = intel_dp->color_range; 3268 3269 switch (val) { 3270 case INTEL_BROADCAST_RGB_AUTO: 3271 intel_dp->color_range_auto = true; 3272 break; 3273 case INTEL_BROADCAST_RGB_FULL: 3274 intel_dp->color_range_auto = false; 3275 intel_dp->color_range = 0; 3276 break; 3277 case INTEL_BROADCAST_RGB_LIMITED: 3278 intel_dp->color_range_auto = false; 3279 intel_dp->color_range = DP_COLOR_RANGE_16_235; 3280 break; 3281 default: 3282 return -EINVAL; 3283 } 3284 3285 if (old_auto == intel_dp->color_range_auto && 3286 old_range == intel_dp->color_range) 3287 return 0; 3288 3289 goto done; 3290 } 3291 3292 if (is_edp(intel_dp) && 3293 property == connector->dev->mode_config.scaling_mode_property) { 3294 if (val == DRM_MODE_SCALE_NONE) { 3295 DRM_DEBUG_KMS("no scaling not supported\n"); 3296 return -EINVAL; 3297 } 3298 3299 if (intel_connector->panel.fitting_mode == val) { 3300 /* the eDP scaling property is not changed */ 3301 return 0; 3302 } 3303 intel_connector->panel.fitting_mode = val; 3304 3305 goto done; 3306 } 3307 3308 return -EINVAL; 3309 3310done: 3311 if (intel_encoder->base.crtc) 3312 intel_crtc_restore_mode(intel_encoder->base.crtc); 3313 3314 return 0; 3315} 3316 3317static void 3318intel_dp_connector_destroy(struct drm_connector *connector) 3319{ 3320 struct intel_connector *intel_connector = to_intel_connector(connector); 3321 3322 if (!IS_ERR_OR_NULL(intel_connector->edid)) 3323 kfree(intel_connector->edid); 3324 3325 /* Can't call is_edp() since the encoder may have been destroyed 3326 * already. */ 3327 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) 3328 intel_panel_fini(&intel_connector->panel); 3329 3330 drm_connector_cleanup(connector); 3331 kfree(connector); 3332} 3333 3334void intel_dp_encoder_destroy(struct drm_encoder *encoder) 3335{ 3336 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); 3337 struct intel_dp *intel_dp = &intel_dig_port->dp; 3338 struct drm_device *dev = intel_dp_to_dev(intel_dp); 3339 3340 drm_dp_aux_unregister_i2c_bus(&intel_dp->aux); 3341 drm_encoder_cleanup(encoder); 3342 if (is_edp(intel_dp)) { 3343 cancel_delayed_work_sync(&intel_dp->panel_vdd_work); 3344 mutex_lock(&dev->mode_config.mutex); 3345 edp_panel_vdd_off_sync(intel_dp); 3346 mutex_unlock(&dev->mode_config.mutex); 3347 } 3348 kfree(intel_dig_port); 3349} 3350 3351static const struct drm_connector_funcs intel_dp_connector_funcs = { 3352 .dpms = intel_connector_dpms, 3353 .detect = intel_dp_detect, 3354 .fill_modes = drm_helper_probe_single_connector_modes, 3355 .set_property = intel_dp_set_property, 3356 .destroy = intel_dp_connector_destroy, 3357}; 3358 3359static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = { 3360 .get_modes = intel_dp_get_modes, 3361 .mode_valid = intel_dp_mode_valid, 3362 .best_encoder = intel_best_encoder, 3363}; 3364 3365static const struct drm_encoder_funcs intel_dp_enc_funcs = { 3366 .destroy = intel_dp_encoder_destroy, 3367}; 3368 3369static void 3370intel_dp_hot_plug(struct intel_encoder *intel_encoder) 3371{ 3372 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base); 3373 3374 intel_dp_check_link_status(intel_dp); 3375} 3376 3377/* Return which DP Port should be selected for Transcoder DP control */ 3378int 3379intel_trans_dp_port_sel(struct drm_crtc *crtc) 3380{ 3381 struct drm_device *dev = crtc->dev; 3382 struct intel_encoder *intel_encoder; 3383 struct intel_dp *intel_dp; 3384 3385 for_each_encoder_on_crtc(dev, crtc, intel_encoder) { 3386 intel_dp = enc_to_intel_dp(&intel_encoder->base); 3387 3388 if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT || 3389 intel_encoder->type == INTEL_OUTPUT_EDP) 3390 return intel_dp->output_reg; 3391 } 3392 3393 return -1; 3394} 3395 3396/* check the VBT to see whether the eDP is on DP-D port */ 3397bool intel_dp_is_edp(struct drm_device *dev, enum port port) 3398{ 3399 struct drm_i915_private *dev_priv = dev->dev_private; 3400 union child_device_config *p_child; 3401 int i; 3402 static const short port_mapping[] = { 3403 [PORT_B] = PORT_IDPB, 3404 [PORT_C] = PORT_IDPC, 3405 [PORT_D] = PORT_IDPD, 3406 }; 3407 3408 if (port == PORT_A) 3409 return true; 3410 3411 if (!dev_priv->vbt.child_dev_num) 3412 return false; 3413 3414 for (i = 0; i < dev_priv->vbt.child_dev_num; i++) { 3415 p_child = dev_priv->vbt.child_dev + i; 3416 3417 if (p_child->common.dvo_port == port_mapping[port] && 3418 (p_child->common.device_type & DEVICE_TYPE_eDP_BITS) == 3419 (DEVICE_TYPE_eDP & DEVICE_TYPE_eDP_BITS)) 3420 return true; 3421 } 3422 return false; 3423} 3424 3425static void 3426intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector) 3427{ 3428 struct intel_connector *intel_connector = to_intel_connector(connector); 3429 3430 intel_attach_force_audio_property(connector); 3431 intel_attach_broadcast_rgb_property(connector); 3432 intel_dp->color_range_auto = true; 3433 3434 if (is_edp(intel_dp)) { 3435 drm_mode_create_scaling_mode_property(connector->dev); 3436 drm_object_attach_property( 3437 &connector->base, 3438 connector->dev->mode_config.scaling_mode_property, 3439 DRM_MODE_SCALE_ASPECT); 3440 intel_connector->panel.fitting_mode = DRM_MODE_SCALE_ASPECT; 3441 } 3442} 3443 3444static void intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp) 3445{ 3446 intel_dp->last_power_cycle = jiffies; 3447 intel_dp->last_power_on = jiffies; 3448 intel_dp->last_backlight_off = jiffies; 3449} 3450 3451static void 3452intel_dp_init_panel_power_sequencer(struct drm_device *dev, 3453 struct intel_dp *intel_dp, 3454 struct edp_power_seq *out) 3455{ 3456 struct drm_i915_private *dev_priv = dev->dev_private; 3457 struct edp_power_seq cur, vbt, spec, final; 3458 u32 pp_on, pp_off, pp_div, pp; 3459 int pp_ctrl_reg, pp_on_reg, pp_off_reg, pp_div_reg; 3460 3461 if (HAS_PCH_SPLIT(dev)) { 3462 pp_ctrl_reg = PCH_PP_CONTROL; 3463 pp_on_reg = PCH_PP_ON_DELAYS; 3464 pp_off_reg = PCH_PP_OFF_DELAYS; 3465 pp_div_reg = PCH_PP_DIVISOR; 3466 } else { 3467 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp); 3468 3469 pp_ctrl_reg = VLV_PIPE_PP_CONTROL(pipe); 3470 pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe); 3471 pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe); 3472 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe); 3473 } 3474 3475 /* Workaround: Need to write PP_CONTROL with the unlock key as 3476 * the very first thing. */ 3477 pp = ironlake_get_pp_control(intel_dp); 3478 I915_WRITE(pp_ctrl_reg, pp); 3479 3480 pp_on = I915_READ(pp_on_reg); 3481 pp_off = I915_READ(pp_off_reg); 3482 pp_div = I915_READ(pp_div_reg); 3483 3484 /* Pull timing values out of registers */ 3485 cur.t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >> 3486 PANEL_POWER_UP_DELAY_SHIFT; 3487 3488 cur.t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >> 3489 PANEL_LIGHT_ON_DELAY_SHIFT; 3490 3491 cur.t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >> 3492 PANEL_LIGHT_OFF_DELAY_SHIFT; 3493 3494 cur.t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >> 3495 PANEL_POWER_DOWN_DELAY_SHIFT; 3496 3497 cur.t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >> 3498 PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000; 3499 3500 DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n", 3501 cur.t1_t3, cur.t8, cur.t9, cur.t10, cur.t11_t12); 3502 3503 vbt = dev_priv->vbt.edp_pps; 3504 3505 /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of 3506 * our hw here, which are all in 100usec. */ 3507 spec.t1_t3 = 210 * 10; 3508 spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */ 3509 spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */ 3510 spec.t10 = 500 * 10; 3511 /* This one is special and actually in units of 100ms, but zero 3512 * based in the hw (so we need to add 100 ms). But the sw vbt 3513 * table multiplies it with 1000 to make it in units of 100usec, 3514 * too. */ 3515 spec.t11_t12 = (510 + 100) * 10; 3516 3517 DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n", 3518 vbt.t1_t3, vbt.t8, vbt.t9, vbt.t10, vbt.t11_t12); 3519 3520 /* Use the max of the register settings and vbt. If both are 3521 * unset, fall back to the spec limits. */ 3522#define assign_final(field) final.field = (max(cur.field, vbt.field) == 0 ? \ 3523 spec.field : \ 3524 max(cur.field, vbt.field)) 3525 assign_final(t1_t3); 3526 assign_final(t8); 3527 assign_final(t9); 3528 assign_final(t10); 3529 assign_final(t11_t12); 3530#undef assign_final 3531 3532#define get_delay(field) (DIV_ROUND_UP(final.field, 10)) 3533 intel_dp->panel_power_up_delay = get_delay(t1_t3); 3534 intel_dp->backlight_on_delay = get_delay(t8); 3535 intel_dp->backlight_off_delay = get_delay(t9); 3536 intel_dp->panel_power_down_delay = get_delay(t10); 3537 intel_dp->panel_power_cycle_delay = get_delay(t11_t12); 3538#undef get_delay 3539 3540 DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n", 3541 intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay, 3542 intel_dp->panel_power_cycle_delay); 3543 3544 DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n", 3545 intel_dp->backlight_on_delay, intel_dp->backlight_off_delay); 3546 3547 if (out) 3548 *out = final; 3549} 3550 3551static void 3552intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev, 3553 struct intel_dp *intel_dp, 3554 struct edp_power_seq *seq) 3555{ 3556 struct drm_i915_private *dev_priv = dev->dev_private; 3557 u32 pp_on, pp_off, pp_div, port_sel = 0; 3558 int div = HAS_PCH_SPLIT(dev) ? intel_pch_rawclk(dev) : intel_hrawclk(dev); 3559 int pp_on_reg, pp_off_reg, pp_div_reg; 3560 3561 if (HAS_PCH_SPLIT(dev)) { 3562 pp_on_reg = PCH_PP_ON_DELAYS; 3563 pp_off_reg = PCH_PP_OFF_DELAYS; 3564 pp_div_reg = PCH_PP_DIVISOR; 3565 } else { 3566 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp); 3567 3568 pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe); 3569 pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe); 3570 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe); 3571 } 3572 3573 /* 3574 * And finally store the new values in the power sequencer. The 3575 * backlight delays are set to 1 because we do manual waits on them. For 3576 * T8, even BSpec recommends doing it. For T9, if we don't do this, 3577 * we'll end up waiting for the backlight off delay twice: once when we 3578 * do the manual sleep, and once when we disable the panel and wait for 3579 * the PP_STATUS bit to become zero. 3580 */ 3581 pp_on = (seq->t1_t3 << PANEL_POWER_UP_DELAY_SHIFT) | 3582 (1 << PANEL_LIGHT_ON_DELAY_SHIFT); 3583 pp_off = (1 << PANEL_LIGHT_OFF_DELAY_SHIFT) | 3584 (seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT); 3585 /* Compute the divisor for the pp clock, simply match the Bspec 3586 * formula. */ 3587 pp_div = ((100 * div)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT; 3588 pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000) 3589 << PANEL_POWER_CYCLE_DELAY_SHIFT); 3590 3591 /* Haswell doesn't have any port selection bits for the panel 3592 * power sequencer any more. */ 3593 if (IS_VALLEYVIEW(dev)) { 3594 if (dp_to_dig_port(intel_dp)->port == PORT_B) 3595 port_sel = PANEL_PORT_SELECT_DPB_VLV; 3596 else 3597 port_sel = PANEL_PORT_SELECT_DPC_VLV; 3598 } else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) { 3599 if (dp_to_dig_port(intel_dp)->port == PORT_A) 3600 port_sel = PANEL_PORT_SELECT_DPA; 3601 else 3602 port_sel = PANEL_PORT_SELECT_DPD; 3603 } 3604 3605 pp_on |= port_sel; 3606 3607 I915_WRITE(pp_on_reg, pp_on); 3608 I915_WRITE(pp_off_reg, pp_off); 3609 I915_WRITE(pp_div_reg, pp_div); 3610 3611 DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n", 3612 I915_READ(pp_on_reg), 3613 I915_READ(pp_off_reg), 3614 I915_READ(pp_div_reg)); 3615} 3616 3617static bool intel_edp_init_connector(struct intel_dp *intel_dp, 3618 struct intel_connector *intel_connector, 3619 struct edp_power_seq *power_seq) 3620{ 3621 struct drm_connector *connector = &intel_connector->base; 3622 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 3623 struct intel_encoder *intel_encoder = &intel_dig_port->base; 3624 struct drm_device *dev = intel_encoder->base.dev; 3625 struct drm_i915_private *dev_priv = dev->dev_private; 3626 struct drm_display_mode *fixed_mode = NULL; 3627 bool has_dpcd; 3628 struct drm_display_mode *scan; 3629 struct edid *edid; 3630 3631 if (!is_edp(intel_dp)) 3632 return true; 3633 3634 /* The VDD bit needs a power domain reference, so if the bit is already 3635 * enabled when we boot, grab this reference. */ 3636 if (edp_have_panel_vdd(intel_dp)) { 3637 enum intel_display_power_domain power_domain; 3638 power_domain = intel_display_port_power_domain(intel_encoder); 3639 intel_display_power_get(dev_priv, power_domain); 3640 } 3641 3642 /* Cache DPCD and EDID for edp. */ 3643 intel_edp_panel_vdd_on(intel_dp); 3644 has_dpcd = intel_dp_get_dpcd(intel_dp); 3645 edp_panel_vdd_off(intel_dp, false); 3646 3647 if (has_dpcd) { 3648 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) 3649 dev_priv->no_aux_handshake = 3650 intel_dp->dpcd[DP_MAX_DOWNSPREAD] & 3651 DP_NO_AUX_HANDSHAKE_LINK_TRAINING; 3652 } else { 3653 /* if this fails, presume the device is a ghost */ 3654 DRM_INFO("failed to retrieve link info, disabling eDP\n"); 3655 return false; 3656 } 3657 3658 /* We now know it's not a ghost, init power sequence regs. */ 3659 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp, power_seq); 3660 3661 mutex_lock(&dev->mode_config.mutex); 3662 edid = drm_get_edid(connector, &intel_dp->aux.ddc); 3663 if (edid) { 3664 if (drm_add_edid_modes(connector, edid)) { 3665 drm_mode_connector_update_edid_property(connector, 3666 edid); 3667 drm_edid_to_eld(connector, edid); 3668 } else { 3669 kfree(edid); 3670 edid = ERR_PTR(-EINVAL); 3671 } 3672 } else { 3673 edid = ERR_PTR(-ENOENT); 3674 } 3675 intel_connector->edid = edid; 3676 3677 /* prefer fixed mode from EDID if available */ 3678 list_for_each_entry(scan, &connector->probed_modes, head) { 3679 if ((scan->type & DRM_MODE_TYPE_PREFERRED)) { 3680 fixed_mode = drm_mode_duplicate(dev, scan); 3681 break; 3682 } 3683 } 3684 3685 /* fallback to VBT if available for eDP */ 3686 if (!fixed_mode && dev_priv->vbt.lfp_lvds_vbt_mode) { 3687 fixed_mode = drm_mode_duplicate(dev, 3688 dev_priv->vbt.lfp_lvds_vbt_mode); 3689 if (fixed_mode) 3690 fixed_mode->type |= DRM_MODE_TYPE_PREFERRED; 3691 } 3692 mutex_unlock(&dev->mode_config.mutex); 3693 3694 intel_panel_init(&intel_connector->panel, fixed_mode, NULL); 3695 intel_panel_setup_backlight(connector); 3696 3697 return true; 3698} 3699 3700bool 3701intel_dp_init_connector(struct intel_digital_port *intel_dig_port, 3702 struct intel_connector *intel_connector) 3703{ 3704 struct drm_connector *connector = &intel_connector->base; 3705 struct intel_dp *intel_dp = &intel_dig_port->dp; 3706 struct intel_encoder *intel_encoder = &intel_dig_port->base; 3707 struct drm_device *dev = intel_encoder->base.dev; 3708 struct drm_i915_private *dev_priv = dev->dev_private; 3709 enum port port = intel_dig_port->port; 3710 struct edp_power_seq power_seq = { 0 }; 3711 int type; 3712 3713 /* intel_dp vfuncs */ 3714 if (IS_VALLEYVIEW(dev)) 3715 intel_dp->get_aux_clock_divider = vlv_get_aux_clock_divider; 3716 else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) 3717 intel_dp->get_aux_clock_divider = hsw_get_aux_clock_divider; 3718 else if (HAS_PCH_SPLIT(dev)) 3719 intel_dp->get_aux_clock_divider = ilk_get_aux_clock_divider; 3720 else 3721 intel_dp->get_aux_clock_divider = i9xx_get_aux_clock_divider; 3722 3723 intel_dp->get_aux_send_ctl = i9xx_get_aux_send_ctl; 3724 3725 /* Preserve the current hw state. */ 3726 intel_dp->DP = I915_READ(intel_dp->output_reg); 3727 intel_dp->attached_connector = intel_connector; 3728 3729 if (intel_dp_is_edp(dev, port)) 3730 type = DRM_MODE_CONNECTOR_eDP; 3731 else 3732 type = DRM_MODE_CONNECTOR_DisplayPort; 3733 3734 /* 3735 * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but 3736 * for DP the encoder type can be set by the caller to 3737 * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it. 3738 */ 3739 if (type == DRM_MODE_CONNECTOR_eDP) 3740 intel_encoder->type = INTEL_OUTPUT_EDP; 3741 3742 DRM_DEBUG_KMS("Adding %s connector on port %c\n", 3743 type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP", 3744 port_name(port)); 3745 3746 drm_connector_init(dev, connector, &intel_dp_connector_funcs, type); 3747 drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs); 3748 3749 connector->interlace_allowed = true; 3750 connector->doublescan_allowed = 0; 3751 3752 INIT_DELAYED_WORK(&intel_dp->panel_vdd_work, 3753 edp_panel_vdd_work); 3754 3755 intel_connector_attach_encoder(intel_connector, intel_encoder); 3756 drm_sysfs_connector_add(connector); 3757 3758 if (HAS_DDI(dev)) 3759 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state; 3760 else 3761 intel_connector->get_hw_state = intel_connector_get_hw_state; 3762 intel_connector->unregister = intel_dp_connector_unregister; 3763 3764 /* Set up the hotplug pin. */ 3765 switch (port) { 3766 case PORT_A: 3767 intel_encoder->hpd_pin = HPD_PORT_A; 3768 break; 3769 case PORT_B: 3770 intel_encoder->hpd_pin = HPD_PORT_B; 3771 break; 3772 case PORT_C: 3773 intel_encoder->hpd_pin = HPD_PORT_C; 3774 break; 3775 case PORT_D: 3776 intel_encoder->hpd_pin = HPD_PORT_D; 3777 break; 3778 default: 3779 BUG(); 3780 } 3781 3782 if (is_edp(intel_dp)) { 3783 intel_dp_init_panel_power_timestamps(intel_dp); 3784 intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq); 3785 } 3786 3787 intel_dp_aux_init(intel_dp, intel_connector); 3788 3789 intel_dp->psr_setup_done = false; 3790 3791 if (!intel_edp_init_connector(intel_dp, intel_connector, &power_seq)) { 3792 drm_dp_aux_unregister_i2c_bus(&intel_dp->aux); 3793 if (is_edp(intel_dp)) { 3794 cancel_delayed_work_sync(&intel_dp->panel_vdd_work); 3795 mutex_lock(&dev->mode_config.mutex); 3796 edp_panel_vdd_off_sync(intel_dp); 3797 mutex_unlock(&dev->mode_config.mutex); 3798 } 3799 drm_sysfs_connector_remove(connector); 3800 drm_connector_cleanup(connector); 3801 return false; 3802 } 3803 3804 intel_dp_add_properties(intel_dp, connector); 3805 3806 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written 3807 * 0xd. Failure to do so will result in spurious interrupts being 3808 * generated on the port when a cable is not attached. 3809 */ 3810 if (IS_G4X(dev) && !IS_GM45(dev)) { 3811 u32 temp = I915_READ(PEG_BAND_GAP_DATA); 3812 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd); 3813 } 3814 3815 return true; 3816} 3817 3818void 3819intel_dp_init(struct drm_device *dev, int output_reg, enum port port) 3820{ 3821 struct intel_digital_port *intel_dig_port; 3822 struct intel_encoder *intel_encoder; 3823 struct drm_encoder *encoder; 3824 struct intel_connector *intel_connector; 3825 3826 intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL); 3827 if (!intel_dig_port) 3828 return; 3829 3830 intel_connector = kzalloc(sizeof(*intel_connector), GFP_KERNEL); 3831 if (!intel_connector) { 3832 kfree(intel_dig_port); 3833 return; 3834 } 3835 3836 intel_encoder = &intel_dig_port->base; 3837 encoder = &intel_encoder->base; 3838 3839 drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs, 3840 DRM_MODE_ENCODER_TMDS); 3841 3842 intel_encoder->compute_config = intel_dp_compute_config; 3843 intel_encoder->mode_set = intel_dp_mode_set; 3844 intel_encoder->disable = intel_disable_dp; 3845 intel_encoder->post_disable = intel_post_disable_dp; 3846 intel_encoder->get_hw_state = intel_dp_get_hw_state; 3847 intel_encoder->get_config = intel_dp_get_config; 3848 if (IS_VALLEYVIEW(dev)) { 3849 intel_encoder->pre_pll_enable = vlv_dp_pre_pll_enable; 3850 intel_encoder->pre_enable = vlv_pre_enable_dp; 3851 intel_encoder->enable = vlv_enable_dp; 3852 } else { 3853 intel_encoder->pre_enable = g4x_pre_enable_dp; 3854 intel_encoder->enable = g4x_enable_dp; 3855 } 3856 3857 intel_dig_port->port = port; 3858 intel_dig_port->dp.output_reg = output_reg; 3859 3860 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT; 3861 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2); 3862 intel_encoder->cloneable = 0; 3863 intel_encoder->hot_plug = intel_dp_hot_plug; 3864 3865 if (!intel_dp_init_connector(intel_dig_port, intel_connector)) { 3866 drm_encoder_cleanup(encoder); 3867 kfree(intel_dig_port); 3868 kfree(intel_connector); 3869 } 3870} 3871