intel_dp.c revision 9d1a1031e84f30f3671f0a650fc38a7c588acc8a
1/* 2 * Copyright © 2008 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 * Authors: 24 * Keith Packard <keithp@keithp.com> 25 * 26 */ 27 28#include <linux/i2c.h> 29#include <linux/slab.h> 30#include <linux/export.h> 31#include <drm/drmP.h> 32#include <drm/drm_crtc.h> 33#include <drm/drm_crtc_helper.h> 34#include <drm/drm_edid.h> 35#include "intel_drv.h" 36#include <drm/i915_drm.h> 37#include "i915_drv.h" 38 39#define DP_LINK_CHECK_TIMEOUT (10 * 1000) 40 41struct dp_link_dpll { 42 int link_bw; 43 struct dpll dpll; 44}; 45 46static const struct dp_link_dpll gen4_dpll[] = { 47 { DP_LINK_BW_1_62, 48 { .p1 = 2, .p2 = 10, .n = 2, .m1 = 23, .m2 = 8 } }, 49 { DP_LINK_BW_2_7, 50 { .p1 = 1, .p2 = 10, .n = 1, .m1 = 14, .m2 = 2 } } 51}; 52 53static const struct dp_link_dpll pch_dpll[] = { 54 { DP_LINK_BW_1_62, 55 { .p1 = 2, .p2 = 10, .n = 1, .m1 = 12, .m2 = 9 } }, 56 { DP_LINK_BW_2_7, 57 { .p1 = 1, .p2 = 10, .n = 2, .m1 = 14, .m2 = 8 } } 58}; 59 60static const struct dp_link_dpll vlv_dpll[] = { 61 { DP_LINK_BW_1_62, 62 { .p1 = 3, .p2 = 2, .n = 5, .m1 = 3, .m2 = 81 } }, 63 { DP_LINK_BW_2_7, 64 { .p1 = 2, .p2 = 2, .n = 1, .m1 = 2, .m2 = 27 } } 65}; 66 67/** 68 * is_edp - is the given port attached to an eDP panel (either CPU or PCH) 69 * @intel_dp: DP struct 70 * 71 * If a CPU or PCH DP output is attached to an eDP panel, this function 72 * will return true, and false otherwise. 73 */ 74static bool is_edp(struct intel_dp *intel_dp) 75{ 76 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 77 78 return intel_dig_port->base.type == INTEL_OUTPUT_EDP; 79} 80 81static struct drm_device *intel_dp_to_dev(struct intel_dp *intel_dp) 82{ 83 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 84 85 return intel_dig_port->base.base.dev; 86} 87 88static struct intel_dp *intel_attached_dp(struct drm_connector *connector) 89{ 90 return enc_to_intel_dp(&intel_attached_encoder(connector)->base); 91} 92 93static void intel_dp_link_down(struct intel_dp *intel_dp); 94static bool _edp_panel_vdd_on(struct intel_dp *intel_dp); 95static void edp_panel_vdd_on(struct intel_dp *intel_dp); 96static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync); 97 98static int 99intel_dp_max_link_bw(struct intel_dp *intel_dp) 100{ 101 int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE]; 102 struct drm_device *dev = intel_dp->attached_connector->base.dev; 103 104 switch (max_link_bw) { 105 case DP_LINK_BW_1_62: 106 case DP_LINK_BW_2_7: 107 break; 108 case DP_LINK_BW_5_4: /* 1.2 capable displays may advertise higher bw */ 109 if ((IS_HASWELL(dev) || INTEL_INFO(dev)->gen >= 8) && 110 intel_dp->dpcd[DP_DPCD_REV] >= 0x12) 111 max_link_bw = DP_LINK_BW_5_4; 112 else 113 max_link_bw = DP_LINK_BW_2_7; 114 break; 115 default: 116 WARN(1, "invalid max DP link bw val %x, using 1.62Gbps\n", 117 max_link_bw); 118 max_link_bw = DP_LINK_BW_1_62; 119 break; 120 } 121 return max_link_bw; 122} 123 124/* 125 * The units on the numbers in the next two are... bizarre. Examples will 126 * make it clearer; this one parallels an example in the eDP spec. 127 * 128 * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as: 129 * 130 * 270000 * 1 * 8 / 10 == 216000 131 * 132 * The actual data capacity of that configuration is 2.16Gbit/s, so the 133 * units are decakilobits. ->clock in a drm_display_mode is in kilohertz - 134 * or equivalently, kilopixels per second - so for 1680x1050R it'd be 135 * 119000. At 18bpp that's 2142000 kilobits per second. 136 * 137 * Thus the strange-looking division by 10 in intel_dp_link_required, to 138 * get the result in decakilobits instead of kilobits. 139 */ 140 141static int 142intel_dp_link_required(int pixel_clock, int bpp) 143{ 144 return (pixel_clock * bpp + 9) / 10; 145} 146 147static int 148intel_dp_max_data_rate(int max_link_clock, int max_lanes) 149{ 150 return (max_link_clock * max_lanes * 8) / 10; 151} 152 153static enum drm_mode_status 154intel_dp_mode_valid(struct drm_connector *connector, 155 struct drm_display_mode *mode) 156{ 157 struct intel_dp *intel_dp = intel_attached_dp(connector); 158 struct intel_connector *intel_connector = to_intel_connector(connector); 159 struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode; 160 int target_clock = mode->clock; 161 int max_rate, mode_rate, max_lanes, max_link_clock; 162 163 if (is_edp(intel_dp) && fixed_mode) { 164 if (mode->hdisplay > fixed_mode->hdisplay) 165 return MODE_PANEL; 166 167 if (mode->vdisplay > fixed_mode->vdisplay) 168 return MODE_PANEL; 169 170 target_clock = fixed_mode->clock; 171 } 172 173 max_link_clock = drm_dp_bw_code_to_link_rate(intel_dp_max_link_bw(intel_dp)); 174 max_lanes = drm_dp_max_lane_count(intel_dp->dpcd); 175 176 max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes); 177 mode_rate = intel_dp_link_required(target_clock, 18); 178 179 if (mode_rate > max_rate) 180 return MODE_CLOCK_HIGH; 181 182 if (mode->clock < 10000) 183 return MODE_CLOCK_LOW; 184 185 if (mode->flags & DRM_MODE_FLAG_DBLCLK) 186 return MODE_H_ILLEGAL; 187 188 return MODE_OK; 189} 190 191static uint32_t 192pack_aux(uint8_t *src, int src_bytes) 193{ 194 int i; 195 uint32_t v = 0; 196 197 if (src_bytes > 4) 198 src_bytes = 4; 199 for (i = 0; i < src_bytes; i++) 200 v |= ((uint32_t) src[i]) << ((3-i) * 8); 201 return v; 202} 203 204static void 205unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes) 206{ 207 int i; 208 if (dst_bytes > 4) 209 dst_bytes = 4; 210 for (i = 0; i < dst_bytes; i++) 211 dst[i] = src >> ((3-i) * 8); 212} 213 214/* hrawclock is 1/4 the FSB frequency */ 215static int 216intel_hrawclk(struct drm_device *dev) 217{ 218 struct drm_i915_private *dev_priv = dev->dev_private; 219 uint32_t clkcfg; 220 221 /* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */ 222 if (IS_VALLEYVIEW(dev)) 223 return 200; 224 225 clkcfg = I915_READ(CLKCFG); 226 switch (clkcfg & CLKCFG_FSB_MASK) { 227 case CLKCFG_FSB_400: 228 return 100; 229 case CLKCFG_FSB_533: 230 return 133; 231 case CLKCFG_FSB_667: 232 return 166; 233 case CLKCFG_FSB_800: 234 return 200; 235 case CLKCFG_FSB_1067: 236 return 266; 237 case CLKCFG_FSB_1333: 238 return 333; 239 /* these two are just a guess; one of them might be right */ 240 case CLKCFG_FSB_1600: 241 case CLKCFG_FSB_1600_ALT: 242 return 400; 243 default: 244 return 133; 245 } 246} 247 248static void 249intel_dp_init_panel_power_sequencer(struct drm_device *dev, 250 struct intel_dp *intel_dp, 251 struct edp_power_seq *out); 252static void 253intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev, 254 struct intel_dp *intel_dp, 255 struct edp_power_seq *out); 256 257static enum pipe 258vlv_power_sequencer_pipe(struct intel_dp *intel_dp) 259{ 260 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 261 struct drm_crtc *crtc = intel_dig_port->base.base.crtc; 262 struct drm_device *dev = intel_dig_port->base.base.dev; 263 struct drm_i915_private *dev_priv = dev->dev_private; 264 enum port port = intel_dig_port->port; 265 enum pipe pipe; 266 267 /* modeset should have pipe */ 268 if (crtc) 269 return to_intel_crtc(crtc)->pipe; 270 271 /* init time, try to find a pipe with this port selected */ 272 for (pipe = PIPE_A; pipe <= PIPE_B; pipe++) { 273 u32 port_sel = I915_READ(VLV_PIPE_PP_ON_DELAYS(pipe)) & 274 PANEL_PORT_SELECT_MASK; 275 if (port_sel == PANEL_PORT_SELECT_DPB_VLV && port == PORT_B) 276 return pipe; 277 if (port_sel == PANEL_PORT_SELECT_DPC_VLV && port == PORT_C) 278 return pipe; 279 } 280 281 /* shrug */ 282 return PIPE_A; 283} 284 285static u32 _pp_ctrl_reg(struct intel_dp *intel_dp) 286{ 287 struct drm_device *dev = intel_dp_to_dev(intel_dp); 288 289 if (HAS_PCH_SPLIT(dev)) 290 return PCH_PP_CONTROL; 291 else 292 return VLV_PIPE_PP_CONTROL(vlv_power_sequencer_pipe(intel_dp)); 293} 294 295static u32 _pp_stat_reg(struct intel_dp *intel_dp) 296{ 297 struct drm_device *dev = intel_dp_to_dev(intel_dp); 298 299 if (HAS_PCH_SPLIT(dev)) 300 return PCH_PP_STATUS; 301 else 302 return VLV_PIPE_PP_STATUS(vlv_power_sequencer_pipe(intel_dp)); 303} 304 305static bool edp_have_panel_power(struct intel_dp *intel_dp) 306{ 307 struct drm_device *dev = intel_dp_to_dev(intel_dp); 308 struct drm_i915_private *dev_priv = dev->dev_private; 309 310 return (I915_READ(_pp_stat_reg(intel_dp)) & PP_ON) != 0; 311} 312 313static bool edp_have_panel_vdd(struct intel_dp *intel_dp) 314{ 315 struct drm_device *dev = intel_dp_to_dev(intel_dp); 316 struct drm_i915_private *dev_priv = dev->dev_private; 317 318 return (I915_READ(_pp_ctrl_reg(intel_dp)) & EDP_FORCE_VDD) != 0; 319} 320 321static void 322intel_dp_check_edp(struct intel_dp *intel_dp) 323{ 324 struct drm_device *dev = intel_dp_to_dev(intel_dp); 325 struct drm_i915_private *dev_priv = dev->dev_private; 326 327 if (!is_edp(intel_dp)) 328 return; 329 330 if (!edp_have_panel_power(intel_dp) && !edp_have_panel_vdd(intel_dp)) { 331 WARN(1, "eDP powered off while attempting aux channel communication.\n"); 332 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n", 333 I915_READ(_pp_stat_reg(intel_dp)), 334 I915_READ(_pp_ctrl_reg(intel_dp))); 335 } 336} 337 338static uint32_t 339intel_dp_aux_wait_done(struct intel_dp *intel_dp, bool has_aux_irq) 340{ 341 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 342 struct drm_device *dev = intel_dig_port->base.base.dev; 343 struct drm_i915_private *dev_priv = dev->dev_private; 344 uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg; 345 uint32_t status; 346 bool done; 347 348#define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0) 349 if (has_aux_irq) 350 done = wait_event_timeout(dev_priv->gmbus_wait_queue, C, 351 msecs_to_jiffies_timeout(10)); 352 else 353 done = wait_for_atomic(C, 10) == 0; 354 if (!done) 355 DRM_ERROR("dp aux hw did not signal timeout (has irq: %i)!\n", 356 has_aux_irq); 357#undef C 358 359 return status; 360} 361 362static uint32_t i9xx_get_aux_clock_divider(struct intel_dp *intel_dp, int index) 363{ 364 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 365 struct drm_device *dev = intel_dig_port->base.base.dev; 366 367 /* 368 * The clock divider is based off the hrawclk, and would like to run at 369 * 2MHz. So, take the hrawclk value and divide by 2 and use that 370 */ 371 return index ? 0 : intel_hrawclk(dev) / 2; 372} 373 374static uint32_t ilk_get_aux_clock_divider(struct intel_dp *intel_dp, int index) 375{ 376 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 377 struct drm_device *dev = intel_dig_port->base.base.dev; 378 379 if (index) 380 return 0; 381 382 if (intel_dig_port->port == PORT_A) { 383 if (IS_GEN6(dev) || IS_GEN7(dev)) 384 return 200; /* SNB & IVB eDP input clock at 400Mhz */ 385 else 386 return 225; /* eDP input clock at 450Mhz */ 387 } else { 388 return DIV_ROUND_UP(intel_pch_rawclk(dev), 2); 389 } 390} 391 392static uint32_t hsw_get_aux_clock_divider(struct intel_dp *intel_dp, int index) 393{ 394 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 395 struct drm_device *dev = intel_dig_port->base.base.dev; 396 struct drm_i915_private *dev_priv = dev->dev_private; 397 398 if (intel_dig_port->port == PORT_A) { 399 if (index) 400 return 0; 401 return DIV_ROUND_CLOSEST(intel_ddi_get_cdclk_freq(dev_priv), 2000); 402 } else if (dev_priv->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE) { 403 /* Workaround for non-ULT HSW */ 404 switch (index) { 405 case 0: return 63; 406 case 1: return 72; 407 default: return 0; 408 } 409 } else { 410 return index ? 0 : DIV_ROUND_UP(intel_pch_rawclk(dev), 2); 411 } 412} 413 414static uint32_t vlv_get_aux_clock_divider(struct intel_dp *intel_dp, int index) 415{ 416 return index ? 0 : 100; 417} 418 419static uint32_t i9xx_get_aux_send_ctl(struct intel_dp *intel_dp, 420 bool has_aux_irq, 421 int send_bytes, 422 uint32_t aux_clock_divider) 423{ 424 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 425 struct drm_device *dev = intel_dig_port->base.base.dev; 426 uint32_t precharge, timeout; 427 428 if (IS_GEN6(dev)) 429 precharge = 3; 430 else 431 precharge = 5; 432 433 if (IS_BROADWELL(dev) && intel_dp->aux_ch_ctl_reg == DPA_AUX_CH_CTL) 434 timeout = DP_AUX_CH_CTL_TIME_OUT_600us; 435 else 436 timeout = DP_AUX_CH_CTL_TIME_OUT_400us; 437 438 return DP_AUX_CH_CTL_SEND_BUSY | 439 DP_AUX_CH_CTL_DONE | 440 (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) | 441 DP_AUX_CH_CTL_TIME_OUT_ERROR | 442 timeout | 443 DP_AUX_CH_CTL_RECEIVE_ERROR | 444 (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) | 445 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) | 446 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT); 447} 448 449static int 450intel_dp_aux_ch(struct intel_dp *intel_dp, 451 uint8_t *send, int send_bytes, 452 uint8_t *recv, int recv_size) 453{ 454 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 455 struct drm_device *dev = intel_dig_port->base.base.dev; 456 struct drm_i915_private *dev_priv = dev->dev_private; 457 uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg; 458 uint32_t ch_data = ch_ctl + 4; 459 uint32_t aux_clock_divider; 460 int i, ret, recv_bytes; 461 uint32_t status; 462 int try, clock = 0; 463 bool has_aux_irq = HAS_AUX_IRQ(dev); 464 bool vdd; 465 466 vdd = _edp_panel_vdd_on(intel_dp); 467 468 /* dp aux is extremely sensitive to irq latency, hence request the 469 * lowest possible wakeup latency and so prevent the cpu from going into 470 * deep sleep states. 471 */ 472 pm_qos_update_request(&dev_priv->pm_qos, 0); 473 474 intel_dp_check_edp(intel_dp); 475 476 intel_aux_display_runtime_get(dev_priv); 477 478 /* Try to wait for any previous AUX channel activity */ 479 for (try = 0; try < 3; try++) { 480 status = I915_READ_NOTRACE(ch_ctl); 481 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0) 482 break; 483 msleep(1); 484 } 485 486 if (try == 3) { 487 WARN(1, "dp_aux_ch not started status 0x%08x\n", 488 I915_READ(ch_ctl)); 489 ret = -EBUSY; 490 goto out; 491 } 492 493 /* Only 5 data registers! */ 494 if (WARN_ON(send_bytes > 20 || recv_size > 20)) { 495 ret = -E2BIG; 496 goto out; 497 } 498 499 while ((aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, clock++))) { 500 u32 send_ctl = intel_dp->get_aux_send_ctl(intel_dp, 501 has_aux_irq, 502 send_bytes, 503 aux_clock_divider); 504 505 /* Must try at least 3 times according to DP spec */ 506 for (try = 0; try < 5; try++) { 507 /* Load the send data into the aux channel data registers */ 508 for (i = 0; i < send_bytes; i += 4) 509 I915_WRITE(ch_data + i, 510 pack_aux(send + i, send_bytes - i)); 511 512 /* Send the command and wait for it to complete */ 513 I915_WRITE(ch_ctl, send_ctl); 514 515 status = intel_dp_aux_wait_done(intel_dp, has_aux_irq); 516 517 /* Clear done status and any errors */ 518 I915_WRITE(ch_ctl, 519 status | 520 DP_AUX_CH_CTL_DONE | 521 DP_AUX_CH_CTL_TIME_OUT_ERROR | 522 DP_AUX_CH_CTL_RECEIVE_ERROR); 523 524 if (status & (DP_AUX_CH_CTL_TIME_OUT_ERROR | 525 DP_AUX_CH_CTL_RECEIVE_ERROR)) 526 continue; 527 if (status & DP_AUX_CH_CTL_DONE) 528 break; 529 } 530 if (status & DP_AUX_CH_CTL_DONE) 531 break; 532 } 533 534 if ((status & DP_AUX_CH_CTL_DONE) == 0) { 535 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status); 536 ret = -EBUSY; 537 goto out; 538 } 539 540 /* Check for timeout or receive error. 541 * Timeouts occur when the sink is not connected 542 */ 543 if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) { 544 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status); 545 ret = -EIO; 546 goto out; 547 } 548 549 /* Timeouts occur when the device isn't connected, so they're 550 * "normal" -- don't fill the kernel log with these */ 551 if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) { 552 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status); 553 ret = -ETIMEDOUT; 554 goto out; 555 } 556 557 /* Unload any bytes sent back from the other side */ 558 recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >> 559 DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT); 560 if (recv_bytes > recv_size) 561 recv_bytes = recv_size; 562 563 for (i = 0; i < recv_bytes; i += 4) 564 unpack_aux(I915_READ(ch_data + i), 565 recv + i, recv_bytes - i); 566 567 ret = recv_bytes; 568out: 569 pm_qos_update_request(&dev_priv->pm_qos, PM_QOS_DEFAULT_VALUE); 570 intel_aux_display_runtime_put(dev_priv); 571 572 if (vdd) 573 edp_panel_vdd_off(intel_dp, false); 574 575 return ret; 576} 577 578#define HEADER_SIZE 4 579static ssize_t 580intel_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg) 581{ 582 struct intel_dp *intel_dp = container_of(aux, struct intel_dp, aux); 583 uint8_t txbuf[20], rxbuf[20]; 584 size_t txsize, rxsize; 585 int ret; 586 587 txbuf[0] = msg->request << 4; 588 txbuf[1] = msg->address >> 8; 589 txbuf[2] = msg->address & 0xff; 590 txbuf[3] = msg->size - 1; 591 592 switch (msg->request & ~DP_AUX_I2C_MOT) { 593 case DP_AUX_NATIVE_WRITE: 594 case DP_AUX_I2C_WRITE: 595 txsize = HEADER_SIZE + msg->size; 596 rxsize = 1; 597 598 if (WARN_ON(txsize > 20)) 599 return -E2BIG; 600 601 memcpy(txbuf + HEADER_SIZE, msg->buffer, msg->size); 602 603 ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize); 604 if (ret > 0) { 605 msg->reply = rxbuf[0] >> 4; 606 607 /* Return payload size. */ 608 ret = msg->size; 609 } 610 break; 611 612 case DP_AUX_NATIVE_READ: 613 case DP_AUX_I2C_READ: 614 txsize = HEADER_SIZE; 615 rxsize = msg->size + 1; 616 617 if (WARN_ON(rxsize > 20)) 618 return -E2BIG; 619 620 ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize); 621 if (ret > 0) { 622 msg->reply = rxbuf[0] >> 4; 623 /* 624 * Assume happy day, and copy the data. The caller is 625 * expected to check msg->reply before touching it. 626 * 627 * Return payload size. 628 */ 629 ret--; 630 memcpy(msg->buffer, rxbuf + 1, ret); 631 } 632 break; 633 634 default: 635 ret = -EINVAL; 636 break; 637 } 638 639 return ret; 640} 641 642static void 643intel_dp_aux_init(struct intel_dp *intel_dp, struct intel_connector *connector) 644{ 645 struct drm_device *dev = intel_dp_to_dev(intel_dp); 646 647 intel_dp->aux.dev = dev->dev; 648 intel_dp->aux.transfer = intel_dp_aux_transfer; 649} 650 651static int 652intel_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode, 653 uint8_t write_byte, uint8_t *read_byte) 654{ 655 struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data; 656 struct intel_dp *intel_dp = container_of(adapter, 657 struct intel_dp, 658 adapter); 659 uint16_t address = algo_data->address; 660 uint8_t msg[5]; 661 uint8_t reply[2]; 662 unsigned retry; 663 int msg_bytes; 664 int reply_bytes; 665 int ret; 666 667 /* Set up the command byte */ 668 if (mode & MODE_I2C_READ) 669 msg[0] = DP_AUX_I2C_READ << 4; 670 else 671 msg[0] = DP_AUX_I2C_WRITE << 4; 672 673 if (!(mode & MODE_I2C_STOP)) 674 msg[0] |= DP_AUX_I2C_MOT << 4; 675 676 msg[1] = address >> 8; 677 msg[2] = address; 678 679 switch (mode) { 680 case MODE_I2C_WRITE: 681 msg[3] = 0; 682 msg[4] = write_byte; 683 msg_bytes = 5; 684 reply_bytes = 1; 685 break; 686 case MODE_I2C_READ: 687 msg[3] = 0; 688 msg_bytes = 4; 689 reply_bytes = 2; 690 break; 691 default: 692 msg_bytes = 3; 693 reply_bytes = 1; 694 break; 695 } 696 697 /* 698 * DP1.2 sections 2.7.7.1.5.6.1 and 2.7.7.1.6.6.1: A DP Source device is 699 * required to retry at least seven times upon receiving AUX_DEFER 700 * before giving up the AUX transaction. 701 */ 702 for (retry = 0; retry < 7; retry++) { 703 ret = intel_dp_aux_ch(intel_dp, 704 msg, msg_bytes, 705 reply, reply_bytes); 706 if (ret < 0) { 707 DRM_DEBUG_KMS("aux_ch failed %d\n", ret); 708 goto out; 709 } 710 711 switch ((reply[0] >> 4) & DP_AUX_NATIVE_REPLY_MASK) { 712 case DP_AUX_NATIVE_REPLY_ACK: 713 /* I2C-over-AUX Reply field is only valid 714 * when paired with AUX ACK. 715 */ 716 break; 717 case DP_AUX_NATIVE_REPLY_NACK: 718 DRM_DEBUG_KMS("aux_ch native nack\n"); 719 ret = -EREMOTEIO; 720 goto out; 721 case DP_AUX_NATIVE_REPLY_DEFER: 722 /* 723 * For now, just give more slack to branch devices. We 724 * could check the DPCD for I2C bit rate capabilities, 725 * and if available, adjust the interval. We could also 726 * be more careful with DP-to-Legacy adapters where a 727 * long legacy cable may force very low I2C bit rates. 728 */ 729 if (intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] & 730 DP_DWN_STRM_PORT_PRESENT) 731 usleep_range(500, 600); 732 else 733 usleep_range(300, 400); 734 continue; 735 default: 736 DRM_ERROR("aux_ch invalid native reply 0x%02x\n", 737 reply[0]); 738 ret = -EREMOTEIO; 739 goto out; 740 } 741 742 switch ((reply[0] >> 4) & DP_AUX_I2C_REPLY_MASK) { 743 case DP_AUX_I2C_REPLY_ACK: 744 if (mode == MODE_I2C_READ) { 745 *read_byte = reply[1]; 746 } 747 ret = reply_bytes - 1; 748 goto out; 749 case DP_AUX_I2C_REPLY_NACK: 750 DRM_DEBUG_KMS("aux_i2c nack\n"); 751 ret = -EREMOTEIO; 752 goto out; 753 case DP_AUX_I2C_REPLY_DEFER: 754 DRM_DEBUG_KMS("aux_i2c defer\n"); 755 udelay(100); 756 break; 757 default: 758 DRM_ERROR("aux_i2c invalid reply 0x%02x\n", reply[0]); 759 ret = -EREMOTEIO; 760 goto out; 761 } 762 } 763 764 DRM_ERROR("too many retries, giving up\n"); 765 ret = -EREMOTEIO; 766 767out: 768 return ret; 769} 770 771static void 772intel_dp_connector_unregister(struct intel_connector *intel_connector) 773{ 774 struct intel_dp *intel_dp = intel_attached_dp(&intel_connector->base); 775 776 sysfs_remove_link(&intel_connector->base.kdev->kobj, 777 intel_dp->adapter.dev.kobj.name); 778 intel_connector_unregister(intel_connector); 779} 780 781static int 782intel_dp_i2c_init(struct intel_dp *intel_dp, 783 struct intel_connector *intel_connector, const char *name) 784{ 785 int ret; 786 787 DRM_DEBUG_KMS("i2c_init %s\n", name); 788 intel_dp->algo.running = false; 789 intel_dp->algo.address = 0; 790 intel_dp->algo.aux_ch = intel_dp_i2c_aux_ch; 791 792 memset(&intel_dp->adapter, '\0', sizeof(intel_dp->adapter)); 793 intel_dp->adapter.owner = THIS_MODULE; 794 intel_dp->adapter.class = I2C_CLASS_DDC; 795 strncpy(intel_dp->adapter.name, name, sizeof(intel_dp->adapter.name) - 1); 796 intel_dp->adapter.name[sizeof(intel_dp->adapter.name) - 1] = '\0'; 797 intel_dp->adapter.algo_data = &intel_dp->algo; 798 intel_dp->adapter.dev.parent = intel_connector->base.dev->dev; 799 800 ret = i2c_dp_aux_add_bus(&intel_dp->adapter); 801 if (ret < 0) 802 return ret; 803 804 ret = sysfs_create_link(&intel_connector->base.kdev->kobj, 805 &intel_dp->adapter.dev.kobj, 806 intel_dp->adapter.dev.kobj.name); 807 808 if (ret < 0) 809 i2c_del_adapter(&intel_dp->adapter); 810 811 return ret; 812} 813 814static void 815intel_dp_set_clock(struct intel_encoder *encoder, 816 struct intel_crtc_config *pipe_config, int link_bw) 817{ 818 struct drm_device *dev = encoder->base.dev; 819 const struct dp_link_dpll *divisor = NULL; 820 int i, count = 0; 821 822 if (IS_G4X(dev)) { 823 divisor = gen4_dpll; 824 count = ARRAY_SIZE(gen4_dpll); 825 } else if (IS_HASWELL(dev)) { 826 /* Haswell has special-purpose DP DDI clocks. */ 827 } else if (HAS_PCH_SPLIT(dev)) { 828 divisor = pch_dpll; 829 count = ARRAY_SIZE(pch_dpll); 830 } else if (IS_VALLEYVIEW(dev)) { 831 divisor = vlv_dpll; 832 count = ARRAY_SIZE(vlv_dpll); 833 } 834 835 if (divisor && count) { 836 for (i = 0; i < count; i++) { 837 if (link_bw == divisor[i].link_bw) { 838 pipe_config->dpll = divisor[i].dpll; 839 pipe_config->clock_set = true; 840 break; 841 } 842 } 843 } 844} 845 846bool 847intel_dp_compute_config(struct intel_encoder *encoder, 848 struct intel_crtc_config *pipe_config) 849{ 850 struct drm_device *dev = encoder->base.dev; 851 struct drm_i915_private *dev_priv = dev->dev_private; 852 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode; 853 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); 854 enum port port = dp_to_dig_port(intel_dp)->port; 855 struct intel_crtc *intel_crtc = encoder->new_crtc; 856 struct intel_connector *intel_connector = intel_dp->attached_connector; 857 int lane_count, clock; 858 int max_lane_count = drm_dp_max_lane_count(intel_dp->dpcd); 859 /* Conveniently, the link BW constants become indices with a shift...*/ 860 int max_clock = intel_dp_max_link_bw(intel_dp) >> 3; 861 int bpp, mode_rate; 862 static int bws[] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7, DP_LINK_BW_5_4 }; 863 int link_avail, link_clock; 864 865 if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev) && port != PORT_A) 866 pipe_config->has_pch_encoder = true; 867 868 pipe_config->has_dp_encoder = true; 869 870 if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) { 871 intel_fixed_panel_mode(intel_connector->panel.fixed_mode, 872 adjusted_mode); 873 if (!HAS_PCH_SPLIT(dev)) 874 intel_gmch_panel_fitting(intel_crtc, pipe_config, 875 intel_connector->panel.fitting_mode); 876 else 877 intel_pch_panel_fitting(intel_crtc, pipe_config, 878 intel_connector->panel.fitting_mode); 879 } 880 881 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK) 882 return false; 883 884 DRM_DEBUG_KMS("DP link computation with max lane count %i " 885 "max bw %02x pixel clock %iKHz\n", 886 max_lane_count, bws[max_clock], 887 adjusted_mode->crtc_clock); 888 889 /* Walk through all bpp values. Luckily they're all nicely spaced with 2 890 * bpc in between. */ 891 bpp = pipe_config->pipe_bpp; 892 if (is_edp(intel_dp) && dev_priv->vbt.edp_bpp && 893 dev_priv->vbt.edp_bpp < bpp) { 894 DRM_DEBUG_KMS("clamping bpp for eDP panel to BIOS-provided %i\n", 895 dev_priv->vbt.edp_bpp); 896 bpp = dev_priv->vbt.edp_bpp; 897 } 898 899 for (; bpp >= 6*3; bpp -= 2*3) { 900 mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock, 901 bpp); 902 903 for (lane_count = 1; lane_count <= max_lane_count; lane_count <<= 1) { 904 for (clock = 0; clock <= max_clock; clock++) { 905 link_clock = drm_dp_bw_code_to_link_rate(bws[clock]); 906 link_avail = intel_dp_max_data_rate(link_clock, 907 lane_count); 908 909 if (mode_rate <= link_avail) { 910 goto found; 911 } 912 } 913 } 914 } 915 916 return false; 917 918found: 919 if (intel_dp->color_range_auto) { 920 /* 921 * See: 922 * CEA-861-E - 5.1 Default Encoding Parameters 923 * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry 924 */ 925 if (bpp != 18 && drm_match_cea_mode(adjusted_mode) > 1) 926 intel_dp->color_range = DP_COLOR_RANGE_16_235; 927 else 928 intel_dp->color_range = 0; 929 } 930 931 if (intel_dp->color_range) 932 pipe_config->limited_color_range = true; 933 934 intel_dp->link_bw = bws[clock]; 935 intel_dp->lane_count = lane_count; 936 pipe_config->pipe_bpp = bpp; 937 pipe_config->port_clock = drm_dp_bw_code_to_link_rate(intel_dp->link_bw); 938 939 DRM_DEBUG_KMS("DP link bw %02x lane count %d clock %d bpp %d\n", 940 intel_dp->link_bw, intel_dp->lane_count, 941 pipe_config->port_clock, bpp); 942 DRM_DEBUG_KMS("DP link bw required %i available %i\n", 943 mode_rate, link_avail); 944 945 intel_link_compute_m_n(bpp, lane_count, 946 adjusted_mode->crtc_clock, 947 pipe_config->port_clock, 948 &pipe_config->dp_m_n); 949 950 intel_dp_set_clock(encoder, pipe_config, intel_dp->link_bw); 951 952 return true; 953} 954 955static void ironlake_set_pll_cpu_edp(struct intel_dp *intel_dp) 956{ 957 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 958 struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc); 959 struct drm_device *dev = crtc->base.dev; 960 struct drm_i915_private *dev_priv = dev->dev_private; 961 u32 dpa_ctl; 962 963 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", crtc->config.port_clock); 964 dpa_ctl = I915_READ(DP_A); 965 dpa_ctl &= ~DP_PLL_FREQ_MASK; 966 967 if (crtc->config.port_clock == 162000) { 968 /* For a long time we've carried around a ILK-DevA w/a for the 969 * 160MHz clock. If we're really unlucky, it's still required. 970 */ 971 DRM_DEBUG_KMS("160MHz cpu eDP clock, might need ilk devA w/a\n"); 972 dpa_ctl |= DP_PLL_FREQ_160MHZ; 973 intel_dp->DP |= DP_PLL_FREQ_160MHZ; 974 } else { 975 dpa_ctl |= DP_PLL_FREQ_270MHZ; 976 intel_dp->DP |= DP_PLL_FREQ_270MHZ; 977 } 978 979 I915_WRITE(DP_A, dpa_ctl); 980 981 POSTING_READ(DP_A); 982 udelay(500); 983} 984 985static void intel_dp_mode_set(struct intel_encoder *encoder) 986{ 987 struct drm_device *dev = encoder->base.dev; 988 struct drm_i915_private *dev_priv = dev->dev_private; 989 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); 990 enum port port = dp_to_dig_port(intel_dp)->port; 991 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); 992 struct drm_display_mode *adjusted_mode = &crtc->config.adjusted_mode; 993 994 /* 995 * There are four kinds of DP registers: 996 * 997 * IBX PCH 998 * SNB CPU 999 * IVB CPU 1000 * CPT PCH 1001 * 1002 * IBX PCH and CPU are the same for almost everything, 1003 * except that the CPU DP PLL is configured in this 1004 * register 1005 * 1006 * CPT PCH is quite different, having many bits moved 1007 * to the TRANS_DP_CTL register instead. That 1008 * configuration happens (oddly) in ironlake_pch_enable 1009 */ 1010 1011 /* Preserve the BIOS-computed detected bit. This is 1012 * supposed to be read-only. 1013 */ 1014 intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED; 1015 1016 /* Handle DP bits in common between all three register formats */ 1017 intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0; 1018 intel_dp->DP |= DP_PORT_WIDTH(intel_dp->lane_count); 1019 1020 if (intel_dp->has_audio) { 1021 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n", 1022 pipe_name(crtc->pipe)); 1023 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE; 1024 intel_write_eld(&encoder->base, adjusted_mode); 1025 } 1026 1027 /* Split out the IBX/CPU vs CPT settings */ 1028 1029 if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) { 1030 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) 1031 intel_dp->DP |= DP_SYNC_HS_HIGH; 1032 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) 1033 intel_dp->DP |= DP_SYNC_VS_HIGH; 1034 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT; 1035 1036 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd)) 1037 intel_dp->DP |= DP_ENHANCED_FRAMING; 1038 1039 intel_dp->DP |= crtc->pipe << 29; 1040 } else if (!HAS_PCH_CPT(dev) || port == PORT_A) { 1041 if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev)) 1042 intel_dp->DP |= intel_dp->color_range; 1043 1044 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) 1045 intel_dp->DP |= DP_SYNC_HS_HIGH; 1046 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) 1047 intel_dp->DP |= DP_SYNC_VS_HIGH; 1048 intel_dp->DP |= DP_LINK_TRAIN_OFF; 1049 1050 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd)) 1051 intel_dp->DP |= DP_ENHANCED_FRAMING; 1052 1053 if (crtc->pipe == 1) 1054 intel_dp->DP |= DP_PIPEB_SELECT; 1055 } else { 1056 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT; 1057 } 1058 1059 if (port == PORT_A && !IS_VALLEYVIEW(dev)) 1060 ironlake_set_pll_cpu_edp(intel_dp); 1061} 1062 1063#define IDLE_ON_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK) 1064#define IDLE_ON_VALUE (PP_ON | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE) 1065 1066#define IDLE_OFF_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | 0) 1067#define IDLE_OFF_VALUE (0 | PP_SEQUENCE_NONE | 0 | 0) 1068 1069#define IDLE_CYCLE_MASK (PP_ON | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK) 1070#define IDLE_CYCLE_VALUE (0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE) 1071 1072static void wait_panel_status(struct intel_dp *intel_dp, 1073 u32 mask, 1074 u32 value) 1075{ 1076 struct drm_device *dev = intel_dp_to_dev(intel_dp); 1077 struct drm_i915_private *dev_priv = dev->dev_private; 1078 u32 pp_stat_reg, pp_ctrl_reg; 1079 1080 pp_stat_reg = _pp_stat_reg(intel_dp); 1081 pp_ctrl_reg = _pp_ctrl_reg(intel_dp); 1082 1083 DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n", 1084 mask, value, 1085 I915_READ(pp_stat_reg), 1086 I915_READ(pp_ctrl_reg)); 1087 1088 if (_wait_for((I915_READ(pp_stat_reg) & mask) == value, 5000, 10)) { 1089 DRM_ERROR("Panel status timeout: status %08x control %08x\n", 1090 I915_READ(pp_stat_reg), 1091 I915_READ(pp_ctrl_reg)); 1092 } 1093 1094 DRM_DEBUG_KMS("Wait complete\n"); 1095} 1096 1097static void wait_panel_on(struct intel_dp *intel_dp) 1098{ 1099 DRM_DEBUG_KMS("Wait for panel power on\n"); 1100 wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE); 1101} 1102 1103static void wait_panel_off(struct intel_dp *intel_dp) 1104{ 1105 DRM_DEBUG_KMS("Wait for panel power off time\n"); 1106 wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE); 1107} 1108 1109static void wait_panel_power_cycle(struct intel_dp *intel_dp) 1110{ 1111 DRM_DEBUG_KMS("Wait for panel power cycle\n"); 1112 1113 /* When we disable the VDD override bit last we have to do the manual 1114 * wait. */ 1115 wait_remaining_ms_from_jiffies(intel_dp->last_power_cycle, 1116 intel_dp->panel_power_cycle_delay); 1117 1118 wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE); 1119} 1120 1121static void wait_backlight_on(struct intel_dp *intel_dp) 1122{ 1123 wait_remaining_ms_from_jiffies(intel_dp->last_power_on, 1124 intel_dp->backlight_on_delay); 1125} 1126 1127static void edp_wait_backlight_off(struct intel_dp *intel_dp) 1128{ 1129 wait_remaining_ms_from_jiffies(intel_dp->last_backlight_off, 1130 intel_dp->backlight_off_delay); 1131} 1132 1133/* Read the current pp_control value, unlocking the register if it 1134 * is locked 1135 */ 1136 1137static u32 ironlake_get_pp_control(struct intel_dp *intel_dp) 1138{ 1139 struct drm_device *dev = intel_dp_to_dev(intel_dp); 1140 struct drm_i915_private *dev_priv = dev->dev_private; 1141 u32 control; 1142 1143 control = I915_READ(_pp_ctrl_reg(intel_dp)); 1144 control &= ~PANEL_UNLOCK_MASK; 1145 control |= PANEL_UNLOCK_REGS; 1146 return control; 1147} 1148 1149static bool _edp_panel_vdd_on(struct intel_dp *intel_dp) 1150{ 1151 struct drm_device *dev = intel_dp_to_dev(intel_dp); 1152 struct drm_i915_private *dev_priv = dev->dev_private; 1153 u32 pp; 1154 u32 pp_stat_reg, pp_ctrl_reg; 1155 bool need_to_disable = !intel_dp->want_panel_vdd; 1156 1157 if (!is_edp(intel_dp)) 1158 return false; 1159 1160 intel_dp->want_panel_vdd = true; 1161 1162 if (edp_have_panel_vdd(intel_dp)) 1163 return need_to_disable; 1164 1165 intel_runtime_pm_get(dev_priv); 1166 1167 DRM_DEBUG_KMS("Turning eDP VDD on\n"); 1168 1169 if (!edp_have_panel_power(intel_dp)) 1170 wait_panel_power_cycle(intel_dp); 1171 1172 pp = ironlake_get_pp_control(intel_dp); 1173 pp |= EDP_FORCE_VDD; 1174 1175 pp_stat_reg = _pp_stat_reg(intel_dp); 1176 pp_ctrl_reg = _pp_ctrl_reg(intel_dp); 1177 1178 I915_WRITE(pp_ctrl_reg, pp); 1179 POSTING_READ(pp_ctrl_reg); 1180 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n", 1181 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg)); 1182 /* 1183 * If the panel wasn't on, delay before accessing aux channel 1184 */ 1185 if (!edp_have_panel_power(intel_dp)) { 1186 DRM_DEBUG_KMS("eDP was not running\n"); 1187 msleep(intel_dp->panel_power_up_delay); 1188 } 1189 1190 return need_to_disable; 1191} 1192 1193static void edp_panel_vdd_on(struct intel_dp *intel_dp) 1194{ 1195 if (is_edp(intel_dp)) { 1196 bool vdd = _edp_panel_vdd_on(intel_dp); 1197 1198 WARN(!vdd, "eDP VDD already requested on\n"); 1199 } 1200} 1201 1202static void edp_panel_vdd_off_sync(struct intel_dp *intel_dp) 1203{ 1204 struct drm_device *dev = intel_dp_to_dev(intel_dp); 1205 struct drm_i915_private *dev_priv = dev->dev_private; 1206 u32 pp; 1207 u32 pp_stat_reg, pp_ctrl_reg; 1208 1209 WARN_ON(!mutex_is_locked(&dev->mode_config.mutex)); 1210 1211 if (!intel_dp->want_panel_vdd && edp_have_panel_vdd(intel_dp)) { 1212 DRM_DEBUG_KMS("Turning eDP VDD off\n"); 1213 1214 pp = ironlake_get_pp_control(intel_dp); 1215 pp &= ~EDP_FORCE_VDD; 1216 1217 pp_ctrl_reg = _pp_ctrl_reg(intel_dp); 1218 pp_stat_reg = _pp_stat_reg(intel_dp); 1219 1220 I915_WRITE(pp_ctrl_reg, pp); 1221 POSTING_READ(pp_ctrl_reg); 1222 1223 /* Make sure sequencer is idle before allowing subsequent activity */ 1224 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n", 1225 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg)); 1226 1227 if ((pp & POWER_TARGET_ON) == 0) 1228 intel_dp->last_power_cycle = jiffies; 1229 1230 intel_runtime_pm_put(dev_priv); 1231 } 1232} 1233 1234static void edp_panel_vdd_work(struct work_struct *__work) 1235{ 1236 struct intel_dp *intel_dp = container_of(to_delayed_work(__work), 1237 struct intel_dp, panel_vdd_work); 1238 struct drm_device *dev = intel_dp_to_dev(intel_dp); 1239 1240 mutex_lock(&dev->mode_config.mutex); 1241 edp_panel_vdd_off_sync(intel_dp); 1242 mutex_unlock(&dev->mode_config.mutex); 1243} 1244 1245static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync) 1246{ 1247 if (!is_edp(intel_dp)) 1248 return; 1249 1250 WARN(!intel_dp->want_panel_vdd, "eDP VDD not forced on"); 1251 1252 intel_dp->want_panel_vdd = false; 1253 1254 if (sync) { 1255 edp_panel_vdd_off_sync(intel_dp); 1256 } else { 1257 /* 1258 * Queue the timer to fire a long 1259 * time from now (relative to the power down delay) 1260 * to keep the panel power up across a sequence of operations 1261 */ 1262 schedule_delayed_work(&intel_dp->panel_vdd_work, 1263 msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5)); 1264 } 1265} 1266 1267void intel_edp_panel_on(struct intel_dp *intel_dp) 1268{ 1269 struct drm_device *dev = intel_dp_to_dev(intel_dp); 1270 struct drm_i915_private *dev_priv = dev->dev_private; 1271 u32 pp; 1272 u32 pp_ctrl_reg; 1273 1274 if (!is_edp(intel_dp)) 1275 return; 1276 1277 DRM_DEBUG_KMS("Turn eDP power on\n"); 1278 1279 if (edp_have_panel_power(intel_dp)) { 1280 DRM_DEBUG_KMS("eDP power already on\n"); 1281 return; 1282 } 1283 1284 wait_panel_power_cycle(intel_dp); 1285 1286 pp_ctrl_reg = _pp_ctrl_reg(intel_dp); 1287 pp = ironlake_get_pp_control(intel_dp); 1288 if (IS_GEN5(dev)) { 1289 /* ILK workaround: disable reset around power sequence */ 1290 pp &= ~PANEL_POWER_RESET; 1291 I915_WRITE(pp_ctrl_reg, pp); 1292 POSTING_READ(pp_ctrl_reg); 1293 } 1294 1295 pp |= POWER_TARGET_ON; 1296 if (!IS_GEN5(dev)) 1297 pp |= PANEL_POWER_RESET; 1298 1299 I915_WRITE(pp_ctrl_reg, pp); 1300 POSTING_READ(pp_ctrl_reg); 1301 1302 wait_panel_on(intel_dp); 1303 intel_dp->last_power_on = jiffies; 1304 1305 if (IS_GEN5(dev)) { 1306 pp |= PANEL_POWER_RESET; /* restore panel reset bit */ 1307 I915_WRITE(pp_ctrl_reg, pp); 1308 POSTING_READ(pp_ctrl_reg); 1309 } 1310} 1311 1312void intel_edp_panel_off(struct intel_dp *intel_dp) 1313{ 1314 struct drm_device *dev = intel_dp_to_dev(intel_dp); 1315 struct drm_i915_private *dev_priv = dev->dev_private; 1316 u32 pp; 1317 u32 pp_ctrl_reg; 1318 1319 if (!is_edp(intel_dp)) 1320 return; 1321 1322 DRM_DEBUG_KMS("Turn eDP power off\n"); 1323 1324 edp_wait_backlight_off(intel_dp); 1325 1326 pp = ironlake_get_pp_control(intel_dp); 1327 /* We need to switch off panel power _and_ force vdd, for otherwise some 1328 * panels get very unhappy and cease to work. */ 1329 pp &= ~(POWER_TARGET_ON | PANEL_POWER_RESET | EDP_FORCE_VDD | 1330 EDP_BLC_ENABLE); 1331 1332 pp_ctrl_reg = _pp_ctrl_reg(intel_dp); 1333 1334 I915_WRITE(pp_ctrl_reg, pp); 1335 POSTING_READ(pp_ctrl_reg); 1336 1337 intel_dp->last_power_cycle = jiffies; 1338 wait_panel_off(intel_dp); 1339} 1340 1341void intel_edp_backlight_on(struct intel_dp *intel_dp) 1342{ 1343 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 1344 struct drm_device *dev = intel_dig_port->base.base.dev; 1345 struct drm_i915_private *dev_priv = dev->dev_private; 1346 u32 pp; 1347 u32 pp_ctrl_reg; 1348 1349 if (!is_edp(intel_dp)) 1350 return; 1351 1352 DRM_DEBUG_KMS("\n"); 1353 /* 1354 * If we enable the backlight right away following a panel power 1355 * on, we may see slight flicker as the panel syncs with the eDP 1356 * link. So delay a bit to make sure the image is solid before 1357 * allowing it to appear. 1358 */ 1359 wait_backlight_on(intel_dp); 1360 pp = ironlake_get_pp_control(intel_dp); 1361 pp |= EDP_BLC_ENABLE; 1362 1363 pp_ctrl_reg = _pp_ctrl_reg(intel_dp); 1364 1365 I915_WRITE(pp_ctrl_reg, pp); 1366 POSTING_READ(pp_ctrl_reg); 1367 1368 intel_panel_enable_backlight(intel_dp->attached_connector); 1369} 1370 1371void intel_edp_backlight_off(struct intel_dp *intel_dp) 1372{ 1373 struct drm_device *dev = intel_dp_to_dev(intel_dp); 1374 struct drm_i915_private *dev_priv = dev->dev_private; 1375 u32 pp; 1376 u32 pp_ctrl_reg; 1377 1378 if (!is_edp(intel_dp)) 1379 return; 1380 1381 intel_panel_disable_backlight(intel_dp->attached_connector); 1382 1383 DRM_DEBUG_KMS("\n"); 1384 pp = ironlake_get_pp_control(intel_dp); 1385 pp &= ~EDP_BLC_ENABLE; 1386 1387 pp_ctrl_reg = _pp_ctrl_reg(intel_dp); 1388 1389 I915_WRITE(pp_ctrl_reg, pp); 1390 POSTING_READ(pp_ctrl_reg); 1391 intel_dp->last_backlight_off = jiffies; 1392} 1393 1394static void ironlake_edp_pll_on(struct intel_dp *intel_dp) 1395{ 1396 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 1397 struct drm_crtc *crtc = intel_dig_port->base.base.crtc; 1398 struct drm_device *dev = crtc->dev; 1399 struct drm_i915_private *dev_priv = dev->dev_private; 1400 u32 dpa_ctl; 1401 1402 assert_pipe_disabled(dev_priv, 1403 to_intel_crtc(crtc)->pipe); 1404 1405 DRM_DEBUG_KMS("\n"); 1406 dpa_ctl = I915_READ(DP_A); 1407 WARN(dpa_ctl & DP_PLL_ENABLE, "dp pll on, should be off\n"); 1408 WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n"); 1409 1410 /* We don't adjust intel_dp->DP while tearing down the link, to 1411 * facilitate link retraining (e.g. after hotplug). Hence clear all 1412 * enable bits here to ensure that we don't enable too much. */ 1413 intel_dp->DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE); 1414 intel_dp->DP |= DP_PLL_ENABLE; 1415 I915_WRITE(DP_A, intel_dp->DP); 1416 POSTING_READ(DP_A); 1417 udelay(200); 1418} 1419 1420static void ironlake_edp_pll_off(struct intel_dp *intel_dp) 1421{ 1422 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 1423 struct drm_crtc *crtc = intel_dig_port->base.base.crtc; 1424 struct drm_device *dev = crtc->dev; 1425 struct drm_i915_private *dev_priv = dev->dev_private; 1426 u32 dpa_ctl; 1427 1428 assert_pipe_disabled(dev_priv, 1429 to_intel_crtc(crtc)->pipe); 1430 1431 dpa_ctl = I915_READ(DP_A); 1432 WARN((dpa_ctl & DP_PLL_ENABLE) == 0, 1433 "dp pll off, should be on\n"); 1434 WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n"); 1435 1436 /* We can't rely on the value tracked for the DP register in 1437 * intel_dp->DP because link_down must not change that (otherwise link 1438 * re-training will fail. */ 1439 dpa_ctl &= ~DP_PLL_ENABLE; 1440 I915_WRITE(DP_A, dpa_ctl); 1441 POSTING_READ(DP_A); 1442 udelay(200); 1443} 1444 1445/* If the sink supports it, try to set the power state appropriately */ 1446void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode) 1447{ 1448 int ret, i; 1449 1450 /* Should have a valid DPCD by this point */ 1451 if (intel_dp->dpcd[DP_DPCD_REV] < 0x11) 1452 return; 1453 1454 if (mode != DRM_MODE_DPMS_ON) { 1455 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER, 1456 DP_SET_POWER_D3); 1457 if (ret != 1) 1458 DRM_DEBUG_DRIVER("failed to write sink power state\n"); 1459 } else { 1460 /* 1461 * When turning on, we need to retry for 1ms to give the sink 1462 * time to wake up. 1463 */ 1464 for (i = 0; i < 3; i++) { 1465 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER, 1466 DP_SET_POWER_D0); 1467 if (ret == 1) 1468 break; 1469 msleep(1); 1470 } 1471 } 1472} 1473 1474static bool intel_dp_get_hw_state(struct intel_encoder *encoder, 1475 enum pipe *pipe) 1476{ 1477 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); 1478 enum port port = dp_to_dig_port(intel_dp)->port; 1479 struct drm_device *dev = encoder->base.dev; 1480 struct drm_i915_private *dev_priv = dev->dev_private; 1481 enum intel_display_power_domain power_domain; 1482 u32 tmp; 1483 1484 power_domain = intel_display_port_power_domain(encoder); 1485 if (!intel_display_power_enabled(dev_priv, power_domain)) 1486 return false; 1487 1488 tmp = I915_READ(intel_dp->output_reg); 1489 1490 if (!(tmp & DP_PORT_EN)) 1491 return false; 1492 1493 if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) { 1494 *pipe = PORT_TO_PIPE_CPT(tmp); 1495 } else if (!HAS_PCH_CPT(dev) || port == PORT_A) { 1496 *pipe = PORT_TO_PIPE(tmp); 1497 } else { 1498 u32 trans_sel; 1499 u32 trans_dp; 1500 int i; 1501 1502 switch (intel_dp->output_reg) { 1503 case PCH_DP_B: 1504 trans_sel = TRANS_DP_PORT_SEL_B; 1505 break; 1506 case PCH_DP_C: 1507 trans_sel = TRANS_DP_PORT_SEL_C; 1508 break; 1509 case PCH_DP_D: 1510 trans_sel = TRANS_DP_PORT_SEL_D; 1511 break; 1512 default: 1513 return true; 1514 } 1515 1516 for_each_pipe(i) { 1517 trans_dp = I915_READ(TRANS_DP_CTL(i)); 1518 if ((trans_dp & TRANS_DP_PORT_SEL_MASK) == trans_sel) { 1519 *pipe = i; 1520 return true; 1521 } 1522 } 1523 1524 DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n", 1525 intel_dp->output_reg); 1526 } 1527 1528 return true; 1529} 1530 1531static void intel_dp_get_config(struct intel_encoder *encoder, 1532 struct intel_crtc_config *pipe_config) 1533{ 1534 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); 1535 u32 tmp, flags = 0; 1536 struct drm_device *dev = encoder->base.dev; 1537 struct drm_i915_private *dev_priv = dev->dev_private; 1538 enum port port = dp_to_dig_port(intel_dp)->port; 1539 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); 1540 int dotclock; 1541 1542 if ((port == PORT_A) || !HAS_PCH_CPT(dev)) { 1543 tmp = I915_READ(intel_dp->output_reg); 1544 if (tmp & DP_SYNC_HS_HIGH) 1545 flags |= DRM_MODE_FLAG_PHSYNC; 1546 else 1547 flags |= DRM_MODE_FLAG_NHSYNC; 1548 1549 if (tmp & DP_SYNC_VS_HIGH) 1550 flags |= DRM_MODE_FLAG_PVSYNC; 1551 else 1552 flags |= DRM_MODE_FLAG_NVSYNC; 1553 } else { 1554 tmp = I915_READ(TRANS_DP_CTL(crtc->pipe)); 1555 if (tmp & TRANS_DP_HSYNC_ACTIVE_HIGH) 1556 flags |= DRM_MODE_FLAG_PHSYNC; 1557 else 1558 flags |= DRM_MODE_FLAG_NHSYNC; 1559 1560 if (tmp & TRANS_DP_VSYNC_ACTIVE_HIGH) 1561 flags |= DRM_MODE_FLAG_PVSYNC; 1562 else 1563 flags |= DRM_MODE_FLAG_NVSYNC; 1564 } 1565 1566 pipe_config->adjusted_mode.flags |= flags; 1567 1568 pipe_config->has_dp_encoder = true; 1569 1570 intel_dp_get_m_n(crtc, pipe_config); 1571 1572 if (port == PORT_A) { 1573 if ((I915_READ(DP_A) & DP_PLL_FREQ_MASK) == DP_PLL_FREQ_160MHZ) 1574 pipe_config->port_clock = 162000; 1575 else 1576 pipe_config->port_clock = 270000; 1577 } 1578 1579 dotclock = intel_dotclock_calculate(pipe_config->port_clock, 1580 &pipe_config->dp_m_n); 1581 1582 if (HAS_PCH_SPLIT(dev_priv->dev) && port != PORT_A) 1583 ironlake_check_encoder_dotclock(pipe_config, dotclock); 1584 1585 pipe_config->adjusted_mode.crtc_clock = dotclock; 1586 1587 if (is_edp(intel_dp) && dev_priv->vbt.edp_bpp && 1588 pipe_config->pipe_bpp > dev_priv->vbt.edp_bpp) { 1589 /* 1590 * This is a big fat ugly hack. 1591 * 1592 * Some machines in UEFI boot mode provide us a VBT that has 18 1593 * bpp and 1.62 GHz link bandwidth for eDP, which for reasons 1594 * unknown we fail to light up. Yet the same BIOS boots up with 1595 * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as 1596 * max, not what it tells us to use. 1597 * 1598 * Note: This will still be broken if the eDP panel is not lit 1599 * up by the BIOS, and thus we can't get the mode at module 1600 * load. 1601 */ 1602 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n", 1603 pipe_config->pipe_bpp, dev_priv->vbt.edp_bpp); 1604 dev_priv->vbt.edp_bpp = pipe_config->pipe_bpp; 1605 } 1606} 1607 1608static bool is_edp_psr(struct drm_device *dev) 1609{ 1610 struct drm_i915_private *dev_priv = dev->dev_private; 1611 1612 return dev_priv->psr.sink_support; 1613} 1614 1615static bool intel_edp_is_psr_enabled(struct drm_device *dev) 1616{ 1617 struct drm_i915_private *dev_priv = dev->dev_private; 1618 1619 if (!HAS_PSR(dev)) 1620 return false; 1621 1622 return I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE; 1623} 1624 1625static void intel_edp_psr_write_vsc(struct intel_dp *intel_dp, 1626 struct edp_vsc_psr *vsc_psr) 1627{ 1628 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 1629 struct drm_device *dev = dig_port->base.base.dev; 1630 struct drm_i915_private *dev_priv = dev->dev_private; 1631 struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc); 1632 u32 ctl_reg = HSW_TVIDEO_DIP_CTL(crtc->config.cpu_transcoder); 1633 u32 data_reg = HSW_TVIDEO_DIP_VSC_DATA(crtc->config.cpu_transcoder); 1634 uint32_t *data = (uint32_t *) vsc_psr; 1635 unsigned int i; 1636 1637 /* As per BSPec (Pipe Video Data Island Packet), we need to disable 1638 the video DIP being updated before program video DIP data buffer 1639 registers for DIP being updated. */ 1640 I915_WRITE(ctl_reg, 0); 1641 POSTING_READ(ctl_reg); 1642 1643 for (i = 0; i < VIDEO_DIP_VSC_DATA_SIZE; i += 4) { 1644 if (i < sizeof(struct edp_vsc_psr)) 1645 I915_WRITE(data_reg + i, *data++); 1646 else 1647 I915_WRITE(data_reg + i, 0); 1648 } 1649 1650 I915_WRITE(ctl_reg, VIDEO_DIP_ENABLE_VSC_HSW); 1651 POSTING_READ(ctl_reg); 1652} 1653 1654static void intel_edp_psr_setup(struct intel_dp *intel_dp) 1655{ 1656 struct drm_device *dev = intel_dp_to_dev(intel_dp); 1657 struct drm_i915_private *dev_priv = dev->dev_private; 1658 struct edp_vsc_psr psr_vsc; 1659 1660 if (intel_dp->psr_setup_done) 1661 return; 1662 1663 /* Prepare VSC packet as per EDP 1.3 spec, Table 3.10 */ 1664 memset(&psr_vsc, 0, sizeof(psr_vsc)); 1665 psr_vsc.sdp_header.HB0 = 0; 1666 psr_vsc.sdp_header.HB1 = 0x7; 1667 psr_vsc.sdp_header.HB2 = 0x2; 1668 psr_vsc.sdp_header.HB3 = 0x8; 1669 intel_edp_psr_write_vsc(intel_dp, &psr_vsc); 1670 1671 /* Avoid continuous PSR exit by masking memup and hpd */ 1672 I915_WRITE(EDP_PSR_DEBUG_CTL(dev), EDP_PSR_DEBUG_MASK_MEMUP | 1673 EDP_PSR_DEBUG_MASK_HPD | EDP_PSR_DEBUG_MASK_LPSP); 1674 1675 intel_dp->psr_setup_done = true; 1676} 1677 1678static void intel_edp_psr_enable_sink(struct intel_dp *intel_dp) 1679{ 1680 struct drm_device *dev = intel_dp_to_dev(intel_dp); 1681 struct drm_i915_private *dev_priv = dev->dev_private; 1682 uint32_t aux_clock_divider; 1683 int precharge = 0x3; 1684 int msg_size = 5; /* Header(4) + Message(1) */ 1685 1686 aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, 0); 1687 1688 /* Enable PSR in sink */ 1689 if (intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT) 1690 drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG, 1691 DP_PSR_ENABLE & ~DP_PSR_MAIN_LINK_ACTIVE); 1692 else 1693 drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG, 1694 DP_PSR_ENABLE | DP_PSR_MAIN_LINK_ACTIVE); 1695 1696 /* Setup AUX registers */ 1697 I915_WRITE(EDP_PSR_AUX_DATA1(dev), EDP_PSR_DPCD_COMMAND); 1698 I915_WRITE(EDP_PSR_AUX_DATA2(dev), EDP_PSR_DPCD_NORMAL_OPERATION); 1699 I915_WRITE(EDP_PSR_AUX_CTL(dev), 1700 DP_AUX_CH_CTL_TIME_OUT_400us | 1701 (msg_size << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) | 1702 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) | 1703 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT)); 1704} 1705 1706static void intel_edp_psr_enable_source(struct intel_dp *intel_dp) 1707{ 1708 struct drm_device *dev = intel_dp_to_dev(intel_dp); 1709 struct drm_i915_private *dev_priv = dev->dev_private; 1710 uint32_t max_sleep_time = 0x1f; 1711 uint32_t idle_frames = 1; 1712 uint32_t val = 0x0; 1713 const uint32_t link_entry_time = EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES; 1714 1715 if (intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT) { 1716 val |= EDP_PSR_LINK_STANDBY; 1717 val |= EDP_PSR_TP2_TP3_TIME_0us; 1718 val |= EDP_PSR_TP1_TIME_0us; 1719 val |= EDP_PSR_SKIP_AUX_EXIT; 1720 } else 1721 val |= EDP_PSR_LINK_DISABLE; 1722 1723 I915_WRITE(EDP_PSR_CTL(dev), val | 1724 IS_BROADWELL(dev) ? 0 : link_entry_time | 1725 max_sleep_time << EDP_PSR_MAX_SLEEP_TIME_SHIFT | 1726 idle_frames << EDP_PSR_IDLE_FRAME_SHIFT | 1727 EDP_PSR_ENABLE); 1728} 1729 1730static bool intel_edp_psr_match_conditions(struct intel_dp *intel_dp) 1731{ 1732 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 1733 struct drm_device *dev = dig_port->base.base.dev; 1734 struct drm_i915_private *dev_priv = dev->dev_private; 1735 struct drm_crtc *crtc = dig_port->base.base.crtc; 1736 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 1737 struct drm_i915_gem_object *obj = to_intel_framebuffer(crtc->fb)->obj; 1738 struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base; 1739 1740 dev_priv->psr.source_ok = false; 1741 1742 if (!HAS_PSR(dev)) { 1743 DRM_DEBUG_KMS("PSR not supported on this platform\n"); 1744 return false; 1745 } 1746 1747 if ((intel_encoder->type != INTEL_OUTPUT_EDP) || 1748 (dig_port->port != PORT_A)) { 1749 DRM_DEBUG_KMS("HSW ties PSR to DDI A (eDP)\n"); 1750 return false; 1751 } 1752 1753 if (!i915.enable_psr) { 1754 DRM_DEBUG_KMS("PSR disable by flag\n"); 1755 return false; 1756 } 1757 1758 crtc = dig_port->base.base.crtc; 1759 if (crtc == NULL) { 1760 DRM_DEBUG_KMS("crtc not active for PSR\n"); 1761 return false; 1762 } 1763 1764 intel_crtc = to_intel_crtc(crtc); 1765 if (!intel_crtc_active(crtc)) { 1766 DRM_DEBUG_KMS("crtc not active for PSR\n"); 1767 return false; 1768 } 1769 1770 obj = to_intel_framebuffer(crtc->fb)->obj; 1771 if (obj->tiling_mode != I915_TILING_X || 1772 obj->fence_reg == I915_FENCE_REG_NONE) { 1773 DRM_DEBUG_KMS("PSR condition failed: fb not tiled or fenced\n"); 1774 return false; 1775 } 1776 1777 if (I915_READ(SPRCTL(intel_crtc->pipe)) & SPRITE_ENABLE) { 1778 DRM_DEBUG_KMS("PSR condition failed: Sprite is Enabled\n"); 1779 return false; 1780 } 1781 1782 if (I915_READ(HSW_STEREO_3D_CTL(intel_crtc->config.cpu_transcoder)) & 1783 S3D_ENABLE) { 1784 DRM_DEBUG_KMS("PSR condition failed: Stereo 3D is Enabled\n"); 1785 return false; 1786 } 1787 1788 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) { 1789 DRM_DEBUG_KMS("PSR condition failed: Interlaced is Enabled\n"); 1790 return false; 1791 } 1792 1793 dev_priv->psr.source_ok = true; 1794 return true; 1795} 1796 1797static void intel_edp_psr_do_enable(struct intel_dp *intel_dp) 1798{ 1799 struct drm_device *dev = intel_dp_to_dev(intel_dp); 1800 1801 if (!intel_edp_psr_match_conditions(intel_dp) || 1802 intel_edp_is_psr_enabled(dev)) 1803 return; 1804 1805 /* Setup PSR once */ 1806 intel_edp_psr_setup(intel_dp); 1807 1808 /* Enable PSR on the panel */ 1809 intel_edp_psr_enable_sink(intel_dp); 1810 1811 /* Enable PSR on the host */ 1812 intel_edp_psr_enable_source(intel_dp); 1813} 1814 1815void intel_edp_psr_enable(struct intel_dp *intel_dp) 1816{ 1817 struct drm_device *dev = intel_dp_to_dev(intel_dp); 1818 1819 if (intel_edp_psr_match_conditions(intel_dp) && 1820 !intel_edp_is_psr_enabled(dev)) 1821 intel_edp_psr_do_enable(intel_dp); 1822} 1823 1824void intel_edp_psr_disable(struct intel_dp *intel_dp) 1825{ 1826 struct drm_device *dev = intel_dp_to_dev(intel_dp); 1827 struct drm_i915_private *dev_priv = dev->dev_private; 1828 1829 if (!intel_edp_is_psr_enabled(dev)) 1830 return; 1831 1832 I915_WRITE(EDP_PSR_CTL(dev), 1833 I915_READ(EDP_PSR_CTL(dev)) & ~EDP_PSR_ENABLE); 1834 1835 /* Wait till PSR is idle */ 1836 if (_wait_for((I915_READ(EDP_PSR_STATUS_CTL(dev)) & 1837 EDP_PSR_STATUS_STATE_MASK) == 0, 2000, 10)) 1838 DRM_ERROR("Timed out waiting for PSR Idle State\n"); 1839} 1840 1841void intel_edp_psr_update(struct drm_device *dev) 1842{ 1843 struct intel_encoder *encoder; 1844 struct intel_dp *intel_dp = NULL; 1845 1846 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) 1847 if (encoder->type == INTEL_OUTPUT_EDP) { 1848 intel_dp = enc_to_intel_dp(&encoder->base); 1849 1850 if (!is_edp_psr(dev)) 1851 return; 1852 1853 if (!intel_edp_psr_match_conditions(intel_dp)) 1854 intel_edp_psr_disable(intel_dp); 1855 else 1856 if (!intel_edp_is_psr_enabled(dev)) 1857 intel_edp_psr_do_enable(intel_dp); 1858 } 1859} 1860 1861static void intel_disable_dp(struct intel_encoder *encoder) 1862{ 1863 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); 1864 enum port port = dp_to_dig_port(intel_dp)->port; 1865 struct drm_device *dev = encoder->base.dev; 1866 1867 /* Make sure the panel is off before trying to change the mode. But also 1868 * ensure that we have vdd while we switch off the panel. */ 1869 edp_panel_vdd_on(intel_dp); 1870 intel_edp_backlight_off(intel_dp); 1871 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF); 1872 intel_edp_panel_off(intel_dp); 1873 edp_panel_vdd_off(intel_dp, true); 1874 1875 /* cpu edp my only be disable _after_ the cpu pipe/plane is disabled. */ 1876 if (!(port == PORT_A || IS_VALLEYVIEW(dev))) 1877 intel_dp_link_down(intel_dp); 1878} 1879 1880static void intel_post_disable_dp(struct intel_encoder *encoder) 1881{ 1882 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); 1883 enum port port = dp_to_dig_port(intel_dp)->port; 1884 struct drm_device *dev = encoder->base.dev; 1885 1886 if (port == PORT_A || IS_VALLEYVIEW(dev)) { 1887 intel_dp_link_down(intel_dp); 1888 if (!IS_VALLEYVIEW(dev)) 1889 ironlake_edp_pll_off(intel_dp); 1890 } 1891} 1892 1893static void intel_enable_dp(struct intel_encoder *encoder) 1894{ 1895 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); 1896 struct drm_device *dev = encoder->base.dev; 1897 struct drm_i915_private *dev_priv = dev->dev_private; 1898 uint32_t dp_reg = I915_READ(intel_dp->output_reg); 1899 1900 if (WARN_ON(dp_reg & DP_PORT_EN)) 1901 return; 1902 1903 edp_panel_vdd_on(intel_dp); 1904 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON); 1905 intel_dp_start_link_train(intel_dp); 1906 intel_edp_panel_on(intel_dp); 1907 edp_panel_vdd_off(intel_dp, true); 1908 intel_dp_complete_link_train(intel_dp); 1909 intel_dp_stop_link_train(intel_dp); 1910} 1911 1912static void g4x_enable_dp(struct intel_encoder *encoder) 1913{ 1914 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); 1915 1916 intel_enable_dp(encoder); 1917 intel_edp_backlight_on(intel_dp); 1918} 1919 1920static void vlv_enable_dp(struct intel_encoder *encoder) 1921{ 1922 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); 1923 1924 intel_edp_backlight_on(intel_dp); 1925} 1926 1927static void g4x_pre_enable_dp(struct intel_encoder *encoder) 1928{ 1929 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); 1930 struct intel_digital_port *dport = dp_to_dig_port(intel_dp); 1931 1932 if (dport->port == PORT_A) 1933 ironlake_edp_pll_on(intel_dp); 1934} 1935 1936static void vlv_pre_enable_dp(struct intel_encoder *encoder) 1937{ 1938 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); 1939 struct intel_digital_port *dport = dp_to_dig_port(intel_dp); 1940 struct drm_device *dev = encoder->base.dev; 1941 struct drm_i915_private *dev_priv = dev->dev_private; 1942 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc); 1943 enum dpio_channel port = vlv_dport_to_channel(dport); 1944 int pipe = intel_crtc->pipe; 1945 struct edp_power_seq power_seq; 1946 u32 val; 1947 1948 mutex_lock(&dev_priv->dpio_lock); 1949 1950 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(port)); 1951 val = 0; 1952 if (pipe) 1953 val |= (1<<21); 1954 else 1955 val &= ~(1<<21); 1956 val |= 0x001000c4; 1957 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW8(port), val); 1958 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW14(port), 0x00760018); 1959 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW23(port), 0x00400888); 1960 1961 mutex_unlock(&dev_priv->dpio_lock); 1962 1963 if (is_edp(intel_dp)) { 1964 /* init power sequencer on this pipe and port */ 1965 intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq); 1966 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp, 1967 &power_seq); 1968 } 1969 1970 intel_enable_dp(encoder); 1971 1972 vlv_wait_port_ready(dev_priv, dport); 1973} 1974 1975static void vlv_dp_pre_pll_enable(struct intel_encoder *encoder) 1976{ 1977 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base); 1978 struct drm_device *dev = encoder->base.dev; 1979 struct drm_i915_private *dev_priv = dev->dev_private; 1980 struct intel_crtc *intel_crtc = 1981 to_intel_crtc(encoder->base.crtc); 1982 enum dpio_channel port = vlv_dport_to_channel(dport); 1983 int pipe = intel_crtc->pipe; 1984 1985 /* Program Tx lane resets to default */ 1986 mutex_lock(&dev_priv->dpio_lock); 1987 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port), 1988 DPIO_PCS_TX_LANE2_RESET | 1989 DPIO_PCS_TX_LANE1_RESET); 1990 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port), 1991 DPIO_PCS_CLK_CRI_RXEB_EIOS_EN | 1992 DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN | 1993 (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT) | 1994 DPIO_PCS_CLK_SOFT_RESET); 1995 1996 /* Fix up inter-pair skew failure */ 1997 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW12(port), 0x00750f00); 1998 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW11(port), 0x00001500); 1999 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW14(port), 0x40400000); 2000 mutex_unlock(&dev_priv->dpio_lock); 2001} 2002 2003/* 2004 * Native read with retry for link status and receiver capability reads for 2005 * cases where the sink may still be asleep. 2006 * 2007 * Sinks are *supposed* to come up within 1ms from an off state, but we're also 2008 * supposed to retry 3 times per the spec. 2009 */ 2010static ssize_t 2011intel_dp_dpcd_read_wake(struct drm_dp_aux *aux, unsigned int offset, 2012 void *buffer, size_t size) 2013{ 2014 ssize_t ret; 2015 int i; 2016 2017 for (i = 0; i < 3; i++) { 2018 ret = drm_dp_dpcd_read(aux, offset, buffer, size); 2019 if (ret == size) 2020 return ret; 2021 msleep(1); 2022 } 2023 2024 return ret; 2025} 2026 2027/* 2028 * Fetch AUX CH registers 0x202 - 0x207 which contain 2029 * link status information 2030 */ 2031static bool 2032intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE]) 2033{ 2034 return intel_dp_dpcd_read_wake(&intel_dp->aux, 2035 DP_LANE0_1_STATUS, 2036 link_status, 2037 DP_LINK_STATUS_SIZE) == DP_LINK_STATUS_SIZE; 2038} 2039 2040/* 2041 * These are source-specific values; current Intel hardware supports 2042 * a maximum voltage of 800mV and a maximum pre-emphasis of 6dB 2043 */ 2044 2045static uint8_t 2046intel_dp_voltage_max(struct intel_dp *intel_dp) 2047{ 2048 struct drm_device *dev = intel_dp_to_dev(intel_dp); 2049 enum port port = dp_to_dig_port(intel_dp)->port; 2050 2051 if (IS_VALLEYVIEW(dev) || IS_BROADWELL(dev)) 2052 return DP_TRAIN_VOLTAGE_SWING_1200; 2053 else if (IS_GEN7(dev) && port == PORT_A) 2054 return DP_TRAIN_VOLTAGE_SWING_800; 2055 else if (HAS_PCH_CPT(dev) && port != PORT_A) 2056 return DP_TRAIN_VOLTAGE_SWING_1200; 2057 else 2058 return DP_TRAIN_VOLTAGE_SWING_800; 2059} 2060 2061static uint8_t 2062intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing) 2063{ 2064 struct drm_device *dev = intel_dp_to_dev(intel_dp); 2065 enum port port = dp_to_dig_port(intel_dp)->port; 2066 2067 if (IS_BROADWELL(dev)) { 2068 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) { 2069 case DP_TRAIN_VOLTAGE_SWING_400: 2070 case DP_TRAIN_VOLTAGE_SWING_600: 2071 return DP_TRAIN_PRE_EMPHASIS_6; 2072 case DP_TRAIN_VOLTAGE_SWING_800: 2073 return DP_TRAIN_PRE_EMPHASIS_3_5; 2074 case DP_TRAIN_VOLTAGE_SWING_1200: 2075 default: 2076 return DP_TRAIN_PRE_EMPHASIS_0; 2077 } 2078 } else if (IS_HASWELL(dev)) { 2079 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) { 2080 case DP_TRAIN_VOLTAGE_SWING_400: 2081 return DP_TRAIN_PRE_EMPHASIS_9_5; 2082 case DP_TRAIN_VOLTAGE_SWING_600: 2083 return DP_TRAIN_PRE_EMPHASIS_6; 2084 case DP_TRAIN_VOLTAGE_SWING_800: 2085 return DP_TRAIN_PRE_EMPHASIS_3_5; 2086 case DP_TRAIN_VOLTAGE_SWING_1200: 2087 default: 2088 return DP_TRAIN_PRE_EMPHASIS_0; 2089 } 2090 } else if (IS_VALLEYVIEW(dev)) { 2091 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) { 2092 case DP_TRAIN_VOLTAGE_SWING_400: 2093 return DP_TRAIN_PRE_EMPHASIS_9_5; 2094 case DP_TRAIN_VOLTAGE_SWING_600: 2095 return DP_TRAIN_PRE_EMPHASIS_6; 2096 case DP_TRAIN_VOLTAGE_SWING_800: 2097 return DP_TRAIN_PRE_EMPHASIS_3_5; 2098 case DP_TRAIN_VOLTAGE_SWING_1200: 2099 default: 2100 return DP_TRAIN_PRE_EMPHASIS_0; 2101 } 2102 } else if (IS_GEN7(dev) && port == PORT_A) { 2103 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) { 2104 case DP_TRAIN_VOLTAGE_SWING_400: 2105 return DP_TRAIN_PRE_EMPHASIS_6; 2106 case DP_TRAIN_VOLTAGE_SWING_600: 2107 case DP_TRAIN_VOLTAGE_SWING_800: 2108 return DP_TRAIN_PRE_EMPHASIS_3_5; 2109 default: 2110 return DP_TRAIN_PRE_EMPHASIS_0; 2111 } 2112 } else { 2113 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) { 2114 case DP_TRAIN_VOLTAGE_SWING_400: 2115 return DP_TRAIN_PRE_EMPHASIS_6; 2116 case DP_TRAIN_VOLTAGE_SWING_600: 2117 return DP_TRAIN_PRE_EMPHASIS_6; 2118 case DP_TRAIN_VOLTAGE_SWING_800: 2119 return DP_TRAIN_PRE_EMPHASIS_3_5; 2120 case DP_TRAIN_VOLTAGE_SWING_1200: 2121 default: 2122 return DP_TRAIN_PRE_EMPHASIS_0; 2123 } 2124 } 2125} 2126 2127static uint32_t intel_vlv_signal_levels(struct intel_dp *intel_dp) 2128{ 2129 struct drm_device *dev = intel_dp_to_dev(intel_dp); 2130 struct drm_i915_private *dev_priv = dev->dev_private; 2131 struct intel_digital_port *dport = dp_to_dig_port(intel_dp); 2132 struct intel_crtc *intel_crtc = 2133 to_intel_crtc(dport->base.base.crtc); 2134 unsigned long demph_reg_value, preemph_reg_value, 2135 uniqtranscale_reg_value; 2136 uint8_t train_set = intel_dp->train_set[0]; 2137 enum dpio_channel port = vlv_dport_to_channel(dport); 2138 int pipe = intel_crtc->pipe; 2139 2140 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) { 2141 case DP_TRAIN_PRE_EMPHASIS_0: 2142 preemph_reg_value = 0x0004000; 2143 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { 2144 case DP_TRAIN_VOLTAGE_SWING_400: 2145 demph_reg_value = 0x2B405555; 2146 uniqtranscale_reg_value = 0x552AB83A; 2147 break; 2148 case DP_TRAIN_VOLTAGE_SWING_600: 2149 demph_reg_value = 0x2B404040; 2150 uniqtranscale_reg_value = 0x5548B83A; 2151 break; 2152 case DP_TRAIN_VOLTAGE_SWING_800: 2153 demph_reg_value = 0x2B245555; 2154 uniqtranscale_reg_value = 0x5560B83A; 2155 break; 2156 case DP_TRAIN_VOLTAGE_SWING_1200: 2157 demph_reg_value = 0x2B405555; 2158 uniqtranscale_reg_value = 0x5598DA3A; 2159 break; 2160 default: 2161 return 0; 2162 } 2163 break; 2164 case DP_TRAIN_PRE_EMPHASIS_3_5: 2165 preemph_reg_value = 0x0002000; 2166 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { 2167 case DP_TRAIN_VOLTAGE_SWING_400: 2168 demph_reg_value = 0x2B404040; 2169 uniqtranscale_reg_value = 0x5552B83A; 2170 break; 2171 case DP_TRAIN_VOLTAGE_SWING_600: 2172 demph_reg_value = 0x2B404848; 2173 uniqtranscale_reg_value = 0x5580B83A; 2174 break; 2175 case DP_TRAIN_VOLTAGE_SWING_800: 2176 demph_reg_value = 0x2B404040; 2177 uniqtranscale_reg_value = 0x55ADDA3A; 2178 break; 2179 default: 2180 return 0; 2181 } 2182 break; 2183 case DP_TRAIN_PRE_EMPHASIS_6: 2184 preemph_reg_value = 0x0000000; 2185 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { 2186 case DP_TRAIN_VOLTAGE_SWING_400: 2187 demph_reg_value = 0x2B305555; 2188 uniqtranscale_reg_value = 0x5570B83A; 2189 break; 2190 case DP_TRAIN_VOLTAGE_SWING_600: 2191 demph_reg_value = 0x2B2B4040; 2192 uniqtranscale_reg_value = 0x55ADDA3A; 2193 break; 2194 default: 2195 return 0; 2196 } 2197 break; 2198 case DP_TRAIN_PRE_EMPHASIS_9_5: 2199 preemph_reg_value = 0x0006000; 2200 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { 2201 case DP_TRAIN_VOLTAGE_SWING_400: 2202 demph_reg_value = 0x1B405555; 2203 uniqtranscale_reg_value = 0x55ADDA3A; 2204 break; 2205 default: 2206 return 0; 2207 } 2208 break; 2209 default: 2210 return 0; 2211 } 2212 2213 mutex_lock(&dev_priv->dpio_lock); 2214 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x00000000); 2215 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW4(port), demph_reg_value); 2216 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(port), 2217 uniqtranscale_reg_value); 2218 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(port), 0x0C782040); 2219 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW11(port), 0x00030000); 2220 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), preemph_reg_value); 2221 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x80000000); 2222 mutex_unlock(&dev_priv->dpio_lock); 2223 2224 return 0; 2225} 2226 2227static void 2228intel_get_adjust_train(struct intel_dp *intel_dp, 2229 const uint8_t link_status[DP_LINK_STATUS_SIZE]) 2230{ 2231 uint8_t v = 0; 2232 uint8_t p = 0; 2233 int lane; 2234 uint8_t voltage_max; 2235 uint8_t preemph_max; 2236 2237 for (lane = 0; lane < intel_dp->lane_count; lane++) { 2238 uint8_t this_v = drm_dp_get_adjust_request_voltage(link_status, lane); 2239 uint8_t this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane); 2240 2241 if (this_v > v) 2242 v = this_v; 2243 if (this_p > p) 2244 p = this_p; 2245 } 2246 2247 voltage_max = intel_dp_voltage_max(intel_dp); 2248 if (v >= voltage_max) 2249 v = voltage_max | DP_TRAIN_MAX_SWING_REACHED; 2250 2251 preemph_max = intel_dp_pre_emphasis_max(intel_dp, v); 2252 if (p >= preemph_max) 2253 p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED; 2254 2255 for (lane = 0; lane < 4; lane++) 2256 intel_dp->train_set[lane] = v | p; 2257} 2258 2259static uint32_t 2260intel_gen4_signal_levels(uint8_t train_set) 2261{ 2262 uint32_t signal_levels = 0; 2263 2264 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { 2265 case DP_TRAIN_VOLTAGE_SWING_400: 2266 default: 2267 signal_levels |= DP_VOLTAGE_0_4; 2268 break; 2269 case DP_TRAIN_VOLTAGE_SWING_600: 2270 signal_levels |= DP_VOLTAGE_0_6; 2271 break; 2272 case DP_TRAIN_VOLTAGE_SWING_800: 2273 signal_levels |= DP_VOLTAGE_0_8; 2274 break; 2275 case DP_TRAIN_VOLTAGE_SWING_1200: 2276 signal_levels |= DP_VOLTAGE_1_2; 2277 break; 2278 } 2279 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) { 2280 case DP_TRAIN_PRE_EMPHASIS_0: 2281 default: 2282 signal_levels |= DP_PRE_EMPHASIS_0; 2283 break; 2284 case DP_TRAIN_PRE_EMPHASIS_3_5: 2285 signal_levels |= DP_PRE_EMPHASIS_3_5; 2286 break; 2287 case DP_TRAIN_PRE_EMPHASIS_6: 2288 signal_levels |= DP_PRE_EMPHASIS_6; 2289 break; 2290 case DP_TRAIN_PRE_EMPHASIS_9_5: 2291 signal_levels |= DP_PRE_EMPHASIS_9_5; 2292 break; 2293 } 2294 return signal_levels; 2295} 2296 2297/* Gen6's DP voltage swing and pre-emphasis control */ 2298static uint32_t 2299intel_gen6_edp_signal_levels(uint8_t train_set) 2300{ 2301 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK | 2302 DP_TRAIN_PRE_EMPHASIS_MASK); 2303 switch (signal_levels) { 2304 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0: 2305 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0: 2306 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B; 2307 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5: 2308 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B; 2309 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6: 2310 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6: 2311 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B; 2312 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5: 2313 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5: 2314 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B; 2315 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0: 2316 case DP_TRAIN_VOLTAGE_SWING_1200 | DP_TRAIN_PRE_EMPHASIS_0: 2317 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B; 2318 default: 2319 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:" 2320 "0x%x\n", signal_levels); 2321 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B; 2322 } 2323} 2324 2325/* Gen7's DP voltage swing and pre-emphasis control */ 2326static uint32_t 2327intel_gen7_edp_signal_levels(uint8_t train_set) 2328{ 2329 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK | 2330 DP_TRAIN_PRE_EMPHASIS_MASK); 2331 switch (signal_levels) { 2332 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0: 2333 return EDP_LINK_TRAIN_400MV_0DB_IVB; 2334 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5: 2335 return EDP_LINK_TRAIN_400MV_3_5DB_IVB; 2336 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6: 2337 return EDP_LINK_TRAIN_400MV_6DB_IVB; 2338 2339 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0: 2340 return EDP_LINK_TRAIN_600MV_0DB_IVB; 2341 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5: 2342 return EDP_LINK_TRAIN_600MV_3_5DB_IVB; 2343 2344 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0: 2345 return EDP_LINK_TRAIN_800MV_0DB_IVB; 2346 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5: 2347 return EDP_LINK_TRAIN_800MV_3_5DB_IVB; 2348 2349 default: 2350 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:" 2351 "0x%x\n", signal_levels); 2352 return EDP_LINK_TRAIN_500MV_0DB_IVB; 2353 } 2354} 2355 2356/* Gen7.5's (HSW) DP voltage swing and pre-emphasis control */ 2357static uint32_t 2358intel_hsw_signal_levels(uint8_t train_set) 2359{ 2360 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK | 2361 DP_TRAIN_PRE_EMPHASIS_MASK); 2362 switch (signal_levels) { 2363 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0: 2364 return DDI_BUF_EMP_400MV_0DB_HSW; 2365 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5: 2366 return DDI_BUF_EMP_400MV_3_5DB_HSW; 2367 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6: 2368 return DDI_BUF_EMP_400MV_6DB_HSW; 2369 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_9_5: 2370 return DDI_BUF_EMP_400MV_9_5DB_HSW; 2371 2372 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0: 2373 return DDI_BUF_EMP_600MV_0DB_HSW; 2374 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5: 2375 return DDI_BUF_EMP_600MV_3_5DB_HSW; 2376 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6: 2377 return DDI_BUF_EMP_600MV_6DB_HSW; 2378 2379 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0: 2380 return DDI_BUF_EMP_800MV_0DB_HSW; 2381 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5: 2382 return DDI_BUF_EMP_800MV_3_5DB_HSW; 2383 default: 2384 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:" 2385 "0x%x\n", signal_levels); 2386 return DDI_BUF_EMP_400MV_0DB_HSW; 2387 } 2388} 2389 2390static uint32_t 2391intel_bdw_signal_levels(uint8_t train_set) 2392{ 2393 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK | 2394 DP_TRAIN_PRE_EMPHASIS_MASK); 2395 switch (signal_levels) { 2396 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0: 2397 return DDI_BUF_EMP_400MV_0DB_BDW; /* Sel0 */ 2398 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5: 2399 return DDI_BUF_EMP_400MV_3_5DB_BDW; /* Sel1 */ 2400 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6: 2401 return DDI_BUF_EMP_400MV_6DB_BDW; /* Sel2 */ 2402 2403 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0: 2404 return DDI_BUF_EMP_600MV_0DB_BDW; /* Sel3 */ 2405 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5: 2406 return DDI_BUF_EMP_600MV_3_5DB_BDW; /* Sel4 */ 2407 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6: 2408 return DDI_BUF_EMP_600MV_6DB_BDW; /* Sel5 */ 2409 2410 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0: 2411 return DDI_BUF_EMP_800MV_0DB_BDW; /* Sel6 */ 2412 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5: 2413 return DDI_BUF_EMP_800MV_3_5DB_BDW; /* Sel7 */ 2414 2415 case DP_TRAIN_VOLTAGE_SWING_1200 | DP_TRAIN_PRE_EMPHASIS_0: 2416 return DDI_BUF_EMP_1200MV_0DB_BDW; /* Sel8 */ 2417 2418 default: 2419 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:" 2420 "0x%x\n", signal_levels); 2421 return DDI_BUF_EMP_400MV_0DB_BDW; /* Sel0 */ 2422 } 2423} 2424 2425/* Properly updates "DP" with the correct signal levels. */ 2426static void 2427intel_dp_set_signal_levels(struct intel_dp *intel_dp, uint32_t *DP) 2428{ 2429 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 2430 enum port port = intel_dig_port->port; 2431 struct drm_device *dev = intel_dig_port->base.base.dev; 2432 uint32_t signal_levels, mask; 2433 uint8_t train_set = intel_dp->train_set[0]; 2434 2435 if (IS_BROADWELL(dev)) { 2436 signal_levels = intel_bdw_signal_levels(train_set); 2437 mask = DDI_BUF_EMP_MASK; 2438 } else if (IS_HASWELL(dev)) { 2439 signal_levels = intel_hsw_signal_levels(train_set); 2440 mask = DDI_BUF_EMP_MASK; 2441 } else if (IS_VALLEYVIEW(dev)) { 2442 signal_levels = intel_vlv_signal_levels(intel_dp); 2443 mask = 0; 2444 } else if (IS_GEN7(dev) && port == PORT_A) { 2445 signal_levels = intel_gen7_edp_signal_levels(train_set); 2446 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_IVB; 2447 } else if (IS_GEN6(dev) && port == PORT_A) { 2448 signal_levels = intel_gen6_edp_signal_levels(train_set); 2449 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB; 2450 } else { 2451 signal_levels = intel_gen4_signal_levels(train_set); 2452 mask = DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK; 2453 } 2454 2455 DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels); 2456 2457 *DP = (*DP & ~mask) | signal_levels; 2458} 2459 2460static bool 2461intel_dp_set_link_train(struct intel_dp *intel_dp, 2462 uint32_t *DP, 2463 uint8_t dp_train_pat) 2464{ 2465 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 2466 struct drm_device *dev = intel_dig_port->base.base.dev; 2467 struct drm_i915_private *dev_priv = dev->dev_private; 2468 enum port port = intel_dig_port->port; 2469 uint8_t buf[sizeof(intel_dp->train_set) + 1]; 2470 int ret, len; 2471 2472 if (HAS_DDI(dev)) { 2473 uint32_t temp = I915_READ(DP_TP_CTL(port)); 2474 2475 if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE) 2476 temp |= DP_TP_CTL_SCRAMBLE_DISABLE; 2477 else 2478 temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE; 2479 2480 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK; 2481 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) { 2482 case DP_TRAINING_PATTERN_DISABLE: 2483 temp |= DP_TP_CTL_LINK_TRAIN_NORMAL; 2484 2485 break; 2486 case DP_TRAINING_PATTERN_1: 2487 temp |= DP_TP_CTL_LINK_TRAIN_PAT1; 2488 break; 2489 case DP_TRAINING_PATTERN_2: 2490 temp |= DP_TP_CTL_LINK_TRAIN_PAT2; 2491 break; 2492 case DP_TRAINING_PATTERN_3: 2493 temp |= DP_TP_CTL_LINK_TRAIN_PAT3; 2494 break; 2495 } 2496 I915_WRITE(DP_TP_CTL(port), temp); 2497 2498 } else if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) { 2499 *DP &= ~DP_LINK_TRAIN_MASK_CPT; 2500 2501 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) { 2502 case DP_TRAINING_PATTERN_DISABLE: 2503 *DP |= DP_LINK_TRAIN_OFF_CPT; 2504 break; 2505 case DP_TRAINING_PATTERN_1: 2506 *DP |= DP_LINK_TRAIN_PAT_1_CPT; 2507 break; 2508 case DP_TRAINING_PATTERN_2: 2509 *DP |= DP_LINK_TRAIN_PAT_2_CPT; 2510 break; 2511 case DP_TRAINING_PATTERN_3: 2512 DRM_ERROR("DP training pattern 3 not supported\n"); 2513 *DP |= DP_LINK_TRAIN_PAT_2_CPT; 2514 break; 2515 } 2516 2517 } else { 2518 *DP &= ~DP_LINK_TRAIN_MASK; 2519 2520 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) { 2521 case DP_TRAINING_PATTERN_DISABLE: 2522 *DP |= DP_LINK_TRAIN_OFF; 2523 break; 2524 case DP_TRAINING_PATTERN_1: 2525 *DP |= DP_LINK_TRAIN_PAT_1; 2526 break; 2527 case DP_TRAINING_PATTERN_2: 2528 *DP |= DP_LINK_TRAIN_PAT_2; 2529 break; 2530 case DP_TRAINING_PATTERN_3: 2531 DRM_ERROR("DP training pattern 3 not supported\n"); 2532 *DP |= DP_LINK_TRAIN_PAT_2; 2533 break; 2534 } 2535 } 2536 2537 I915_WRITE(intel_dp->output_reg, *DP); 2538 POSTING_READ(intel_dp->output_reg); 2539 2540 buf[0] = dp_train_pat; 2541 if ((dp_train_pat & DP_TRAINING_PATTERN_MASK) == 2542 DP_TRAINING_PATTERN_DISABLE) { 2543 /* don't write DP_TRAINING_LANEx_SET on disable */ 2544 len = 1; 2545 } else { 2546 /* DP_TRAINING_LANEx_SET follow DP_TRAINING_PATTERN_SET */ 2547 memcpy(buf + 1, intel_dp->train_set, intel_dp->lane_count); 2548 len = intel_dp->lane_count + 1; 2549 } 2550 2551 ret = drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_PATTERN_SET, 2552 buf, len); 2553 2554 return ret == len; 2555} 2556 2557static bool 2558intel_dp_reset_link_train(struct intel_dp *intel_dp, uint32_t *DP, 2559 uint8_t dp_train_pat) 2560{ 2561 memset(intel_dp->train_set, 0, sizeof(intel_dp->train_set)); 2562 intel_dp_set_signal_levels(intel_dp, DP); 2563 return intel_dp_set_link_train(intel_dp, DP, dp_train_pat); 2564} 2565 2566static bool 2567intel_dp_update_link_train(struct intel_dp *intel_dp, uint32_t *DP, 2568 const uint8_t link_status[DP_LINK_STATUS_SIZE]) 2569{ 2570 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 2571 struct drm_device *dev = intel_dig_port->base.base.dev; 2572 struct drm_i915_private *dev_priv = dev->dev_private; 2573 int ret; 2574 2575 intel_get_adjust_train(intel_dp, link_status); 2576 intel_dp_set_signal_levels(intel_dp, DP); 2577 2578 I915_WRITE(intel_dp->output_reg, *DP); 2579 POSTING_READ(intel_dp->output_reg); 2580 2581 ret = drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_LANE0_SET, 2582 intel_dp->train_set, intel_dp->lane_count); 2583 2584 return ret == intel_dp->lane_count; 2585} 2586 2587static void intel_dp_set_idle_link_train(struct intel_dp *intel_dp) 2588{ 2589 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 2590 struct drm_device *dev = intel_dig_port->base.base.dev; 2591 struct drm_i915_private *dev_priv = dev->dev_private; 2592 enum port port = intel_dig_port->port; 2593 uint32_t val; 2594 2595 if (!HAS_DDI(dev)) 2596 return; 2597 2598 val = I915_READ(DP_TP_CTL(port)); 2599 val &= ~DP_TP_CTL_LINK_TRAIN_MASK; 2600 val |= DP_TP_CTL_LINK_TRAIN_IDLE; 2601 I915_WRITE(DP_TP_CTL(port), val); 2602 2603 /* 2604 * On PORT_A we can have only eDP in SST mode. There the only reason 2605 * we need to set idle transmission mode is to work around a HW issue 2606 * where we enable the pipe while not in idle link-training mode. 2607 * In this case there is requirement to wait for a minimum number of 2608 * idle patterns to be sent. 2609 */ 2610 if (port == PORT_A) 2611 return; 2612 2613 if (wait_for((I915_READ(DP_TP_STATUS(port)) & DP_TP_STATUS_IDLE_DONE), 2614 1)) 2615 DRM_ERROR("Timed out waiting for DP idle patterns\n"); 2616} 2617 2618/* Enable corresponding port and start training pattern 1 */ 2619void 2620intel_dp_start_link_train(struct intel_dp *intel_dp) 2621{ 2622 struct drm_encoder *encoder = &dp_to_dig_port(intel_dp)->base.base; 2623 struct drm_device *dev = encoder->dev; 2624 int i; 2625 uint8_t voltage; 2626 int voltage_tries, loop_tries; 2627 uint32_t DP = intel_dp->DP; 2628 uint8_t link_config[2]; 2629 2630 if (HAS_DDI(dev)) 2631 intel_ddi_prepare_link_retrain(encoder); 2632 2633 /* Write the link configuration data */ 2634 link_config[0] = intel_dp->link_bw; 2635 link_config[1] = intel_dp->lane_count; 2636 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd)) 2637 link_config[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN; 2638 drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_BW_SET, link_config, 2); 2639 2640 link_config[0] = 0; 2641 link_config[1] = DP_SET_ANSI_8B10B; 2642 drm_dp_dpcd_write(&intel_dp->aux, DP_DOWNSPREAD_CTRL, link_config, 2); 2643 2644 DP |= DP_PORT_EN; 2645 2646 /* clock recovery */ 2647 if (!intel_dp_reset_link_train(intel_dp, &DP, 2648 DP_TRAINING_PATTERN_1 | 2649 DP_LINK_SCRAMBLING_DISABLE)) { 2650 DRM_ERROR("failed to enable link training\n"); 2651 return; 2652 } 2653 2654 voltage = 0xff; 2655 voltage_tries = 0; 2656 loop_tries = 0; 2657 for (;;) { 2658 uint8_t link_status[DP_LINK_STATUS_SIZE]; 2659 2660 drm_dp_link_train_clock_recovery_delay(intel_dp->dpcd); 2661 if (!intel_dp_get_link_status(intel_dp, link_status)) { 2662 DRM_ERROR("failed to get link status\n"); 2663 break; 2664 } 2665 2666 if (drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) { 2667 DRM_DEBUG_KMS("clock recovery OK\n"); 2668 break; 2669 } 2670 2671 /* Check to see if we've tried the max voltage */ 2672 for (i = 0; i < intel_dp->lane_count; i++) 2673 if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0) 2674 break; 2675 if (i == intel_dp->lane_count) { 2676 ++loop_tries; 2677 if (loop_tries == 5) { 2678 DRM_ERROR("too many full retries, give up\n"); 2679 break; 2680 } 2681 intel_dp_reset_link_train(intel_dp, &DP, 2682 DP_TRAINING_PATTERN_1 | 2683 DP_LINK_SCRAMBLING_DISABLE); 2684 voltage_tries = 0; 2685 continue; 2686 } 2687 2688 /* Check to see if we've tried the same voltage 5 times */ 2689 if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) { 2690 ++voltage_tries; 2691 if (voltage_tries == 5) { 2692 DRM_ERROR("too many voltage retries, give up\n"); 2693 break; 2694 } 2695 } else 2696 voltage_tries = 0; 2697 voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK; 2698 2699 /* Update training set as requested by target */ 2700 if (!intel_dp_update_link_train(intel_dp, &DP, link_status)) { 2701 DRM_ERROR("failed to update link training\n"); 2702 break; 2703 } 2704 } 2705 2706 intel_dp->DP = DP; 2707} 2708 2709void 2710intel_dp_complete_link_train(struct intel_dp *intel_dp) 2711{ 2712 bool channel_eq = false; 2713 int tries, cr_tries; 2714 uint32_t DP = intel_dp->DP; 2715 uint32_t training_pattern = DP_TRAINING_PATTERN_2; 2716 2717 /* Training Pattern 3 for HBR2 ot 1.2 devices that support it*/ 2718 if (intel_dp->link_bw == DP_LINK_BW_5_4 || intel_dp->use_tps3) 2719 training_pattern = DP_TRAINING_PATTERN_3; 2720 2721 /* channel equalization */ 2722 if (!intel_dp_set_link_train(intel_dp, &DP, 2723 training_pattern | 2724 DP_LINK_SCRAMBLING_DISABLE)) { 2725 DRM_ERROR("failed to start channel equalization\n"); 2726 return; 2727 } 2728 2729 tries = 0; 2730 cr_tries = 0; 2731 channel_eq = false; 2732 for (;;) { 2733 uint8_t link_status[DP_LINK_STATUS_SIZE]; 2734 2735 if (cr_tries > 5) { 2736 DRM_ERROR("failed to train DP, aborting\n"); 2737 break; 2738 } 2739 2740 drm_dp_link_train_channel_eq_delay(intel_dp->dpcd); 2741 if (!intel_dp_get_link_status(intel_dp, link_status)) { 2742 DRM_ERROR("failed to get link status\n"); 2743 break; 2744 } 2745 2746 /* Make sure clock is still ok */ 2747 if (!drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) { 2748 intel_dp_start_link_train(intel_dp); 2749 intel_dp_set_link_train(intel_dp, &DP, 2750 training_pattern | 2751 DP_LINK_SCRAMBLING_DISABLE); 2752 cr_tries++; 2753 continue; 2754 } 2755 2756 if (drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) { 2757 channel_eq = true; 2758 break; 2759 } 2760 2761 /* Try 5 times, then try clock recovery if that fails */ 2762 if (tries > 5) { 2763 intel_dp_link_down(intel_dp); 2764 intel_dp_start_link_train(intel_dp); 2765 intel_dp_set_link_train(intel_dp, &DP, 2766 training_pattern | 2767 DP_LINK_SCRAMBLING_DISABLE); 2768 tries = 0; 2769 cr_tries++; 2770 continue; 2771 } 2772 2773 /* Update training set as requested by target */ 2774 if (!intel_dp_update_link_train(intel_dp, &DP, link_status)) { 2775 DRM_ERROR("failed to update link training\n"); 2776 break; 2777 } 2778 ++tries; 2779 } 2780 2781 intel_dp_set_idle_link_train(intel_dp); 2782 2783 intel_dp->DP = DP; 2784 2785 if (channel_eq) 2786 DRM_DEBUG_KMS("Channel EQ done. DP Training successful\n"); 2787 2788} 2789 2790void intel_dp_stop_link_train(struct intel_dp *intel_dp) 2791{ 2792 intel_dp_set_link_train(intel_dp, &intel_dp->DP, 2793 DP_TRAINING_PATTERN_DISABLE); 2794} 2795 2796static void 2797intel_dp_link_down(struct intel_dp *intel_dp) 2798{ 2799 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 2800 enum port port = intel_dig_port->port; 2801 struct drm_device *dev = intel_dig_port->base.base.dev; 2802 struct drm_i915_private *dev_priv = dev->dev_private; 2803 struct intel_crtc *intel_crtc = 2804 to_intel_crtc(intel_dig_port->base.base.crtc); 2805 uint32_t DP = intel_dp->DP; 2806 2807 /* 2808 * DDI code has a strict mode set sequence and we should try to respect 2809 * it, otherwise we might hang the machine in many different ways. So we 2810 * really should be disabling the port only on a complete crtc_disable 2811 * sequence. This function is just called under two conditions on DDI 2812 * code: 2813 * - Link train failed while doing crtc_enable, and on this case we 2814 * really should respect the mode set sequence and wait for a 2815 * crtc_disable. 2816 * - Someone turned the monitor off and intel_dp_check_link_status 2817 * called us. We don't need to disable the whole port on this case, so 2818 * when someone turns the monitor on again, 2819 * intel_ddi_prepare_link_retrain will take care of redoing the link 2820 * train. 2821 */ 2822 if (HAS_DDI(dev)) 2823 return; 2824 2825 if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0)) 2826 return; 2827 2828 DRM_DEBUG_KMS("\n"); 2829 2830 if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) { 2831 DP &= ~DP_LINK_TRAIN_MASK_CPT; 2832 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT); 2833 } else { 2834 DP &= ~DP_LINK_TRAIN_MASK; 2835 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE); 2836 } 2837 POSTING_READ(intel_dp->output_reg); 2838 2839 /* We don't really know why we're doing this */ 2840 intel_wait_for_vblank(dev, intel_crtc->pipe); 2841 2842 if (HAS_PCH_IBX(dev) && 2843 I915_READ(intel_dp->output_reg) & DP_PIPEB_SELECT) { 2844 struct drm_crtc *crtc = intel_dig_port->base.base.crtc; 2845 2846 /* Hardware workaround: leaving our transcoder select 2847 * set to transcoder B while it's off will prevent the 2848 * corresponding HDMI output on transcoder A. 2849 * 2850 * Combine this with another hardware workaround: 2851 * transcoder select bit can only be cleared while the 2852 * port is enabled. 2853 */ 2854 DP &= ~DP_PIPEB_SELECT; 2855 I915_WRITE(intel_dp->output_reg, DP); 2856 2857 /* Changes to enable or select take place the vblank 2858 * after being written. 2859 */ 2860 if (WARN_ON(crtc == NULL)) { 2861 /* We should never try to disable a port without a crtc 2862 * attached. For paranoia keep the code around for a 2863 * bit. */ 2864 POSTING_READ(intel_dp->output_reg); 2865 msleep(50); 2866 } else 2867 intel_wait_for_vblank(dev, intel_crtc->pipe); 2868 } 2869 2870 DP &= ~DP_AUDIO_OUTPUT_ENABLE; 2871 I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN); 2872 POSTING_READ(intel_dp->output_reg); 2873 msleep(intel_dp->panel_power_down_delay); 2874} 2875 2876static bool 2877intel_dp_get_dpcd(struct intel_dp *intel_dp) 2878{ 2879 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 2880 struct drm_device *dev = dig_port->base.base.dev; 2881 struct drm_i915_private *dev_priv = dev->dev_private; 2882 2883 char dpcd_hex_dump[sizeof(intel_dp->dpcd) * 3]; 2884 2885 if (intel_dp_dpcd_read_wake(&intel_dp->aux, 0x000, intel_dp->dpcd, 2886 sizeof(intel_dp->dpcd)) < 0) 2887 return false; /* aux transfer failed */ 2888 2889 hex_dump_to_buffer(intel_dp->dpcd, sizeof(intel_dp->dpcd), 2890 32, 1, dpcd_hex_dump, sizeof(dpcd_hex_dump), false); 2891 DRM_DEBUG_KMS("DPCD: %s\n", dpcd_hex_dump); 2892 2893 if (intel_dp->dpcd[DP_DPCD_REV] == 0) 2894 return false; /* DPCD not present */ 2895 2896 /* Check if the panel supports PSR */ 2897 memset(intel_dp->psr_dpcd, 0, sizeof(intel_dp->psr_dpcd)); 2898 if (is_edp(intel_dp)) { 2899 intel_dp_dpcd_read_wake(&intel_dp->aux, DP_PSR_SUPPORT, 2900 intel_dp->psr_dpcd, 2901 sizeof(intel_dp->psr_dpcd)); 2902 if (intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED) { 2903 dev_priv->psr.sink_support = true; 2904 DRM_DEBUG_KMS("Detected EDP PSR Panel.\n"); 2905 } 2906 } 2907 2908 /* Training Pattern 3 support */ 2909 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x12 && 2910 intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_TPS3_SUPPORTED) { 2911 intel_dp->use_tps3 = true; 2912 DRM_DEBUG_KMS("Displayport TPS3 supported"); 2913 } else 2914 intel_dp->use_tps3 = false; 2915 2916 if (!(intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] & 2917 DP_DWN_STRM_PORT_PRESENT)) 2918 return true; /* native DP sink */ 2919 2920 if (intel_dp->dpcd[DP_DPCD_REV] == 0x10) 2921 return true; /* no per-port downstream info */ 2922 2923 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_DOWNSTREAM_PORT_0, 2924 intel_dp->downstream_ports, 2925 DP_MAX_DOWNSTREAM_PORTS) < 0) 2926 return false; /* downstream port status fetch failed */ 2927 2928 return true; 2929} 2930 2931static void 2932intel_dp_probe_oui(struct intel_dp *intel_dp) 2933{ 2934 u8 buf[3]; 2935 2936 if (!(intel_dp->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT)) 2937 return; 2938 2939 edp_panel_vdd_on(intel_dp); 2940 2941 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_SINK_OUI, buf, 3) == 3) 2942 DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n", 2943 buf[0], buf[1], buf[2]); 2944 2945 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_BRANCH_OUI, buf, 3) == 3) 2946 DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n", 2947 buf[0], buf[1], buf[2]); 2948 2949 edp_panel_vdd_off(intel_dp, false); 2950} 2951 2952int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc) 2953{ 2954 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 2955 struct drm_device *dev = intel_dig_port->base.base.dev; 2956 struct intel_crtc *intel_crtc = 2957 to_intel_crtc(intel_dig_port->base.base.crtc); 2958 u8 buf[1]; 2959 2960 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK_MISC, buf) < 0) 2961 return -EAGAIN; 2962 2963 if (!(buf[0] & DP_TEST_CRC_SUPPORTED)) 2964 return -ENOTTY; 2965 2966 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK, 2967 DP_TEST_SINK_START) < 0) 2968 return -EAGAIN; 2969 2970 /* Wait 2 vblanks to be sure we will have the correct CRC value */ 2971 intel_wait_for_vblank(dev, intel_crtc->pipe); 2972 intel_wait_for_vblank(dev, intel_crtc->pipe); 2973 2974 if (drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_CRC_R_CR, crc, 6) < 0) 2975 return -EAGAIN; 2976 2977 drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK, 0); 2978 return 0; 2979} 2980 2981static bool 2982intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector) 2983{ 2984 return intel_dp_dpcd_read_wake(&intel_dp->aux, 2985 DP_DEVICE_SERVICE_IRQ_VECTOR, 2986 sink_irq_vector, 1) == 1; 2987} 2988 2989static void 2990intel_dp_handle_test_request(struct intel_dp *intel_dp) 2991{ 2992 /* NAK by default */ 2993 drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_RESPONSE, DP_TEST_NAK); 2994} 2995 2996/* 2997 * According to DP spec 2998 * 5.1.2: 2999 * 1. Read DPCD 3000 * 2. Configure link according to Receiver Capabilities 3001 * 3. Use Link Training from 2.5.3.3 and 3.5.1.3 3002 * 4. Check link status on receipt of hot-plug interrupt 3003 */ 3004 3005void 3006intel_dp_check_link_status(struct intel_dp *intel_dp) 3007{ 3008 struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base; 3009 u8 sink_irq_vector; 3010 u8 link_status[DP_LINK_STATUS_SIZE]; 3011 3012 if (!intel_encoder->connectors_active) 3013 return; 3014 3015 if (WARN_ON(!intel_encoder->base.crtc)) 3016 return; 3017 3018 /* Try to read receiver status if the link appears to be up */ 3019 if (!intel_dp_get_link_status(intel_dp, link_status)) { 3020 return; 3021 } 3022 3023 /* Now read the DPCD to see if it's actually running */ 3024 if (!intel_dp_get_dpcd(intel_dp)) { 3025 return; 3026 } 3027 3028 /* Try to read the source of the interrupt */ 3029 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 && 3030 intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) { 3031 /* Clear interrupt source */ 3032 drm_dp_dpcd_writeb(&intel_dp->aux, 3033 DP_DEVICE_SERVICE_IRQ_VECTOR, 3034 sink_irq_vector); 3035 3036 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST) 3037 intel_dp_handle_test_request(intel_dp); 3038 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ)) 3039 DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n"); 3040 } 3041 3042 if (!drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) { 3043 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n", 3044 drm_get_encoder_name(&intel_encoder->base)); 3045 intel_dp_start_link_train(intel_dp); 3046 intel_dp_complete_link_train(intel_dp); 3047 intel_dp_stop_link_train(intel_dp); 3048 } 3049} 3050 3051/* XXX this is probably wrong for multiple downstream ports */ 3052static enum drm_connector_status 3053intel_dp_detect_dpcd(struct intel_dp *intel_dp) 3054{ 3055 uint8_t *dpcd = intel_dp->dpcd; 3056 uint8_t type; 3057 3058 if (!intel_dp_get_dpcd(intel_dp)) 3059 return connector_status_disconnected; 3060 3061 /* if there's no downstream port, we're done */ 3062 if (!(dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT)) 3063 return connector_status_connected; 3064 3065 /* If we're HPD-aware, SINK_COUNT changes dynamically */ 3066 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 && 3067 intel_dp->downstream_ports[0] & DP_DS_PORT_HPD) { 3068 uint8_t reg; 3069 3070 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_SINK_COUNT, 3071 ®, 1) < 0) 3072 return connector_status_unknown; 3073 3074 return DP_GET_SINK_COUNT(reg) ? connector_status_connected 3075 : connector_status_disconnected; 3076 } 3077 3078 /* If no HPD, poke DDC gently */ 3079 if (drm_probe_ddc(&intel_dp->adapter)) 3080 return connector_status_connected; 3081 3082 /* Well we tried, say unknown for unreliable port types */ 3083 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) { 3084 type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK; 3085 if (type == DP_DS_PORT_TYPE_VGA || 3086 type == DP_DS_PORT_TYPE_NON_EDID) 3087 return connector_status_unknown; 3088 } else { 3089 type = intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] & 3090 DP_DWN_STRM_PORT_TYPE_MASK; 3091 if (type == DP_DWN_STRM_PORT_TYPE_ANALOG || 3092 type == DP_DWN_STRM_PORT_TYPE_OTHER) 3093 return connector_status_unknown; 3094 } 3095 3096 /* Anything else is out of spec, warn and ignore */ 3097 DRM_DEBUG_KMS("Broken DP branch device, ignoring\n"); 3098 return connector_status_disconnected; 3099} 3100 3101static enum drm_connector_status 3102ironlake_dp_detect(struct intel_dp *intel_dp) 3103{ 3104 struct drm_device *dev = intel_dp_to_dev(intel_dp); 3105 struct drm_i915_private *dev_priv = dev->dev_private; 3106 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 3107 enum drm_connector_status status; 3108 3109 /* Can't disconnect eDP, but you can close the lid... */ 3110 if (is_edp(intel_dp)) { 3111 status = intel_panel_detect(dev); 3112 if (status == connector_status_unknown) 3113 status = connector_status_connected; 3114 return status; 3115 } 3116 3117 if (!ibx_digital_port_connected(dev_priv, intel_dig_port)) 3118 return connector_status_disconnected; 3119 3120 return intel_dp_detect_dpcd(intel_dp); 3121} 3122 3123static enum drm_connector_status 3124g4x_dp_detect(struct intel_dp *intel_dp) 3125{ 3126 struct drm_device *dev = intel_dp_to_dev(intel_dp); 3127 struct drm_i915_private *dev_priv = dev->dev_private; 3128 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 3129 uint32_t bit; 3130 3131 /* Can't disconnect eDP, but you can close the lid... */ 3132 if (is_edp(intel_dp)) { 3133 enum drm_connector_status status; 3134 3135 status = intel_panel_detect(dev); 3136 if (status == connector_status_unknown) 3137 status = connector_status_connected; 3138 return status; 3139 } 3140 3141 if (IS_VALLEYVIEW(dev)) { 3142 switch (intel_dig_port->port) { 3143 case PORT_B: 3144 bit = PORTB_HOTPLUG_LIVE_STATUS_VLV; 3145 break; 3146 case PORT_C: 3147 bit = PORTC_HOTPLUG_LIVE_STATUS_VLV; 3148 break; 3149 case PORT_D: 3150 bit = PORTD_HOTPLUG_LIVE_STATUS_VLV; 3151 break; 3152 default: 3153 return connector_status_unknown; 3154 } 3155 } else { 3156 switch (intel_dig_port->port) { 3157 case PORT_B: 3158 bit = PORTB_HOTPLUG_LIVE_STATUS_G4X; 3159 break; 3160 case PORT_C: 3161 bit = PORTC_HOTPLUG_LIVE_STATUS_G4X; 3162 break; 3163 case PORT_D: 3164 bit = PORTD_HOTPLUG_LIVE_STATUS_G4X; 3165 break; 3166 default: 3167 return connector_status_unknown; 3168 } 3169 } 3170 3171 if ((I915_READ(PORT_HOTPLUG_STAT) & bit) == 0) 3172 return connector_status_disconnected; 3173 3174 return intel_dp_detect_dpcd(intel_dp); 3175} 3176 3177static struct edid * 3178intel_dp_get_edid(struct drm_connector *connector, struct i2c_adapter *adapter) 3179{ 3180 struct intel_connector *intel_connector = to_intel_connector(connector); 3181 3182 /* use cached edid if we have one */ 3183 if (intel_connector->edid) { 3184 /* invalid edid */ 3185 if (IS_ERR(intel_connector->edid)) 3186 return NULL; 3187 3188 return drm_edid_duplicate(intel_connector->edid); 3189 } 3190 3191 return drm_get_edid(connector, adapter); 3192} 3193 3194static int 3195intel_dp_get_edid_modes(struct drm_connector *connector, struct i2c_adapter *adapter) 3196{ 3197 struct intel_connector *intel_connector = to_intel_connector(connector); 3198 3199 /* use cached edid if we have one */ 3200 if (intel_connector->edid) { 3201 /* invalid edid */ 3202 if (IS_ERR(intel_connector->edid)) 3203 return 0; 3204 3205 return intel_connector_update_modes(connector, 3206 intel_connector->edid); 3207 } 3208 3209 return intel_ddc_get_modes(connector, adapter); 3210} 3211 3212static enum drm_connector_status 3213intel_dp_detect(struct drm_connector *connector, bool force) 3214{ 3215 struct intel_dp *intel_dp = intel_attached_dp(connector); 3216 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 3217 struct intel_encoder *intel_encoder = &intel_dig_port->base; 3218 struct drm_device *dev = connector->dev; 3219 struct drm_i915_private *dev_priv = dev->dev_private; 3220 enum drm_connector_status status; 3221 enum intel_display_power_domain power_domain; 3222 struct edid *edid = NULL; 3223 3224 intel_runtime_pm_get(dev_priv); 3225 3226 power_domain = intel_display_port_power_domain(intel_encoder); 3227 intel_display_power_get(dev_priv, power_domain); 3228 3229 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", 3230 connector->base.id, drm_get_connector_name(connector)); 3231 3232 intel_dp->has_audio = false; 3233 3234 if (HAS_PCH_SPLIT(dev)) 3235 status = ironlake_dp_detect(intel_dp); 3236 else 3237 status = g4x_dp_detect(intel_dp); 3238 3239 if (status != connector_status_connected) 3240 goto out; 3241 3242 intel_dp_probe_oui(intel_dp); 3243 3244 if (intel_dp->force_audio != HDMI_AUDIO_AUTO) { 3245 intel_dp->has_audio = (intel_dp->force_audio == HDMI_AUDIO_ON); 3246 } else { 3247 edid = intel_dp_get_edid(connector, &intel_dp->adapter); 3248 if (edid) { 3249 intel_dp->has_audio = drm_detect_monitor_audio(edid); 3250 kfree(edid); 3251 } 3252 } 3253 3254 if (intel_encoder->type != INTEL_OUTPUT_EDP) 3255 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT; 3256 status = connector_status_connected; 3257 3258out: 3259 intel_display_power_put(dev_priv, power_domain); 3260 3261 intel_runtime_pm_put(dev_priv); 3262 3263 return status; 3264} 3265 3266static int intel_dp_get_modes(struct drm_connector *connector) 3267{ 3268 struct intel_dp *intel_dp = intel_attached_dp(connector); 3269 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 3270 struct intel_encoder *intel_encoder = &intel_dig_port->base; 3271 struct intel_connector *intel_connector = to_intel_connector(connector); 3272 struct drm_device *dev = connector->dev; 3273 struct drm_i915_private *dev_priv = dev->dev_private; 3274 enum intel_display_power_domain power_domain; 3275 int ret; 3276 3277 /* We should parse the EDID data and find out if it has an audio sink 3278 */ 3279 3280 power_domain = intel_display_port_power_domain(intel_encoder); 3281 intel_display_power_get(dev_priv, power_domain); 3282 3283 ret = intel_dp_get_edid_modes(connector, &intel_dp->adapter); 3284 intel_display_power_put(dev_priv, power_domain); 3285 if (ret) 3286 return ret; 3287 3288 /* if eDP has no EDID, fall back to fixed mode */ 3289 if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) { 3290 struct drm_display_mode *mode; 3291 mode = drm_mode_duplicate(dev, 3292 intel_connector->panel.fixed_mode); 3293 if (mode) { 3294 drm_mode_probed_add(connector, mode); 3295 return 1; 3296 } 3297 } 3298 return 0; 3299} 3300 3301static bool 3302intel_dp_detect_audio(struct drm_connector *connector) 3303{ 3304 struct intel_dp *intel_dp = intel_attached_dp(connector); 3305 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 3306 struct intel_encoder *intel_encoder = &intel_dig_port->base; 3307 struct drm_device *dev = connector->dev; 3308 struct drm_i915_private *dev_priv = dev->dev_private; 3309 enum intel_display_power_domain power_domain; 3310 struct edid *edid; 3311 bool has_audio = false; 3312 3313 power_domain = intel_display_port_power_domain(intel_encoder); 3314 intel_display_power_get(dev_priv, power_domain); 3315 3316 edid = intel_dp_get_edid(connector, &intel_dp->adapter); 3317 if (edid) { 3318 has_audio = drm_detect_monitor_audio(edid); 3319 kfree(edid); 3320 } 3321 3322 intel_display_power_put(dev_priv, power_domain); 3323 3324 return has_audio; 3325} 3326 3327static int 3328intel_dp_set_property(struct drm_connector *connector, 3329 struct drm_property *property, 3330 uint64_t val) 3331{ 3332 struct drm_i915_private *dev_priv = connector->dev->dev_private; 3333 struct intel_connector *intel_connector = to_intel_connector(connector); 3334 struct intel_encoder *intel_encoder = intel_attached_encoder(connector); 3335 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base); 3336 int ret; 3337 3338 ret = drm_object_property_set_value(&connector->base, property, val); 3339 if (ret) 3340 return ret; 3341 3342 if (property == dev_priv->force_audio_property) { 3343 int i = val; 3344 bool has_audio; 3345 3346 if (i == intel_dp->force_audio) 3347 return 0; 3348 3349 intel_dp->force_audio = i; 3350 3351 if (i == HDMI_AUDIO_AUTO) 3352 has_audio = intel_dp_detect_audio(connector); 3353 else 3354 has_audio = (i == HDMI_AUDIO_ON); 3355 3356 if (has_audio == intel_dp->has_audio) 3357 return 0; 3358 3359 intel_dp->has_audio = has_audio; 3360 goto done; 3361 } 3362 3363 if (property == dev_priv->broadcast_rgb_property) { 3364 bool old_auto = intel_dp->color_range_auto; 3365 uint32_t old_range = intel_dp->color_range; 3366 3367 switch (val) { 3368 case INTEL_BROADCAST_RGB_AUTO: 3369 intel_dp->color_range_auto = true; 3370 break; 3371 case INTEL_BROADCAST_RGB_FULL: 3372 intel_dp->color_range_auto = false; 3373 intel_dp->color_range = 0; 3374 break; 3375 case INTEL_BROADCAST_RGB_LIMITED: 3376 intel_dp->color_range_auto = false; 3377 intel_dp->color_range = DP_COLOR_RANGE_16_235; 3378 break; 3379 default: 3380 return -EINVAL; 3381 } 3382 3383 if (old_auto == intel_dp->color_range_auto && 3384 old_range == intel_dp->color_range) 3385 return 0; 3386 3387 goto done; 3388 } 3389 3390 if (is_edp(intel_dp) && 3391 property == connector->dev->mode_config.scaling_mode_property) { 3392 if (val == DRM_MODE_SCALE_NONE) { 3393 DRM_DEBUG_KMS("no scaling not supported\n"); 3394 return -EINVAL; 3395 } 3396 3397 if (intel_connector->panel.fitting_mode == val) { 3398 /* the eDP scaling property is not changed */ 3399 return 0; 3400 } 3401 intel_connector->panel.fitting_mode = val; 3402 3403 goto done; 3404 } 3405 3406 return -EINVAL; 3407 3408done: 3409 if (intel_encoder->base.crtc) 3410 intel_crtc_restore_mode(intel_encoder->base.crtc); 3411 3412 return 0; 3413} 3414 3415static void 3416intel_dp_connector_destroy(struct drm_connector *connector) 3417{ 3418 struct intel_connector *intel_connector = to_intel_connector(connector); 3419 3420 if (!IS_ERR_OR_NULL(intel_connector->edid)) 3421 kfree(intel_connector->edid); 3422 3423 /* Can't call is_edp() since the encoder may have been destroyed 3424 * already. */ 3425 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) 3426 intel_panel_fini(&intel_connector->panel); 3427 3428 drm_connector_cleanup(connector); 3429 kfree(connector); 3430} 3431 3432void intel_dp_encoder_destroy(struct drm_encoder *encoder) 3433{ 3434 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); 3435 struct intel_dp *intel_dp = &intel_dig_port->dp; 3436 struct drm_device *dev = intel_dp_to_dev(intel_dp); 3437 3438 i2c_del_adapter(&intel_dp->adapter); 3439 drm_encoder_cleanup(encoder); 3440 if (is_edp(intel_dp)) { 3441 cancel_delayed_work_sync(&intel_dp->panel_vdd_work); 3442 mutex_lock(&dev->mode_config.mutex); 3443 edp_panel_vdd_off_sync(intel_dp); 3444 mutex_unlock(&dev->mode_config.mutex); 3445 } 3446 kfree(intel_dig_port); 3447} 3448 3449static const struct drm_connector_funcs intel_dp_connector_funcs = { 3450 .dpms = intel_connector_dpms, 3451 .detect = intel_dp_detect, 3452 .fill_modes = drm_helper_probe_single_connector_modes, 3453 .set_property = intel_dp_set_property, 3454 .destroy = intel_dp_connector_destroy, 3455}; 3456 3457static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = { 3458 .get_modes = intel_dp_get_modes, 3459 .mode_valid = intel_dp_mode_valid, 3460 .best_encoder = intel_best_encoder, 3461}; 3462 3463static const struct drm_encoder_funcs intel_dp_enc_funcs = { 3464 .destroy = intel_dp_encoder_destroy, 3465}; 3466 3467static void 3468intel_dp_hot_plug(struct intel_encoder *intel_encoder) 3469{ 3470 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base); 3471 3472 intel_dp_check_link_status(intel_dp); 3473} 3474 3475/* Return which DP Port should be selected for Transcoder DP control */ 3476int 3477intel_trans_dp_port_sel(struct drm_crtc *crtc) 3478{ 3479 struct drm_device *dev = crtc->dev; 3480 struct intel_encoder *intel_encoder; 3481 struct intel_dp *intel_dp; 3482 3483 for_each_encoder_on_crtc(dev, crtc, intel_encoder) { 3484 intel_dp = enc_to_intel_dp(&intel_encoder->base); 3485 3486 if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT || 3487 intel_encoder->type == INTEL_OUTPUT_EDP) 3488 return intel_dp->output_reg; 3489 } 3490 3491 return -1; 3492} 3493 3494/* check the VBT to see whether the eDP is on DP-D port */ 3495bool intel_dp_is_edp(struct drm_device *dev, enum port port) 3496{ 3497 struct drm_i915_private *dev_priv = dev->dev_private; 3498 union child_device_config *p_child; 3499 int i; 3500 static const short port_mapping[] = { 3501 [PORT_B] = PORT_IDPB, 3502 [PORT_C] = PORT_IDPC, 3503 [PORT_D] = PORT_IDPD, 3504 }; 3505 3506 if (port == PORT_A) 3507 return true; 3508 3509 if (!dev_priv->vbt.child_dev_num) 3510 return false; 3511 3512 for (i = 0; i < dev_priv->vbt.child_dev_num; i++) { 3513 p_child = dev_priv->vbt.child_dev + i; 3514 3515 if (p_child->common.dvo_port == port_mapping[port] && 3516 (p_child->common.device_type & DEVICE_TYPE_eDP_BITS) == 3517 (DEVICE_TYPE_eDP & DEVICE_TYPE_eDP_BITS)) 3518 return true; 3519 } 3520 return false; 3521} 3522 3523static void 3524intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector) 3525{ 3526 struct intel_connector *intel_connector = to_intel_connector(connector); 3527 3528 intel_attach_force_audio_property(connector); 3529 intel_attach_broadcast_rgb_property(connector); 3530 intel_dp->color_range_auto = true; 3531 3532 if (is_edp(intel_dp)) { 3533 drm_mode_create_scaling_mode_property(connector->dev); 3534 drm_object_attach_property( 3535 &connector->base, 3536 connector->dev->mode_config.scaling_mode_property, 3537 DRM_MODE_SCALE_ASPECT); 3538 intel_connector->panel.fitting_mode = DRM_MODE_SCALE_ASPECT; 3539 } 3540} 3541 3542static void intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp) 3543{ 3544 intel_dp->last_power_cycle = jiffies; 3545 intel_dp->last_power_on = jiffies; 3546 intel_dp->last_backlight_off = jiffies; 3547} 3548 3549static void 3550intel_dp_init_panel_power_sequencer(struct drm_device *dev, 3551 struct intel_dp *intel_dp, 3552 struct edp_power_seq *out) 3553{ 3554 struct drm_i915_private *dev_priv = dev->dev_private; 3555 struct edp_power_seq cur, vbt, spec, final; 3556 u32 pp_on, pp_off, pp_div, pp; 3557 int pp_ctrl_reg, pp_on_reg, pp_off_reg, pp_div_reg; 3558 3559 if (HAS_PCH_SPLIT(dev)) { 3560 pp_ctrl_reg = PCH_PP_CONTROL; 3561 pp_on_reg = PCH_PP_ON_DELAYS; 3562 pp_off_reg = PCH_PP_OFF_DELAYS; 3563 pp_div_reg = PCH_PP_DIVISOR; 3564 } else { 3565 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp); 3566 3567 pp_ctrl_reg = VLV_PIPE_PP_CONTROL(pipe); 3568 pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe); 3569 pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe); 3570 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe); 3571 } 3572 3573 /* Workaround: Need to write PP_CONTROL with the unlock key as 3574 * the very first thing. */ 3575 pp = ironlake_get_pp_control(intel_dp); 3576 I915_WRITE(pp_ctrl_reg, pp); 3577 3578 pp_on = I915_READ(pp_on_reg); 3579 pp_off = I915_READ(pp_off_reg); 3580 pp_div = I915_READ(pp_div_reg); 3581 3582 /* Pull timing values out of registers */ 3583 cur.t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >> 3584 PANEL_POWER_UP_DELAY_SHIFT; 3585 3586 cur.t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >> 3587 PANEL_LIGHT_ON_DELAY_SHIFT; 3588 3589 cur.t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >> 3590 PANEL_LIGHT_OFF_DELAY_SHIFT; 3591 3592 cur.t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >> 3593 PANEL_POWER_DOWN_DELAY_SHIFT; 3594 3595 cur.t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >> 3596 PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000; 3597 3598 DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n", 3599 cur.t1_t3, cur.t8, cur.t9, cur.t10, cur.t11_t12); 3600 3601 vbt = dev_priv->vbt.edp_pps; 3602 3603 /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of 3604 * our hw here, which are all in 100usec. */ 3605 spec.t1_t3 = 210 * 10; 3606 spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */ 3607 spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */ 3608 spec.t10 = 500 * 10; 3609 /* This one is special and actually in units of 100ms, but zero 3610 * based in the hw (so we need to add 100 ms). But the sw vbt 3611 * table multiplies it with 1000 to make it in units of 100usec, 3612 * too. */ 3613 spec.t11_t12 = (510 + 100) * 10; 3614 3615 DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n", 3616 vbt.t1_t3, vbt.t8, vbt.t9, vbt.t10, vbt.t11_t12); 3617 3618 /* Use the max of the register settings and vbt. If both are 3619 * unset, fall back to the spec limits. */ 3620#define assign_final(field) final.field = (max(cur.field, vbt.field) == 0 ? \ 3621 spec.field : \ 3622 max(cur.field, vbt.field)) 3623 assign_final(t1_t3); 3624 assign_final(t8); 3625 assign_final(t9); 3626 assign_final(t10); 3627 assign_final(t11_t12); 3628#undef assign_final 3629 3630#define get_delay(field) (DIV_ROUND_UP(final.field, 10)) 3631 intel_dp->panel_power_up_delay = get_delay(t1_t3); 3632 intel_dp->backlight_on_delay = get_delay(t8); 3633 intel_dp->backlight_off_delay = get_delay(t9); 3634 intel_dp->panel_power_down_delay = get_delay(t10); 3635 intel_dp->panel_power_cycle_delay = get_delay(t11_t12); 3636#undef get_delay 3637 3638 DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n", 3639 intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay, 3640 intel_dp->panel_power_cycle_delay); 3641 3642 DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n", 3643 intel_dp->backlight_on_delay, intel_dp->backlight_off_delay); 3644 3645 if (out) 3646 *out = final; 3647} 3648 3649static void 3650intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev, 3651 struct intel_dp *intel_dp, 3652 struct edp_power_seq *seq) 3653{ 3654 struct drm_i915_private *dev_priv = dev->dev_private; 3655 u32 pp_on, pp_off, pp_div, port_sel = 0; 3656 int div = HAS_PCH_SPLIT(dev) ? intel_pch_rawclk(dev) : intel_hrawclk(dev); 3657 int pp_on_reg, pp_off_reg, pp_div_reg; 3658 3659 if (HAS_PCH_SPLIT(dev)) { 3660 pp_on_reg = PCH_PP_ON_DELAYS; 3661 pp_off_reg = PCH_PP_OFF_DELAYS; 3662 pp_div_reg = PCH_PP_DIVISOR; 3663 } else { 3664 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp); 3665 3666 pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe); 3667 pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe); 3668 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe); 3669 } 3670 3671 /* 3672 * And finally store the new values in the power sequencer. The 3673 * backlight delays are set to 1 because we do manual waits on them. For 3674 * T8, even BSpec recommends doing it. For T9, if we don't do this, 3675 * we'll end up waiting for the backlight off delay twice: once when we 3676 * do the manual sleep, and once when we disable the panel and wait for 3677 * the PP_STATUS bit to become zero. 3678 */ 3679 pp_on = (seq->t1_t3 << PANEL_POWER_UP_DELAY_SHIFT) | 3680 (1 << PANEL_LIGHT_ON_DELAY_SHIFT); 3681 pp_off = (1 << PANEL_LIGHT_OFF_DELAY_SHIFT) | 3682 (seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT); 3683 /* Compute the divisor for the pp clock, simply match the Bspec 3684 * formula. */ 3685 pp_div = ((100 * div)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT; 3686 pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000) 3687 << PANEL_POWER_CYCLE_DELAY_SHIFT); 3688 3689 /* Haswell doesn't have any port selection bits for the panel 3690 * power sequencer any more. */ 3691 if (IS_VALLEYVIEW(dev)) { 3692 if (dp_to_dig_port(intel_dp)->port == PORT_B) 3693 port_sel = PANEL_PORT_SELECT_DPB_VLV; 3694 else 3695 port_sel = PANEL_PORT_SELECT_DPC_VLV; 3696 } else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) { 3697 if (dp_to_dig_port(intel_dp)->port == PORT_A) 3698 port_sel = PANEL_PORT_SELECT_DPA; 3699 else 3700 port_sel = PANEL_PORT_SELECT_DPD; 3701 } 3702 3703 pp_on |= port_sel; 3704 3705 I915_WRITE(pp_on_reg, pp_on); 3706 I915_WRITE(pp_off_reg, pp_off); 3707 I915_WRITE(pp_div_reg, pp_div); 3708 3709 DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n", 3710 I915_READ(pp_on_reg), 3711 I915_READ(pp_off_reg), 3712 I915_READ(pp_div_reg)); 3713} 3714 3715static bool intel_edp_init_connector(struct intel_dp *intel_dp, 3716 struct intel_connector *intel_connector, 3717 struct edp_power_seq *power_seq) 3718{ 3719 struct drm_connector *connector = &intel_connector->base; 3720 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 3721 struct drm_device *dev = intel_dig_port->base.base.dev; 3722 struct drm_i915_private *dev_priv = dev->dev_private; 3723 struct drm_display_mode *fixed_mode = NULL; 3724 bool has_dpcd; 3725 struct drm_display_mode *scan; 3726 struct edid *edid; 3727 3728 if (!is_edp(intel_dp)) 3729 return true; 3730 3731 /* Cache DPCD and EDID for edp. */ 3732 edp_panel_vdd_on(intel_dp); 3733 has_dpcd = intel_dp_get_dpcd(intel_dp); 3734 edp_panel_vdd_off(intel_dp, false); 3735 3736 if (has_dpcd) { 3737 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) 3738 dev_priv->no_aux_handshake = 3739 intel_dp->dpcd[DP_MAX_DOWNSPREAD] & 3740 DP_NO_AUX_HANDSHAKE_LINK_TRAINING; 3741 } else { 3742 /* if this fails, presume the device is a ghost */ 3743 DRM_INFO("failed to retrieve link info, disabling eDP\n"); 3744 return false; 3745 } 3746 3747 /* We now know it's not a ghost, init power sequence regs. */ 3748 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp, power_seq); 3749 3750 edid = drm_get_edid(connector, &intel_dp->adapter); 3751 if (edid) { 3752 if (drm_add_edid_modes(connector, edid)) { 3753 drm_mode_connector_update_edid_property(connector, 3754 edid); 3755 drm_edid_to_eld(connector, edid); 3756 } else { 3757 kfree(edid); 3758 edid = ERR_PTR(-EINVAL); 3759 } 3760 } else { 3761 edid = ERR_PTR(-ENOENT); 3762 } 3763 intel_connector->edid = edid; 3764 3765 /* prefer fixed mode from EDID if available */ 3766 list_for_each_entry(scan, &connector->probed_modes, head) { 3767 if ((scan->type & DRM_MODE_TYPE_PREFERRED)) { 3768 fixed_mode = drm_mode_duplicate(dev, scan); 3769 break; 3770 } 3771 } 3772 3773 /* fallback to VBT if available for eDP */ 3774 if (!fixed_mode && dev_priv->vbt.lfp_lvds_vbt_mode) { 3775 fixed_mode = drm_mode_duplicate(dev, 3776 dev_priv->vbt.lfp_lvds_vbt_mode); 3777 if (fixed_mode) 3778 fixed_mode->type |= DRM_MODE_TYPE_PREFERRED; 3779 } 3780 3781 intel_panel_init(&intel_connector->panel, fixed_mode, NULL); 3782 intel_panel_setup_backlight(connector); 3783 3784 return true; 3785} 3786 3787bool 3788intel_dp_init_connector(struct intel_digital_port *intel_dig_port, 3789 struct intel_connector *intel_connector) 3790{ 3791 struct drm_connector *connector = &intel_connector->base; 3792 struct intel_dp *intel_dp = &intel_dig_port->dp; 3793 struct intel_encoder *intel_encoder = &intel_dig_port->base; 3794 struct drm_device *dev = intel_encoder->base.dev; 3795 struct drm_i915_private *dev_priv = dev->dev_private; 3796 enum port port = intel_dig_port->port; 3797 struct edp_power_seq power_seq = { 0 }; 3798 const char *name = NULL; 3799 int type, error; 3800 3801 /* intel_dp vfuncs */ 3802 if (IS_VALLEYVIEW(dev)) 3803 intel_dp->get_aux_clock_divider = vlv_get_aux_clock_divider; 3804 else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) 3805 intel_dp->get_aux_clock_divider = hsw_get_aux_clock_divider; 3806 else if (HAS_PCH_SPLIT(dev)) 3807 intel_dp->get_aux_clock_divider = ilk_get_aux_clock_divider; 3808 else 3809 intel_dp->get_aux_clock_divider = i9xx_get_aux_clock_divider; 3810 3811 intel_dp->get_aux_send_ctl = i9xx_get_aux_send_ctl; 3812 3813 /* Preserve the current hw state. */ 3814 intel_dp->DP = I915_READ(intel_dp->output_reg); 3815 intel_dp->attached_connector = intel_connector; 3816 3817 if (intel_dp_is_edp(dev, port)) 3818 type = DRM_MODE_CONNECTOR_eDP; 3819 else 3820 type = DRM_MODE_CONNECTOR_DisplayPort; 3821 3822 /* 3823 * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but 3824 * for DP the encoder type can be set by the caller to 3825 * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it. 3826 */ 3827 if (type == DRM_MODE_CONNECTOR_eDP) 3828 intel_encoder->type = INTEL_OUTPUT_EDP; 3829 3830 DRM_DEBUG_KMS("Adding %s connector on port %c\n", 3831 type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP", 3832 port_name(port)); 3833 3834 drm_connector_init(dev, connector, &intel_dp_connector_funcs, type); 3835 drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs); 3836 3837 connector->interlace_allowed = true; 3838 connector->doublescan_allowed = 0; 3839 3840 INIT_DELAYED_WORK(&intel_dp->panel_vdd_work, 3841 edp_panel_vdd_work); 3842 3843 intel_connector_attach_encoder(intel_connector, intel_encoder); 3844 drm_sysfs_connector_add(connector); 3845 3846 if (HAS_DDI(dev)) 3847 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state; 3848 else 3849 intel_connector->get_hw_state = intel_connector_get_hw_state; 3850 intel_connector->unregister = intel_dp_connector_unregister; 3851 3852 intel_dp->aux_ch_ctl_reg = intel_dp->output_reg + 0x10; 3853 if (HAS_DDI(dev)) { 3854 switch (intel_dig_port->port) { 3855 case PORT_A: 3856 intel_dp->aux_ch_ctl_reg = DPA_AUX_CH_CTL; 3857 break; 3858 case PORT_B: 3859 intel_dp->aux_ch_ctl_reg = PCH_DPB_AUX_CH_CTL; 3860 break; 3861 case PORT_C: 3862 intel_dp->aux_ch_ctl_reg = PCH_DPC_AUX_CH_CTL; 3863 break; 3864 case PORT_D: 3865 intel_dp->aux_ch_ctl_reg = PCH_DPD_AUX_CH_CTL; 3866 break; 3867 default: 3868 BUG(); 3869 } 3870 } 3871 3872 /* Set up the DDC bus. */ 3873 switch (port) { 3874 case PORT_A: 3875 intel_encoder->hpd_pin = HPD_PORT_A; 3876 name = "DPDDC-A"; 3877 break; 3878 case PORT_B: 3879 intel_encoder->hpd_pin = HPD_PORT_B; 3880 name = "DPDDC-B"; 3881 break; 3882 case PORT_C: 3883 intel_encoder->hpd_pin = HPD_PORT_C; 3884 name = "DPDDC-C"; 3885 break; 3886 case PORT_D: 3887 intel_encoder->hpd_pin = HPD_PORT_D; 3888 name = "DPDDC-D"; 3889 break; 3890 default: 3891 BUG(); 3892 } 3893 3894 if (is_edp(intel_dp)) { 3895 intel_dp_init_panel_power_timestamps(intel_dp); 3896 intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq); 3897 } 3898 3899 intel_dp_aux_init(intel_dp, intel_connector); 3900 3901 error = intel_dp_i2c_init(intel_dp, intel_connector, name); 3902 WARN(error, "intel_dp_i2c_init failed with error %d for port %c\n", 3903 error, port_name(port)); 3904 3905 intel_dp->psr_setup_done = false; 3906 3907 if (!intel_edp_init_connector(intel_dp, intel_connector, &power_seq)) { 3908 i2c_del_adapter(&intel_dp->adapter); 3909 if (is_edp(intel_dp)) { 3910 cancel_delayed_work_sync(&intel_dp->panel_vdd_work); 3911 mutex_lock(&dev->mode_config.mutex); 3912 edp_panel_vdd_off_sync(intel_dp); 3913 mutex_unlock(&dev->mode_config.mutex); 3914 } 3915 drm_sysfs_connector_remove(connector); 3916 drm_connector_cleanup(connector); 3917 return false; 3918 } 3919 3920 intel_dp_add_properties(intel_dp, connector); 3921 3922 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written 3923 * 0xd. Failure to do so will result in spurious interrupts being 3924 * generated on the port when a cable is not attached. 3925 */ 3926 if (IS_G4X(dev) && !IS_GM45(dev)) { 3927 u32 temp = I915_READ(PEG_BAND_GAP_DATA); 3928 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd); 3929 } 3930 3931 return true; 3932} 3933 3934void 3935intel_dp_init(struct drm_device *dev, int output_reg, enum port port) 3936{ 3937 struct intel_digital_port *intel_dig_port; 3938 struct intel_encoder *intel_encoder; 3939 struct drm_encoder *encoder; 3940 struct intel_connector *intel_connector; 3941 3942 intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL); 3943 if (!intel_dig_port) 3944 return; 3945 3946 intel_connector = kzalloc(sizeof(*intel_connector), GFP_KERNEL); 3947 if (!intel_connector) { 3948 kfree(intel_dig_port); 3949 return; 3950 } 3951 3952 intel_encoder = &intel_dig_port->base; 3953 encoder = &intel_encoder->base; 3954 3955 drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs, 3956 DRM_MODE_ENCODER_TMDS); 3957 3958 intel_encoder->compute_config = intel_dp_compute_config; 3959 intel_encoder->mode_set = intel_dp_mode_set; 3960 intel_encoder->disable = intel_disable_dp; 3961 intel_encoder->post_disable = intel_post_disable_dp; 3962 intel_encoder->get_hw_state = intel_dp_get_hw_state; 3963 intel_encoder->get_config = intel_dp_get_config; 3964 if (IS_VALLEYVIEW(dev)) { 3965 intel_encoder->pre_pll_enable = vlv_dp_pre_pll_enable; 3966 intel_encoder->pre_enable = vlv_pre_enable_dp; 3967 intel_encoder->enable = vlv_enable_dp; 3968 } else { 3969 intel_encoder->pre_enable = g4x_pre_enable_dp; 3970 intel_encoder->enable = g4x_enable_dp; 3971 } 3972 3973 intel_dig_port->port = port; 3974 intel_dig_port->dp.output_reg = output_reg; 3975 3976 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT; 3977 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2); 3978 intel_encoder->cloneable = false; 3979 intel_encoder->hot_plug = intel_dp_hot_plug; 3980 3981 if (!intel_dp_init_connector(intel_dig_port, intel_connector)) { 3982 drm_encoder_cleanup(encoder); 3983 kfree(intel_dig_port); 3984 kfree(intel_connector); 3985 } 3986} 3987