intel_dp.c revision 9de88e6e89a2222061af8e1448f6f346e3413fc8
1/* 2 * Copyright © 2008 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 * Authors: 24 * Keith Packard <keithp@keithp.com> 25 * 26 */ 27 28#include <linux/i2c.h> 29#include <linux/slab.h> 30#include "drmP.h" 31#include "drm.h" 32#include "drm_crtc.h" 33#include "drm_crtc_helper.h" 34#include "intel_drv.h" 35#include "i915_drm.h" 36#include "i915_drv.h" 37#include "drm_dp_helper.h" 38 39 40#define DP_LINK_STATUS_SIZE 6 41#define DP_LINK_CHECK_TIMEOUT (10 * 1000) 42 43#define DP_LINK_CONFIGURATION_SIZE 9 44 45struct intel_dp { 46 struct intel_encoder base; 47 uint32_t output_reg; 48 uint32_t DP; 49 uint8_t link_configuration[DP_LINK_CONFIGURATION_SIZE]; 50 bool has_audio; 51 int force_audio; 52 uint32_t color_range; 53 uint8_t link_bw; 54 uint8_t lane_count; 55 uint8_t dpcd[8]; 56 struct i2c_adapter adapter; 57 struct i2c_algo_dp_aux_data algo; 58 bool is_pch_edp; 59 uint8_t train_set[4]; 60 uint8_t link_status[DP_LINK_STATUS_SIZE]; 61}; 62 63/** 64 * is_edp - is the given port attached to an eDP panel (either CPU or PCH) 65 * @intel_dp: DP struct 66 * 67 * If a CPU or PCH DP output is attached to an eDP panel, this function 68 * will return true, and false otherwise. 69 */ 70static bool is_edp(struct intel_dp *intel_dp) 71{ 72 return intel_dp->base.type == INTEL_OUTPUT_EDP; 73} 74 75/** 76 * is_pch_edp - is the port on the PCH and attached to an eDP panel? 77 * @intel_dp: DP struct 78 * 79 * Returns true if the given DP struct corresponds to a PCH DP port attached 80 * to an eDP panel, false otherwise. Helpful for determining whether we 81 * may need FDI resources for a given DP output or not. 82 */ 83static bool is_pch_edp(struct intel_dp *intel_dp) 84{ 85 return intel_dp->is_pch_edp; 86} 87 88static struct intel_dp *enc_to_intel_dp(struct drm_encoder *encoder) 89{ 90 return container_of(encoder, struct intel_dp, base.base); 91} 92 93static struct intel_dp *intel_attached_dp(struct drm_connector *connector) 94{ 95 return container_of(intel_attached_encoder(connector), 96 struct intel_dp, base); 97} 98 99/** 100 * intel_encoder_is_pch_edp - is the given encoder a PCH attached eDP? 101 * @encoder: DRM encoder 102 * 103 * Return true if @encoder corresponds to a PCH attached eDP panel. Needed 104 * by intel_display.c. 105 */ 106bool intel_encoder_is_pch_edp(struct drm_encoder *encoder) 107{ 108 struct intel_dp *intel_dp; 109 110 if (!encoder) 111 return false; 112 113 intel_dp = enc_to_intel_dp(encoder); 114 115 return is_pch_edp(intel_dp); 116} 117 118static void intel_dp_start_link_train(struct intel_dp *intel_dp); 119static void intel_dp_complete_link_train(struct intel_dp *intel_dp); 120static void intel_dp_link_down(struct intel_dp *intel_dp); 121 122void 123intel_edp_link_config (struct intel_encoder *intel_encoder, 124 int *lane_num, int *link_bw) 125{ 126 struct intel_dp *intel_dp = container_of(intel_encoder, struct intel_dp, base); 127 128 *lane_num = intel_dp->lane_count; 129 if (intel_dp->link_bw == DP_LINK_BW_1_62) 130 *link_bw = 162000; 131 else if (intel_dp->link_bw == DP_LINK_BW_2_7) 132 *link_bw = 270000; 133} 134 135static int 136intel_dp_max_lane_count(struct intel_dp *intel_dp) 137{ 138 int max_lane_count = 4; 139 140 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) { 141 max_lane_count = intel_dp->dpcd[DP_MAX_LANE_COUNT] & 0x1f; 142 switch (max_lane_count) { 143 case 1: case 2: case 4: 144 break; 145 default: 146 max_lane_count = 4; 147 } 148 } 149 return max_lane_count; 150} 151 152static int 153intel_dp_max_link_bw(struct intel_dp *intel_dp) 154{ 155 int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE]; 156 157 switch (max_link_bw) { 158 case DP_LINK_BW_1_62: 159 case DP_LINK_BW_2_7: 160 break; 161 default: 162 max_link_bw = DP_LINK_BW_1_62; 163 break; 164 } 165 return max_link_bw; 166} 167 168static int 169intel_dp_link_clock(uint8_t link_bw) 170{ 171 if (link_bw == DP_LINK_BW_2_7) 172 return 270000; 173 else 174 return 162000; 175} 176 177/* I think this is a fiction */ 178static int 179intel_dp_link_required(struct drm_device *dev, struct intel_dp *intel_dp, int pixel_clock) 180{ 181 struct drm_i915_private *dev_priv = dev->dev_private; 182 183 if (is_edp(intel_dp)) 184 return (pixel_clock * dev_priv->edp.bpp + 7) / 8; 185 else 186 return pixel_clock * 3; 187} 188 189static int 190intel_dp_max_data_rate(int max_link_clock, int max_lanes) 191{ 192 return (max_link_clock * max_lanes * 8) / 10; 193} 194 195static int 196intel_dp_mode_valid(struct drm_connector *connector, 197 struct drm_display_mode *mode) 198{ 199 struct intel_dp *intel_dp = intel_attached_dp(connector); 200 struct drm_device *dev = connector->dev; 201 struct drm_i915_private *dev_priv = dev->dev_private; 202 int max_link_clock = intel_dp_link_clock(intel_dp_max_link_bw(intel_dp)); 203 int max_lanes = intel_dp_max_lane_count(intel_dp); 204 205 if (is_edp(intel_dp) && dev_priv->panel_fixed_mode) { 206 if (mode->hdisplay > dev_priv->panel_fixed_mode->hdisplay) 207 return MODE_PANEL; 208 209 if (mode->vdisplay > dev_priv->panel_fixed_mode->vdisplay) 210 return MODE_PANEL; 211 } 212 213 /* only refuse the mode on non eDP since we have seen some weird eDP panels 214 which are outside spec tolerances but somehow work by magic */ 215 if (!is_edp(intel_dp) && 216 (intel_dp_link_required(connector->dev, intel_dp, mode->clock) 217 > intel_dp_max_data_rate(max_link_clock, max_lanes))) 218 return MODE_CLOCK_HIGH; 219 220 if (mode->clock < 10000) 221 return MODE_CLOCK_LOW; 222 223 return MODE_OK; 224} 225 226static uint32_t 227pack_aux(uint8_t *src, int src_bytes) 228{ 229 int i; 230 uint32_t v = 0; 231 232 if (src_bytes > 4) 233 src_bytes = 4; 234 for (i = 0; i < src_bytes; i++) 235 v |= ((uint32_t) src[i]) << ((3-i) * 8); 236 return v; 237} 238 239static void 240unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes) 241{ 242 int i; 243 if (dst_bytes > 4) 244 dst_bytes = 4; 245 for (i = 0; i < dst_bytes; i++) 246 dst[i] = src >> ((3-i) * 8); 247} 248 249/* hrawclock is 1/4 the FSB frequency */ 250static int 251intel_hrawclk(struct drm_device *dev) 252{ 253 struct drm_i915_private *dev_priv = dev->dev_private; 254 uint32_t clkcfg; 255 256 clkcfg = I915_READ(CLKCFG); 257 switch (clkcfg & CLKCFG_FSB_MASK) { 258 case CLKCFG_FSB_400: 259 return 100; 260 case CLKCFG_FSB_533: 261 return 133; 262 case CLKCFG_FSB_667: 263 return 166; 264 case CLKCFG_FSB_800: 265 return 200; 266 case CLKCFG_FSB_1067: 267 return 266; 268 case CLKCFG_FSB_1333: 269 return 333; 270 /* these two are just a guess; one of them might be right */ 271 case CLKCFG_FSB_1600: 272 case CLKCFG_FSB_1600_ALT: 273 return 400; 274 default: 275 return 133; 276 } 277} 278 279static int 280intel_dp_aux_ch(struct intel_dp *intel_dp, 281 uint8_t *send, int send_bytes, 282 uint8_t *recv, int recv_size) 283{ 284 uint32_t output_reg = intel_dp->output_reg; 285 struct drm_device *dev = intel_dp->base.base.dev; 286 struct drm_i915_private *dev_priv = dev->dev_private; 287 uint32_t ch_ctl = output_reg + 0x10; 288 uint32_t ch_data = ch_ctl + 4; 289 int i; 290 int recv_bytes; 291 uint32_t status; 292 uint32_t aux_clock_divider; 293 int try, precharge; 294 295 /* The clock divider is based off the hrawclk, 296 * and would like to run at 2MHz. So, take the 297 * hrawclk value and divide by 2 and use that 298 * 299 * Note that PCH attached eDP panels should use a 125MHz input 300 * clock divider. 301 */ 302 if (is_edp(intel_dp) && !is_pch_edp(intel_dp)) { 303 if (IS_GEN6(dev)) 304 aux_clock_divider = 200; /* SNB eDP input clock at 400Mhz */ 305 else 306 aux_clock_divider = 225; /* eDP input clock at 450Mhz */ 307 } else if (HAS_PCH_SPLIT(dev)) 308 aux_clock_divider = 62; /* IRL input clock fixed at 125Mhz */ 309 else 310 aux_clock_divider = intel_hrawclk(dev) / 2; 311 312 if (IS_GEN6(dev)) 313 precharge = 3; 314 else 315 precharge = 5; 316 317 if (I915_READ(ch_ctl) & DP_AUX_CH_CTL_SEND_BUSY) { 318 DRM_ERROR("dp_aux_ch not started status 0x%08x\n", 319 I915_READ(ch_ctl)); 320 return -EBUSY; 321 } 322 323 /* Must try at least 3 times according to DP spec */ 324 for (try = 0; try < 5; try++) { 325 /* Load the send data into the aux channel data registers */ 326 for (i = 0; i < send_bytes; i += 4) 327 I915_WRITE(ch_data + i, 328 pack_aux(send + i, send_bytes - i)); 329 330 /* Send the command and wait for it to complete */ 331 I915_WRITE(ch_ctl, 332 DP_AUX_CH_CTL_SEND_BUSY | 333 DP_AUX_CH_CTL_TIME_OUT_400us | 334 (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) | 335 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) | 336 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT) | 337 DP_AUX_CH_CTL_DONE | 338 DP_AUX_CH_CTL_TIME_OUT_ERROR | 339 DP_AUX_CH_CTL_RECEIVE_ERROR); 340 for (;;) { 341 status = I915_READ(ch_ctl); 342 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0) 343 break; 344 udelay(100); 345 } 346 347 /* Clear done status and any errors */ 348 I915_WRITE(ch_ctl, 349 status | 350 DP_AUX_CH_CTL_DONE | 351 DP_AUX_CH_CTL_TIME_OUT_ERROR | 352 DP_AUX_CH_CTL_RECEIVE_ERROR); 353 if (status & DP_AUX_CH_CTL_DONE) 354 break; 355 } 356 357 if ((status & DP_AUX_CH_CTL_DONE) == 0) { 358 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status); 359 return -EBUSY; 360 } 361 362 /* Check for timeout or receive error. 363 * Timeouts occur when the sink is not connected 364 */ 365 if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) { 366 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status); 367 return -EIO; 368 } 369 370 /* Timeouts occur when the device isn't connected, so they're 371 * "normal" -- don't fill the kernel log with these */ 372 if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) { 373 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status); 374 return -ETIMEDOUT; 375 } 376 377 /* Unload any bytes sent back from the other side */ 378 recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >> 379 DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT); 380 if (recv_bytes > recv_size) 381 recv_bytes = recv_size; 382 383 for (i = 0; i < recv_bytes; i += 4) 384 unpack_aux(I915_READ(ch_data + i), 385 recv + i, recv_bytes - i); 386 387 return recv_bytes; 388} 389 390/* Write data to the aux channel in native mode */ 391static int 392intel_dp_aux_native_write(struct intel_dp *intel_dp, 393 uint16_t address, uint8_t *send, int send_bytes) 394{ 395 int ret; 396 uint8_t msg[20]; 397 int msg_bytes; 398 uint8_t ack; 399 400 if (send_bytes > 16) 401 return -1; 402 msg[0] = AUX_NATIVE_WRITE << 4; 403 msg[1] = address >> 8; 404 msg[2] = address & 0xff; 405 msg[3] = send_bytes - 1; 406 memcpy(&msg[4], send, send_bytes); 407 msg_bytes = send_bytes + 4; 408 for (;;) { 409 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes, &ack, 1); 410 if (ret < 0) 411 return ret; 412 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK) 413 break; 414 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER) 415 udelay(100); 416 else 417 return -EIO; 418 } 419 return send_bytes; 420} 421 422/* Write a single byte to the aux channel in native mode */ 423static int 424intel_dp_aux_native_write_1(struct intel_dp *intel_dp, 425 uint16_t address, uint8_t byte) 426{ 427 return intel_dp_aux_native_write(intel_dp, address, &byte, 1); 428} 429 430/* read bytes from a native aux channel */ 431static int 432intel_dp_aux_native_read(struct intel_dp *intel_dp, 433 uint16_t address, uint8_t *recv, int recv_bytes) 434{ 435 uint8_t msg[4]; 436 int msg_bytes; 437 uint8_t reply[20]; 438 int reply_bytes; 439 uint8_t ack; 440 int ret; 441 442 msg[0] = AUX_NATIVE_READ << 4; 443 msg[1] = address >> 8; 444 msg[2] = address & 0xff; 445 msg[3] = recv_bytes - 1; 446 447 msg_bytes = 4; 448 reply_bytes = recv_bytes + 1; 449 450 for (;;) { 451 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes, 452 reply, reply_bytes); 453 if (ret == 0) 454 return -EPROTO; 455 if (ret < 0) 456 return ret; 457 ack = reply[0]; 458 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK) { 459 memcpy(recv, reply + 1, ret - 1); 460 return ret - 1; 461 } 462 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER) 463 udelay(100); 464 else 465 return -EIO; 466 } 467} 468 469static int 470intel_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode, 471 uint8_t write_byte, uint8_t *read_byte) 472{ 473 struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data; 474 struct intel_dp *intel_dp = container_of(adapter, 475 struct intel_dp, 476 adapter); 477 uint16_t address = algo_data->address; 478 uint8_t msg[5]; 479 uint8_t reply[2]; 480 unsigned retry; 481 int msg_bytes; 482 int reply_bytes; 483 int ret; 484 485 /* Set up the command byte */ 486 if (mode & MODE_I2C_READ) 487 msg[0] = AUX_I2C_READ << 4; 488 else 489 msg[0] = AUX_I2C_WRITE << 4; 490 491 if (!(mode & MODE_I2C_STOP)) 492 msg[0] |= AUX_I2C_MOT << 4; 493 494 msg[1] = address >> 8; 495 msg[2] = address; 496 497 switch (mode) { 498 case MODE_I2C_WRITE: 499 msg[3] = 0; 500 msg[4] = write_byte; 501 msg_bytes = 5; 502 reply_bytes = 1; 503 break; 504 case MODE_I2C_READ: 505 msg[3] = 0; 506 msg_bytes = 4; 507 reply_bytes = 2; 508 break; 509 default: 510 msg_bytes = 3; 511 reply_bytes = 1; 512 break; 513 } 514 515 for (retry = 0; retry < 5; retry++) { 516 ret = intel_dp_aux_ch(intel_dp, 517 msg, msg_bytes, 518 reply, reply_bytes); 519 if (ret < 0) { 520 DRM_DEBUG_KMS("aux_ch failed %d\n", ret); 521 return ret; 522 } 523 524 switch (reply[0] & AUX_NATIVE_REPLY_MASK) { 525 case AUX_NATIVE_REPLY_ACK: 526 /* I2C-over-AUX Reply field is only valid 527 * when paired with AUX ACK. 528 */ 529 break; 530 case AUX_NATIVE_REPLY_NACK: 531 DRM_DEBUG_KMS("aux_ch native nack\n"); 532 return -EREMOTEIO; 533 case AUX_NATIVE_REPLY_DEFER: 534 udelay(100); 535 continue; 536 default: 537 DRM_ERROR("aux_ch invalid native reply 0x%02x\n", 538 reply[0]); 539 return -EREMOTEIO; 540 } 541 542 switch (reply[0] & AUX_I2C_REPLY_MASK) { 543 case AUX_I2C_REPLY_ACK: 544 if (mode == MODE_I2C_READ) { 545 *read_byte = reply[1]; 546 } 547 return reply_bytes - 1; 548 case AUX_I2C_REPLY_NACK: 549 DRM_DEBUG_KMS("aux_i2c nack\n"); 550 return -EREMOTEIO; 551 case AUX_I2C_REPLY_DEFER: 552 DRM_DEBUG_KMS("aux_i2c defer\n"); 553 udelay(100); 554 break; 555 default: 556 DRM_ERROR("aux_i2c invalid reply 0x%02x\n", reply[0]); 557 return -EREMOTEIO; 558 } 559 } 560 561 DRM_ERROR("too many retries, giving up\n"); 562 return -EREMOTEIO; 563} 564 565static int 566intel_dp_i2c_init(struct intel_dp *intel_dp, 567 struct intel_connector *intel_connector, const char *name) 568{ 569 DRM_DEBUG_KMS("i2c_init %s\n", name); 570 intel_dp->algo.running = false; 571 intel_dp->algo.address = 0; 572 intel_dp->algo.aux_ch = intel_dp_i2c_aux_ch; 573 574 memset(&intel_dp->adapter, '\0', sizeof (intel_dp->adapter)); 575 intel_dp->adapter.owner = THIS_MODULE; 576 intel_dp->adapter.class = I2C_CLASS_DDC; 577 strncpy (intel_dp->adapter.name, name, sizeof(intel_dp->adapter.name) - 1); 578 intel_dp->adapter.name[sizeof(intel_dp->adapter.name) - 1] = '\0'; 579 intel_dp->adapter.algo_data = &intel_dp->algo; 580 intel_dp->adapter.dev.parent = &intel_connector->base.kdev; 581 582 return i2c_dp_aux_add_bus(&intel_dp->adapter); 583} 584 585static bool 586intel_dp_mode_fixup(struct drm_encoder *encoder, struct drm_display_mode *mode, 587 struct drm_display_mode *adjusted_mode) 588{ 589 struct drm_device *dev = encoder->dev; 590 struct drm_i915_private *dev_priv = dev->dev_private; 591 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 592 int lane_count, clock; 593 int max_lane_count = intel_dp_max_lane_count(intel_dp); 594 int max_clock = intel_dp_max_link_bw(intel_dp) == DP_LINK_BW_2_7 ? 1 : 0; 595 static int bws[2] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7 }; 596 597 if (is_edp(intel_dp) && dev_priv->panel_fixed_mode) { 598 intel_fixed_panel_mode(dev_priv->panel_fixed_mode, adjusted_mode); 599 intel_pch_panel_fitting(dev, DRM_MODE_SCALE_FULLSCREEN, 600 mode, adjusted_mode); 601 /* 602 * the mode->clock is used to calculate the Data&Link M/N 603 * of the pipe. For the eDP the fixed clock should be used. 604 */ 605 mode->clock = dev_priv->panel_fixed_mode->clock; 606 } 607 608 for (lane_count = 1; lane_count <= max_lane_count; lane_count <<= 1) { 609 for (clock = 0; clock <= max_clock; clock++) { 610 int link_avail = intel_dp_max_data_rate(intel_dp_link_clock(bws[clock]), lane_count); 611 612 if (intel_dp_link_required(encoder->dev, intel_dp, mode->clock) 613 <= link_avail) { 614 intel_dp->link_bw = bws[clock]; 615 intel_dp->lane_count = lane_count; 616 adjusted_mode->clock = intel_dp_link_clock(intel_dp->link_bw); 617 DRM_DEBUG_KMS("Display port link bw %02x lane " 618 "count %d clock %d\n", 619 intel_dp->link_bw, intel_dp->lane_count, 620 adjusted_mode->clock); 621 return true; 622 } 623 } 624 } 625 626 if (is_edp(intel_dp)) { 627 /* okay we failed just pick the highest */ 628 intel_dp->lane_count = max_lane_count; 629 intel_dp->link_bw = bws[max_clock]; 630 adjusted_mode->clock = intel_dp_link_clock(intel_dp->link_bw); 631 DRM_DEBUG_KMS("Force picking display port link bw %02x lane " 632 "count %d clock %d\n", 633 intel_dp->link_bw, intel_dp->lane_count, 634 adjusted_mode->clock); 635 636 return true; 637 } 638 639 return false; 640} 641 642struct intel_dp_m_n { 643 uint32_t tu; 644 uint32_t gmch_m; 645 uint32_t gmch_n; 646 uint32_t link_m; 647 uint32_t link_n; 648}; 649 650static void 651intel_reduce_ratio(uint32_t *num, uint32_t *den) 652{ 653 while (*num > 0xffffff || *den > 0xffffff) { 654 *num >>= 1; 655 *den >>= 1; 656 } 657} 658 659static void 660intel_dp_compute_m_n(int bpp, 661 int nlanes, 662 int pixel_clock, 663 int link_clock, 664 struct intel_dp_m_n *m_n) 665{ 666 m_n->tu = 64; 667 m_n->gmch_m = (pixel_clock * bpp) >> 3; 668 m_n->gmch_n = link_clock * nlanes; 669 intel_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n); 670 m_n->link_m = pixel_clock; 671 m_n->link_n = link_clock; 672 intel_reduce_ratio(&m_n->link_m, &m_n->link_n); 673} 674 675void 676intel_dp_set_m_n(struct drm_crtc *crtc, struct drm_display_mode *mode, 677 struct drm_display_mode *adjusted_mode) 678{ 679 struct drm_device *dev = crtc->dev; 680 struct drm_mode_config *mode_config = &dev->mode_config; 681 struct drm_encoder *encoder; 682 struct drm_i915_private *dev_priv = dev->dev_private; 683 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 684 int lane_count = 4, bpp = 24; 685 struct intel_dp_m_n m_n; 686 int pipe = intel_crtc->pipe; 687 688 /* 689 * Find the lane count in the intel_encoder private 690 */ 691 list_for_each_entry(encoder, &mode_config->encoder_list, head) { 692 struct intel_dp *intel_dp; 693 694 if (encoder->crtc != crtc) 695 continue; 696 697 intel_dp = enc_to_intel_dp(encoder); 698 if (intel_dp->base.type == INTEL_OUTPUT_DISPLAYPORT) { 699 lane_count = intel_dp->lane_count; 700 break; 701 } else if (is_edp(intel_dp)) { 702 lane_count = dev_priv->edp.lanes; 703 bpp = dev_priv->edp.bpp; 704 break; 705 } 706 } 707 708 /* 709 * Compute the GMCH and Link ratios. The '3' here is 710 * the number of bytes_per_pixel post-LUT, which we always 711 * set up for 8-bits of R/G/B, or 3 bytes total. 712 */ 713 intel_dp_compute_m_n(bpp, lane_count, 714 mode->clock, adjusted_mode->clock, &m_n); 715 716 if (HAS_PCH_SPLIT(dev)) { 717 I915_WRITE(TRANSDATA_M1(pipe), 718 ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) | 719 m_n.gmch_m); 720 I915_WRITE(TRANSDATA_N1(pipe), m_n.gmch_n); 721 I915_WRITE(TRANSDPLINK_M1(pipe), m_n.link_m); 722 I915_WRITE(TRANSDPLINK_N1(pipe), m_n.link_n); 723 } else { 724 I915_WRITE(PIPE_GMCH_DATA_M(pipe), 725 ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) | 726 m_n.gmch_m); 727 I915_WRITE(PIPE_GMCH_DATA_N(pipe), m_n.gmch_n); 728 I915_WRITE(PIPE_DP_LINK_M(pipe), m_n.link_m); 729 I915_WRITE(PIPE_DP_LINK_N(pipe), m_n.link_n); 730 } 731} 732 733static void 734intel_dp_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode, 735 struct drm_display_mode *adjusted_mode) 736{ 737 struct drm_device *dev = encoder->dev; 738 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 739 struct drm_crtc *crtc = intel_dp->base.base.crtc; 740 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 741 742 intel_dp->DP = DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0; 743 intel_dp->DP |= intel_dp->color_range; 744 745 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) 746 intel_dp->DP |= DP_SYNC_HS_HIGH; 747 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) 748 intel_dp->DP |= DP_SYNC_VS_HIGH; 749 750 if (HAS_PCH_CPT(dev) && !is_edp(intel_dp)) 751 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT; 752 else 753 intel_dp->DP |= DP_LINK_TRAIN_OFF; 754 755 switch (intel_dp->lane_count) { 756 case 1: 757 intel_dp->DP |= DP_PORT_WIDTH_1; 758 break; 759 case 2: 760 intel_dp->DP |= DP_PORT_WIDTH_2; 761 break; 762 case 4: 763 intel_dp->DP |= DP_PORT_WIDTH_4; 764 break; 765 } 766 if (intel_dp->has_audio) 767 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE; 768 769 memset(intel_dp->link_configuration, 0, DP_LINK_CONFIGURATION_SIZE); 770 intel_dp->link_configuration[0] = intel_dp->link_bw; 771 intel_dp->link_configuration[1] = intel_dp->lane_count; 772 773 /* 774 * Check for DPCD version > 1.1 and enhanced framing support 775 */ 776 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 && 777 (intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_ENHANCED_FRAME_CAP)) { 778 intel_dp->link_configuration[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN; 779 intel_dp->DP |= DP_ENHANCED_FRAMING; 780 } 781 782 /* CPT DP's pipe select is decided in TRANS_DP_CTL */ 783 if (intel_crtc->pipe == 1 && !HAS_PCH_CPT(dev)) 784 intel_dp->DP |= DP_PIPEB_SELECT; 785 786 if (is_edp(intel_dp) && !is_pch_edp(intel_dp)) { 787 /* don't miss out required setting for eDP */ 788 intel_dp->DP |= DP_PLL_ENABLE; 789 if (adjusted_mode->clock < 200000) 790 intel_dp->DP |= DP_PLL_FREQ_160MHZ; 791 else 792 intel_dp->DP |= DP_PLL_FREQ_270MHZ; 793 } 794} 795 796static void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp) 797{ 798 struct drm_device *dev = intel_dp->base.base.dev; 799 struct drm_i915_private *dev_priv = dev->dev_private; 800 u32 pp; 801 802 /* 803 * If the panel wasn't on, make sure there's not a currently 804 * active PP sequence before enabling AUX VDD. 805 */ 806 if (!(I915_READ(PCH_PP_STATUS) & PP_ON)) 807 msleep(dev_priv->panel_t3); 808 809 pp = I915_READ(PCH_PP_CONTROL); 810 pp |= EDP_FORCE_VDD; 811 I915_WRITE(PCH_PP_CONTROL, pp); 812 POSTING_READ(PCH_PP_CONTROL); 813} 814 815static void ironlake_edp_panel_vdd_off(struct intel_dp *intel_dp) 816{ 817 struct drm_device *dev = intel_dp->base.base.dev; 818 struct drm_i915_private *dev_priv = dev->dev_private; 819 u32 pp; 820 821 pp = I915_READ(PCH_PP_CONTROL); 822 pp &= ~EDP_FORCE_VDD; 823 I915_WRITE(PCH_PP_CONTROL, pp); 824 POSTING_READ(PCH_PP_CONTROL); 825 826 /* Make sure sequencer is idle before allowing subsequent activity */ 827 msleep(dev_priv->panel_t12); 828} 829 830/* Returns true if the panel was already on when called */ 831static bool ironlake_edp_panel_on (struct intel_dp *intel_dp) 832{ 833 struct drm_device *dev = intel_dp->base.base.dev; 834 struct drm_i915_private *dev_priv = dev->dev_private; 835 u32 pp, idle_on_mask = PP_ON | PP_SEQUENCE_STATE_ON_IDLE; 836 837 if (I915_READ(PCH_PP_STATUS) & PP_ON) 838 return true; 839 840 pp = I915_READ(PCH_PP_CONTROL); 841 842 /* ILK workaround: disable reset around power sequence */ 843 pp &= ~PANEL_POWER_RESET; 844 I915_WRITE(PCH_PP_CONTROL, pp); 845 POSTING_READ(PCH_PP_CONTROL); 846 847 pp |= PANEL_UNLOCK_REGS | POWER_TARGET_ON; 848 I915_WRITE(PCH_PP_CONTROL, pp); 849 POSTING_READ(PCH_PP_CONTROL); 850 851 if (wait_for((I915_READ(PCH_PP_STATUS) & idle_on_mask) == idle_on_mask, 852 5000)) 853 DRM_ERROR("panel on wait timed out: 0x%08x\n", 854 I915_READ(PCH_PP_STATUS)); 855 856 pp |= PANEL_POWER_RESET; /* restore panel reset bit */ 857 I915_WRITE(PCH_PP_CONTROL, pp); 858 POSTING_READ(PCH_PP_CONTROL); 859 860 return false; 861} 862 863static void ironlake_edp_panel_off (struct drm_device *dev) 864{ 865 struct drm_i915_private *dev_priv = dev->dev_private; 866 u32 pp, idle_off_mask = PP_ON | PP_SEQUENCE_MASK | 867 PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK; 868 869 pp = I915_READ(PCH_PP_CONTROL); 870 871 /* ILK workaround: disable reset around power sequence */ 872 pp &= ~PANEL_POWER_RESET; 873 I915_WRITE(PCH_PP_CONTROL, pp); 874 POSTING_READ(PCH_PP_CONTROL); 875 876 pp &= ~POWER_TARGET_ON; 877 I915_WRITE(PCH_PP_CONTROL, pp); 878 POSTING_READ(PCH_PP_CONTROL); 879 880 if (wait_for((I915_READ(PCH_PP_STATUS) & idle_off_mask) == 0, 5000)) 881 DRM_ERROR("panel off wait timed out: 0x%08x\n", 882 I915_READ(PCH_PP_STATUS)); 883 884 pp |= PANEL_POWER_RESET; /* restore panel reset bit */ 885 I915_WRITE(PCH_PP_CONTROL, pp); 886 POSTING_READ(PCH_PP_CONTROL); 887} 888 889static void ironlake_edp_backlight_on (struct drm_device *dev) 890{ 891 struct drm_i915_private *dev_priv = dev->dev_private; 892 u32 pp; 893 894 DRM_DEBUG_KMS("\n"); 895 /* 896 * If we enable the backlight right away following a panel power 897 * on, we may see slight flicker as the panel syncs with the eDP 898 * link. So delay a bit to make sure the image is solid before 899 * allowing it to appear. 900 */ 901 msleep(300); 902 pp = I915_READ(PCH_PP_CONTROL); 903 pp |= EDP_BLC_ENABLE; 904 I915_WRITE(PCH_PP_CONTROL, pp); 905} 906 907static void ironlake_edp_backlight_off (struct drm_device *dev) 908{ 909 struct drm_i915_private *dev_priv = dev->dev_private; 910 u32 pp; 911 912 DRM_DEBUG_KMS("\n"); 913 pp = I915_READ(PCH_PP_CONTROL); 914 pp &= ~EDP_BLC_ENABLE; 915 I915_WRITE(PCH_PP_CONTROL, pp); 916} 917 918static void ironlake_edp_pll_on(struct drm_encoder *encoder) 919{ 920 struct drm_device *dev = encoder->dev; 921 struct drm_i915_private *dev_priv = dev->dev_private; 922 u32 dpa_ctl; 923 924 DRM_DEBUG_KMS("\n"); 925 dpa_ctl = I915_READ(DP_A); 926 dpa_ctl |= DP_PLL_ENABLE; 927 I915_WRITE(DP_A, dpa_ctl); 928 POSTING_READ(DP_A); 929 udelay(200); 930} 931 932static void ironlake_edp_pll_off(struct drm_encoder *encoder) 933{ 934 struct drm_device *dev = encoder->dev; 935 struct drm_i915_private *dev_priv = dev->dev_private; 936 u32 dpa_ctl; 937 938 dpa_ctl = I915_READ(DP_A); 939 dpa_ctl &= ~DP_PLL_ENABLE; 940 I915_WRITE(DP_A, dpa_ctl); 941 POSTING_READ(DP_A); 942 udelay(200); 943} 944 945/* If the sink supports it, try to set the power state appropriately */ 946static void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode) 947{ 948 int ret, i; 949 950 /* Should have a valid DPCD by this point */ 951 if (intel_dp->dpcd[DP_DPCD_REV] < 0x11) 952 return; 953 954 if (mode != DRM_MODE_DPMS_ON) { 955 ret = intel_dp_aux_native_write_1(intel_dp, DP_SET_POWER, 956 DP_SET_POWER_D3); 957 if (ret != 1) 958 DRM_DEBUG_DRIVER("failed to write sink power state\n"); 959 } else { 960 /* 961 * When turning on, we need to retry for 1ms to give the sink 962 * time to wake up. 963 */ 964 for (i = 0; i < 3; i++) { 965 ret = intel_dp_aux_native_write_1(intel_dp, 966 DP_SET_POWER, 967 DP_SET_POWER_D0); 968 if (ret == 1) 969 break; 970 msleep(1); 971 } 972 } 973} 974 975static void intel_dp_prepare(struct drm_encoder *encoder) 976{ 977 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 978 struct drm_device *dev = encoder->dev; 979 980 /* Wake up the sink first */ 981 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON); 982 983 if (is_edp(intel_dp)) { 984 ironlake_edp_backlight_off(dev); 985 ironlake_edp_panel_off(dev); 986 if (!is_pch_edp(intel_dp)) 987 ironlake_edp_pll_on(encoder); 988 else 989 ironlake_edp_pll_off(encoder); 990 } 991 intel_dp_link_down(intel_dp); 992} 993 994static void intel_dp_commit(struct drm_encoder *encoder) 995{ 996 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 997 struct drm_device *dev = encoder->dev; 998 999 if (is_edp(intel_dp)) 1000 ironlake_edp_panel_vdd_on(intel_dp); 1001 1002 intel_dp_start_link_train(intel_dp); 1003 1004 if (is_edp(intel_dp)) { 1005 ironlake_edp_panel_on(intel_dp); 1006 ironlake_edp_panel_vdd_off(intel_dp); 1007 } 1008 1009 intel_dp_complete_link_train(intel_dp); 1010 1011 if (is_edp(intel_dp)) 1012 ironlake_edp_backlight_on(dev); 1013} 1014 1015static void 1016intel_dp_dpms(struct drm_encoder *encoder, int mode) 1017{ 1018 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 1019 struct drm_device *dev = encoder->dev; 1020 struct drm_i915_private *dev_priv = dev->dev_private; 1021 uint32_t dp_reg = I915_READ(intel_dp->output_reg); 1022 1023 if (mode != DRM_MODE_DPMS_ON) { 1024 if (is_edp(intel_dp)) 1025 ironlake_edp_backlight_off(dev); 1026 intel_dp_sink_dpms(intel_dp, mode); 1027 intel_dp_link_down(intel_dp); 1028 if (is_edp(intel_dp)) 1029 ironlake_edp_panel_off(dev); 1030 if (is_edp(intel_dp) && !is_pch_edp(intel_dp)) 1031 ironlake_edp_pll_off(encoder); 1032 } else { 1033 if (is_edp(intel_dp)) 1034 ironlake_edp_panel_vdd_on(intel_dp); 1035 intel_dp_sink_dpms(intel_dp, mode); 1036 if (!(dp_reg & DP_PORT_EN)) { 1037 intel_dp_start_link_train(intel_dp); 1038 if (is_edp(intel_dp)) { 1039 ironlake_edp_panel_on(intel_dp); 1040 ironlake_edp_panel_vdd_off(intel_dp); 1041 } 1042 intel_dp_complete_link_train(intel_dp); 1043 } 1044 if (is_edp(intel_dp)) 1045 ironlake_edp_backlight_on(dev); 1046 } 1047} 1048 1049/* 1050 * Native read with retry for link status and receiver capability reads for 1051 * cases where the sink may still be asleep. 1052 */ 1053static bool 1054intel_dp_aux_native_read_retry(struct intel_dp *intel_dp, uint16_t address, 1055 uint8_t *recv, int recv_bytes) 1056{ 1057 int ret, i; 1058 1059 /* 1060 * Sinks are *supposed* to come up within 1ms from an off state, 1061 * but we're also supposed to retry 3 times per the spec. 1062 */ 1063 for (i = 0; i < 3; i++) { 1064 ret = intel_dp_aux_native_read(intel_dp, address, recv, 1065 recv_bytes); 1066 if (ret == recv_bytes) 1067 return true; 1068 msleep(1); 1069 } 1070 1071 return false; 1072} 1073 1074/* 1075 * Fetch AUX CH registers 0x202 - 0x207 which contain 1076 * link status information 1077 */ 1078static bool 1079intel_dp_get_link_status(struct intel_dp *intel_dp) 1080{ 1081 return intel_dp_aux_native_read_retry(intel_dp, 1082 DP_LANE0_1_STATUS, 1083 intel_dp->link_status, 1084 DP_LINK_STATUS_SIZE); 1085} 1086 1087static uint8_t 1088intel_dp_link_status(uint8_t link_status[DP_LINK_STATUS_SIZE], 1089 int r) 1090{ 1091 return link_status[r - DP_LANE0_1_STATUS]; 1092} 1093 1094static uint8_t 1095intel_get_adjust_request_voltage(uint8_t link_status[DP_LINK_STATUS_SIZE], 1096 int lane) 1097{ 1098 int i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1); 1099 int s = ((lane & 1) ? 1100 DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT : 1101 DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT); 1102 uint8_t l = intel_dp_link_status(link_status, i); 1103 1104 return ((l >> s) & 3) << DP_TRAIN_VOLTAGE_SWING_SHIFT; 1105} 1106 1107static uint8_t 1108intel_get_adjust_request_pre_emphasis(uint8_t link_status[DP_LINK_STATUS_SIZE], 1109 int lane) 1110{ 1111 int i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1); 1112 int s = ((lane & 1) ? 1113 DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT : 1114 DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT); 1115 uint8_t l = intel_dp_link_status(link_status, i); 1116 1117 return ((l >> s) & 3) << DP_TRAIN_PRE_EMPHASIS_SHIFT; 1118} 1119 1120 1121#if 0 1122static char *voltage_names[] = { 1123 "0.4V", "0.6V", "0.8V", "1.2V" 1124}; 1125static char *pre_emph_names[] = { 1126 "0dB", "3.5dB", "6dB", "9.5dB" 1127}; 1128static char *link_train_names[] = { 1129 "pattern 1", "pattern 2", "idle", "off" 1130}; 1131#endif 1132 1133/* 1134 * These are source-specific values; current Intel hardware supports 1135 * a maximum voltage of 800mV and a maximum pre-emphasis of 6dB 1136 */ 1137#define I830_DP_VOLTAGE_MAX DP_TRAIN_VOLTAGE_SWING_800 1138 1139static uint8_t 1140intel_dp_pre_emphasis_max(uint8_t voltage_swing) 1141{ 1142 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) { 1143 case DP_TRAIN_VOLTAGE_SWING_400: 1144 return DP_TRAIN_PRE_EMPHASIS_6; 1145 case DP_TRAIN_VOLTAGE_SWING_600: 1146 return DP_TRAIN_PRE_EMPHASIS_6; 1147 case DP_TRAIN_VOLTAGE_SWING_800: 1148 return DP_TRAIN_PRE_EMPHASIS_3_5; 1149 case DP_TRAIN_VOLTAGE_SWING_1200: 1150 default: 1151 return DP_TRAIN_PRE_EMPHASIS_0; 1152 } 1153} 1154 1155static void 1156intel_get_adjust_train(struct intel_dp *intel_dp) 1157{ 1158 uint8_t v = 0; 1159 uint8_t p = 0; 1160 int lane; 1161 1162 for (lane = 0; lane < intel_dp->lane_count; lane++) { 1163 uint8_t this_v = intel_get_adjust_request_voltage(intel_dp->link_status, lane); 1164 uint8_t this_p = intel_get_adjust_request_pre_emphasis(intel_dp->link_status, lane); 1165 1166 if (this_v > v) 1167 v = this_v; 1168 if (this_p > p) 1169 p = this_p; 1170 } 1171 1172 if (v >= I830_DP_VOLTAGE_MAX) 1173 v = I830_DP_VOLTAGE_MAX | DP_TRAIN_MAX_SWING_REACHED; 1174 1175 if (p >= intel_dp_pre_emphasis_max(v)) 1176 p = intel_dp_pre_emphasis_max(v) | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED; 1177 1178 for (lane = 0; lane < 4; lane++) 1179 intel_dp->train_set[lane] = v | p; 1180} 1181 1182static uint32_t 1183intel_dp_signal_levels(uint8_t train_set, int lane_count) 1184{ 1185 uint32_t signal_levels = 0; 1186 1187 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { 1188 case DP_TRAIN_VOLTAGE_SWING_400: 1189 default: 1190 signal_levels |= DP_VOLTAGE_0_4; 1191 break; 1192 case DP_TRAIN_VOLTAGE_SWING_600: 1193 signal_levels |= DP_VOLTAGE_0_6; 1194 break; 1195 case DP_TRAIN_VOLTAGE_SWING_800: 1196 signal_levels |= DP_VOLTAGE_0_8; 1197 break; 1198 case DP_TRAIN_VOLTAGE_SWING_1200: 1199 signal_levels |= DP_VOLTAGE_1_2; 1200 break; 1201 } 1202 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) { 1203 case DP_TRAIN_PRE_EMPHASIS_0: 1204 default: 1205 signal_levels |= DP_PRE_EMPHASIS_0; 1206 break; 1207 case DP_TRAIN_PRE_EMPHASIS_3_5: 1208 signal_levels |= DP_PRE_EMPHASIS_3_5; 1209 break; 1210 case DP_TRAIN_PRE_EMPHASIS_6: 1211 signal_levels |= DP_PRE_EMPHASIS_6; 1212 break; 1213 case DP_TRAIN_PRE_EMPHASIS_9_5: 1214 signal_levels |= DP_PRE_EMPHASIS_9_5; 1215 break; 1216 } 1217 return signal_levels; 1218} 1219 1220/* Gen6's DP voltage swing and pre-emphasis control */ 1221static uint32_t 1222intel_gen6_edp_signal_levels(uint8_t train_set) 1223{ 1224 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK | 1225 DP_TRAIN_PRE_EMPHASIS_MASK); 1226 switch (signal_levels) { 1227 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0: 1228 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0: 1229 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B; 1230 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5: 1231 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B; 1232 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6: 1233 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6: 1234 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B; 1235 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5: 1236 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5: 1237 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B; 1238 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0: 1239 case DP_TRAIN_VOLTAGE_SWING_1200 | DP_TRAIN_PRE_EMPHASIS_0: 1240 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B; 1241 default: 1242 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:" 1243 "0x%x\n", signal_levels); 1244 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B; 1245 } 1246} 1247 1248static uint8_t 1249intel_get_lane_status(uint8_t link_status[DP_LINK_STATUS_SIZE], 1250 int lane) 1251{ 1252 int i = DP_LANE0_1_STATUS + (lane >> 1); 1253 int s = (lane & 1) * 4; 1254 uint8_t l = intel_dp_link_status(link_status, i); 1255 1256 return (l >> s) & 0xf; 1257} 1258 1259/* Check for clock recovery is done on all channels */ 1260static bool 1261intel_clock_recovery_ok(uint8_t link_status[DP_LINK_STATUS_SIZE], int lane_count) 1262{ 1263 int lane; 1264 uint8_t lane_status; 1265 1266 for (lane = 0; lane < lane_count; lane++) { 1267 lane_status = intel_get_lane_status(link_status, lane); 1268 if ((lane_status & DP_LANE_CR_DONE) == 0) 1269 return false; 1270 } 1271 return true; 1272} 1273 1274/* Check to see if channel eq is done on all channels */ 1275#define CHANNEL_EQ_BITS (DP_LANE_CR_DONE|\ 1276 DP_LANE_CHANNEL_EQ_DONE|\ 1277 DP_LANE_SYMBOL_LOCKED) 1278static bool 1279intel_channel_eq_ok(struct intel_dp *intel_dp) 1280{ 1281 uint8_t lane_align; 1282 uint8_t lane_status; 1283 int lane; 1284 1285 lane_align = intel_dp_link_status(intel_dp->link_status, 1286 DP_LANE_ALIGN_STATUS_UPDATED); 1287 if ((lane_align & DP_INTERLANE_ALIGN_DONE) == 0) 1288 return false; 1289 for (lane = 0; lane < intel_dp->lane_count; lane++) { 1290 lane_status = intel_get_lane_status(intel_dp->link_status, lane); 1291 if ((lane_status & CHANNEL_EQ_BITS) != CHANNEL_EQ_BITS) 1292 return false; 1293 } 1294 return true; 1295} 1296 1297static bool 1298intel_dp_set_link_train(struct intel_dp *intel_dp, 1299 uint32_t dp_reg_value, 1300 uint8_t dp_train_pat) 1301{ 1302 struct drm_device *dev = intel_dp->base.base.dev; 1303 struct drm_i915_private *dev_priv = dev->dev_private; 1304 int ret; 1305 1306 I915_WRITE(intel_dp->output_reg, dp_reg_value); 1307 POSTING_READ(intel_dp->output_reg); 1308 1309 intel_dp_aux_native_write_1(intel_dp, 1310 DP_TRAINING_PATTERN_SET, 1311 dp_train_pat); 1312 1313 ret = intel_dp_aux_native_write(intel_dp, 1314 DP_TRAINING_LANE0_SET, 1315 intel_dp->train_set, 4); 1316 if (ret != 4) 1317 return false; 1318 1319 return true; 1320} 1321 1322/* Enable corresponding port and start training pattern 1 */ 1323static void 1324intel_dp_start_link_train(struct intel_dp *intel_dp) 1325{ 1326 struct drm_device *dev = intel_dp->base.base.dev; 1327 struct drm_i915_private *dev_priv = dev->dev_private; 1328 struct intel_crtc *intel_crtc = to_intel_crtc(intel_dp->base.base.crtc); 1329 int i; 1330 uint8_t voltage; 1331 bool clock_recovery = false; 1332 int tries; 1333 u32 reg; 1334 uint32_t DP = intel_dp->DP; 1335 1336 /* Enable output, wait for it to become active */ 1337 I915_WRITE(intel_dp->output_reg, intel_dp->DP); 1338 POSTING_READ(intel_dp->output_reg); 1339 intel_wait_for_vblank(dev, intel_crtc->pipe); 1340 1341 /* Write the link configuration data */ 1342 intel_dp_aux_native_write(intel_dp, DP_LINK_BW_SET, 1343 intel_dp->link_configuration, 1344 DP_LINK_CONFIGURATION_SIZE); 1345 1346 DP |= DP_PORT_EN; 1347 if (HAS_PCH_CPT(dev) && !is_edp(intel_dp)) 1348 DP &= ~DP_LINK_TRAIN_MASK_CPT; 1349 else 1350 DP &= ~DP_LINK_TRAIN_MASK; 1351 memset(intel_dp->train_set, 0, 4); 1352 voltage = 0xff; 1353 tries = 0; 1354 clock_recovery = false; 1355 for (;;) { 1356 /* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */ 1357 uint32_t signal_levels; 1358 if (IS_GEN6(dev) && is_edp(intel_dp)) { 1359 signal_levels = intel_gen6_edp_signal_levels(intel_dp->train_set[0]); 1360 DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB) | signal_levels; 1361 } else { 1362 signal_levels = intel_dp_signal_levels(intel_dp->train_set[0], intel_dp->lane_count); 1363 DP = (DP & ~(DP_VOLTAGE_MASK|DP_PRE_EMPHASIS_MASK)) | signal_levels; 1364 } 1365 1366 if (HAS_PCH_CPT(dev) && !is_edp(intel_dp)) 1367 reg = DP | DP_LINK_TRAIN_PAT_1_CPT; 1368 else 1369 reg = DP | DP_LINK_TRAIN_PAT_1; 1370 1371 if (!intel_dp_set_link_train(intel_dp, reg, 1372 DP_TRAINING_PATTERN_1)) 1373 break; 1374 /* Set training pattern 1 */ 1375 1376 udelay(100); 1377 if (!intel_dp_get_link_status(intel_dp)) 1378 break; 1379 1380 if (intel_clock_recovery_ok(intel_dp->link_status, intel_dp->lane_count)) { 1381 clock_recovery = true; 1382 break; 1383 } 1384 1385 /* Check to see if we've tried the max voltage */ 1386 for (i = 0; i < intel_dp->lane_count; i++) 1387 if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0) 1388 break; 1389 if (i == intel_dp->lane_count) 1390 break; 1391 1392 /* Check to see if we've tried the same voltage 5 times */ 1393 if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) { 1394 ++tries; 1395 if (tries == 5) 1396 break; 1397 } else 1398 tries = 0; 1399 voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK; 1400 1401 /* Compute new intel_dp->train_set as requested by target */ 1402 intel_get_adjust_train(intel_dp); 1403 } 1404 1405 intel_dp->DP = DP; 1406} 1407 1408static void 1409intel_dp_complete_link_train(struct intel_dp *intel_dp) 1410{ 1411 struct drm_device *dev = intel_dp->base.base.dev; 1412 struct drm_i915_private *dev_priv = dev->dev_private; 1413 bool channel_eq = false; 1414 int tries, cr_tries; 1415 u32 reg; 1416 uint32_t DP = intel_dp->DP; 1417 1418 /* channel equalization */ 1419 tries = 0; 1420 cr_tries = 0; 1421 channel_eq = false; 1422 for (;;) { 1423 /* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */ 1424 uint32_t signal_levels; 1425 1426 if (cr_tries > 5) { 1427 DRM_ERROR("failed to train DP, aborting\n"); 1428 intel_dp_link_down(intel_dp); 1429 break; 1430 } 1431 1432 if (IS_GEN6(dev) && is_edp(intel_dp)) { 1433 signal_levels = intel_gen6_edp_signal_levels(intel_dp->train_set[0]); 1434 DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB) | signal_levels; 1435 } else { 1436 signal_levels = intel_dp_signal_levels(intel_dp->train_set[0], intel_dp->lane_count); 1437 DP = (DP & ~(DP_VOLTAGE_MASK|DP_PRE_EMPHASIS_MASK)) | signal_levels; 1438 } 1439 1440 if (HAS_PCH_CPT(dev) && !is_edp(intel_dp)) 1441 reg = DP | DP_LINK_TRAIN_PAT_2_CPT; 1442 else 1443 reg = DP | DP_LINK_TRAIN_PAT_2; 1444 1445 /* channel eq pattern */ 1446 if (!intel_dp_set_link_train(intel_dp, reg, 1447 DP_TRAINING_PATTERN_2)) 1448 break; 1449 1450 udelay(400); 1451 if (!intel_dp_get_link_status(intel_dp)) 1452 break; 1453 1454 /* Make sure clock is still ok */ 1455 if (!intel_clock_recovery_ok(intel_dp->link_status, intel_dp->lane_count)) { 1456 intel_dp_start_link_train(intel_dp); 1457 cr_tries++; 1458 continue; 1459 } 1460 1461 if (intel_channel_eq_ok(intel_dp)) { 1462 channel_eq = true; 1463 break; 1464 } 1465 1466 /* Try 5 times, then try clock recovery if that fails */ 1467 if (tries > 5) { 1468 intel_dp_link_down(intel_dp); 1469 intel_dp_start_link_train(intel_dp); 1470 tries = 0; 1471 cr_tries++; 1472 continue; 1473 } 1474 1475 /* Compute new intel_dp->train_set as requested by target */ 1476 intel_get_adjust_train(intel_dp); 1477 ++tries; 1478 } 1479 1480 if (HAS_PCH_CPT(dev) && !is_edp(intel_dp)) 1481 reg = DP | DP_LINK_TRAIN_OFF_CPT; 1482 else 1483 reg = DP | DP_LINK_TRAIN_OFF; 1484 1485 I915_WRITE(intel_dp->output_reg, reg); 1486 POSTING_READ(intel_dp->output_reg); 1487 intel_dp_aux_native_write_1(intel_dp, 1488 DP_TRAINING_PATTERN_SET, DP_TRAINING_PATTERN_DISABLE); 1489} 1490 1491static void 1492intel_dp_link_down(struct intel_dp *intel_dp) 1493{ 1494 struct drm_device *dev = intel_dp->base.base.dev; 1495 struct drm_i915_private *dev_priv = dev->dev_private; 1496 uint32_t DP = intel_dp->DP; 1497 1498 if ((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0) 1499 return; 1500 1501 DRM_DEBUG_KMS("\n"); 1502 1503 if (is_edp(intel_dp)) { 1504 DP &= ~DP_PLL_ENABLE; 1505 I915_WRITE(intel_dp->output_reg, DP); 1506 POSTING_READ(intel_dp->output_reg); 1507 udelay(100); 1508 } 1509 1510 if (HAS_PCH_CPT(dev) && !is_edp(intel_dp)) { 1511 DP &= ~DP_LINK_TRAIN_MASK_CPT; 1512 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT); 1513 } else { 1514 DP &= ~DP_LINK_TRAIN_MASK; 1515 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE); 1516 } 1517 POSTING_READ(intel_dp->output_reg); 1518 1519 msleep(17); 1520 1521 if (is_edp(intel_dp)) 1522 DP |= DP_LINK_TRAIN_OFF; 1523 1524 if (!HAS_PCH_CPT(dev) && 1525 I915_READ(intel_dp->output_reg) & DP_PIPEB_SELECT) { 1526 struct drm_crtc *crtc = intel_dp->base.base.crtc; 1527 1528 /* Hardware workaround: leaving our transcoder select 1529 * set to transcoder B while it's off will prevent the 1530 * corresponding HDMI output on transcoder A. 1531 * 1532 * Combine this with another hardware workaround: 1533 * transcoder select bit can only be cleared while the 1534 * port is enabled. 1535 */ 1536 DP &= ~DP_PIPEB_SELECT; 1537 I915_WRITE(intel_dp->output_reg, DP); 1538 1539 /* Changes to enable or select take place the vblank 1540 * after being written. 1541 */ 1542 if (crtc == NULL) { 1543 /* We can arrive here never having been attached 1544 * to a CRTC, for instance, due to inheriting 1545 * random state from the BIOS. 1546 * 1547 * If the pipe is not running, play safe and 1548 * wait for the clocks to stabilise before 1549 * continuing. 1550 */ 1551 POSTING_READ(intel_dp->output_reg); 1552 msleep(50); 1553 } else 1554 intel_wait_for_vblank(dev, to_intel_crtc(crtc)->pipe); 1555 } 1556 1557 I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN); 1558 POSTING_READ(intel_dp->output_reg); 1559} 1560 1561/* 1562 * According to DP spec 1563 * 5.1.2: 1564 * 1. Read DPCD 1565 * 2. Configure link according to Receiver Capabilities 1566 * 3. Use Link Training from 2.5.3.3 and 3.5.1.3 1567 * 4. Check link status on receipt of hot-plug interrupt 1568 */ 1569 1570static void 1571intel_dp_check_link_status(struct intel_dp *intel_dp) 1572{ 1573 int ret; 1574 1575 if (!intel_dp->base.base.crtc) 1576 return; 1577 1578 if (!intel_dp_get_link_status(intel_dp)) { 1579 intel_dp_link_down(intel_dp); 1580 return; 1581 } 1582 1583 /* Try to read receiver status if the link appears to be up */ 1584 ret = intel_dp_aux_native_read(intel_dp, 1585 0x000, intel_dp->dpcd, 1586 sizeof (intel_dp->dpcd)); 1587 if (ret != sizeof(intel_dp->dpcd)) { 1588 intel_dp_link_down(intel_dp); 1589 return; 1590 } 1591 1592 if (!intel_channel_eq_ok(intel_dp)) { 1593 intel_dp_start_link_train(intel_dp); 1594 intel_dp_complete_link_train(intel_dp); 1595 } 1596} 1597 1598static enum drm_connector_status 1599ironlake_dp_detect(struct intel_dp *intel_dp) 1600{ 1601 enum drm_connector_status status; 1602 bool ret; 1603 1604 /* Can't disconnect eDP, but you can close the lid... */ 1605 if (is_edp(intel_dp)) { 1606 status = intel_panel_detect(intel_dp->base.base.dev); 1607 if (status == connector_status_unknown) 1608 status = connector_status_connected; 1609 return status; 1610 } 1611 1612 status = connector_status_disconnected; 1613 ret = intel_dp_aux_native_read_retry(intel_dp, 1614 0x000, intel_dp->dpcd, 1615 sizeof (intel_dp->dpcd)); 1616 if (ret && intel_dp->dpcd[DP_DPCD_REV] != 0) 1617 status = connector_status_connected; 1618 return status; 1619} 1620 1621static enum drm_connector_status 1622g4x_dp_detect(struct intel_dp *intel_dp) 1623{ 1624 struct drm_device *dev = intel_dp->base.base.dev; 1625 struct drm_i915_private *dev_priv = dev->dev_private; 1626 enum drm_connector_status status; 1627 uint32_t temp, bit; 1628 1629 switch (intel_dp->output_reg) { 1630 case DP_B: 1631 bit = DPB_HOTPLUG_INT_STATUS; 1632 break; 1633 case DP_C: 1634 bit = DPC_HOTPLUG_INT_STATUS; 1635 break; 1636 case DP_D: 1637 bit = DPD_HOTPLUG_INT_STATUS; 1638 break; 1639 default: 1640 return connector_status_unknown; 1641 } 1642 1643 temp = I915_READ(PORT_HOTPLUG_STAT); 1644 1645 if ((temp & bit) == 0) 1646 return connector_status_disconnected; 1647 1648 status = connector_status_disconnected; 1649 if (intel_dp_aux_native_read(intel_dp, 0x000, intel_dp->dpcd, 1650 sizeof (intel_dp->dpcd)) == sizeof (intel_dp->dpcd)) 1651 { 1652 if (intel_dp->dpcd[DP_DPCD_REV] != 0) 1653 status = connector_status_connected; 1654 } 1655 1656 return status; 1657} 1658 1659/** 1660 * Uses CRT_HOTPLUG_EN and CRT_HOTPLUG_STAT to detect DP connection. 1661 * 1662 * \return true if DP port is connected. 1663 * \return false if DP port is disconnected. 1664 */ 1665static enum drm_connector_status 1666intel_dp_detect(struct drm_connector *connector, bool force) 1667{ 1668 struct intel_dp *intel_dp = intel_attached_dp(connector); 1669 struct drm_device *dev = intel_dp->base.base.dev; 1670 enum drm_connector_status status; 1671 struct edid *edid = NULL; 1672 1673 intel_dp->has_audio = false; 1674 memset(intel_dp->dpcd, 0, sizeof(intel_dp->dpcd)); 1675 1676 if (HAS_PCH_SPLIT(dev)) 1677 status = ironlake_dp_detect(intel_dp); 1678 else 1679 status = g4x_dp_detect(intel_dp); 1680 1681 DRM_DEBUG_KMS("DPCD: %hx%hx%hx%hx%hx%hx%hx%hx\n", intel_dp->dpcd[0], 1682 intel_dp->dpcd[1], intel_dp->dpcd[2], intel_dp->dpcd[3], 1683 intel_dp->dpcd[4], intel_dp->dpcd[5], intel_dp->dpcd[6], 1684 intel_dp->dpcd[7]); 1685 1686 if (status != connector_status_connected) 1687 return status; 1688 1689 if (intel_dp->force_audio) { 1690 intel_dp->has_audio = intel_dp->force_audio > 0; 1691 } else { 1692 edid = drm_get_edid(connector, &intel_dp->adapter); 1693 if (edid) { 1694 intel_dp->has_audio = drm_detect_monitor_audio(edid); 1695 connector->display_info.raw_edid = NULL; 1696 kfree(edid); 1697 } 1698 } 1699 1700 return connector_status_connected; 1701} 1702 1703static int intel_dp_get_modes(struct drm_connector *connector) 1704{ 1705 struct intel_dp *intel_dp = intel_attached_dp(connector); 1706 struct drm_device *dev = intel_dp->base.base.dev; 1707 struct drm_i915_private *dev_priv = dev->dev_private; 1708 int ret; 1709 1710 /* We should parse the EDID data and find out if it has an audio sink 1711 */ 1712 1713 ret = intel_ddc_get_modes(connector, &intel_dp->adapter); 1714 if (ret) { 1715 if (is_edp(intel_dp) && !dev_priv->panel_fixed_mode) { 1716 struct drm_display_mode *newmode; 1717 list_for_each_entry(newmode, &connector->probed_modes, 1718 head) { 1719 if (newmode->type & DRM_MODE_TYPE_PREFERRED) { 1720 dev_priv->panel_fixed_mode = 1721 drm_mode_duplicate(dev, newmode); 1722 break; 1723 } 1724 } 1725 } 1726 1727 return ret; 1728 } 1729 1730 /* if eDP has no EDID, try to use fixed panel mode from VBT */ 1731 if (is_edp(intel_dp)) { 1732 if (dev_priv->panel_fixed_mode != NULL) { 1733 struct drm_display_mode *mode; 1734 mode = drm_mode_duplicate(dev, dev_priv->panel_fixed_mode); 1735 drm_mode_probed_add(connector, mode); 1736 return 1; 1737 } 1738 } 1739 return 0; 1740} 1741 1742static bool 1743intel_dp_detect_audio(struct drm_connector *connector) 1744{ 1745 struct intel_dp *intel_dp = intel_attached_dp(connector); 1746 struct edid *edid; 1747 bool has_audio = false; 1748 1749 edid = drm_get_edid(connector, &intel_dp->adapter); 1750 if (edid) { 1751 has_audio = drm_detect_monitor_audio(edid); 1752 1753 connector->display_info.raw_edid = NULL; 1754 kfree(edid); 1755 } 1756 1757 return has_audio; 1758} 1759 1760static int 1761intel_dp_set_property(struct drm_connector *connector, 1762 struct drm_property *property, 1763 uint64_t val) 1764{ 1765 struct drm_i915_private *dev_priv = connector->dev->dev_private; 1766 struct intel_dp *intel_dp = intel_attached_dp(connector); 1767 int ret; 1768 1769 ret = drm_connector_property_set_value(connector, property, val); 1770 if (ret) 1771 return ret; 1772 1773 if (property == dev_priv->force_audio_property) { 1774 int i = val; 1775 bool has_audio; 1776 1777 if (i == intel_dp->force_audio) 1778 return 0; 1779 1780 intel_dp->force_audio = i; 1781 1782 if (i == 0) 1783 has_audio = intel_dp_detect_audio(connector); 1784 else 1785 has_audio = i > 0; 1786 1787 if (has_audio == intel_dp->has_audio) 1788 return 0; 1789 1790 intel_dp->has_audio = has_audio; 1791 goto done; 1792 } 1793 1794 if (property == dev_priv->broadcast_rgb_property) { 1795 if (val == !!intel_dp->color_range) 1796 return 0; 1797 1798 intel_dp->color_range = val ? DP_COLOR_RANGE_16_235 : 0; 1799 goto done; 1800 } 1801 1802 return -EINVAL; 1803 1804done: 1805 if (intel_dp->base.base.crtc) { 1806 struct drm_crtc *crtc = intel_dp->base.base.crtc; 1807 drm_crtc_helper_set_mode(crtc, &crtc->mode, 1808 crtc->x, crtc->y, 1809 crtc->fb); 1810 } 1811 1812 return 0; 1813} 1814 1815static void 1816intel_dp_destroy (struct drm_connector *connector) 1817{ 1818 drm_sysfs_connector_remove(connector); 1819 drm_connector_cleanup(connector); 1820 kfree(connector); 1821} 1822 1823static void intel_dp_encoder_destroy(struct drm_encoder *encoder) 1824{ 1825 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 1826 1827 i2c_del_adapter(&intel_dp->adapter); 1828 drm_encoder_cleanup(encoder); 1829 kfree(intel_dp); 1830} 1831 1832static const struct drm_encoder_helper_funcs intel_dp_helper_funcs = { 1833 .dpms = intel_dp_dpms, 1834 .mode_fixup = intel_dp_mode_fixup, 1835 .prepare = intel_dp_prepare, 1836 .mode_set = intel_dp_mode_set, 1837 .commit = intel_dp_commit, 1838}; 1839 1840static const struct drm_connector_funcs intel_dp_connector_funcs = { 1841 .dpms = drm_helper_connector_dpms, 1842 .detect = intel_dp_detect, 1843 .fill_modes = drm_helper_probe_single_connector_modes, 1844 .set_property = intel_dp_set_property, 1845 .destroy = intel_dp_destroy, 1846}; 1847 1848static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = { 1849 .get_modes = intel_dp_get_modes, 1850 .mode_valid = intel_dp_mode_valid, 1851 .best_encoder = intel_best_encoder, 1852}; 1853 1854static const struct drm_encoder_funcs intel_dp_enc_funcs = { 1855 .destroy = intel_dp_encoder_destroy, 1856}; 1857 1858static void 1859intel_dp_hot_plug(struct intel_encoder *intel_encoder) 1860{ 1861 struct intel_dp *intel_dp = container_of(intel_encoder, struct intel_dp, base); 1862 1863 intel_dp_check_link_status(intel_dp); 1864} 1865 1866/* Return which DP Port should be selected for Transcoder DP control */ 1867int 1868intel_trans_dp_port_sel (struct drm_crtc *crtc) 1869{ 1870 struct drm_device *dev = crtc->dev; 1871 struct drm_mode_config *mode_config = &dev->mode_config; 1872 struct drm_encoder *encoder; 1873 1874 list_for_each_entry(encoder, &mode_config->encoder_list, head) { 1875 struct intel_dp *intel_dp; 1876 1877 if (encoder->crtc != crtc) 1878 continue; 1879 1880 intel_dp = enc_to_intel_dp(encoder); 1881 if (intel_dp->base.type == INTEL_OUTPUT_DISPLAYPORT) 1882 return intel_dp->output_reg; 1883 } 1884 1885 return -1; 1886} 1887 1888/* check the VBT to see whether the eDP is on DP-D port */ 1889bool intel_dpd_is_edp(struct drm_device *dev) 1890{ 1891 struct drm_i915_private *dev_priv = dev->dev_private; 1892 struct child_device_config *p_child; 1893 int i; 1894 1895 if (!dev_priv->child_dev_num) 1896 return false; 1897 1898 for (i = 0; i < dev_priv->child_dev_num; i++) { 1899 p_child = dev_priv->child_dev + i; 1900 1901 if (p_child->dvo_port == PORT_IDPD && 1902 p_child->device_type == DEVICE_TYPE_eDP) 1903 return true; 1904 } 1905 return false; 1906} 1907 1908static void 1909intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector) 1910{ 1911 intel_attach_force_audio_property(connector); 1912 intel_attach_broadcast_rgb_property(connector); 1913} 1914 1915void 1916intel_dp_init(struct drm_device *dev, int output_reg) 1917{ 1918 struct drm_i915_private *dev_priv = dev->dev_private; 1919 struct drm_connector *connector; 1920 struct intel_dp *intel_dp; 1921 struct intel_encoder *intel_encoder; 1922 struct intel_connector *intel_connector; 1923 const char *name = NULL; 1924 int type; 1925 1926 intel_dp = kzalloc(sizeof(struct intel_dp), GFP_KERNEL); 1927 if (!intel_dp) 1928 return; 1929 1930 intel_dp->output_reg = output_reg; 1931 1932 intel_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL); 1933 if (!intel_connector) { 1934 kfree(intel_dp); 1935 return; 1936 } 1937 intel_encoder = &intel_dp->base; 1938 1939 if (HAS_PCH_SPLIT(dev) && output_reg == PCH_DP_D) 1940 if (intel_dpd_is_edp(dev)) 1941 intel_dp->is_pch_edp = true; 1942 1943 if (output_reg == DP_A || is_pch_edp(intel_dp)) { 1944 type = DRM_MODE_CONNECTOR_eDP; 1945 intel_encoder->type = INTEL_OUTPUT_EDP; 1946 } else { 1947 type = DRM_MODE_CONNECTOR_DisplayPort; 1948 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT; 1949 } 1950 1951 connector = &intel_connector->base; 1952 drm_connector_init(dev, connector, &intel_dp_connector_funcs, type); 1953 drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs); 1954 1955 connector->polled = DRM_CONNECTOR_POLL_HPD; 1956 1957 if (output_reg == DP_B || output_reg == PCH_DP_B) 1958 intel_encoder->clone_mask = (1 << INTEL_DP_B_CLONE_BIT); 1959 else if (output_reg == DP_C || output_reg == PCH_DP_C) 1960 intel_encoder->clone_mask = (1 << INTEL_DP_C_CLONE_BIT); 1961 else if (output_reg == DP_D || output_reg == PCH_DP_D) 1962 intel_encoder->clone_mask = (1 << INTEL_DP_D_CLONE_BIT); 1963 1964 if (is_edp(intel_dp)) 1965 intel_encoder->clone_mask = (1 << INTEL_EDP_CLONE_BIT); 1966 1967 intel_encoder->crtc_mask = (1 << 0) | (1 << 1); 1968 connector->interlace_allowed = true; 1969 connector->doublescan_allowed = 0; 1970 1971 drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs, 1972 DRM_MODE_ENCODER_TMDS); 1973 drm_encoder_helper_add(&intel_encoder->base, &intel_dp_helper_funcs); 1974 1975 intel_connector_attach_encoder(intel_connector, intel_encoder); 1976 drm_sysfs_connector_add(connector); 1977 1978 /* Set up the DDC bus. */ 1979 switch (output_reg) { 1980 case DP_A: 1981 name = "DPDDC-A"; 1982 break; 1983 case DP_B: 1984 case PCH_DP_B: 1985 dev_priv->hotplug_supported_mask |= 1986 HDMIB_HOTPLUG_INT_STATUS; 1987 name = "DPDDC-B"; 1988 break; 1989 case DP_C: 1990 case PCH_DP_C: 1991 dev_priv->hotplug_supported_mask |= 1992 HDMIC_HOTPLUG_INT_STATUS; 1993 name = "DPDDC-C"; 1994 break; 1995 case DP_D: 1996 case PCH_DP_D: 1997 dev_priv->hotplug_supported_mask |= 1998 HDMID_HOTPLUG_INT_STATUS; 1999 name = "DPDDC-D"; 2000 break; 2001 } 2002 2003 intel_dp_i2c_init(intel_dp, intel_connector, name); 2004 2005 /* Cache some DPCD data in the eDP case */ 2006 if (is_edp(intel_dp)) { 2007 int ret; 2008 u32 pp_on, pp_div; 2009 2010 pp_on = I915_READ(PCH_PP_ON_DELAYS); 2011 pp_div = I915_READ(PCH_PP_DIVISOR); 2012 2013 /* Get T3 & T12 values (note: VESA not bspec terminology) */ 2014 dev_priv->panel_t3 = (pp_on & 0x1fff0000) >> 16; 2015 dev_priv->panel_t3 /= 10; /* t3 in 100us units */ 2016 dev_priv->panel_t12 = pp_div & 0xf; 2017 dev_priv->panel_t12 *= 100; /* t12 in 100ms units */ 2018 2019 ironlake_edp_panel_vdd_on(intel_dp); 2020 ret = intel_dp_aux_native_read(intel_dp, DP_DPCD_REV, 2021 intel_dp->dpcd, 2022 sizeof(intel_dp->dpcd)); 2023 ironlake_edp_panel_vdd_off(intel_dp); 2024 if (ret == sizeof(intel_dp->dpcd)) { 2025 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) 2026 dev_priv->no_aux_handshake = 2027 intel_dp->dpcd[DP_MAX_DOWNSPREAD] & 2028 DP_NO_AUX_HANDSHAKE_LINK_TRAINING; 2029 } else { 2030 /* if this fails, presume the device is a ghost */ 2031 DRM_INFO("failed to retrieve link info, disabling eDP\n"); 2032 intel_dp_encoder_destroy(&intel_dp->base.base); 2033 intel_dp_destroy(&intel_connector->base); 2034 return; 2035 } 2036 } 2037 2038 intel_encoder->hot_plug = intel_dp_hot_plug; 2039 2040 if (is_edp(intel_dp)) { 2041 /* initialize panel mode from VBT if available for eDP */ 2042 if (dev_priv->lfp_lvds_vbt_mode) { 2043 dev_priv->panel_fixed_mode = 2044 drm_mode_duplicate(dev, dev_priv->lfp_lvds_vbt_mode); 2045 if (dev_priv->panel_fixed_mode) { 2046 dev_priv->panel_fixed_mode->type |= 2047 DRM_MODE_TYPE_PREFERRED; 2048 } 2049 } 2050 } 2051 2052 intel_dp_add_properties(intel_dp, connector); 2053 2054 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written 2055 * 0xd. Failure to do so will result in spurious interrupts being 2056 * generated on the port when a cable is not attached. 2057 */ 2058 if (IS_G4X(dev) && !IS_GM45(dev)) { 2059 u32 temp = I915_READ(PEG_BAND_GAP_DATA); 2060 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd); 2061 } 2062} 2063