intel_dp.c revision b3064154dfd37deb386b1e459c54e1ca2460b3d5
1/* 2 * Copyright © 2008 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 * Authors: 24 * Keith Packard <keithp@keithp.com> 25 * 26 */ 27 28#include <linux/i2c.h> 29#include <linux/slab.h> 30#include <linux/export.h> 31#include <drm/drmP.h> 32#include <drm/drm_crtc.h> 33#include <drm/drm_crtc_helper.h> 34#include <drm/drm_edid.h> 35#include "intel_drv.h" 36#include <drm/i915_drm.h> 37#include "i915_drv.h" 38 39#define DP_LINK_CHECK_TIMEOUT (10 * 1000) 40 41struct dp_link_dpll { 42 int link_bw; 43 struct dpll dpll; 44}; 45 46static const struct dp_link_dpll gen4_dpll[] = { 47 { DP_LINK_BW_1_62, 48 { .p1 = 2, .p2 = 10, .n = 2, .m1 = 23, .m2 = 8 } }, 49 { DP_LINK_BW_2_7, 50 { .p1 = 1, .p2 = 10, .n = 1, .m1 = 14, .m2 = 2 } } 51}; 52 53static const struct dp_link_dpll pch_dpll[] = { 54 { DP_LINK_BW_1_62, 55 { .p1 = 2, .p2 = 10, .n = 1, .m1 = 12, .m2 = 9 } }, 56 { DP_LINK_BW_2_7, 57 { .p1 = 1, .p2 = 10, .n = 2, .m1 = 14, .m2 = 8 } } 58}; 59 60static const struct dp_link_dpll vlv_dpll[] = { 61 { DP_LINK_BW_1_62, 62 { .p1 = 3, .p2 = 2, .n = 5, .m1 = 3, .m2 = 81 } }, 63 { DP_LINK_BW_2_7, 64 { .p1 = 2, .p2 = 2, .n = 1, .m1 = 2, .m2 = 27 } } 65}; 66 67/** 68 * is_edp - is the given port attached to an eDP panel (either CPU or PCH) 69 * @intel_dp: DP struct 70 * 71 * If a CPU or PCH DP output is attached to an eDP panel, this function 72 * will return true, and false otherwise. 73 */ 74static bool is_edp(struct intel_dp *intel_dp) 75{ 76 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 77 78 return intel_dig_port->base.type == INTEL_OUTPUT_EDP; 79} 80 81static struct drm_device *intel_dp_to_dev(struct intel_dp *intel_dp) 82{ 83 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 84 85 return intel_dig_port->base.base.dev; 86} 87 88static struct intel_dp *intel_attached_dp(struct drm_connector *connector) 89{ 90 return enc_to_intel_dp(&intel_attached_encoder(connector)->base); 91} 92 93static void intel_dp_link_down(struct intel_dp *intel_dp); 94static void edp_panel_vdd_on(struct intel_dp *intel_dp); 95static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync); 96 97static int 98intel_dp_max_link_bw(struct intel_dp *intel_dp) 99{ 100 int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE]; 101 struct drm_device *dev = intel_dp->attached_connector->base.dev; 102 103 switch (max_link_bw) { 104 case DP_LINK_BW_1_62: 105 case DP_LINK_BW_2_7: 106 break; 107 case DP_LINK_BW_5_4: /* 1.2 capable displays may advertise higher bw */ 108 if ((IS_HASWELL(dev) || INTEL_INFO(dev)->gen >= 8) && 109 intel_dp->dpcd[DP_DPCD_REV] >= 0x12) 110 max_link_bw = DP_LINK_BW_5_4; 111 else 112 max_link_bw = DP_LINK_BW_2_7; 113 break; 114 default: 115 WARN(1, "invalid max DP link bw val %x, using 1.62Gbps\n", 116 max_link_bw); 117 max_link_bw = DP_LINK_BW_1_62; 118 break; 119 } 120 return max_link_bw; 121} 122 123/* 124 * The units on the numbers in the next two are... bizarre. Examples will 125 * make it clearer; this one parallels an example in the eDP spec. 126 * 127 * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as: 128 * 129 * 270000 * 1 * 8 / 10 == 216000 130 * 131 * The actual data capacity of that configuration is 2.16Gbit/s, so the 132 * units are decakilobits. ->clock in a drm_display_mode is in kilohertz - 133 * or equivalently, kilopixels per second - so for 1680x1050R it'd be 134 * 119000. At 18bpp that's 2142000 kilobits per second. 135 * 136 * Thus the strange-looking division by 10 in intel_dp_link_required, to 137 * get the result in decakilobits instead of kilobits. 138 */ 139 140static int 141intel_dp_link_required(int pixel_clock, int bpp) 142{ 143 return (pixel_clock * bpp + 9) / 10; 144} 145 146static int 147intel_dp_max_data_rate(int max_link_clock, int max_lanes) 148{ 149 return (max_link_clock * max_lanes * 8) / 10; 150} 151 152static enum drm_mode_status 153intel_dp_mode_valid(struct drm_connector *connector, 154 struct drm_display_mode *mode) 155{ 156 struct intel_dp *intel_dp = intel_attached_dp(connector); 157 struct intel_connector *intel_connector = to_intel_connector(connector); 158 struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode; 159 int target_clock = mode->clock; 160 int max_rate, mode_rate, max_lanes, max_link_clock; 161 162 if (is_edp(intel_dp) && fixed_mode) { 163 if (mode->hdisplay > fixed_mode->hdisplay) 164 return MODE_PANEL; 165 166 if (mode->vdisplay > fixed_mode->vdisplay) 167 return MODE_PANEL; 168 169 target_clock = fixed_mode->clock; 170 } 171 172 max_link_clock = drm_dp_bw_code_to_link_rate(intel_dp_max_link_bw(intel_dp)); 173 max_lanes = drm_dp_max_lane_count(intel_dp->dpcd); 174 175 max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes); 176 mode_rate = intel_dp_link_required(target_clock, 18); 177 178 if (mode_rate > max_rate) 179 return MODE_CLOCK_HIGH; 180 181 if (mode->clock < 10000) 182 return MODE_CLOCK_LOW; 183 184 if (mode->flags & DRM_MODE_FLAG_DBLCLK) 185 return MODE_H_ILLEGAL; 186 187 return MODE_OK; 188} 189 190static uint32_t 191pack_aux(uint8_t *src, int src_bytes) 192{ 193 int i; 194 uint32_t v = 0; 195 196 if (src_bytes > 4) 197 src_bytes = 4; 198 for (i = 0; i < src_bytes; i++) 199 v |= ((uint32_t) src[i]) << ((3-i) * 8); 200 return v; 201} 202 203static void 204unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes) 205{ 206 int i; 207 if (dst_bytes > 4) 208 dst_bytes = 4; 209 for (i = 0; i < dst_bytes; i++) 210 dst[i] = src >> ((3-i) * 8); 211} 212 213/* hrawclock is 1/4 the FSB frequency */ 214static int 215intel_hrawclk(struct drm_device *dev) 216{ 217 struct drm_i915_private *dev_priv = dev->dev_private; 218 uint32_t clkcfg; 219 220 /* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */ 221 if (IS_VALLEYVIEW(dev)) 222 return 200; 223 224 clkcfg = I915_READ(CLKCFG); 225 switch (clkcfg & CLKCFG_FSB_MASK) { 226 case CLKCFG_FSB_400: 227 return 100; 228 case CLKCFG_FSB_533: 229 return 133; 230 case CLKCFG_FSB_667: 231 return 166; 232 case CLKCFG_FSB_800: 233 return 200; 234 case CLKCFG_FSB_1067: 235 return 266; 236 case CLKCFG_FSB_1333: 237 return 333; 238 /* these two are just a guess; one of them might be right */ 239 case CLKCFG_FSB_1600: 240 case CLKCFG_FSB_1600_ALT: 241 return 400; 242 default: 243 return 133; 244 } 245} 246 247static void 248intel_dp_init_panel_power_sequencer(struct drm_device *dev, 249 struct intel_dp *intel_dp, 250 struct edp_power_seq *out); 251static void 252intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev, 253 struct intel_dp *intel_dp, 254 struct edp_power_seq *out); 255 256static enum pipe 257vlv_power_sequencer_pipe(struct intel_dp *intel_dp) 258{ 259 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 260 struct drm_crtc *crtc = intel_dig_port->base.base.crtc; 261 struct drm_device *dev = intel_dig_port->base.base.dev; 262 struct drm_i915_private *dev_priv = dev->dev_private; 263 enum port port = intel_dig_port->port; 264 enum pipe pipe; 265 266 /* modeset should have pipe */ 267 if (crtc) 268 return to_intel_crtc(crtc)->pipe; 269 270 /* init time, try to find a pipe with this port selected */ 271 for (pipe = PIPE_A; pipe <= PIPE_B; pipe++) { 272 u32 port_sel = I915_READ(VLV_PIPE_PP_ON_DELAYS(pipe)) & 273 PANEL_PORT_SELECT_MASK; 274 if (port_sel == PANEL_PORT_SELECT_DPB_VLV && port == PORT_B) 275 return pipe; 276 if (port_sel == PANEL_PORT_SELECT_DPC_VLV && port == PORT_C) 277 return pipe; 278 } 279 280 /* shrug */ 281 return PIPE_A; 282} 283 284static u32 _pp_ctrl_reg(struct intel_dp *intel_dp) 285{ 286 struct drm_device *dev = intel_dp_to_dev(intel_dp); 287 288 if (HAS_PCH_SPLIT(dev)) 289 return PCH_PP_CONTROL; 290 else 291 return VLV_PIPE_PP_CONTROL(vlv_power_sequencer_pipe(intel_dp)); 292} 293 294static u32 _pp_stat_reg(struct intel_dp *intel_dp) 295{ 296 struct drm_device *dev = intel_dp_to_dev(intel_dp); 297 298 if (HAS_PCH_SPLIT(dev)) 299 return PCH_PP_STATUS; 300 else 301 return VLV_PIPE_PP_STATUS(vlv_power_sequencer_pipe(intel_dp)); 302} 303 304static bool edp_have_panel_power(struct intel_dp *intel_dp) 305{ 306 struct drm_device *dev = intel_dp_to_dev(intel_dp); 307 struct drm_i915_private *dev_priv = dev->dev_private; 308 309 return (I915_READ(_pp_stat_reg(intel_dp)) & PP_ON) != 0; 310} 311 312static bool edp_have_panel_vdd(struct intel_dp *intel_dp) 313{ 314 struct drm_device *dev = intel_dp_to_dev(intel_dp); 315 struct drm_i915_private *dev_priv = dev->dev_private; 316 317 return (I915_READ(_pp_ctrl_reg(intel_dp)) & EDP_FORCE_VDD) != 0; 318} 319 320static void 321intel_dp_check_edp(struct intel_dp *intel_dp) 322{ 323 struct drm_device *dev = intel_dp_to_dev(intel_dp); 324 struct drm_i915_private *dev_priv = dev->dev_private; 325 326 if (!is_edp(intel_dp)) 327 return; 328 329 if (!edp_have_panel_power(intel_dp) && !edp_have_panel_vdd(intel_dp)) { 330 WARN(1, "eDP powered off while attempting aux channel communication.\n"); 331 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n", 332 I915_READ(_pp_stat_reg(intel_dp)), 333 I915_READ(_pp_ctrl_reg(intel_dp))); 334 } 335} 336 337static uint32_t 338intel_dp_aux_wait_done(struct intel_dp *intel_dp, bool has_aux_irq) 339{ 340 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 341 struct drm_device *dev = intel_dig_port->base.base.dev; 342 struct drm_i915_private *dev_priv = dev->dev_private; 343 uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg; 344 uint32_t status; 345 bool done; 346 347#define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0) 348 if (has_aux_irq) 349 done = wait_event_timeout(dev_priv->gmbus_wait_queue, C, 350 msecs_to_jiffies_timeout(10)); 351 else 352 done = wait_for_atomic(C, 10) == 0; 353 if (!done) 354 DRM_ERROR("dp aux hw did not signal timeout (has irq: %i)!\n", 355 has_aux_irq); 356#undef C 357 358 return status; 359} 360 361static uint32_t i9xx_get_aux_clock_divider(struct intel_dp *intel_dp, int index) 362{ 363 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 364 struct drm_device *dev = intel_dig_port->base.base.dev; 365 366 /* 367 * The clock divider is based off the hrawclk, and would like to run at 368 * 2MHz. So, take the hrawclk value and divide by 2 and use that 369 */ 370 return index ? 0 : intel_hrawclk(dev) / 2; 371} 372 373static uint32_t ilk_get_aux_clock_divider(struct intel_dp *intel_dp, int index) 374{ 375 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 376 struct drm_device *dev = intel_dig_port->base.base.dev; 377 378 if (index) 379 return 0; 380 381 if (intel_dig_port->port == PORT_A) { 382 if (IS_GEN6(dev) || IS_GEN7(dev)) 383 return 200; /* SNB & IVB eDP input clock at 400Mhz */ 384 else 385 return 225; /* eDP input clock at 450Mhz */ 386 } else { 387 return DIV_ROUND_UP(intel_pch_rawclk(dev), 2); 388 } 389} 390 391static uint32_t hsw_get_aux_clock_divider(struct intel_dp *intel_dp, int index) 392{ 393 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 394 struct drm_device *dev = intel_dig_port->base.base.dev; 395 struct drm_i915_private *dev_priv = dev->dev_private; 396 397 if (intel_dig_port->port == PORT_A) { 398 if (index) 399 return 0; 400 return DIV_ROUND_CLOSEST(intel_ddi_get_cdclk_freq(dev_priv), 2000); 401 } else if (dev_priv->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE) { 402 /* Workaround for non-ULT HSW */ 403 switch (index) { 404 case 0: return 63; 405 case 1: return 72; 406 default: return 0; 407 } 408 } else { 409 return index ? 0 : DIV_ROUND_UP(intel_pch_rawclk(dev), 2); 410 } 411} 412 413static uint32_t vlv_get_aux_clock_divider(struct intel_dp *intel_dp, int index) 414{ 415 return index ? 0 : 100; 416} 417 418static uint32_t i9xx_get_aux_send_ctl(struct intel_dp *intel_dp, 419 bool has_aux_irq, 420 int send_bytes, 421 uint32_t aux_clock_divider) 422{ 423 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 424 struct drm_device *dev = intel_dig_port->base.base.dev; 425 uint32_t precharge, timeout; 426 427 if (IS_GEN6(dev)) 428 precharge = 3; 429 else 430 precharge = 5; 431 432 if (IS_BROADWELL(dev) && intel_dp->aux_ch_ctl_reg == DPA_AUX_CH_CTL) 433 timeout = DP_AUX_CH_CTL_TIME_OUT_600us; 434 else 435 timeout = DP_AUX_CH_CTL_TIME_OUT_400us; 436 437 return DP_AUX_CH_CTL_SEND_BUSY | 438 DP_AUX_CH_CTL_DONE | 439 (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) | 440 DP_AUX_CH_CTL_TIME_OUT_ERROR | 441 timeout | 442 DP_AUX_CH_CTL_RECEIVE_ERROR | 443 (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) | 444 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) | 445 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT); 446} 447 448static int 449intel_dp_aux_ch(struct intel_dp *intel_dp, 450 uint8_t *send, int send_bytes, 451 uint8_t *recv, int recv_size) 452{ 453 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 454 struct drm_device *dev = intel_dig_port->base.base.dev; 455 struct drm_i915_private *dev_priv = dev->dev_private; 456 uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg; 457 uint32_t ch_data = ch_ctl + 4; 458 uint32_t aux_clock_divider; 459 int i, ret, recv_bytes; 460 uint32_t status; 461 int try, clock = 0; 462 bool has_aux_irq = true; 463 464 /* dp aux is extremely sensitive to irq latency, hence request the 465 * lowest possible wakeup latency and so prevent the cpu from going into 466 * deep sleep states. 467 */ 468 pm_qos_update_request(&dev_priv->pm_qos, 0); 469 470 intel_dp_check_edp(intel_dp); 471 472 intel_aux_display_runtime_get(dev_priv); 473 474 /* Try to wait for any previous AUX channel activity */ 475 for (try = 0; try < 3; try++) { 476 status = I915_READ_NOTRACE(ch_ctl); 477 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0) 478 break; 479 msleep(1); 480 } 481 482 if (try == 3) { 483 WARN(1, "dp_aux_ch not started status 0x%08x\n", 484 I915_READ(ch_ctl)); 485 ret = -EBUSY; 486 goto out; 487 } 488 489 /* Only 5 data registers! */ 490 if (WARN_ON(send_bytes > 20 || recv_size > 20)) { 491 ret = -E2BIG; 492 goto out; 493 } 494 495 while ((aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, clock++))) { 496 u32 send_ctl = intel_dp->get_aux_send_ctl(intel_dp, 497 has_aux_irq, 498 send_bytes, 499 aux_clock_divider); 500 501 /* Must try at least 3 times according to DP spec */ 502 for (try = 0; try < 5; try++) { 503 /* Load the send data into the aux channel data registers */ 504 for (i = 0; i < send_bytes; i += 4) 505 I915_WRITE(ch_data + i, 506 pack_aux(send + i, send_bytes - i)); 507 508 /* Send the command and wait for it to complete */ 509 I915_WRITE(ch_ctl, send_ctl); 510 511 status = intel_dp_aux_wait_done(intel_dp, has_aux_irq); 512 513 /* Clear done status and any errors */ 514 I915_WRITE(ch_ctl, 515 status | 516 DP_AUX_CH_CTL_DONE | 517 DP_AUX_CH_CTL_TIME_OUT_ERROR | 518 DP_AUX_CH_CTL_RECEIVE_ERROR); 519 520 if (status & (DP_AUX_CH_CTL_TIME_OUT_ERROR | 521 DP_AUX_CH_CTL_RECEIVE_ERROR)) 522 continue; 523 if (status & DP_AUX_CH_CTL_DONE) 524 break; 525 } 526 if (status & DP_AUX_CH_CTL_DONE) 527 break; 528 } 529 530 if ((status & DP_AUX_CH_CTL_DONE) == 0) { 531 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status); 532 ret = -EBUSY; 533 goto out; 534 } 535 536 /* Check for timeout or receive error. 537 * Timeouts occur when the sink is not connected 538 */ 539 if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) { 540 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status); 541 ret = -EIO; 542 goto out; 543 } 544 545 /* Timeouts occur when the device isn't connected, so they're 546 * "normal" -- don't fill the kernel log with these */ 547 if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) { 548 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status); 549 ret = -ETIMEDOUT; 550 goto out; 551 } 552 553 /* Unload any bytes sent back from the other side */ 554 recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >> 555 DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT); 556 if (recv_bytes > recv_size) 557 recv_bytes = recv_size; 558 559 for (i = 0; i < recv_bytes; i += 4) 560 unpack_aux(I915_READ(ch_data + i), 561 recv + i, recv_bytes - i); 562 563 ret = recv_bytes; 564out: 565 pm_qos_update_request(&dev_priv->pm_qos, PM_QOS_DEFAULT_VALUE); 566 intel_aux_display_runtime_put(dev_priv); 567 568 return ret; 569} 570 571/* Write data to the aux channel in native mode */ 572static int 573intel_dp_aux_native_write(struct intel_dp *intel_dp, 574 uint16_t address, uint8_t *send, int send_bytes) 575{ 576 int ret; 577 uint8_t msg[20]; 578 int msg_bytes; 579 uint8_t ack; 580 581 if (WARN_ON(send_bytes > 16)) 582 return -E2BIG; 583 584 intel_dp_check_edp(intel_dp); 585 msg[0] = DP_AUX_NATIVE_WRITE << 4; 586 msg[1] = address >> 8; 587 msg[2] = address & 0xff; 588 msg[3] = send_bytes - 1; 589 memcpy(&msg[4], send, send_bytes); 590 msg_bytes = send_bytes + 4; 591 for (;;) { 592 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes, &ack, 1); 593 if (ret < 0) 594 return ret; 595 ack >>= 4; 596 if ((ack & DP_AUX_NATIVE_REPLY_MASK) == DP_AUX_NATIVE_REPLY_ACK) 597 break; 598 else if ((ack & DP_AUX_NATIVE_REPLY_MASK) == DP_AUX_NATIVE_REPLY_DEFER) 599 udelay(100); 600 else 601 return -EIO; 602 } 603 return send_bytes; 604} 605 606/* Write a single byte to the aux channel in native mode */ 607static int 608intel_dp_aux_native_write_1(struct intel_dp *intel_dp, 609 uint16_t address, uint8_t byte) 610{ 611 return intel_dp_aux_native_write(intel_dp, address, &byte, 1); 612} 613 614/* read bytes from a native aux channel */ 615static int 616intel_dp_aux_native_read(struct intel_dp *intel_dp, 617 uint16_t address, uint8_t *recv, int recv_bytes) 618{ 619 uint8_t msg[4]; 620 int msg_bytes; 621 uint8_t reply[20]; 622 int reply_bytes; 623 uint8_t ack; 624 int ret; 625 626 if (WARN_ON(recv_bytes > 19)) 627 return -E2BIG; 628 629 intel_dp_check_edp(intel_dp); 630 msg[0] = DP_AUX_NATIVE_READ << 4; 631 msg[1] = address >> 8; 632 msg[2] = address & 0xff; 633 msg[3] = recv_bytes - 1; 634 635 msg_bytes = 4; 636 reply_bytes = recv_bytes + 1; 637 638 for (;;) { 639 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes, 640 reply, reply_bytes); 641 if (ret == 0) 642 return -EPROTO; 643 if (ret < 0) 644 return ret; 645 ack = reply[0] >> 4; 646 if ((ack & DP_AUX_NATIVE_REPLY_MASK) == DP_AUX_NATIVE_REPLY_ACK) { 647 memcpy(recv, reply + 1, ret - 1); 648 return ret - 1; 649 } 650 else if ((ack & DP_AUX_NATIVE_REPLY_MASK) == DP_AUX_NATIVE_REPLY_DEFER) 651 udelay(100); 652 else 653 return -EIO; 654 } 655} 656 657static int 658intel_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode, 659 uint8_t write_byte, uint8_t *read_byte) 660{ 661 struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data; 662 struct intel_dp *intel_dp = container_of(adapter, 663 struct intel_dp, 664 adapter); 665 uint16_t address = algo_data->address; 666 uint8_t msg[5]; 667 uint8_t reply[2]; 668 unsigned retry; 669 int msg_bytes; 670 int reply_bytes; 671 int ret; 672 673 edp_panel_vdd_on(intel_dp); 674 intel_dp_check_edp(intel_dp); 675 /* Set up the command byte */ 676 if (mode & MODE_I2C_READ) 677 msg[0] = DP_AUX_I2C_READ << 4; 678 else 679 msg[0] = DP_AUX_I2C_WRITE << 4; 680 681 if (!(mode & MODE_I2C_STOP)) 682 msg[0] |= DP_AUX_I2C_MOT << 4; 683 684 msg[1] = address >> 8; 685 msg[2] = address; 686 687 switch (mode) { 688 case MODE_I2C_WRITE: 689 msg[3] = 0; 690 msg[4] = write_byte; 691 msg_bytes = 5; 692 reply_bytes = 1; 693 break; 694 case MODE_I2C_READ: 695 msg[3] = 0; 696 msg_bytes = 4; 697 reply_bytes = 2; 698 break; 699 default: 700 msg_bytes = 3; 701 reply_bytes = 1; 702 break; 703 } 704 705 /* 706 * DP1.2 sections 2.7.7.1.5.6.1 and 2.7.7.1.6.6.1: A DP Source device is 707 * required to retry at least seven times upon receiving AUX_DEFER 708 * before giving up the AUX transaction. 709 */ 710 for (retry = 0; retry < 7; retry++) { 711 ret = intel_dp_aux_ch(intel_dp, 712 msg, msg_bytes, 713 reply, reply_bytes); 714 if (ret < 0) { 715 DRM_DEBUG_KMS("aux_ch failed %d\n", ret); 716 goto out; 717 } 718 719 switch ((reply[0] >> 4) & DP_AUX_NATIVE_REPLY_MASK) { 720 case DP_AUX_NATIVE_REPLY_ACK: 721 /* I2C-over-AUX Reply field is only valid 722 * when paired with AUX ACK. 723 */ 724 break; 725 case DP_AUX_NATIVE_REPLY_NACK: 726 DRM_DEBUG_KMS("aux_ch native nack\n"); 727 ret = -EREMOTEIO; 728 goto out; 729 case DP_AUX_NATIVE_REPLY_DEFER: 730 /* 731 * For now, just give more slack to branch devices. We 732 * could check the DPCD for I2C bit rate capabilities, 733 * and if available, adjust the interval. We could also 734 * be more careful with DP-to-Legacy adapters where a 735 * long legacy cable may force very low I2C bit rates. 736 */ 737 if (intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] & 738 DP_DWN_STRM_PORT_PRESENT) 739 usleep_range(500, 600); 740 else 741 usleep_range(300, 400); 742 continue; 743 default: 744 DRM_ERROR("aux_ch invalid native reply 0x%02x\n", 745 reply[0]); 746 ret = -EREMOTEIO; 747 goto out; 748 } 749 750 switch ((reply[0] >> 4) & DP_AUX_I2C_REPLY_MASK) { 751 case DP_AUX_I2C_REPLY_ACK: 752 if (mode == MODE_I2C_READ) { 753 *read_byte = reply[1]; 754 } 755 ret = reply_bytes - 1; 756 goto out; 757 case DP_AUX_I2C_REPLY_NACK: 758 DRM_DEBUG_KMS("aux_i2c nack\n"); 759 ret = -EREMOTEIO; 760 goto out; 761 case DP_AUX_I2C_REPLY_DEFER: 762 DRM_DEBUG_KMS("aux_i2c defer\n"); 763 udelay(100); 764 break; 765 default: 766 DRM_ERROR("aux_i2c invalid reply 0x%02x\n", reply[0]); 767 ret = -EREMOTEIO; 768 goto out; 769 } 770 } 771 772 DRM_ERROR("too many retries, giving up\n"); 773 ret = -EREMOTEIO; 774 775out: 776 edp_panel_vdd_off(intel_dp, false); 777 return ret; 778} 779 780static void 781intel_dp_connector_unregister(struct intel_connector *intel_connector) 782{ 783 struct intel_dp *intel_dp = intel_attached_dp(&intel_connector->base); 784 785 sysfs_remove_link(&intel_connector->base.kdev->kobj, 786 intel_dp->adapter.dev.kobj.name); 787 intel_connector_unregister(intel_connector); 788} 789 790static int 791intel_dp_i2c_init(struct intel_dp *intel_dp, 792 struct intel_connector *intel_connector, const char *name) 793{ 794 int ret; 795 796 DRM_DEBUG_KMS("i2c_init %s\n", name); 797 intel_dp->algo.running = false; 798 intel_dp->algo.address = 0; 799 intel_dp->algo.aux_ch = intel_dp_i2c_aux_ch; 800 801 memset(&intel_dp->adapter, '\0', sizeof(intel_dp->adapter)); 802 intel_dp->adapter.owner = THIS_MODULE; 803 intel_dp->adapter.class = I2C_CLASS_DDC; 804 strncpy(intel_dp->adapter.name, name, sizeof(intel_dp->adapter.name) - 1); 805 intel_dp->adapter.name[sizeof(intel_dp->adapter.name) - 1] = '\0'; 806 intel_dp->adapter.algo_data = &intel_dp->algo; 807 intel_dp->adapter.dev.parent = intel_connector->base.dev->dev; 808 809 ret = i2c_dp_aux_add_bus(&intel_dp->adapter); 810 if (ret < 0) 811 return ret; 812 813 ret = sysfs_create_link(&intel_connector->base.kdev->kobj, 814 &intel_dp->adapter.dev.kobj, 815 intel_dp->adapter.dev.kobj.name); 816 817 if (ret < 0) 818 i2c_del_adapter(&intel_dp->adapter); 819 820 return ret; 821} 822 823static void 824intel_dp_set_clock(struct intel_encoder *encoder, 825 struct intel_crtc_config *pipe_config, int link_bw) 826{ 827 struct drm_device *dev = encoder->base.dev; 828 const struct dp_link_dpll *divisor = NULL; 829 int i, count = 0; 830 831 if (IS_G4X(dev)) { 832 divisor = gen4_dpll; 833 count = ARRAY_SIZE(gen4_dpll); 834 } else if (IS_HASWELL(dev)) { 835 /* Haswell has special-purpose DP DDI clocks. */ 836 } else if (HAS_PCH_SPLIT(dev)) { 837 divisor = pch_dpll; 838 count = ARRAY_SIZE(pch_dpll); 839 } else if (IS_VALLEYVIEW(dev)) { 840 divisor = vlv_dpll; 841 count = ARRAY_SIZE(vlv_dpll); 842 } 843 844 if (divisor && count) { 845 for (i = 0; i < count; i++) { 846 if (link_bw == divisor[i].link_bw) { 847 pipe_config->dpll = divisor[i].dpll; 848 pipe_config->clock_set = true; 849 break; 850 } 851 } 852 } 853} 854 855bool 856intel_dp_compute_config(struct intel_encoder *encoder, 857 struct intel_crtc_config *pipe_config) 858{ 859 struct drm_device *dev = encoder->base.dev; 860 struct drm_i915_private *dev_priv = dev->dev_private; 861 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode; 862 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); 863 enum port port = dp_to_dig_port(intel_dp)->port; 864 struct intel_crtc *intel_crtc = encoder->new_crtc; 865 struct intel_connector *intel_connector = intel_dp->attached_connector; 866 int lane_count, clock; 867 int max_lane_count = drm_dp_max_lane_count(intel_dp->dpcd); 868 /* Conveniently, the link BW constants become indices with a shift...*/ 869 int max_clock = intel_dp_max_link_bw(intel_dp) >> 3; 870 int bpp, mode_rate; 871 static int bws[] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7, DP_LINK_BW_5_4 }; 872 int link_avail, link_clock; 873 874 if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev) && port != PORT_A) 875 pipe_config->has_pch_encoder = true; 876 877 pipe_config->has_dp_encoder = true; 878 879 if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) { 880 intel_fixed_panel_mode(intel_connector->panel.fixed_mode, 881 adjusted_mode); 882 if (!HAS_PCH_SPLIT(dev)) 883 intel_gmch_panel_fitting(intel_crtc, pipe_config, 884 intel_connector->panel.fitting_mode); 885 else 886 intel_pch_panel_fitting(intel_crtc, pipe_config, 887 intel_connector->panel.fitting_mode); 888 } 889 890 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK) 891 return false; 892 893 DRM_DEBUG_KMS("DP link computation with max lane count %i " 894 "max bw %02x pixel clock %iKHz\n", 895 max_lane_count, bws[max_clock], 896 adjusted_mode->crtc_clock); 897 898 /* Walk through all bpp values. Luckily they're all nicely spaced with 2 899 * bpc in between. */ 900 bpp = pipe_config->pipe_bpp; 901 if (is_edp(intel_dp) && dev_priv->vbt.edp_bpp && 902 dev_priv->vbt.edp_bpp < bpp) { 903 DRM_DEBUG_KMS("clamping bpp for eDP panel to BIOS-provided %i\n", 904 dev_priv->vbt.edp_bpp); 905 bpp = dev_priv->vbt.edp_bpp; 906 } 907 908 for (; bpp >= 6*3; bpp -= 2*3) { 909 mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock, 910 bpp); 911 912 for (clock = 0; clock <= max_clock; clock++) { 913 for (lane_count = 1; lane_count <= max_lane_count; lane_count <<= 1) { 914 link_clock = drm_dp_bw_code_to_link_rate(bws[clock]); 915 link_avail = intel_dp_max_data_rate(link_clock, 916 lane_count); 917 918 if (mode_rate <= link_avail) { 919 goto found; 920 } 921 } 922 } 923 } 924 925 return false; 926 927found: 928 if (intel_dp->color_range_auto) { 929 /* 930 * See: 931 * CEA-861-E - 5.1 Default Encoding Parameters 932 * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry 933 */ 934 if (bpp != 18 && drm_match_cea_mode(adjusted_mode) > 1) 935 intel_dp->color_range = DP_COLOR_RANGE_16_235; 936 else 937 intel_dp->color_range = 0; 938 } 939 940 if (intel_dp->color_range) 941 pipe_config->limited_color_range = true; 942 943 intel_dp->link_bw = bws[clock]; 944 intel_dp->lane_count = lane_count; 945 pipe_config->pipe_bpp = bpp; 946 pipe_config->port_clock = drm_dp_bw_code_to_link_rate(intel_dp->link_bw); 947 948 DRM_DEBUG_KMS("DP link bw %02x lane count %d clock %d bpp %d\n", 949 intel_dp->link_bw, intel_dp->lane_count, 950 pipe_config->port_clock, bpp); 951 DRM_DEBUG_KMS("DP link bw required %i available %i\n", 952 mode_rate, link_avail); 953 954 intel_link_compute_m_n(bpp, lane_count, 955 adjusted_mode->crtc_clock, 956 pipe_config->port_clock, 957 &pipe_config->dp_m_n); 958 959 intel_dp_set_clock(encoder, pipe_config, intel_dp->link_bw); 960 961 return true; 962} 963 964static void ironlake_set_pll_cpu_edp(struct intel_dp *intel_dp) 965{ 966 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 967 struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc); 968 struct drm_device *dev = crtc->base.dev; 969 struct drm_i915_private *dev_priv = dev->dev_private; 970 u32 dpa_ctl; 971 972 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", crtc->config.port_clock); 973 dpa_ctl = I915_READ(DP_A); 974 dpa_ctl &= ~DP_PLL_FREQ_MASK; 975 976 if (crtc->config.port_clock == 162000) { 977 /* For a long time we've carried around a ILK-DevA w/a for the 978 * 160MHz clock. If we're really unlucky, it's still required. 979 */ 980 DRM_DEBUG_KMS("160MHz cpu eDP clock, might need ilk devA w/a\n"); 981 dpa_ctl |= DP_PLL_FREQ_160MHZ; 982 intel_dp->DP |= DP_PLL_FREQ_160MHZ; 983 } else { 984 dpa_ctl |= DP_PLL_FREQ_270MHZ; 985 intel_dp->DP |= DP_PLL_FREQ_270MHZ; 986 } 987 988 I915_WRITE(DP_A, dpa_ctl); 989 990 POSTING_READ(DP_A); 991 udelay(500); 992} 993 994static void intel_dp_mode_set(struct intel_encoder *encoder) 995{ 996 struct drm_device *dev = encoder->base.dev; 997 struct drm_i915_private *dev_priv = dev->dev_private; 998 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); 999 enum port port = dp_to_dig_port(intel_dp)->port; 1000 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); 1001 struct drm_display_mode *adjusted_mode = &crtc->config.adjusted_mode; 1002 1003 /* 1004 * There are four kinds of DP registers: 1005 * 1006 * IBX PCH 1007 * SNB CPU 1008 * IVB CPU 1009 * CPT PCH 1010 * 1011 * IBX PCH and CPU are the same for almost everything, 1012 * except that the CPU DP PLL is configured in this 1013 * register 1014 * 1015 * CPT PCH is quite different, having many bits moved 1016 * to the TRANS_DP_CTL register instead. That 1017 * configuration happens (oddly) in ironlake_pch_enable 1018 */ 1019 1020 /* Preserve the BIOS-computed detected bit. This is 1021 * supposed to be read-only. 1022 */ 1023 intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED; 1024 1025 /* Handle DP bits in common between all three register formats */ 1026 intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0; 1027 intel_dp->DP |= DP_PORT_WIDTH(intel_dp->lane_count); 1028 1029 if (intel_dp->has_audio) { 1030 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n", 1031 pipe_name(crtc->pipe)); 1032 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE; 1033 intel_write_eld(&encoder->base, adjusted_mode); 1034 } 1035 1036 /* Split out the IBX/CPU vs CPT settings */ 1037 1038 if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) { 1039 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) 1040 intel_dp->DP |= DP_SYNC_HS_HIGH; 1041 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) 1042 intel_dp->DP |= DP_SYNC_VS_HIGH; 1043 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT; 1044 1045 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd)) 1046 intel_dp->DP |= DP_ENHANCED_FRAMING; 1047 1048 intel_dp->DP |= crtc->pipe << 29; 1049 } else if (!HAS_PCH_CPT(dev) || port == PORT_A) { 1050 if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev)) 1051 intel_dp->DP |= intel_dp->color_range; 1052 1053 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) 1054 intel_dp->DP |= DP_SYNC_HS_HIGH; 1055 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) 1056 intel_dp->DP |= DP_SYNC_VS_HIGH; 1057 intel_dp->DP |= DP_LINK_TRAIN_OFF; 1058 1059 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd)) 1060 intel_dp->DP |= DP_ENHANCED_FRAMING; 1061 1062 if (crtc->pipe == 1) 1063 intel_dp->DP |= DP_PIPEB_SELECT; 1064 } else { 1065 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT; 1066 } 1067 1068 if (port == PORT_A && !IS_VALLEYVIEW(dev)) 1069 ironlake_set_pll_cpu_edp(intel_dp); 1070} 1071 1072#define IDLE_ON_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK) 1073#define IDLE_ON_VALUE (PP_ON | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE) 1074 1075#define IDLE_OFF_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | 0) 1076#define IDLE_OFF_VALUE (0 | PP_SEQUENCE_NONE | 0 | 0) 1077 1078#define IDLE_CYCLE_MASK (PP_ON | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK) 1079#define IDLE_CYCLE_VALUE (0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE) 1080 1081static void wait_panel_status(struct intel_dp *intel_dp, 1082 u32 mask, 1083 u32 value) 1084{ 1085 struct drm_device *dev = intel_dp_to_dev(intel_dp); 1086 struct drm_i915_private *dev_priv = dev->dev_private; 1087 u32 pp_stat_reg, pp_ctrl_reg; 1088 1089 pp_stat_reg = _pp_stat_reg(intel_dp); 1090 pp_ctrl_reg = _pp_ctrl_reg(intel_dp); 1091 1092 DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n", 1093 mask, value, 1094 I915_READ(pp_stat_reg), 1095 I915_READ(pp_ctrl_reg)); 1096 1097 if (_wait_for((I915_READ(pp_stat_reg) & mask) == value, 5000, 10)) { 1098 DRM_ERROR("Panel status timeout: status %08x control %08x\n", 1099 I915_READ(pp_stat_reg), 1100 I915_READ(pp_ctrl_reg)); 1101 } 1102 1103 DRM_DEBUG_KMS("Wait complete\n"); 1104} 1105 1106static void wait_panel_on(struct intel_dp *intel_dp) 1107{ 1108 DRM_DEBUG_KMS("Wait for panel power on\n"); 1109 wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE); 1110} 1111 1112static void wait_panel_off(struct intel_dp *intel_dp) 1113{ 1114 DRM_DEBUG_KMS("Wait for panel power off time\n"); 1115 wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE); 1116} 1117 1118static void wait_panel_power_cycle(struct intel_dp *intel_dp) 1119{ 1120 DRM_DEBUG_KMS("Wait for panel power cycle\n"); 1121 1122 /* When we disable the VDD override bit last we have to do the manual 1123 * wait. */ 1124 wait_remaining_ms_from_jiffies(intel_dp->last_power_cycle, 1125 intel_dp->panel_power_cycle_delay); 1126 1127 wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE); 1128} 1129 1130static void wait_backlight_on(struct intel_dp *intel_dp) 1131{ 1132 wait_remaining_ms_from_jiffies(intel_dp->last_power_on, 1133 intel_dp->backlight_on_delay); 1134} 1135 1136static void edp_wait_backlight_off(struct intel_dp *intel_dp) 1137{ 1138 wait_remaining_ms_from_jiffies(intel_dp->last_backlight_off, 1139 intel_dp->backlight_off_delay); 1140} 1141 1142/* Read the current pp_control value, unlocking the register if it 1143 * is locked 1144 */ 1145 1146static u32 ironlake_get_pp_control(struct intel_dp *intel_dp) 1147{ 1148 struct drm_device *dev = intel_dp_to_dev(intel_dp); 1149 struct drm_i915_private *dev_priv = dev->dev_private; 1150 u32 control; 1151 1152 control = I915_READ(_pp_ctrl_reg(intel_dp)); 1153 control &= ~PANEL_UNLOCK_MASK; 1154 control |= PANEL_UNLOCK_REGS; 1155 return control; 1156} 1157 1158static void edp_panel_vdd_on(struct intel_dp *intel_dp) 1159{ 1160 struct drm_device *dev = intel_dp_to_dev(intel_dp); 1161 struct drm_i915_private *dev_priv = dev->dev_private; 1162 u32 pp; 1163 u32 pp_stat_reg, pp_ctrl_reg; 1164 1165 if (!is_edp(intel_dp)) 1166 return; 1167 1168 WARN(intel_dp->want_panel_vdd, 1169 "eDP VDD already requested on\n"); 1170 1171 intel_dp->want_panel_vdd = true; 1172 1173 if (edp_have_panel_vdd(intel_dp)) 1174 return; 1175 1176 intel_runtime_pm_get(dev_priv); 1177 1178 DRM_DEBUG_KMS("Turning eDP VDD on\n"); 1179 1180 if (!edp_have_panel_power(intel_dp)) 1181 wait_panel_power_cycle(intel_dp); 1182 1183 pp = ironlake_get_pp_control(intel_dp); 1184 pp |= EDP_FORCE_VDD; 1185 1186 pp_stat_reg = _pp_stat_reg(intel_dp); 1187 pp_ctrl_reg = _pp_ctrl_reg(intel_dp); 1188 1189 I915_WRITE(pp_ctrl_reg, pp); 1190 POSTING_READ(pp_ctrl_reg); 1191 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n", 1192 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg)); 1193 /* 1194 * If the panel wasn't on, delay before accessing aux channel 1195 */ 1196 if (!edp_have_panel_power(intel_dp)) { 1197 DRM_DEBUG_KMS("eDP was not running\n"); 1198 msleep(intel_dp->panel_power_up_delay); 1199 } 1200} 1201 1202static void edp_panel_vdd_off_sync(struct intel_dp *intel_dp) 1203{ 1204 struct drm_device *dev = intel_dp_to_dev(intel_dp); 1205 struct drm_i915_private *dev_priv = dev->dev_private; 1206 u32 pp; 1207 u32 pp_stat_reg, pp_ctrl_reg; 1208 1209 WARN_ON(!mutex_is_locked(&dev->mode_config.mutex)); 1210 1211 if (!intel_dp->want_panel_vdd && edp_have_panel_vdd(intel_dp)) { 1212 DRM_DEBUG_KMS("Turning eDP VDD off\n"); 1213 1214 pp = ironlake_get_pp_control(intel_dp); 1215 pp &= ~EDP_FORCE_VDD; 1216 1217 pp_ctrl_reg = _pp_ctrl_reg(intel_dp); 1218 pp_stat_reg = _pp_stat_reg(intel_dp); 1219 1220 I915_WRITE(pp_ctrl_reg, pp); 1221 POSTING_READ(pp_ctrl_reg); 1222 1223 /* Make sure sequencer is idle before allowing subsequent activity */ 1224 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n", 1225 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg)); 1226 1227 if ((pp & POWER_TARGET_ON) == 0) 1228 intel_dp->last_power_cycle = jiffies; 1229 1230 intel_runtime_pm_put(dev_priv); 1231 } 1232} 1233 1234static void edp_panel_vdd_work(struct work_struct *__work) 1235{ 1236 struct intel_dp *intel_dp = container_of(to_delayed_work(__work), 1237 struct intel_dp, panel_vdd_work); 1238 struct drm_device *dev = intel_dp_to_dev(intel_dp); 1239 1240 mutex_lock(&dev->mode_config.mutex); 1241 edp_panel_vdd_off_sync(intel_dp); 1242 mutex_unlock(&dev->mode_config.mutex); 1243} 1244 1245static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync) 1246{ 1247 if (!is_edp(intel_dp)) 1248 return; 1249 1250 WARN(!intel_dp->want_panel_vdd, "eDP VDD not forced on"); 1251 1252 intel_dp->want_panel_vdd = false; 1253 1254 if (sync) { 1255 edp_panel_vdd_off_sync(intel_dp); 1256 } else { 1257 /* 1258 * Queue the timer to fire a long 1259 * time from now (relative to the power down delay) 1260 * to keep the panel power up across a sequence of operations 1261 */ 1262 schedule_delayed_work(&intel_dp->panel_vdd_work, 1263 msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5)); 1264 } 1265} 1266 1267void intel_edp_panel_on(struct intel_dp *intel_dp) 1268{ 1269 struct drm_device *dev = intel_dp_to_dev(intel_dp); 1270 struct drm_i915_private *dev_priv = dev->dev_private; 1271 u32 pp; 1272 u32 pp_ctrl_reg; 1273 1274 if (!is_edp(intel_dp)) 1275 return; 1276 1277 DRM_DEBUG_KMS("Turn eDP power on\n"); 1278 1279 if (edp_have_panel_power(intel_dp)) { 1280 DRM_DEBUG_KMS("eDP power already on\n"); 1281 return; 1282 } 1283 1284 wait_panel_power_cycle(intel_dp); 1285 1286 pp_ctrl_reg = _pp_ctrl_reg(intel_dp); 1287 pp = ironlake_get_pp_control(intel_dp); 1288 if (IS_GEN5(dev)) { 1289 /* ILK workaround: disable reset around power sequence */ 1290 pp &= ~PANEL_POWER_RESET; 1291 I915_WRITE(pp_ctrl_reg, pp); 1292 POSTING_READ(pp_ctrl_reg); 1293 } 1294 1295 pp |= POWER_TARGET_ON; 1296 if (!IS_GEN5(dev)) 1297 pp |= PANEL_POWER_RESET; 1298 1299 I915_WRITE(pp_ctrl_reg, pp); 1300 POSTING_READ(pp_ctrl_reg); 1301 1302 wait_panel_on(intel_dp); 1303 intel_dp->last_power_on = jiffies; 1304 1305 if (IS_GEN5(dev)) { 1306 pp |= PANEL_POWER_RESET; /* restore panel reset bit */ 1307 I915_WRITE(pp_ctrl_reg, pp); 1308 POSTING_READ(pp_ctrl_reg); 1309 } 1310} 1311 1312void intel_edp_panel_off(struct intel_dp *intel_dp) 1313{ 1314 struct drm_device *dev = intel_dp_to_dev(intel_dp); 1315 struct drm_i915_private *dev_priv = dev->dev_private; 1316 u32 pp; 1317 u32 pp_ctrl_reg; 1318 1319 if (!is_edp(intel_dp)) 1320 return; 1321 1322 DRM_DEBUG_KMS("Turn eDP power off\n"); 1323 1324 edp_wait_backlight_off(intel_dp); 1325 1326 pp = ironlake_get_pp_control(intel_dp); 1327 /* We need to switch off panel power _and_ force vdd, for otherwise some 1328 * panels get very unhappy and cease to work. */ 1329 pp &= ~(POWER_TARGET_ON | PANEL_POWER_RESET | EDP_FORCE_VDD | 1330 EDP_BLC_ENABLE); 1331 1332 pp_ctrl_reg = _pp_ctrl_reg(intel_dp); 1333 1334 I915_WRITE(pp_ctrl_reg, pp); 1335 POSTING_READ(pp_ctrl_reg); 1336 1337 intel_dp->last_power_cycle = jiffies; 1338 wait_panel_off(intel_dp); 1339} 1340 1341void intel_edp_backlight_on(struct intel_dp *intel_dp) 1342{ 1343 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 1344 struct drm_device *dev = intel_dig_port->base.base.dev; 1345 struct drm_i915_private *dev_priv = dev->dev_private; 1346 u32 pp; 1347 u32 pp_ctrl_reg; 1348 1349 if (!is_edp(intel_dp)) 1350 return; 1351 1352 DRM_DEBUG_KMS("\n"); 1353 /* 1354 * If we enable the backlight right away following a panel power 1355 * on, we may see slight flicker as the panel syncs with the eDP 1356 * link. So delay a bit to make sure the image is solid before 1357 * allowing it to appear. 1358 */ 1359 wait_backlight_on(intel_dp); 1360 pp = ironlake_get_pp_control(intel_dp); 1361 pp |= EDP_BLC_ENABLE; 1362 1363 pp_ctrl_reg = _pp_ctrl_reg(intel_dp); 1364 1365 I915_WRITE(pp_ctrl_reg, pp); 1366 POSTING_READ(pp_ctrl_reg); 1367 1368 intel_panel_enable_backlight(intel_dp->attached_connector); 1369} 1370 1371void intel_edp_backlight_off(struct intel_dp *intel_dp) 1372{ 1373 struct drm_device *dev = intel_dp_to_dev(intel_dp); 1374 struct drm_i915_private *dev_priv = dev->dev_private; 1375 u32 pp; 1376 u32 pp_ctrl_reg; 1377 1378 if (!is_edp(intel_dp)) 1379 return; 1380 1381 intel_panel_disable_backlight(intel_dp->attached_connector); 1382 1383 DRM_DEBUG_KMS("\n"); 1384 pp = ironlake_get_pp_control(intel_dp); 1385 pp &= ~EDP_BLC_ENABLE; 1386 1387 pp_ctrl_reg = _pp_ctrl_reg(intel_dp); 1388 1389 I915_WRITE(pp_ctrl_reg, pp); 1390 POSTING_READ(pp_ctrl_reg); 1391 intel_dp->last_backlight_off = jiffies; 1392} 1393 1394static void ironlake_edp_pll_on(struct intel_dp *intel_dp) 1395{ 1396 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 1397 struct drm_crtc *crtc = intel_dig_port->base.base.crtc; 1398 struct drm_device *dev = crtc->dev; 1399 struct drm_i915_private *dev_priv = dev->dev_private; 1400 u32 dpa_ctl; 1401 1402 assert_pipe_disabled(dev_priv, 1403 to_intel_crtc(crtc)->pipe); 1404 1405 DRM_DEBUG_KMS("\n"); 1406 dpa_ctl = I915_READ(DP_A); 1407 WARN(dpa_ctl & DP_PLL_ENABLE, "dp pll on, should be off\n"); 1408 WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n"); 1409 1410 /* We don't adjust intel_dp->DP while tearing down the link, to 1411 * facilitate link retraining (e.g. after hotplug). Hence clear all 1412 * enable bits here to ensure that we don't enable too much. */ 1413 intel_dp->DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE); 1414 intel_dp->DP |= DP_PLL_ENABLE; 1415 I915_WRITE(DP_A, intel_dp->DP); 1416 POSTING_READ(DP_A); 1417 udelay(200); 1418} 1419 1420static void ironlake_edp_pll_off(struct intel_dp *intel_dp) 1421{ 1422 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 1423 struct drm_crtc *crtc = intel_dig_port->base.base.crtc; 1424 struct drm_device *dev = crtc->dev; 1425 struct drm_i915_private *dev_priv = dev->dev_private; 1426 u32 dpa_ctl; 1427 1428 assert_pipe_disabled(dev_priv, 1429 to_intel_crtc(crtc)->pipe); 1430 1431 dpa_ctl = I915_READ(DP_A); 1432 WARN((dpa_ctl & DP_PLL_ENABLE) == 0, 1433 "dp pll off, should be on\n"); 1434 WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n"); 1435 1436 /* We can't rely on the value tracked for the DP register in 1437 * intel_dp->DP because link_down must not change that (otherwise link 1438 * re-training will fail. */ 1439 dpa_ctl &= ~DP_PLL_ENABLE; 1440 I915_WRITE(DP_A, dpa_ctl); 1441 POSTING_READ(DP_A); 1442 udelay(200); 1443} 1444 1445/* If the sink supports it, try to set the power state appropriately */ 1446void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode) 1447{ 1448 int ret, i; 1449 1450 /* Should have a valid DPCD by this point */ 1451 if (intel_dp->dpcd[DP_DPCD_REV] < 0x11) 1452 return; 1453 1454 if (mode != DRM_MODE_DPMS_ON) { 1455 ret = intel_dp_aux_native_write_1(intel_dp, DP_SET_POWER, 1456 DP_SET_POWER_D3); 1457 if (ret != 1) 1458 DRM_DEBUG_DRIVER("failed to write sink power state\n"); 1459 } else { 1460 /* 1461 * When turning on, we need to retry for 1ms to give the sink 1462 * time to wake up. 1463 */ 1464 for (i = 0; i < 3; i++) { 1465 ret = intel_dp_aux_native_write_1(intel_dp, 1466 DP_SET_POWER, 1467 DP_SET_POWER_D0); 1468 if (ret == 1) 1469 break; 1470 msleep(1); 1471 } 1472 } 1473} 1474 1475static bool intel_dp_get_hw_state(struct intel_encoder *encoder, 1476 enum pipe *pipe) 1477{ 1478 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); 1479 enum port port = dp_to_dig_port(intel_dp)->port; 1480 struct drm_device *dev = encoder->base.dev; 1481 struct drm_i915_private *dev_priv = dev->dev_private; 1482 u32 tmp = I915_READ(intel_dp->output_reg); 1483 1484 if (!(tmp & DP_PORT_EN)) 1485 return false; 1486 1487 if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) { 1488 *pipe = PORT_TO_PIPE_CPT(tmp); 1489 } else if (!HAS_PCH_CPT(dev) || port == PORT_A) { 1490 *pipe = PORT_TO_PIPE(tmp); 1491 } else { 1492 u32 trans_sel; 1493 u32 trans_dp; 1494 int i; 1495 1496 switch (intel_dp->output_reg) { 1497 case PCH_DP_B: 1498 trans_sel = TRANS_DP_PORT_SEL_B; 1499 break; 1500 case PCH_DP_C: 1501 trans_sel = TRANS_DP_PORT_SEL_C; 1502 break; 1503 case PCH_DP_D: 1504 trans_sel = TRANS_DP_PORT_SEL_D; 1505 break; 1506 default: 1507 return true; 1508 } 1509 1510 for_each_pipe(i) { 1511 trans_dp = I915_READ(TRANS_DP_CTL(i)); 1512 if ((trans_dp & TRANS_DP_PORT_SEL_MASK) == trans_sel) { 1513 *pipe = i; 1514 return true; 1515 } 1516 } 1517 1518 DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n", 1519 intel_dp->output_reg); 1520 } 1521 1522 return true; 1523} 1524 1525static void intel_dp_get_config(struct intel_encoder *encoder, 1526 struct intel_crtc_config *pipe_config) 1527{ 1528 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); 1529 u32 tmp, flags = 0; 1530 struct drm_device *dev = encoder->base.dev; 1531 struct drm_i915_private *dev_priv = dev->dev_private; 1532 enum port port = dp_to_dig_port(intel_dp)->port; 1533 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); 1534 int dotclock; 1535 1536 if ((port == PORT_A) || !HAS_PCH_CPT(dev)) { 1537 tmp = I915_READ(intel_dp->output_reg); 1538 if (tmp & DP_SYNC_HS_HIGH) 1539 flags |= DRM_MODE_FLAG_PHSYNC; 1540 else 1541 flags |= DRM_MODE_FLAG_NHSYNC; 1542 1543 if (tmp & DP_SYNC_VS_HIGH) 1544 flags |= DRM_MODE_FLAG_PVSYNC; 1545 else 1546 flags |= DRM_MODE_FLAG_NVSYNC; 1547 } else { 1548 tmp = I915_READ(TRANS_DP_CTL(crtc->pipe)); 1549 if (tmp & TRANS_DP_HSYNC_ACTIVE_HIGH) 1550 flags |= DRM_MODE_FLAG_PHSYNC; 1551 else 1552 flags |= DRM_MODE_FLAG_NHSYNC; 1553 1554 if (tmp & TRANS_DP_VSYNC_ACTIVE_HIGH) 1555 flags |= DRM_MODE_FLAG_PVSYNC; 1556 else 1557 flags |= DRM_MODE_FLAG_NVSYNC; 1558 } 1559 1560 pipe_config->adjusted_mode.flags |= flags; 1561 1562 pipe_config->has_dp_encoder = true; 1563 1564 intel_dp_get_m_n(crtc, pipe_config); 1565 1566 if (port == PORT_A) { 1567 if ((I915_READ(DP_A) & DP_PLL_FREQ_MASK) == DP_PLL_FREQ_160MHZ) 1568 pipe_config->port_clock = 162000; 1569 else 1570 pipe_config->port_clock = 270000; 1571 } 1572 1573 dotclock = intel_dotclock_calculate(pipe_config->port_clock, 1574 &pipe_config->dp_m_n); 1575 1576 if (HAS_PCH_SPLIT(dev_priv->dev) && port != PORT_A) 1577 ironlake_check_encoder_dotclock(pipe_config, dotclock); 1578 1579 pipe_config->adjusted_mode.crtc_clock = dotclock; 1580 1581 if (is_edp(intel_dp) && dev_priv->vbt.edp_bpp && 1582 pipe_config->pipe_bpp > dev_priv->vbt.edp_bpp) { 1583 /* 1584 * This is a big fat ugly hack. 1585 * 1586 * Some machines in UEFI boot mode provide us a VBT that has 18 1587 * bpp and 1.62 GHz link bandwidth for eDP, which for reasons 1588 * unknown we fail to light up. Yet the same BIOS boots up with 1589 * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as 1590 * max, not what it tells us to use. 1591 * 1592 * Note: This will still be broken if the eDP panel is not lit 1593 * up by the BIOS, and thus we can't get the mode at module 1594 * load. 1595 */ 1596 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n", 1597 pipe_config->pipe_bpp, dev_priv->vbt.edp_bpp); 1598 dev_priv->vbt.edp_bpp = pipe_config->pipe_bpp; 1599 } 1600} 1601 1602static bool is_edp_psr(struct drm_device *dev) 1603{ 1604 struct drm_i915_private *dev_priv = dev->dev_private; 1605 1606 return dev_priv->psr.sink_support; 1607} 1608 1609static bool intel_edp_is_psr_enabled(struct drm_device *dev) 1610{ 1611 struct drm_i915_private *dev_priv = dev->dev_private; 1612 1613 if (!HAS_PSR(dev)) 1614 return false; 1615 1616 return I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE; 1617} 1618 1619static void intel_edp_psr_write_vsc(struct intel_dp *intel_dp, 1620 struct edp_vsc_psr *vsc_psr) 1621{ 1622 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 1623 struct drm_device *dev = dig_port->base.base.dev; 1624 struct drm_i915_private *dev_priv = dev->dev_private; 1625 struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc); 1626 u32 ctl_reg = HSW_TVIDEO_DIP_CTL(crtc->config.cpu_transcoder); 1627 u32 data_reg = HSW_TVIDEO_DIP_VSC_DATA(crtc->config.cpu_transcoder); 1628 uint32_t *data = (uint32_t *) vsc_psr; 1629 unsigned int i; 1630 1631 /* As per BSPec (Pipe Video Data Island Packet), we need to disable 1632 the video DIP being updated before program video DIP data buffer 1633 registers for DIP being updated. */ 1634 I915_WRITE(ctl_reg, 0); 1635 POSTING_READ(ctl_reg); 1636 1637 for (i = 0; i < VIDEO_DIP_VSC_DATA_SIZE; i += 4) { 1638 if (i < sizeof(struct edp_vsc_psr)) 1639 I915_WRITE(data_reg + i, *data++); 1640 else 1641 I915_WRITE(data_reg + i, 0); 1642 } 1643 1644 I915_WRITE(ctl_reg, VIDEO_DIP_ENABLE_VSC_HSW); 1645 POSTING_READ(ctl_reg); 1646} 1647 1648static void intel_edp_psr_setup(struct intel_dp *intel_dp) 1649{ 1650 struct drm_device *dev = intel_dp_to_dev(intel_dp); 1651 struct drm_i915_private *dev_priv = dev->dev_private; 1652 struct edp_vsc_psr psr_vsc; 1653 1654 if (intel_dp->psr_setup_done) 1655 return; 1656 1657 /* Prepare VSC packet as per EDP 1.3 spec, Table 3.10 */ 1658 memset(&psr_vsc, 0, sizeof(psr_vsc)); 1659 psr_vsc.sdp_header.HB0 = 0; 1660 psr_vsc.sdp_header.HB1 = 0x7; 1661 psr_vsc.sdp_header.HB2 = 0x2; 1662 psr_vsc.sdp_header.HB3 = 0x8; 1663 intel_edp_psr_write_vsc(intel_dp, &psr_vsc); 1664 1665 /* Avoid continuous PSR exit by masking memup and hpd */ 1666 I915_WRITE(EDP_PSR_DEBUG_CTL(dev), EDP_PSR_DEBUG_MASK_MEMUP | 1667 EDP_PSR_DEBUG_MASK_HPD | EDP_PSR_DEBUG_MASK_LPSP); 1668 1669 intel_dp->psr_setup_done = true; 1670} 1671 1672static void intel_edp_psr_enable_sink(struct intel_dp *intel_dp) 1673{ 1674 struct drm_device *dev = intel_dp_to_dev(intel_dp); 1675 struct drm_i915_private *dev_priv = dev->dev_private; 1676 uint32_t aux_clock_divider; 1677 int precharge = 0x3; 1678 int msg_size = 5; /* Header(4) + Message(1) */ 1679 1680 aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, 0); 1681 1682 /* Enable PSR in sink */ 1683 if (intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT) 1684 intel_dp_aux_native_write_1(intel_dp, DP_PSR_EN_CFG, 1685 DP_PSR_ENABLE & 1686 ~DP_PSR_MAIN_LINK_ACTIVE); 1687 else 1688 intel_dp_aux_native_write_1(intel_dp, DP_PSR_EN_CFG, 1689 DP_PSR_ENABLE | 1690 DP_PSR_MAIN_LINK_ACTIVE); 1691 1692 /* Setup AUX registers */ 1693 I915_WRITE(EDP_PSR_AUX_DATA1(dev), EDP_PSR_DPCD_COMMAND); 1694 I915_WRITE(EDP_PSR_AUX_DATA2(dev), EDP_PSR_DPCD_NORMAL_OPERATION); 1695 I915_WRITE(EDP_PSR_AUX_CTL(dev), 1696 DP_AUX_CH_CTL_TIME_OUT_400us | 1697 (msg_size << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) | 1698 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) | 1699 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT)); 1700} 1701 1702static void intel_edp_psr_enable_source(struct intel_dp *intel_dp) 1703{ 1704 struct drm_device *dev = intel_dp_to_dev(intel_dp); 1705 struct drm_i915_private *dev_priv = dev->dev_private; 1706 uint32_t max_sleep_time = 0x1f; 1707 uint32_t idle_frames = 1; 1708 uint32_t val = 0x0; 1709 const uint32_t link_entry_time = EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES; 1710 1711 if (intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT) { 1712 val |= EDP_PSR_LINK_STANDBY; 1713 val |= EDP_PSR_TP2_TP3_TIME_0us; 1714 val |= EDP_PSR_TP1_TIME_0us; 1715 val |= EDP_PSR_SKIP_AUX_EXIT; 1716 } else 1717 val |= EDP_PSR_LINK_DISABLE; 1718 1719 I915_WRITE(EDP_PSR_CTL(dev), val | 1720 IS_BROADWELL(dev) ? 0 : link_entry_time | 1721 max_sleep_time << EDP_PSR_MAX_SLEEP_TIME_SHIFT | 1722 idle_frames << EDP_PSR_IDLE_FRAME_SHIFT | 1723 EDP_PSR_ENABLE); 1724} 1725 1726static bool intel_edp_psr_match_conditions(struct intel_dp *intel_dp) 1727{ 1728 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 1729 struct drm_device *dev = dig_port->base.base.dev; 1730 struct drm_i915_private *dev_priv = dev->dev_private; 1731 struct drm_crtc *crtc = dig_port->base.base.crtc; 1732 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 1733 struct drm_i915_gem_object *obj = to_intel_framebuffer(crtc->fb)->obj; 1734 struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base; 1735 1736 dev_priv->psr.source_ok = false; 1737 1738 if (!HAS_PSR(dev)) { 1739 DRM_DEBUG_KMS("PSR not supported on this platform\n"); 1740 return false; 1741 } 1742 1743 if ((intel_encoder->type != INTEL_OUTPUT_EDP) || 1744 (dig_port->port != PORT_A)) { 1745 DRM_DEBUG_KMS("HSW ties PSR to DDI A (eDP)\n"); 1746 return false; 1747 } 1748 1749 if (!i915.enable_psr) { 1750 DRM_DEBUG_KMS("PSR disable by flag\n"); 1751 return false; 1752 } 1753 1754 crtc = dig_port->base.base.crtc; 1755 if (crtc == NULL) { 1756 DRM_DEBUG_KMS("crtc not active for PSR\n"); 1757 return false; 1758 } 1759 1760 intel_crtc = to_intel_crtc(crtc); 1761 if (!intel_crtc_active(crtc)) { 1762 DRM_DEBUG_KMS("crtc not active for PSR\n"); 1763 return false; 1764 } 1765 1766 obj = to_intel_framebuffer(crtc->fb)->obj; 1767 if (obj->tiling_mode != I915_TILING_X || 1768 obj->fence_reg == I915_FENCE_REG_NONE) { 1769 DRM_DEBUG_KMS("PSR condition failed: fb not tiled or fenced\n"); 1770 return false; 1771 } 1772 1773 if (I915_READ(SPRCTL(intel_crtc->pipe)) & SPRITE_ENABLE) { 1774 DRM_DEBUG_KMS("PSR condition failed: Sprite is Enabled\n"); 1775 return false; 1776 } 1777 1778 if (I915_READ(HSW_STEREO_3D_CTL(intel_crtc->config.cpu_transcoder)) & 1779 S3D_ENABLE) { 1780 DRM_DEBUG_KMS("PSR condition failed: Stereo 3D is Enabled\n"); 1781 return false; 1782 } 1783 1784 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) { 1785 DRM_DEBUG_KMS("PSR condition failed: Interlaced is Enabled\n"); 1786 return false; 1787 } 1788 1789 dev_priv->psr.source_ok = true; 1790 return true; 1791} 1792 1793static void intel_edp_psr_do_enable(struct intel_dp *intel_dp) 1794{ 1795 struct drm_device *dev = intel_dp_to_dev(intel_dp); 1796 1797 if (!intel_edp_psr_match_conditions(intel_dp) || 1798 intel_edp_is_psr_enabled(dev)) 1799 return; 1800 1801 /* Setup PSR once */ 1802 intel_edp_psr_setup(intel_dp); 1803 1804 /* Enable PSR on the panel */ 1805 intel_edp_psr_enable_sink(intel_dp); 1806 1807 /* Enable PSR on the host */ 1808 intel_edp_psr_enable_source(intel_dp); 1809} 1810 1811void intel_edp_psr_enable(struct intel_dp *intel_dp) 1812{ 1813 struct drm_device *dev = intel_dp_to_dev(intel_dp); 1814 1815 if (intel_edp_psr_match_conditions(intel_dp) && 1816 !intel_edp_is_psr_enabled(dev)) 1817 intel_edp_psr_do_enable(intel_dp); 1818} 1819 1820void intel_edp_psr_disable(struct intel_dp *intel_dp) 1821{ 1822 struct drm_device *dev = intel_dp_to_dev(intel_dp); 1823 struct drm_i915_private *dev_priv = dev->dev_private; 1824 1825 if (!intel_edp_is_psr_enabled(dev)) 1826 return; 1827 1828 I915_WRITE(EDP_PSR_CTL(dev), 1829 I915_READ(EDP_PSR_CTL(dev)) & ~EDP_PSR_ENABLE); 1830 1831 /* Wait till PSR is idle */ 1832 if (_wait_for((I915_READ(EDP_PSR_STATUS_CTL(dev)) & 1833 EDP_PSR_STATUS_STATE_MASK) == 0, 2000, 10)) 1834 DRM_ERROR("Timed out waiting for PSR Idle State\n"); 1835} 1836 1837void intel_edp_psr_update(struct drm_device *dev) 1838{ 1839 struct intel_encoder *encoder; 1840 struct intel_dp *intel_dp = NULL; 1841 1842 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) 1843 if (encoder->type == INTEL_OUTPUT_EDP) { 1844 intel_dp = enc_to_intel_dp(&encoder->base); 1845 1846 if (!is_edp_psr(dev)) 1847 return; 1848 1849 if (!intel_edp_psr_match_conditions(intel_dp)) 1850 intel_edp_psr_disable(intel_dp); 1851 else 1852 if (!intel_edp_is_psr_enabled(dev)) 1853 intel_edp_psr_do_enable(intel_dp); 1854 } 1855} 1856 1857static void intel_disable_dp(struct intel_encoder *encoder) 1858{ 1859 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); 1860 enum port port = dp_to_dig_port(intel_dp)->port; 1861 struct drm_device *dev = encoder->base.dev; 1862 1863 /* Make sure the panel is off before trying to change the mode. But also 1864 * ensure that we have vdd while we switch off the panel. */ 1865 edp_panel_vdd_on(intel_dp); 1866 intel_edp_backlight_off(intel_dp); 1867 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF); 1868 intel_edp_panel_off(intel_dp); 1869 edp_panel_vdd_off(intel_dp, true); 1870 1871 /* cpu edp my only be disable _after_ the cpu pipe/plane is disabled. */ 1872 if (!(port == PORT_A || IS_VALLEYVIEW(dev))) 1873 intel_dp_link_down(intel_dp); 1874} 1875 1876static void intel_post_disable_dp(struct intel_encoder *encoder) 1877{ 1878 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); 1879 enum port port = dp_to_dig_port(intel_dp)->port; 1880 struct drm_device *dev = encoder->base.dev; 1881 1882 if (port == PORT_A || IS_VALLEYVIEW(dev)) { 1883 intel_dp_link_down(intel_dp); 1884 if (!IS_VALLEYVIEW(dev)) 1885 ironlake_edp_pll_off(intel_dp); 1886 } 1887} 1888 1889static void intel_enable_dp(struct intel_encoder *encoder) 1890{ 1891 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); 1892 struct drm_device *dev = encoder->base.dev; 1893 struct drm_i915_private *dev_priv = dev->dev_private; 1894 uint32_t dp_reg = I915_READ(intel_dp->output_reg); 1895 1896 if (WARN_ON(dp_reg & DP_PORT_EN)) 1897 return; 1898 1899 edp_panel_vdd_on(intel_dp); 1900 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON); 1901 intel_dp_start_link_train(intel_dp); 1902 intel_edp_panel_on(intel_dp); 1903 edp_panel_vdd_off(intel_dp, true); 1904 intel_dp_complete_link_train(intel_dp); 1905 intel_dp_stop_link_train(intel_dp); 1906} 1907 1908static void g4x_enable_dp(struct intel_encoder *encoder) 1909{ 1910 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); 1911 1912 intel_enable_dp(encoder); 1913 intel_edp_backlight_on(intel_dp); 1914} 1915 1916static void vlv_enable_dp(struct intel_encoder *encoder) 1917{ 1918 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); 1919 1920 intel_edp_backlight_on(intel_dp); 1921} 1922 1923static void g4x_pre_enable_dp(struct intel_encoder *encoder) 1924{ 1925 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); 1926 struct intel_digital_port *dport = dp_to_dig_port(intel_dp); 1927 1928 if (dport->port == PORT_A) 1929 ironlake_edp_pll_on(intel_dp); 1930} 1931 1932static void vlv_pre_enable_dp(struct intel_encoder *encoder) 1933{ 1934 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); 1935 struct intel_digital_port *dport = dp_to_dig_port(intel_dp); 1936 struct drm_device *dev = encoder->base.dev; 1937 struct drm_i915_private *dev_priv = dev->dev_private; 1938 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc); 1939 enum dpio_channel port = vlv_dport_to_channel(dport); 1940 int pipe = intel_crtc->pipe; 1941 struct edp_power_seq power_seq; 1942 u32 val; 1943 1944 mutex_lock(&dev_priv->dpio_lock); 1945 1946 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(port)); 1947 val = 0; 1948 if (pipe) 1949 val |= (1<<21); 1950 else 1951 val &= ~(1<<21); 1952 val |= 0x001000c4; 1953 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW8(port), val); 1954 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW14(port), 0x00760018); 1955 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW23(port), 0x00400888); 1956 1957 mutex_unlock(&dev_priv->dpio_lock); 1958 1959 /* init power sequencer on this pipe and port */ 1960 intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq); 1961 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp, 1962 &power_seq); 1963 1964 intel_enable_dp(encoder); 1965 1966 vlv_wait_port_ready(dev_priv, dport); 1967} 1968 1969static void vlv_dp_pre_pll_enable(struct intel_encoder *encoder) 1970{ 1971 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base); 1972 struct drm_device *dev = encoder->base.dev; 1973 struct drm_i915_private *dev_priv = dev->dev_private; 1974 struct intel_crtc *intel_crtc = 1975 to_intel_crtc(encoder->base.crtc); 1976 enum dpio_channel port = vlv_dport_to_channel(dport); 1977 int pipe = intel_crtc->pipe; 1978 1979 /* Program Tx lane resets to default */ 1980 mutex_lock(&dev_priv->dpio_lock); 1981 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port), 1982 DPIO_PCS_TX_LANE2_RESET | 1983 DPIO_PCS_TX_LANE1_RESET); 1984 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port), 1985 DPIO_PCS_CLK_CRI_RXEB_EIOS_EN | 1986 DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN | 1987 (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT) | 1988 DPIO_PCS_CLK_SOFT_RESET); 1989 1990 /* Fix up inter-pair skew failure */ 1991 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW12(port), 0x00750f00); 1992 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW11(port), 0x00001500); 1993 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW14(port), 0x40400000); 1994 mutex_unlock(&dev_priv->dpio_lock); 1995} 1996 1997/* 1998 * Native read with retry for link status and receiver capability reads for 1999 * cases where the sink may still be asleep. 2000 */ 2001static bool 2002intel_dp_aux_native_read_retry(struct intel_dp *intel_dp, uint16_t address, 2003 uint8_t *recv, int recv_bytes) 2004{ 2005 int ret, i; 2006 2007 /* 2008 * Sinks are *supposed* to come up within 1ms from an off state, 2009 * but we're also supposed to retry 3 times per the spec. 2010 */ 2011 for (i = 0; i < 3; i++) { 2012 ret = intel_dp_aux_native_read(intel_dp, address, recv, 2013 recv_bytes); 2014 if (ret == recv_bytes) 2015 return true; 2016 msleep(1); 2017 } 2018 2019 return false; 2020} 2021 2022/* 2023 * Fetch AUX CH registers 0x202 - 0x207 which contain 2024 * link status information 2025 */ 2026static bool 2027intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE]) 2028{ 2029 return intel_dp_aux_native_read_retry(intel_dp, 2030 DP_LANE0_1_STATUS, 2031 link_status, 2032 DP_LINK_STATUS_SIZE); 2033} 2034 2035/* 2036 * These are source-specific values; current Intel hardware supports 2037 * a maximum voltage of 800mV and a maximum pre-emphasis of 6dB 2038 */ 2039 2040static uint8_t 2041intel_dp_voltage_max(struct intel_dp *intel_dp) 2042{ 2043 struct drm_device *dev = intel_dp_to_dev(intel_dp); 2044 enum port port = dp_to_dig_port(intel_dp)->port; 2045 2046 if (IS_VALLEYVIEW(dev) || IS_BROADWELL(dev)) 2047 return DP_TRAIN_VOLTAGE_SWING_1200; 2048 else if (IS_GEN7(dev) && port == PORT_A) 2049 return DP_TRAIN_VOLTAGE_SWING_800; 2050 else if (HAS_PCH_CPT(dev) && port != PORT_A) 2051 return DP_TRAIN_VOLTAGE_SWING_1200; 2052 else 2053 return DP_TRAIN_VOLTAGE_SWING_800; 2054} 2055 2056static uint8_t 2057intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing) 2058{ 2059 struct drm_device *dev = intel_dp_to_dev(intel_dp); 2060 enum port port = dp_to_dig_port(intel_dp)->port; 2061 2062 if (IS_BROADWELL(dev)) { 2063 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) { 2064 case DP_TRAIN_VOLTAGE_SWING_400: 2065 case DP_TRAIN_VOLTAGE_SWING_600: 2066 return DP_TRAIN_PRE_EMPHASIS_6; 2067 case DP_TRAIN_VOLTAGE_SWING_800: 2068 return DP_TRAIN_PRE_EMPHASIS_3_5; 2069 case DP_TRAIN_VOLTAGE_SWING_1200: 2070 default: 2071 return DP_TRAIN_PRE_EMPHASIS_0; 2072 } 2073 } else if (IS_HASWELL(dev)) { 2074 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) { 2075 case DP_TRAIN_VOLTAGE_SWING_400: 2076 return DP_TRAIN_PRE_EMPHASIS_9_5; 2077 case DP_TRAIN_VOLTAGE_SWING_600: 2078 return DP_TRAIN_PRE_EMPHASIS_6; 2079 case DP_TRAIN_VOLTAGE_SWING_800: 2080 return DP_TRAIN_PRE_EMPHASIS_3_5; 2081 case DP_TRAIN_VOLTAGE_SWING_1200: 2082 default: 2083 return DP_TRAIN_PRE_EMPHASIS_0; 2084 } 2085 } else if (IS_VALLEYVIEW(dev)) { 2086 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) { 2087 case DP_TRAIN_VOLTAGE_SWING_400: 2088 return DP_TRAIN_PRE_EMPHASIS_9_5; 2089 case DP_TRAIN_VOLTAGE_SWING_600: 2090 return DP_TRAIN_PRE_EMPHASIS_6; 2091 case DP_TRAIN_VOLTAGE_SWING_800: 2092 return DP_TRAIN_PRE_EMPHASIS_3_5; 2093 case DP_TRAIN_VOLTAGE_SWING_1200: 2094 default: 2095 return DP_TRAIN_PRE_EMPHASIS_0; 2096 } 2097 } else if (IS_GEN7(dev) && port == PORT_A) { 2098 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) { 2099 case DP_TRAIN_VOLTAGE_SWING_400: 2100 return DP_TRAIN_PRE_EMPHASIS_6; 2101 case DP_TRAIN_VOLTAGE_SWING_600: 2102 case DP_TRAIN_VOLTAGE_SWING_800: 2103 return DP_TRAIN_PRE_EMPHASIS_3_5; 2104 default: 2105 return DP_TRAIN_PRE_EMPHASIS_0; 2106 } 2107 } else { 2108 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) { 2109 case DP_TRAIN_VOLTAGE_SWING_400: 2110 return DP_TRAIN_PRE_EMPHASIS_6; 2111 case DP_TRAIN_VOLTAGE_SWING_600: 2112 return DP_TRAIN_PRE_EMPHASIS_6; 2113 case DP_TRAIN_VOLTAGE_SWING_800: 2114 return DP_TRAIN_PRE_EMPHASIS_3_5; 2115 case DP_TRAIN_VOLTAGE_SWING_1200: 2116 default: 2117 return DP_TRAIN_PRE_EMPHASIS_0; 2118 } 2119 } 2120} 2121 2122static uint32_t intel_vlv_signal_levels(struct intel_dp *intel_dp) 2123{ 2124 struct drm_device *dev = intel_dp_to_dev(intel_dp); 2125 struct drm_i915_private *dev_priv = dev->dev_private; 2126 struct intel_digital_port *dport = dp_to_dig_port(intel_dp); 2127 struct intel_crtc *intel_crtc = 2128 to_intel_crtc(dport->base.base.crtc); 2129 unsigned long demph_reg_value, preemph_reg_value, 2130 uniqtranscale_reg_value; 2131 uint8_t train_set = intel_dp->train_set[0]; 2132 enum dpio_channel port = vlv_dport_to_channel(dport); 2133 int pipe = intel_crtc->pipe; 2134 2135 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) { 2136 case DP_TRAIN_PRE_EMPHASIS_0: 2137 preemph_reg_value = 0x0004000; 2138 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { 2139 case DP_TRAIN_VOLTAGE_SWING_400: 2140 demph_reg_value = 0x2B405555; 2141 uniqtranscale_reg_value = 0x552AB83A; 2142 break; 2143 case DP_TRAIN_VOLTAGE_SWING_600: 2144 demph_reg_value = 0x2B404040; 2145 uniqtranscale_reg_value = 0x5548B83A; 2146 break; 2147 case DP_TRAIN_VOLTAGE_SWING_800: 2148 demph_reg_value = 0x2B245555; 2149 uniqtranscale_reg_value = 0x5560B83A; 2150 break; 2151 case DP_TRAIN_VOLTAGE_SWING_1200: 2152 demph_reg_value = 0x2B405555; 2153 uniqtranscale_reg_value = 0x5598DA3A; 2154 break; 2155 default: 2156 return 0; 2157 } 2158 break; 2159 case DP_TRAIN_PRE_EMPHASIS_3_5: 2160 preemph_reg_value = 0x0002000; 2161 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { 2162 case DP_TRAIN_VOLTAGE_SWING_400: 2163 demph_reg_value = 0x2B404040; 2164 uniqtranscale_reg_value = 0x5552B83A; 2165 break; 2166 case DP_TRAIN_VOLTAGE_SWING_600: 2167 demph_reg_value = 0x2B404848; 2168 uniqtranscale_reg_value = 0x5580B83A; 2169 break; 2170 case DP_TRAIN_VOLTAGE_SWING_800: 2171 demph_reg_value = 0x2B404040; 2172 uniqtranscale_reg_value = 0x55ADDA3A; 2173 break; 2174 default: 2175 return 0; 2176 } 2177 break; 2178 case DP_TRAIN_PRE_EMPHASIS_6: 2179 preemph_reg_value = 0x0000000; 2180 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { 2181 case DP_TRAIN_VOLTAGE_SWING_400: 2182 demph_reg_value = 0x2B305555; 2183 uniqtranscale_reg_value = 0x5570B83A; 2184 break; 2185 case DP_TRAIN_VOLTAGE_SWING_600: 2186 demph_reg_value = 0x2B2B4040; 2187 uniqtranscale_reg_value = 0x55ADDA3A; 2188 break; 2189 default: 2190 return 0; 2191 } 2192 break; 2193 case DP_TRAIN_PRE_EMPHASIS_9_5: 2194 preemph_reg_value = 0x0006000; 2195 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { 2196 case DP_TRAIN_VOLTAGE_SWING_400: 2197 demph_reg_value = 0x1B405555; 2198 uniqtranscale_reg_value = 0x55ADDA3A; 2199 break; 2200 default: 2201 return 0; 2202 } 2203 break; 2204 default: 2205 return 0; 2206 } 2207 2208 mutex_lock(&dev_priv->dpio_lock); 2209 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x00000000); 2210 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW4(port), demph_reg_value); 2211 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(port), 2212 uniqtranscale_reg_value); 2213 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(port), 0x0C782040); 2214 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW11(port), 0x00030000); 2215 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), preemph_reg_value); 2216 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x80000000); 2217 mutex_unlock(&dev_priv->dpio_lock); 2218 2219 return 0; 2220} 2221 2222static void 2223intel_get_adjust_train(struct intel_dp *intel_dp, 2224 const uint8_t link_status[DP_LINK_STATUS_SIZE]) 2225{ 2226 uint8_t v = 0; 2227 uint8_t p = 0; 2228 int lane; 2229 uint8_t voltage_max; 2230 uint8_t preemph_max; 2231 2232 for (lane = 0; lane < intel_dp->lane_count; lane++) { 2233 uint8_t this_v = drm_dp_get_adjust_request_voltage(link_status, lane); 2234 uint8_t this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane); 2235 2236 if (this_v > v) 2237 v = this_v; 2238 if (this_p > p) 2239 p = this_p; 2240 } 2241 2242 voltage_max = intel_dp_voltage_max(intel_dp); 2243 if (v >= voltage_max) 2244 v = voltage_max | DP_TRAIN_MAX_SWING_REACHED; 2245 2246 preemph_max = intel_dp_pre_emphasis_max(intel_dp, v); 2247 if (p >= preemph_max) 2248 p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED; 2249 2250 for (lane = 0; lane < 4; lane++) 2251 intel_dp->train_set[lane] = v | p; 2252} 2253 2254static uint32_t 2255intel_gen4_signal_levels(uint8_t train_set) 2256{ 2257 uint32_t signal_levels = 0; 2258 2259 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { 2260 case DP_TRAIN_VOLTAGE_SWING_400: 2261 default: 2262 signal_levels |= DP_VOLTAGE_0_4; 2263 break; 2264 case DP_TRAIN_VOLTAGE_SWING_600: 2265 signal_levels |= DP_VOLTAGE_0_6; 2266 break; 2267 case DP_TRAIN_VOLTAGE_SWING_800: 2268 signal_levels |= DP_VOLTAGE_0_8; 2269 break; 2270 case DP_TRAIN_VOLTAGE_SWING_1200: 2271 signal_levels |= DP_VOLTAGE_1_2; 2272 break; 2273 } 2274 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) { 2275 case DP_TRAIN_PRE_EMPHASIS_0: 2276 default: 2277 signal_levels |= DP_PRE_EMPHASIS_0; 2278 break; 2279 case DP_TRAIN_PRE_EMPHASIS_3_5: 2280 signal_levels |= DP_PRE_EMPHASIS_3_5; 2281 break; 2282 case DP_TRAIN_PRE_EMPHASIS_6: 2283 signal_levels |= DP_PRE_EMPHASIS_6; 2284 break; 2285 case DP_TRAIN_PRE_EMPHASIS_9_5: 2286 signal_levels |= DP_PRE_EMPHASIS_9_5; 2287 break; 2288 } 2289 return signal_levels; 2290} 2291 2292/* Gen6's DP voltage swing and pre-emphasis control */ 2293static uint32_t 2294intel_gen6_edp_signal_levels(uint8_t train_set) 2295{ 2296 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK | 2297 DP_TRAIN_PRE_EMPHASIS_MASK); 2298 switch (signal_levels) { 2299 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0: 2300 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0: 2301 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B; 2302 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5: 2303 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B; 2304 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6: 2305 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6: 2306 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B; 2307 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5: 2308 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5: 2309 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B; 2310 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0: 2311 case DP_TRAIN_VOLTAGE_SWING_1200 | DP_TRAIN_PRE_EMPHASIS_0: 2312 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B; 2313 default: 2314 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:" 2315 "0x%x\n", signal_levels); 2316 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B; 2317 } 2318} 2319 2320/* Gen7's DP voltage swing and pre-emphasis control */ 2321static uint32_t 2322intel_gen7_edp_signal_levels(uint8_t train_set) 2323{ 2324 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK | 2325 DP_TRAIN_PRE_EMPHASIS_MASK); 2326 switch (signal_levels) { 2327 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0: 2328 return EDP_LINK_TRAIN_400MV_0DB_IVB; 2329 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5: 2330 return EDP_LINK_TRAIN_400MV_3_5DB_IVB; 2331 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6: 2332 return EDP_LINK_TRAIN_400MV_6DB_IVB; 2333 2334 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0: 2335 return EDP_LINK_TRAIN_600MV_0DB_IVB; 2336 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5: 2337 return EDP_LINK_TRAIN_600MV_3_5DB_IVB; 2338 2339 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0: 2340 return EDP_LINK_TRAIN_800MV_0DB_IVB; 2341 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5: 2342 return EDP_LINK_TRAIN_800MV_3_5DB_IVB; 2343 2344 default: 2345 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:" 2346 "0x%x\n", signal_levels); 2347 return EDP_LINK_TRAIN_500MV_0DB_IVB; 2348 } 2349} 2350 2351/* Gen7.5's (HSW) DP voltage swing and pre-emphasis control */ 2352static uint32_t 2353intel_hsw_signal_levels(uint8_t train_set) 2354{ 2355 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK | 2356 DP_TRAIN_PRE_EMPHASIS_MASK); 2357 switch (signal_levels) { 2358 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0: 2359 return DDI_BUF_EMP_400MV_0DB_HSW; 2360 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5: 2361 return DDI_BUF_EMP_400MV_3_5DB_HSW; 2362 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6: 2363 return DDI_BUF_EMP_400MV_6DB_HSW; 2364 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_9_5: 2365 return DDI_BUF_EMP_400MV_9_5DB_HSW; 2366 2367 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0: 2368 return DDI_BUF_EMP_600MV_0DB_HSW; 2369 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5: 2370 return DDI_BUF_EMP_600MV_3_5DB_HSW; 2371 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6: 2372 return DDI_BUF_EMP_600MV_6DB_HSW; 2373 2374 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0: 2375 return DDI_BUF_EMP_800MV_0DB_HSW; 2376 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5: 2377 return DDI_BUF_EMP_800MV_3_5DB_HSW; 2378 default: 2379 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:" 2380 "0x%x\n", signal_levels); 2381 return DDI_BUF_EMP_400MV_0DB_HSW; 2382 } 2383} 2384 2385static uint32_t 2386intel_bdw_signal_levels(uint8_t train_set) 2387{ 2388 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK | 2389 DP_TRAIN_PRE_EMPHASIS_MASK); 2390 switch (signal_levels) { 2391 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0: 2392 return DDI_BUF_EMP_400MV_0DB_BDW; /* Sel0 */ 2393 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5: 2394 return DDI_BUF_EMP_400MV_3_5DB_BDW; /* Sel1 */ 2395 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6: 2396 return DDI_BUF_EMP_400MV_6DB_BDW; /* Sel2 */ 2397 2398 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0: 2399 return DDI_BUF_EMP_600MV_0DB_BDW; /* Sel3 */ 2400 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5: 2401 return DDI_BUF_EMP_600MV_3_5DB_BDW; /* Sel4 */ 2402 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6: 2403 return DDI_BUF_EMP_600MV_6DB_BDW; /* Sel5 */ 2404 2405 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0: 2406 return DDI_BUF_EMP_800MV_0DB_BDW; /* Sel6 */ 2407 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5: 2408 return DDI_BUF_EMP_800MV_3_5DB_BDW; /* Sel7 */ 2409 2410 case DP_TRAIN_VOLTAGE_SWING_1200 | DP_TRAIN_PRE_EMPHASIS_0: 2411 return DDI_BUF_EMP_1200MV_0DB_BDW; /* Sel8 */ 2412 2413 default: 2414 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:" 2415 "0x%x\n", signal_levels); 2416 return DDI_BUF_EMP_400MV_0DB_BDW; /* Sel0 */ 2417 } 2418} 2419 2420/* Properly updates "DP" with the correct signal levels. */ 2421static void 2422intel_dp_set_signal_levels(struct intel_dp *intel_dp, uint32_t *DP) 2423{ 2424 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 2425 enum port port = intel_dig_port->port; 2426 struct drm_device *dev = intel_dig_port->base.base.dev; 2427 uint32_t signal_levels, mask; 2428 uint8_t train_set = intel_dp->train_set[0]; 2429 2430 if (IS_BROADWELL(dev)) { 2431 signal_levels = intel_bdw_signal_levels(train_set); 2432 mask = DDI_BUF_EMP_MASK; 2433 } else if (IS_HASWELL(dev)) { 2434 signal_levels = intel_hsw_signal_levels(train_set); 2435 mask = DDI_BUF_EMP_MASK; 2436 } else if (IS_VALLEYVIEW(dev)) { 2437 signal_levels = intel_vlv_signal_levels(intel_dp); 2438 mask = 0; 2439 } else if (IS_GEN7(dev) && port == PORT_A) { 2440 signal_levels = intel_gen7_edp_signal_levels(train_set); 2441 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_IVB; 2442 } else if (IS_GEN6(dev) && port == PORT_A) { 2443 signal_levels = intel_gen6_edp_signal_levels(train_set); 2444 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB; 2445 } else { 2446 signal_levels = intel_gen4_signal_levels(train_set); 2447 mask = DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK; 2448 } 2449 2450 DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels); 2451 2452 *DP = (*DP & ~mask) | signal_levels; 2453} 2454 2455static bool 2456intel_dp_set_link_train(struct intel_dp *intel_dp, 2457 uint32_t *DP, 2458 uint8_t dp_train_pat) 2459{ 2460 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 2461 struct drm_device *dev = intel_dig_port->base.base.dev; 2462 struct drm_i915_private *dev_priv = dev->dev_private; 2463 enum port port = intel_dig_port->port; 2464 uint8_t buf[sizeof(intel_dp->train_set) + 1]; 2465 int ret, len; 2466 2467 if (HAS_DDI(dev)) { 2468 uint32_t temp = I915_READ(DP_TP_CTL(port)); 2469 2470 if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE) 2471 temp |= DP_TP_CTL_SCRAMBLE_DISABLE; 2472 else 2473 temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE; 2474 2475 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK; 2476 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) { 2477 case DP_TRAINING_PATTERN_DISABLE: 2478 temp |= DP_TP_CTL_LINK_TRAIN_NORMAL; 2479 2480 break; 2481 case DP_TRAINING_PATTERN_1: 2482 temp |= DP_TP_CTL_LINK_TRAIN_PAT1; 2483 break; 2484 case DP_TRAINING_PATTERN_2: 2485 temp |= DP_TP_CTL_LINK_TRAIN_PAT2; 2486 break; 2487 case DP_TRAINING_PATTERN_3: 2488 temp |= DP_TP_CTL_LINK_TRAIN_PAT3; 2489 break; 2490 } 2491 I915_WRITE(DP_TP_CTL(port), temp); 2492 2493 } else if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) { 2494 *DP &= ~DP_LINK_TRAIN_MASK_CPT; 2495 2496 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) { 2497 case DP_TRAINING_PATTERN_DISABLE: 2498 *DP |= DP_LINK_TRAIN_OFF_CPT; 2499 break; 2500 case DP_TRAINING_PATTERN_1: 2501 *DP |= DP_LINK_TRAIN_PAT_1_CPT; 2502 break; 2503 case DP_TRAINING_PATTERN_2: 2504 *DP |= DP_LINK_TRAIN_PAT_2_CPT; 2505 break; 2506 case DP_TRAINING_PATTERN_3: 2507 DRM_ERROR("DP training pattern 3 not supported\n"); 2508 *DP |= DP_LINK_TRAIN_PAT_2_CPT; 2509 break; 2510 } 2511 2512 } else { 2513 *DP &= ~DP_LINK_TRAIN_MASK; 2514 2515 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) { 2516 case DP_TRAINING_PATTERN_DISABLE: 2517 *DP |= DP_LINK_TRAIN_OFF; 2518 break; 2519 case DP_TRAINING_PATTERN_1: 2520 *DP |= DP_LINK_TRAIN_PAT_1; 2521 break; 2522 case DP_TRAINING_PATTERN_2: 2523 *DP |= DP_LINK_TRAIN_PAT_2; 2524 break; 2525 case DP_TRAINING_PATTERN_3: 2526 DRM_ERROR("DP training pattern 3 not supported\n"); 2527 *DP |= DP_LINK_TRAIN_PAT_2; 2528 break; 2529 } 2530 } 2531 2532 I915_WRITE(intel_dp->output_reg, *DP); 2533 POSTING_READ(intel_dp->output_reg); 2534 2535 buf[0] = dp_train_pat; 2536 if ((dp_train_pat & DP_TRAINING_PATTERN_MASK) == 2537 DP_TRAINING_PATTERN_DISABLE) { 2538 /* don't write DP_TRAINING_LANEx_SET on disable */ 2539 len = 1; 2540 } else { 2541 /* DP_TRAINING_LANEx_SET follow DP_TRAINING_PATTERN_SET */ 2542 memcpy(buf + 1, intel_dp->train_set, intel_dp->lane_count); 2543 len = intel_dp->lane_count + 1; 2544 } 2545 2546 ret = intel_dp_aux_native_write(intel_dp, DP_TRAINING_PATTERN_SET, 2547 buf, len); 2548 2549 return ret == len; 2550} 2551 2552static bool 2553intel_dp_reset_link_train(struct intel_dp *intel_dp, uint32_t *DP, 2554 uint8_t dp_train_pat) 2555{ 2556 memset(intel_dp->train_set, 0, sizeof(intel_dp->train_set)); 2557 intel_dp_set_signal_levels(intel_dp, DP); 2558 return intel_dp_set_link_train(intel_dp, DP, dp_train_pat); 2559} 2560 2561static bool 2562intel_dp_update_link_train(struct intel_dp *intel_dp, uint32_t *DP, 2563 const uint8_t link_status[DP_LINK_STATUS_SIZE]) 2564{ 2565 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 2566 struct drm_device *dev = intel_dig_port->base.base.dev; 2567 struct drm_i915_private *dev_priv = dev->dev_private; 2568 int ret; 2569 2570 intel_get_adjust_train(intel_dp, link_status); 2571 intel_dp_set_signal_levels(intel_dp, DP); 2572 2573 I915_WRITE(intel_dp->output_reg, *DP); 2574 POSTING_READ(intel_dp->output_reg); 2575 2576 ret = intel_dp_aux_native_write(intel_dp, DP_TRAINING_LANE0_SET, 2577 intel_dp->train_set, 2578 intel_dp->lane_count); 2579 2580 return ret == intel_dp->lane_count; 2581} 2582 2583static void intel_dp_set_idle_link_train(struct intel_dp *intel_dp) 2584{ 2585 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 2586 struct drm_device *dev = intel_dig_port->base.base.dev; 2587 struct drm_i915_private *dev_priv = dev->dev_private; 2588 enum port port = intel_dig_port->port; 2589 uint32_t val; 2590 2591 if (!HAS_DDI(dev)) 2592 return; 2593 2594 val = I915_READ(DP_TP_CTL(port)); 2595 val &= ~DP_TP_CTL_LINK_TRAIN_MASK; 2596 val |= DP_TP_CTL_LINK_TRAIN_IDLE; 2597 I915_WRITE(DP_TP_CTL(port), val); 2598 2599 /* 2600 * On PORT_A we can have only eDP in SST mode. There the only reason 2601 * we need to set idle transmission mode is to work around a HW issue 2602 * where we enable the pipe while not in idle link-training mode. 2603 * In this case there is requirement to wait for a minimum number of 2604 * idle patterns to be sent. 2605 */ 2606 if (port == PORT_A) 2607 return; 2608 2609 if (wait_for((I915_READ(DP_TP_STATUS(port)) & DP_TP_STATUS_IDLE_DONE), 2610 1)) 2611 DRM_ERROR("Timed out waiting for DP idle patterns\n"); 2612} 2613 2614/* Enable corresponding port and start training pattern 1 */ 2615void 2616intel_dp_start_link_train(struct intel_dp *intel_dp) 2617{ 2618 struct drm_encoder *encoder = &dp_to_dig_port(intel_dp)->base.base; 2619 struct drm_device *dev = encoder->dev; 2620 int i; 2621 uint8_t voltage; 2622 int voltage_tries, loop_tries; 2623 uint32_t DP = intel_dp->DP; 2624 uint8_t link_config[2]; 2625 2626 if (HAS_DDI(dev)) 2627 intel_ddi_prepare_link_retrain(encoder); 2628 2629 /* Write the link configuration data */ 2630 link_config[0] = intel_dp->link_bw; 2631 link_config[1] = intel_dp->lane_count; 2632 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd)) 2633 link_config[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN; 2634 intel_dp_aux_native_write(intel_dp, DP_LINK_BW_SET, link_config, 2); 2635 2636 link_config[0] = 0; 2637 link_config[1] = DP_SET_ANSI_8B10B; 2638 intel_dp_aux_native_write(intel_dp, DP_DOWNSPREAD_CTRL, link_config, 2); 2639 2640 DP |= DP_PORT_EN; 2641 2642 /* clock recovery */ 2643 if (!intel_dp_reset_link_train(intel_dp, &DP, 2644 DP_TRAINING_PATTERN_1 | 2645 DP_LINK_SCRAMBLING_DISABLE)) { 2646 DRM_ERROR("failed to enable link training\n"); 2647 return; 2648 } 2649 2650 voltage = 0xff; 2651 voltage_tries = 0; 2652 loop_tries = 0; 2653 for (;;) { 2654 uint8_t link_status[DP_LINK_STATUS_SIZE]; 2655 2656 drm_dp_link_train_clock_recovery_delay(intel_dp->dpcd); 2657 if (!intel_dp_get_link_status(intel_dp, link_status)) { 2658 DRM_ERROR("failed to get link status\n"); 2659 break; 2660 } 2661 2662 if (drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) { 2663 DRM_DEBUG_KMS("clock recovery OK\n"); 2664 break; 2665 } 2666 2667 /* Check to see if we've tried the max voltage */ 2668 for (i = 0; i < intel_dp->lane_count; i++) 2669 if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0) 2670 break; 2671 if (i == intel_dp->lane_count) { 2672 ++loop_tries; 2673 if (loop_tries == 5) { 2674 DRM_ERROR("too many full retries, give up\n"); 2675 break; 2676 } 2677 intel_dp_reset_link_train(intel_dp, &DP, 2678 DP_TRAINING_PATTERN_1 | 2679 DP_LINK_SCRAMBLING_DISABLE); 2680 voltage_tries = 0; 2681 continue; 2682 } 2683 2684 /* Check to see if we've tried the same voltage 5 times */ 2685 if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) { 2686 ++voltage_tries; 2687 if (voltage_tries == 5) { 2688 DRM_ERROR("too many voltage retries, give up\n"); 2689 break; 2690 } 2691 } else 2692 voltage_tries = 0; 2693 voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK; 2694 2695 /* Update training set as requested by target */ 2696 if (!intel_dp_update_link_train(intel_dp, &DP, link_status)) { 2697 DRM_ERROR("failed to update link training\n"); 2698 break; 2699 } 2700 } 2701 2702 intel_dp->DP = DP; 2703} 2704 2705void 2706intel_dp_complete_link_train(struct intel_dp *intel_dp) 2707{ 2708 bool channel_eq = false; 2709 int tries, cr_tries; 2710 uint32_t DP = intel_dp->DP; 2711 uint32_t training_pattern = DP_TRAINING_PATTERN_2; 2712 2713 /* Training Pattern 3 for HBR2 ot 1.2 devices that support it*/ 2714 if (intel_dp->link_bw == DP_LINK_BW_5_4 || intel_dp->use_tps3) 2715 training_pattern = DP_TRAINING_PATTERN_3; 2716 2717 /* channel equalization */ 2718 if (!intel_dp_set_link_train(intel_dp, &DP, 2719 training_pattern | 2720 DP_LINK_SCRAMBLING_DISABLE)) { 2721 DRM_ERROR("failed to start channel equalization\n"); 2722 return; 2723 } 2724 2725 tries = 0; 2726 cr_tries = 0; 2727 channel_eq = false; 2728 for (;;) { 2729 uint8_t link_status[DP_LINK_STATUS_SIZE]; 2730 2731 if (cr_tries > 5) { 2732 DRM_ERROR("failed to train DP, aborting\n"); 2733 break; 2734 } 2735 2736 drm_dp_link_train_channel_eq_delay(intel_dp->dpcd); 2737 if (!intel_dp_get_link_status(intel_dp, link_status)) { 2738 DRM_ERROR("failed to get link status\n"); 2739 break; 2740 } 2741 2742 /* Make sure clock is still ok */ 2743 if (!drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) { 2744 intel_dp_start_link_train(intel_dp); 2745 intel_dp_set_link_train(intel_dp, &DP, 2746 training_pattern | 2747 DP_LINK_SCRAMBLING_DISABLE); 2748 cr_tries++; 2749 continue; 2750 } 2751 2752 if (drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) { 2753 channel_eq = true; 2754 break; 2755 } 2756 2757 /* Try 5 times, then try clock recovery if that fails */ 2758 if (tries > 5) { 2759 intel_dp_link_down(intel_dp); 2760 intel_dp_start_link_train(intel_dp); 2761 intel_dp_set_link_train(intel_dp, &DP, 2762 training_pattern | 2763 DP_LINK_SCRAMBLING_DISABLE); 2764 tries = 0; 2765 cr_tries++; 2766 continue; 2767 } 2768 2769 /* Update training set as requested by target */ 2770 if (!intel_dp_update_link_train(intel_dp, &DP, link_status)) { 2771 DRM_ERROR("failed to update link training\n"); 2772 break; 2773 } 2774 ++tries; 2775 } 2776 2777 intel_dp_set_idle_link_train(intel_dp); 2778 2779 intel_dp->DP = DP; 2780 2781 if (channel_eq) 2782 DRM_DEBUG_KMS("Channel EQ done. DP Training successful\n"); 2783 2784} 2785 2786void intel_dp_stop_link_train(struct intel_dp *intel_dp) 2787{ 2788 intel_dp_set_link_train(intel_dp, &intel_dp->DP, 2789 DP_TRAINING_PATTERN_DISABLE); 2790} 2791 2792static void 2793intel_dp_link_down(struct intel_dp *intel_dp) 2794{ 2795 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 2796 enum port port = intel_dig_port->port; 2797 struct drm_device *dev = intel_dig_port->base.base.dev; 2798 struct drm_i915_private *dev_priv = dev->dev_private; 2799 struct intel_crtc *intel_crtc = 2800 to_intel_crtc(intel_dig_port->base.base.crtc); 2801 uint32_t DP = intel_dp->DP; 2802 2803 /* 2804 * DDI code has a strict mode set sequence and we should try to respect 2805 * it, otherwise we might hang the machine in many different ways. So we 2806 * really should be disabling the port only on a complete crtc_disable 2807 * sequence. This function is just called under two conditions on DDI 2808 * code: 2809 * - Link train failed while doing crtc_enable, and on this case we 2810 * really should respect the mode set sequence and wait for a 2811 * crtc_disable. 2812 * - Someone turned the monitor off and intel_dp_check_link_status 2813 * called us. We don't need to disable the whole port on this case, so 2814 * when someone turns the monitor on again, 2815 * intel_ddi_prepare_link_retrain will take care of redoing the link 2816 * train. 2817 */ 2818 if (HAS_DDI(dev)) 2819 return; 2820 2821 if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0)) 2822 return; 2823 2824 DRM_DEBUG_KMS("\n"); 2825 2826 if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) { 2827 DP &= ~DP_LINK_TRAIN_MASK_CPT; 2828 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT); 2829 } else { 2830 DP &= ~DP_LINK_TRAIN_MASK; 2831 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE); 2832 } 2833 POSTING_READ(intel_dp->output_reg); 2834 2835 /* We don't really know why we're doing this */ 2836 intel_wait_for_vblank(dev, intel_crtc->pipe); 2837 2838 if (HAS_PCH_IBX(dev) && 2839 I915_READ(intel_dp->output_reg) & DP_PIPEB_SELECT) { 2840 struct drm_crtc *crtc = intel_dig_port->base.base.crtc; 2841 2842 /* Hardware workaround: leaving our transcoder select 2843 * set to transcoder B while it's off will prevent the 2844 * corresponding HDMI output on transcoder A. 2845 * 2846 * Combine this with another hardware workaround: 2847 * transcoder select bit can only be cleared while the 2848 * port is enabled. 2849 */ 2850 DP &= ~DP_PIPEB_SELECT; 2851 I915_WRITE(intel_dp->output_reg, DP); 2852 2853 /* Changes to enable or select take place the vblank 2854 * after being written. 2855 */ 2856 if (WARN_ON(crtc == NULL)) { 2857 /* We should never try to disable a port without a crtc 2858 * attached. For paranoia keep the code around for a 2859 * bit. */ 2860 POSTING_READ(intel_dp->output_reg); 2861 msleep(50); 2862 } else 2863 intel_wait_for_vblank(dev, intel_crtc->pipe); 2864 } 2865 2866 DP &= ~DP_AUDIO_OUTPUT_ENABLE; 2867 I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN); 2868 POSTING_READ(intel_dp->output_reg); 2869 msleep(intel_dp->panel_power_down_delay); 2870} 2871 2872static bool 2873intel_dp_get_dpcd(struct intel_dp *intel_dp) 2874{ 2875 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 2876 struct drm_device *dev = dig_port->base.base.dev; 2877 struct drm_i915_private *dev_priv = dev->dev_private; 2878 2879 char dpcd_hex_dump[sizeof(intel_dp->dpcd) * 3]; 2880 2881 if (intel_dp_aux_native_read_retry(intel_dp, 0x000, intel_dp->dpcd, 2882 sizeof(intel_dp->dpcd)) == 0) 2883 return false; /* aux transfer failed */ 2884 2885 hex_dump_to_buffer(intel_dp->dpcd, sizeof(intel_dp->dpcd), 2886 32, 1, dpcd_hex_dump, sizeof(dpcd_hex_dump), false); 2887 DRM_DEBUG_KMS("DPCD: %s\n", dpcd_hex_dump); 2888 2889 if (intel_dp->dpcd[DP_DPCD_REV] == 0) 2890 return false; /* DPCD not present */ 2891 2892 /* Check if the panel supports PSR */ 2893 memset(intel_dp->psr_dpcd, 0, sizeof(intel_dp->psr_dpcd)); 2894 if (is_edp(intel_dp)) { 2895 intel_dp_aux_native_read_retry(intel_dp, DP_PSR_SUPPORT, 2896 intel_dp->psr_dpcd, 2897 sizeof(intel_dp->psr_dpcd)); 2898 if (intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED) { 2899 dev_priv->psr.sink_support = true; 2900 DRM_DEBUG_KMS("Detected EDP PSR Panel.\n"); 2901 } 2902 } 2903 2904 /* Training Pattern 3 support */ 2905 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x12 && 2906 intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_TPS3_SUPPORTED) { 2907 intel_dp->use_tps3 = true; 2908 DRM_DEBUG_KMS("Displayport TPS3 supported"); 2909 } else 2910 intel_dp->use_tps3 = false; 2911 2912 if (!(intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] & 2913 DP_DWN_STRM_PORT_PRESENT)) 2914 return true; /* native DP sink */ 2915 2916 if (intel_dp->dpcd[DP_DPCD_REV] == 0x10) 2917 return true; /* no per-port downstream info */ 2918 2919 if (intel_dp_aux_native_read_retry(intel_dp, DP_DOWNSTREAM_PORT_0, 2920 intel_dp->downstream_ports, 2921 DP_MAX_DOWNSTREAM_PORTS) == 0) 2922 return false; /* downstream port status fetch failed */ 2923 2924 return true; 2925} 2926 2927static void 2928intel_dp_probe_oui(struct intel_dp *intel_dp) 2929{ 2930 u8 buf[3]; 2931 2932 if (!(intel_dp->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT)) 2933 return; 2934 2935 edp_panel_vdd_on(intel_dp); 2936 2937 if (intel_dp_aux_native_read_retry(intel_dp, DP_SINK_OUI, buf, 3)) 2938 DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n", 2939 buf[0], buf[1], buf[2]); 2940 2941 if (intel_dp_aux_native_read_retry(intel_dp, DP_BRANCH_OUI, buf, 3)) 2942 DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n", 2943 buf[0], buf[1], buf[2]); 2944 2945 edp_panel_vdd_off(intel_dp, false); 2946} 2947 2948int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc) 2949{ 2950 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 2951 struct drm_device *dev = intel_dig_port->base.base.dev; 2952 struct intel_crtc *intel_crtc = 2953 to_intel_crtc(intel_dig_port->base.base.crtc); 2954 u8 buf[1]; 2955 2956 if (!intel_dp_aux_native_read(intel_dp, DP_TEST_SINK_MISC, buf, 1)) 2957 return -EAGAIN; 2958 2959 if (!(buf[0] & DP_TEST_CRC_SUPPORTED)) 2960 return -ENOTTY; 2961 2962 if (!intel_dp_aux_native_write_1(intel_dp, DP_TEST_SINK, 2963 DP_TEST_SINK_START)) 2964 return -EAGAIN; 2965 2966 /* Wait 2 vblanks to be sure we will have the correct CRC value */ 2967 intel_wait_for_vblank(dev, intel_crtc->pipe); 2968 intel_wait_for_vblank(dev, intel_crtc->pipe); 2969 2970 if (!intel_dp_aux_native_read(intel_dp, DP_TEST_CRC_R_CR, crc, 6)) 2971 return -EAGAIN; 2972 2973 intel_dp_aux_native_write_1(intel_dp, DP_TEST_SINK, 0); 2974 return 0; 2975} 2976 2977static bool 2978intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector) 2979{ 2980 int ret; 2981 2982 ret = intel_dp_aux_native_read_retry(intel_dp, 2983 DP_DEVICE_SERVICE_IRQ_VECTOR, 2984 sink_irq_vector, 1); 2985 if (!ret) 2986 return false; 2987 2988 return true; 2989} 2990 2991static void 2992intel_dp_handle_test_request(struct intel_dp *intel_dp) 2993{ 2994 /* NAK by default */ 2995 intel_dp_aux_native_write_1(intel_dp, DP_TEST_RESPONSE, DP_TEST_NAK); 2996} 2997 2998/* 2999 * According to DP spec 3000 * 5.1.2: 3001 * 1. Read DPCD 3002 * 2. Configure link according to Receiver Capabilities 3003 * 3. Use Link Training from 2.5.3.3 and 3.5.1.3 3004 * 4. Check link status on receipt of hot-plug interrupt 3005 */ 3006 3007void 3008intel_dp_check_link_status(struct intel_dp *intel_dp) 3009{ 3010 struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base; 3011 u8 sink_irq_vector; 3012 u8 link_status[DP_LINK_STATUS_SIZE]; 3013 3014 if (!intel_encoder->connectors_active) 3015 return; 3016 3017 if (WARN_ON(!intel_encoder->base.crtc)) 3018 return; 3019 3020 /* Try to read receiver status if the link appears to be up */ 3021 if (!intel_dp_get_link_status(intel_dp, link_status)) { 3022 return; 3023 } 3024 3025 /* Now read the DPCD to see if it's actually running */ 3026 if (!intel_dp_get_dpcd(intel_dp)) { 3027 return; 3028 } 3029 3030 /* Try to read the source of the interrupt */ 3031 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 && 3032 intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) { 3033 /* Clear interrupt source */ 3034 intel_dp_aux_native_write_1(intel_dp, 3035 DP_DEVICE_SERVICE_IRQ_VECTOR, 3036 sink_irq_vector); 3037 3038 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST) 3039 intel_dp_handle_test_request(intel_dp); 3040 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ)) 3041 DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n"); 3042 } 3043 3044 if (!drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) { 3045 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n", 3046 drm_get_encoder_name(&intel_encoder->base)); 3047 intel_dp_start_link_train(intel_dp); 3048 intel_dp_complete_link_train(intel_dp); 3049 intel_dp_stop_link_train(intel_dp); 3050 } 3051} 3052 3053/* XXX this is probably wrong for multiple downstream ports */ 3054static enum drm_connector_status 3055intel_dp_detect_dpcd(struct intel_dp *intel_dp) 3056{ 3057 uint8_t *dpcd = intel_dp->dpcd; 3058 uint8_t type; 3059 3060 if (!intel_dp_get_dpcd(intel_dp)) 3061 return connector_status_disconnected; 3062 3063 /* if there's no downstream port, we're done */ 3064 if (!(dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT)) 3065 return connector_status_connected; 3066 3067 /* If we're HPD-aware, SINK_COUNT changes dynamically */ 3068 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 && 3069 intel_dp->downstream_ports[0] & DP_DS_PORT_HPD) { 3070 uint8_t reg; 3071 if (!intel_dp_aux_native_read_retry(intel_dp, DP_SINK_COUNT, 3072 ®, 1)) 3073 return connector_status_unknown; 3074 return DP_GET_SINK_COUNT(reg) ? connector_status_connected 3075 : connector_status_disconnected; 3076 } 3077 3078 /* If no HPD, poke DDC gently */ 3079 if (drm_probe_ddc(&intel_dp->adapter)) 3080 return connector_status_connected; 3081 3082 /* Well we tried, say unknown for unreliable port types */ 3083 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) { 3084 type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK; 3085 if (type == DP_DS_PORT_TYPE_VGA || 3086 type == DP_DS_PORT_TYPE_NON_EDID) 3087 return connector_status_unknown; 3088 } else { 3089 type = intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] & 3090 DP_DWN_STRM_PORT_TYPE_MASK; 3091 if (type == DP_DWN_STRM_PORT_TYPE_ANALOG || 3092 type == DP_DWN_STRM_PORT_TYPE_OTHER) 3093 return connector_status_unknown; 3094 } 3095 3096 /* Anything else is out of spec, warn and ignore */ 3097 DRM_DEBUG_KMS("Broken DP branch device, ignoring\n"); 3098 return connector_status_disconnected; 3099} 3100 3101static enum drm_connector_status 3102ironlake_dp_detect(struct intel_dp *intel_dp) 3103{ 3104 struct drm_device *dev = intel_dp_to_dev(intel_dp); 3105 struct drm_i915_private *dev_priv = dev->dev_private; 3106 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 3107 enum drm_connector_status status; 3108 3109 /* Can't disconnect eDP, but you can close the lid... */ 3110 if (is_edp(intel_dp)) { 3111 status = intel_panel_detect(dev); 3112 if (status == connector_status_unknown) 3113 status = connector_status_connected; 3114 return status; 3115 } 3116 3117 if (!ibx_digital_port_connected(dev_priv, intel_dig_port)) 3118 return connector_status_disconnected; 3119 3120 return intel_dp_detect_dpcd(intel_dp); 3121} 3122 3123static enum drm_connector_status 3124g4x_dp_detect(struct intel_dp *intel_dp) 3125{ 3126 struct drm_device *dev = intel_dp_to_dev(intel_dp); 3127 struct drm_i915_private *dev_priv = dev->dev_private; 3128 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 3129 uint32_t bit; 3130 3131 /* Can't disconnect eDP, but you can close the lid... */ 3132 if (is_edp(intel_dp)) { 3133 enum drm_connector_status status; 3134 3135 status = intel_panel_detect(dev); 3136 if (status == connector_status_unknown) 3137 status = connector_status_connected; 3138 return status; 3139 } 3140 3141 if (IS_VALLEYVIEW(dev)) { 3142 switch (intel_dig_port->port) { 3143 case PORT_B: 3144 bit = PORTB_HOTPLUG_LIVE_STATUS_VLV; 3145 break; 3146 case PORT_C: 3147 bit = PORTC_HOTPLUG_LIVE_STATUS_VLV; 3148 break; 3149 case PORT_D: 3150 bit = PORTD_HOTPLUG_LIVE_STATUS_VLV; 3151 break; 3152 default: 3153 return connector_status_unknown; 3154 } 3155 } else { 3156 switch (intel_dig_port->port) { 3157 case PORT_B: 3158 bit = PORTB_HOTPLUG_LIVE_STATUS_G4X; 3159 break; 3160 case PORT_C: 3161 bit = PORTC_HOTPLUG_LIVE_STATUS_G4X; 3162 break; 3163 case PORT_D: 3164 bit = PORTD_HOTPLUG_LIVE_STATUS_G4X; 3165 break; 3166 default: 3167 return connector_status_unknown; 3168 } 3169 } 3170 3171 if ((I915_READ(PORT_HOTPLUG_STAT) & bit) == 0) 3172 return connector_status_disconnected; 3173 3174 return intel_dp_detect_dpcd(intel_dp); 3175} 3176 3177static struct edid * 3178intel_dp_get_edid(struct drm_connector *connector, struct i2c_adapter *adapter) 3179{ 3180 struct intel_connector *intel_connector = to_intel_connector(connector); 3181 3182 /* use cached edid if we have one */ 3183 if (intel_connector->edid) { 3184 /* invalid edid */ 3185 if (IS_ERR(intel_connector->edid)) 3186 return NULL; 3187 3188 return drm_edid_duplicate(intel_connector->edid); 3189 } 3190 3191 return drm_get_edid(connector, adapter); 3192} 3193 3194static int 3195intel_dp_get_edid_modes(struct drm_connector *connector, struct i2c_adapter *adapter) 3196{ 3197 struct intel_connector *intel_connector = to_intel_connector(connector); 3198 3199 /* use cached edid if we have one */ 3200 if (intel_connector->edid) { 3201 /* invalid edid */ 3202 if (IS_ERR(intel_connector->edid)) 3203 return 0; 3204 3205 return intel_connector_update_modes(connector, 3206 intel_connector->edid); 3207 } 3208 3209 return intel_ddc_get_modes(connector, adapter); 3210} 3211 3212static enum drm_connector_status 3213intel_dp_detect(struct drm_connector *connector, bool force) 3214{ 3215 struct intel_dp *intel_dp = intel_attached_dp(connector); 3216 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 3217 struct intel_encoder *intel_encoder = &intel_dig_port->base; 3218 struct drm_device *dev = connector->dev; 3219 struct drm_i915_private *dev_priv = dev->dev_private; 3220 enum drm_connector_status status; 3221 struct edid *edid = NULL; 3222 3223 intel_runtime_pm_get(dev_priv); 3224 3225 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", 3226 connector->base.id, drm_get_connector_name(connector)); 3227 3228 intel_dp->has_audio = false; 3229 3230 if (HAS_PCH_SPLIT(dev)) 3231 status = ironlake_dp_detect(intel_dp); 3232 else 3233 status = g4x_dp_detect(intel_dp); 3234 3235 if (status != connector_status_connected) 3236 goto out; 3237 3238 intel_dp_probe_oui(intel_dp); 3239 3240 if (intel_dp->force_audio != HDMI_AUDIO_AUTO) { 3241 intel_dp->has_audio = (intel_dp->force_audio == HDMI_AUDIO_ON); 3242 } else { 3243 edid = intel_dp_get_edid(connector, &intel_dp->adapter); 3244 if (edid) { 3245 intel_dp->has_audio = drm_detect_monitor_audio(edid); 3246 kfree(edid); 3247 } 3248 } 3249 3250 if (intel_encoder->type != INTEL_OUTPUT_EDP) 3251 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT; 3252 status = connector_status_connected; 3253 3254out: 3255 intel_runtime_pm_put(dev_priv); 3256 return status; 3257} 3258 3259static int intel_dp_get_modes(struct drm_connector *connector) 3260{ 3261 struct intel_dp *intel_dp = intel_attached_dp(connector); 3262 struct intel_connector *intel_connector = to_intel_connector(connector); 3263 struct drm_device *dev = connector->dev; 3264 int ret; 3265 3266 /* We should parse the EDID data and find out if it has an audio sink 3267 */ 3268 3269 ret = intel_dp_get_edid_modes(connector, &intel_dp->adapter); 3270 if (ret) 3271 return ret; 3272 3273 /* if eDP has no EDID, fall back to fixed mode */ 3274 if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) { 3275 struct drm_display_mode *mode; 3276 mode = drm_mode_duplicate(dev, 3277 intel_connector->panel.fixed_mode); 3278 if (mode) { 3279 drm_mode_probed_add(connector, mode); 3280 return 1; 3281 } 3282 } 3283 return 0; 3284} 3285 3286static bool 3287intel_dp_detect_audio(struct drm_connector *connector) 3288{ 3289 struct intel_dp *intel_dp = intel_attached_dp(connector); 3290 struct edid *edid; 3291 bool has_audio = false; 3292 3293 edid = intel_dp_get_edid(connector, &intel_dp->adapter); 3294 if (edid) { 3295 has_audio = drm_detect_monitor_audio(edid); 3296 kfree(edid); 3297 } 3298 3299 return has_audio; 3300} 3301 3302static int 3303intel_dp_set_property(struct drm_connector *connector, 3304 struct drm_property *property, 3305 uint64_t val) 3306{ 3307 struct drm_i915_private *dev_priv = connector->dev->dev_private; 3308 struct intel_connector *intel_connector = to_intel_connector(connector); 3309 struct intel_encoder *intel_encoder = intel_attached_encoder(connector); 3310 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base); 3311 int ret; 3312 3313 ret = drm_object_property_set_value(&connector->base, property, val); 3314 if (ret) 3315 return ret; 3316 3317 if (property == dev_priv->force_audio_property) { 3318 int i = val; 3319 bool has_audio; 3320 3321 if (i == intel_dp->force_audio) 3322 return 0; 3323 3324 intel_dp->force_audio = i; 3325 3326 if (i == HDMI_AUDIO_AUTO) 3327 has_audio = intel_dp_detect_audio(connector); 3328 else 3329 has_audio = (i == HDMI_AUDIO_ON); 3330 3331 if (has_audio == intel_dp->has_audio) 3332 return 0; 3333 3334 intel_dp->has_audio = has_audio; 3335 goto done; 3336 } 3337 3338 if (property == dev_priv->broadcast_rgb_property) { 3339 bool old_auto = intel_dp->color_range_auto; 3340 uint32_t old_range = intel_dp->color_range; 3341 3342 switch (val) { 3343 case INTEL_BROADCAST_RGB_AUTO: 3344 intel_dp->color_range_auto = true; 3345 break; 3346 case INTEL_BROADCAST_RGB_FULL: 3347 intel_dp->color_range_auto = false; 3348 intel_dp->color_range = 0; 3349 break; 3350 case INTEL_BROADCAST_RGB_LIMITED: 3351 intel_dp->color_range_auto = false; 3352 intel_dp->color_range = DP_COLOR_RANGE_16_235; 3353 break; 3354 default: 3355 return -EINVAL; 3356 } 3357 3358 if (old_auto == intel_dp->color_range_auto && 3359 old_range == intel_dp->color_range) 3360 return 0; 3361 3362 goto done; 3363 } 3364 3365 if (is_edp(intel_dp) && 3366 property == connector->dev->mode_config.scaling_mode_property) { 3367 if (val == DRM_MODE_SCALE_NONE) { 3368 DRM_DEBUG_KMS("no scaling not supported\n"); 3369 return -EINVAL; 3370 } 3371 3372 if (intel_connector->panel.fitting_mode == val) { 3373 /* the eDP scaling property is not changed */ 3374 return 0; 3375 } 3376 intel_connector->panel.fitting_mode = val; 3377 3378 goto done; 3379 } 3380 3381 return -EINVAL; 3382 3383done: 3384 if (intel_encoder->base.crtc) 3385 intel_crtc_restore_mode(intel_encoder->base.crtc); 3386 3387 return 0; 3388} 3389 3390static void 3391intel_dp_connector_destroy(struct drm_connector *connector) 3392{ 3393 struct intel_connector *intel_connector = to_intel_connector(connector); 3394 3395 if (!IS_ERR_OR_NULL(intel_connector->edid)) 3396 kfree(intel_connector->edid); 3397 3398 /* Can't call is_edp() since the encoder may have been destroyed 3399 * already. */ 3400 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) 3401 intel_panel_fini(&intel_connector->panel); 3402 3403 drm_connector_cleanup(connector); 3404 kfree(connector); 3405} 3406 3407void intel_dp_encoder_destroy(struct drm_encoder *encoder) 3408{ 3409 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); 3410 struct intel_dp *intel_dp = &intel_dig_port->dp; 3411 struct drm_device *dev = intel_dp_to_dev(intel_dp); 3412 3413 i2c_del_adapter(&intel_dp->adapter); 3414 drm_encoder_cleanup(encoder); 3415 if (is_edp(intel_dp)) { 3416 cancel_delayed_work_sync(&intel_dp->panel_vdd_work); 3417 mutex_lock(&dev->mode_config.mutex); 3418 edp_panel_vdd_off_sync(intel_dp); 3419 mutex_unlock(&dev->mode_config.mutex); 3420 } 3421 kfree(intel_dig_port); 3422} 3423 3424static const struct drm_connector_funcs intel_dp_connector_funcs = { 3425 .dpms = intel_connector_dpms, 3426 .detect = intel_dp_detect, 3427 .fill_modes = drm_helper_probe_single_connector_modes, 3428 .set_property = intel_dp_set_property, 3429 .destroy = intel_dp_connector_destroy, 3430}; 3431 3432static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = { 3433 .get_modes = intel_dp_get_modes, 3434 .mode_valid = intel_dp_mode_valid, 3435 .best_encoder = intel_best_encoder, 3436}; 3437 3438static const struct drm_encoder_funcs intel_dp_enc_funcs = { 3439 .destroy = intel_dp_encoder_destroy, 3440}; 3441 3442static void 3443intel_dp_hot_plug(struct intel_encoder *intel_encoder) 3444{ 3445 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base); 3446 3447 intel_dp_check_link_status(intel_dp); 3448} 3449 3450/* Return which DP Port should be selected for Transcoder DP control */ 3451int 3452intel_trans_dp_port_sel(struct drm_crtc *crtc) 3453{ 3454 struct drm_device *dev = crtc->dev; 3455 struct intel_encoder *intel_encoder; 3456 struct intel_dp *intel_dp; 3457 3458 for_each_encoder_on_crtc(dev, crtc, intel_encoder) { 3459 intel_dp = enc_to_intel_dp(&intel_encoder->base); 3460 3461 if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT || 3462 intel_encoder->type == INTEL_OUTPUT_EDP) 3463 return intel_dp->output_reg; 3464 } 3465 3466 return -1; 3467} 3468 3469/* check the VBT to see whether the eDP is on DP-D port */ 3470bool intel_dp_is_edp(struct drm_device *dev, enum port port) 3471{ 3472 struct drm_i915_private *dev_priv = dev->dev_private; 3473 union child_device_config *p_child; 3474 int i; 3475 static const short port_mapping[] = { 3476 [PORT_B] = PORT_IDPB, 3477 [PORT_C] = PORT_IDPC, 3478 [PORT_D] = PORT_IDPD, 3479 }; 3480 3481 if (port == PORT_A) 3482 return true; 3483 3484 if (!dev_priv->vbt.child_dev_num) 3485 return false; 3486 3487 for (i = 0; i < dev_priv->vbt.child_dev_num; i++) { 3488 p_child = dev_priv->vbt.child_dev + i; 3489 3490 if (p_child->common.dvo_port == port_mapping[port] && 3491 (p_child->common.device_type & DEVICE_TYPE_eDP_BITS) == 3492 (DEVICE_TYPE_eDP & DEVICE_TYPE_eDP_BITS)) 3493 return true; 3494 } 3495 return false; 3496} 3497 3498static void 3499intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector) 3500{ 3501 struct intel_connector *intel_connector = to_intel_connector(connector); 3502 3503 intel_attach_force_audio_property(connector); 3504 intel_attach_broadcast_rgb_property(connector); 3505 intel_dp->color_range_auto = true; 3506 3507 if (is_edp(intel_dp)) { 3508 drm_mode_create_scaling_mode_property(connector->dev); 3509 drm_object_attach_property( 3510 &connector->base, 3511 connector->dev->mode_config.scaling_mode_property, 3512 DRM_MODE_SCALE_ASPECT); 3513 intel_connector->panel.fitting_mode = DRM_MODE_SCALE_ASPECT; 3514 } 3515} 3516 3517static void intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp) 3518{ 3519 intel_dp->last_power_cycle = jiffies; 3520 intel_dp->last_power_on = jiffies; 3521 intel_dp->last_backlight_off = jiffies; 3522} 3523 3524static void 3525intel_dp_init_panel_power_sequencer(struct drm_device *dev, 3526 struct intel_dp *intel_dp, 3527 struct edp_power_seq *out) 3528{ 3529 struct drm_i915_private *dev_priv = dev->dev_private; 3530 struct edp_power_seq cur, vbt, spec, final; 3531 u32 pp_on, pp_off, pp_div, pp; 3532 int pp_ctrl_reg, pp_on_reg, pp_off_reg, pp_div_reg; 3533 3534 if (HAS_PCH_SPLIT(dev)) { 3535 pp_ctrl_reg = PCH_PP_CONTROL; 3536 pp_on_reg = PCH_PP_ON_DELAYS; 3537 pp_off_reg = PCH_PP_OFF_DELAYS; 3538 pp_div_reg = PCH_PP_DIVISOR; 3539 } else { 3540 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp); 3541 3542 pp_ctrl_reg = VLV_PIPE_PP_CONTROL(pipe); 3543 pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe); 3544 pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe); 3545 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe); 3546 } 3547 3548 /* Workaround: Need to write PP_CONTROL with the unlock key as 3549 * the very first thing. */ 3550 pp = ironlake_get_pp_control(intel_dp); 3551 I915_WRITE(pp_ctrl_reg, pp); 3552 3553 pp_on = I915_READ(pp_on_reg); 3554 pp_off = I915_READ(pp_off_reg); 3555 pp_div = I915_READ(pp_div_reg); 3556 3557 /* Pull timing values out of registers */ 3558 cur.t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >> 3559 PANEL_POWER_UP_DELAY_SHIFT; 3560 3561 cur.t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >> 3562 PANEL_LIGHT_ON_DELAY_SHIFT; 3563 3564 cur.t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >> 3565 PANEL_LIGHT_OFF_DELAY_SHIFT; 3566 3567 cur.t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >> 3568 PANEL_POWER_DOWN_DELAY_SHIFT; 3569 3570 cur.t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >> 3571 PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000; 3572 3573 DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n", 3574 cur.t1_t3, cur.t8, cur.t9, cur.t10, cur.t11_t12); 3575 3576 vbt = dev_priv->vbt.edp_pps; 3577 3578 /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of 3579 * our hw here, which are all in 100usec. */ 3580 spec.t1_t3 = 210 * 10; 3581 spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */ 3582 spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */ 3583 spec.t10 = 500 * 10; 3584 /* This one is special and actually in units of 100ms, but zero 3585 * based in the hw (so we need to add 100 ms). But the sw vbt 3586 * table multiplies it with 1000 to make it in units of 100usec, 3587 * too. */ 3588 spec.t11_t12 = (510 + 100) * 10; 3589 3590 DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n", 3591 vbt.t1_t3, vbt.t8, vbt.t9, vbt.t10, vbt.t11_t12); 3592 3593 /* Use the max of the register settings and vbt. If both are 3594 * unset, fall back to the spec limits. */ 3595#define assign_final(field) final.field = (max(cur.field, vbt.field) == 0 ? \ 3596 spec.field : \ 3597 max(cur.field, vbt.field)) 3598 assign_final(t1_t3); 3599 assign_final(t8); 3600 assign_final(t9); 3601 assign_final(t10); 3602 assign_final(t11_t12); 3603#undef assign_final 3604 3605#define get_delay(field) (DIV_ROUND_UP(final.field, 10)) 3606 intel_dp->panel_power_up_delay = get_delay(t1_t3); 3607 intel_dp->backlight_on_delay = get_delay(t8); 3608 intel_dp->backlight_off_delay = get_delay(t9); 3609 intel_dp->panel_power_down_delay = get_delay(t10); 3610 intel_dp->panel_power_cycle_delay = get_delay(t11_t12); 3611#undef get_delay 3612 3613 DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n", 3614 intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay, 3615 intel_dp->panel_power_cycle_delay); 3616 3617 DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n", 3618 intel_dp->backlight_on_delay, intel_dp->backlight_off_delay); 3619 3620 if (out) 3621 *out = final; 3622} 3623 3624static void 3625intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev, 3626 struct intel_dp *intel_dp, 3627 struct edp_power_seq *seq) 3628{ 3629 struct drm_i915_private *dev_priv = dev->dev_private; 3630 u32 pp_on, pp_off, pp_div, port_sel = 0; 3631 int div = HAS_PCH_SPLIT(dev) ? intel_pch_rawclk(dev) : intel_hrawclk(dev); 3632 int pp_on_reg, pp_off_reg, pp_div_reg; 3633 3634 if (HAS_PCH_SPLIT(dev)) { 3635 pp_on_reg = PCH_PP_ON_DELAYS; 3636 pp_off_reg = PCH_PP_OFF_DELAYS; 3637 pp_div_reg = PCH_PP_DIVISOR; 3638 } else { 3639 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp); 3640 3641 pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe); 3642 pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe); 3643 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe); 3644 } 3645 3646 /* 3647 * And finally store the new values in the power sequencer. The 3648 * backlight delays are set to 1 because we do manual waits on them. For 3649 * T8, even BSpec recommends doing it. For T9, if we don't do this, 3650 * we'll end up waiting for the backlight off delay twice: once when we 3651 * do the manual sleep, and once when we disable the panel and wait for 3652 * the PP_STATUS bit to become zero. 3653 */ 3654 pp_on = (seq->t1_t3 << PANEL_POWER_UP_DELAY_SHIFT) | 3655 (1 << PANEL_LIGHT_ON_DELAY_SHIFT); 3656 pp_off = (1 << PANEL_LIGHT_OFF_DELAY_SHIFT) | 3657 (seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT); 3658 /* Compute the divisor for the pp clock, simply match the Bspec 3659 * formula. */ 3660 pp_div = ((100 * div)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT; 3661 pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000) 3662 << PANEL_POWER_CYCLE_DELAY_SHIFT); 3663 3664 /* Haswell doesn't have any port selection bits for the panel 3665 * power sequencer any more. */ 3666 if (IS_VALLEYVIEW(dev)) { 3667 if (dp_to_dig_port(intel_dp)->port == PORT_B) 3668 port_sel = PANEL_PORT_SELECT_DPB_VLV; 3669 else 3670 port_sel = PANEL_PORT_SELECT_DPC_VLV; 3671 } else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) { 3672 if (dp_to_dig_port(intel_dp)->port == PORT_A) 3673 port_sel = PANEL_PORT_SELECT_DPA; 3674 else 3675 port_sel = PANEL_PORT_SELECT_DPD; 3676 } 3677 3678 pp_on |= port_sel; 3679 3680 I915_WRITE(pp_on_reg, pp_on); 3681 I915_WRITE(pp_off_reg, pp_off); 3682 I915_WRITE(pp_div_reg, pp_div); 3683 3684 DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n", 3685 I915_READ(pp_on_reg), 3686 I915_READ(pp_off_reg), 3687 I915_READ(pp_div_reg)); 3688} 3689 3690static bool intel_edp_init_connector(struct intel_dp *intel_dp, 3691 struct intel_connector *intel_connector, 3692 struct edp_power_seq *power_seq) 3693{ 3694 struct drm_connector *connector = &intel_connector->base; 3695 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 3696 struct drm_device *dev = intel_dig_port->base.base.dev; 3697 struct drm_i915_private *dev_priv = dev->dev_private; 3698 struct drm_display_mode *fixed_mode = NULL; 3699 bool has_dpcd; 3700 struct drm_display_mode *scan; 3701 struct edid *edid; 3702 3703 if (!is_edp(intel_dp)) 3704 return true; 3705 3706 /* Cache DPCD and EDID for edp. */ 3707 edp_panel_vdd_on(intel_dp); 3708 has_dpcd = intel_dp_get_dpcd(intel_dp); 3709 edp_panel_vdd_off(intel_dp, false); 3710 3711 if (has_dpcd) { 3712 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) 3713 dev_priv->no_aux_handshake = 3714 intel_dp->dpcd[DP_MAX_DOWNSPREAD] & 3715 DP_NO_AUX_HANDSHAKE_LINK_TRAINING; 3716 } else { 3717 /* if this fails, presume the device is a ghost */ 3718 DRM_INFO("failed to retrieve link info, disabling eDP\n"); 3719 return false; 3720 } 3721 3722 /* We now know it's not a ghost, init power sequence regs. */ 3723 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp, power_seq); 3724 3725 edid = drm_get_edid(connector, &intel_dp->adapter); 3726 if (edid) { 3727 if (drm_add_edid_modes(connector, edid)) { 3728 drm_mode_connector_update_edid_property(connector, 3729 edid); 3730 drm_edid_to_eld(connector, edid); 3731 } else { 3732 kfree(edid); 3733 edid = ERR_PTR(-EINVAL); 3734 } 3735 } else { 3736 edid = ERR_PTR(-ENOENT); 3737 } 3738 intel_connector->edid = edid; 3739 3740 /* prefer fixed mode from EDID if available */ 3741 list_for_each_entry(scan, &connector->probed_modes, head) { 3742 if ((scan->type & DRM_MODE_TYPE_PREFERRED)) { 3743 fixed_mode = drm_mode_duplicate(dev, scan); 3744 break; 3745 } 3746 } 3747 3748 /* fallback to VBT if available for eDP */ 3749 if (!fixed_mode && dev_priv->vbt.lfp_lvds_vbt_mode) { 3750 fixed_mode = drm_mode_duplicate(dev, 3751 dev_priv->vbt.lfp_lvds_vbt_mode); 3752 if (fixed_mode) 3753 fixed_mode->type |= DRM_MODE_TYPE_PREFERRED; 3754 } 3755 3756 intel_panel_init(&intel_connector->panel, fixed_mode, NULL); 3757 intel_panel_setup_backlight(connector); 3758 3759 return true; 3760} 3761 3762bool 3763intel_dp_init_connector(struct intel_digital_port *intel_dig_port, 3764 struct intel_connector *intel_connector) 3765{ 3766 struct drm_connector *connector = &intel_connector->base; 3767 struct intel_dp *intel_dp = &intel_dig_port->dp; 3768 struct intel_encoder *intel_encoder = &intel_dig_port->base; 3769 struct drm_device *dev = intel_encoder->base.dev; 3770 struct drm_i915_private *dev_priv = dev->dev_private; 3771 enum port port = intel_dig_port->port; 3772 struct edp_power_seq power_seq = { 0 }; 3773 const char *name = NULL; 3774 int type, error; 3775 3776 /* intel_dp vfuncs */ 3777 if (IS_VALLEYVIEW(dev)) 3778 intel_dp->get_aux_clock_divider = vlv_get_aux_clock_divider; 3779 else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) 3780 intel_dp->get_aux_clock_divider = hsw_get_aux_clock_divider; 3781 else if (HAS_PCH_SPLIT(dev)) 3782 intel_dp->get_aux_clock_divider = ilk_get_aux_clock_divider; 3783 else 3784 intel_dp->get_aux_clock_divider = i9xx_get_aux_clock_divider; 3785 3786 intel_dp->get_aux_send_ctl = i9xx_get_aux_send_ctl; 3787 3788 /* Preserve the current hw state. */ 3789 intel_dp->DP = I915_READ(intel_dp->output_reg); 3790 intel_dp->attached_connector = intel_connector; 3791 3792 if (intel_dp_is_edp(dev, port)) 3793 type = DRM_MODE_CONNECTOR_eDP; 3794 else 3795 type = DRM_MODE_CONNECTOR_DisplayPort; 3796 3797 /* 3798 * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but 3799 * for DP the encoder type can be set by the caller to 3800 * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it. 3801 */ 3802 if (type == DRM_MODE_CONNECTOR_eDP) 3803 intel_encoder->type = INTEL_OUTPUT_EDP; 3804 3805 DRM_DEBUG_KMS("Adding %s connector on port %c\n", 3806 type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP", 3807 port_name(port)); 3808 3809 drm_connector_init(dev, connector, &intel_dp_connector_funcs, type); 3810 drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs); 3811 3812 connector->interlace_allowed = true; 3813 connector->doublescan_allowed = 0; 3814 3815 INIT_DELAYED_WORK(&intel_dp->panel_vdd_work, 3816 edp_panel_vdd_work); 3817 3818 intel_connector_attach_encoder(intel_connector, intel_encoder); 3819 drm_sysfs_connector_add(connector); 3820 3821 if (HAS_DDI(dev)) 3822 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state; 3823 else 3824 intel_connector->get_hw_state = intel_connector_get_hw_state; 3825 intel_connector->unregister = intel_dp_connector_unregister; 3826 3827 intel_dp->aux_ch_ctl_reg = intel_dp->output_reg + 0x10; 3828 if (HAS_DDI(dev)) { 3829 switch (intel_dig_port->port) { 3830 case PORT_A: 3831 intel_dp->aux_ch_ctl_reg = DPA_AUX_CH_CTL; 3832 break; 3833 case PORT_B: 3834 intel_dp->aux_ch_ctl_reg = PCH_DPB_AUX_CH_CTL; 3835 break; 3836 case PORT_C: 3837 intel_dp->aux_ch_ctl_reg = PCH_DPC_AUX_CH_CTL; 3838 break; 3839 case PORT_D: 3840 intel_dp->aux_ch_ctl_reg = PCH_DPD_AUX_CH_CTL; 3841 break; 3842 default: 3843 BUG(); 3844 } 3845 } 3846 3847 /* Set up the DDC bus. */ 3848 switch (port) { 3849 case PORT_A: 3850 intel_encoder->hpd_pin = HPD_PORT_A; 3851 name = "DPDDC-A"; 3852 break; 3853 case PORT_B: 3854 intel_encoder->hpd_pin = HPD_PORT_B; 3855 name = "DPDDC-B"; 3856 break; 3857 case PORT_C: 3858 intel_encoder->hpd_pin = HPD_PORT_C; 3859 name = "DPDDC-C"; 3860 break; 3861 case PORT_D: 3862 intel_encoder->hpd_pin = HPD_PORT_D; 3863 name = "DPDDC-D"; 3864 break; 3865 default: 3866 BUG(); 3867 } 3868 3869 if (is_edp(intel_dp)) { 3870 intel_dp_init_panel_power_timestamps(intel_dp); 3871 intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq); 3872 } 3873 3874 error = intel_dp_i2c_init(intel_dp, intel_connector, name); 3875 WARN(error, "intel_dp_i2c_init failed with error %d for port %c\n", 3876 error, port_name(port)); 3877 3878 intel_dp->psr_setup_done = false; 3879 3880 if (!intel_edp_init_connector(intel_dp, intel_connector, &power_seq)) { 3881 i2c_del_adapter(&intel_dp->adapter); 3882 if (is_edp(intel_dp)) { 3883 cancel_delayed_work_sync(&intel_dp->panel_vdd_work); 3884 mutex_lock(&dev->mode_config.mutex); 3885 edp_panel_vdd_off_sync(intel_dp); 3886 mutex_unlock(&dev->mode_config.mutex); 3887 } 3888 drm_sysfs_connector_remove(connector); 3889 drm_connector_cleanup(connector); 3890 return false; 3891 } 3892 3893 intel_dp_add_properties(intel_dp, connector); 3894 3895 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written 3896 * 0xd. Failure to do so will result in spurious interrupts being 3897 * generated on the port when a cable is not attached. 3898 */ 3899 if (IS_G4X(dev) && !IS_GM45(dev)) { 3900 u32 temp = I915_READ(PEG_BAND_GAP_DATA); 3901 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd); 3902 } 3903 3904 return true; 3905} 3906 3907void 3908intel_dp_init(struct drm_device *dev, int output_reg, enum port port) 3909{ 3910 struct intel_digital_port *intel_dig_port; 3911 struct intel_encoder *intel_encoder; 3912 struct drm_encoder *encoder; 3913 struct intel_connector *intel_connector; 3914 3915 intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL); 3916 if (!intel_dig_port) 3917 return; 3918 3919 intel_connector = kzalloc(sizeof(*intel_connector), GFP_KERNEL); 3920 if (!intel_connector) { 3921 kfree(intel_dig_port); 3922 return; 3923 } 3924 3925 intel_encoder = &intel_dig_port->base; 3926 encoder = &intel_encoder->base; 3927 3928 drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs, 3929 DRM_MODE_ENCODER_TMDS); 3930 3931 intel_encoder->compute_config = intel_dp_compute_config; 3932 intel_encoder->mode_set = intel_dp_mode_set; 3933 intel_encoder->disable = intel_disable_dp; 3934 intel_encoder->post_disable = intel_post_disable_dp; 3935 intel_encoder->get_hw_state = intel_dp_get_hw_state; 3936 intel_encoder->get_config = intel_dp_get_config; 3937 if (IS_VALLEYVIEW(dev)) { 3938 intel_encoder->pre_pll_enable = vlv_dp_pre_pll_enable; 3939 intel_encoder->pre_enable = vlv_pre_enable_dp; 3940 intel_encoder->enable = vlv_enable_dp; 3941 } else { 3942 intel_encoder->pre_enable = g4x_pre_enable_dp; 3943 intel_encoder->enable = g4x_enable_dp; 3944 } 3945 3946 intel_dig_port->port = port; 3947 intel_dig_port->dp.output_reg = output_reg; 3948 3949 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT; 3950 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2); 3951 intel_encoder->cloneable = false; 3952 intel_encoder->hot_plug = intel_dp_hot_plug; 3953 3954 if (!intel_dp_init_connector(intel_dig_port, intel_connector)) { 3955 drm_encoder_cleanup(encoder); 3956 kfree(intel_dig_port); 3957 kfree(intel_connector); 3958 } 3959} 3960