intel_dp.c revision b6f69c9a7f800c9f22cc94aa193f8451b3cc299c
1/* 2 * Copyright © 2008 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 * Authors: 24 * Keith Packard <keithp@keithp.com> 25 * 26 */ 27 28#include <linux/i2c.h> 29#include <linux/slab.h> 30#include <linux/export.h> 31#include "drmP.h" 32#include "drm.h" 33#include "drm_crtc.h" 34#include "drm_crtc_helper.h" 35#include "drm_edid.h" 36#include "intel_drv.h" 37#include "i915_drm.h" 38#include "i915_drv.h" 39 40#define DP_LINK_STATUS_SIZE 6 41#define DP_LINK_CHECK_TIMEOUT (10 * 1000) 42 43/** 44 * is_edp - is the given port attached to an eDP panel (either CPU or PCH) 45 * @intel_dp: DP struct 46 * 47 * If a CPU or PCH DP output is attached to an eDP panel, this function 48 * will return true, and false otherwise. 49 */ 50static bool is_edp(struct intel_dp *intel_dp) 51{ 52 return intel_dp->base.type == INTEL_OUTPUT_EDP; 53} 54 55/** 56 * is_pch_edp - is the port on the PCH and attached to an eDP panel? 57 * @intel_dp: DP struct 58 * 59 * Returns true if the given DP struct corresponds to a PCH DP port attached 60 * to an eDP panel, false otherwise. Helpful for determining whether we 61 * may need FDI resources for a given DP output or not. 62 */ 63static bool is_pch_edp(struct intel_dp *intel_dp) 64{ 65 return intel_dp->is_pch_edp; 66} 67 68/** 69 * is_cpu_edp - is the port on the CPU and attached to an eDP panel? 70 * @intel_dp: DP struct 71 * 72 * Returns true if the given DP struct corresponds to a CPU eDP port. 73 */ 74static bool is_cpu_edp(struct intel_dp *intel_dp) 75{ 76 return is_edp(intel_dp) && !is_pch_edp(intel_dp); 77} 78 79static struct intel_dp *enc_to_intel_dp(struct drm_encoder *encoder) 80{ 81 return container_of(encoder, struct intel_dp, base.base); 82} 83 84static struct intel_dp *intel_attached_dp(struct drm_connector *connector) 85{ 86 return container_of(intel_attached_encoder(connector), 87 struct intel_dp, base); 88} 89 90/** 91 * intel_encoder_is_pch_edp - is the given encoder a PCH attached eDP? 92 * @encoder: DRM encoder 93 * 94 * Return true if @encoder corresponds to a PCH attached eDP panel. Needed 95 * by intel_display.c. 96 */ 97bool intel_encoder_is_pch_edp(struct drm_encoder *encoder) 98{ 99 struct intel_dp *intel_dp; 100 101 if (!encoder) 102 return false; 103 104 intel_dp = enc_to_intel_dp(encoder); 105 106 return is_pch_edp(intel_dp); 107} 108 109static void intel_dp_start_link_train(struct intel_dp *intel_dp); 110static void intel_dp_complete_link_train(struct intel_dp *intel_dp); 111static void intel_dp_link_down(struct intel_dp *intel_dp); 112 113void 114intel_edp_link_config(struct intel_encoder *intel_encoder, 115 int *lane_num, int *link_bw) 116{ 117 struct intel_dp *intel_dp = container_of(intel_encoder, struct intel_dp, base); 118 119 *lane_num = intel_dp->lane_count; 120 if (intel_dp->link_bw == DP_LINK_BW_1_62) 121 *link_bw = 162000; 122 else if (intel_dp->link_bw == DP_LINK_BW_2_7) 123 *link_bw = 270000; 124} 125 126int 127intel_edp_target_clock(struct intel_encoder *intel_encoder, 128 struct drm_display_mode *mode) 129{ 130 struct intel_dp *intel_dp = container_of(intel_encoder, struct intel_dp, base); 131 132 if (intel_dp->panel_fixed_mode) 133 return intel_dp->panel_fixed_mode->clock; 134 else 135 return mode->clock; 136} 137 138static int 139intel_dp_max_lane_count(struct intel_dp *intel_dp) 140{ 141 int max_lane_count = intel_dp->dpcd[DP_MAX_LANE_COUNT] & 0x1f; 142 switch (max_lane_count) { 143 case 1: case 2: case 4: 144 break; 145 default: 146 max_lane_count = 4; 147 } 148 return max_lane_count; 149} 150 151static int 152intel_dp_max_link_bw(struct intel_dp *intel_dp) 153{ 154 int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE]; 155 156 switch (max_link_bw) { 157 case DP_LINK_BW_1_62: 158 case DP_LINK_BW_2_7: 159 break; 160 default: 161 max_link_bw = DP_LINK_BW_1_62; 162 break; 163 } 164 return max_link_bw; 165} 166 167static int 168intel_dp_link_clock(uint8_t link_bw) 169{ 170 if (link_bw == DP_LINK_BW_2_7) 171 return 270000; 172 else 173 return 162000; 174} 175 176/* 177 * The units on the numbers in the next two are... bizarre. Examples will 178 * make it clearer; this one parallels an example in the eDP spec. 179 * 180 * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as: 181 * 182 * 270000 * 1 * 8 / 10 == 216000 183 * 184 * The actual data capacity of that configuration is 2.16Gbit/s, so the 185 * units are decakilobits. ->clock in a drm_display_mode is in kilohertz - 186 * or equivalently, kilopixels per second - so for 1680x1050R it'd be 187 * 119000. At 18bpp that's 2142000 kilobits per second. 188 * 189 * Thus the strange-looking division by 10 in intel_dp_link_required, to 190 * get the result in decakilobits instead of kilobits. 191 */ 192 193static int 194intel_dp_link_required(int pixel_clock, int bpp) 195{ 196 return (pixel_clock * bpp + 9) / 10; 197} 198 199static int 200intel_dp_max_data_rate(int max_link_clock, int max_lanes) 201{ 202 return (max_link_clock * max_lanes * 8) / 10; 203} 204 205static bool 206intel_dp_adjust_dithering(struct intel_dp *intel_dp, 207 struct drm_display_mode *mode, 208 bool adjust_mode) 209{ 210 int max_link_clock = intel_dp_link_clock(intel_dp_max_link_bw(intel_dp)); 211 int max_lanes = intel_dp_max_lane_count(intel_dp); 212 int max_rate, mode_rate; 213 214 mode_rate = intel_dp_link_required(mode->clock, 24); 215 max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes); 216 217 if (mode_rate > max_rate) { 218 mode_rate = intel_dp_link_required(mode->clock, 18); 219 if (mode_rate > max_rate) 220 return false; 221 222 if (adjust_mode) 223 mode->private_flags 224 |= INTEL_MODE_DP_FORCE_6BPC; 225 226 return true; 227 } 228 229 return true; 230} 231 232static int 233intel_dp_mode_valid(struct drm_connector *connector, 234 struct drm_display_mode *mode) 235{ 236 struct intel_dp *intel_dp = intel_attached_dp(connector); 237 238 if (is_edp(intel_dp) && intel_dp->panel_fixed_mode) { 239 if (mode->hdisplay > intel_dp->panel_fixed_mode->hdisplay) 240 return MODE_PANEL; 241 242 if (mode->vdisplay > intel_dp->panel_fixed_mode->vdisplay) 243 return MODE_PANEL; 244 } 245 246 if (!intel_dp_adjust_dithering(intel_dp, mode, false)) 247 return MODE_CLOCK_HIGH; 248 249 if (mode->clock < 10000) 250 return MODE_CLOCK_LOW; 251 252 if (mode->flags & DRM_MODE_FLAG_DBLCLK) 253 return MODE_H_ILLEGAL; 254 255 return MODE_OK; 256} 257 258static uint32_t 259pack_aux(uint8_t *src, int src_bytes) 260{ 261 int i; 262 uint32_t v = 0; 263 264 if (src_bytes > 4) 265 src_bytes = 4; 266 for (i = 0; i < src_bytes; i++) 267 v |= ((uint32_t) src[i]) << ((3-i) * 8); 268 return v; 269} 270 271static void 272unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes) 273{ 274 int i; 275 if (dst_bytes > 4) 276 dst_bytes = 4; 277 for (i = 0; i < dst_bytes; i++) 278 dst[i] = src >> ((3-i) * 8); 279} 280 281/* hrawclock is 1/4 the FSB frequency */ 282static int 283intel_hrawclk(struct drm_device *dev) 284{ 285 struct drm_i915_private *dev_priv = dev->dev_private; 286 uint32_t clkcfg; 287 288 clkcfg = I915_READ(CLKCFG); 289 switch (clkcfg & CLKCFG_FSB_MASK) { 290 case CLKCFG_FSB_400: 291 return 100; 292 case CLKCFG_FSB_533: 293 return 133; 294 case CLKCFG_FSB_667: 295 return 166; 296 case CLKCFG_FSB_800: 297 return 200; 298 case CLKCFG_FSB_1067: 299 return 266; 300 case CLKCFG_FSB_1333: 301 return 333; 302 /* these two are just a guess; one of them might be right */ 303 case CLKCFG_FSB_1600: 304 case CLKCFG_FSB_1600_ALT: 305 return 400; 306 default: 307 return 133; 308 } 309} 310 311static bool ironlake_edp_have_panel_power(struct intel_dp *intel_dp) 312{ 313 struct drm_device *dev = intel_dp->base.base.dev; 314 struct drm_i915_private *dev_priv = dev->dev_private; 315 316 return (I915_READ(PCH_PP_STATUS) & PP_ON) != 0; 317} 318 319static bool ironlake_edp_have_panel_vdd(struct intel_dp *intel_dp) 320{ 321 struct drm_device *dev = intel_dp->base.base.dev; 322 struct drm_i915_private *dev_priv = dev->dev_private; 323 324 return (I915_READ(PCH_PP_CONTROL) & EDP_FORCE_VDD) != 0; 325} 326 327static void 328intel_dp_check_edp(struct intel_dp *intel_dp) 329{ 330 struct drm_device *dev = intel_dp->base.base.dev; 331 struct drm_i915_private *dev_priv = dev->dev_private; 332 333 if (!is_edp(intel_dp)) 334 return; 335 if (!ironlake_edp_have_panel_power(intel_dp) && !ironlake_edp_have_panel_vdd(intel_dp)) { 336 WARN(1, "eDP powered off while attempting aux channel communication.\n"); 337 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n", 338 I915_READ(PCH_PP_STATUS), 339 I915_READ(PCH_PP_CONTROL)); 340 } 341} 342 343static int 344intel_dp_aux_ch(struct intel_dp *intel_dp, 345 uint8_t *send, int send_bytes, 346 uint8_t *recv, int recv_size) 347{ 348 uint32_t output_reg = intel_dp->output_reg; 349 struct drm_device *dev = intel_dp->base.base.dev; 350 struct drm_i915_private *dev_priv = dev->dev_private; 351 uint32_t ch_ctl = output_reg + 0x10; 352 uint32_t ch_data = ch_ctl + 4; 353 int i; 354 int recv_bytes; 355 uint32_t status; 356 uint32_t aux_clock_divider; 357 int try, precharge; 358 359 intel_dp_check_edp(intel_dp); 360 /* The clock divider is based off the hrawclk, 361 * and would like to run at 2MHz. So, take the 362 * hrawclk value and divide by 2 and use that 363 * 364 * Note that PCH attached eDP panels should use a 125MHz input 365 * clock divider. 366 */ 367 if (is_cpu_edp(intel_dp)) { 368 if (IS_GEN6(dev) || IS_GEN7(dev)) 369 aux_clock_divider = 200; /* SNB & IVB eDP input clock at 400Mhz */ 370 else 371 aux_clock_divider = 225; /* eDP input clock at 450Mhz */ 372 } else if (HAS_PCH_SPLIT(dev)) 373 aux_clock_divider = 63; /* IRL input clock fixed at 125Mhz */ 374 else 375 aux_clock_divider = intel_hrawclk(dev) / 2; 376 377 if (IS_GEN6(dev)) 378 precharge = 3; 379 else 380 precharge = 5; 381 382 /* Try to wait for any previous AUX channel activity */ 383 for (try = 0; try < 3; try++) { 384 status = I915_READ(ch_ctl); 385 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0) 386 break; 387 msleep(1); 388 } 389 390 if (try == 3) { 391 WARN(1, "dp_aux_ch not started status 0x%08x\n", 392 I915_READ(ch_ctl)); 393 return -EBUSY; 394 } 395 396 /* Must try at least 3 times according to DP spec */ 397 for (try = 0; try < 5; try++) { 398 /* Load the send data into the aux channel data registers */ 399 for (i = 0; i < send_bytes; i += 4) 400 I915_WRITE(ch_data + i, 401 pack_aux(send + i, send_bytes - i)); 402 403 /* Send the command and wait for it to complete */ 404 I915_WRITE(ch_ctl, 405 DP_AUX_CH_CTL_SEND_BUSY | 406 DP_AUX_CH_CTL_TIME_OUT_400us | 407 (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) | 408 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) | 409 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT) | 410 DP_AUX_CH_CTL_DONE | 411 DP_AUX_CH_CTL_TIME_OUT_ERROR | 412 DP_AUX_CH_CTL_RECEIVE_ERROR); 413 for (;;) { 414 status = I915_READ(ch_ctl); 415 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0) 416 break; 417 udelay(100); 418 } 419 420 /* Clear done status and any errors */ 421 I915_WRITE(ch_ctl, 422 status | 423 DP_AUX_CH_CTL_DONE | 424 DP_AUX_CH_CTL_TIME_OUT_ERROR | 425 DP_AUX_CH_CTL_RECEIVE_ERROR); 426 427 if (status & (DP_AUX_CH_CTL_TIME_OUT_ERROR | 428 DP_AUX_CH_CTL_RECEIVE_ERROR)) 429 continue; 430 if (status & DP_AUX_CH_CTL_DONE) 431 break; 432 } 433 434 if ((status & DP_AUX_CH_CTL_DONE) == 0) { 435 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status); 436 return -EBUSY; 437 } 438 439 /* Check for timeout or receive error. 440 * Timeouts occur when the sink is not connected 441 */ 442 if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) { 443 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status); 444 return -EIO; 445 } 446 447 /* Timeouts occur when the device isn't connected, so they're 448 * "normal" -- don't fill the kernel log with these */ 449 if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) { 450 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status); 451 return -ETIMEDOUT; 452 } 453 454 /* Unload any bytes sent back from the other side */ 455 recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >> 456 DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT); 457 if (recv_bytes > recv_size) 458 recv_bytes = recv_size; 459 460 for (i = 0; i < recv_bytes; i += 4) 461 unpack_aux(I915_READ(ch_data + i), 462 recv + i, recv_bytes - i); 463 464 return recv_bytes; 465} 466 467/* Write data to the aux channel in native mode */ 468static int 469intel_dp_aux_native_write(struct intel_dp *intel_dp, 470 uint16_t address, uint8_t *send, int send_bytes) 471{ 472 int ret; 473 uint8_t msg[20]; 474 int msg_bytes; 475 uint8_t ack; 476 477 intel_dp_check_edp(intel_dp); 478 if (send_bytes > 16) 479 return -1; 480 msg[0] = AUX_NATIVE_WRITE << 4; 481 msg[1] = address >> 8; 482 msg[2] = address & 0xff; 483 msg[3] = send_bytes - 1; 484 memcpy(&msg[4], send, send_bytes); 485 msg_bytes = send_bytes + 4; 486 for (;;) { 487 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes, &ack, 1); 488 if (ret < 0) 489 return ret; 490 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK) 491 break; 492 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER) 493 udelay(100); 494 else 495 return -EIO; 496 } 497 return send_bytes; 498} 499 500/* Write a single byte to the aux channel in native mode */ 501static int 502intel_dp_aux_native_write_1(struct intel_dp *intel_dp, 503 uint16_t address, uint8_t byte) 504{ 505 return intel_dp_aux_native_write(intel_dp, address, &byte, 1); 506} 507 508/* read bytes from a native aux channel */ 509static int 510intel_dp_aux_native_read(struct intel_dp *intel_dp, 511 uint16_t address, uint8_t *recv, int recv_bytes) 512{ 513 uint8_t msg[4]; 514 int msg_bytes; 515 uint8_t reply[20]; 516 int reply_bytes; 517 uint8_t ack; 518 int ret; 519 520 intel_dp_check_edp(intel_dp); 521 msg[0] = AUX_NATIVE_READ << 4; 522 msg[1] = address >> 8; 523 msg[2] = address & 0xff; 524 msg[3] = recv_bytes - 1; 525 526 msg_bytes = 4; 527 reply_bytes = recv_bytes + 1; 528 529 for (;;) { 530 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes, 531 reply, reply_bytes); 532 if (ret == 0) 533 return -EPROTO; 534 if (ret < 0) 535 return ret; 536 ack = reply[0]; 537 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK) { 538 memcpy(recv, reply + 1, ret - 1); 539 return ret - 1; 540 } 541 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER) 542 udelay(100); 543 else 544 return -EIO; 545 } 546} 547 548static int 549intel_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode, 550 uint8_t write_byte, uint8_t *read_byte) 551{ 552 struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data; 553 struct intel_dp *intel_dp = container_of(adapter, 554 struct intel_dp, 555 adapter); 556 uint16_t address = algo_data->address; 557 uint8_t msg[5]; 558 uint8_t reply[2]; 559 unsigned retry; 560 int msg_bytes; 561 int reply_bytes; 562 int ret; 563 564 intel_dp_check_edp(intel_dp); 565 /* Set up the command byte */ 566 if (mode & MODE_I2C_READ) 567 msg[0] = AUX_I2C_READ << 4; 568 else 569 msg[0] = AUX_I2C_WRITE << 4; 570 571 if (!(mode & MODE_I2C_STOP)) 572 msg[0] |= AUX_I2C_MOT << 4; 573 574 msg[1] = address >> 8; 575 msg[2] = address; 576 577 switch (mode) { 578 case MODE_I2C_WRITE: 579 msg[3] = 0; 580 msg[4] = write_byte; 581 msg_bytes = 5; 582 reply_bytes = 1; 583 break; 584 case MODE_I2C_READ: 585 msg[3] = 0; 586 msg_bytes = 4; 587 reply_bytes = 2; 588 break; 589 default: 590 msg_bytes = 3; 591 reply_bytes = 1; 592 break; 593 } 594 595 for (retry = 0; retry < 5; retry++) { 596 ret = intel_dp_aux_ch(intel_dp, 597 msg, msg_bytes, 598 reply, reply_bytes); 599 if (ret < 0) { 600 DRM_DEBUG_KMS("aux_ch failed %d\n", ret); 601 return ret; 602 } 603 604 switch (reply[0] & AUX_NATIVE_REPLY_MASK) { 605 case AUX_NATIVE_REPLY_ACK: 606 /* I2C-over-AUX Reply field is only valid 607 * when paired with AUX ACK. 608 */ 609 break; 610 case AUX_NATIVE_REPLY_NACK: 611 DRM_DEBUG_KMS("aux_ch native nack\n"); 612 return -EREMOTEIO; 613 case AUX_NATIVE_REPLY_DEFER: 614 udelay(100); 615 continue; 616 default: 617 DRM_ERROR("aux_ch invalid native reply 0x%02x\n", 618 reply[0]); 619 return -EREMOTEIO; 620 } 621 622 switch (reply[0] & AUX_I2C_REPLY_MASK) { 623 case AUX_I2C_REPLY_ACK: 624 if (mode == MODE_I2C_READ) { 625 *read_byte = reply[1]; 626 } 627 return reply_bytes - 1; 628 case AUX_I2C_REPLY_NACK: 629 DRM_DEBUG_KMS("aux_i2c nack\n"); 630 return -EREMOTEIO; 631 case AUX_I2C_REPLY_DEFER: 632 DRM_DEBUG_KMS("aux_i2c defer\n"); 633 udelay(100); 634 break; 635 default: 636 DRM_ERROR("aux_i2c invalid reply 0x%02x\n", reply[0]); 637 return -EREMOTEIO; 638 } 639 } 640 641 DRM_ERROR("too many retries, giving up\n"); 642 return -EREMOTEIO; 643} 644 645static void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp); 646static void ironlake_edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync); 647 648static int 649intel_dp_i2c_init(struct intel_dp *intel_dp, 650 struct intel_connector *intel_connector, const char *name) 651{ 652 int ret; 653 654 DRM_DEBUG_KMS("i2c_init %s\n", name); 655 intel_dp->algo.running = false; 656 intel_dp->algo.address = 0; 657 intel_dp->algo.aux_ch = intel_dp_i2c_aux_ch; 658 659 memset(&intel_dp->adapter, '\0', sizeof(intel_dp->adapter)); 660 intel_dp->adapter.owner = THIS_MODULE; 661 intel_dp->adapter.class = I2C_CLASS_DDC; 662 strncpy(intel_dp->adapter.name, name, sizeof(intel_dp->adapter.name) - 1); 663 intel_dp->adapter.name[sizeof(intel_dp->adapter.name) - 1] = '\0'; 664 intel_dp->adapter.algo_data = &intel_dp->algo; 665 intel_dp->adapter.dev.parent = &intel_connector->base.kdev; 666 667 ironlake_edp_panel_vdd_on(intel_dp); 668 ret = i2c_dp_aux_add_bus(&intel_dp->adapter); 669 ironlake_edp_panel_vdd_off(intel_dp, false); 670 return ret; 671} 672 673static bool 674intel_dp_mode_fixup(struct drm_encoder *encoder, 675 const struct drm_display_mode *mode, 676 struct drm_display_mode *adjusted_mode) 677{ 678 struct drm_device *dev = encoder->dev; 679 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 680 int lane_count, clock; 681 int max_lane_count = intel_dp_max_lane_count(intel_dp); 682 int max_clock = intel_dp_max_link_bw(intel_dp) == DP_LINK_BW_2_7 ? 1 : 0; 683 int bpp, mode_rate; 684 static int bws[2] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7 }; 685 686 if (is_edp(intel_dp) && intel_dp->panel_fixed_mode) { 687 intel_fixed_panel_mode(intel_dp->panel_fixed_mode, adjusted_mode); 688 intel_pch_panel_fitting(dev, DRM_MODE_SCALE_FULLSCREEN, 689 mode, adjusted_mode); 690 } 691 692 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK) 693 return false; 694 695 DRM_DEBUG_KMS("DP link computation with max lane count %i " 696 "max bw %02x pixel clock %iKHz\n", 697 max_lane_count, bws[max_clock], adjusted_mode->clock); 698 699 if (!intel_dp_adjust_dithering(intel_dp, adjusted_mode, true)) 700 return false; 701 702 bpp = adjusted_mode->private_flags & INTEL_MODE_DP_FORCE_6BPC ? 18 : 24; 703 mode_rate = intel_dp_link_required(adjusted_mode->clock, bpp); 704 705 for (clock = 0; clock <= max_clock; clock++) { 706 for (lane_count = 1; lane_count <= max_lane_count; lane_count <<= 1) { 707 int link_avail = intel_dp_max_data_rate(intel_dp_link_clock(bws[clock]), lane_count); 708 709 if (mode_rate <= link_avail) { 710 intel_dp->link_bw = bws[clock]; 711 intel_dp->lane_count = lane_count; 712 adjusted_mode->clock = intel_dp_link_clock(intel_dp->link_bw); 713 DRM_DEBUG_KMS("DP link bw %02x lane " 714 "count %d clock %d bpp %d\n", 715 intel_dp->link_bw, intel_dp->lane_count, 716 adjusted_mode->clock, bpp); 717 DRM_DEBUG_KMS("DP link bw required %i available %i\n", 718 mode_rate, link_avail); 719 return true; 720 } 721 } 722 } 723 724 return false; 725} 726 727struct intel_dp_m_n { 728 uint32_t tu; 729 uint32_t gmch_m; 730 uint32_t gmch_n; 731 uint32_t link_m; 732 uint32_t link_n; 733}; 734 735static void 736intel_reduce_ratio(uint32_t *num, uint32_t *den) 737{ 738 while (*num > 0xffffff || *den > 0xffffff) { 739 *num >>= 1; 740 *den >>= 1; 741 } 742} 743 744static void 745intel_dp_compute_m_n(int bpp, 746 int nlanes, 747 int pixel_clock, 748 int link_clock, 749 struct intel_dp_m_n *m_n) 750{ 751 m_n->tu = 64; 752 m_n->gmch_m = (pixel_clock * bpp) >> 3; 753 m_n->gmch_n = link_clock * nlanes; 754 intel_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n); 755 m_n->link_m = pixel_clock; 756 m_n->link_n = link_clock; 757 intel_reduce_ratio(&m_n->link_m, &m_n->link_n); 758} 759 760void 761intel_dp_set_m_n(struct drm_crtc *crtc, struct drm_display_mode *mode, 762 struct drm_display_mode *adjusted_mode) 763{ 764 struct drm_device *dev = crtc->dev; 765 struct intel_encoder *encoder; 766 struct drm_i915_private *dev_priv = dev->dev_private; 767 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 768 int lane_count = 4; 769 struct intel_dp_m_n m_n; 770 int pipe = intel_crtc->pipe; 771 772 /* 773 * Find the lane count in the intel_encoder private 774 */ 775 for_each_encoder_on_crtc(dev, crtc, encoder) { 776 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); 777 778 if (intel_dp->base.type == INTEL_OUTPUT_DISPLAYPORT || 779 intel_dp->base.type == INTEL_OUTPUT_EDP) 780 { 781 lane_count = intel_dp->lane_count; 782 break; 783 } 784 } 785 786 /* 787 * Compute the GMCH and Link ratios. The '3' here is 788 * the number of bytes_per_pixel post-LUT, which we always 789 * set up for 8-bits of R/G/B, or 3 bytes total. 790 */ 791 intel_dp_compute_m_n(intel_crtc->bpp, lane_count, 792 mode->clock, adjusted_mode->clock, &m_n); 793 794 if (HAS_PCH_SPLIT(dev)) { 795 I915_WRITE(TRANSDATA_M1(pipe), 796 ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) | 797 m_n.gmch_m); 798 I915_WRITE(TRANSDATA_N1(pipe), m_n.gmch_n); 799 I915_WRITE(TRANSDPLINK_M1(pipe), m_n.link_m); 800 I915_WRITE(TRANSDPLINK_N1(pipe), m_n.link_n); 801 } else { 802 I915_WRITE(PIPE_GMCH_DATA_M(pipe), 803 ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) | 804 m_n.gmch_m); 805 I915_WRITE(PIPE_GMCH_DATA_N(pipe), m_n.gmch_n); 806 I915_WRITE(PIPE_DP_LINK_M(pipe), m_n.link_m); 807 I915_WRITE(PIPE_DP_LINK_N(pipe), m_n.link_n); 808 } 809} 810 811static void 812intel_dp_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode, 813 struct drm_display_mode *adjusted_mode) 814{ 815 struct drm_device *dev = encoder->dev; 816 struct drm_i915_private *dev_priv = dev->dev_private; 817 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 818 struct drm_crtc *crtc = intel_dp->base.base.crtc; 819 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 820 821 /* 822 * There are four kinds of DP registers: 823 * 824 * IBX PCH 825 * SNB CPU 826 * IVB CPU 827 * CPT PCH 828 * 829 * IBX PCH and CPU are the same for almost everything, 830 * except that the CPU DP PLL is configured in this 831 * register 832 * 833 * CPT PCH is quite different, having many bits moved 834 * to the TRANS_DP_CTL register instead. That 835 * configuration happens (oddly) in ironlake_pch_enable 836 */ 837 838 /* Preserve the BIOS-computed detected bit. This is 839 * supposed to be read-only. 840 */ 841 intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED; 842 843 /* Handle DP bits in common between all three register formats */ 844 intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0; 845 846 switch (intel_dp->lane_count) { 847 case 1: 848 intel_dp->DP |= DP_PORT_WIDTH_1; 849 break; 850 case 2: 851 intel_dp->DP |= DP_PORT_WIDTH_2; 852 break; 853 case 4: 854 intel_dp->DP |= DP_PORT_WIDTH_4; 855 break; 856 } 857 if (intel_dp->has_audio) { 858 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n", 859 pipe_name(intel_crtc->pipe)); 860 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE; 861 intel_write_eld(encoder, adjusted_mode); 862 } 863 memset(intel_dp->link_configuration, 0, DP_LINK_CONFIGURATION_SIZE); 864 intel_dp->link_configuration[0] = intel_dp->link_bw; 865 intel_dp->link_configuration[1] = intel_dp->lane_count; 866 intel_dp->link_configuration[8] = DP_SET_ANSI_8B10B; 867 /* 868 * Check for DPCD version > 1.1 and enhanced framing support 869 */ 870 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 && 871 (intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_ENHANCED_FRAME_CAP)) { 872 intel_dp->link_configuration[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN; 873 } 874 875 /* Split out the IBX/CPU vs CPT settings */ 876 877 if (is_cpu_edp(intel_dp) && IS_GEN7(dev)) { 878 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) 879 intel_dp->DP |= DP_SYNC_HS_HIGH; 880 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) 881 intel_dp->DP |= DP_SYNC_VS_HIGH; 882 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT; 883 884 if (intel_dp->link_configuration[1] & DP_LANE_COUNT_ENHANCED_FRAME_EN) 885 intel_dp->DP |= DP_ENHANCED_FRAMING; 886 887 intel_dp->DP |= intel_crtc->pipe << 29; 888 889 /* don't miss out required setting for eDP */ 890 if (adjusted_mode->clock < 200000) 891 intel_dp->DP |= DP_PLL_FREQ_160MHZ; 892 else 893 intel_dp->DP |= DP_PLL_FREQ_270MHZ; 894 } else if (!HAS_PCH_CPT(dev) || is_cpu_edp(intel_dp)) { 895 intel_dp->DP |= intel_dp->color_range; 896 897 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) 898 intel_dp->DP |= DP_SYNC_HS_HIGH; 899 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) 900 intel_dp->DP |= DP_SYNC_VS_HIGH; 901 intel_dp->DP |= DP_LINK_TRAIN_OFF; 902 903 if (intel_dp->link_configuration[1] & DP_LANE_COUNT_ENHANCED_FRAME_EN) 904 intel_dp->DP |= DP_ENHANCED_FRAMING; 905 906 if (intel_crtc->pipe == 1) 907 intel_dp->DP |= DP_PIPEB_SELECT; 908 909 if (is_cpu_edp(intel_dp)) { 910 /* don't miss out required setting for eDP */ 911 if (adjusted_mode->clock < 200000) 912 intel_dp->DP |= DP_PLL_FREQ_160MHZ; 913 else 914 intel_dp->DP |= DP_PLL_FREQ_270MHZ; 915 } 916 } else { 917 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT; 918 } 919} 920 921#define IDLE_ON_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK) 922#define IDLE_ON_VALUE (PP_ON | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE) 923 924#define IDLE_OFF_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK) 925#define IDLE_OFF_VALUE (0 | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE) 926 927#define IDLE_CYCLE_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK) 928#define IDLE_CYCLE_VALUE (0 | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE) 929 930static void ironlake_wait_panel_status(struct intel_dp *intel_dp, 931 u32 mask, 932 u32 value) 933{ 934 struct drm_device *dev = intel_dp->base.base.dev; 935 struct drm_i915_private *dev_priv = dev->dev_private; 936 937 DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n", 938 mask, value, 939 I915_READ(PCH_PP_STATUS), 940 I915_READ(PCH_PP_CONTROL)); 941 942 if (_wait_for((I915_READ(PCH_PP_STATUS) & mask) == value, 5000, 10)) { 943 DRM_ERROR("Panel status timeout: status %08x control %08x\n", 944 I915_READ(PCH_PP_STATUS), 945 I915_READ(PCH_PP_CONTROL)); 946 } 947} 948 949static void ironlake_wait_panel_on(struct intel_dp *intel_dp) 950{ 951 DRM_DEBUG_KMS("Wait for panel power on\n"); 952 ironlake_wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE); 953} 954 955static void ironlake_wait_panel_off(struct intel_dp *intel_dp) 956{ 957 DRM_DEBUG_KMS("Wait for panel power off time\n"); 958 ironlake_wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE); 959} 960 961static void ironlake_wait_panel_power_cycle(struct intel_dp *intel_dp) 962{ 963 DRM_DEBUG_KMS("Wait for panel power cycle\n"); 964 ironlake_wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE); 965} 966 967 968/* Read the current pp_control value, unlocking the register if it 969 * is locked 970 */ 971 972static u32 ironlake_get_pp_control(struct drm_i915_private *dev_priv) 973{ 974 u32 control = I915_READ(PCH_PP_CONTROL); 975 976 control &= ~PANEL_UNLOCK_MASK; 977 control |= PANEL_UNLOCK_REGS; 978 return control; 979} 980 981static void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp) 982{ 983 struct drm_device *dev = intel_dp->base.base.dev; 984 struct drm_i915_private *dev_priv = dev->dev_private; 985 u32 pp; 986 987 if (!is_edp(intel_dp)) 988 return; 989 DRM_DEBUG_KMS("Turn eDP VDD on\n"); 990 991 WARN(intel_dp->want_panel_vdd, 992 "eDP VDD already requested on\n"); 993 994 intel_dp->want_panel_vdd = true; 995 996 if (ironlake_edp_have_panel_vdd(intel_dp)) { 997 DRM_DEBUG_KMS("eDP VDD already on\n"); 998 return; 999 } 1000 1001 if (!ironlake_edp_have_panel_power(intel_dp)) 1002 ironlake_wait_panel_power_cycle(intel_dp); 1003 1004 pp = ironlake_get_pp_control(dev_priv); 1005 pp |= EDP_FORCE_VDD; 1006 I915_WRITE(PCH_PP_CONTROL, pp); 1007 POSTING_READ(PCH_PP_CONTROL); 1008 DRM_DEBUG_KMS("PCH_PP_STATUS: 0x%08x PCH_PP_CONTROL: 0x%08x\n", 1009 I915_READ(PCH_PP_STATUS), I915_READ(PCH_PP_CONTROL)); 1010 1011 /* 1012 * If the panel wasn't on, delay before accessing aux channel 1013 */ 1014 if (!ironlake_edp_have_panel_power(intel_dp)) { 1015 DRM_DEBUG_KMS("eDP was not running\n"); 1016 msleep(intel_dp->panel_power_up_delay); 1017 } 1018} 1019 1020static void ironlake_panel_vdd_off_sync(struct intel_dp *intel_dp) 1021{ 1022 struct drm_device *dev = intel_dp->base.base.dev; 1023 struct drm_i915_private *dev_priv = dev->dev_private; 1024 u32 pp; 1025 1026 if (!intel_dp->want_panel_vdd && ironlake_edp_have_panel_vdd(intel_dp)) { 1027 pp = ironlake_get_pp_control(dev_priv); 1028 pp &= ~EDP_FORCE_VDD; 1029 I915_WRITE(PCH_PP_CONTROL, pp); 1030 POSTING_READ(PCH_PP_CONTROL); 1031 1032 /* Make sure sequencer is idle before allowing subsequent activity */ 1033 DRM_DEBUG_KMS("PCH_PP_STATUS: 0x%08x PCH_PP_CONTROL: 0x%08x\n", 1034 I915_READ(PCH_PP_STATUS), I915_READ(PCH_PP_CONTROL)); 1035 1036 msleep(intel_dp->panel_power_down_delay); 1037 } 1038} 1039 1040static void ironlake_panel_vdd_work(struct work_struct *__work) 1041{ 1042 struct intel_dp *intel_dp = container_of(to_delayed_work(__work), 1043 struct intel_dp, panel_vdd_work); 1044 struct drm_device *dev = intel_dp->base.base.dev; 1045 1046 mutex_lock(&dev->mode_config.mutex); 1047 ironlake_panel_vdd_off_sync(intel_dp); 1048 mutex_unlock(&dev->mode_config.mutex); 1049} 1050 1051static void ironlake_edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync) 1052{ 1053 if (!is_edp(intel_dp)) 1054 return; 1055 1056 DRM_DEBUG_KMS("Turn eDP VDD off %d\n", intel_dp->want_panel_vdd); 1057 WARN(!intel_dp->want_panel_vdd, "eDP VDD not forced on"); 1058 1059 intel_dp->want_panel_vdd = false; 1060 1061 if (sync) { 1062 ironlake_panel_vdd_off_sync(intel_dp); 1063 } else { 1064 /* 1065 * Queue the timer to fire a long 1066 * time from now (relative to the power down delay) 1067 * to keep the panel power up across a sequence of operations 1068 */ 1069 schedule_delayed_work(&intel_dp->panel_vdd_work, 1070 msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5)); 1071 } 1072} 1073 1074static void ironlake_edp_panel_on(struct intel_dp *intel_dp) 1075{ 1076 struct drm_device *dev = intel_dp->base.base.dev; 1077 struct drm_i915_private *dev_priv = dev->dev_private; 1078 u32 pp; 1079 1080 if (!is_edp(intel_dp)) 1081 return; 1082 1083 DRM_DEBUG_KMS("Turn eDP power on\n"); 1084 1085 if (ironlake_edp_have_panel_power(intel_dp)) { 1086 DRM_DEBUG_KMS("eDP power already on\n"); 1087 return; 1088 } 1089 1090 ironlake_wait_panel_power_cycle(intel_dp); 1091 1092 pp = ironlake_get_pp_control(dev_priv); 1093 if (IS_GEN5(dev)) { 1094 /* ILK workaround: disable reset around power sequence */ 1095 pp &= ~PANEL_POWER_RESET; 1096 I915_WRITE(PCH_PP_CONTROL, pp); 1097 POSTING_READ(PCH_PP_CONTROL); 1098 } 1099 1100 pp |= POWER_TARGET_ON; 1101 if (!IS_GEN5(dev)) 1102 pp |= PANEL_POWER_RESET; 1103 1104 I915_WRITE(PCH_PP_CONTROL, pp); 1105 POSTING_READ(PCH_PP_CONTROL); 1106 1107 ironlake_wait_panel_on(intel_dp); 1108 1109 if (IS_GEN5(dev)) { 1110 pp |= PANEL_POWER_RESET; /* restore panel reset bit */ 1111 I915_WRITE(PCH_PP_CONTROL, pp); 1112 POSTING_READ(PCH_PP_CONTROL); 1113 } 1114} 1115 1116static void ironlake_edp_panel_off(struct intel_dp *intel_dp) 1117{ 1118 struct drm_device *dev = intel_dp->base.base.dev; 1119 struct drm_i915_private *dev_priv = dev->dev_private; 1120 u32 pp; 1121 1122 if (!is_edp(intel_dp)) 1123 return; 1124 1125 DRM_DEBUG_KMS("Turn eDP power off\n"); 1126 1127 WARN(!intel_dp->want_panel_vdd, "Need VDD to turn off panel\n"); 1128 1129 pp = ironlake_get_pp_control(dev_priv); 1130 /* We need to switch off panel power _and_ force vdd, for otherwise some 1131 * panels get very unhappy and cease to work. */ 1132 pp &= ~(POWER_TARGET_ON | EDP_FORCE_VDD | PANEL_POWER_RESET | EDP_BLC_ENABLE); 1133 I915_WRITE(PCH_PP_CONTROL, pp); 1134 POSTING_READ(PCH_PP_CONTROL); 1135 1136 intel_dp->want_panel_vdd = false; 1137 1138 ironlake_wait_panel_off(intel_dp); 1139} 1140 1141static void ironlake_edp_backlight_on(struct intel_dp *intel_dp) 1142{ 1143 struct drm_device *dev = intel_dp->base.base.dev; 1144 struct drm_i915_private *dev_priv = dev->dev_private; 1145 u32 pp; 1146 1147 if (!is_edp(intel_dp)) 1148 return; 1149 1150 DRM_DEBUG_KMS("\n"); 1151 /* 1152 * If we enable the backlight right away following a panel power 1153 * on, we may see slight flicker as the panel syncs with the eDP 1154 * link. So delay a bit to make sure the image is solid before 1155 * allowing it to appear. 1156 */ 1157 msleep(intel_dp->backlight_on_delay); 1158 pp = ironlake_get_pp_control(dev_priv); 1159 pp |= EDP_BLC_ENABLE; 1160 I915_WRITE(PCH_PP_CONTROL, pp); 1161 POSTING_READ(PCH_PP_CONTROL); 1162} 1163 1164static void ironlake_edp_backlight_off(struct intel_dp *intel_dp) 1165{ 1166 struct drm_device *dev = intel_dp->base.base.dev; 1167 struct drm_i915_private *dev_priv = dev->dev_private; 1168 u32 pp; 1169 1170 if (!is_edp(intel_dp)) 1171 return; 1172 1173 DRM_DEBUG_KMS("\n"); 1174 pp = ironlake_get_pp_control(dev_priv); 1175 pp &= ~EDP_BLC_ENABLE; 1176 I915_WRITE(PCH_PP_CONTROL, pp); 1177 POSTING_READ(PCH_PP_CONTROL); 1178 msleep(intel_dp->backlight_off_delay); 1179} 1180 1181static void ironlake_edp_pll_on(struct intel_dp *intel_dp) 1182{ 1183 struct drm_device *dev = intel_dp->base.base.dev; 1184 struct drm_crtc *crtc = intel_dp->base.base.crtc; 1185 struct drm_i915_private *dev_priv = dev->dev_private; 1186 u32 dpa_ctl; 1187 1188 assert_pipe_disabled(dev_priv, 1189 to_intel_crtc(crtc)->pipe); 1190 1191 DRM_DEBUG_KMS("\n"); 1192 dpa_ctl = I915_READ(DP_A); 1193 WARN(dpa_ctl & DP_PLL_ENABLE, "dp pll on, should be off\n"); 1194 WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n"); 1195 1196 /* We don't adjust intel_dp->DP while tearing down the link, to 1197 * facilitate link retraining (e.g. after hotplug). Hence clear all 1198 * enable bits here to ensure that we don't enable too much. */ 1199 intel_dp->DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE); 1200 intel_dp->DP |= DP_PLL_ENABLE; 1201 I915_WRITE(DP_A, intel_dp->DP); 1202 POSTING_READ(DP_A); 1203 udelay(200); 1204} 1205 1206static void ironlake_edp_pll_off(struct intel_dp *intel_dp) 1207{ 1208 struct drm_device *dev = intel_dp->base.base.dev; 1209 struct drm_crtc *crtc = intel_dp->base.base.crtc; 1210 struct drm_i915_private *dev_priv = dev->dev_private; 1211 u32 dpa_ctl; 1212 1213 assert_pipe_disabled(dev_priv, 1214 to_intel_crtc(crtc)->pipe); 1215 1216 dpa_ctl = I915_READ(DP_A); 1217 WARN((dpa_ctl & DP_PLL_ENABLE) == 0, 1218 "dp pll off, should be on\n"); 1219 WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n"); 1220 1221 /* We can't rely on the value tracked for the DP register in 1222 * intel_dp->DP because link_down must not change that (otherwise link 1223 * re-training will fail. */ 1224 dpa_ctl &= ~DP_PLL_ENABLE; 1225 I915_WRITE(DP_A, dpa_ctl); 1226 POSTING_READ(DP_A); 1227 udelay(200); 1228} 1229 1230/* If the sink supports it, try to set the power state appropriately */ 1231static void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode) 1232{ 1233 int ret, i; 1234 1235 /* Should have a valid DPCD by this point */ 1236 if (intel_dp->dpcd[DP_DPCD_REV] < 0x11) 1237 return; 1238 1239 if (mode != DRM_MODE_DPMS_ON) { 1240 ret = intel_dp_aux_native_write_1(intel_dp, DP_SET_POWER, 1241 DP_SET_POWER_D3); 1242 if (ret != 1) 1243 DRM_DEBUG_DRIVER("failed to write sink power state\n"); 1244 } else { 1245 /* 1246 * When turning on, we need to retry for 1ms to give the sink 1247 * time to wake up. 1248 */ 1249 for (i = 0; i < 3; i++) { 1250 ret = intel_dp_aux_native_write_1(intel_dp, 1251 DP_SET_POWER, 1252 DP_SET_POWER_D0); 1253 if (ret == 1) 1254 break; 1255 msleep(1); 1256 } 1257 } 1258} 1259 1260static bool intel_dp_get_hw_state(struct intel_encoder *encoder, 1261 enum pipe *pipe) 1262{ 1263 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); 1264 struct drm_device *dev = encoder->base.dev; 1265 struct drm_i915_private *dev_priv = dev->dev_private; 1266 u32 tmp = I915_READ(intel_dp->output_reg); 1267 1268 if (!(tmp & DP_PORT_EN)) 1269 return false; 1270 1271 if (is_cpu_edp(intel_dp) && IS_GEN7(dev)) { 1272 *pipe = PORT_TO_PIPE_CPT(tmp); 1273 } else if (!HAS_PCH_CPT(dev) || is_cpu_edp(intel_dp)) { 1274 *pipe = PORT_TO_PIPE(tmp); 1275 } else { 1276 u32 trans_sel; 1277 u32 trans_dp; 1278 int i; 1279 1280 switch (intel_dp->output_reg) { 1281 case PCH_DP_B: 1282 trans_sel = TRANS_DP_PORT_SEL_B; 1283 break; 1284 case PCH_DP_C: 1285 trans_sel = TRANS_DP_PORT_SEL_C; 1286 break; 1287 case PCH_DP_D: 1288 trans_sel = TRANS_DP_PORT_SEL_D; 1289 break; 1290 default: 1291 return true; 1292 } 1293 1294 for_each_pipe(i) { 1295 trans_dp = I915_READ(TRANS_DP_CTL(i)); 1296 if ((trans_dp & TRANS_DP_PORT_SEL_MASK) == trans_sel) { 1297 *pipe = i; 1298 return true; 1299 } 1300 } 1301 } 1302 1303 DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n", intel_dp->output_reg); 1304 1305 return true; 1306} 1307 1308static void intel_disable_dp(struct intel_encoder *encoder) 1309{ 1310 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); 1311 1312 /* Make sure the panel is off before trying to change the mode. But also 1313 * ensure that we have vdd while we switch off the panel. */ 1314 ironlake_edp_panel_vdd_on(intel_dp); 1315 ironlake_edp_backlight_off(intel_dp); 1316 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON); 1317 ironlake_edp_panel_off(intel_dp); 1318 1319 /* cpu edp my only be disable _after_ the cpu pipe/plane is disabled. */ 1320 if (!is_cpu_edp(intel_dp)) 1321 intel_dp_link_down(intel_dp); 1322} 1323 1324static void intel_post_disable_dp(struct intel_encoder *encoder) 1325{ 1326 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); 1327 1328 if (is_cpu_edp(intel_dp)) { 1329 intel_dp_link_down(intel_dp); 1330 ironlake_edp_pll_off(intel_dp); 1331 } 1332} 1333 1334static void intel_enable_dp(struct intel_encoder *encoder) 1335{ 1336 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); 1337 struct drm_device *dev = encoder->base.dev; 1338 struct drm_i915_private *dev_priv = dev->dev_private; 1339 uint32_t dp_reg = I915_READ(intel_dp->output_reg); 1340 1341 if (WARN_ON(dp_reg & DP_PORT_EN)) 1342 return; 1343 1344 ironlake_edp_panel_vdd_on(intel_dp); 1345 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON); 1346 intel_dp_start_link_train(intel_dp); 1347 ironlake_edp_panel_on(intel_dp); 1348 ironlake_edp_panel_vdd_off(intel_dp, true); 1349 intel_dp_complete_link_train(intel_dp); 1350 ironlake_edp_backlight_on(intel_dp); 1351} 1352 1353static void intel_pre_enable_dp(struct intel_encoder *encoder) 1354{ 1355 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); 1356 1357 if (is_cpu_edp(intel_dp)) 1358 ironlake_edp_pll_on(intel_dp); 1359} 1360 1361/* 1362 * Native read with retry for link status and receiver capability reads for 1363 * cases where the sink may still be asleep. 1364 */ 1365static bool 1366intel_dp_aux_native_read_retry(struct intel_dp *intel_dp, uint16_t address, 1367 uint8_t *recv, int recv_bytes) 1368{ 1369 int ret, i; 1370 1371 /* 1372 * Sinks are *supposed* to come up within 1ms from an off state, 1373 * but we're also supposed to retry 3 times per the spec. 1374 */ 1375 for (i = 0; i < 3; i++) { 1376 ret = intel_dp_aux_native_read(intel_dp, address, recv, 1377 recv_bytes); 1378 if (ret == recv_bytes) 1379 return true; 1380 msleep(1); 1381 } 1382 1383 return false; 1384} 1385 1386/* 1387 * Fetch AUX CH registers 0x202 - 0x207 which contain 1388 * link status information 1389 */ 1390static bool 1391intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE]) 1392{ 1393 return intel_dp_aux_native_read_retry(intel_dp, 1394 DP_LANE0_1_STATUS, 1395 link_status, 1396 DP_LINK_STATUS_SIZE); 1397} 1398 1399static uint8_t 1400intel_dp_link_status(uint8_t link_status[DP_LINK_STATUS_SIZE], 1401 int r) 1402{ 1403 return link_status[r - DP_LANE0_1_STATUS]; 1404} 1405 1406static uint8_t 1407intel_get_adjust_request_voltage(uint8_t adjust_request[2], 1408 int lane) 1409{ 1410 int s = ((lane & 1) ? 1411 DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT : 1412 DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT); 1413 uint8_t l = adjust_request[lane>>1]; 1414 1415 return ((l >> s) & 3) << DP_TRAIN_VOLTAGE_SWING_SHIFT; 1416} 1417 1418static uint8_t 1419intel_get_adjust_request_pre_emphasis(uint8_t adjust_request[2], 1420 int lane) 1421{ 1422 int s = ((lane & 1) ? 1423 DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT : 1424 DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT); 1425 uint8_t l = adjust_request[lane>>1]; 1426 1427 return ((l >> s) & 3) << DP_TRAIN_PRE_EMPHASIS_SHIFT; 1428} 1429 1430 1431#if 0 1432static char *voltage_names[] = { 1433 "0.4V", "0.6V", "0.8V", "1.2V" 1434}; 1435static char *pre_emph_names[] = { 1436 "0dB", "3.5dB", "6dB", "9.5dB" 1437}; 1438static char *link_train_names[] = { 1439 "pattern 1", "pattern 2", "idle", "off" 1440}; 1441#endif 1442 1443/* 1444 * These are source-specific values; current Intel hardware supports 1445 * a maximum voltage of 800mV and a maximum pre-emphasis of 6dB 1446 */ 1447 1448static uint8_t 1449intel_dp_voltage_max(struct intel_dp *intel_dp) 1450{ 1451 struct drm_device *dev = intel_dp->base.base.dev; 1452 1453 if (IS_GEN7(dev) && is_cpu_edp(intel_dp)) 1454 return DP_TRAIN_VOLTAGE_SWING_800; 1455 else if (HAS_PCH_CPT(dev) && !is_cpu_edp(intel_dp)) 1456 return DP_TRAIN_VOLTAGE_SWING_1200; 1457 else 1458 return DP_TRAIN_VOLTAGE_SWING_800; 1459} 1460 1461static uint8_t 1462intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing) 1463{ 1464 struct drm_device *dev = intel_dp->base.base.dev; 1465 1466 if (IS_GEN7(dev) && is_cpu_edp(intel_dp)) { 1467 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) { 1468 case DP_TRAIN_VOLTAGE_SWING_400: 1469 return DP_TRAIN_PRE_EMPHASIS_6; 1470 case DP_TRAIN_VOLTAGE_SWING_600: 1471 case DP_TRAIN_VOLTAGE_SWING_800: 1472 return DP_TRAIN_PRE_EMPHASIS_3_5; 1473 default: 1474 return DP_TRAIN_PRE_EMPHASIS_0; 1475 } 1476 } else { 1477 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) { 1478 case DP_TRAIN_VOLTAGE_SWING_400: 1479 return DP_TRAIN_PRE_EMPHASIS_6; 1480 case DP_TRAIN_VOLTAGE_SWING_600: 1481 return DP_TRAIN_PRE_EMPHASIS_6; 1482 case DP_TRAIN_VOLTAGE_SWING_800: 1483 return DP_TRAIN_PRE_EMPHASIS_3_5; 1484 case DP_TRAIN_VOLTAGE_SWING_1200: 1485 default: 1486 return DP_TRAIN_PRE_EMPHASIS_0; 1487 } 1488 } 1489} 1490 1491static void 1492intel_get_adjust_train(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE]) 1493{ 1494 uint8_t v = 0; 1495 uint8_t p = 0; 1496 int lane; 1497 uint8_t *adjust_request = link_status + (DP_ADJUST_REQUEST_LANE0_1 - DP_LANE0_1_STATUS); 1498 uint8_t voltage_max; 1499 uint8_t preemph_max; 1500 1501 for (lane = 0; lane < intel_dp->lane_count; lane++) { 1502 uint8_t this_v = intel_get_adjust_request_voltage(adjust_request, lane); 1503 uint8_t this_p = intel_get_adjust_request_pre_emphasis(adjust_request, lane); 1504 1505 if (this_v > v) 1506 v = this_v; 1507 if (this_p > p) 1508 p = this_p; 1509 } 1510 1511 voltage_max = intel_dp_voltage_max(intel_dp); 1512 if (v >= voltage_max) 1513 v = voltage_max | DP_TRAIN_MAX_SWING_REACHED; 1514 1515 preemph_max = intel_dp_pre_emphasis_max(intel_dp, v); 1516 if (p >= preemph_max) 1517 p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED; 1518 1519 for (lane = 0; lane < 4; lane++) 1520 intel_dp->train_set[lane] = v | p; 1521} 1522 1523static uint32_t 1524intel_dp_signal_levels(uint8_t train_set) 1525{ 1526 uint32_t signal_levels = 0; 1527 1528 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { 1529 case DP_TRAIN_VOLTAGE_SWING_400: 1530 default: 1531 signal_levels |= DP_VOLTAGE_0_4; 1532 break; 1533 case DP_TRAIN_VOLTAGE_SWING_600: 1534 signal_levels |= DP_VOLTAGE_0_6; 1535 break; 1536 case DP_TRAIN_VOLTAGE_SWING_800: 1537 signal_levels |= DP_VOLTAGE_0_8; 1538 break; 1539 case DP_TRAIN_VOLTAGE_SWING_1200: 1540 signal_levels |= DP_VOLTAGE_1_2; 1541 break; 1542 } 1543 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) { 1544 case DP_TRAIN_PRE_EMPHASIS_0: 1545 default: 1546 signal_levels |= DP_PRE_EMPHASIS_0; 1547 break; 1548 case DP_TRAIN_PRE_EMPHASIS_3_5: 1549 signal_levels |= DP_PRE_EMPHASIS_3_5; 1550 break; 1551 case DP_TRAIN_PRE_EMPHASIS_6: 1552 signal_levels |= DP_PRE_EMPHASIS_6; 1553 break; 1554 case DP_TRAIN_PRE_EMPHASIS_9_5: 1555 signal_levels |= DP_PRE_EMPHASIS_9_5; 1556 break; 1557 } 1558 return signal_levels; 1559} 1560 1561/* Gen6's DP voltage swing and pre-emphasis control */ 1562static uint32_t 1563intel_gen6_edp_signal_levels(uint8_t train_set) 1564{ 1565 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK | 1566 DP_TRAIN_PRE_EMPHASIS_MASK); 1567 switch (signal_levels) { 1568 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0: 1569 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0: 1570 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B; 1571 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5: 1572 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B; 1573 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6: 1574 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6: 1575 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B; 1576 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5: 1577 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5: 1578 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B; 1579 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0: 1580 case DP_TRAIN_VOLTAGE_SWING_1200 | DP_TRAIN_PRE_EMPHASIS_0: 1581 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B; 1582 default: 1583 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:" 1584 "0x%x\n", signal_levels); 1585 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B; 1586 } 1587} 1588 1589/* Gen7's DP voltage swing and pre-emphasis control */ 1590static uint32_t 1591intel_gen7_edp_signal_levels(uint8_t train_set) 1592{ 1593 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK | 1594 DP_TRAIN_PRE_EMPHASIS_MASK); 1595 switch (signal_levels) { 1596 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0: 1597 return EDP_LINK_TRAIN_400MV_0DB_IVB; 1598 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5: 1599 return EDP_LINK_TRAIN_400MV_3_5DB_IVB; 1600 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6: 1601 return EDP_LINK_TRAIN_400MV_6DB_IVB; 1602 1603 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0: 1604 return EDP_LINK_TRAIN_600MV_0DB_IVB; 1605 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5: 1606 return EDP_LINK_TRAIN_600MV_3_5DB_IVB; 1607 1608 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0: 1609 return EDP_LINK_TRAIN_800MV_0DB_IVB; 1610 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5: 1611 return EDP_LINK_TRAIN_800MV_3_5DB_IVB; 1612 1613 default: 1614 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:" 1615 "0x%x\n", signal_levels); 1616 return EDP_LINK_TRAIN_500MV_0DB_IVB; 1617 } 1618} 1619 1620static uint8_t 1621intel_get_lane_status(uint8_t link_status[DP_LINK_STATUS_SIZE], 1622 int lane) 1623{ 1624 int s = (lane & 1) * 4; 1625 uint8_t l = link_status[lane>>1]; 1626 1627 return (l >> s) & 0xf; 1628} 1629 1630/* Check for clock recovery is done on all channels */ 1631static bool 1632intel_clock_recovery_ok(uint8_t link_status[DP_LINK_STATUS_SIZE], int lane_count) 1633{ 1634 int lane; 1635 uint8_t lane_status; 1636 1637 for (lane = 0; lane < lane_count; lane++) { 1638 lane_status = intel_get_lane_status(link_status, lane); 1639 if ((lane_status & DP_LANE_CR_DONE) == 0) 1640 return false; 1641 } 1642 return true; 1643} 1644 1645/* Check to see if channel eq is done on all channels */ 1646#define CHANNEL_EQ_BITS (DP_LANE_CR_DONE|\ 1647 DP_LANE_CHANNEL_EQ_DONE|\ 1648 DP_LANE_SYMBOL_LOCKED) 1649static bool 1650intel_channel_eq_ok(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE]) 1651{ 1652 uint8_t lane_align; 1653 uint8_t lane_status; 1654 int lane; 1655 1656 lane_align = intel_dp_link_status(link_status, 1657 DP_LANE_ALIGN_STATUS_UPDATED); 1658 if ((lane_align & DP_INTERLANE_ALIGN_DONE) == 0) 1659 return false; 1660 for (lane = 0; lane < intel_dp->lane_count; lane++) { 1661 lane_status = intel_get_lane_status(link_status, lane); 1662 if ((lane_status & CHANNEL_EQ_BITS) != CHANNEL_EQ_BITS) 1663 return false; 1664 } 1665 return true; 1666} 1667 1668static bool 1669intel_dp_set_link_train(struct intel_dp *intel_dp, 1670 uint32_t dp_reg_value, 1671 uint8_t dp_train_pat) 1672{ 1673 struct drm_device *dev = intel_dp->base.base.dev; 1674 struct drm_i915_private *dev_priv = dev->dev_private; 1675 int ret; 1676 1677 if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || !is_cpu_edp(intel_dp))) { 1678 dp_reg_value &= ~DP_LINK_TRAIN_MASK_CPT; 1679 1680 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) { 1681 case DP_TRAINING_PATTERN_DISABLE: 1682 dp_reg_value |= DP_LINK_TRAIN_OFF_CPT; 1683 break; 1684 case DP_TRAINING_PATTERN_1: 1685 dp_reg_value |= DP_LINK_TRAIN_PAT_1_CPT; 1686 break; 1687 case DP_TRAINING_PATTERN_2: 1688 dp_reg_value |= DP_LINK_TRAIN_PAT_2_CPT; 1689 break; 1690 case DP_TRAINING_PATTERN_3: 1691 DRM_ERROR("DP training pattern 3 not supported\n"); 1692 dp_reg_value |= DP_LINK_TRAIN_PAT_2_CPT; 1693 break; 1694 } 1695 1696 } else { 1697 dp_reg_value &= ~DP_LINK_TRAIN_MASK; 1698 1699 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) { 1700 case DP_TRAINING_PATTERN_DISABLE: 1701 dp_reg_value |= DP_LINK_TRAIN_OFF; 1702 break; 1703 case DP_TRAINING_PATTERN_1: 1704 dp_reg_value |= DP_LINK_TRAIN_PAT_1; 1705 break; 1706 case DP_TRAINING_PATTERN_2: 1707 dp_reg_value |= DP_LINK_TRAIN_PAT_2; 1708 break; 1709 case DP_TRAINING_PATTERN_3: 1710 DRM_ERROR("DP training pattern 3 not supported\n"); 1711 dp_reg_value |= DP_LINK_TRAIN_PAT_2; 1712 break; 1713 } 1714 } 1715 1716 I915_WRITE(intel_dp->output_reg, dp_reg_value); 1717 POSTING_READ(intel_dp->output_reg); 1718 1719 intel_dp_aux_native_write_1(intel_dp, 1720 DP_TRAINING_PATTERN_SET, 1721 dp_train_pat); 1722 1723 if ((dp_train_pat & DP_TRAINING_PATTERN_MASK) != 1724 DP_TRAINING_PATTERN_DISABLE) { 1725 ret = intel_dp_aux_native_write(intel_dp, 1726 DP_TRAINING_LANE0_SET, 1727 intel_dp->train_set, 1728 intel_dp->lane_count); 1729 if (ret != intel_dp->lane_count) 1730 return false; 1731 } 1732 1733 return true; 1734} 1735 1736/* Enable corresponding port and start training pattern 1 */ 1737static void 1738intel_dp_start_link_train(struct intel_dp *intel_dp) 1739{ 1740 struct drm_device *dev = intel_dp->base.base.dev; 1741 int i; 1742 uint8_t voltage; 1743 bool clock_recovery = false; 1744 int voltage_tries, loop_tries; 1745 uint32_t DP = intel_dp->DP; 1746 1747 /* Write the link configuration data */ 1748 intel_dp_aux_native_write(intel_dp, DP_LINK_BW_SET, 1749 intel_dp->link_configuration, 1750 DP_LINK_CONFIGURATION_SIZE); 1751 1752 DP |= DP_PORT_EN; 1753 1754 memset(intel_dp->train_set, 0, 4); 1755 voltage = 0xff; 1756 voltage_tries = 0; 1757 loop_tries = 0; 1758 clock_recovery = false; 1759 for (;;) { 1760 /* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */ 1761 uint8_t link_status[DP_LINK_STATUS_SIZE]; 1762 uint32_t signal_levels; 1763 1764 1765 if (IS_GEN7(dev) && is_cpu_edp(intel_dp)) { 1766 signal_levels = intel_gen7_edp_signal_levels(intel_dp->train_set[0]); 1767 DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_IVB) | signal_levels; 1768 } else if (IS_GEN6(dev) && is_cpu_edp(intel_dp)) { 1769 signal_levels = intel_gen6_edp_signal_levels(intel_dp->train_set[0]); 1770 DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB) | signal_levels; 1771 } else { 1772 signal_levels = intel_dp_signal_levels(intel_dp->train_set[0]); 1773 DRM_DEBUG_KMS("training pattern 1 signal levels %08x\n", signal_levels); 1774 DP = (DP & ~(DP_VOLTAGE_MASK|DP_PRE_EMPHASIS_MASK)) | signal_levels; 1775 } 1776 1777 if (!intel_dp_set_link_train(intel_dp, DP, 1778 DP_TRAINING_PATTERN_1 | 1779 DP_LINK_SCRAMBLING_DISABLE)) 1780 break; 1781 /* Set training pattern 1 */ 1782 1783 udelay(100); 1784 if (!intel_dp_get_link_status(intel_dp, link_status)) { 1785 DRM_ERROR("failed to get link status\n"); 1786 break; 1787 } 1788 1789 if (intel_clock_recovery_ok(link_status, intel_dp->lane_count)) { 1790 DRM_DEBUG_KMS("clock recovery OK\n"); 1791 clock_recovery = true; 1792 break; 1793 } 1794 1795 /* Check to see if we've tried the max voltage */ 1796 for (i = 0; i < intel_dp->lane_count; i++) 1797 if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0) 1798 break; 1799 if (i == intel_dp->lane_count && voltage_tries == 5) { 1800 ++loop_tries; 1801 if (loop_tries == 5) { 1802 DRM_DEBUG_KMS("too many full retries, give up\n"); 1803 break; 1804 } 1805 memset(intel_dp->train_set, 0, 4); 1806 voltage_tries = 0; 1807 continue; 1808 } 1809 1810 /* Check to see if we've tried the same voltage 5 times */ 1811 if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) { 1812 ++voltage_tries; 1813 if (voltage_tries == 5) { 1814 DRM_DEBUG_KMS("too many voltage retries, give up\n"); 1815 break; 1816 } 1817 } else 1818 voltage_tries = 0; 1819 voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK; 1820 1821 /* Compute new intel_dp->train_set as requested by target */ 1822 intel_get_adjust_train(intel_dp, link_status); 1823 } 1824 1825 intel_dp->DP = DP; 1826} 1827 1828static void 1829intel_dp_complete_link_train(struct intel_dp *intel_dp) 1830{ 1831 struct drm_device *dev = intel_dp->base.base.dev; 1832 bool channel_eq = false; 1833 int tries, cr_tries; 1834 uint32_t DP = intel_dp->DP; 1835 1836 /* channel equalization */ 1837 tries = 0; 1838 cr_tries = 0; 1839 channel_eq = false; 1840 for (;;) { 1841 /* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */ 1842 uint32_t signal_levels; 1843 uint8_t link_status[DP_LINK_STATUS_SIZE]; 1844 1845 if (cr_tries > 5) { 1846 DRM_ERROR("failed to train DP, aborting\n"); 1847 intel_dp_link_down(intel_dp); 1848 break; 1849 } 1850 1851 if (IS_GEN7(dev) && is_cpu_edp(intel_dp)) { 1852 signal_levels = intel_gen7_edp_signal_levels(intel_dp->train_set[0]); 1853 DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_IVB) | signal_levels; 1854 } else if (IS_GEN6(dev) && is_cpu_edp(intel_dp)) { 1855 signal_levels = intel_gen6_edp_signal_levels(intel_dp->train_set[0]); 1856 DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB) | signal_levels; 1857 } else { 1858 signal_levels = intel_dp_signal_levels(intel_dp->train_set[0]); 1859 DP = (DP & ~(DP_VOLTAGE_MASK|DP_PRE_EMPHASIS_MASK)) | signal_levels; 1860 } 1861 1862 /* channel eq pattern */ 1863 if (!intel_dp_set_link_train(intel_dp, DP, 1864 DP_TRAINING_PATTERN_2 | 1865 DP_LINK_SCRAMBLING_DISABLE)) 1866 break; 1867 1868 udelay(400); 1869 if (!intel_dp_get_link_status(intel_dp, link_status)) 1870 break; 1871 1872 /* Make sure clock is still ok */ 1873 if (!intel_clock_recovery_ok(link_status, intel_dp->lane_count)) { 1874 intel_dp_start_link_train(intel_dp); 1875 cr_tries++; 1876 continue; 1877 } 1878 1879 if (intel_channel_eq_ok(intel_dp, link_status)) { 1880 channel_eq = true; 1881 break; 1882 } 1883 1884 /* Try 5 times, then try clock recovery if that fails */ 1885 if (tries > 5) { 1886 intel_dp_link_down(intel_dp); 1887 intel_dp_start_link_train(intel_dp); 1888 tries = 0; 1889 cr_tries++; 1890 continue; 1891 } 1892 1893 /* Compute new intel_dp->train_set as requested by target */ 1894 intel_get_adjust_train(intel_dp, link_status); 1895 ++tries; 1896 } 1897 1898 intel_dp_set_link_train(intel_dp, DP, DP_TRAINING_PATTERN_DISABLE); 1899} 1900 1901static void 1902intel_dp_link_down(struct intel_dp *intel_dp) 1903{ 1904 struct drm_device *dev = intel_dp->base.base.dev; 1905 struct drm_i915_private *dev_priv = dev->dev_private; 1906 uint32_t DP = intel_dp->DP; 1907 1908 if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0)) 1909 return; 1910 1911 DRM_DEBUG_KMS("\n"); 1912 1913 if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || !is_cpu_edp(intel_dp))) { 1914 DP &= ~DP_LINK_TRAIN_MASK_CPT; 1915 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT); 1916 } else { 1917 DP &= ~DP_LINK_TRAIN_MASK; 1918 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE); 1919 } 1920 POSTING_READ(intel_dp->output_reg); 1921 1922 msleep(17); 1923 1924 if (HAS_PCH_IBX(dev) && 1925 I915_READ(intel_dp->output_reg) & DP_PIPEB_SELECT) { 1926 struct drm_crtc *crtc = intel_dp->base.base.crtc; 1927 1928 /* Hardware workaround: leaving our transcoder select 1929 * set to transcoder B while it's off will prevent the 1930 * corresponding HDMI output on transcoder A. 1931 * 1932 * Combine this with another hardware workaround: 1933 * transcoder select bit can only be cleared while the 1934 * port is enabled. 1935 */ 1936 DP &= ~DP_PIPEB_SELECT; 1937 I915_WRITE(intel_dp->output_reg, DP); 1938 1939 /* Changes to enable or select take place the vblank 1940 * after being written. 1941 */ 1942 if (crtc == NULL) { 1943 /* We can arrive here never having been attached 1944 * to a CRTC, for instance, due to inheriting 1945 * random state from the BIOS. 1946 * 1947 * If the pipe is not running, play safe and 1948 * wait for the clocks to stabilise before 1949 * continuing. 1950 */ 1951 POSTING_READ(intel_dp->output_reg); 1952 msleep(50); 1953 } else 1954 intel_wait_for_vblank(dev, to_intel_crtc(crtc)->pipe); 1955 } 1956 1957 DP &= ~DP_AUDIO_OUTPUT_ENABLE; 1958 I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN); 1959 POSTING_READ(intel_dp->output_reg); 1960 msleep(intel_dp->panel_power_down_delay); 1961} 1962 1963static bool 1964intel_dp_get_dpcd(struct intel_dp *intel_dp) 1965{ 1966 if (intel_dp_aux_native_read_retry(intel_dp, 0x000, intel_dp->dpcd, 1967 sizeof(intel_dp->dpcd)) && 1968 (intel_dp->dpcd[DP_DPCD_REV] != 0)) { 1969 return true; 1970 } 1971 1972 return false; 1973} 1974 1975static void 1976intel_dp_probe_oui(struct intel_dp *intel_dp) 1977{ 1978 u8 buf[3]; 1979 1980 if (!(intel_dp->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT)) 1981 return; 1982 1983 ironlake_edp_panel_vdd_on(intel_dp); 1984 1985 if (intel_dp_aux_native_read_retry(intel_dp, DP_SINK_OUI, buf, 3)) 1986 DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n", 1987 buf[0], buf[1], buf[2]); 1988 1989 if (intel_dp_aux_native_read_retry(intel_dp, DP_BRANCH_OUI, buf, 3)) 1990 DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n", 1991 buf[0], buf[1], buf[2]); 1992 1993 ironlake_edp_panel_vdd_off(intel_dp, false); 1994} 1995 1996static bool 1997intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector) 1998{ 1999 int ret; 2000 2001 ret = intel_dp_aux_native_read_retry(intel_dp, 2002 DP_DEVICE_SERVICE_IRQ_VECTOR, 2003 sink_irq_vector, 1); 2004 if (!ret) 2005 return false; 2006 2007 return true; 2008} 2009 2010static void 2011intel_dp_handle_test_request(struct intel_dp *intel_dp) 2012{ 2013 /* NAK by default */ 2014 intel_dp_aux_native_write_1(intel_dp, DP_TEST_RESPONSE, DP_TEST_ACK); 2015} 2016 2017/* 2018 * According to DP spec 2019 * 5.1.2: 2020 * 1. Read DPCD 2021 * 2. Configure link according to Receiver Capabilities 2022 * 3. Use Link Training from 2.5.3.3 and 3.5.1.3 2023 * 4. Check link status on receipt of hot-plug interrupt 2024 */ 2025 2026static void 2027intel_dp_check_link_status(struct intel_dp *intel_dp) 2028{ 2029 u8 sink_irq_vector; 2030 u8 link_status[DP_LINK_STATUS_SIZE]; 2031 2032 if (!intel_dp->base.connectors_active) 2033 return; 2034 2035 if (WARN_ON(!intel_dp->base.base.crtc)) 2036 return; 2037 2038 /* Try to read receiver status if the link appears to be up */ 2039 if (!intel_dp_get_link_status(intel_dp, link_status)) { 2040 intel_dp_link_down(intel_dp); 2041 return; 2042 } 2043 2044 /* Now read the DPCD to see if it's actually running */ 2045 if (!intel_dp_get_dpcd(intel_dp)) { 2046 intel_dp_link_down(intel_dp); 2047 return; 2048 } 2049 2050 /* Try to read the source of the interrupt */ 2051 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 && 2052 intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) { 2053 /* Clear interrupt source */ 2054 intel_dp_aux_native_write_1(intel_dp, 2055 DP_DEVICE_SERVICE_IRQ_VECTOR, 2056 sink_irq_vector); 2057 2058 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST) 2059 intel_dp_handle_test_request(intel_dp); 2060 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ)) 2061 DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n"); 2062 } 2063 2064 if (!intel_channel_eq_ok(intel_dp, link_status)) { 2065 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n", 2066 drm_get_encoder_name(&intel_dp->base.base)); 2067 intel_dp_start_link_train(intel_dp); 2068 intel_dp_complete_link_train(intel_dp); 2069 } 2070} 2071 2072static enum drm_connector_status 2073intel_dp_detect_dpcd(struct intel_dp *intel_dp) 2074{ 2075 if (intel_dp_get_dpcd(intel_dp)) 2076 return connector_status_connected; 2077 return connector_status_disconnected; 2078} 2079 2080static enum drm_connector_status 2081ironlake_dp_detect(struct intel_dp *intel_dp) 2082{ 2083 enum drm_connector_status status; 2084 2085 /* Can't disconnect eDP, but you can close the lid... */ 2086 if (is_edp(intel_dp)) { 2087 status = intel_panel_detect(intel_dp->base.base.dev); 2088 if (status == connector_status_unknown) 2089 status = connector_status_connected; 2090 return status; 2091 } 2092 2093 return intel_dp_detect_dpcd(intel_dp); 2094} 2095 2096static enum drm_connector_status 2097g4x_dp_detect(struct intel_dp *intel_dp) 2098{ 2099 struct drm_device *dev = intel_dp->base.base.dev; 2100 struct drm_i915_private *dev_priv = dev->dev_private; 2101 uint32_t bit; 2102 2103 switch (intel_dp->output_reg) { 2104 case DP_B: 2105 bit = DPB_HOTPLUG_LIVE_STATUS; 2106 break; 2107 case DP_C: 2108 bit = DPC_HOTPLUG_LIVE_STATUS; 2109 break; 2110 case DP_D: 2111 bit = DPD_HOTPLUG_LIVE_STATUS; 2112 break; 2113 default: 2114 return connector_status_unknown; 2115 } 2116 2117 if ((I915_READ(PORT_HOTPLUG_STAT) & bit) == 0) 2118 return connector_status_disconnected; 2119 2120 return intel_dp_detect_dpcd(intel_dp); 2121} 2122 2123static struct edid * 2124intel_dp_get_edid(struct drm_connector *connector, struct i2c_adapter *adapter) 2125{ 2126 struct intel_dp *intel_dp = intel_attached_dp(connector); 2127 struct edid *edid; 2128 int size; 2129 2130 if (is_edp(intel_dp)) { 2131 if (!intel_dp->edid) 2132 return NULL; 2133 2134 size = (intel_dp->edid->extensions + 1) * EDID_LENGTH; 2135 edid = kmalloc(size, GFP_KERNEL); 2136 if (!edid) 2137 return NULL; 2138 2139 memcpy(edid, intel_dp->edid, size); 2140 return edid; 2141 } 2142 2143 edid = drm_get_edid(connector, adapter); 2144 return edid; 2145} 2146 2147static int 2148intel_dp_get_edid_modes(struct drm_connector *connector, struct i2c_adapter *adapter) 2149{ 2150 struct intel_dp *intel_dp = intel_attached_dp(connector); 2151 int ret; 2152 2153 if (is_edp(intel_dp)) { 2154 drm_mode_connector_update_edid_property(connector, 2155 intel_dp->edid); 2156 ret = drm_add_edid_modes(connector, intel_dp->edid); 2157 drm_edid_to_eld(connector, 2158 intel_dp->edid); 2159 return intel_dp->edid_mode_count; 2160 } 2161 2162 ret = intel_ddc_get_modes(connector, adapter); 2163 return ret; 2164} 2165 2166 2167/** 2168 * Uses CRT_HOTPLUG_EN and CRT_HOTPLUG_STAT to detect DP connection. 2169 * 2170 * \return true if DP port is connected. 2171 * \return false if DP port is disconnected. 2172 */ 2173static enum drm_connector_status 2174intel_dp_detect(struct drm_connector *connector, bool force) 2175{ 2176 struct intel_dp *intel_dp = intel_attached_dp(connector); 2177 struct drm_device *dev = intel_dp->base.base.dev; 2178 enum drm_connector_status status; 2179 struct edid *edid = NULL; 2180 2181 intel_dp->has_audio = false; 2182 2183 if (HAS_PCH_SPLIT(dev)) 2184 status = ironlake_dp_detect(intel_dp); 2185 else 2186 status = g4x_dp_detect(intel_dp); 2187 2188 DRM_DEBUG_KMS("DPCD: %02hx%02hx%02hx%02hx%02hx%02hx%02hx%02hx\n", 2189 intel_dp->dpcd[0], intel_dp->dpcd[1], intel_dp->dpcd[2], 2190 intel_dp->dpcd[3], intel_dp->dpcd[4], intel_dp->dpcd[5], 2191 intel_dp->dpcd[6], intel_dp->dpcd[7]); 2192 2193 if (status != connector_status_connected) 2194 return status; 2195 2196 intel_dp_probe_oui(intel_dp); 2197 2198 if (intel_dp->force_audio != HDMI_AUDIO_AUTO) { 2199 intel_dp->has_audio = (intel_dp->force_audio == HDMI_AUDIO_ON); 2200 } else { 2201 edid = intel_dp_get_edid(connector, &intel_dp->adapter); 2202 if (edid) { 2203 intel_dp->has_audio = drm_detect_monitor_audio(edid); 2204 kfree(edid); 2205 } 2206 } 2207 2208 return connector_status_connected; 2209} 2210 2211static int intel_dp_get_modes(struct drm_connector *connector) 2212{ 2213 struct intel_dp *intel_dp = intel_attached_dp(connector); 2214 struct drm_device *dev = intel_dp->base.base.dev; 2215 struct drm_i915_private *dev_priv = dev->dev_private; 2216 int ret; 2217 2218 /* We should parse the EDID data and find out if it has an audio sink 2219 */ 2220 2221 ret = intel_dp_get_edid_modes(connector, &intel_dp->adapter); 2222 if (ret) { 2223 if (is_edp(intel_dp) && !intel_dp->panel_fixed_mode) { 2224 struct drm_display_mode *newmode; 2225 list_for_each_entry(newmode, &connector->probed_modes, 2226 head) { 2227 if ((newmode->type & DRM_MODE_TYPE_PREFERRED)) { 2228 intel_dp->panel_fixed_mode = 2229 drm_mode_duplicate(dev, newmode); 2230 break; 2231 } 2232 } 2233 } 2234 return ret; 2235 } 2236 2237 /* if eDP has no EDID, try to use fixed panel mode from VBT */ 2238 if (is_edp(intel_dp)) { 2239 /* initialize panel mode from VBT if available for eDP */ 2240 if (intel_dp->panel_fixed_mode == NULL && dev_priv->lfp_lvds_vbt_mode != NULL) { 2241 intel_dp->panel_fixed_mode = 2242 drm_mode_duplicate(dev, dev_priv->lfp_lvds_vbt_mode); 2243 if (intel_dp->panel_fixed_mode) { 2244 intel_dp->panel_fixed_mode->type |= 2245 DRM_MODE_TYPE_PREFERRED; 2246 } 2247 } 2248 if (intel_dp->panel_fixed_mode) { 2249 struct drm_display_mode *mode; 2250 mode = drm_mode_duplicate(dev, intel_dp->panel_fixed_mode); 2251 drm_mode_probed_add(connector, mode); 2252 return 1; 2253 } 2254 } 2255 return 0; 2256} 2257 2258static bool 2259intel_dp_detect_audio(struct drm_connector *connector) 2260{ 2261 struct intel_dp *intel_dp = intel_attached_dp(connector); 2262 struct edid *edid; 2263 bool has_audio = false; 2264 2265 edid = intel_dp_get_edid(connector, &intel_dp->adapter); 2266 if (edid) { 2267 has_audio = drm_detect_monitor_audio(edid); 2268 kfree(edid); 2269 } 2270 2271 return has_audio; 2272} 2273 2274static int 2275intel_dp_set_property(struct drm_connector *connector, 2276 struct drm_property *property, 2277 uint64_t val) 2278{ 2279 struct drm_i915_private *dev_priv = connector->dev->dev_private; 2280 struct intel_dp *intel_dp = intel_attached_dp(connector); 2281 int ret; 2282 2283 ret = drm_connector_property_set_value(connector, property, val); 2284 if (ret) 2285 return ret; 2286 2287 if (property == dev_priv->force_audio_property) { 2288 int i = val; 2289 bool has_audio; 2290 2291 if (i == intel_dp->force_audio) 2292 return 0; 2293 2294 intel_dp->force_audio = i; 2295 2296 if (i == HDMI_AUDIO_AUTO) 2297 has_audio = intel_dp_detect_audio(connector); 2298 else 2299 has_audio = (i == HDMI_AUDIO_ON); 2300 2301 if (has_audio == intel_dp->has_audio) 2302 return 0; 2303 2304 intel_dp->has_audio = has_audio; 2305 goto done; 2306 } 2307 2308 if (property == dev_priv->broadcast_rgb_property) { 2309 if (val == !!intel_dp->color_range) 2310 return 0; 2311 2312 intel_dp->color_range = val ? DP_COLOR_RANGE_16_235 : 0; 2313 goto done; 2314 } 2315 2316 return -EINVAL; 2317 2318done: 2319 if (intel_dp->base.base.crtc) { 2320 struct drm_crtc *crtc = intel_dp->base.base.crtc; 2321 intel_set_mode(crtc, &crtc->mode, 2322 crtc->x, crtc->y, crtc->fb); 2323 } 2324 2325 return 0; 2326} 2327 2328static void 2329intel_dp_destroy(struct drm_connector *connector) 2330{ 2331 struct drm_device *dev = connector->dev; 2332 2333 if (intel_dpd_is_edp(dev)) 2334 intel_panel_destroy_backlight(dev); 2335 2336 drm_sysfs_connector_remove(connector); 2337 drm_connector_cleanup(connector); 2338 kfree(connector); 2339} 2340 2341static void intel_dp_encoder_destroy(struct drm_encoder *encoder) 2342{ 2343 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 2344 2345 i2c_del_adapter(&intel_dp->adapter); 2346 drm_encoder_cleanup(encoder); 2347 if (is_edp(intel_dp)) { 2348 kfree(intel_dp->edid); 2349 cancel_delayed_work_sync(&intel_dp->panel_vdd_work); 2350 ironlake_panel_vdd_off_sync(intel_dp); 2351 } 2352 kfree(intel_dp); 2353} 2354 2355static const struct drm_encoder_helper_funcs intel_dp_helper_funcs = { 2356 .mode_fixup = intel_dp_mode_fixup, 2357 .mode_set = intel_dp_mode_set, 2358 .disable = intel_encoder_noop, 2359}; 2360 2361static const struct drm_connector_funcs intel_dp_connector_funcs = { 2362 .dpms = intel_connector_dpms, 2363 .detect = intel_dp_detect, 2364 .fill_modes = drm_helper_probe_single_connector_modes, 2365 .set_property = intel_dp_set_property, 2366 .destroy = intel_dp_destroy, 2367}; 2368 2369static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = { 2370 .get_modes = intel_dp_get_modes, 2371 .mode_valid = intel_dp_mode_valid, 2372 .best_encoder = intel_best_encoder, 2373}; 2374 2375static const struct drm_encoder_funcs intel_dp_enc_funcs = { 2376 .destroy = intel_dp_encoder_destroy, 2377}; 2378 2379static void 2380intel_dp_hot_plug(struct intel_encoder *intel_encoder) 2381{ 2382 struct intel_dp *intel_dp = container_of(intel_encoder, struct intel_dp, base); 2383 2384 intel_dp_check_link_status(intel_dp); 2385} 2386 2387/* Return which DP Port should be selected for Transcoder DP control */ 2388int 2389intel_trans_dp_port_sel(struct drm_crtc *crtc) 2390{ 2391 struct drm_device *dev = crtc->dev; 2392 struct intel_encoder *encoder; 2393 2394 for_each_encoder_on_crtc(dev, crtc, encoder) { 2395 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); 2396 2397 if (intel_dp->base.type == INTEL_OUTPUT_DISPLAYPORT || 2398 intel_dp->base.type == INTEL_OUTPUT_EDP) 2399 return intel_dp->output_reg; 2400 } 2401 2402 return -1; 2403} 2404 2405/* check the VBT to see whether the eDP is on DP-D port */ 2406bool intel_dpd_is_edp(struct drm_device *dev) 2407{ 2408 struct drm_i915_private *dev_priv = dev->dev_private; 2409 struct child_device_config *p_child; 2410 int i; 2411 2412 if (!dev_priv->child_dev_num) 2413 return false; 2414 2415 for (i = 0; i < dev_priv->child_dev_num; i++) { 2416 p_child = dev_priv->child_dev + i; 2417 2418 if (p_child->dvo_port == PORT_IDPD && 2419 p_child->device_type == DEVICE_TYPE_eDP) 2420 return true; 2421 } 2422 return false; 2423} 2424 2425static void 2426intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector) 2427{ 2428 intel_attach_force_audio_property(connector); 2429 intel_attach_broadcast_rgb_property(connector); 2430} 2431 2432void 2433intel_dp_init(struct drm_device *dev, int output_reg, enum port port) 2434{ 2435 struct drm_i915_private *dev_priv = dev->dev_private; 2436 struct drm_connector *connector; 2437 struct intel_dp *intel_dp; 2438 struct intel_encoder *intel_encoder; 2439 struct intel_connector *intel_connector; 2440 const char *name = NULL; 2441 int type; 2442 2443 intel_dp = kzalloc(sizeof(struct intel_dp), GFP_KERNEL); 2444 if (!intel_dp) 2445 return; 2446 2447 intel_dp->output_reg = output_reg; 2448 intel_dp->port = port; 2449 /* Preserve the current hw state. */ 2450 intel_dp->DP = I915_READ(intel_dp->output_reg); 2451 2452 intel_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL); 2453 if (!intel_connector) { 2454 kfree(intel_dp); 2455 return; 2456 } 2457 intel_encoder = &intel_dp->base; 2458 2459 if (HAS_PCH_SPLIT(dev) && output_reg == PCH_DP_D) 2460 if (intel_dpd_is_edp(dev)) 2461 intel_dp->is_pch_edp = true; 2462 2463 if (output_reg == DP_A || is_pch_edp(intel_dp)) { 2464 type = DRM_MODE_CONNECTOR_eDP; 2465 intel_encoder->type = INTEL_OUTPUT_EDP; 2466 } else { 2467 type = DRM_MODE_CONNECTOR_DisplayPort; 2468 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT; 2469 } 2470 2471 connector = &intel_connector->base; 2472 drm_connector_init(dev, connector, &intel_dp_connector_funcs, type); 2473 drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs); 2474 2475 connector->polled = DRM_CONNECTOR_POLL_HPD; 2476 2477 intel_encoder->cloneable = false; 2478 2479 INIT_DELAYED_WORK(&intel_dp->panel_vdd_work, 2480 ironlake_panel_vdd_work); 2481 2482 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2); 2483 2484 connector->interlace_allowed = true; 2485 connector->doublescan_allowed = 0; 2486 2487 drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs, 2488 DRM_MODE_ENCODER_TMDS); 2489 drm_encoder_helper_add(&intel_encoder->base, &intel_dp_helper_funcs); 2490 2491 intel_connector_attach_encoder(intel_connector, intel_encoder); 2492 drm_sysfs_connector_add(connector); 2493 2494 intel_encoder->enable = intel_enable_dp; 2495 intel_encoder->pre_enable = intel_pre_enable_dp; 2496 intel_encoder->disable = intel_disable_dp; 2497 intel_encoder->post_disable = intel_post_disable_dp; 2498 intel_encoder->get_hw_state = intel_dp_get_hw_state; 2499 intel_connector->get_hw_state = intel_connector_get_hw_state; 2500 2501 /* Set up the DDC bus. */ 2502 switch (port) { 2503 case PORT_A: 2504 name = "DPDDC-A"; 2505 break; 2506 case PORT_B: 2507 dev_priv->hotplug_supported_mask |= DPB_HOTPLUG_INT_STATUS; 2508 name = "DPDDC-B"; 2509 break; 2510 case PORT_C: 2511 dev_priv->hotplug_supported_mask |= DPC_HOTPLUG_INT_STATUS; 2512 name = "DPDDC-C"; 2513 break; 2514 case PORT_D: 2515 dev_priv->hotplug_supported_mask |= DPD_HOTPLUG_INT_STATUS; 2516 name = "DPDDC-D"; 2517 break; 2518 default: 2519 WARN(1, "Invalid port %c\n", port_name(port)); 2520 break; 2521 } 2522 2523 intel_dp_i2c_init(intel_dp, intel_connector, name); 2524 2525 /* Cache some DPCD data in the eDP case */ 2526 if (is_edp(intel_dp)) { 2527 bool ret; 2528 struct edp_power_seq cur, vbt; 2529 u32 pp_on, pp_off, pp_div; 2530 struct edid *edid; 2531 2532 pp_on = I915_READ(PCH_PP_ON_DELAYS); 2533 pp_off = I915_READ(PCH_PP_OFF_DELAYS); 2534 pp_div = I915_READ(PCH_PP_DIVISOR); 2535 2536 if (!pp_on || !pp_off || !pp_div) { 2537 DRM_INFO("bad panel power sequencing delays, disabling panel\n"); 2538 intel_dp_encoder_destroy(&intel_dp->base.base); 2539 intel_dp_destroy(&intel_connector->base); 2540 return; 2541 } 2542 2543 /* Pull timing values out of registers */ 2544 cur.t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >> 2545 PANEL_POWER_UP_DELAY_SHIFT; 2546 2547 cur.t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >> 2548 PANEL_LIGHT_ON_DELAY_SHIFT; 2549 2550 cur.t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >> 2551 PANEL_LIGHT_OFF_DELAY_SHIFT; 2552 2553 cur.t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >> 2554 PANEL_POWER_DOWN_DELAY_SHIFT; 2555 2556 cur.t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >> 2557 PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000; 2558 2559 DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n", 2560 cur.t1_t3, cur.t8, cur.t9, cur.t10, cur.t11_t12); 2561 2562 vbt = dev_priv->edp.pps; 2563 2564 DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n", 2565 vbt.t1_t3, vbt.t8, vbt.t9, vbt.t10, vbt.t11_t12); 2566 2567#define get_delay(field) ((max(cur.field, vbt.field) + 9) / 10) 2568 2569 intel_dp->panel_power_up_delay = get_delay(t1_t3); 2570 intel_dp->backlight_on_delay = get_delay(t8); 2571 intel_dp->backlight_off_delay = get_delay(t9); 2572 intel_dp->panel_power_down_delay = get_delay(t10); 2573 intel_dp->panel_power_cycle_delay = get_delay(t11_t12); 2574 2575 DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n", 2576 intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay, 2577 intel_dp->panel_power_cycle_delay); 2578 2579 DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n", 2580 intel_dp->backlight_on_delay, intel_dp->backlight_off_delay); 2581 2582 ironlake_edp_panel_vdd_on(intel_dp); 2583 ret = intel_dp_get_dpcd(intel_dp); 2584 ironlake_edp_panel_vdd_off(intel_dp, false); 2585 2586 if (ret) { 2587 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) 2588 dev_priv->no_aux_handshake = 2589 intel_dp->dpcd[DP_MAX_DOWNSPREAD] & 2590 DP_NO_AUX_HANDSHAKE_LINK_TRAINING; 2591 } else { 2592 /* if this fails, presume the device is a ghost */ 2593 DRM_INFO("failed to retrieve link info, disabling eDP\n"); 2594 intel_dp_encoder_destroy(&intel_dp->base.base); 2595 intel_dp_destroy(&intel_connector->base); 2596 return; 2597 } 2598 2599 ironlake_edp_panel_vdd_on(intel_dp); 2600 edid = drm_get_edid(connector, &intel_dp->adapter); 2601 if (edid) { 2602 drm_mode_connector_update_edid_property(connector, 2603 edid); 2604 intel_dp->edid_mode_count = 2605 drm_add_edid_modes(connector, edid); 2606 drm_edid_to_eld(connector, edid); 2607 intel_dp->edid = edid; 2608 } 2609 ironlake_edp_panel_vdd_off(intel_dp, false); 2610 } 2611 2612 intel_encoder->hot_plug = intel_dp_hot_plug; 2613 2614 if (is_edp(intel_dp)) { 2615 dev_priv->int_edp_connector = connector; 2616 intel_panel_setup_backlight(dev); 2617 } 2618 2619 intel_dp_add_properties(intel_dp, connector); 2620 2621 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written 2622 * 0xd. Failure to do so will result in spurious interrupts being 2623 * generated on the port when a cable is not attached. 2624 */ 2625 if (IS_G4X(dev) && !IS_GM45(dev)) { 2626 u32 temp = I915_READ(PEG_BAND_GAP_DATA); 2627 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd); 2628 } 2629} 2630