intel_dp.c revision d410b56d74bc706f414158cb0149e2a149ee1650
1/* 2 * Copyright © 2008 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 * Authors: 24 * Keith Packard <keithp@keithp.com> 25 * 26 */ 27 28#include <linux/i2c.h> 29#include <linux/slab.h> 30#include <linux/export.h> 31#include <linux/notifier.h> 32#include <linux/reboot.h> 33#include <drm/drmP.h> 34#include <drm/drm_crtc.h> 35#include <drm/drm_crtc_helper.h> 36#include <drm/drm_edid.h> 37#include "intel_drv.h" 38#include <drm/i915_drm.h> 39#include "i915_drv.h" 40 41#define DP_LINK_CHECK_TIMEOUT (10 * 1000) 42 43struct dp_link_dpll { 44 int link_bw; 45 struct dpll dpll; 46}; 47 48static const struct dp_link_dpll gen4_dpll[] = { 49 { DP_LINK_BW_1_62, 50 { .p1 = 2, .p2 = 10, .n = 2, .m1 = 23, .m2 = 8 } }, 51 { DP_LINK_BW_2_7, 52 { .p1 = 1, .p2 = 10, .n = 1, .m1 = 14, .m2 = 2 } } 53}; 54 55static const struct dp_link_dpll pch_dpll[] = { 56 { DP_LINK_BW_1_62, 57 { .p1 = 2, .p2 = 10, .n = 1, .m1 = 12, .m2 = 9 } }, 58 { DP_LINK_BW_2_7, 59 { .p1 = 1, .p2 = 10, .n = 2, .m1 = 14, .m2 = 8 } } 60}; 61 62static const struct dp_link_dpll vlv_dpll[] = { 63 { DP_LINK_BW_1_62, 64 { .p1 = 3, .p2 = 2, .n = 5, .m1 = 3, .m2 = 81 } }, 65 { DP_LINK_BW_2_7, 66 { .p1 = 2, .p2 = 2, .n = 1, .m1 = 2, .m2 = 27 } } 67}; 68 69/* 70 * CHV supports eDP 1.4 that have more link rates. 71 * Below only provides the fixed rate but exclude variable rate. 72 */ 73static const struct dp_link_dpll chv_dpll[] = { 74 /* 75 * CHV requires to program fractional division for m2. 76 * m2 is stored in fixed point format using formula below 77 * (m2_int << 22) | m2_fraction 78 */ 79 { DP_LINK_BW_1_62, /* m2_int = 32, m2_fraction = 1677722 */ 80 { .p1 = 4, .p2 = 2, .n = 1, .m1 = 2, .m2 = 0x819999a } }, 81 { DP_LINK_BW_2_7, /* m2_int = 27, m2_fraction = 0 */ 82 { .p1 = 4, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } }, 83 { DP_LINK_BW_5_4, /* m2_int = 27, m2_fraction = 0 */ 84 { .p1 = 2, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } } 85}; 86 87/** 88 * is_edp - is the given port attached to an eDP panel (either CPU or PCH) 89 * @intel_dp: DP struct 90 * 91 * If a CPU or PCH DP output is attached to an eDP panel, this function 92 * will return true, and false otherwise. 93 */ 94static bool is_edp(struct intel_dp *intel_dp) 95{ 96 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 97 98 return intel_dig_port->base.type == INTEL_OUTPUT_EDP; 99} 100 101static struct drm_device *intel_dp_to_dev(struct intel_dp *intel_dp) 102{ 103 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 104 105 return intel_dig_port->base.base.dev; 106} 107 108static struct intel_dp *intel_attached_dp(struct drm_connector *connector) 109{ 110 return enc_to_intel_dp(&intel_attached_encoder(connector)->base); 111} 112 113static void intel_dp_link_down(struct intel_dp *intel_dp); 114static bool edp_panel_vdd_on(struct intel_dp *intel_dp); 115static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync); 116 117int 118intel_dp_max_link_bw(struct intel_dp *intel_dp) 119{ 120 int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE]; 121 struct drm_device *dev = intel_dp->attached_connector->base.dev; 122 123 switch (max_link_bw) { 124 case DP_LINK_BW_1_62: 125 case DP_LINK_BW_2_7: 126 break; 127 case DP_LINK_BW_5_4: /* 1.2 capable displays may advertise higher bw */ 128 if (((IS_HASWELL(dev) && !IS_HSW_ULX(dev)) || 129 INTEL_INFO(dev)->gen >= 8) && 130 intel_dp->dpcd[DP_DPCD_REV] >= 0x12) 131 max_link_bw = DP_LINK_BW_5_4; 132 else 133 max_link_bw = DP_LINK_BW_2_7; 134 break; 135 default: 136 WARN(1, "invalid max DP link bw val %x, using 1.62Gbps\n", 137 max_link_bw); 138 max_link_bw = DP_LINK_BW_1_62; 139 break; 140 } 141 return max_link_bw; 142} 143 144static u8 intel_dp_max_lane_count(struct intel_dp *intel_dp) 145{ 146 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 147 struct drm_device *dev = intel_dig_port->base.base.dev; 148 u8 source_max, sink_max; 149 150 source_max = 4; 151 if (HAS_DDI(dev) && intel_dig_port->port == PORT_A && 152 (intel_dig_port->saved_port_bits & DDI_A_4_LANES) == 0) 153 source_max = 2; 154 155 sink_max = drm_dp_max_lane_count(intel_dp->dpcd); 156 157 return min(source_max, sink_max); 158} 159 160/* 161 * The units on the numbers in the next two are... bizarre. Examples will 162 * make it clearer; this one parallels an example in the eDP spec. 163 * 164 * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as: 165 * 166 * 270000 * 1 * 8 / 10 == 216000 167 * 168 * The actual data capacity of that configuration is 2.16Gbit/s, so the 169 * units are decakilobits. ->clock in a drm_display_mode is in kilohertz - 170 * or equivalently, kilopixels per second - so for 1680x1050R it'd be 171 * 119000. At 18bpp that's 2142000 kilobits per second. 172 * 173 * Thus the strange-looking division by 10 in intel_dp_link_required, to 174 * get the result in decakilobits instead of kilobits. 175 */ 176 177static int 178intel_dp_link_required(int pixel_clock, int bpp) 179{ 180 return (pixel_clock * bpp + 9) / 10; 181} 182 183static int 184intel_dp_max_data_rate(int max_link_clock, int max_lanes) 185{ 186 return (max_link_clock * max_lanes * 8) / 10; 187} 188 189static enum drm_mode_status 190intel_dp_mode_valid(struct drm_connector *connector, 191 struct drm_display_mode *mode) 192{ 193 struct intel_dp *intel_dp = intel_attached_dp(connector); 194 struct intel_connector *intel_connector = to_intel_connector(connector); 195 struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode; 196 int target_clock = mode->clock; 197 int max_rate, mode_rate, max_lanes, max_link_clock; 198 199 if (is_edp(intel_dp) && fixed_mode) { 200 if (mode->hdisplay > fixed_mode->hdisplay) 201 return MODE_PANEL; 202 203 if (mode->vdisplay > fixed_mode->vdisplay) 204 return MODE_PANEL; 205 206 target_clock = fixed_mode->clock; 207 } 208 209 max_link_clock = drm_dp_bw_code_to_link_rate(intel_dp_max_link_bw(intel_dp)); 210 max_lanes = intel_dp_max_lane_count(intel_dp); 211 212 max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes); 213 mode_rate = intel_dp_link_required(target_clock, 18); 214 215 if (mode_rate > max_rate) 216 return MODE_CLOCK_HIGH; 217 218 if (mode->clock < 10000) 219 return MODE_CLOCK_LOW; 220 221 if (mode->flags & DRM_MODE_FLAG_DBLCLK) 222 return MODE_H_ILLEGAL; 223 224 return MODE_OK; 225} 226 227static uint32_t 228pack_aux(uint8_t *src, int src_bytes) 229{ 230 int i; 231 uint32_t v = 0; 232 233 if (src_bytes > 4) 234 src_bytes = 4; 235 for (i = 0; i < src_bytes; i++) 236 v |= ((uint32_t) src[i]) << ((3-i) * 8); 237 return v; 238} 239 240static void 241unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes) 242{ 243 int i; 244 if (dst_bytes > 4) 245 dst_bytes = 4; 246 for (i = 0; i < dst_bytes; i++) 247 dst[i] = src >> ((3-i) * 8); 248} 249 250/* hrawclock is 1/4 the FSB frequency */ 251static int 252intel_hrawclk(struct drm_device *dev) 253{ 254 struct drm_i915_private *dev_priv = dev->dev_private; 255 uint32_t clkcfg; 256 257 /* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */ 258 if (IS_VALLEYVIEW(dev)) 259 return 200; 260 261 clkcfg = I915_READ(CLKCFG); 262 switch (clkcfg & CLKCFG_FSB_MASK) { 263 case CLKCFG_FSB_400: 264 return 100; 265 case CLKCFG_FSB_533: 266 return 133; 267 case CLKCFG_FSB_667: 268 return 166; 269 case CLKCFG_FSB_800: 270 return 200; 271 case CLKCFG_FSB_1067: 272 return 266; 273 case CLKCFG_FSB_1333: 274 return 333; 275 /* these two are just a guess; one of them might be right */ 276 case CLKCFG_FSB_1600: 277 case CLKCFG_FSB_1600_ALT: 278 return 400; 279 default: 280 return 133; 281 } 282} 283 284static void 285intel_dp_init_panel_power_sequencer(struct drm_device *dev, 286 struct intel_dp *intel_dp, 287 struct edp_power_seq *out); 288static void 289intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev, 290 struct intel_dp *intel_dp, 291 struct edp_power_seq *out); 292 293static enum pipe 294vlv_power_sequencer_pipe(struct intel_dp *intel_dp) 295{ 296 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 297 struct drm_crtc *crtc = intel_dig_port->base.base.crtc; 298 struct drm_device *dev = intel_dig_port->base.base.dev; 299 struct drm_i915_private *dev_priv = dev->dev_private; 300 enum port port = intel_dig_port->port; 301 enum pipe pipe; 302 303 /* modeset should have pipe */ 304 if (crtc) 305 return to_intel_crtc(crtc)->pipe; 306 307 /* init time, try to find a pipe with this port selected */ 308 for (pipe = PIPE_A; pipe <= PIPE_B; pipe++) { 309 u32 port_sel = I915_READ(VLV_PIPE_PP_ON_DELAYS(pipe)) & 310 PANEL_PORT_SELECT_MASK; 311 if (port_sel == PANEL_PORT_SELECT_VLV(port)) 312 return pipe; 313 } 314 315 /* shrug */ 316 return PIPE_A; 317} 318 319static u32 _pp_ctrl_reg(struct intel_dp *intel_dp) 320{ 321 struct drm_device *dev = intel_dp_to_dev(intel_dp); 322 323 if (HAS_PCH_SPLIT(dev)) 324 return PCH_PP_CONTROL; 325 else 326 return VLV_PIPE_PP_CONTROL(vlv_power_sequencer_pipe(intel_dp)); 327} 328 329static u32 _pp_stat_reg(struct intel_dp *intel_dp) 330{ 331 struct drm_device *dev = intel_dp_to_dev(intel_dp); 332 333 if (HAS_PCH_SPLIT(dev)) 334 return PCH_PP_STATUS; 335 else 336 return VLV_PIPE_PP_STATUS(vlv_power_sequencer_pipe(intel_dp)); 337} 338 339/* Reboot notifier handler to shutdown panel power to guarantee T12 timing 340 This function only applicable when panel PM state is not to be tracked */ 341static int edp_notify_handler(struct notifier_block *this, unsigned long code, 342 void *unused) 343{ 344 struct intel_dp *intel_dp = container_of(this, typeof(* intel_dp), 345 edp_notifier); 346 struct drm_device *dev = intel_dp_to_dev(intel_dp); 347 struct drm_i915_private *dev_priv = dev->dev_private; 348 u32 pp_div; 349 u32 pp_ctrl_reg, pp_div_reg; 350 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp); 351 352 if (!is_edp(intel_dp) || code != SYS_RESTART) 353 return 0; 354 355 if (IS_VALLEYVIEW(dev)) { 356 pp_ctrl_reg = VLV_PIPE_PP_CONTROL(pipe); 357 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe); 358 pp_div = I915_READ(pp_div_reg); 359 pp_div &= PP_REFERENCE_DIVIDER_MASK; 360 361 /* 0x1F write to PP_DIV_REG sets max cycle delay */ 362 I915_WRITE(pp_div_reg, pp_div | 0x1F); 363 I915_WRITE(pp_ctrl_reg, PANEL_UNLOCK_REGS | PANEL_POWER_OFF); 364 msleep(intel_dp->panel_power_cycle_delay); 365 } 366 367 return 0; 368} 369 370static bool edp_have_panel_power(struct intel_dp *intel_dp) 371{ 372 struct drm_device *dev = intel_dp_to_dev(intel_dp); 373 struct drm_i915_private *dev_priv = dev->dev_private; 374 375 return (I915_READ(_pp_stat_reg(intel_dp)) & PP_ON) != 0; 376} 377 378static bool edp_have_panel_vdd(struct intel_dp *intel_dp) 379{ 380 struct drm_device *dev = intel_dp_to_dev(intel_dp); 381 struct drm_i915_private *dev_priv = dev->dev_private; 382 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 383 struct intel_encoder *intel_encoder = &intel_dig_port->base; 384 enum intel_display_power_domain power_domain; 385 386 power_domain = intel_display_port_power_domain(intel_encoder); 387 return intel_display_power_enabled(dev_priv, power_domain) && 388 (I915_READ(_pp_ctrl_reg(intel_dp)) & EDP_FORCE_VDD) != 0; 389} 390 391static void 392intel_dp_check_edp(struct intel_dp *intel_dp) 393{ 394 struct drm_device *dev = intel_dp_to_dev(intel_dp); 395 struct drm_i915_private *dev_priv = dev->dev_private; 396 397 if (!is_edp(intel_dp)) 398 return; 399 400 if (!edp_have_panel_power(intel_dp) && !edp_have_panel_vdd(intel_dp)) { 401 WARN(1, "eDP powered off while attempting aux channel communication.\n"); 402 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n", 403 I915_READ(_pp_stat_reg(intel_dp)), 404 I915_READ(_pp_ctrl_reg(intel_dp))); 405 } 406} 407 408static uint32_t 409intel_dp_aux_wait_done(struct intel_dp *intel_dp, bool has_aux_irq) 410{ 411 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 412 struct drm_device *dev = intel_dig_port->base.base.dev; 413 struct drm_i915_private *dev_priv = dev->dev_private; 414 uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg; 415 uint32_t status; 416 bool done; 417 418#define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0) 419 if (has_aux_irq) 420 done = wait_event_timeout(dev_priv->gmbus_wait_queue, C, 421 msecs_to_jiffies_timeout(10)); 422 else 423 done = wait_for_atomic(C, 10) == 0; 424 if (!done) 425 DRM_ERROR("dp aux hw did not signal timeout (has irq: %i)!\n", 426 has_aux_irq); 427#undef C 428 429 return status; 430} 431 432static uint32_t i9xx_get_aux_clock_divider(struct intel_dp *intel_dp, int index) 433{ 434 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 435 struct drm_device *dev = intel_dig_port->base.base.dev; 436 437 /* 438 * The clock divider is based off the hrawclk, and would like to run at 439 * 2MHz. So, take the hrawclk value and divide by 2 and use that 440 */ 441 return index ? 0 : intel_hrawclk(dev) / 2; 442} 443 444static uint32_t ilk_get_aux_clock_divider(struct intel_dp *intel_dp, int index) 445{ 446 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 447 struct drm_device *dev = intel_dig_port->base.base.dev; 448 449 if (index) 450 return 0; 451 452 if (intel_dig_port->port == PORT_A) { 453 if (IS_GEN6(dev) || IS_GEN7(dev)) 454 return 200; /* SNB & IVB eDP input clock at 400Mhz */ 455 else 456 return 225; /* eDP input clock at 450Mhz */ 457 } else { 458 return DIV_ROUND_UP(intel_pch_rawclk(dev), 2); 459 } 460} 461 462static uint32_t hsw_get_aux_clock_divider(struct intel_dp *intel_dp, int index) 463{ 464 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 465 struct drm_device *dev = intel_dig_port->base.base.dev; 466 struct drm_i915_private *dev_priv = dev->dev_private; 467 468 if (intel_dig_port->port == PORT_A) { 469 if (index) 470 return 0; 471 return DIV_ROUND_CLOSEST(intel_ddi_get_cdclk_freq(dev_priv), 2000); 472 } else if (dev_priv->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE) { 473 /* Workaround for non-ULT HSW */ 474 switch (index) { 475 case 0: return 63; 476 case 1: return 72; 477 default: return 0; 478 } 479 } else { 480 return index ? 0 : DIV_ROUND_UP(intel_pch_rawclk(dev), 2); 481 } 482} 483 484static uint32_t vlv_get_aux_clock_divider(struct intel_dp *intel_dp, int index) 485{ 486 return index ? 0 : 100; 487} 488 489static uint32_t i9xx_get_aux_send_ctl(struct intel_dp *intel_dp, 490 bool has_aux_irq, 491 int send_bytes, 492 uint32_t aux_clock_divider) 493{ 494 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 495 struct drm_device *dev = intel_dig_port->base.base.dev; 496 uint32_t precharge, timeout; 497 498 if (IS_GEN6(dev)) 499 precharge = 3; 500 else 501 precharge = 5; 502 503 if (IS_BROADWELL(dev) && intel_dp->aux_ch_ctl_reg == DPA_AUX_CH_CTL) 504 timeout = DP_AUX_CH_CTL_TIME_OUT_600us; 505 else 506 timeout = DP_AUX_CH_CTL_TIME_OUT_400us; 507 508 return DP_AUX_CH_CTL_SEND_BUSY | 509 DP_AUX_CH_CTL_DONE | 510 (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) | 511 DP_AUX_CH_CTL_TIME_OUT_ERROR | 512 timeout | 513 DP_AUX_CH_CTL_RECEIVE_ERROR | 514 (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) | 515 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) | 516 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT); 517} 518 519static int 520intel_dp_aux_ch(struct intel_dp *intel_dp, 521 uint8_t *send, int send_bytes, 522 uint8_t *recv, int recv_size) 523{ 524 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 525 struct drm_device *dev = intel_dig_port->base.base.dev; 526 struct drm_i915_private *dev_priv = dev->dev_private; 527 uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg; 528 uint32_t ch_data = ch_ctl + 4; 529 uint32_t aux_clock_divider; 530 int i, ret, recv_bytes; 531 uint32_t status; 532 int try, clock = 0; 533 bool has_aux_irq = HAS_AUX_IRQ(dev); 534 bool vdd; 535 536 /* 537 * We will be called with VDD already enabled for dpcd/edid/oui reads. 538 * In such cases we want to leave VDD enabled and it's up to upper layers 539 * to turn it off. But for eg. i2c-dev access we need to turn it on/off 540 * ourselves. 541 */ 542 vdd = edp_panel_vdd_on(intel_dp); 543 544 /* dp aux is extremely sensitive to irq latency, hence request the 545 * lowest possible wakeup latency and so prevent the cpu from going into 546 * deep sleep states. 547 */ 548 pm_qos_update_request(&dev_priv->pm_qos, 0); 549 550 intel_dp_check_edp(intel_dp); 551 552 intel_aux_display_runtime_get(dev_priv); 553 554 /* Try to wait for any previous AUX channel activity */ 555 for (try = 0; try < 3; try++) { 556 status = I915_READ_NOTRACE(ch_ctl); 557 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0) 558 break; 559 msleep(1); 560 } 561 562 if (try == 3) { 563 WARN(1, "dp_aux_ch not started status 0x%08x\n", 564 I915_READ(ch_ctl)); 565 ret = -EBUSY; 566 goto out; 567 } 568 569 /* Only 5 data registers! */ 570 if (WARN_ON(send_bytes > 20 || recv_size > 20)) { 571 ret = -E2BIG; 572 goto out; 573 } 574 575 while ((aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, clock++))) { 576 u32 send_ctl = intel_dp->get_aux_send_ctl(intel_dp, 577 has_aux_irq, 578 send_bytes, 579 aux_clock_divider); 580 581 /* Must try at least 3 times according to DP spec */ 582 for (try = 0; try < 5; try++) { 583 /* Load the send data into the aux channel data registers */ 584 for (i = 0; i < send_bytes; i += 4) 585 I915_WRITE(ch_data + i, 586 pack_aux(send + i, send_bytes - i)); 587 588 /* Send the command and wait for it to complete */ 589 I915_WRITE(ch_ctl, send_ctl); 590 591 status = intel_dp_aux_wait_done(intel_dp, has_aux_irq); 592 593 /* Clear done status and any errors */ 594 I915_WRITE(ch_ctl, 595 status | 596 DP_AUX_CH_CTL_DONE | 597 DP_AUX_CH_CTL_TIME_OUT_ERROR | 598 DP_AUX_CH_CTL_RECEIVE_ERROR); 599 600 if (status & (DP_AUX_CH_CTL_TIME_OUT_ERROR | 601 DP_AUX_CH_CTL_RECEIVE_ERROR)) 602 continue; 603 if (status & DP_AUX_CH_CTL_DONE) 604 break; 605 } 606 if (status & DP_AUX_CH_CTL_DONE) 607 break; 608 } 609 610 if ((status & DP_AUX_CH_CTL_DONE) == 0) { 611 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status); 612 ret = -EBUSY; 613 goto out; 614 } 615 616 /* Check for timeout or receive error. 617 * Timeouts occur when the sink is not connected 618 */ 619 if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) { 620 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status); 621 ret = -EIO; 622 goto out; 623 } 624 625 /* Timeouts occur when the device isn't connected, so they're 626 * "normal" -- don't fill the kernel log with these */ 627 if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) { 628 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status); 629 ret = -ETIMEDOUT; 630 goto out; 631 } 632 633 /* Unload any bytes sent back from the other side */ 634 recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >> 635 DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT); 636 if (recv_bytes > recv_size) 637 recv_bytes = recv_size; 638 639 for (i = 0; i < recv_bytes; i += 4) 640 unpack_aux(I915_READ(ch_data + i), 641 recv + i, recv_bytes - i); 642 643 ret = recv_bytes; 644out: 645 pm_qos_update_request(&dev_priv->pm_qos, PM_QOS_DEFAULT_VALUE); 646 intel_aux_display_runtime_put(dev_priv); 647 648 if (vdd) 649 edp_panel_vdd_off(intel_dp, false); 650 651 return ret; 652} 653 654#define BARE_ADDRESS_SIZE 3 655#define HEADER_SIZE (BARE_ADDRESS_SIZE + 1) 656static ssize_t 657intel_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg) 658{ 659 struct intel_dp *intel_dp = container_of(aux, struct intel_dp, aux); 660 uint8_t txbuf[20], rxbuf[20]; 661 size_t txsize, rxsize; 662 int ret; 663 664 txbuf[0] = msg->request << 4; 665 txbuf[1] = msg->address >> 8; 666 txbuf[2] = msg->address & 0xff; 667 txbuf[3] = msg->size - 1; 668 669 switch (msg->request & ~DP_AUX_I2C_MOT) { 670 case DP_AUX_NATIVE_WRITE: 671 case DP_AUX_I2C_WRITE: 672 txsize = msg->size ? HEADER_SIZE + msg->size : BARE_ADDRESS_SIZE; 673 rxsize = 1; 674 675 if (WARN_ON(txsize > 20)) 676 return -E2BIG; 677 678 memcpy(txbuf + HEADER_SIZE, msg->buffer, msg->size); 679 680 ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize); 681 if (ret > 0) { 682 msg->reply = rxbuf[0] >> 4; 683 684 /* Return payload size. */ 685 ret = msg->size; 686 } 687 break; 688 689 case DP_AUX_NATIVE_READ: 690 case DP_AUX_I2C_READ: 691 txsize = msg->size ? HEADER_SIZE : BARE_ADDRESS_SIZE; 692 rxsize = msg->size + 1; 693 694 if (WARN_ON(rxsize > 20)) 695 return -E2BIG; 696 697 ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize); 698 if (ret > 0) { 699 msg->reply = rxbuf[0] >> 4; 700 /* 701 * Assume happy day, and copy the data. The caller is 702 * expected to check msg->reply before touching it. 703 * 704 * Return payload size. 705 */ 706 ret--; 707 memcpy(msg->buffer, rxbuf + 1, ret); 708 } 709 break; 710 711 default: 712 ret = -EINVAL; 713 break; 714 } 715 716 return ret; 717} 718 719static void 720intel_dp_aux_init(struct intel_dp *intel_dp, struct intel_connector *connector) 721{ 722 struct drm_device *dev = intel_dp_to_dev(intel_dp); 723 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 724 enum port port = intel_dig_port->port; 725 const char *name = NULL; 726 int ret; 727 728 switch (port) { 729 case PORT_A: 730 intel_dp->aux_ch_ctl_reg = DPA_AUX_CH_CTL; 731 name = "DPDDC-A"; 732 break; 733 case PORT_B: 734 intel_dp->aux_ch_ctl_reg = PCH_DPB_AUX_CH_CTL; 735 name = "DPDDC-B"; 736 break; 737 case PORT_C: 738 intel_dp->aux_ch_ctl_reg = PCH_DPC_AUX_CH_CTL; 739 name = "DPDDC-C"; 740 break; 741 case PORT_D: 742 intel_dp->aux_ch_ctl_reg = PCH_DPD_AUX_CH_CTL; 743 name = "DPDDC-D"; 744 break; 745 default: 746 BUG(); 747 } 748 749 if (!HAS_DDI(dev)) 750 intel_dp->aux_ch_ctl_reg = intel_dp->output_reg + 0x10; 751 752 intel_dp->aux.name = name; 753 intel_dp->aux.dev = dev->dev; 754 intel_dp->aux.transfer = intel_dp_aux_transfer; 755 756 DRM_DEBUG_KMS("registering %s bus for %s\n", name, 757 connector->base.kdev->kobj.name); 758 759 ret = drm_dp_aux_register(&intel_dp->aux); 760 if (ret < 0) { 761 DRM_ERROR("drm_dp_aux_register() for %s failed (%d)\n", 762 name, ret); 763 return; 764 } 765 766 ret = sysfs_create_link(&connector->base.kdev->kobj, 767 &intel_dp->aux.ddc.dev.kobj, 768 intel_dp->aux.ddc.dev.kobj.name); 769 if (ret < 0) { 770 DRM_ERROR("sysfs_create_link() for %s failed (%d)\n", name, ret); 771 drm_dp_aux_unregister(&intel_dp->aux); 772 } 773} 774 775static void 776intel_dp_connector_unregister(struct intel_connector *intel_connector) 777{ 778 struct intel_dp *intel_dp = intel_attached_dp(&intel_connector->base); 779 780 if (!intel_connector->mst_port) 781 sysfs_remove_link(&intel_connector->base.kdev->kobj, 782 intel_dp->aux.ddc.dev.kobj.name); 783 intel_connector_unregister(intel_connector); 784} 785 786static void 787hsw_dp_set_ddi_pll_sel(struct intel_crtc_config *pipe_config, int link_bw) 788{ 789 switch (link_bw) { 790 case DP_LINK_BW_1_62: 791 pipe_config->ddi_pll_sel = PORT_CLK_SEL_LCPLL_810; 792 break; 793 case DP_LINK_BW_2_7: 794 pipe_config->ddi_pll_sel = PORT_CLK_SEL_LCPLL_1350; 795 break; 796 case DP_LINK_BW_5_4: 797 pipe_config->ddi_pll_sel = PORT_CLK_SEL_LCPLL_2700; 798 break; 799 } 800} 801 802static void 803intel_dp_set_clock(struct intel_encoder *encoder, 804 struct intel_crtc_config *pipe_config, int link_bw) 805{ 806 struct drm_device *dev = encoder->base.dev; 807 const struct dp_link_dpll *divisor = NULL; 808 int i, count = 0; 809 810 if (IS_G4X(dev)) { 811 divisor = gen4_dpll; 812 count = ARRAY_SIZE(gen4_dpll); 813 } else if (HAS_PCH_SPLIT(dev)) { 814 divisor = pch_dpll; 815 count = ARRAY_SIZE(pch_dpll); 816 } else if (IS_CHERRYVIEW(dev)) { 817 divisor = chv_dpll; 818 count = ARRAY_SIZE(chv_dpll); 819 } else if (IS_VALLEYVIEW(dev)) { 820 divisor = vlv_dpll; 821 count = ARRAY_SIZE(vlv_dpll); 822 } 823 824 if (divisor && count) { 825 for (i = 0; i < count; i++) { 826 if (link_bw == divisor[i].link_bw) { 827 pipe_config->dpll = divisor[i].dpll; 828 pipe_config->clock_set = true; 829 break; 830 } 831 } 832 } 833} 834 835bool 836intel_dp_compute_config(struct intel_encoder *encoder, 837 struct intel_crtc_config *pipe_config) 838{ 839 struct drm_device *dev = encoder->base.dev; 840 struct drm_i915_private *dev_priv = dev->dev_private; 841 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode; 842 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); 843 enum port port = dp_to_dig_port(intel_dp)->port; 844 struct intel_crtc *intel_crtc = encoder->new_crtc; 845 struct intel_connector *intel_connector = intel_dp->attached_connector; 846 int lane_count, clock; 847 int min_lane_count = 1; 848 int max_lane_count = intel_dp_max_lane_count(intel_dp); 849 /* Conveniently, the link BW constants become indices with a shift...*/ 850 int min_clock = 0; 851 int max_clock = intel_dp_max_link_bw(intel_dp) >> 3; 852 int bpp, mode_rate; 853 static int bws[] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7, DP_LINK_BW_5_4 }; 854 int link_avail, link_clock; 855 856 if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev) && port != PORT_A) 857 pipe_config->has_pch_encoder = true; 858 859 pipe_config->has_dp_encoder = true; 860 pipe_config->has_drrs = false; 861 pipe_config->has_audio = intel_dp->has_audio; 862 863 if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) { 864 intel_fixed_panel_mode(intel_connector->panel.fixed_mode, 865 adjusted_mode); 866 if (!HAS_PCH_SPLIT(dev)) 867 intel_gmch_panel_fitting(intel_crtc, pipe_config, 868 intel_connector->panel.fitting_mode); 869 else 870 intel_pch_panel_fitting(intel_crtc, pipe_config, 871 intel_connector->panel.fitting_mode); 872 } 873 874 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK) 875 return false; 876 877 DRM_DEBUG_KMS("DP link computation with max lane count %i " 878 "max bw %02x pixel clock %iKHz\n", 879 max_lane_count, bws[max_clock], 880 adjusted_mode->crtc_clock); 881 882 /* Walk through all bpp values. Luckily they're all nicely spaced with 2 883 * bpc in between. */ 884 bpp = pipe_config->pipe_bpp; 885 if (is_edp(intel_dp)) { 886 if (dev_priv->vbt.edp_bpp && dev_priv->vbt.edp_bpp < bpp) { 887 DRM_DEBUG_KMS("clamping bpp for eDP panel to BIOS-provided %i\n", 888 dev_priv->vbt.edp_bpp); 889 bpp = dev_priv->vbt.edp_bpp; 890 } 891 892 if (IS_BROADWELL(dev)) { 893 /* Yes, it's an ugly hack. */ 894 min_lane_count = max_lane_count; 895 DRM_DEBUG_KMS("forcing lane count to max (%u) on BDW\n", 896 min_lane_count); 897 } else if (dev_priv->vbt.edp_lanes) { 898 min_lane_count = min(dev_priv->vbt.edp_lanes, 899 max_lane_count); 900 DRM_DEBUG_KMS("using min %u lanes per VBT\n", 901 min_lane_count); 902 } 903 904 if (dev_priv->vbt.edp_rate) { 905 min_clock = min(dev_priv->vbt.edp_rate >> 3, max_clock); 906 DRM_DEBUG_KMS("using min %02x link bw per VBT\n", 907 bws[min_clock]); 908 } 909 } 910 911 for (; bpp >= 6*3; bpp -= 2*3) { 912 mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock, 913 bpp); 914 915 for (clock = min_clock; clock <= max_clock; clock++) { 916 for (lane_count = min_lane_count; lane_count <= max_lane_count; lane_count <<= 1) { 917 link_clock = drm_dp_bw_code_to_link_rate(bws[clock]); 918 link_avail = intel_dp_max_data_rate(link_clock, 919 lane_count); 920 921 if (mode_rate <= link_avail) { 922 goto found; 923 } 924 } 925 } 926 } 927 928 return false; 929 930found: 931 if (intel_dp->color_range_auto) { 932 /* 933 * See: 934 * CEA-861-E - 5.1 Default Encoding Parameters 935 * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry 936 */ 937 if (bpp != 18 && drm_match_cea_mode(adjusted_mode) > 1) 938 intel_dp->color_range = DP_COLOR_RANGE_16_235; 939 else 940 intel_dp->color_range = 0; 941 } 942 943 if (intel_dp->color_range) 944 pipe_config->limited_color_range = true; 945 946 intel_dp->link_bw = bws[clock]; 947 intel_dp->lane_count = lane_count; 948 pipe_config->pipe_bpp = bpp; 949 pipe_config->port_clock = drm_dp_bw_code_to_link_rate(intel_dp->link_bw); 950 951 DRM_DEBUG_KMS("DP link bw %02x lane count %d clock %d bpp %d\n", 952 intel_dp->link_bw, intel_dp->lane_count, 953 pipe_config->port_clock, bpp); 954 DRM_DEBUG_KMS("DP link bw required %i available %i\n", 955 mode_rate, link_avail); 956 957 intel_link_compute_m_n(bpp, lane_count, 958 adjusted_mode->crtc_clock, 959 pipe_config->port_clock, 960 &pipe_config->dp_m_n); 961 962 if (intel_connector->panel.downclock_mode != NULL && 963 intel_dp->drrs_state.type == SEAMLESS_DRRS_SUPPORT) { 964 pipe_config->has_drrs = true; 965 intel_link_compute_m_n(bpp, lane_count, 966 intel_connector->panel.downclock_mode->clock, 967 pipe_config->port_clock, 968 &pipe_config->dp_m2_n2); 969 } 970 971 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) 972 hsw_dp_set_ddi_pll_sel(pipe_config, intel_dp->link_bw); 973 else 974 intel_dp_set_clock(encoder, pipe_config, intel_dp->link_bw); 975 976 return true; 977} 978 979static void ironlake_set_pll_cpu_edp(struct intel_dp *intel_dp) 980{ 981 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 982 struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc); 983 struct drm_device *dev = crtc->base.dev; 984 struct drm_i915_private *dev_priv = dev->dev_private; 985 u32 dpa_ctl; 986 987 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", crtc->config.port_clock); 988 dpa_ctl = I915_READ(DP_A); 989 dpa_ctl &= ~DP_PLL_FREQ_MASK; 990 991 if (crtc->config.port_clock == 162000) { 992 /* For a long time we've carried around a ILK-DevA w/a for the 993 * 160MHz clock. If we're really unlucky, it's still required. 994 */ 995 DRM_DEBUG_KMS("160MHz cpu eDP clock, might need ilk devA w/a\n"); 996 dpa_ctl |= DP_PLL_FREQ_160MHZ; 997 intel_dp->DP |= DP_PLL_FREQ_160MHZ; 998 } else { 999 dpa_ctl |= DP_PLL_FREQ_270MHZ; 1000 intel_dp->DP |= DP_PLL_FREQ_270MHZ; 1001 } 1002 1003 I915_WRITE(DP_A, dpa_ctl); 1004 1005 POSTING_READ(DP_A); 1006 udelay(500); 1007} 1008 1009static void intel_dp_prepare(struct intel_encoder *encoder) 1010{ 1011 struct drm_device *dev = encoder->base.dev; 1012 struct drm_i915_private *dev_priv = dev->dev_private; 1013 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); 1014 enum port port = dp_to_dig_port(intel_dp)->port; 1015 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); 1016 struct drm_display_mode *adjusted_mode = &crtc->config.adjusted_mode; 1017 1018 /* 1019 * There are four kinds of DP registers: 1020 * 1021 * IBX PCH 1022 * SNB CPU 1023 * IVB CPU 1024 * CPT PCH 1025 * 1026 * IBX PCH and CPU are the same for almost everything, 1027 * except that the CPU DP PLL is configured in this 1028 * register 1029 * 1030 * CPT PCH is quite different, having many bits moved 1031 * to the TRANS_DP_CTL register instead. That 1032 * configuration happens (oddly) in ironlake_pch_enable 1033 */ 1034 1035 /* Preserve the BIOS-computed detected bit. This is 1036 * supposed to be read-only. 1037 */ 1038 intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED; 1039 1040 /* Handle DP bits in common between all three register formats */ 1041 intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0; 1042 intel_dp->DP |= DP_PORT_WIDTH(intel_dp->lane_count); 1043 1044 if (crtc->config.has_audio) { 1045 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n", 1046 pipe_name(crtc->pipe)); 1047 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE; 1048 intel_write_eld(&encoder->base, adjusted_mode); 1049 } 1050 1051 /* Split out the IBX/CPU vs CPT settings */ 1052 1053 if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) { 1054 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) 1055 intel_dp->DP |= DP_SYNC_HS_HIGH; 1056 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) 1057 intel_dp->DP |= DP_SYNC_VS_HIGH; 1058 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT; 1059 1060 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd)) 1061 intel_dp->DP |= DP_ENHANCED_FRAMING; 1062 1063 intel_dp->DP |= crtc->pipe << 29; 1064 } else if (!HAS_PCH_CPT(dev) || port == PORT_A) { 1065 if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev)) 1066 intel_dp->DP |= intel_dp->color_range; 1067 1068 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) 1069 intel_dp->DP |= DP_SYNC_HS_HIGH; 1070 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) 1071 intel_dp->DP |= DP_SYNC_VS_HIGH; 1072 intel_dp->DP |= DP_LINK_TRAIN_OFF; 1073 1074 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd)) 1075 intel_dp->DP |= DP_ENHANCED_FRAMING; 1076 1077 if (!IS_CHERRYVIEW(dev)) { 1078 if (crtc->pipe == 1) 1079 intel_dp->DP |= DP_PIPEB_SELECT; 1080 } else { 1081 intel_dp->DP |= DP_PIPE_SELECT_CHV(crtc->pipe); 1082 } 1083 } else { 1084 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT; 1085 } 1086} 1087 1088#define IDLE_ON_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK) 1089#define IDLE_ON_VALUE (PP_ON | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE) 1090 1091#define IDLE_OFF_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | 0) 1092#define IDLE_OFF_VALUE (0 | PP_SEQUENCE_NONE | 0 | 0) 1093 1094#define IDLE_CYCLE_MASK (PP_ON | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK) 1095#define IDLE_CYCLE_VALUE (0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE) 1096 1097static void wait_panel_status(struct intel_dp *intel_dp, 1098 u32 mask, 1099 u32 value) 1100{ 1101 struct drm_device *dev = intel_dp_to_dev(intel_dp); 1102 struct drm_i915_private *dev_priv = dev->dev_private; 1103 u32 pp_stat_reg, pp_ctrl_reg; 1104 1105 pp_stat_reg = _pp_stat_reg(intel_dp); 1106 pp_ctrl_reg = _pp_ctrl_reg(intel_dp); 1107 1108 DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n", 1109 mask, value, 1110 I915_READ(pp_stat_reg), 1111 I915_READ(pp_ctrl_reg)); 1112 1113 if (_wait_for((I915_READ(pp_stat_reg) & mask) == value, 5000, 10)) { 1114 DRM_ERROR("Panel status timeout: status %08x control %08x\n", 1115 I915_READ(pp_stat_reg), 1116 I915_READ(pp_ctrl_reg)); 1117 } 1118 1119 DRM_DEBUG_KMS("Wait complete\n"); 1120} 1121 1122static void wait_panel_on(struct intel_dp *intel_dp) 1123{ 1124 DRM_DEBUG_KMS("Wait for panel power on\n"); 1125 wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE); 1126} 1127 1128static void wait_panel_off(struct intel_dp *intel_dp) 1129{ 1130 DRM_DEBUG_KMS("Wait for panel power off time\n"); 1131 wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE); 1132} 1133 1134static void wait_panel_power_cycle(struct intel_dp *intel_dp) 1135{ 1136 DRM_DEBUG_KMS("Wait for panel power cycle\n"); 1137 1138 /* When we disable the VDD override bit last we have to do the manual 1139 * wait. */ 1140 wait_remaining_ms_from_jiffies(intel_dp->last_power_cycle, 1141 intel_dp->panel_power_cycle_delay); 1142 1143 wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE); 1144} 1145 1146static void wait_backlight_on(struct intel_dp *intel_dp) 1147{ 1148 wait_remaining_ms_from_jiffies(intel_dp->last_power_on, 1149 intel_dp->backlight_on_delay); 1150} 1151 1152static void edp_wait_backlight_off(struct intel_dp *intel_dp) 1153{ 1154 wait_remaining_ms_from_jiffies(intel_dp->last_backlight_off, 1155 intel_dp->backlight_off_delay); 1156} 1157 1158/* Read the current pp_control value, unlocking the register if it 1159 * is locked 1160 */ 1161 1162static u32 ironlake_get_pp_control(struct intel_dp *intel_dp) 1163{ 1164 struct drm_device *dev = intel_dp_to_dev(intel_dp); 1165 struct drm_i915_private *dev_priv = dev->dev_private; 1166 u32 control; 1167 1168 control = I915_READ(_pp_ctrl_reg(intel_dp)); 1169 control &= ~PANEL_UNLOCK_MASK; 1170 control |= PANEL_UNLOCK_REGS; 1171 return control; 1172} 1173 1174static bool edp_panel_vdd_on(struct intel_dp *intel_dp) 1175{ 1176 struct drm_device *dev = intel_dp_to_dev(intel_dp); 1177 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 1178 struct intel_encoder *intel_encoder = &intel_dig_port->base; 1179 struct drm_i915_private *dev_priv = dev->dev_private; 1180 enum intel_display_power_domain power_domain; 1181 u32 pp; 1182 u32 pp_stat_reg, pp_ctrl_reg; 1183 bool need_to_disable = !intel_dp->want_panel_vdd; 1184 1185 if (!is_edp(intel_dp)) 1186 return false; 1187 1188 intel_dp->want_panel_vdd = true; 1189 1190 if (edp_have_panel_vdd(intel_dp)) 1191 return need_to_disable; 1192 1193 power_domain = intel_display_port_power_domain(intel_encoder); 1194 intel_display_power_get(dev_priv, power_domain); 1195 1196 DRM_DEBUG_KMS("Turning eDP VDD on\n"); 1197 1198 if (!edp_have_panel_power(intel_dp)) 1199 wait_panel_power_cycle(intel_dp); 1200 1201 pp = ironlake_get_pp_control(intel_dp); 1202 pp |= EDP_FORCE_VDD; 1203 1204 pp_stat_reg = _pp_stat_reg(intel_dp); 1205 pp_ctrl_reg = _pp_ctrl_reg(intel_dp); 1206 1207 I915_WRITE(pp_ctrl_reg, pp); 1208 POSTING_READ(pp_ctrl_reg); 1209 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n", 1210 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg)); 1211 /* 1212 * If the panel wasn't on, delay before accessing aux channel 1213 */ 1214 if (!edp_have_panel_power(intel_dp)) { 1215 DRM_DEBUG_KMS("eDP was not running\n"); 1216 msleep(intel_dp->panel_power_up_delay); 1217 } 1218 1219 return need_to_disable; 1220} 1221 1222void intel_edp_panel_vdd_on(struct intel_dp *intel_dp) 1223{ 1224 bool vdd; 1225 1226 if (!is_edp(intel_dp)) 1227 return; 1228 1229 vdd = edp_panel_vdd_on(intel_dp); 1230 1231 WARN(!vdd, "eDP VDD already requested on\n"); 1232} 1233 1234static void edp_panel_vdd_off_sync(struct intel_dp *intel_dp) 1235{ 1236 struct drm_device *dev = intel_dp_to_dev(intel_dp); 1237 struct drm_i915_private *dev_priv = dev->dev_private; 1238 struct intel_digital_port *intel_dig_port = 1239 dp_to_dig_port(intel_dp); 1240 struct intel_encoder *intel_encoder = &intel_dig_port->base; 1241 enum intel_display_power_domain power_domain; 1242 u32 pp; 1243 u32 pp_stat_reg, pp_ctrl_reg; 1244 1245 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex)); 1246 1247 WARN_ON(intel_dp->want_panel_vdd); 1248 1249 if (!edp_have_panel_vdd(intel_dp)) 1250 return; 1251 1252 DRM_DEBUG_KMS("Turning eDP VDD off\n"); 1253 1254 pp = ironlake_get_pp_control(intel_dp); 1255 pp &= ~EDP_FORCE_VDD; 1256 1257 pp_ctrl_reg = _pp_ctrl_reg(intel_dp); 1258 pp_stat_reg = _pp_stat_reg(intel_dp); 1259 1260 I915_WRITE(pp_ctrl_reg, pp); 1261 POSTING_READ(pp_ctrl_reg); 1262 1263 /* Make sure sequencer is idle before allowing subsequent activity */ 1264 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n", 1265 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg)); 1266 1267 if ((pp & POWER_TARGET_ON) == 0) 1268 intel_dp->last_power_cycle = jiffies; 1269 1270 power_domain = intel_display_port_power_domain(intel_encoder); 1271 intel_display_power_put(dev_priv, power_domain); 1272} 1273 1274static void edp_panel_vdd_work(struct work_struct *__work) 1275{ 1276 struct intel_dp *intel_dp = container_of(to_delayed_work(__work), 1277 struct intel_dp, panel_vdd_work); 1278 struct drm_device *dev = intel_dp_to_dev(intel_dp); 1279 1280 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL); 1281 if (!intel_dp->want_panel_vdd) 1282 edp_panel_vdd_off_sync(intel_dp); 1283 drm_modeset_unlock(&dev->mode_config.connection_mutex); 1284} 1285 1286static void edp_panel_vdd_schedule_off(struct intel_dp *intel_dp) 1287{ 1288 unsigned long delay; 1289 1290 /* 1291 * Queue the timer to fire a long time from now (relative to the power 1292 * down delay) to keep the panel power up across a sequence of 1293 * operations. 1294 */ 1295 delay = msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5); 1296 schedule_delayed_work(&intel_dp->panel_vdd_work, delay); 1297} 1298 1299static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync) 1300{ 1301 if (!is_edp(intel_dp)) 1302 return; 1303 1304 WARN(!intel_dp->want_panel_vdd, "eDP VDD not forced on"); 1305 1306 intel_dp->want_panel_vdd = false; 1307 1308 if (sync) 1309 edp_panel_vdd_off_sync(intel_dp); 1310 else 1311 edp_panel_vdd_schedule_off(intel_dp); 1312} 1313 1314static void intel_edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync) 1315{ 1316 edp_panel_vdd_off(intel_dp, sync); 1317} 1318 1319void intel_edp_panel_on(struct intel_dp *intel_dp) 1320{ 1321 struct drm_device *dev = intel_dp_to_dev(intel_dp); 1322 struct drm_i915_private *dev_priv = dev->dev_private; 1323 u32 pp; 1324 u32 pp_ctrl_reg; 1325 1326 if (!is_edp(intel_dp)) 1327 return; 1328 1329 DRM_DEBUG_KMS("Turn eDP power on\n"); 1330 1331 if (edp_have_panel_power(intel_dp)) { 1332 DRM_DEBUG_KMS("eDP power already on\n"); 1333 return; 1334 } 1335 1336 wait_panel_power_cycle(intel_dp); 1337 1338 pp_ctrl_reg = _pp_ctrl_reg(intel_dp); 1339 pp = ironlake_get_pp_control(intel_dp); 1340 if (IS_GEN5(dev)) { 1341 /* ILK workaround: disable reset around power sequence */ 1342 pp &= ~PANEL_POWER_RESET; 1343 I915_WRITE(pp_ctrl_reg, pp); 1344 POSTING_READ(pp_ctrl_reg); 1345 } 1346 1347 pp |= POWER_TARGET_ON; 1348 if (!IS_GEN5(dev)) 1349 pp |= PANEL_POWER_RESET; 1350 1351 I915_WRITE(pp_ctrl_reg, pp); 1352 POSTING_READ(pp_ctrl_reg); 1353 1354 wait_panel_on(intel_dp); 1355 intel_dp->last_power_on = jiffies; 1356 1357 if (IS_GEN5(dev)) { 1358 pp |= PANEL_POWER_RESET; /* restore panel reset bit */ 1359 I915_WRITE(pp_ctrl_reg, pp); 1360 POSTING_READ(pp_ctrl_reg); 1361 } 1362} 1363 1364void intel_edp_panel_off(struct intel_dp *intel_dp) 1365{ 1366 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 1367 struct intel_encoder *intel_encoder = &intel_dig_port->base; 1368 struct drm_device *dev = intel_dp_to_dev(intel_dp); 1369 struct drm_i915_private *dev_priv = dev->dev_private; 1370 enum intel_display_power_domain power_domain; 1371 u32 pp; 1372 u32 pp_ctrl_reg; 1373 1374 if (!is_edp(intel_dp)) 1375 return; 1376 1377 DRM_DEBUG_KMS("Turn eDP power off\n"); 1378 1379 WARN(!intel_dp->want_panel_vdd, "Need VDD to turn off panel\n"); 1380 1381 pp = ironlake_get_pp_control(intel_dp); 1382 /* We need to switch off panel power _and_ force vdd, for otherwise some 1383 * panels get very unhappy and cease to work. */ 1384 pp &= ~(POWER_TARGET_ON | PANEL_POWER_RESET | EDP_FORCE_VDD | 1385 EDP_BLC_ENABLE); 1386 1387 pp_ctrl_reg = _pp_ctrl_reg(intel_dp); 1388 1389 intel_dp->want_panel_vdd = false; 1390 1391 I915_WRITE(pp_ctrl_reg, pp); 1392 POSTING_READ(pp_ctrl_reg); 1393 1394 intel_dp->last_power_cycle = jiffies; 1395 wait_panel_off(intel_dp); 1396 1397 /* We got a reference when we enabled the VDD. */ 1398 power_domain = intel_display_port_power_domain(intel_encoder); 1399 intel_display_power_put(dev_priv, power_domain); 1400} 1401 1402/* Enable backlight in the panel power control. */ 1403static void _intel_edp_backlight_on(struct intel_dp *intel_dp) 1404{ 1405 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 1406 struct drm_device *dev = intel_dig_port->base.base.dev; 1407 struct drm_i915_private *dev_priv = dev->dev_private; 1408 u32 pp; 1409 u32 pp_ctrl_reg; 1410 1411 /* 1412 * If we enable the backlight right away following a panel power 1413 * on, we may see slight flicker as the panel syncs with the eDP 1414 * link. So delay a bit to make sure the image is solid before 1415 * allowing it to appear. 1416 */ 1417 wait_backlight_on(intel_dp); 1418 pp = ironlake_get_pp_control(intel_dp); 1419 pp |= EDP_BLC_ENABLE; 1420 1421 pp_ctrl_reg = _pp_ctrl_reg(intel_dp); 1422 1423 I915_WRITE(pp_ctrl_reg, pp); 1424 POSTING_READ(pp_ctrl_reg); 1425} 1426 1427/* Enable backlight PWM and backlight PP control. */ 1428void intel_edp_backlight_on(struct intel_dp *intel_dp) 1429{ 1430 if (!is_edp(intel_dp)) 1431 return; 1432 1433 DRM_DEBUG_KMS("\n"); 1434 1435 intel_panel_enable_backlight(intel_dp->attached_connector); 1436 _intel_edp_backlight_on(intel_dp); 1437} 1438 1439/* Disable backlight in the panel power control. */ 1440static void _intel_edp_backlight_off(struct intel_dp *intel_dp) 1441{ 1442 struct drm_device *dev = intel_dp_to_dev(intel_dp); 1443 struct drm_i915_private *dev_priv = dev->dev_private; 1444 u32 pp; 1445 u32 pp_ctrl_reg; 1446 1447 pp = ironlake_get_pp_control(intel_dp); 1448 pp &= ~EDP_BLC_ENABLE; 1449 1450 pp_ctrl_reg = _pp_ctrl_reg(intel_dp); 1451 1452 I915_WRITE(pp_ctrl_reg, pp); 1453 POSTING_READ(pp_ctrl_reg); 1454 intel_dp->last_backlight_off = jiffies; 1455 1456 edp_wait_backlight_off(intel_dp); 1457} 1458 1459/* Disable backlight PP control and backlight PWM. */ 1460void intel_edp_backlight_off(struct intel_dp *intel_dp) 1461{ 1462 if (!is_edp(intel_dp)) 1463 return; 1464 1465 DRM_DEBUG_KMS("\n"); 1466 1467 _intel_edp_backlight_off(intel_dp); 1468 intel_panel_disable_backlight(intel_dp->attached_connector); 1469} 1470 1471/* 1472 * Hook for controlling the panel power control backlight through the bl_power 1473 * sysfs attribute. Take care to handle multiple calls. 1474 */ 1475static void intel_edp_backlight_power(struct intel_connector *connector, 1476 bool enable) 1477{ 1478 struct intel_dp *intel_dp = intel_attached_dp(&connector->base); 1479 bool is_enabled = ironlake_get_pp_control(intel_dp) & EDP_BLC_ENABLE; 1480 1481 if (is_enabled == enable) 1482 return; 1483 1484 DRM_DEBUG_KMS("panel power control backlight %s\n", 1485 enable ? "enable" : "disable"); 1486 1487 if (enable) 1488 _intel_edp_backlight_on(intel_dp); 1489 else 1490 _intel_edp_backlight_off(intel_dp); 1491} 1492 1493static void ironlake_edp_pll_on(struct intel_dp *intel_dp) 1494{ 1495 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 1496 struct drm_crtc *crtc = intel_dig_port->base.base.crtc; 1497 struct drm_device *dev = crtc->dev; 1498 struct drm_i915_private *dev_priv = dev->dev_private; 1499 u32 dpa_ctl; 1500 1501 assert_pipe_disabled(dev_priv, 1502 to_intel_crtc(crtc)->pipe); 1503 1504 DRM_DEBUG_KMS("\n"); 1505 dpa_ctl = I915_READ(DP_A); 1506 WARN(dpa_ctl & DP_PLL_ENABLE, "dp pll on, should be off\n"); 1507 WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n"); 1508 1509 /* We don't adjust intel_dp->DP while tearing down the link, to 1510 * facilitate link retraining (e.g. after hotplug). Hence clear all 1511 * enable bits here to ensure that we don't enable too much. */ 1512 intel_dp->DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE); 1513 intel_dp->DP |= DP_PLL_ENABLE; 1514 I915_WRITE(DP_A, intel_dp->DP); 1515 POSTING_READ(DP_A); 1516 udelay(200); 1517} 1518 1519static void ironlake_edp_pll_off(struct intel_dp *intel_dp) 1520{ 1521 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 1522 struct drm_crtc *crtc = intel_dig_port->base.base.crtc; 1523 struct drm_device *dev = crtc->dev; 1524 struct drm_i915_private *dev_priv = dev->dev_private; 1525 u32 dpa_ctl; 1526 1527 assert_pipe_disabled(dev_priv, 1528 to_intel_crtc(crtc)->pipe); 1529 1530 dpa_ctl = I915_READ(DP_A); 1531 WARN((dpa_ctl & DP_PLL_ENABLE) == 0, 1532 "dp pll off, should be on\n"); 1533 WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n"); 1534 1535 /* We can't rely on the value tracked for the DP register in 1536 * intel_dp->DP because link_down must not change that (otherwise link 1537 * re-training will fail. */ 1538 dpa_ctl &= ~DP_PLL_ENABLE; 1539 I915_WRITE(DP_A, dpa_ctl); 1540 POSTING_READ(DP_A); 1541 udelay(200); 1542} 1543 1544/* If the sink supports it, try to set the power state appropriately */ 1545void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode) 1546{ 1547 int ret, i; 1548 1549 /* Should have a valid DPCD by this point */ 1550 if (intel_dp->dpcd[DP_DPCD_REV] < 0x11) 1551 return; 1552 1553 if (mode != DRM_MODE_DPMS_ON) { 1554 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER, 1555 DP_SET_POWER_D3); 1556 } else { 1557 /* 1558 * When turning on, we need to retry for 1ms to give the sink 1559 * time to wake up. 1560 */ 1561 for (i = 0; i < 3; i++) { 1562 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER, 1563 DP_SET_POWER_D0); 1564 if (ret == 1) 1565 break; 1566 msleep(1); 1567 } 1568 } 1569 1570 if (ret != 1) 1571 DRM_DEBUG_KMS("failed to %s sink power state\n", 1572 mode == DRM_MODE_DPMS_ON ? "enable" : "disable"); 1573} 1574 1575static bool intel_dp_get_hw_state(struct intel_encoder *encoder, 1576 enum pipe *pipe) 1577{ 1578 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); 1579 enum port port = dp_to_dig_port(intel_dp)->port; 1580 struct drm_device *dev = encoder->base.dev; 1581 struct drm_i915_private *dev_priv = dev->dev_private; 1582 enum intel_display_power_domain power_domain; 1583 u32 tmp; 1584 1585 power_domain = intel_display_port_power_domain(encoder); 1586 if (!intel_display_power_enabled(dev_priv, power_domain)) 1587 return false; 1588 1589 tmp = I915_READ(intel_dp->output_reg); 1590 1591 if (!(tmp & DP_PORT_EN)) 1592 return false; 1593 1594 if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) { 1595 *pipe = PORT_TO_PIPE_CPT(tmp); 1596 } else if (IS_CHERRYVIEW(dev)) { 1597 *pipe = DP_PORT_TO_PIPE_CHV(tmp); 1598 } else if (!HAS_PCH_CPT(dev) || port == PORT_A) { 1599 *pipe = PORT_TO_PIPE(tmp); 1600 } else { 1601 u32 trans_sel; 1602 u32 trans_dp; 1603 int i; 1604 1605 switch (intel_dp->output_reg) { 1606 case PCH_DP_B: 1607 trans_sel = TRANS_DP_PORT_SEL_B; 1608 break; 1609 case PCH_DP_C: 1610 trans_sel = TRANS_DP_PORT_SEL_C; 1611 break; 1612 case PCH_DP_D: 1613 trans_sel = TRANS_DP_PORT_SEL_D; 1614 break; 1615 default: 1616 return true; 1617 } 1618 1619 for_each_pipe(dev_priv, i) { 1620 trans_dp = I915_READ(TRANS_DP_CTL(i)); 1621 if ((trans_dp & TRANS_DP_PORT_SEL_MASK) == trans_sel) { 1622 *pipe = i; 1623 return true; 1624 } 1625 } 1626 1627 DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n", 1628 intel_dp->output_reg); 1629 } 1630 1631 return true; 1632} 1633 1634static void intel_dp_get_config(struct intel_encoder *encoder, 1635 struct intel_crtc_config *pipe_config) 1636{ 1637 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); 1638 u32 tmp, flags = 0; 1639 struct drm_device *dev = encoder->base.dev; 1640 struct drm_i915_private *dev_priv = dev->dev_private; 1641 enum port port = dp_to_dig_port(intel_dp)->port; 1642 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); 1643 int dotclock; 1644 1645 tmp = I915_READ(intel_dp->output_reg); 1646 if (tmp & DP_AUDIO_OUTPUT_ENABLE) 1647 pipe_config->has_audio = true; 1648 1649 if ((port == PORT_A) || !HAS_PCH_CPT(dev)) { 1650 if (tmp & DP_SYNC_HS_HIGH) 1651 flags |= DRM_MODE_FLAG_PHSYNC; 1652 else 1653 flags |= DRM_MODE_FLAG_NHSYNC; 1654 1655 if (tmp & DP_SYNC_VS_HIGH) 1656 flags |= DRM_MODE_FLAG_PVSYNC; 1657 else 1658 flags |= DRM_MODE_FLAG_NVSYNC; 1659 } else { 1660 tmp = I915_READ(TRANS_DP_CTL(crtc->pipe)); 1661 if (tmp & TRANS_DP_HSYNC_ACTIVE_HIGH) 1662 flags |= DRM_MODE_FLAG_PHSYNC; 1663 else 1664 flags |= DRM_MODE_FLAG_NHSYNC; 1665 1666 if (tmp & TRANS_DP_VSYNC_ACTIVE_HIGH) 1667 flags |= DRM_MODE_FLAG_PVSYNC; 1668 else 1669 flags |= DRM_MODE_FLAG_NVSYNC; 1670 } 1671 1672 pipe_config->adjusted_mode.flags |= flags; 1673 1674 pipe_config->has_dp_encoder = true; 1675 1676 intel_dp_get_m_n(crtc, pipe_config); 1677 1678 if (port == PORT_A) { 1679 if ((I915_READ(DP_A) & DP_PLL_FREQ_MASK) == DP_PLL_FREQ_160MHZ) 1680 pipe_config->port_clock = 162000; 1681 else 1682 pipe_config->port_clock = 270000; 1683 } 1684 1685 dotclock = intel_dotclock_calculate(pipe_config->port_clock, 1686 &pipe_config->dp_m_n); 1687 1688 if (HAS_PCH_SPLIT(dev_priv->dev) && port != PORT_A) 1689 ironlake_check_encoder_dotclock(pipe_config, dotclock); 1690 1691 pipe_config->adjusted_mode.crtc_clock = dotclock; 1692 1693 if (is_edp(intel_dp) && dev_priv->vbt.edp_bpp && 1694 pipe_config->pipe_bpp > dev_priv->vbt.edp_bpp) { 1695 /* 1696 * This is a big fat ugly hack. 1697 * 1698 * Some machines in UEFI boot mode provide us a VBT that has 18 1699 * bpp and 1.62 GHz link bandwidth for eDP, which for reasons 1700 * unknown we fail to light up. Yet the same BIOS boots up with 1701 * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as 1702 * max, not what it tells us to use. 1703 * 1704 * Note: This will still be broken if the eDP panel is not lit 1705 * up by the BIOS, and thus we can't get the mode at module 1706 * load. 1707 */ 1708 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n", 1709 pipe_config->pipe_bpp, dev_priv->vbt.edp_bpp); 1710 dev_priv->vbt.edp_bpp = pipe_config->pipe_bpp; 1711 } 1712} 1713 1714static bool is_edp_psr(struct intel_dp *intel_dp) 1715{ 1716 return intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED; 1717} 1718 1719static bool intel_edp_is_psr_enabled(struct drm_device *dev) 1720{ 1721 struct drm_i915_private *dev_priv = dev->dev_private; 1722 1723 if (!HAS_PSR(dev)) 1724 return false; 1725 1726 return I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE; 1727} 1728 1729static void intel_edp_psr_write_vsc(struct intel_dp *intel_dp, 1730 struct edp_vsc_psr *vsc_psr) 1731{ 1732 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 1733 struct drm_device *dev = dig_port->base.base.dev; 1734 struct drm_i915_private *dev_priv = dev->dev_private; 1735 struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc); 1736 u32 ctl_reg = HSW_TVIDEO_DIP_CTL(crtc->config.cpu_transcoder); 1737 u32 data_reg = HSW_TVIDEO_DIP_VSC_DATA(crtc->config.cpu_transcoder); 1738 uint32_t *data = (uint32_t *) vsc_psr; 1739 unsigned int i; 1740 1741 /* As per BSPec (Pipe Video Data Island Packet), we need to disable 1742 the video DIP being updated before program video DIP data buffer 1743 registers for DIP being updated. */ 1744 I915_WRITE(ctl_reg, 0); 1745 POSTING_READ(ctl_reg); 1746 1747 for (i = 0; i < VIDEO_DIP_VSC_DATA_SIZE; i += 4) { 1748 if (i < sizeof(struct edp_vsc_psr)) 1749 I915_WRITE(data_reg + i, *data++); 1750 else 1751 I915_WRITE(data_reg + i, 0); 1752 } 1753 1754 I915_WRITE(ctl_reg, VIDEO_DIP_ENABLE_VSC_HSW); 1755 POSTING_READ(ctl_reg); 1756} 1757 1758static void intel_edp_psr_setup(struct intel_dp *intel_dp) 1759{ 1760 struct drm_device *dev = intel_dp_to_dev(intel_dp); 1761 struct drm_i915_private *dev_priv = dev->dev_private; 1762 struct edp_vsc_psr psr_vsc; 1763 1764 /* Prepare VSC packet as per EDP 1.3 spec, Table 3.10 */ 1765 memset(&psr_vsc, 0, sizeof(psr_vsc)); 1766 psr_vsc.sdp_header.HB0 = 0; 1767 psr_vsc.sdp_header.HB1 = 0x7; 1768 psr_vsc.sdp_header.HB2 = 0x2; 1769 psr_vsc.sdp_header.HB3 = 0x8; 1770 intel_edp_psr_write_vsc(intel_dp, &psr_vsc); 1771 1772 /* Avoid continuous PSR exit by masking memup and hpd */ 1773 I915_WRITE(EDP_PSR_DEBUG_CTL(dev), EDP_PSR_DEBUG_MASK_MEMUP | 1774 EDP_PSR_DEBUG_MASK_HPD | EDP_PSR_DEBUG_MASK_LPSP); 1775} 1776 1777static void intel_edp_psr_enable_sink(struct intel_dp *intel_dp) 1778{ 1779 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 1780 struct drm_device *dev = dig_port->base.base.dev; 1781 struct drm_i915_private *dev_priv = dev->dev_private; 1782 uint32_t aux_clock_divider; 1783 int precharge = 0x3; 1784 int msg_size = 5; /* Header(4) + Message(1) */ 1785 bool only_standby = false; 1786 1787 aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, 0); 1788 1789 if (IS_BROADWELL(dev) && dig_port->port != PORT_A) 1790 only_standby = true; 1791 1792 /* Enable PSR in sink */ 1793 if (intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT || only_standby) 1794 drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG, 1795 DP_PSR_ENABLE & ~DP_PSR_MAIN_LINK_ACTIVE); 1796 else 1797 drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG, 1798 DP_PSR_ENABLE | DP_PSR_MAIN_LINK_ACTIVE); 1799 1800 /* Setup AUX registers */ 1801 I915_WRITE(EDP_PSR_AUX_DATA1(dev), EDP_PSR_DPCD_COMMAND); 1802 I915_WRITE(EDP_PSR_AUX_DATA2(dev), EDP_PSR_DPCD_NORMAL_OPERATION); 1803 I915_WRITE(EDP_PSR_AUX_CTL(dev), 1804 DP_AUX_CH_CTL_TIME_OUT_400us | 1805 (msg_size << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) | 1806 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) | 1807 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT)); 1808} 1809 1810static void intel_edp_psr_enable_source(struct intel_dp *intel_dp) 1811{ 1812 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 1813 struct drm_device *dev = dig_port->base.base.dev; 1814 struct drm_i915_private *dev_priv = dev->dev_private; 1815 uint32_t max_sleep_time = 0x1f; 1816 uint32_t idle_frames = 1; 1817 uint32_t val = 0x0; 1818 const uint32_t link_entry_time = EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES; 1819 bool only_standby = false; 1820 1821 if (IS_BROADWELL(dev) && dig_port->port != PORT_A) 1822 only_standby = true; 1823 1824 if (intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT || only_standby) { 1825 val |= EDP_PSR_LINK_STANDBY; 1826 val |= EDP_PSR_TP2_TP3_TIME_0us; 1827 val |= EDP_PSR_TP1_TIME_0us; 1828 val |= EDP_PSR_SKIP_AUX_EXIT; 1829 val |= IS_BROADWELL(dev) ? BDW_PSR_SINGLE_FRAME : 0; 1830 } else 1831 val |= EDP_PSR_LINK_DISABLE; 1832 1833 I915_WRITE(EDP_PSR_CTL(dev), val | 1834 (IS_BROADWELL(dev) ? 0 : link_entry_time) | 1835 max_sleep_time << EDP_PSR_MAX_SLEEP_TIME_SHIFT | 1836 idle_frames << EDP_PSR_IDLE_FRAME_SHIFT | 1837 EDP_PSR_ENABLE); 1838} 1839 1840static bool intel_edp_psr_match_conditions(struct intel_dp *intel_dp) 1841{ 1842 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 1843 struct drm_device *dev = dig_port->base.base.dev; 1844 struct drm_i915_private *dev_priv = dev->dev_private; 1845 struct drm_crtc *crtc = dig_port->base.base.crtc; 1846 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 1847 1848 lockdep_assert_held(&dev_priv->psr.lock); 1849 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex)); 1850 WARN_ON(!drm_modeset_is_locked(&crtc->mutex)); 1851 1852 dev_priv->psr.source_ok = false; 1853 1854 if (IS_HASWELL(dev) && dig_port->port != PORT_A) { 1855 DRM_DEBUG_KMS("HSW ties PSR to DDI A (eDP)\n"); 1856 return false; 1857 } 1858 1859 if (!i915.enable_psr) { 1860 DRM_DEBUG_KMS("PSR disable by flag\n"); 1861 return false; 1862 } 1863 1864 /* Below limitations aren't valid for Broadwell */ 1865 if (IS_BROADWELL(dev)) 1866 goto out; 1867 1868 if (I915_READ(HSW_STEREO_3D_CTL(intel_crtc->config.cpu_transcoder)) & 1869 S3D_ENABLE) { 1870 DRM_DEBUG_KMS("PSR condition failed: Stereo 3D is Enabled\n"); 1871 return false; 1872 } 1873 1874 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) { 1875 DRM_DEBUG_KMS("PSR condition failed: Interlaced is Enabled\n"); 1876 return false; 1877 } 1878 1879 out: 1880 dev_priv->psr.source_ok = true; 1881 return true; 1882} 1883 1884static void intel_edp_psr_do_enable(struct intel_dp *intel_dp) 1885{ 1886 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 1887 struct drm_device *dev = intel_dig_port->base.base.dev; 1888 struct drm_i915_private *dev_priv = dev->dev_private; 1889 1890 WARN_ON(I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE); 1891 WARN_ON(dev_priv->psr.active); 1892 lockdep_assert_held(&dev_priv->psr.lock); 1893 1894 /* Enable PSR on the panel */ 1895 intel_edp_psr_enable_sink(intel_dp); 1896 1897 /* Enable PSR on the host */ 1898 intel_edp_psr_enable_source(intel_dp); 1899 1900 dev_priv->psr.active = true; 1901} 1902 1903void intel_edp_psr_enable(struct intel_dp *intel_dp) 1904{ 1905 struct drm_device *dev = intel_dp_to_dev(intel_dp); 1906 struct drm_i915_private *dev_priv = dev->dev_private; 1907 1908 if (!HAS_PSR(dev)) { 1909 DRM_DEBUG_KMS("PSR not supported on this platform\n"); 1910 return; 1911 } 1912 1913 if (!is_edp_psr(intel_dp)) { 1914 DRM_DEBUG_KMS("PSR not supported by this panel\n"); 1915 return; 1916 } 1917 1918 mutex_lock(&dev_priv->psr.lock); 1919 if (dev_priv->psr.enabled) { 1920 DRM_DEBUG_KMS("PSR already in use\n"); 1921 mutex_unlock(&dev_priv->psr.lock); 1922 return; 1923 } 1924 1925 dev_priv->psr.busy_frontbuffer_bits = 0; 1926 1927 /* Setup PSR once */ 1928 intel_edp_psr_setup(intel_dp); 1929 1930 if (intel_edp_psr_match_conditions(intel_dp)) 1931 dev_priv->psr.enabled = intel_dp; 1932 mutex_unlock(&dev_priv->psr.lock); 1933} 1934 1935void intel_edp_psr_disable(struct intel_dp *intel_dp) 1936{ 1937 struct drm_device *dev = intel_dp_to_dev(intel_dp); 1938 struct drm_i915_private *dev_priv = dev->dev_private; 1939 1940 mutex_lock(&dev_priv->psr.lock); 1941 if (!dev_priv->psr.enabled) { 1942 mutex_unlock(&dev_priv->psr.lock); 1943 return; 1944 } 1945 1946 if (dev_priv->psr.active) { 1947 I915_WRITE(EDP_PSR_CTL(dev), 1948 I915_READ(EDP_PSR_CTL(dev)) & ~EDP_PSR_ENABLE); 1949 1950 /* Wait till PSR is idle */ 1951 if (_wait_for((I915_READ(EDP_PSR_STATUS_CTL(dev)) & 1952 EDP_PSR_STATUS_STATE_MASK) == 0, 2000, 10)) 1953 DRM_ERROR("Timed out waiting for PSR Idle State\n"); 1954 1955 dev_priv->psr.active = false; 1956 } else { 1957 WARN_ON(I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE); 1958 } 1959 1960 dev_priv->psr.enabled = NULL; 1961 mutex_unlock(&dev_priv->psr.lock); 1962 1963 cancel_delayed_work_sync(&dev_priv->psr.work); 1964} 1965 1966static void intel_edp_psr_work(struct work_struct *work) 1967{ 1968 struct drm_i915_private *dev_priv = 1969 container_of(work, typeof(*dev_priv), psr.work.work); 1970 struct intel_dp *intel_dp = dev_priv->psr.enabled; 1971 1972 mutex_lock(&dev_priv->psr.lock); 1973 intel_dp = dev_priv->psr.enabled; 1974 1975 if (!intel_dp) 1976 goto unlock; 1977 1978 /* 1979 * The delayed work can race with an invalidate hence we need to 1980 * recheck. Since psr_flush first clears this and then reschedules we 1981 * won't ever miss a flush when bailing out here. 1982 */ 1983 if (dev_priv->psr.busy_frontbuffer_bits) 1984 goto unlock; 1985 1986 intel_edp_psr_do_enable(intel_dp); 1987unlock: 1988 mutex_unlock(&dev_priv->psr.lock); 1989} 1990 1991static void intel_edp_psr_do_exit(struct drm_device *dev) 1992{ 1993 struct drm_i915_private *dev_priv = dev->dev_private; 1994 1995 if (dev_priv->psr.active) { 1996 u32 val = I915_READ(EDP_PSR_CTL(dev)); 1997 1998 WARN_ON(!(val & EDP_PSR_ENABLE)); 1999 2000 I915_WRITE(EDP_PSR_CTL(dev), val & ~EDP_PSR_ENABLE); 2001 2002 dev_priv->psr.active = false; 2003 } 2004 2005} 2006 2007void intel_edp_psr_invalidate(struct drm_device *dev, 2008 unsigned frontbuffer_bits) 2009{ 2010 struct drm_i915_private *dev_priv = dev->dev_private; 2011 struct drm_crtc *crtc; 2012 enum pipe pipe; 2013 2014 mutex_lock(&dev_priv->psr.lock); 2015 if (!dev_priv->psr.enabled) { 2016 mutex_unlock(&dev_priv->psr.lock); 2017 return; 2018 } 2019 2020 crtc = dp_to_dig_port(dev_priv->psr.enabled)->base.base.crtc; 2021 pipe = to_intel_crtc(crtc)->pipe; 2022 2023 intel_edp_psr_do_exit(dev); 2024 2025 frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe); 2026 2027 dev_priv->psr.busy_frontbuffer_bits |= frontbuffer_bits; 2028 mutex_unlock(&dev_priv->psr.lock); 2029} 2030 2031void intel_edp_psr_flush(struct drm_device *dev, 2032 unsigned frontbuffer_bits) 2033{ 2034 struct drm_i915_private *dev_priv = dev->dev_private; 2035 struct drm_crtc *crtc; 2036 enum pipe pipe; 2037 2038 mutex_lock(&dev_priv->psr.lock); 2039 if (!dev_priv->psr.enabled) { 2040 mutex_unlock(&dev_priv->psr.lock); 2041 return; 2042 } 2043 2044 crtc = dp_to_dig_port(dev_priv->psr.enabled)->base.base.crtc; 2045 pipe = to_intel_crtc(crtc)->pipe; 2046 dev_priv->psr.busy_frontbuffer_bits &= ~frontbuffer_bits; 2047 2048 /* 2049 * On Haswell sprite plane updates don't result in a psr invalidating 2050 * signal in the hardware. Which means we need to manually fake this in 2051 * software for all flushes, not just when we've seen a preceding 2052 * invalidation through frontbuffer rendering. 2053 */ 2054 if (IS_HASWELL(dev) && 2055 (frontbuffer_bits & INTEL_FRONTBUFFER_SPRITE(pipe))) 2056 intel_edp_psr_do_exit(dev); 2057 2058 if (!dev_priv->psr.active && !dev_priv->psr.busy_frontbuffer_bits) 2059 schedule_delayed_work(&dev_priv->psr.work, 2060 msecs_to_jiffies(100)); 2061 mutex_unlock(&dev_priv->psr.lock); 2062} 2063 2064void intel_edp_psr_init(struct drm_device *dev) 2065{ 2066 struct drm_i915_private *dev_priv = dev->dev_private; 2067 2068 INIT_DELAYED_WORK(&dev_priv->psr.work, intel_edp_psr_work); 2069 mutex_init(&dev_priv->psr.lock); 2070} 2071 2072static void intel_disable_dp(struct intel_encoder *encoder) 2073{ 2074 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); 2075 enum port port = dp_to_dig_port(intel_dp)->port; 2076 struct drm_device *dev = encoder->base.dev; 2077 2078 /* Make sure the panel is off before trying to change the mode. But also 2079 * ensure that we have vdd while we switch off the panel. */ 2080 intel_edp_panel_vdd_on(intel_dp); 2081 intel_edp_backlight_off(intel_dp); 2082 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF); 2083 intel_edp_panel_off(intel_dp); 2084 2085 /* cpu edp my only be disable _after_ the cpu pipe/plane is disabled. */ 2086 if (!(port == PORT_A || IS_VALLEYVIEW(dev))) 2087 intel_dp_link_down(intel_dp); 2088} 2089 2090static void g4x_post_disable_dp(struct intel_encoder *encoder) 2091{ 2092 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); 2093 enum port port = dp_to_dig_port(intel_dp)->port; 2094 2095 if (port != PORT_A) 2096 return; 2097 2098 intel_dp_link_down(intel_dp); 2099 ironlake_edp_pll_off(intel_dp); 2100} 2101 2102static void vlv_post_disable_dp(struct intel_encoder *encoder) 2103{ 2104 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); 2105 2106 intel_dp_link_down(intel_dp); 2107} 2108 2109static void chv_post_disable_dp(struct intel_encoder *encoder) 2110{ 2111 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); 2112 struct intel_digital_port *dport = dp_to_dig_port(intel_dp); 2113 struct drm_device *dev = encoder->base.dev; 2114 struct drm_i915_private *dev_priv = dev->dev_private; 2115 struct intel_crtc *intel_crtc = 2116 to_intel_crtc(encoder->base.crtc); 2117 enum dpio_channel ch = vlv_dport_to_channel(dport); 2118 enum pipe pipe = intel_crtc->pipe; 2119 u32 val; 2120 2121 intel_dp_link_down(intel_dp); 2122 2123 mutex_lock(&dev_priv->dpio_lock); 2124 2125 /* Propagate soft reset to data lane reset */ 2126 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch)); 2127 val |= CHV_PCS_REQ_SOFTRESET_EN; 2128 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val); 2129 2130 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch)); 2131 val |= CHV_PCS_REQ_SOFTRESET_EN; 2132 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val); 2133 2134 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch)); 2135 val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET); 2136 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val); 2137 2138 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch)); 2139 val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET); 2140 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val); 2141 2142 mutex_unlock(&dev_priv->dpio_lock); 2143} 2144 2145static void intel_enable_dp(struct intel_encoder *encoder) 2146{ 2147 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); 2148 struct drm_device *dev = encoder->base.dev; 2149 struct drm_i915_private *dev_priv = dev->dev_private; 2150 uint32_t dp_reg = I915_READ(intel_dp->output_reg); 2151 2152 if (WARN_ON(dp_reg & DP_PORT_EN)) 2153 return; 2154 2155 intel_edp_panel_vdd_on(intel_dp); 2156 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON); 2157 intel_dp_start_link_train(intel_dp); 2158 intel_edp_panel_on(intel_dp); 2159 intel_edp_panel_vdd_off(intel_dp, true); 2160 intel_dp_complete_link_train(intel_dp); 2161 intel_dp_stop_link_train(intel_dp); 2162} 2163 2164static void g4x_enable_dp(struct intel_encoder *encoder) 2165{ 2166 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); 2167 2168 intel_enable_dp(encoder); 2169 intel_edp_backlight_on(intel_dp); 2170} 2171 2172static void vlv_enable_dp(struct intel_encoder *encoder) 2173{ 2174 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); 2175 2176 intel_edp_backlight_on(intel_dp); 2177} 2178 2179static void g4x_pre_enable_dp(struct intel_encoder *encoder) 2180{ 2181 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); 2182 struct intel_digital_port *dport = dp_to_dig_port(intel_dp); 2183 2184 intel_dp_prepare(encoder); 2185 2186 /* Only ilk+ has port A */ 2187 if (dport->port == PORT_A) { 2188 ironlake_set_pll_cpu_edp(intel_dp); 2189 ironlake_edp_pll_on(intel_dp); 2190 } 2191} 2192 2193static void vlv_pre_enable_dp(struct intel_encoder *encoder) 2194{ 2195 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); 2196 struct intel_digital_port *dport = dp_to_dig_port(intel_dp); 2197 struct drm_device *dev = encoder->base.dev; 2198 struct drm_i915_private *dev_priv = dev->dev_private; 2199 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc); 2200 enum dpio_channel port = vlv_dport_to_channel(dport); 2201 int pipe = intel_crtc->pipe; 2202 struct edp_power_seq power_seq; 2203 u32 val; 2204 2205 mutex_lock(&dev_priv->dpio_lock); 2206 2207 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(port)); 2208 val = 0; 2209 if (pipe) 2210 val |= (1<<21); 2211 else 2212 val &= ~(1<<21); 2213 val |= 0x001000c4; 2214 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW8(port), val); 2215 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW14(port), 0x00760018); 2216 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW23(port), 0x00400888); 2217 2218 mutex_unlock(&dev_priv->dpio_lock); 2219 2220 if (is_edp(intel_dp)) { 2221 /* init power sequencer on this pipe and port */ 2222 intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq); 2223 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp, 2224 &power_seq); 2225 } 2226 2227 intel_enable_dp(encoder); 2228 2229 vlv_wait_port_ready(dev_priv, dport); 2230} 2231 2232static void vlv_dp_pre_pll_enable(struct intel_encoder *encoder) 2233{ 2234 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base); 2235 struct drm_device *dev = encoder->base.dev; 2236 struct drm_i915_private *dev_priv = dev->dev_private; 2237 struct intel_crtc *intel_crtc = 2238 to_intel_crtc(encoder->base.crtc); 2239 enum dpio_channel port = vlv_dport_to_channel(dport); 2240 int pipe = intel_crtc->pipe; 2241 2242 intel_dp_prepare(encoder); 2243 2244 /* Program Tx lane resets to default */ 2245 mutex_lock(&dev_priv->dpio_lock); 2246 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port), 2247 DPIO_PCS_TX_LANE2_RESET | 2248 DPIO_PCS_TX_LANE1_RESET); 2249 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port), 2250 DPIO_PCS_CLK_CRI_RXEB_EIOS_EN | 2251 DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN | 2252 (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT) | 2253 DPIO_PCS_CLK_SOFT_RESET); 2254 2255 /* Fix up inter-pair skew failure */ 2256 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW12(port), 0x00750f00); 2257 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW11(port), 0x00001500); 2258 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW14(port), 0x40400000); 2259 mutex_unlock(&dev_priv->dpio_lock); 2260} 2261 2262static void chv_pre_enable_dp(struct intel_encoder *encoder) 2263{ 2264 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); 2265 struct intel_digital_port *dport = dp_to_dig_port(intel_dp); 2266 struct drm_device *dev = encoder->base.dev; 2267 struct drm_i915_private *dev_priv = dev->dev_private; 2268 struct edp_power_seq power_seq; 2269 struct intel_crtc *intel_crtc = 2270 to_intel_crtc(encoder->base.crtc); 2271 enum dpio_channel ch = vlv_dport_to_channel(dport); 2272 int pipe = intel_crtc->pipe; 2273 int data, i; 2274 u32 val; 2275 2276 mutex_lock(&dev_priv->dpio_lock); 2277 2278 /* Deassert soft data lane reset*/ 2279 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch)); 2280 val |= CHV_PCS_REQ_SOFTRESET_EN; 2281 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val); 2282 2283 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch)); 2284 val |= CHV_PCS_REQ_SOFTRESET_EN; 2285 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val); 2286 2287 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch)); 2288 val |= (DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET); 2289 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val); 2290 2291 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch)); 2292 val |= (DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET); 2293 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val); 2294 2295 /* Program Tx lane latency optimal setting*/ 2296 for (i = 0; i < 4; i++) { 2297 /* Set the latency optimal bit */ 2298 data = (i == 1) ? 0x0 : 0x6; 2299 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW11(ch, i), 2300 data << DPIO_FRC_LATENCY_SHFIT); 2301 2302 /* Set the upar bit */ 2303 data = (i == 1) ? 0x0 : 0x1; 2304 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW14(ch, i), 2305 data << DPIO_UPAR_SHIFT); 2306 } 2307 2308 /* Data lane stagger programming */ 2309 /* FIXME: Fix up value only after power analysis */ 2310 2311 mutex_unlock(&dev_priv->dpio_lock); 2312 2313 if (is_edp(intel_dp)) { 2314 /* init power sequencer on this pipe and port */ 2315 intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq); 2316 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp, 2317 &power_seq); 2318 } 2319 2320 intel_enable_dp(encoder); 2321 2322 vlv_wait_port_ready(dev_priv, dport); 2323} 2324 2325static void chv_dp_pre_pll_enable(struct intel_encoder *encoder) 2326{ 2327 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base); 2328 struct drm_device *dev = encoder->base.dev; 2329 struct drm_i915_private *dev_priv = dev->dev_private; 2330 struct intel_crtc *intel_crtc = 2331 to_intel_crtc(encoder->base.crtc); 2332 enum dpio_channel ch = vlv_dport_to_channel(dport); 2333 enum pipe pipe = intel_crtc->pipe; 2334 u32 val; 2335 2336 intel_dp_prepare(encoder); 2337 2338 mutex_lock(&dev_priv->dpio_lock); 2339 2340 /* program left/right clock distribution */ 2341 if (pipe != PIPE_B) { 2342 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0); 2343 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK); 2344 if (ch == DPIO_CH0) 2345 val |= CHV_BUFLEFTENA1_FORCE; 2346 if (ch == DPIO_CH1) 2347 val |= CHV_BUFRIGHTENA1_FORCE; 2348 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val); 2349 } else { 2350 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1); 2351 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK); 2352 if (ch == DPIO_CH0) 2353 val |= CHV_BUFLEFTENA2_FORCE; 2354 if (ch == DPIO_CH1) 2355 val |= CHV_BUFRIGHTENA2_FORCE; 2356 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val); 2357 } 2358 2359 /* program clock channel usage */ 2360 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(ch)); 2361 val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE; 2362 if (pipe != PIPE_B) 2363 val &= ~CHV_PCS_USEDCLKCHANNEL; 2364 else 2365 val |= CHV_PCS_USEDCLKCHANNEL; 2366 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW8(ch), val); 2367 2368 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW8(ch)); 2369 val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE; 2370 if (pipe != PIPE_B) 2371 val &= ~CHV_PCS_USEDCLKCHANNEL; 2372 else 2373 val |= CHV_PCS_USEDCLKCHANNEL; 2374 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW8(ch), val); 2375 2376 /* 2377 * This a a bit weird since generally CL 2378 * matches the pipe, but here we need to 2379 * pick the CL based on the port. 2380 */ 2381 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW19(ch)); 2382 if (pipe != PIPE_B) 2383 val &= ~CHV_CMN_USEDCLKCHANNEL; 2384 else 2385 val |= CHV_CMN_USEDCLKCHANNEL; 2386 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW19(ch), val); 2387 2388 mutex_unlock(&dev_priv->dpio_lock); 2389} 2390 2391/* 2392 * Native read with retry for link status and receiver capability reads for 2393 * cases where the sink may still be asleep. 2394 * 2395 * Sinks are *supposed* to come up within 1ms from an off state, but we're also 2396 * supposed to retry 3 times per the spec. 2397 */ 2398static ssize_t 2399intel_dp_dpcd_read_wake(struct drm_dp_aux *aux, unsigned int offset, 2400 void *buffer, size_t size) 2401{ 2402 ssize_t ret; 2403 int i; 2404 2405 for (i = 0; i < 3; i++) { 2406 ret = drm_dp_dpcd_read(aux, offset, buffer, size); 2407 if (ret == size) 2408 return ret; 2409 msleep(1); 2410 } 2411 2412 return ret; 2413} 2414 2415/* 2416 * Fetch AUX CH registers 0x202 - 0x207 which contain 2417 * link status information 2418 */ 2419static bool 2420intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE]) 2421{ 2422 return intel_dp_dpcd_read_wake(&intel_dp->aux, 2423 DP_LANE0_1_STATUS, 2424 link_status, 2425 DP_LINK_STATUS_SIZE) == DP_LINK_STATUS_SIZE; 2426} 2427 2428/* These are source-specific values. */ 2429static uint8_t 2430intel_dp_voltage_max(struct intel_dp *intel_dp) 2431{ 2432 struct drm_device *dev = intel_dp_to_dev(intel_dp); 2433 enum port port = dp_to_dig_port(intel_dp)->port; 2434 2435 if (IS_VALLEYVIEW(dev)) 2436 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3; 2437 else if (IS_GEN7(dev) && port == PORT_A) 2438 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2; 2439 else if (HAS_PCH_CPT(dev) && port != PORT_A) 2440 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3; 2441 else 2442 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2; 2443} 2444 2445static uint8_t 2446intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing) 2447{ 2448 struct drm_device *dev = intel_dp_to_dev(intel_dp); 2449 enum port port = dp_to_dig_port(intel_dp)->port; 2450 2451 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { 2452 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) { 2453 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: 2454 return DP_TRAIN_PRE_EMPH_LEVEL_3; 2455 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: 2456 return DP_TRAIN_PRE_EMPH_LEVEL_2; 2457 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: 2458 return DP_TRAIN_PRE_EMPH_LEVEL_1; 2459 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3: 2460 default: 2461 return DP_TRAIN_PRE_EMPH_LEVEL_0; 2462 } 2463 } else if (IS_VALLEYVIEW(dev)) { 2464 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) { 2465 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: 2466 return DP_TRAIN_PRE_EMPH_LEVEL_3; 2467 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: 2468 return DP_TRAIN_PRE_EMPH_LEVEL_2; 2469 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: 2470 return DP_TRAIN_PRE_EMPH_LEVEL_1; 2471 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3: 2472 default: 2473 return DP_TRAIN_PRE_EMPH_LEVEL_0; 2474 } 2475 } else if (IS_GEN7(dev) && port == PORT_A) { 2476 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) { 2477 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: 2478 return DP_TRAIN_PRE_EMPH_LEVEL_2; 2479 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: 2480 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: 2481 return DP_TRAIN_PRE_EMPH_LEVEL_1; 2482 default: 2483 return DP_TRAIN_PRE_EMPH_LEVEL_0; 2484 } 2485 } else { 2486 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) { 2487 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: 2488 return DP_TRAIN_PRE_EMPH_LEVEL_2; 2489 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: 2490 return DP_TRAIN_PRE_EMPH_LEVEL_2; 2491 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: 2492 return DP_TRAIN_PRE_EMPH_LEVEL_1; 2493 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3: 2494 default: 2495 return DP_TRAIN_PRE_EMPH_LEVEL_0; 2496 } 2497 } 2498} 2499 2500static uint32_t intel_vlv_signal_levels(struct intel_dp *intel_dp) 2501{ 2502 struct drm_device *dev = intel_dp_to_dev(intel_dp); 2503 struct drm_i915_private *dev_priv = dev->dev_private; 2504 struct intel_digital_port *dport = dp_to_dig_port(intel_dp); 2505 struct intel_crtc *intel_crtc = 2506 to_intel_crtc(dport->base.base.crtc); 2507 unsigned long demph_reg_value, preemph_reg_value, 2508 uniqtranscale_reg_value; 2509 uint8_t train_set = intel_dp->train_set[0]; 2510 enum dpio_channel port = vlv_dport_to_channel(dport); 2511 int pipe = intel_crtc->pipe; 2512 2513 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) { 2514 case DP_TRAIN_PRE_EMPH_LEVEL_0: 2515 preemph_reg_value = 0x0004000; 2516 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { 2517 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: 2518 demph_reg_value = 0x2B405555; 2519 uniqtranscale_reg_value = 0x552AB83A; 2520 break; 2521 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: 2522 demph_reg_value = 0x2B404040; 2523 uniqtranscale_reg_value = 0x5548B83A; 2524 break; 2525 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: 2526 demph_reg_value = 0x2B245555; 2527 uniqtranscale_reg_value = 0x5560B83A; 2528 break; 2529 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3: 2530 demph_reg_value = 0x2B405555; 2531 uniqtranscale_reg_value = 0x5598DA3A; 2532 break; 2533 default: 2534 return 0; 2535 } 2536 break; 2537 case DP_TRAIN_PRE_EMPH_LEVEL_1: 2538 preemph_reg_value = 0x0002000; 2539 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { 2540 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: 2541 demph_reg_value = 0x2B404040; 2542 uniqtranscale_reg_value = 0x5552B83A; 2543 break; 2544 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: 2545 demph_reg_value = 0x2B404848; 2546 uniqtranscale_reg_value = 0x5580B83A; 2547 break; 2548 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: 2549 demph_reg_value = 0x2B404040; 2550 uniqtranscale_reg_value = 0x55ADDA3A; 2551 break; 2552 default: 2553 return 0; 2554 } 2555 break; 2556 case DP_TRAIN_PRE_EMPH_LEVEL_2: 2557 preemph_reg_value = 0x0000000; 2558 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { 2559 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: 2560 demph_reg_value = 0x2B305555; 2561 uniqtranscale_reg_value = 0x5570B83A; 2562 break; 2563 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: 2564 demph_reg_value = 0x2B2B4040; 2565 uniqtranscale_reg_value = 0x55ADDA3A; 2566 break; 2567 default: 2568 return 0; 2569 } 2570 break; 2571 case DP_TRAIN_PRE_EMPH_LEVEL_3: 2572 preemph_reg_value = 0x0006000; 2573 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { 2574 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: 2575 demph_reg_value = 0x1B405555; 2576 uniqtranscale_reg_value = 0x55ADDA3A; 2577 break; 2578 default: 2579 return 0; 2580 } 2581 break; 2582 default: 2583 return 0; 2584 } 2585 2586 mutex_lock(&dev_priv->dpio_lock); 2587 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x00000000); 2588 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW4(port), demph_reg_value); 2589 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(port), 2590 uniqtranscale_reg_value); 2591 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(port), 0x0C782040); 2592 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW11(port), 0x00030000); 2593 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), preemph_reg_value); 2594 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x80000000); 2595 mutex_unlock(&dev_priv->dpio_lock); 2596 2597 return 0; 2598} 2599 2600static uint32_t intel_chv_signal_levels(struct intel_dp *intel_dp) 2601{ 2602 struct drm_device *dev = intel_dp_to_dev(intel_dp); 2603 struct drm_i915_private *dev_priv = dev->dev_private; 2604 struct intel_digital_port *dport = dp_to_dig_port(intel_dp); 2605 struct intel_crtc *intel_crtc = to_intel_crtc(dport->base.base.crtc); 2606 u32 deemph_reg_value, margin_reg_value, val; 2607 uint8_t train_set = intel_dp->train_set[0]; 2608 enum dpio_channel ch = vlv_dport_to_channel(dport); 2609 enum pipe pipe = intel_crtc->pipe; 2610 int i; 2611 2612 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) { 2613 case DP_TRAIN_PRE_EMPH_LEVEL_0: 2614 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { 2615 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: 2616 deemph_reg_value = 128; 2617 margin_reg_value = 52; 2618 break; 2619 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: 2620 deemph_reg_value = 128; 2621 margin_reg_value = 77; 2622 break; 2623 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: 2624 deemph_reg_value = 128; 2625 margin_reg_value = 102; 2626 break; 2627 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3: 2628 deemph_reg_value = 128; 2629 margin_reg_value = 154; 2630 /* FIXME extra to set for 1200 */ 2631 break; 2632 default: 2633 return 0; 2634 } 2635 break; 2636 case DP_TRAIN_PRE_EMPH_LEVEL_1: 2637 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { 2638 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: 2639 deemph_reg_value = 85; 2640 margin_reg_value = 78; 2641 break; 2642 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: 2643 deemph_reg_value = 85; 2644 margin_reg_value = 116; 2645 break; 2646 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: 2647 deemph_reg_value = 85; 2648 margin_reg_value = 154; 2649 break; 2650 default: 2651 return 0; 2652 } 2653 break; 2654 case DP_TRAIN_PRE_EMPH_LEVEL_2: 2655 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { 2656 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: 2657 deemph_reg_value = 64; 2658 margin_reg_value = 104; 2659 break; 2660 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: 2661 deemph_reg_value = 64; 2662 margin_reg_value = 154; 2663 break; 2664 default: 2665 return 0; 2666 } 2667 break; 2668 case DP_TRAIN_PRE_EMPH_LEVEL_3: 2669 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { 2670 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: 2671 deemph_reg_value = 43; 2672 margin_reg_value = 154; 2673 break; 2674 default: 2675 return 0; 2676 } 2677 break; 2678 default: 2679 return 0; 2680 } 2681 2682 mutex_lock(&dev_priv->dpio_lock); 2683 2684 /* Clear calc init */ 2685 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch)); 2686 val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3); 2687 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val); 2688 2689 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch)); 2690 val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3); 2691 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val); 2692 2693 /* Program swing deemph */ 2694 for (i = 0; i < 4; i++) { 2695 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW4(ch, i)); 2696 val &= ~DPIO_SWING_DEEMPH9P5_MASK; 2697 val |= deemph_reg_value << DPIO_SWING_DEEMPH9P5_SHIFT; 2698 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW4(ch, i), val); 2699 } 2700 2701 /* Program swing margin */ 2702 for (i = 0; i < 4; i++) { 2703 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW2(ch, i)); 2704 val &= ~DPIO_SWING_MARGIN000_MASK; 2705 val |= margin_reg_value << DPIO_SWING_MARGIN000_SHIFT; 2706 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW2(ch, i), val); 2707 } 2708 2709 /* Disable unique transition scale */ 2710 for (i = 0; i < 4; i++) { 2711 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW3(ch, i)); 2712 val &= ~DPIO_TX_UNIQ_TRANS_SCALE_EN; 2713 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW3(ch, i), val); 2714 } 2715 2716 if (((train_set & DP_TRAIN_PRE_EMPHASIS_MASK) 2717 == DP_TRAIN_PRE_EMPH_LEVEL_0) && 2718 ((train_set & DP_TRAIN_VOLTAGE_SWING_MASK) 2719 == DP_TRAIN_VOLTAGE_SWING_LEVEL_3)) { 2720 2721 /* 2722 * The document said it needs to set bit 27 for ch0 and bit 26 2723 * for ch1. Might be a typo in the doc. 2724 * For now, for this unique transition scale selection, set bit 2725 * 27 for ch0 and ch1. 2726 */ 2727 for (i = 0; i < 4; i++) { 2728 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW3(ch, i)); 2729 val |= DPIO_TX_UNIQ_TRANS_SCALE_EN; 2730 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW3(ch, i), val); 2731 } 2732 2733 for (i = 0; i < 4; i++) { 2734 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW2(ch, i)); 2735 val &= ~(0xff << DPIO_UNIQ_TRANS_SCALE_SHIFT); 2736 val |= (0x9a << DPIO_UNIQ_TRANS_SCALE_SHIFT); 2737 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW2(ch, i), val); 2738 } 2739 } 2740 2741 /* Start swing calculation */ 2742 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch)); 2743 val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3; 2744 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val); 2745 2746 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch)); 2747 val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3; 2748 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val); 2749 2750 /* LRC Bypass */ 2751 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW30); 2752 val |= DPIO_LRC_BYPASS; 2753 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW30, val); 2754 2755 mutex_unlock(&dev_priv->dpio_lock); 2756 2757 return 0; 2758} 2759 2760static void 2761intel_get_adjust_train(struct intel_dp *intel_dp, 2762 const uint8_t link_status[DP_LINK_STATUS_SIZE]) 2763{ 2764 uint8_t v = 0; 2765 uint8_t p = 0; 2766 int lane; 2767 uint8_t voltage_max; 2768 uint8_t preemph_max; 2769 2770 for (lane = 0; lane < intel_dp->lane_count; lane++) { 2771 uint8_t this_v = drm_dp_get_adjust_request_voltage(link_status, lane); 2772 uint8_t this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane); 2773 2774 if (this_v > v) 2775 v = this_v; 2776 if (this_p > p) 2777 p = this_p; 2778 } 2779 2780 voltage_max = intel_dp_voltage_max(intel_dp); 2781 if (v >= voltage_max) 2782 v = voltage_max | DP_TRAIN_MAX_SWING_REACHED; 2783 2784 preemph_max = intel_dp_pre_emphasis_max(intel_dp, v); 2785 if (p >= preemph_max) 2786 p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED; 2787 2788 for (lane = 0; lane < 4; lane++) 2789 intel_dp->train_set[lane] = v | p; 2790} 2791 2792static uint32_t 2793intel_gen4_signal_levels(uint8_t train_set) 2794{ 2795 uint32_t signal_levels = 0; 2796 2797 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { 2798 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: 2799 default: 2800 signal_levels |= DP_VOLTAGE_0_4; 2801 break; 2802 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: 2803 signal_levels |= DP_VOLTAGE_0_6; 2804 break; 2805 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: 2806 signal_levels |= DP_VOLTAGE_0_8; 2807 break; 2808 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3: 2809 signal_levels |= DP_VOLTAGE_1_2; 2810 break; 2811 } 2812 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) { 2813 case DP_TRAIN_PRE_EMPH_LEVEL_0: 2814 default: 2815 signal_levels |= DP_PRE_EMPHASIS_0; 2816 break; 2817 case DP_TRAIN_PRE_EMPH_LEVEL_1: 2818 signal_levels |= DP_PRE_EMPHASIS_3_5; 2819 break; 2820 case DP_TRAIN_PRE_EMPH_LEVEL_2: 2821 signal_levels |= DP_PRE_EMPHASIS_6; 2822 break; 2823 case DP_TRAIN_PRE_EMPH_LEVEL_3: 2824 signal_levels |= DP_PRE_EMPHASIS_9_5; 2825 break; 2826 } 2827 return signal_levels; 2828} 2829 2830/* Gen6's DP voltage swing and pre-emphasis control */ 2831static uint32_t 2832intel_gen6_edp_signal_levels(uint8_t train_set) 2833{ 2834 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK | 2835 DP_TRAIN_PRE_EMPHASIS_MASK); 2836 switch (signal_levels) { 2837 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0: 2838 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0: 2839 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B; 2840 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1: 2841 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B; 2842 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2: 2843 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2: 2844 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B; 2845 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1: 2846 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1: 2847 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B; 2848 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0: 2849 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0: 2850 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B; 2851 default: 2852 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:" 2853 "0x%x\n", signal_levels); 2854 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B; 2855 } 2856} 2857 2858/* Gen7's DP voltage swing and pre-emphasis control */ 2859static uint32_t 2860intel_gen7_edp_signal_levels(uint8_t train_set) 2861{ 2862 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK | 2863 DP_TRAIN_PRE_EMPHASIS_MASK); 2864 switch (signal_levels) { 2865 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0: 2866 return EDP_LINK_TRAIN_400MV_0DB_IVB; 2867 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1: 2868 return EDP_LINK_TRAIN_400MV_3_5DB_IVB; 2869 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2: 2870 return EDP_LINK_TRAIN_400MV_6DB_IVB; 2871 2872 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0: 2873 return EDP_LINK_TRAIN_600MV_0DB_IVB; 2874 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1: 2875 return EDP_LINK_TRAIN_600MV_3_5DB_IVB; 2876 2877 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0: 2878 return EDP_LINK_TRAIN_800MV_0DB_IVB; 2879 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1: 2880 return EDP_LINK_TRAIN_800MV_3_5DB_IVB; 2881 2882 default: 2883 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:" 2884 "0x%x\n", signal_levels); 2885 return EDP_LINK_TRAIN_500MV_0DB_IVB; 2886 } 2887} 2888 2889/* Gen7.5's (HSW) DP voltage swing and pre-emphasis control */ 2890static uint32_t 2891intel_hsw_signal_levels(uint8_t train_set) 2892{ 2893 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK | 2894 DP_TRAIN_PRE_EMPHASIS_MASK); 2895 switch (signal_levels) { 2896 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0: 2897 return DDI_BUF_TRANS_SELECT(0); 2898 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1: 2899 return DDI_BUF_TRANS_SELECT(1); 2900 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2: 2901 return DDI_BUF_TRANS_SELECT(2); 2902 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_3: 2903 return DDI_BUF_TRANS_SELECT(3); 2904 2905 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0: 2906 return DDI_BUF_TRANS_SELECT(4); 2907 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1: 2908 return DDI_BUF_TRANS_SELECT(5); 2909 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2: 2910 return DDI_BUF_TRANS_SELECT(6); 2911 2912 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0: 2913 return DDI_BUF_TRANS_SELECT(7); 2914 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1: 2915 return DDI_BUF_TRANS_SELECT(8); 2916 default: 2917 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:" 2918 "0x%x\n", signal_levels); 2919 return DDI_BUF_TRANS_SELECT(0); 2920 } 2921} 2922 2923/* Properly updates "DP" with the correct signal levels. */ 2924static void 2925intel_dp_set_signal_levels(struct intel_dp *intel_dp, uint32_t *DP) 2926{ 2927 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 2928 enum port port = intel_dig_port->port; 2929 struct drm_device *dev = intel_dig_port->base.base.dev; 2930 uint32_t signal_levels, mask; 2931 uint8_t train_set = intel_dp->train_set[0]; 2932 2933 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { 2934 signal_levels = intel_hsw_signal_levels(train_set); 2935 mask = DDI_BUF_EMP_MASK; 2936 } else if (IS_CHERRYVIEW(dev)) { 2937 signal_levels = intel_chv_signal_levels(intel_dp); 2938 mask = 0; 2939 } else if (IS_VALLEYVIEW(dev)) { 2940 signal_levels = intel_vlv_signal_levels(intel_dp); 2941 mask = 0; 2942 } else if (IS_GEN7(dev) && port == PORT_A) { 2943 signal_levels = intel_gen7_edp_signal_levels(train_set); 2944 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_IVB; 2945 } else if (IS_GEN6(dev) && port == PORT_A) { 2946 signal_levels = intel_gen6_edp_signal_levels(train_set); 2947 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB; 2948 } else { 2949 signal_levels = intel_gen4_signal_levels(train_set); 2950 mask = DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK; 2951 } 2952 2953 DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels); 2954 2955 *DP = (*DP & ~mask) | signal_levels; 2956} 2957 2958static bool 2959intel_dp_set_link_train(struct intel_dp *intel_dp, 2960 uint32_t *DP, 2961 uint8_t dp_train_pat) 2962{ 2963 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 2964 struct drm_device *dev = intel_dig_port->base.base.dev; 2965 struct drm_i915_private *dev_priv = dev->dev_private; 2966 enum port port = intel_dig_port->port; 2967 uint8_t buf[sizeof(intel_dp->train_set) + 1]; 2968 int ret, len; 2969 2970 if (HAS_DDI(dev)) { 2971 uint32_t temp = I915_READ(DP_TP_CTL(port)); 2972 2973 if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE) 2974 temp |= DP_TP_CTL_SCRAMBLE_DISABLE; 2975 else 2976 temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE; 2977 2978 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK; 2979 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) { 2980 case DP_TRAINING_PATTERN_DISABLE: 2981 temp |= DP_TP_CTL_LINK_TRAIN_NORMAL; 2982 2983 break; 2984 case DP_TRAINING_PATTERN_1: 2985 temp |= DP_TP_CTL_LINK_TRAIN_PAT1; 2986 break; 2987 case DP_TRAINING_PATTERN_2: 2988 temp |= DP_TP_CTL_LINK_TRAIN_PAT2; 2989 break; 2990 case DP_TRAINING_PATTERN_3: 2991 temp |= DP_TP_CTL_LINK_TRAIN_PAT3; 2992 break; 2993 } 2994 I915_WRITE(DP_TP_CTL(port), temp); 2995 2996 } else if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) { 2997 *DP &= ~DP_LINK_TRAIN_MASK_CPT; 2998 2999 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) { 3000 case DP_TRAINING_PATTERN_DISABLE: 3001 *DP |= DP_LINK_TRAIN_OFF_CPT; 3002 break; 3003 case DP_TRAINING_PATTERN_1: 3004 *DP |= DP_LINK_TRAIN_PAT_1_CPT; 3005 break; 3006 case DP_TRAINING_PATTERN_2: 3007 *DP |= DP_LINK_TRAIN_PAT_2_CPT; 3008 break; 3009 case DP_TRAINING_PATTERN_3: 3010 DRM_ERROR("DP training pattern 3 not supported\n"); 3011 *DP |= DP_LINK_TRAIN_PAT_2_CPT; 3012 break; 3013 } 3014 3015 } else { 3016 if (IS_CHERRYVIEW(dev)) 3017 *DP &= ~DP_LINK_TRAIN_MASK_CHV; 3018 else 3019 *DP &= ~DP_LINK_TRAIN_MASK; 3020 3021 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) { 3022 case DP_TRAINING_PATTERN_DISABLE: 3023 *DP |= DP_LINK_TRAIN_OFF; 3024 break; 3025 case DP_TRAINING_PATTERN_1: 3026 *DP |= DP_LINK_TRAIN_PAT_1; 3027 break; 3028 case DP_TRAINING_PATTERN_2: 3029 *DP |= DP_LINK_TRAIN_PAT_2; 3030 break; 3031 case DP_TRAINING_PATTERN_3: 3032 if (IS_CHERRYVIEW(dev)) { 3033 *DP |= DP_LINK_TRAIN_PAT_3_CHV; 3034 } else { 3035 DRM_ERROR("DP training pattern 3 not supported\n"); 3036 *DP |= DP_LINK_TRAIN_PAT_2; 3037 } 3038 break; 3039 } 3040 } 3041 3042 I915_WRITE(intel_dp->output_reg, *DP); 3043 POSTING_READ(intel_dp->output_reg); 3044 3045 buf[0] = dp_train_pat; 3046 if ((dp_train_pat & DP_TRAINING_PATTERN_MASK) == 3047 DP_TRAINING_PATTERN_DISABLE) { 3048 /* don't write DP_TRAINING_LANEx_SET on disable */ 3049 len = 1; 3050 } else { 3051 /* DP_TRAINING_LANEx_SET follow DP_TRAINING_PATTERN_SET */ 3052 memcpy(buf + 1, intel_dp->train_set, intel_dp->lane_count); 3053 len = intel_dp->lane_count + 1; 3054 } 3055 3056 ret = drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_PATTERN_SET, 3057 buf, len); 3058 3059 return ret == len; 3060} 3061 3062static bool 3063intel_dp_reset_link_train(struct intel_dp *intel_dp, uint32_t *DP, 3064 uint8_t dp_train_pat) 3065{ 3066 memset(intel_dp->train_set, 0, sizeof(intel_dp->train_set)); 3067 intel_dp_set_signal_levels(intel_dp, DP); 3068 return intel_dp_set_link_train(intel_dp, DP, dp_train_pat); 3069} 3070 3071static bool 3072intel_dp_update_link_train(struct intel_dp *intel_dp, uint32_t *DP, 3073 const uint8_t link_status[DP_LINK_STATUS_SIZE]) 3074{ 3075 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 3076 struct drm_device *dev = intel_dig_port->base.base.dev; 3077 struct drm_i915_private *dev_priv = dev->dev_private; 3078 int ret; 3079 3080 intel_get_adjust_train(intel_dp, link_status); 3081 intel_dp_set_signal_levels(intel_dp, DP); 3082 3083 I915_WRITE(intel_dp->output_reg, *DP); 3084 POSTING_READ(intel_dp->output_reg); 3085 3086 ret = drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_LANE0_SET, 3087 intel_dp->train_set, intel_dp->lane_count); 3088 3089 return ret == intel_dp->lane_count; 3090} 3091 3092static void intel_dp_set_idle_link_train(struct intel_dp *intel_dp) 3093{ 3094 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 3095 struct drm_device *dev = intel_dig_port->base.base.dev; 3096 struct drm_i915_private *dev_priv = dev->dev_private; 3097 enum port port = intel_dig_port->port; 3098 uint32_t val; 3099 3100 if (!HAS_DDI(dev)) 3101 return; 3102 3103 val = I915_READ(DP_TP_CTL(port)); 3104 val &= ~DP_TP_CTL_LINK_TRAIN_MASK; 3105 val |= DP_TP_CTL_LINK_TRAIN_IDLE; 3106 I915_WRITE(DP_TP_CTL(port), val); 3107 3108 /* 3109 * On PORT_A we can have only eDP in SST mode. There the only reason 3110 * we need to set idle transmission mode is to work around a HW issue 3111 * where we enable the pipe while not in idle link-training mode. 3112 * In this case there is requirement to wait for a minimum number of 3113 * idle patterns to be sent. 3114 */ 3115 if (port == PORT_A) 3116 return; 3117 3118 if (wait_for((I915_READ(DP_TP_STATUS(port)) & DP_TP_STATUS_IDLE_DONE), 3119 1)) 3120 DRM_ERROR("Timed out waiting for DP idle patterns\n"); 3121} 3122 3123/* Enable corresponding port and start training pattern 1 */ 3124void 3125intel_dp_start_link_train(struct intel_dp *intel_dp) 3126{ 3127 struct drm_encoder *encoder = &dp_to_dig_port(intel_dp)->base.base; 3128 struct drm_device *dev = encoder->dev; 3129 int i; 3130 uint8_t voltage; 3131 int voltage_tries, loop_tries; 3132 uint32_t DP = intel_dp->DP; 3133 uint8_t link_config[2]; 3134 3135 if (HAS_DDI(dev)) 3136 intel_ddi_prepare_link_retrain(encoder); 3137 3138 /* Write the link configuration data */ 3139 link_config[0] = intel_dp->link_bw; 3140 link_config[1] = intel_dp->lane_count; 3141 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd)) 3142 link_config[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN; 3143 drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_BW_SET, link_config, 2); 3144 3145 link_config[0] = 0; 3146 link_config[1] = DP_SET_ANSI_8B10B; 3147 drm_dp_dpcd_write(&intel_dp->aux, DP_DOWNSPREAD_CTRL, link_config, 2); 3148 3149 DP |= DP_PORT_EN; 3150 3151 /* clock recovery */ 3152 if (!intel_dp_reset_link_train(intel_dp, &DP, 3153 DP_TRAINING_PATTERN_1 | 3154 DP_LINK_SCRAMBLING_DISABLE)) { 3155 DRM_ERROR("failed to enable link training\n"); 3156 return; 3157 } 3158 3159 voltage = 0xff; 3160 voltage_tries = 0; 3161 loop_tries = 0; 3162 for (;;) { 3163 uint8_t link_status[DP_LINK_STATUS_SIZE]; 3164 3165 drm_dp_link_train_clock_recovery_delay(intel_dp->dpcd); 3166 if (!intel_dp_get_link_status(intel_dp, link_status)) { 3167 DRM_ERROR("failed to get link status\n"); 3168 break; 3169 } 3170 3171 if (drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) { 3172 DRM_DEBUG_KMS("clock recovery OK\n"); 3173 break; 3174 } 3175 3176 /* Check to see if we've tried the max voltage */ 3177 for (i = 0; i < intel_dp->lane_count; i++) 3178 if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0) 3179 break; 3180 if (i == intel_dp->lane_count) { 3181 ++loop_tries; 3182 if (loop_tries == 5) { 3183 DRM_ERROR("too many full retries, give up\n"); 3184 break; 3185 } 3186 intel_dp_reset_link_train(intel_dp, &DP, 3187 DP_TRAINING_PATTERN_1 | 3188 DP_LINK_SCRAMBLING_DISABLE); 3189 voltage_tries = 0; 3190 continue; 3191 } 3192 3193 /* Check to see if we've tried the same voltage 5 times */ 3194 if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) { 3195 ++voltage_tries; 3196 if (voltage_tries == 5) { 3197 DRM_ERROR("too many voltage retries, give up\n"); 3198 break; 3199 } 3200 } else 3201 voltage_tries = 0; 3202 voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK; 3203 3204 /* Update training set as requested by target */ 3205 if (!intel_dp_update_link_train(intel_dp, &DP, link_status)) { 3206 DRM_ERROR("failed to update link training\n"); 3207 break; 3208 } 3209 } 3210 3211 intel_dp->DP = DP; 3212} 3213 3214void 3215intel_dp_complete_link_train(struct intel_dp *intel_dp) 3216{ 3217 bool channel_eq = false; 3218 int tries, cr_tries; 3219 uint32_t DP = intel_dp->DP; 3220 uint32_t training_pattern = DP_TRAINING_PATTERN_2; 3221 3222 /* Training Pattern 3 for HBR2 ot 1.2 devices that support it*/ 3223 if (intel_dp->link_bw == DP_LINK_BW_5_4 || intel_dp->use_tps3) 3224 training_pattern = DP_TRAINING_PATTERN_3; 3225 3226 /* channel equalization */ 3227 if (!intel_dp_set_link_train(intel_dp, &DP, 3228 training_pattern | 3229 DP_LINK_SCRAMBLING_DISABLE)) { 3230 DRM_ERROR("failed to start channel equalization\n"); 3231 return; 3232 } 3233 3234 tries = 0; 3235 cr_tries = 0; 3236 channel_eq = false; 3237 for (;;) { 3238 uint8_t link_status[DP_LINK_STATUS_SIZE]; 3239 3240 if (cr_tries > 5) { 3241 DRM_ERROR("failed to train DP, aborting\n"); 3242 break; 3243 } 3244 3245 drm_dp_link_train_channel_eq_delay(intel_dp->dpcd); 3246 if (!intel_dp_get_link_status(intel_dp, link_status)) { 3247 DRM_ERROR("failed to get link status\n"); 3248 break; 3249 } 3250 3251 /* Make sure clock is still ok */ 3252 if (!drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) { 3253 intel_dp_start_link_train(intel_dp); 3254 intel_dp_set_link_train(intel_dp, &DP, 3255 training_pattern | 3256 DP_LINK_SCRAMBLING_DISABLE); 3257 cr_tries++; 3258 continue; 3259 } 3260 3261 if (drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) { 3262 channel_eq = true; 3263 break; 3264 } 3265 3266 /* Try 5 times, then try clock recovery if that fails */ 3267 if (tries > 5) { 3268 intel_dp_link_down(intel_dp); 3269 intel_dp_start_link_train(intel_dp); 3270 intel_dp_set_link_train(intel_dp, &DP, 3271 training_pattern | 3272 DP_LINK_SCRAMBLING_DISABLE); 3273 tries = 0; 3274 cr_tries++; 3275 continue; 3276 } 3277 3278 /* Update training set as requested by target */ 3279 if (!intel_dp_update_link_train(intel_dp, &DP, link_status)) { 3280 DRM_ERROR("failed to update link training\n"); 3281 break; 3282 } 3283 ++tries; 3284 } 3285 3286 intel_dp_set_idle_link_train(intel_dp); 3287 3288 intel_dp->DP = DP; 3289 3290 if (channel_eq) 3291 DRM_DEBUG_KMS("Channel EQ done. DP Training successful\n"); 3292 3293} 3294 3295void intel_dp_stop_link_train(struct intel_dp *intel_dp) 3296{ 3297 intel_dp_set_link_train(intel_dp, &intel_dp->DP, 3298 DP_TRAINING_PATTERN_DISABLE); 3299} 3300 3301static void 3302intel_dp_link_down(struct intel_dp *intel_dp) 3303{ 3304 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 3305 enum port port = intel_dig_port->port; 3306 struct drm_device *dev = intel_dig_port->base.base.dev; 3307 struct drm_i915_private *dev_priv = dev->dev_private; 3308 struct intel_crtc *intel_crtc = 3309 to_intel_crtc(intel_dig_port->base.base.crtc); 3310 uint32_t DP = intel_dp->DP; 3311 3312 if (WARN_ON(HAS_DDI(dev))) 3313 return; 3314 3315 if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0)) 3316 return; 3317 3318 DRM_DEBUG_KMS("\n"); 3319 3320 if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) { 3321 DP &= ~DP_LINK_TRAIN_MASK_CPT; 3322 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT); 3323 } else { 3324 if (IS_CHERRYVIEW(dev)) 3325 DP &= ~DP_LINK_TRAIN_MASK_CHV; 3326 else 3327 DP &= ~DP_LINK_TRAIN_MASK; 3328 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE); 3329 } 3330 POSTING_READ(intel_dp->output_reg); 3331 3332 if (HAS_PCH_IBX(dev) && 3333 I915_READ(intel_dp->output_reg) & DP_PIPEB_SELECT) { 3334 struct drm_crtc *crtc = intel_dig_port->base.base.crtc; 3335 3336 /* Hardware workaround: leaving our transcoder select 3337 * set to transcoder B while it's off will prevent the 3338 * corresponding HDMI output on transcoder A. 3339 * 3340 * Combine this with another hardware workaround: 3341 * transcoder select bit can only be cleared while the 3342 * port is enabled. 3343 */ 3344 DP &= ~DP_PIPEB_SELECT; 3345 I915_WRITE(intel_dp->output_reg, DP); 3346 3347 /* Changes to enable or select take place the vblank 3348 * after being written. 3349 */ 3350 if (WARN_ON(crtc == NULL)) { 3351 /* We should never try to disable a port without a crtc 3352 * attached. For paranoia keep the code around for a 3353 * bit. */ 3354 POSTING_READ(intel_dp->output_reg); 3355 msleep(50); 3356 } else 3357 intel_wait_for_vblank(dev, intel_crtc->pipe); 3358 } 3359 3360 DP &= ~DP_AUDIO_OUTPUT_ENABLE; 3361 I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN); 3362 POSTING_READ(intel_dp->output_reg); 3363 msleep(intel_dp->panel_power_down_delay); 3364} 3365 3366static bool 3367intel_dp_get_dpcd(struct intel_dp *intel_dp) 3368{ 3369 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 3370 struct drm_device *dev = dig_port->base.base.dev; 3371 struct drm_i915_private *dev_priv = dev->dev_private; 3372 3373 if (intel_dp_dpcd_read_wake(&intel_dp->aux, 0x000, intel_dp->dpcd, 3374 sizeof(intel_dp->dpcd)) < 0) 3375 return false; /* aux transfer failed */ 3376 3377 DRM_DEBUG_KMS("DPCD: %*ph\n", (int) sizeof(intel_dp->dpcd), intel_dp->dpcd); 3378 3379 if (intel_dp->dpcd[DP_DPCD_REV] == 0) 3380 return false; /* DPCD not present */ 3381 3382 /* Check if the panel supports PSR */ 3383 memset(intel_dp->psr_dpcd, 0, sizeof(intel_dp->psr_dpcd)); 3384 if (is_edp(intel_dp)) { 3385 intel_dp_dpcd_read_wake(&intel_dp->aux, DP_PSR_SUPPORT, 3386 intel_dp->psr_dpcd, 3387 sizeof(intel_dp->psr_dpcd)); 3388 if (intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED) { 3389 dev_priv->psr.sink_support = true; 3390 DRM_DEBUG_KMS("Detected EDP PSR Panel.\n"); 3391 } 3392 } 3393 3394 /* Training Pattern 3 support */ 3395 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x12 && 3396 intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_TPS3_SUPPORTED) { 3397 intel_dp->use_tps3 = true; 3398 DRM_DEBUG_KMS("Displayport TPS3 supported"); 3399 } else 3400 intel_dp->use_tps3 = false; 3401 3402 if (!(intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] & 3403 DP_DWN_STRM_PORT_PRESENT)) 3404 return true; /* native DP sink */ 3405 3406 if (intel_dp->dpcd[DP_DPCD_REV] == 0x10) 3407 return true; /* no per-port downstream info */ 3408 3409 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_DOWNSTREAM_PORT_0, 3410 intel_dp->downstream_ports, 3411 DP_MAX_DOWNSTREAM_PORTS) < 0) 3412 return false; /* downstream port status fetch failed */ 3413 3414 return true; 3415} 3416 3417static void 3418intel_dp_probe_oui(struct intel_dp *intel_dp) 3419{ 3420 u8 buf[3]; 3421 3422 if (!(intel_dp->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT)) 3423 return; 3424 3425 intel_edp_panel_vdd_on(intel_dp); 3426 3427 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_SINK_OUI, buf, 3) == 3) 3428 DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n", 3429 buf[0], buf[1], buf[2]); 3430 3431 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_BRANCH_OUI, buf, 3) == 3) 3432 DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n", 3433 buf[0], buf[1], buf[2]); 3434 3435 intel_edp_panel_vdd_off(intel_dp, false); 3436} 3437 3438static bool 3439intel_dp_probe_mst(struct intel_dp *intel_dp) 3440{ 3441 u8 buf[1]; 3442 3443 if (!intel_dp->can_mst) 3444 return false; 3445 3446 if (intel_dp->dpcd[DP_DPCD_REV] < 0x12) 3447 return false; 3448 3449 intel_edp_panel_vdd_on(intel_dp); 3450 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_MSTM_CAP, buf, 1)) { 3451 if (buf[0] & DP_MST_CAP) { 3452 DRM_DEBUG_KMS("Sink is MST capable\n"); 3453 intel_dp->is_mst = true; 3454 } else { 3455 DRM_DEBUG_KMS("Sink is not MST capable\n"); 3456 intel_dp->is_mst = false; 3457 } 3458 } 3459 intel_edp_panel_vdd_off(intel_dp, false); 3460 3461 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst); 3462 return intel_dp->is_mst; 3463} 3464 3465int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc) 3466{ 3467 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 3468 struct drm_device *dev = intel_dig_port->base.base.dev; 3469 struct intel_crtc *intel_crtc = 3470 to_intel_crtc(intel_dig_port->base.base.crtc); 3471 u8 buf[1]; 3472 3473 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK_MISC, buf) < 0) 3474 return -EAGAIN; 3475 3476 if (!(buf[0] & DP_TEST_CRC_SUPPORTED)) 3477 return -ENOTTY; 3478 3479 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK, 3480 DP_TEST_SINK_START) < 0) 3481 return -EAGAIN; 3482 3483 /* Wait 2 vblanks to be sure we will have the correct CRC value */ 3484 intel_wait_for_vblank(dev, intel_crtc->pipe); 3485 intel_wait_for_vblank(dev, intel_crtc->pipe); 3486 3487 if (drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_CRC_R_CR, crc, 6) < 0) 3488 return -EAGAIN; 3489 3490 drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK, 0); 3491 return 0; 3492} 3493 3494static bool 3495intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector) 3496{ 3497 return intel_dp_dpcd_read_wake(&intel_dp->aux, 3498 DP_DEVICE_SERVICE_IRQ_VECTOR, 3499 sink_irq_vector, 1) == 1; 3500} 3501 3502static bool 3503intel_dp_get_sink_irq_esi(struct intel_dp *intel_dp, u8 *sink_irq_vector) 3504{ 3505 int ret; 3506 3507 ret = intel_dp_dpcd_read_wake(&intel_dp->aux, 3508 DP_SINK_COUNT_ESI, 3509 sink_irq_vector, 14); 3510 if (ret != 14) 3511 return false; 3512 3513 return true; 3514} 3515 3516static void 3517intel_dp_handle_test_request(struct intel_dp *intel_dp) 3518{ 3519 /* NAK by default */ 3520 drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_RESPONSE, DP_TEST_NAK); 3521} 3522 3523static int 3524intel_dp_check_mst_status(struct intel_dp *intel_dp) 3525{ 3526 bool bret; 3527 3528 if (intel_dp->is_mst) { 3529 u8 esi[16] = { 0 }; 3530 int ret = 0; 3531 int retry; 3532 bool handled; 3533 bret = intel_dp_get_sink_irq_esi(intel_dp, esi); 3534go_again: 3535 if (bret == true) { 3536 3537 /* check link status - esi[10] = 0x200c */ 3538 if (intel_dp->active_mst_links && !drm_dp_channel_eq_ok(&esi[10], intel_dp->lane_count)) { 3539 DRM_DEBUG_KMS("channel EQ not ok, retraining\n"); 3540 intel_dp_start_link_train(intel_dp); 3541 intel_dp_complete_link_train(intel_dp); 3542 intel_dp_stop_link_train(intel_dp); 3543 } 3544 3545 DRM_DEBUG_KMS("got esi %02x %02x %02x\n", esi[0], esi[1], esi[2]); 3546 ret = drm_dp_mst_hpd_irq(&intel_dp->mst_mgr, esi, &handled); 3547 3548 if (handled) { 3549 for (retry = 0; retry < 3; retry++) { 3550 int wret; 3551 wret = drm_dp_dpcd_write(&intel_dp->aux, 3552 DP_SINK_COUNT_ESI+1, 3553 &esi[1], 3); 3554 if (wret == 3) { 3555 break; 3556 } 3557 } 3558 3559 bret = intel_dp_get_sink_irq_esi(intel_dp, esi); 3560 if (bret == true) { 3561 DRM_DEBUG_KMS("got esi2 %02x %02x %02x\n", esi[0], esi[1], esi[2]); 3562 goto go_again; 3563 } 3564 } else 3565 ret = 0; 3566 3567 return ret; 3568 } else { 3569 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 3570 DRM_DEBUG_KMS("failed to get ESI - device may have failed\n"); 3571 intel_dp->is_mst = false; 3572 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst); 3573 /* send a hotplug event */ 3574 drm_kms_helper_hotplug_event(intel_dig_port->base.base.dev); 3575 } 3576 } 3577 return -EINVAL; 3578} 3579 3580/* 3581 * According to DP spec 3582 * 5.1.2: 3583 * 1. Read DPCD 3584 * 2. Configure link according to Receiver Capabilities 3585 * 3. Use Link Training from 2.5.3.3 and 3.5.1.3 3586 * 4. Check link status on receipt of hot-plug interrupt 3587 */ 3588void 3589intel_dp_check_link_status(struct intel_dp *intel_dp) 3590{ 3591 struct drm_device *dev = intel_dp_to_dev(intel_dp); 3592 struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base; 3593 u8 sink_irq_vector; 3594 u8 link_status[DP_LINK_STATUS_SIZE]; 3595 3596 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex)); 3597 3598 if (!intel_encoder->connectors_active) 3599 return; 3600 3601 if (WARN_ON(!intel_encoder->base.crtc)) 3602 return; 3603 3604 if (!to_intel_crtc(intel_encoder->base.crtc)->active) 3605 return; 3606 3607 /* Try to read receiver status if the link appears to be up */ 3608 if (!intel_dp_get_link_status(intel_dp, link_status)) { 3609 return; 3610 } 3611 3612 /* Now read the DPCD to see if it's actually running */ 3613 if (!intel_dp_get_dpcd(intel_dp)) { 3614 return; 3615 } 3616 3617 /* Try to read the source of the interrupt */ 3618 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 && 3619 intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) { 3620 /* Clear interrupt source */ 3621 drm_dp_dpcd_writeb(&intel_dp->aux, 3622 DP_DEVICE_SERVICE_IRQ_VECTOR, 3623 sink_irq_vector); 3624 3625 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST) 3626 intel_dp_handle_test_request(intel_dp); 3627 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ)) 3628 DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n"); 3629 } 3630 3631 if (!drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) { 3632 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n", 3633 intel_encoder->base.name); 3634 intel_dp_start_link_train(intel_dp); 3635 intel_dp_complete_link_train(intel_dp); 3636 intel_dp_stop_link_train(intel_dp); 3637 } 3638} 3639 3640/* XXX this is probably wrong for multiple downstream ports */ 3641static enum drm_connector_status 3642intel_dp_detect_dpcd(struct intel_dp *intel_dp) 3643{ 3644 uint8_t *dpcd = intel_dp->dpcd; 3645 uint8_t type; 3646 3647 if (!intel_dp_get_dpcd(intel_dp)) 3648 return connector_status_disconnected; 3649 3650 /* if there's no downstream port, we're done */ 3651 if (!(dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT)) 3652 return connector_status_connected; 3653 3654 /* If we're HPD-aware, SINK_COUNT changes dynamically */ 3655 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 && 3656 intel_dp->downstream_ports[0] & DP_DS_PORT_HPD) { 3657 uint8_t reg; 3658 3659 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_SINK_COUNT, 3660 ®, 1) < 0) 3661 return connector_status_unknown; 3662 3663 return DP_GET_SINK_COUNT(reg) ? connector_status_connected 3664 : connector_status_disconnected; 3665 } 3666 3667 /* If no HPD, poke DDC gently */ 3668 if (drm_probe_ddc(&intel_dp->aux.ddc)) 3669 return connector_status_connected; 3670 3671 /* Well we tried, say unknown for unreliable port types */ 3672 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) { 3673 type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK; 3674 if (type == DP_DS_PORT_TYPE_VGA || 3675 type == DP_DS_PORT_TYPE_NON_EDID) 3676 return connector_status_unknown; 3677 } else { 3678 type = intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] & 3679 DP_DWN_STRM_PORT_TYPE_MASK; 3680 if (type == DP_DWN_STRM_PORT_TYPE_ANALOG || 3681 type == DP_DWN_STRM_PORT_TYPE_OTHER) 3682 return connector_status_unknown; 3683 } 3684 3685 /* Anything else is out of spec, warn and ignore */ 3686 DRM_DEBUG_KMS("Broken DP branch device, ignoring\n"); 3687 return connector_status_disconnected; 3688} 3689 3690static enum drm_connector_status 3691edp_detect(struct intel_dp *intel_dp) 3692{ 3693 struct drm_device *dev = intel_dp_to_dev(intel_dp); 3694 enum drm_connector_status status; 3695 3696 status = intel_panel_detect(dev); 3697 if (status == connector_status_unknown) 3698 status = connector_status_connected; 3699 3700 return status; 3701} 3702 3703static enum drm_connector_status 3704ironlake_dp_detect(struct intel_dp *intel_dp) 3705{ 3706 struct drm_device *dev = intel_dp_to_dev(intel_dp); 3707 struct drm_i915_private *dev_priv = dev->dev_private; 3708 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 3709 3710 if (!ibx_digital_port_connected(dev_priv, intel_dig_port)) 3711 return connector_status_disconnected; 3712 3713 return intel_dp_detect_dpcd(intel_dp); 3714} 3715 3716static enum drm_connector_status 3717g4x_dp_detect(struct intel_dp *intel_dp) 3718{ 3719 struct drm_device *dev = intel_dp_to_dev(intel_dp); 3720 struct drm_i915_private *dev_priv = dev->dev_private; 3721 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 3722 uint32_t bit; 3723 3724 if (IS_VALLEYVIEW(dev)) { 3725 switch (intel_dig_port->port) { 3726 case PORT_B: 3727 bit = PORTB_HOTPLUG_LIVE_STATUS_VLV; 3728 break; 3729 case PORT_C: 3730 bit = PORTC_HOTPLUG_LIVE_STATUS_VLV; 3731 break; 3732 case PORT_D: 3733 bit = PORTD_HOTPLUG_LIVE_STATUS_VLV; 3734 break; 3735 default: 3736 return connector_status_unknown; 3737 } 3738 } else { 3739 switch (intel_dig_port->port) { 3740 case PORT_B: 3741 bit = PORTB_HOTPLUG_LIVE_STATUS_G4X; 3742 break; 3743 case PORT_C: 3744 bit = PORTC_HOTPLUG_LIVE_STATUS_G4X; 3745 break; 3746 case PORT_D: 3747 bit = PORTD_HOTPLUG_LIVE_STATUS_G4X; 3748 break; 3749 default: 3750 return connector_status_unknown; 3751 } 3752 } 3753 3754 if ((I915_READ(PORT_HOTPLUG_STAT) & bit) == 0) 3755 return connector_status_disconnected; 3756 3757 return intel_dp_detect_dpcd(intel_dp); 3758} 3759 3760static struct edid * 3761intel_dp_get_edid(struct drm_connector *connector, struct i2c_adapter *adapter) 3762{ 3763 struct intel_connector *intel_connector = to_intel_connector(connector); 3764 3765 /* use cached edid if we have one */ 3766 if (intel_connector->edid) { 3767 /* invalid edid */ 3768 if (IS_ERR(intel_connector->edid)) 3769 return NULL; 3770 3771 return drm_edid_duplicate(intel_connector->edid); 3772 } 3773 3774 return drm_get_edid(connector, adapter); 3775} 3776 3777static int 3778intel_dp_get_edid_modes(struct drm_connector *connector, struct i2c_adapter *adapter) 3779{ 3780 struct intel_connector *intel_connector = to_intel_connector(connector); 3781 3782 /* use cached edid if we have one */ 3783 if (intel_connector->edid) { 3784 /* invalid edid */ 3785 if (IS_ERR(intel_connector->edid)) 3786 return 0; 3787 3788 return intel_connector_update_modes(connector, 3789 intel_connector->edid); 3790 } 3791 3792 return intel_ddc_get_modes(connector, adapter); 3793} 3794 3795static enum drm_connector_status 3796intel_dp_detect(struct drm_connector *connector, bool force) 3797{ 3798 struct intel_dp *intel_dp = intel_attached_dp(connector); 3799 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 3800 struct intel_encoder *intel_encoder = &intel_dig_port->base; 3801 struct drm_device *dev = connector->dev; 3802 struct drm_i915_private *dev_priv = dev->dev_private; 3803 enum drm_connector_status status; 3804 enum intel_display_power_domain power_domain; 3805 struct edid *edid = NULL; 3806 bool ret; 3807 3808 power_domain = intel_display_port_power_domain(intel_encoder); 3809 intel_display_power_get(dev_priv, power_domain); 3810 3811 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", 3812 connector->base.id, connector->name); 3813 3814 if (intel_dp->is_mst) { 3815 /* MST devices are disconnected from a monitor POV */ 3816 if (intel_encoder->type != INTEL_OUTPUT_EDP) 3817 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT; 3818 status = connector_status_disconnected; 3819 goto out; 3820 } 3821 3822 intel_dp->has_audio = false; 3823 3824 /* Can't disconnect eDP, but you can close the lid... */ 3825 if (is_edp(intel_dp)) 3826 status = edp_detect(intel_dp); 3827 else if (HAS_PCH_SPLIT(dev)) 3828 status = ironlake_dp_detect(intel_dp); 3829 else 3830 status = g4x_dp_detect(intel_dp); 3831 if (status != connector_status_connected) 3832 goto out; 3833 3834 intel_dp_probe_oui(intel_dp); 3835 3836 ret = intel_dp_probe_mst(intel_dp); 3837 if (ret) { 3838 /* if we are in MST mode then this connector 3839 won't appear connected or have anything with EDID on it */ 3840 if (intel_encoder->type != INTEL_OUTPUT_EDP) 3841 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT; 3842 status = connector_status_disconnected; 3843 goto out; 3844 } 3845 3846 if (intel_dp->force_audio != HDMI_AUDIO_AUTO) { 3847 intel_dp->has_audio = (intel_dp->force_audio == HDMI_AUDIO_ON); 3848 } else { 3849 edid = intel_dp_get_edid(connector, &intel_dp->aux.ddc); 3850 if (edid) { 3851 intel_dp->has_audio = drm_detect_monitor_audio(edid); 3852 kfree(edid); 3853 } 3854 } 3855 3856 if (intel_encoder->type != INTEL_OUTPUT_EDP) 3857 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT; 3858 status = connector_status_connected; 3859 3860out: 3861 intel_display_power_put(dev_priv, power_domain); 3862 return status; 3863} 3864 3865static int intel_dp_get_modes(struct drm_connector *connector) 3866{ 3867 struct intel_dp *intel_dp = intel_attached_dp(connector); 3868 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 3869 struct intel_encoder *intel_encoder = &intel_dig_port->base; 3870 struct intel_connector *intel_connector = to_intel_connector(connector); 3871 struct drm_device *dev = connector->dev; 3872 struct drm_i915_private *dev_priv = dev->dev_private; 3873 enum intel_display_power_domain power_domain; 3874 int ret; 3875 3876 /* We should parse the EDID data and find out if it has an audio sink 3877 */ 3878 3879 power_domain = intel_display_port_power_domain(intel_encoder); 3880 intel_display_power_get(dev_priv, power_domain); 3881 3882 ret = intel_dp_get_edid_modes(connector, &intel_dp->aux.ddc); 3883 intel_display_power_put(dev_priv, power_domain); 3884 if (ret) 3885 return ret; 3886 3887 /* if eDP has no EDID, fall back to fixed mode */ 3888 if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) { 3889 struct drm_display_mode *mode; 3890 mode = drm_mode_duplicate(dev, 3891 intel_connector->panel.fixed_mode); 3892 if (mode) { 3893 drm_mode_probed_add(connector, mode); 3894 return 1; 3895 } 3896 } 3897 return 0; 3898} 3899 3900static bool 3901intel_dp_detect_audio(struct drm_connector *connector) 3902{ 3903 struct intel_dp *intel_dp = intel_attached_dp(connector); 3904 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 3905 struct intel_encoder *intel_encoder = &intel_dig_port->base; 3906 struct drm_device *dev = connector->dev; 3907 struct drm_i915_private *dev_priv = dev->dev_private; 3908 enum intel_display_power_domain power_domain; 3909 struct edid *edid; 3910 bool has_audio = false; 3911 3912 power_domain = intel_display_port_power_domain(intel_encoder); 3913 intel_display_power_get(dev_priv, power_domain); 3914 3915 edid = intel_dp_get_edid(connector, &intel_dp->aux.ddc); 3916 if (edid) { 3917 has_audio = drm_detect_monitor_audio(edid); 3918 kfree(edid); 3919 } 3920 3921 intel_display_power_put(dev_priv, power_domain); 3922 3923 return has_audio; 3924} 3925 3926static int 3927intel_dp_set_property(struct drm_connector *connector, 3928 struct drm_property *property, 3929 uint64_t val) 3930{ 3931 struct drm_i915_private *dev_priv = connector->dev->dev_private; 3932 struct intel_connector *intel_connector = to_intel_connector(connector); 3933 struct intel_encoder *intel_encoder = intel_attached_encoder(connector); 3934 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base); 3935 int ret; 3936 3937 ret = drm_object_property_set_value(&connector->base, property, val); 3938 if (ret) 3939 return ret; 3940 3941 if (property == dev_priv->force_audio_property) { 3942 int i = val; 3943 bool has_audio; 3944 3945 if (i == intel_dp->force_audio) 3946 return 0; 3947 3948 intel_dp->force_audio = i; 3949 3950 if (i == HDMI_AUDIO_AUTO) 3951 has_audio = intel_dp_detect_audio(connector); 3952 else 3953 has_audio = (i == HDMI_AUDIO_ON); 3954 3955 if (has_audio == intel_dp->has_audio) 3956 return 0; 3957 3958 intel_dp->has_audio = has_audio; 3959 goto done; 3960 } 3961 3962 if (property == dev_priv->broadcast_rgb_property) { 3963 bool old_auto = intel_dp->color_range_auto; 3964 uint32_t old_range = intel_dp->color_range; 3965 3966 switch (val) { 3967 case INTEL_BROADCAST_RGB_AUTO: 3968 intel_dp->color_range_auto = true; 3969 break; 3970 case INTEL_BROADCAST_RGB_FULL: 3971 intel_dp->color_range_auto = false; 3972 intel_dp->color_range = 0; 3973 break; 3974 case INTEL_BROADCAST_RGB_LIMITED: 3975 intel_dp->color_range_auto = false; 3976 intel_dp->color_range = DP_COLOR_RANGE_16_235; 3977 break; 3978 default: 3979 return -EINVAL; 3980 } 3981 3982 if (old_auto == intel_dp->color_range_auto && 3983 old_range == intel_dp->color_range) 3984 return 0; 3985 3986 goto done; 3987 } 3988 3989 if (is_edp(intel_dp) && 3990 property == connector->dev->mode_config.scaling_mode_property) { 3991 if (val == DRM_MODE_SCALE_NONE) { 3992 DRM_DEBUG_KMS("no scaling not supported\n"); 3993 return -EINVAL; 3994 } 3995 3996 if (intel_connector->panel.fitting_mode == val) { 3997 /* the eDP scaling property is not changed */ 3998 return 0; 3999 } 4000 intel_connector->panel.fitting_mode = val; 4001 4002 goto done; 4003 } 4004 4005 return -EINVAL; 4006 4007done: 4008 if (intel_encoder->base.crtc) 4009 intel_crtc_restore_mode(intel_encoder->base.crtc); 4010 4011 return 0; 4012} 4013 4014static void 4015intel_dp_connector_destroy(struct drm_connector *connector) 4016{ 4017 struct intel_connector *intel_connector = to_intel_connector(connector); 4018 4019 if (!IS_ERR_OR_NULL(intel_connector->edid)) 4020 kfree(intel_connector->edid); 4021 4022 /* Can't call is_edp() since the encoder may have been destroyed 4023 * already. */ 4024 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) 4025 intel_panel_fini(&intel_connector->panel); 4026 4027 drm_connector_cleanup(connector); 4028 kfree(connector); 4029} 4030 4031void intel_dp_encoder_destroy(struct drm_encoder *encoder) 4032{ 4033 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); 4034 struct intel_dp *intel_dp = &intel_dig_port->dp; 4035 struct drm_device *dev = intel_dp_to_dev(intel_dp); 4036 4037 drm_dp_aux_unregister(&intel_dp->aux); 4038 intel_dp_mst_encoder_cleanup(intel_dig_port); 4039 drm_encoder_cleanup(encoder); 4040 if (is_edp(intel_dp)) { 4041 cancel_delayed_work_sync(&intel_dp->panel_vdd_work); 4042 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL); 4043 edp_panel_vdd_off_sync(intel_dp); 4044 drm_modeset_unlock(&dev->mode_config.connection_mutex); 4045 if (intel_dp->edp_notifier.notifier_call) { 4046 unregister_reboot_notifier(&intel_dp->edp_notifier); 4047 intel_dp->edp_notifier.notifier_call = NULL; 4048 } 4049 } 4050 kfree(intel_dig_port); 4051} 4052 4053static void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder) 4054{ 4055 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base); 4056 4057 if (!is_edp(intel_dp)) 4058 return; 4059 4060 edp_panel_vdd_off_sync(intel_dp); 4061} 4062 4063static void intel_dp_encoder_reset(struct drm_encoder *encoder) 4064{ 4065 intel_edp_panel_vdd_sanitize(to_intel_encoder(encoder)); 4066} 4067 4068static const struct drm_connector_funcs intel_dp_connector_funcs = { 4069 .dpms = intel_connector_dpms, 4070 .detect = intel_dp_detect, 4071 .fill_modes = drm_helper_probe_single_connector_modes, 4072 .set_property = intel_dp_set_property, 4073 .destroy = intel_dp_connector_destroy, 4074}; 4075 4076static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = { 4077 .get_modes = intel_dp_get_modes, 4078 .mode_valid = intel_dp_mode_valid, 4079 .best_encoder = intel_best_encoder, 4080}; 4081 4082static const struct drm_encoder_funcs intel_dp_enc_funcs = { 4083 .reset = intel_dp_encoder_reset, 4084 .destroy = intel_dp_encoder_destroy, 4085}; 4086 4087void 4088intel_dp_hot_plug(struct intel_encoder *intel_encoder) 4089{ 4090 return; 4091} 4092 4093bool 4094intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port, bool long_hpd) 4095{ 4096 struct intel_dp *intel_dp = &intel_dig_port->dp; 4097 struct intel_encoder *intel_encoder = &intel_dig_port->base; 4098 struct drm_device *dev = intel_dig_port->base.base.dev; 4099 struct drm_i915_private *dev_priv = dev->dev_private; 4100 enum intel_display_power_domain power_domain; 4101 bool ret = true; 4102 4103 if (intel_dig_port->base.type != INTEL_OUTPUT_EDP) 4104 intel_dig_port->base.type = INTEL_OUTPUT_DISPLAYPORT; 4105 4106 DRM_DEBUG_KMS("got hpd irq on port %c - %s\n", 4107 port_name(intel_dig_port->port), 4108 long_hpd ? "long" : "short"); 4109 4110 power_domain = intel_display_port_power_domain(intel_encoder); 4111 intel_display_power_get(dev_priv, power_domain); 4112 4113 if (long_hpd) { 4114 if (!ibx_digital_port_connected(dev_priv, intel_dig_port)) 4115 goto mst_fail; 4116 4117 if (!intel_dp_get_dpcd(intel_dp)) { 4118 goto mst_fail; 4119 } 4120 4121 intel_dp_probe_oui(intel_dp); 4122 4123 if (!intel_dp_probe_mst(intel_dp)) 4124 goto mst_fail; 4125 4126 } else { 4127 if (intel_dp->is_mst) { 4128 if (intel_dp_check_mst_status(intel_dp) == -EINVAL) 4129 goto mst_fail; 4130 } 4131 4132 if (!intel_dp->is_mst) { 4133 /* 4134 * we'll check the link status via the normal hot plug path later - 4135 * but for short hpds we should check it now 4136 */ 4137 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL); 4138 intel_dp_check_link_status(intel_dp); 4139 drm_modeset_unlock(&dev->mode_config.connection_mutex); 4140 } 4141 } 4142 ret = false; 4143 goto put_power; 4144mst_fail: 4145 /* if we were in MST mode, and device is not there get out of MST mode */ 4146 if (intel_dp->is_mst) { 4147 DRM_DEBUG_KMS("MST device may have disappeared %d vs %d\n", intel_dp->is_mst, intel_dp->mst_mgr.mst_state); 4148 intel_dp->is_mst = false; 4149 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst); 4150 } 4151put_power: 4152 intel_display_power_put(dev_priv, power_domain); 4153 4154 return ret; 4155} 4156 4157/* Return which DP Port should be selected for Transcoder DP control */ 4158int 4159intel_trans_dp_port_sel(struct drm_crtc *crtc) 4160{ 4161 struct drm_device *dev = crtc->dev; 4162 struct intel_encoder *intel_encoder; 4163 struct intel_dp *intel_dp; 4164 4165 for_each_encoder_on_crtc(dev, crtc, intel_encoder) { 4166 intel_dp = enc_to_intel_dp(&intel_encoder->base); 4167 4168 if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT || 4169 intel_encoder->type == INTEL_OUTPUT_EDP) 4170 return intel_dp->output_reg; 4171 } 4172 4173 return -1; 4174} 4175 4176/* check the VBT to see whether the eDP is on DP-D port */ 4177bool intel_dp_is_edp(struct drm_device *dev, enum port port) 4178{ 4179 struct drm_i915_private *dev_priv = dev->dev_private; 4180 union child_device_config *p_child; 4181 int i; 4182 static const short port_mapping[] = { 4183 [PORT_B] = PORT_IDPB, 4184 [PORT_C] = PORT_IDPC, 4185 [PORT_D] = PORT_IDPD, 4186 }; 4187 4188 if (port == PORT_A) 4189 return true; 4190 4191 if (!dev_priv->vbt.child_dev_num) 4192 return false; 4193 4194 for (i = 0; i < dev_priv->vbt.child_dev_num; i++) { 4195 p_child = dev_priv->vbt.child_dev + i; 4196 4197 if (p_child->common.dvo_port == port_mapping[port] && 4198 (p_child->common.device_type & DEVICE_TYPE_eDP_BITS) == 4199 (DEVICE_TYPE_eDP & DEVICE_TYPE_eDP_BITS)) 4200 return true; 4201 } 4202 return false; 4203} 4204 4205void 4206intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector) 4207{ 4208 struct intel_connector *intel_connector = to_intel_connector(connector); 4209 4210 intel_attach_force_audio_property(connector); 4211 intel_attach_broadcast_rgb_property(connector); 4212 intel_dp->color_range_auto = true; 4213 4214 if (is_edp(intel_dp)) { 4215 drm_mode_create_scaling_mode_property(connector->dev); 4216 drm_object_attach_property( 4217 &connector->base, 4218 connector->dev->mode_config.scaling_mode_property, 4219 DRM_MODE_SCALE_ASPECT); 4220 intel_connector->panel.fitting_mode = DRM_MODE_SCALE_ASPECT; 4221 } 4222} 4223 4224static void intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp) 4225{ 4226 intel_dp->last_power_cycle = jiffies; 4227 intel_dp->last_power_on = jiffies; 4228 intel_dp->last_backlight_off = jiffies; 4229} 4230 4231static void 4232intel_dp_init_panel_power_sequencer(struct drm_device *dev, 4233 struct intel_dp *intel_dp, 4234 struct edp_power_seq *out) 4235{ 4236 struct drm_i915_private *dev_priv = dev->dev_private; 4237 struct edp_power_seq cur, vbt, spec, final; 4238 u32 pp_on, pp_off, pp_div, pp; 4239 int pp_ctrl_reg, pp_on_reg, pp_off_reg, pp_div_reg; 4240 4241 if (HAS_PCH_SPLIT(dev)) { 4242 pp_ctrl_reg = PCH_PP_CONTROL; 4243 pp_on_reg = PCH_PP_ON_DELAYS; 4244 pp_off_reg = PCH_PP_OFF_DELAYS; 4245 pp_div_reg = PCH_PP_DIVISOR; 4246 } else { 4247 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp); 4248 4249 pp_ctrl_reg = VLV_PIPE_PP_CONTROL(pipe); 4250 pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe); 4251 pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe); 4252 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe); 4253 } 4254 4255 /* Workaround: Need to write PP_CONTROL with the unlock key as 4256 * the very first thing. */ 4257 pp = ironlake_get_pp_control(intel_dp); 4258 I915_WRITE(pp_ctrl_reg, pp); 4259 4260 pp_on = I915_READ(pp_on_reg); 4261 pp_off = I915_READ(pp_off_reg); 4262 pp_div = I915_READ(pp_div_reg); 4263 4264 /* Pull timing values out of registers */ 4265 cur.t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >> 4266 PANEL_POWER_UP_DELAY_SHIFT; 4267 4268 cur.t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >> 4269 PANEL_LIGHT_ON_DELAY_SHIFT; 4270 4271 cur.t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >> 4272 PANEL_LIGHT_OFF_DELAY_SHIFT; 4273 4274 cur.t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >> 4275 PANEL_POWER_DOWN_DELAY_SHIFT; 4276 4277 cur.t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >> 4278 PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000; 4279 4280 DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n", 4281 cur.t1_t3, cur.t8, cur.t9, cur.t10, cur.t11_t12); 4282 4283 vbt = dev_priv->vbt.edp_pps; 4284 4285 /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of 4286 * our hw here, which are all in 100usec. */ 4287 spec.t1_t3 = 210 * 10; 4288 spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */ 4289 spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */ 4290 spec.t10 = 500 * 10; 4291 /* This one is special and actually in units of 100ms, but zero 4292 * based in the hw (so we need to add 100 ms). But the sw vbt 4293 * table multiplies it with 1000 to make it in units of 100usec, 4294 * too. */ 4295 spec.t11_t12 = (510 + 100) * 10; 4296 4297 DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n", 4298 vbt.t1_t3, vbt.t8, vbt.t9, vbt.t10, vbt.t11_t12); 4299 4300 /* Use the max of the register settings and vbt. If both are 4301 * unset, fall back to the spec limits. */ 4302#define assign_final(field) final.field = (max(cur.field, vbt.field) == 0 ? \ 4303 spec.field : \ 4304 max(cur.field, vbt.field)) 4305 assign_final(t1_t3); 4306 assign_final(t8); 4307 assign_final(t9); 4308 assign_final(t10); 4309 assign_final(t11_t12); 4310#undef assign_final 4311 4312#define get_delay(field) (DIV_ROUND_UP(final.field, 10)) 4313 intel_dp->panel_power_up_delay = get_delay(t1_t3); 4314 intel_dp->backlight_on_delay = get_delay(t8); 4315 intel_dp->backlight_off_delay = get_delay(t9); 4316 intel_dp->panel_power_down_delay = get_delay(t10); 4317 intel_dp->panel_power_cycle_delay = get_delay(t11_t12); 4318#undef get_delay 4319 4320 DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n", 4321 intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay, 4322 intel_dp->panel_power_cycle_delay); 4323 4324 DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n", 4325 intel_dp->backlight_on_delay, intel_dp->backlight_off_delay); 4326 4327 if (out) 4328 *out = final; 4329} 4330 4331static void 4332intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev, 4333 struct intel_dp *intel_dp, 4334 struct edp_power_seq *seq) 4335{ 4336 struct drm_i915_private *dev_priv = dev->dev_private; 4337 u32 pp_on, pp_off, pp_div, port_sel = 0; 4338 int div = HAS_PCH_SPLIT(dev) ? intel_pch_rawclk(dev) : intel_hrawclk(dev); 4339 int pp_on_reg, pp_off_reg, pp_div_reg; 4340 enum port port = dp_to_dig_port(intel_dp)->port; 4341 4342 if (HAS_PCH_SPLIT(dev)) { 4343 pp_on_reg = PCH_PP_ON_DELAYS; 4344 pp_off_reg = PCH_PP_OFF_DELAYS; 4345 pp_div_reg = PCH_PP_DIVISOR; 4346 } else { 4347 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp); 4348 4349 pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe); 4350 pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe); 4351 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe); 4352 } 4353 4354 /* 4355 * And finally store the new values in the power sequencer. The 4356 * backlight delays are set to 1 because we do manual waits on them. For 4357 * T8, even BSpec recommends doing it. For T9, if we don't do this, 4358 * we'll end up waiting for the backlight off delay twice: once when we 4359 * do the manual sleep, and once when we disable the panel and wait for 4360 * the PP_STATUS bit to become zero. 4361 */ 4362 pp_on = (seq->t1_t3 << PANEL_POWER_UP_DELAY_SHIFT) | 4363 (1 << PANEL_LIGHT_ON_DELAY_SHIFT); 4364 pp_off = (1 << PANEL_LIGHT_OFF_DELAY_SHIFT) | 4365 (seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT); 4366 /* Compute the divisor for the pp clock, simply match the Bspec 4367 * formula. */ 4368 pp_div = ((100 * div)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT; 4369 pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000) 4370 << PANEL_POWER_CYCLE_DELAY_SHIFT); 4371 4372 /* Haswell doesn't have any port selection bits for the panel 4373 * power sequencer any more. */ 4374 if (IS_VALLEYVIEW(dev)) { 4375 port_sel = PANEL_PORT_SELECT_VLV(port); 4376 } else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) { 4377 if (port == PORT_A) 4378 port_sel = PANEL_PORT_SELECT_DPA; 4379 else 4380 port_sel = PANEL_PORT_SELECT_DPD; 4381 } 4382 4383 pp_on |= port_sel; 4384 4385 I915_WRITE(pp_on_reg, pp_on); 4386 I915_WRITE(pp_off_reg, pp_off); 4387 I915_WRITE(pp_div_reg, pp_div); 4388 4389 DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n", 4390 I915_READ(pp_on_reg), 4391 I915_READ(pp_off_reg), 4392 I915_READ(pp_div_reg)); 4393} 4394 4395void intel_dp_set_drrs_state(struct drm_device *dev, int refresh_rate) 4396{ 4397 struct drm_i915_private *dev_priv = dev->dev_private; 4398 struct intel_encoder *encoder; 4399 struct intel_dp *intel_dp = NULL; 4400 struct intel_crtc_config *config = NULL; 4401 struct intel_crtc *intel_crtc = NULL; 4402 struct intel_connector *intel_connector = dev_priv->drrs.connector; 4403 u32 reg, val; 4404 enum edp_drrs_refresh_rate_type index = DRRS_HIGH_RR; 4405 4406 if (refresh_rate <= 0) { 4407 DRM_DEBUG_KMS("Refresh rate should be positive non-zero.\n"); 4408 return; 4409 } 4410 4411 if (intel_connector == NULL) { 4412 DRM_DEBUG_KMS("DRRS supported for eDP only.\n"); 4413 return; 4414 } 4415 4416 /* 4417 * FIXME: This needs proper synchronization with psr state. But really 4418 * hard to tell without seeing the user of this function of this code. 4419 * Check locking and ordering once that lands. 4420 */ 4421 if (INTEL_INFO(dev)->gen < 8 && intel_edp_is_psr_enabled(dev)) { 4422 DRM_DEBUG_KMS("DRRS is disabled as PSR is enabled\n"); 4423 return; 4424 } 4425 4426 encoder = intel_attached_encoder(&intel_connector->base); 4427 intel_dp = enc_to_intel_dp(&encoder->base); 4428 intel_crtc = encoder->new_crtc; 4429 4430 if (!intel_crtc) { 4431 DRM_DEBUG_KMS("DRRS: intel_crtc not initialized\n"); 4432 return; 4433 } 4434 4435 config = &intel_crtc->config; 4436 4437 if (intel_dp->drrs_state.type < SEAMLESS_DRRS_SUPPORT) { 4438 DRM_DEBUG_KMS("Only Seamless DRRS supported.\n"); 4439 return; 4440 } 4441 4442 if (intel_connector->panel.downclock_mode->vrefresh == refresh_rate) 4443 index = DRRS_LOW_RR; 4444 4445 if (index == intel_dp->drrs_state.refresh_rate_type) { 4446 DRM_DEBUG_KMS( 4447 "DRRS requested for previously set RR...ignoring\n"); 4448 return; 4449 } 4450 4451 if (!intel_crtc->active) { 4452 DRM_DEBUG_KMS("eDP encoder disabled. CRTC not Active\n"); 4453 return; 4454 } 4455 4456 if (INTEL_INFO(dev)->gen > 6 && INTEL_INFO(dev)->gen < 8) { 4457 reg = PIPECONF(intel_crtc->config.cpu_transcoder); 4458 val = I915_READ(reg); 4459 if (index > DRRS_HIGH_RR) { 4460 val |= PIPECONF_EDP_RR_MODE_SWITCH; 4461 intel_dp_set_m_n(intel_crtc); 4462 } else { 4463 val &= ~PIPECONF_EDP_RR_MODE_SWITCH; 4464 } 4465 I915_WRITE(reg, val); 4466 } 4467 4468 /* 4469 * mutex taken to ensure that there is no race between differnt 4470 * drrs calls trying to update refresh rate. This scenario may occur 4471 * in future when idleness detection based DRRS in kernel and 4472 * possible calls from user space to set differnt RR are made. 4473 */ 4474 4475 mutex_lock(&intel_dp->drrs_state.mutex); 4476 4477 intel_dp->drrs_state.refresh_rate_type = index; 4478 4479 mutex_unlock(&intel_dp->drrs_state.mutex); 4480 4481 DRM_DEBUG_KMS("eDP Refresh Rate set to : %dHz\n", refresh_rate); 4482} 4483 4484static struct drm_display_mode * 4485intel_dp_drrs_init(struct intel_digital_port *intel_dig_port, 4486 struct intel_connector *intel_connector, 4487 struct drm_display_mode *fixed_mode) 4488{ 4489 struct drm_connector *connector = &intel_connector->base; 4490 struct intel_dp *intel_dp = &intel_dig_port->dp; 4491 struct drm_device *dev = intel_dig_port->base.base.dev; 4492 struct drm_i915_private *dev_priv = dev->dev_private; 4493 struct drm_display_mode *downclock_mode = NULL; 4494 4495 if (INTEL_INFO(dev)->gen <= 6) { 4496 DRM_DEBUG_KMS("DRRS supported for Gen7 and above\n"); 4497 return NULL; 4498 } 4499 4500 if (dev_priv->vbt.drrs_type != SEAMLESS_DRRS_SUPPORT) { 4501 DRM_DEBUG_KMS("VBT doesn't support DRRS\n"); 4502 return NULL; 4503 } 4504 4505 downclock_mode = intel_find_panel_downclock 4506 (dev, fixed_mode, connector); 4507 4508 if (!downclock_mode) { 4509 DRM_DEBUG_KMS("DRRS not supported\n"); 4510 return NULL; 4511 } 4512 4513 dev_priv->drrs.connector = intel_connector; 4514 4515 mutex_init(&intel_dp->drrs_state.mutex); 4516 4517 intel_dp->drrs_state.type = dev_priv->vbt.drrs_type; 4518 4519 intel_dp->drrs_state.refresh_rate_type = DRRS_HIGH_RR; 4520 DRM_DEBUG_KMS("seamless DRRS supported for eDP panel.\n"); 4521 return downclock_mode; 4522} 4523 4524void intel_edp_panel_vdd_sanitize(struct intel_encoder *intel_encoder) 4525{ 4526 struct drm_device *dev = intel_encoder->base.dev; 4527 struct drm_i915_private *dev_priv = dev->dev_private; 4528 struct intel_dp *intel_dp; 4529 enum intel_display_power_domain power_domain; 4530 4531 if (intel_encoder->type != INTEL_OUTPUT_EDP) 4532 return; 4533 4534 intel_dp = enc_to_intel_dp(&intel_encoder->base); 4535 if (!edp_have_panel_vdd(intel_dp)) 4536 return; 4537 /* 4538 * The VDD bit needs a power domain reference, so if the bit is 4539 * already enabled when we boot or resume, grab this reference and 4540 * schedule a vdd off, so we don't hold on to the reference 4541 * indefinitely. 4542 */ 4543 DRM_DEBUG_KMS("VDD left on by BIOS, adjusting state tracking\n"); 4544 power_domain = intel_display_port_power_domain(intel_encoder); 4545 intel_display_power_get(dev_priv, power_domain); 4546 4547 edp_panel_vdd_schedule_off(intel_dp); 4548} 4549 4550static bool intel_edp_init_connector(struct intel_dp *intel_dp, 4551 struct intel_connector *intel_connector, 4552 struct edp_power_seq *power_seq) 4553{ 4554 struct drm_connector *connector = &intel_connector->base; 4555 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 4556 struct intel_encoder *intel_encoder = &intel_dig_port->base; 4557 struct drm_device *dev = intel_encoder->base.dev; 4558 struct drm_i915_private *dev_priv = dev->dev_private; 4559 struct drm_display_mode *fixed_mode = NULL; 4560 struct drm_display_mode *downclock_mode = NULL; 4561 bool has_dpcd; 4562 struct drm_display_mode *scan; 4563 struct edid *edid; 4564 4565 intel_dp->drrs_state.type = DRRS_NOT_SUPPORTED; 4566 4567 if (!is_edp(intel_dp)) 4568 return true; 4569 4570 intel_edp_panel_vdd_sanitize(intel_encoder); 4571 4572 /* Cache DPCD and EDID for edp. */ 4573 intel_edp_panel_vdd_on(intel_dp); 4574 has_dpcd = intel_dp_get_dpcd(intel_dp); 4575 intel_edp_panel_vdd_off(intel_dp, false); 4576 4577 if (has_dpcd) { 4578 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) 4579 dev_priv->no_aux_handshake = 4580 intel_dp->dpcd[DP_MAX_DOWNSPREAD] & 4581 DP_NO_AUX_HANDSHAKE_LINK_TRAINING; 4582 } else { 4583 /* if this fails, presume the device is a ghost */ 4584 DRM_INFO("failed to retrieve link info, disabling eDP\n"); 4585 return false; 4586 } 4587 4588 /* We now know it's not a ghost, init power sequence regs. */ 4589 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp, power_seq); 4590 4591 mutex_lock(&dev->mode_config.mutex); 4592 edid = drm_get_edid(connector, &intel_dp->aux.ddc); 4593 if (edid) { 4594 if (drm_add_edid_modes(connector, edid)) { 4595 drm_mode_connector_update_edid_property(connector, 4596 edid); 4597 drm_edid_to_eld(connector, edid); 4598 } else { 4599 kfree(edid); 4600 edid = ERR_PTR(-EINVAL); 4601 } 4602 } else { 4603 edid = ERR_PTR(-ENOENT); 4604 } 4605 intel_connector->edid = edid; 4606 4607 /* prefer fixed mode from EDID if available */ 4608 list_for_each_entry(scan, &connector->probed_modes, head) { 4609 if ((scan->type & DRM_MODE_TYPE_PREFERRED)) { 4610 fixed_mode = drm_mode_duplicate(dev, scan); 4611 downclock_mode = intel_dp_drrs_init( 4612 intel_dig_port, 4613 intel_connector, fixed_mode); 4614 break; 4615 } 4616 } 4617 4618 /* fallback to VBT if available for eDP */ 4619 if (!fixed_mode && dev_priv->vbt.lfp_lvds_vbt_mode) { 4620 fixed_mode = drm_mode_duplicate(dev, 4621 dev_priv->vbt.lfp_lvds_vbt_mode); 4622 if (fixed_mode) 4623 fixed_mode->type |= DRM_MODE_TYPE_PREFERRED; 4624 } 4625 mutex_unlock(&dev->mode_config.mutex); 4626 4627 if (IS_VALLEYVIEW(dev)) { 4628 intel_dp->edp_notifier.notifier_call = edp_notify_handler; 4629 register_reboot_notifier(&intel_dp->edp_notifier); 4630 } 4631 4632 intel_panel_init(&intel_connector->panel, fixed_mode, downclock_mode); 4633 intel_connector->panel.backlight_power = intel_edp_backlight_power; 4634 intel_panel_setup_backlight(connector); 4635 4636 return true; 4637} 4638 4639bool 4640intel_dp_init_connector(struct intel_digital_port *intel_dig_port, 4641 struct intel_connector *intel_connector) 4642{ 4643 struct drm_connector *connector = &intel_connector->base; 4644 struct intel_dp *intel_dp = &intel_dig_port->dp; 4645 struct intel_encoder *intel_encoder = &intel_dig_port->base; 4646 struct drm_device *dev = intel_encoder->base.dev; 4647 struct drm_i915_private *dev_priv = dev->dev_private; 4648 enum port port = intel_dig_port->port; 4649 struct edp_power_seq power_seq = { 0 }; 4650 int type; 4651 4652 /* intel_dp vfuncs */ 4653 if (IS_VALLEYVIEW(dev)) 4654 intel_dp->get_aux_clock_divider = vlv_get_aux_clock_divider; 4655 else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) 4656 intel_dp->get_aux_clock_divider = hsw_get_aux_clock_divider; 4657 else if (HAS_PCH_SPLIT(dev)) 4658 intel_dp->get_aux_clock_divider = ilk_get_aux_clock_divider; 4659 else 4660 intel_dp->get_aux_clock_divider = i9xx_get_aux_clock_divider; 4661 4662 intel_dp->get_aux_send_ctl = i9xx_get_aux_send_ctl; 4663 4664 /* Preserve the current hw state. */ 4665 intel_dp->DP = I915_READ(intel_dp->output_reg); 4666 intel_dp->attached_connector = intel_connector; 4667 4668 if (intel_dp_is_edp(dev, port)) 4669 type = DRM_MODE_CONNECTOR_eDP; 4670 else 4671 type = DRM_MODE_CONNECTOR_DisplayPort; 4672 4673 /* 4674 * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but 4675 * for DP the encoder type can be set by the caller to 4676 * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it. 4677 */ 4678 if (type == DRM_MODE_CONNECTOR_eDP) 4679 intel_encoder->type = INTEL_OUTPUT_EDP; 4680 4681 DRM_DEBUG_KMS("Adding %s connector on port %c\n", 4682 type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP", 4683 port_name(port)); 4684 4685 drm_connector_init(dev, connector, &intel_dp_connector_funcs, type); 4686 drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs); 4687 4688 connector->interlace_allowed = true; 4689 connector->doublescan_allowed = 0; 4690 4691 INIT_DELAYED_WORK(&intel_dp->panel_vdd_work, 4692 edp_panel_vdd_work); 4693 4694 intel_connector_attach_encoder(intel_connector, intel_encoder); 4695 drm_connector_register(connector); 4696 4697 if (HAS_DDI(dev)) 4698 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state; 4699 else 4700 intel_connector->get_hw_state = intel_connector_get_hw_state; 4701 intel_connector->unregister = intel_dp_connector_unregister; 4702 4703 /* Set up the hotplug pin. */ 4704 switch (port) { 4705 case PORT_A: 4706 intel_encoder->hpd_pin = HPD_PORT_A; 4707 break; 4708 case PORT_B: 4709 intel_encoder->hpd_pin = HPD_PORT_B; 4710 break; 4711 case PORT_C: 4712 intel_encoder->hpd_pin = HPD_PORT_C; 4713 break; 4714 case PORT_D: 4715 intel_encoder->hpd_pin = HPD_PORT_D; 4716 break; 4717 default: 4718 BUG(); 4719 } 4720 4721 if (is_edp(intel_dp)) { 4722 intel_dp_init_panel_power_timestamps(intel_dp); 4723 intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq); 4724 } 4725 4726 intel_dp_aux_init(intel_dp, intel_connector); 4727 4728 /* init MST on ports that can support it */ 4729 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { 4730 if (port == PORT_B || port == PORT_C || port == PORT_D) { 4731 intel_dp_mst_encoder_init(intel_dig_port, intel_connector->base.base.id); 4732 } 4733 } 4734 4735 if (!intel_edp_init_connector(intel_dp, intel_connector, &power_seq)) { 4736 drm_dp_aux_unregister(&intel_dp->aux); 4737 if (is_edp(intel_dp)) { 4738 cancel_delayed_work_sync(&intel_dp->panel_vdd_work); 4739 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL); 4740 edp_panel_vdd_off_sync(intel_dp); 4741 drm_modeset_unlock(&dev->mode_config.connection_mutex); 4742 } 4743 drm_connector_unregister(connector); 4744 drm_connector_cleanup(connector); 4745 return false; 4746 } 4747 4748 intel_dp_add_properties(intel_dp, connector); 4749 4750 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written 4751 * 0xd. Failure to do so will result in spurious interrupts being 4752 * generated on the port when a cable is not attached. 4753 */ 4754 if (IS_G4X(dev) && !IS_GM45(dev)) { 4755 u32 temp = I915_READ(PEG_BAND_GAP_DATA); 4756 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd); 4757 } 4758 4759 return true; 4760} 4761 4762void 4763intel_dp_init(struct drm_device *dev, int output_reg, enum port port) 4764{ 4765 struct drm_i915_private *dev_priv = dev->dev_private; 4766 struct intel_digital_port *intel_dig_port; 4767 struct intel_encoder *intel_encoder; 4768 struct drm_encoder *encoder; 4769 struct intel_connector *intel_connector; 4770 4771 intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL); 4772 if (!intel_dig_port) 4773 return; 4774 4775 intel_connector = kzalloc(sizeof(*intel_connector), GFP_KERNEL); 4776 if (!intel_connector) { 4777 kfree(intel_dig_port); 4778 return; 4779 } 4780 4781 intel_encoder = &intel_dig_port->base; 4782 encoder = &intel_encoder->base; 4783 4784 drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs, 4785 DRM_MODE_ENCODER_TMDS); 4786 4787 intel_encoder->compute_config = intel_dp_compute_config; 4788 intel_encoder->disable = intel_disable_dp; 4789 intel_encoder->get_hw_state = intel_dp_get_hw_state; 4790 intel_encoder->get_config = intel_dp_get_config; 4791 intel_encoder->suspend = intel_dp_encoder_suspend; 4792 if (IS_CHERRYVIEW(dev)) { 4793 intel_encoder->pre_pll_enable = chv_dp_pre_pll_enable; 4794 intel_encoder->pre_enable = chv_pre_enable_dp; 4795 intel_encoder->enable = vlv_enable_dp; 4796 intel_encoder->post_disable = chv_post_disable_dp; 4797 } else if (IS_VALLEYVIEW(dev)) { 4798 intel_encoder->pre_pll_enable = vlv_dp_pre_pll_enable; 4799 intel_encoder->pre_enable = vlv_pre_enable_dp; 4800 intel_encoder->enable = vlv_enable_dp; 4801 intel_encoder->post_disable = vlv_post_disable_dp; 4802 } else { 4803 intel_encoder->pre_enable = g4x_pre_enable_dp; 4804 intel_encoder->enable = g4x_enable_dp; 4805 intel_encoder->post_disable = g4x_post_disable_dp; 4806 } 4807 4808 intel_dig_port->port = port; 4809 intel_dig_port->dp.output_reg = output_reg; 4810 4811 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT; 4812 if (IS_CHERRYVIEW(dev)) { 4813 if (port == PORT_D) 4814 intel_encoder->crtc_mask = 1 << 2; 4815 else 4816 intel_encoder->crtc_mask = (1 << 0) | (1 << 1); 4817 } else { 4818 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2); 4819 } 4820 intel_encoder->cloneable = 0; 4821 intel_encoder->hot_plug = intel_dp_hot_plug; 4822 4823 intel_dig_port->hpd_pulse = intel_dp_hpd_pulse; 4824 dev_priv->hpd_irq_port[port] = intel_dig_port; 4825 4826 if (!intel_dp_init_connector(intel_dig_port, intel_connector)) { 4827 drm_encoder_cleanup(encoder); 4828 kfree(intel_dig_port); 4829 kfree(intel_connector); 4830 } 4831} 4832 4833void intel_dp_mst_suspend(struct drm_device *dev) 4834{ 4835 struct drm_i915_private *dev_priv = dev->dev_private; 4836 int i; 4837 4838 /* disable MST */ 4839 for (i = 0; i < I915_MAX_PORTS; i++) { 4840 struct intel_digital_port *intel_dig_port = dev_priv->hpd_irq_port[i]; 4841 if (!intel_dig_port) 4842 continue; 4843 4844 if (intel_dig_port->base.type == INTEL_OUTPUT_DISPLAYPORT) { 4845 if (!intel_dig_port->dp.can_mst) 4846 continue; 4847 if (intel_dig_port->dp.is_mst) 4848 drm_dp_mst_topology_mgr_suspend(&intel_dig_port->dp.mst_mgr); 4849 } 4850 } 4851} 4852 4853void intel_dp_mst_resume(struct drm_device *dev) 4854{ 4855 struct drm_i915_private *dev_priv = dev->dev_private; 4856 int i; 4857 4858 for (i = 0; i < I915_MAX_PORTS; i++) { 4859 struct intel_digital_port *intel_dig_port = dev_priv->hpd_irq_port[i]; 4860 if (!intel_dig_port) 4861 continue; 4862 if (intel_dig_port->base.type == INTEL_OUTPUT_DISPLAYPORT) { 4863 int ret; 4864 4865 if (!intel_dig_port->dp.can_mst) 4866 continue; 4867 4868 ret = drm_dp_mst_topology_mgr_resume(&intel_dig_port->dp.mst_mgr); 4869 if (ret != 0) { 4870 intel_dp_check_mst_status(&intel_dig_port->dp); 4871 } 4872 } 4873 } 4874} 4875