intel_dp.c revision f51a44b9a6c4982cc25bfb3727de9bb893621ebc
1/* 2 * Copyright © 2008 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 * Authors: 24 * Keith Packard <keithp@keithp.com> 25 * 26 */ 27 28#include <linux/i2c.h> 29#include <linux/slab.h> 30#include <linux/export.h> 31#include <drm/drmP.h> 32#include <drm/drm_crtc.h> 33#include <drm/drm_crtc_helper.h> 34#include <drm/drm_edid.h> 35#include "intel_drv.h" 36#include <drm/i915_drm.h> 37#include "i915_drv.h" 38 39#define DP_LINK_CHECK_TIMEOUT (10 * 1000) 40 41struct dp_link_dpll { 42 int link_bw; 43 struct dpll dpll; 44}; 45 46static const struct dp_link_dpll gen4_dpll[] = { 47 { DP_LINK_BW_1_62, 48 { .p1 = 2, .p2 = 10, .n = 2, .m1 = 23, .m2 = 8 } }, 49 { DP_LINK_BW_2_7, 50 { .p1 = 1, .p2 = 10, .n = 1, .m1 = 14, .m2 = 2 } } 51}; 52 53static const struct dp_link_dpll pch_dpll[] = { 54 { DP_LINK_BW_1_62, 55 { .p1 = 2, .p2 = 10, .n = 1, .m1 = 12, .m2 = 9 } }, 56 { DP_LINK_BW_2_7, 57 { .p1 = 1, .p2 = 10, .n = 2, .m1 = 14, .m2 = 8 } } 58}; 59 60static const struct dp_link_dpll vlv_dpll[] = { 61 { DP_LINK_BW_1_62, 62 { .p1 = 3, .p2 = 2, .n = 5, .m1 = 3, .m2 = 81 } }, 63 { DP_LINK_BW_2_7, 64 { .p1 = 2, .p2 = 2, .n = 1, .m1 = 2, .m2 = 27 } } 65}; 66 67/** 68 * is_edp - is the given port attached to an eDP panel (either CPU or PCH) 69 * @intel_dp: DP struct 70 * 71 * If a CPU or PCH DP output is attached to an eDP panel, this function 72 * will return true, and false otherwise. 73 */ 74static bool is_edp(struct intel_dp *intel_dp) 75{ 76 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 77 78 return intel_dig_port->base.type == INTEL_OUTPUT_EDP; 79} 80 81static struct drm_device *intel_dp_to_dev(struct intel_dp *intel_dp) 82{ 83 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 84 85 return intel_dig_port->base.base.dev; 86} 87 88static struct intel_dp *intel_attached_dp(struct drm_connector *connector) 89{ 90 return enc_to_intel_dp(&intel_attached_encoder(connector)->base); 91} 92 93static void intel_dp_link_down(struct intel_dp *intel_dp); 94 95static int 96intel_dp_max_link_bw(struct intel_dp *intel_dp) 97{ 98 int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE]; 99 100 switch (max_link_bw) { 101 case DP_LINK_BW_1_62: 102 case DP_LINK_BW_2_7: 103 break; 104 case DP_LINK_BW_5_4: /* 1.2 capable displays may advertise higher bw */ 105 max_link_bw = DP_LINK_BW_2_7; 106 break; 107 default: 108 WARN(1, "invalid max DP link bw val %x, using 1.62Gbps\n", 109 max_link_bw); 110 max_link_bw = DP_LINK_BW_1_62; 111 break; 112 } 113 return max_link_bw; 114} 115 116/* 117 * The units on the numbers in the next two are... bizarre. Examples will 118 * make it clearer; this one parallels an example in the eDP spec. 119 * 120 * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as: 121 * 122 * 270000 * 1 * 8 / 10 == 216000 123 * 124 * The actual data capacity of that configuration is 2.16Gbit/s, so the 125 * units are decakilobits. ->clock in a drm_display_mode is in kilohertz - 126 * or equivalently, kilopixels per second - so for 1680x1050R it'd be 127 * 119000. At 18bpp that's 2142000 kilobits per second. 128 * 129 * Thus the strange-looking division by 10 in intel_dp_link_required, to 130 * get the result in decakilobits instead of kilobits. 131 */ 132 133static int 134intel_dp_link_required(int pixel_clock, int bpp) 135{ 136 return (pixel_clock * bpp + 9) / 10; 137} 138 139static int 140intel_dp_max_data_rate(int max_link_clock, int max_lanes) 141{ 142 return (max_link_clock * max_lanes * 8) / 10; 143} 144 145static enum drm_mode_status 146intel_dp_mode_valid(struct drm_connector *connector, 147 struct drm_display_mode *mode) 148{ 149 struct intel_dp *intel_dp = intel_attached_dp(connector); 150 struct intel_connector *intel_connector = to_intel_connector(connector); 151 struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode; 152 int target_clock = mode->clock; 153 int max_rate, mode_rate, max_lanes, max_link_clock; 154 155 if (is_edp(intel_dp) && fixed_mode) { 156 if (mode->hdisplay > fixed_mode->hdisplay) 157 return MODE_PANEL; 158 159 if (mode->vdisplay > fixed_mode->vdisplay) 160 return MODE_PANEL; 161 162 target_clock = fixed_mode->clock; 163 } 164 165 max_link_clock = drm_dp_bw_code_to_link_rate(intel_dp_max_link_bw(intel_dp)); 166 max_lanes = drm_dp_max_lane_count(intel_dp->dpcd); 167 168 max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes); 169 mode_rate = intel_dp_link_required(target_clock, 18); 170 171 if (mode_rate > max_rate) 172 return MODE_CLOCK_HIGH; 173 174 if (mode->clock < 10000) 175 return MODE_CLOCK_LOW; 176 177 if (mode->flags & DRM_MODE_FLAG_DBLCLK) 178 return MODE_H_ILLEGAL; 179 180 return MODE_OK; 181} 182 183static uint32_t 184pack_aux(uint8_t *src, int src_bytes) 185{ 186 int i; 187 uint32_t v = 0; 188 189 if (src_bytes > 4) 190 src_bytes = 4; 191 for (i = 0; i < src_bytes; i++) 192 v |= ((uint32_t) src[i]) << ((3-i) * 8); 193 return v; 194} 195 196static void 197unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes) 198{ 199 int i; 200 if (dst_bytes > 4) 201 dst_bytes = 4; 202 for (i = 0; i < dst_bytes; i++) 203 dst[i] = src >> ((3-i) * 8); 204} 205 206/* hrawclock is 1/4 the FSB frequency */ 207static int 208intel_hrawclk(struct drm_device *dev) 209{ 210 struct drm_i915_private *dev_priv = dev->dev_private; 211 uint32_t clkcfg; 212 213 /* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */ 214 if (IS_VALLEYVIEW(dev)) 215 return 200; 216 217 clkcfg = I915_READ(CLKCFG); 218 switch (clkcfg & CLKCFG_FSB_MASK) { 219 case CLKCFG_FSB_400: 220 return 100; 221 case CLKCFG_FSB_533: 222 return 133; 223 case CLKCFG_FSB_667: 224 return 166; 225 case CLKCFG_FSB_800: 226 return 200; 227 case CLKCFG_FSB_1067: 228 return 266; 229 case CLKCFG_FSB_1333: 230 return 333; 231 /* these two are just a guess; one of them might be right */ 232 case CLKCFG_FSB_1600: 233 case CLKCFG_FSB_1600_ALT: 234 return 400; 235 default: 236 return 133; 237 } 238} 239 240static void 241intel_dp_init_panel_power_sequencer(struct drm_device *dev, 242 struct intel_dp *intel_dp, 243 struct edp_power_seq *out); 244static void 245intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev, 246 struct intel_dp *intel_dp, 247 struct edp_power_seq *out); 248 249static enum pipe 250vlv_power_sequencer_pipe(struct intel_dp *intel_dp) 251{ 252 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 253 struct drm_crtc *crtc = intel_dig_port->base.base.crtc; 254 struct drm_device *dev = intel_dig_port->base.base.dev; 255 struct drm_i915_private *dev_priv = dev->dev_private; 256 enum port port = intel_dig_port->port; 257 enum pipe pipe; 258 259 /* modeset should have pipe */ 260 if (crtc) 261 return to_intel_crtc(crtc)->pipe; 262 263 /* init time, try to find a pipe with this port selected */ 264 for (pipe = PIPE_A; pipe <= PIPE_B; pipe++) { 265 u32 port_sel = I915_READ(VLV_PIPE_PP_ON_DELAYS(pipe)) & 266 PANEL_PORT_SELECT_MASK; 267 if (port_sel == PANEL_PORT_SELECT_DPB_VLV && port == PORT_B) 268 return pipe; 269 if (port_sel == PANEL_PORT_SELECT_DPC_VLV && port == PORT_C) 270 return pipe; 271 } 272 273 /* shrug */ 274 return PIPE_A; 275} 276 277static u32 _pp_ctrl_reg(struct intel_dp *intel_dp) 278{ 279 struct drm_device *dev = intel_dp_to_dev(intel_dp); 280 281 if (HAS_PCH_SPLIT(dev)) 282 return PCH_PP_CONTROL; 283 else 284 return VLV_PIPE_PP_CONTROL(vlv_power_sequencer_pipe(intel_dp)); 285} 286 287static u32 _pp_stat_reg(struct intel_dp *intel_dp) 288{ 289 struct drm_device *dev = intel_dp_to_dev(intel_dp); 290 291 if (HAS_PCH_SPLIT(dev)) 292 return PCH_PP_STATUS; 293 else 294 return VLV_PIPE_PP_STATUS(vlv_power_sequencer_pipe(intel_dp)); 295} 296 297static bool ironlake_edp_have_panel_power(struct intel_dp *intel_dp) 298{ 299 struct drm_device *dev = intel_dp_to_dev(intel_dp); 300 struct drm_i915_private *dev_priv = dev->dev_private; 301 302 return (I915_READ(_pp_stat_reg(intel_dp)) & PP_ON) != 0; 303} 304 305static bool ironlake_edp_have_panel_vdd(struct intel_dp *intel_dp) 306{ 307 struct drm_device *dev = intel_dp_to_dev(intel_dp); 308 struct drm_i915_private *dev_priv = dev->dev_private; 309 310 return (I915_READ(_pp_ctrl_reg(intel_dp)) & EDP_FORCE_VDD) != 0; 311} 312 313static void 314intel_dp_check_edp(struct intel_dp *intel_dp) 315{ 316 struct drm_device *dev = intel_dp_to_dev(intel_dp); 317 struct drm_i915_private *dev_priv = dev->dev_private; 318 319 if (!is_edp(intel_dp)) 320 return; 321 322 if (!ironlake_edp_have_panel_power(intel_dp) && !ironlake_edp_have_panel_vdd(intel_dp)) { 323 WARN(1, "eDP powered off while attempting aux channel communication.\n"); 324 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n", 325 I915_READ(_pp_stat_reg(intel_dp)), 326 I915_READ(_pp_ctrl_reg(intel_dp))); 327 } 328} 329 330static uint32_t 331intel_dp_aux_wait_done(struct intel_dp *intel_dp, bool has_aux_irq) 332{ 333 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 334 struct drm_device *dev = intel_dig_port->base.base.dev; 335 struct drm_i915_private *dev_priv = dev->dev_private; 336 uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg; 337 uint32_t status; 338 bool done; 339 340#define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0) 341 if (has_aux_irq) 342 done = wait_event_timeout(dev_priv->gmbus_wait_queue, C, 343 msecs_to_jiffies_timeout(10)); 344 else 345 done = wait_for_atomic(C, 10) == 0; 346 if (!done) 347 DRM_ERROR("dp aux hw did not signal timeout (has irq: %i)!\n", 348 has_aux_irq); 349#undef C 350 351 return status; 352} 353 354static uint32_t get_aux_clock_divider(struct intel_dp *intel_dp, 355 int index) 356{ 357 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 358 struct drm_device *dev = intel_dig_port->base.base.dev; 359 struct drm_i915_private *dev_priv = dev->dev_private; 360 361 /* The clock divider is based off the hrawclk, 362 * and would like to run at 2MHz. So, take the 363 * hrawclk value and divide by 2 and use that 364 * 365 * Note that PCH attached eDP panels should use a 125MHz input 366 * clock divider. 367 */ 368 if (IS_VALLEYVIEW(dev)) { 369 return index ? 0 : 100; 370 } else if (intel_dig_port->port == PORT_A) { 371 if (index) 372 return 0; 373 if (HAS_DDI(dev)) 374 return DIV_ROUND_CLOSEST(intel_ddi_get_cdclk_freq(dev_priv), 2000); 375 else if (IS_GEN6(dev) || IS_GEN7(dev)) 376 return 200; /* SNB & IVB eDP input clock at 400Mhz */ 377 else 378 return 225; /* eDP input clock at 450Mhz */ 379 } else if (dev_priv->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE) { 380 /* Workaround for non-ULT HSW */ 381 switch (index) { 382 case 0: return 63; 383 case 1: return 72; 384 default: return 0; 385 } 386 } else if (HAS_PCH_SPLIT(dev)) { 387 return index ? 0 : DIV_ROUND_UP(intel_pch_rawclk(dev), 2); 388 } else { 389 return index ? 0 :intel_hrawclk(dev) / 2; 390 } 391} 392 393static int 394intel_dp_aux_ch(struct intel_dp *intel_dp, 395 uint8_t *send, int send_bytes, 396 uint8_t *recv, int recv_size) 397{ 398 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 399 struct drm_device *dev = intel_dig_port->base.base.dev; 400 struct drm_i915_private *dev_priv = dev->dev_private; 401 uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg; 402 uint32_t ch_data = ch_ctl + 4; 403 uint32_t aux_clock_divider; 404 int i, ret, recv_bytes; 405 uint32_t status; 406 int try, precharge, clock = 0; 407 bool has_aux_irq = HAS_AUX_IRQ(dev); 408 uint32_t timeout; 409 410 /* dp aux is extremely sensitive to irq latency, hence request the 411 * lowest possible wakeup latency and so prevent the cpu from going into 412 * deep sleep states. 413 */ 414 pm_qos_update_request(&dev_priv->pm_qos, 0); 415 416 intel_dp_check_edp(intel_dp); 417 418 if (IS_GEN6(dev)) 419 precharge = 3; 420 else 421 precharge = 5; 422 423 if (IS_BROADWELL(dev) && ch_ctl == DPA_AUX_CH_CTL) 424 timeout = DP_AUX_CH_CTL_TIME_OUT_600us; 425 else 426 timeout = DP_AUX_CH_CTL_TIME_OUT_400us; 427 428 intel_aux_display_runtime_get(dev_priv); 429 430 /* Try to wait for any previous AUX channel activity */ 431 for (try = 0; try < 3; try++) { 432 status = I915_READ_NOTRACE(ch_ctl); 433 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0) 434 break; 435 msleep(1); 436 } 437 438 if (try == 3) { 439 WARN(1, "dp_aux_ch not started status 0x%08x\n", 440 I915_READ(ch_ctl)); 441 ret = -EBUSY; 442 goto out; 443 } 444 445 /* Only 5 data registers! */ 446 if (WARN_ON(send_bytes > 20 || recv_size > 20)) { 447 ret = -E2BIG; 448 goto out; 449 } 450 451 while ((aux_clock_divider = get_aux_clock_divider(intel_dp, clock++))) { 452 /* Must try at least 3 times according to DP spec */ 453 for (try = 0; try < 5; try++) { 454 /* Load the send data into the aux channel data registers */ 455 for (i = 0; i < send_bytes; i += 4) 456 I915_WRITE(ch_data + i, 457 pack_aux(send + i, send_bytes - i)); 458 459 /* Send the command and wait for it to complete */ 460 I915_WRITE(ch_ctl, 461 DP_AUX_CH_CTL_SEND_BUSY | 462 (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) | 463 timeout | 464 (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) | 465 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) | 466 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT) | 467 DP_AUX_CH_CTL_DONE | 468 DP_AUX_CH_CTL_TIME_OUT_ERROR | 469 DP_AUX_CH_CTL_RECEIVE_ERROR); 470 471 status = intel_dp_aux_wait_done(intel_dp, has_aux_irq); 472 473 /* Clear done status and any errors */ 474 I915_WRITE(ch_ctl, 475 status | 476 DP_AUX_CH_CTL_DONE | 477 DP_AUX_CH_CTL_TIME_OUT_ERROR | 478 DP_AUX_CH_CTL_RECEIVE_ERROR); 479 480 if (status & (DP_AUX_CH_CTL_TIME_OUT_ERROR | 481 DP_AUX_CH_CTL_RECEIVE_ERROR)) 482 continue; 483 if (status & DP_AUX_CH_CTL_DONE) 484 break; 485 } 486 if (status & DP_AUX_CH_CTL_DONE) 487 break; 488 } 489 490 if ((status & DP_AUX_CH_CTL_DONE) == 0) { 491 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status); 492 ret = -EBUSY; 493 goto out; 494 } 495 496 /* Check for timeout or receive error. 497 * Timeouts occur when the sink is not connected 498 */ 499 if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) { 500 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status); 501 ret = -EIO; 502 goto out; 503 } 504 505 /* Timeouts occur when the device isn't connected, so they're 506 * "normal" -- don't fill the kernel log with these */ 507 if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) { 508 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status); 509 ret = -ETIMEDOUT; 510 goto out; 511 } 512 513 /* Unload any bytes sent back from the other side */ 514 recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >> 515 DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT); 516 if (recv_bytes > recv_size) 517 recv_bytes = recv_size; 518 519 for (i = 0; i < recv_bytes; i += 4) 520 unpack_aux(I915_READ(ch_data + i), 521 recv + i, recv_bytes - i); 522 523 ret = recv_bytes; 524out: 525 pm_qos_update_request(&dev_priv->pm_qos, PM_QOS_DEFAULT_VALUE); 526 intel_aux_display_runtime_put(dev_priv); 527 528 return ret; 529} 530 531/* Write data to the aux channel in native mode */ 532static int 533intel_dp_aux_native_write(struct intel_dp *intel_dp, 534 uint16_t address, uint8_t *send, int send_bytes) 535{ 536 int ret; 537 uint8_t msg[20]; 538 int msg_bytes; 539 uint8_t ack; 540 int retry; 541 542 if (WARN_ON(send_bytes > 16)) 543 return -E2BIG; 544 545 intel_dp_check_edp(intel_dp); 546 msg[0] = DP_AUX_NATIVE_WRITE << 4; 547 msg[1] = address >> 8; 548 msg[2] = address & 0xff; 549 msg[3] = send_bytes - 1; 550 memcpy(&msg[4], send, send_bytes); 551 msg_bytes = send_bytes + 4; 552 for (retry = 0; retry < 7; retry++) { 553 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes, &ack, 1); 554 if (ret < 0) 555 return ret; 556 ack >>= 4; 557 if ((ack & DP_AUX_NATIVE_REPLY_MASK) == DP_AUX_NATIVE_REPLY_ACK) 558 return send_bytes; 559 else if ((ack & DP_AUX_NATIVE_REPLY_MASK) == DP_AUX_NATIVE_REPLY_DEFER) 560 usleep_range(400, 500); 561 else 562 return -EIO; 563 } 564 565 DRM_ERROR("too many retries, giving up\n"); 566 return -EIO; 567} 568 569/* Write a single byte to the aux channel in native mode */ 570static int 571intel_dp_aux_native_write_1(struct intel_dp *intel_dp, 572 uint16_t address, uint8_t byte) 573{ 574 return intel_dp_aux_native_write(intel_dp, address, &byte, 1); 575} 576 577/* read bytes from a native aux channel */ 578static int 579intel_dp_aux_native_read(struct intel_dp *intel_dp, 580 uint16_t address, uint8_t *recv, int recv_bytes) 581{ 582 uint8_t msg[4]; 583 int msg_bytes; 584 uint8_t reply[20]; 585 int reply_bytes; 586 uint8_t ack; 587 int ret; 588 int retry; 589 590 if (WARN_ON(recv_bytes > 19)) 591 return -E2BIG; 592 593 intel_dp_check_edp(intel_dp); 594 msg[0] = DP_AUX_NATIVE_READ << 4; 595 msg[1] = address >> 8; 596 msg[2] = address & 0xff; 597 msg[3] = recv_bytes - 1; 598 599 msg_bytes = 4; 600 reply_bytes = recv_bytes + 1; 601 602 for (retry = 0; retry < 7; retry++) { 603 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes, 604 reply, reply_bytes); 605 if (ret == 0) 606 return -EPROTO; 607 if (ret < 0) 608 return ret; 609 ack = reply[0] >> 4; 610 if ((ack & DP_AUX_NATIVE_REPLY_MASK) == DP_AUX_NATIVE_REPLY_ACK) { 611 memcpy(recv, reply + 1, ret - 1); 612 return ret - 1; 613 } 614 else if ((ack & DP_AUX_NATIVE_REPLY_MASK) == DP_AUX_NATIVE_REPLY_DEFER) 615 usleep_range(400, 500); 616 else 617 return -EIO; 618 } 619 620 DRM_ERROR("too many retries, giving up\n"); 621 return -EIO; 622} 623 624static int 625intel_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode, 626 uint8_t write_byte, uint8_t *read_byte) 627{ 628 struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data; 629 struct intel_dp *intel_dp = container_of(adapter, 630 struct intel_dp, 631 adapter); 632 uint16_t address = algo_data->address; 633 uint8_t msg[5]; 634 uint8_t reply[2]; 635 unsigned retry; 636 int msg_bytes; 637 int reply_bytes; 638 int ret; 639 640 ironlake_edp_panel_vdd_on(intel_dp); 641 intel_dp_check_edp(intel_dp); 642 /* Set up the command byte */ 643 if (mode & MODE_I2C_READ) 644 msg[0] = DP_AUX_I2C_READ << 4; 645 else 646 msg[0] = DP_AUX_I2C_WRITE << 4; 647 648 if (!(mode & MODE_I2C_STOP)) 649 msg[0] |= DP_AUX_I2C_MOT << 4; 650 651 msg[1] = address >> 8; 652 msg[2] = address; 653 654 switch (mode) { 655 case MODE_I2C_WRITE: 656 msg[3] = 0; 657 msg[4] = write_byte; 658 msg_bytes = 5; 659 reply_bytes = 1; 660 break; 661 case MODE_I2C_READ: 662 msg[3] = 0; 663 msg_bytes = 4; 664 reply_bytes = 2; 665 break; 666 default: 667 msg_bytes = 3; 668 reply_bytes = 1; 669 break; 670 } 671 672 /* 673 * DP1.2 sections 2.7.7.1.5.6.1 and 2.7.7.1.6.6.1: A DP Source device is 674 * required to retry at least seven times upon receiving AUX_DEFER 675 * before giving up the AUX transaction. 676 */ 677 for (retry = 0; retry < 7; retry++) { 678 ret = intel_dp_aux_ch(intel_dp, 679 msg, msg_bytes, 680 reply, reply_bytes); 681 if (ret < 0) { 682 DRM_DEBUG_KMS("aux_ch failed %d\n", ret); 683 goto out; 684 } 685 686 switch ((reply[0] >> 4) & DP_AUX_NATIVE_REPLY_MASK) { 687 case DP_AUX_NATIVE_REPLY_ACK: 688 /* I2C-over-AUX Reply field is only valid 689 * when paired with AUX ACK. 690 */ 691 break; 692 case DP_AUX_NATIVE_REPLY_NACK: 693 DRM_DEBUG_KMS("aux_ch native nack\n"); 694 ret = -EREMOTEIO; 695 goto out; 696 case DP_AUX_NATIVE_REPLY_DEFER: 697 /* 698 * For now, just give more slack to branch devices. We 699 * could check the DPCD for I2C bit rate capabilities, 700 * and if available, adjust the interval. We could also 701 * be more careful with DP-to-Legacy adapters where a 702 * long legacy cable may force very low I2C bit rates. 703 */ 704 if (intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] & 705 DP_DWN_STRM_PORT_PRESENT) 706 usleep_range(500, 600); 707 else 708 usleep_range(300, 400); 709 continue; 710 default: 711 DRM_ERROR("aux_ch invalid native reply 0x%02x\n", 712 reply[0]); 713 ret = -EREMOTEIO; 714 goto out; 715 } 716 717 switch ((reply[0] >> 4) & DP_AUX_I2C_REPLY_MASK) { 718 case DP_AUX_I2C_REPLY_ACK: 719 if (mode == MODE_I2C_READ) { 720 *read_byte = reply[1]; 721 } 722 ret = reply_bytes - 1; 723 goto out; 724 case DP_AUX_I2C_REPLY_NACK: 725 DRM_DEBUG_KMS("aux_i2c nack\n"); 726 ret = -EREMOTEIO; 727 goto out; 728 case DP_AUX_I2C_REPLY_DEFER: 729 DRM_DEBUG_KMS("aux_i2c defer\n"); 730 udelay(100); 731 break; 732 default: 733 DRM_ERROR("aux_i2c invalid reply 0x%02x\n", reply[0]); 734 ret = -EREMOTEIO; 735 goto out; 736 } 737 } 738 739 DRM_ERROR("too many retries, giving up\n"); 740 ret = -EREMOTEIO; 741 742out: 743 ironlake_edp_panel_vdd_off(intel_dp, false); 744 return ret; 745} 746 747static int 748intel_dp_i2c_init(struct intel_dp *intel_dp, 749 struct intel_connector *intel_connector, const char *name) 750{ 751 int ret; 752 753 DRM_DEBUG_KMS("i2c_init %s\n", name); 754 intel_dp->algo.running = false; 755 intel_dp->algo.address = 0; 756 intel_dp->algo.aux_ch = intel_dp_i2c_aux_ch; 757 758 memset(&intel_dp->adapter, '\0', sizeof(intel_dp->adapter)); 759 intel_dp->adapter.owner = THIS_MODULE; 760 intel_dp->adapter.class = I2C_CLASS_DDC; 761 strncpy(intel_dp->adapter.name, name, sizeof(intel_dp->adapter.name) - 1); 762 intel_dp->adapter.name[sizeof(intel_dp->adapter.name) - 1] = '\0'; 763 intel_dp->adapter.algo_data = &intel_dp->algo; 764 intel_dp->adapter.dev.parent = intel_connector->base.kdev; 765 766 ret = i2c_dp_aux_add_bus(&intel_dp->adapter); 767 return ret; 768} 769 770static void 771intel_dp_set_clock(struct intel_encoder *encoder, 772 struct intel_crtc_config *pipe_config, int link_bw) 773{ 774 struct drm_device *dev = encoder->base.dev; 775 const struct dp_link_dpll *divisor = NULL; 776 int i, count = 0; 777 778 if (IS_G4X(dev)) { 779 divisor = gen4_dpll; 780 count = ARRAY_SIZE(gen4_dpll); 781 } else if (IS_HASWELL(dev)) { 782 /* Haswell has special-purpose DP DDI clocks. */ 783 } else if (HAS_PCH_SPLIT(dev)) { 784 divisor = pch_dpll; 785 count = ARRAY_SIZE(pch_dpll); 786 } else if (IS_VALLEYVIEW(dev)) { 787 divisor = vlv_dpll; 788 count = ARRAY_SIZE(vlv_dpll); 789 } 790 791 if (divisor && count) { 792 for (i = 0; i < count; i++) { 793 if (link_bw == divisor[i].link_bw) { 794 pipe_config->dpll = divisor[i].dpll; 795 pipe_config->clock_set = true; 796 break; 797 } 798 } 799 } 800} 801 802bool 803intel_dp_compute_config(struct intel_encoder *encoder, 804 struct intel_crtc_config *pipe_config) 805{ 806 struct drm_device *dev = encoder->base.dev; 807 struct drm_i915_private *dev_priv = dev->dev_private; 808 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode; 809 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); 810 enum port port = dp_to_dig_port(intel_dp)->port; 811 struct intel_crtc *intel_crtc = encoder->new_crtc; 812 struct intel_connector *intel_connector = intel_dp->attached_connector; 813 int lane_count, clock; 814 int max_lane_count = drm_dp_max_lane_count(intel_dp->dpcd); 815 int max_clock = intel_dp_max_link_bw(intel_dp) == DP_LINK_BW_2_7 ? 1 : 0; 816 int bpp, mode_rate; 817 static int bws[2] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7 }; 818 int link_avail, link_clock; 819 820 if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev) && port != PORT_A) 821 pipe_config->has_pch_encoder = true; 822 823 pipe_config->has_dp_encoder = true; 824 825 if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) { 826 intel_fixed_panel_mode(intel_connector->panel.fixed_mode, 827 adjusted_mode); 828 if (!HAS_PCH_SPLIT(dev)) 829 intel_gmch_panel_fitting(intel_crtc, pipe_config, 830 intel_connector->panel.fitting_mode); 831 else 832 intel_pch_panel_fitting(intel_crtc, pipe_config, 833 intel_connector->panel.fitting_mode); 834 } 835 836 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK) 837 return false; 838 839 DRM_DEBUG_KMS("DP link computation with max lane count %i " 840 "max bw %02x pixel clock %iKHz\n", 841 max_lane_count, bws[max_clock], 842 adjusted_mode->crtc_clock); 843 844 /* Walk through all bpp values. Luckily they're all nicely spaced with 2 845 * bpc in between. */ 846 bpp = pipe_config->pipe_bpp; 847 if (is_edp(intel_dp) && dev_priv->vbt.edp_bpp && 848 dev_priv->vbt.edp_bpp < bpp) { 849 DRM_DEBUG_KMS("clamping bpp for eDP panel to BIOS-provided %i\n", 850 dev_priv->vbt.edp_bpp); 851 bpp = dev_priv->vbt.edp_bpp; 852 } 853 854 for (; bpp >= 6*3; bpp -= 2*3) { 855 mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock, 856 bpp); 857 858 for (clock = 0; clock <= max_clock; clock++) { 859 for (lane_count = 1; lane_count <= max_lane_count; lane_count <<= 1) { 860 link_clock = drm_dp_bw_code_to_link_rate(bws[clock]); 861 link_avail = intel_dp_max_data_rate(link_clock, 862 lane_count); 863 864 if (mode_rate <= link_avail) { 865 goto found; 866 } 867 } 868 } 869 } 870 871 return false; 872 873found: 874 if (intel_dp->color_range_auto) { 875 /* 876 * See: 877 * CEA-861-E - 5.1 Default Encoding Parameters 878 * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry 879 */ 880 if (bpp != 18 && drm_match_cea_mode(adjusted_mode) > 1) 881 intel_dp->color_range = DP_COLOR_RANGE_16_235; 882 else 883 intel_dp->color_range = 0; 884 } 885 886 if (intel_dp->color_range) 887 pipe_config->limited_color_range = true; 888 889 intel_dp->link_bw = bws[clock]; 890 intel_dp->lane_count = lane_count; 891 pipe_config->pipe_bpp = bpp; 892 pipe_config->port_clock = drm_dp_bw_code_to_link_rate(intel_dp->link_bw); 893 894 DRM_DEBUG_KMS("DP link bw %02x lane count %d clock %d bpp %d\n", 895 intel_dp->link_bw, intel_dp->lane_count, 896 pipe_config->port_clock, bpp); 897 DRM_DEBUG_KMS("DP link bw required %i available %i\n", 898 mode_rate, link_avail); 899 900 intel_link_compute_m_n(bpp, lane_count, 901 adjusted_mode->crtc_clock, 902 pipe_config->port_clock, 903 &pipe_config->dp_m_n); 904 905 intel_dp_set_clock(encoder, pipe_config, intel_dp->link_bw); 906 907 return true; 908} 909 910static void ironlake_set_pll_cpu_edp(struct intel_dp *intel_dp) 911{ 912 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 913 struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc); 914 struct drm_device *dev = crtc->base.dev; 915 struct drm_i915_private *dev_priv = dev->dev_private; 916 u32 dpa_ctl; 917 918 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", crtc->config.port_clock); 919 dpa_ctl = I915_READ(DP_A); 920 dpa_ctl &= ~DP_PLL_FREQ_MASK; 921 922 if (crtc->config.port_clock == 162000) { 923 /* For a long time we've carried around a ILK-DevA w/a for the 924 * 160MHz clock. If we're really unlucky, it's still required. 925 */ 926 DRM_DEBUG_KMS("160MHz cpu eDP clock, might need ilk devA w/a\n"); 927 dpa_ctl |= DP_PLL_FREQ_160MHZ; 928 intel_dp->DP |= DP_PLL_FREQ_160MHZ; 929 } else { 930 dpa_ctl |= DP_PLL_FREQ_270MHZ; 931 intel_dp->DP |= DP_PLL_FREQ_270MHZ; 932 } 933 934 I915_WRITE(DP_A, dpa_ctl); 935 936 POSTING_READ(DP_A); 937 udelay(500); 938} 939 940static void intel_dp_mode_set(struct intel_encoder *encoder) 941{ 942 struct drm_device *dev = encoder->base.dev; 943 struct drm_i915_private *dev_priv = dev->dev_private; 944 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); 945 enum port port = dp_to_dig_port(intel_dp)->port; 946 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); 947 struct drm_display_mode *adjusted_mode = &crtc->config.adjusted_mode; 948 949 /* 950 * There are four kinds of DP registers: 951 * 952 * IBX PCH 953 * SNB CPU 954 * IVB CPU 955 * CPT PCH 956 * 957 * IBX PCH and CPU are the same for almost everything, 958 * except that the CPU DP PLL is configured in this 959 * register 960 * 961 * CPT PCH is quite different, having many bits moved 962 * to the TRANS_DP_CTL register instead. That 963 * configuration happens (oddly) in ironlake_pch_enable 964 */ 965 966 /* Preserve the BIOS-computed detected bit. This is 967 * supposed to be read-only. 968 */ 969 intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED; 970 971 /* Handle DP bits in common between all three register formats */ 972 intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0; 973 intel_dp->DP |= DP_PORT_WIDTH(intel_dp->lane_count); 974 975 if (intel_dp->has_audio) { 976 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n", 977 pipe_name(crtc->pipe)); 978 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE; 979 intel_write_eld(&encoder->base, adjusted_mode); 980 } 981 982 /* Split out the IBX/CPU vs CPT settings */ 983 984 if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) { 985 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) 986 intel_dp->DP |= DP_SYNC_HS_HIGH; 987 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) 988 intel_dp->DP |= DP_SYNC_VS_HIGH; 989 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT; 990 991 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd)) 992 intel_dp->DP |= DP_ENHANCED_FRAMING; 993 994 intel_dp->DP |= crtc->pipe << 29; 995 } else if (!HAS_PCH_CPT(dev) || port == PORT_A) { 996 if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev)) 997 intel_dp->DP |= intel_dp->color_range; 998 999 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) 1000 intel_dp->DP |= DP_SYNC_HS_HIGH; 1001 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) 1002 intel_dp->DP |= DP_SYNC_VS_HIGH; 1003 intel_dp->DP |= DP_LINK_TRAIN_OFF; 1004 1005 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd)) 1006 intel_dp->DP |= DP_ENHANCED_FRAMING; 1007 1008 if (crtc->pipe == 1) 1009 intel_dp->DP |= DP_PIPEB_SELECT; 1010 } else { 1011 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT; 1012 } 1013 1014 if (port == PORT_A && !IS_VALLEYVIEW(dev)) 1015 ironlake_set_pll_cpu_edp(intel_dp); 1016} 1017 1018#define IDLE_ON_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK) 1019#define IDLE_ON_VALUE (PP_ON | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE) 1020 1021#define IDLE_OFF_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK) 1022#define IDLE_OFF_VALUE (0 | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE) 1023 1024#define IDLE_CYCLE_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK) 1025#define IDLE_CYCLE_VALUE (0 | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE) 1026 1027static void ironlake_wait_panel_status(struct intel_dp *intel_dp, 1028 u32 mask, 1029 u32 value) 1030{ 1031 struct drm_device *dev = intel_dp_to_dev(intel_dp); 1032 struct drm_i915_private *dev_priv = dev->dev_private; 1033 u32 pp_stat_reg, pp_ctrl_reg; 1034 1035 pp_stat_reg = _pp_stat_reg(intel_dp); 1036 pp_ctrl_reg = _pp_ctrl_reg(intel_dp); 1037 1038 DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n", 1039 mask, value, 1040 I915_READ(pp_stat_reg), 1041 I915_READ(pp_ctrl_reg)); 1042 1043 if (_wait_for((I915_READ(pp_stat_reg) & mask) == value, 5000, 10)) { 1044 DRM_ERROR("Panel status timeout: status %08x control %08x\n", 1045 I915_READ(pp_stat_reg), 1046 I915_READ(pp_ctrl_reg)); 1047 } 1048 1049 DRM_DEBUG_KMS("Wait complete\n"); 1050} 1051 1052static void ironlake_wait_panel_on(struct intel_dp *intel_dp) 1053{ 1054 DRM_DEBUG_KMS("Wait for panel power on\n"); 1055 ironlake_wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE); 1056} 1057 1058static void ironlake_wait_panel_off(struct intel_dp *intel_dp) 1059{ 1060 DRM_DEBUG_KMS("Wait for panel power off time\n"); 1061 ironlake_wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE); 1062} 1063 1064static void ironlake_wait_panel_power_cycle(struct intel_dp *intel_dp) 1065{ 1066 DRM_DEBUG_KMS("Wait for panel power cycle\n"); 1067 ironlake_wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE); 1068} 1069 1070 1071/* Read the current pp_control value, unlocking the register if it 1072 * is locked 1073 */ 1074 1075static u32 ironlake_get_pp_control(struct intel_dp *intel_dp) 1076{ 1077 struct drm_device *dev = intel_dp_to_dev(intel_dp); 1078 struct drm_i915_private *dev_priv = dev->dev_private; 1079 u32 control; 1080 1081 control = I915_READ(_pp_ctrl_reg(intel_dp)); 1082 control &= ~PANEL_UNLOCK_MASK; 1083 control |= PANEL_UNLOCK_REGS; 1084 return control; 1085} 1086 1087void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp) 1088{ 1089 struct drm_device *dev = intel_dp_to_dev(intel_dp); 1090 struct drm_i915_private *dev_priv = dev->dev_private; 1091 u32 pp; 1092 u32 pp_stat_reg, pp_ctrl_reg; 1093 1094 if (!is_edp(intel_dp)) 1095 return; 1096 1097 WARN(intel_dp->want_panel_vdd, 1098 "eDP VDD already requested on\n"); 1099 1100 intel_dp->want_panel_vdd = true; 1101 1102 if (ironlake_edp_have_panel_vdd(intel_dp)) 1103 return; 1104 1105 intel_runtime_pm_get(dev_priv); 1106 1107 DRM_DEBUG_KMS("Turning eDP VDD on\n"); 1108 1109 if (!ironlake_edp_have_panel_power(intel_dp)) 1110 ironlake_wait_panel_power_cycle(intel_dp); 1111 1112 pp = ironlake_get_pp_control(intel_dp); 1113 pp |= EDP_FORCE_VDD; 1114 1115 pp_stat_reg = _pp_stat_reg(intel_dp); 1116 pp_ctrl_reg = _pp_ctrl_reg(intel_dp); 1117 1118 I915_WRITE(pp_ctrl_reg, pp); 1119 POSTING_READ(pp_ctrl_reg); 1120 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n", 1121 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg)); 1122 /* 1123 * If the panel wasn't on, delay before accessing aux channel 1124 */ 1125 if (!ironlake_edp_have_panel_power(intel_dp)) { 1126 DRM_DEBUG_KMS("eDP was not running\n"); 1127 msleep(intel_dp->panel_power_up_delay); 1128 } 1129} 1130 1131static void ironlake_panel_vdd_off_sync(struct intel_dp *intel_dp) 1132{ 1133 struct drm_device *dev = intel_dp_to_dev(intel_dp); 1134 struct drm_i915_private *dev_priv = dev->dev_private; 1135 u32 pp; 1136 u32 pp_stat_reg, pp_ctrl_reg; 1137 1138 WARN_ON(!mutex_is_locked(&dev->mode_config.mutex)); 1139 1140 if (!intel_dp->want_panel_vdd && ironlake_edp_have_panel_vdd(intel_dp)) { 1141 DRM_DEBUG_KMS("Turning eDP VDD off\n"); 1142 1143 pp = ironlake_get_pp_control(intel_dp); 1144 pp &= ~EDP_FORCE_VDD; 1145 1146 pp_ctrl_reg = _pp_ctrl_reg(intel_dp); 1147 pp_stat_reg = _pp_stat_reg(intel_dp); 1148 1149 I915_WRITE(pp_ctrl_reg, pp); 1150 POSTING_READ(pp_ctrl_reg); 1151 1152 /* Make sure sequencer is idle before allowing subsequent activity */ 1153 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n", 1154 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg)); 1155 1156 if ((pp & POWER_TARGET_ON) == 0) 1157 msleep(intel_dp->panel_power_cycle_delay); 1158 1159 intel_runtime_pm_put(dev_priv); 1160 } 1161} 1162 1163static void ironlake_panel_vdd_work(struct work_struct *__work) 1164{ 1165 struct intel_dp *intel_dp = container_of(to_delayed_work(__work), 1166 struct intel_dp, panel_vdd_work); 1167 struct drm_device *dev = intel_dp_to_dev(intel_dp); 1168 1169 mutex_lock(&dev->mode_config.mutex); 1170 ironlake_panel_vdd_off_sync(intel_dp); 1171 mutex_unlock(&dev->mode_config.mutex); 1172} 1173 1174void ironlake_edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync) 1175{ 1176 if (!is_edp(intel_dp)) 1177 return; 1178 1179 WARN(!intel_dp->want_panel_vdd, "eDP VDD not forced on"); 1180 1181 intel_dp->want_panel_vdd = false; 1182 1183 if (sync) { 1184 ironlake_panel_vdd_off_sync(intel_dp); 1185 } else { 1186 /* 1187 * Queue the timer to fire a long 1188 * time from now (relative to the power down delay) 1189 * to keep the panel power up across a sequence of operations 1190 */ 1191 schedule_delayed_work(&intel_dp->panel_vdd_work, 1192 msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5)); 1193 } 1194} 1195 1196void ironlake_edp_panel_on(struct intel_dp *intel_dp) 1197{ 1198 struct drm_device *dev = intel_dp_to_dev(intel_dp); 1199 struct drm_i915_private *dev_priv = dev->dev_private; 1200 u32 pp; 1201 u32 pp_ctrl_reg; 1202 1203 if (!is_edp(intel_dp)) 1204 return; 1205 1206 DRM_DEBUG_KMS("Turn eDP power on\n"); 1207 1208 if (ironlake_edp_have_panel_power(intel_dp)) { 1209 DRM_DEBUG_KMS("eDP power already on\n"); 1210 return; 1211 } 1212 1213 ironlake_wait_panel_power_cycle(intel_dp); 1214 1215 pp_ctrl_reg = _pp_ctrl_reg(intel_dp); 1216 pp = ironlake_get_pp_control(intel_dp); 1217 if (IS_GEN5(dev)) { 1218 /* ILK workaround: disable reset around power sequence */ 1219 pp &= ~PANEL_POWER_RESET; 1220 I915_WRITE(pp_ctrl_reg, pp); 1221 POSTING_READ(pp_ctrl_reg); 1222 } 1223 1224 pp |= POWER_TARGET_ON; 1225 if (!IS_GEN5(dev)) 1226 pp |= PANEL_POWER_RESET; 1227 1228 I915_WRITE(pp_ctrl_reg, pp); 1229 POSTING_READ(pp_ctrl_reg); 1230 1231 ironlake_wait_panel_on(intel_dp); 1232 1233 if (IS_GEN5(dev)) { 1234 pp |= PANEL_POWER_RESET; /* restore panel reset bit */ 1235 I915_WRITE(pp_ctrl_reg, pp); 1236 POSTING_READ(pp_ctrl_reg); 1237 } 1238} 1239 1240void ironlake_edp_panel_off(struct intel_dp *intel_dp) 1241{ 1242 struct drm_device *dev = intel_dp_to_dev(intel_dp); 1243 struct drm_i915_private *dev_priv = dev->dev_private; 1244 u32 pp; 1245 u32 pp_ctrl_reg; 1246 1247 if (!is_edp(intel_dp)) 1248 return; 1249 1250 DRM_DEBUG_KMS("Turn eDP power off\n"); 1251 1252 pp = ironlake_get_pp_control(intel_dp); 1253 /* We need to switch off panel power _and_ force vdd, for otherwise some 1254 * panels get very unhappy and cease to work. */ 1255 pp &= ~(POWER_TARGET_ON | PANEL_POWER_RESET | EDP_BLC_ENABLE); 1256 1257 pp_ctrl_reg = _pp_ctrl_reg(intel_dp); 1258 1259 I915_WRITE(pp_ctrl_reg, pp); 1260 POSTING_READ(pp_ctrl_reg); 1261 1262 ironlake_wait_panel_off(intel_dp); 1263} 1264 1265void ironlake_edp_backlight_on(struct intel_dp *intel_dp) 1266{ 1267 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 1268 struct drm_device *dev = intel_dig_port->base.base.dev; 1269 struct drm_i915_private *dev_priv = dev->dev_private; 1270 u32 pp; 1271 u32 pp_ctrl_reg; 1272 1273 if (!is_edp(intel_dp)) 1274 return; 1275 1276 DRM_DEBUG_KMS("\n"); 1277 /* 1278 * If we enable the backlight right away following a panel power 1279 * on, we may see slight flicker as the panel syncs with the eDP 1280 * link. So delay a bit to make sure the image is solid before 1281 * allowing it to appear. 1282 */ 1283 msleep(intel_dp->backlight_on_delay); 1284 pp = ironlake_get_pp_control(intel_dp); 1285 pp |= EDP_BLC_ENABLE; 1286 1287 pp_ctrl_reg = _pp_ctrl_reg(intel_dp); 1288 1289 I915_WRITE(pp_ctrl_reg, pp); 1290 POSTING_READ(pp_ctrl_reg); 1291 1292 intel_panel_enable_backlight(intel_dp->attached_connector); 1293} 1294 1295void ironlake_edp_backlight_off(struct intel_dp *intel_dp) 1296{ 1297 struct drm_device *dev = intel_dp_to_dev(intel_dp); 1298 struct drm_i915_private *dev_priv = dev->dev_private; 1299 u32 pp; 1300 u32 pp_ctrl_reg; 1301 1302 if (!is_edp(intel_dp)) 1303 return; 1304 1305 intel_panel_disable_backlight(intel_dp->attached_connector); 1306 1307 DRM_DEBUG_KMS("\n"); 1308 pp = ironlake_get_pp_control(intel_dp); 1309 pp &= ~EDP_BLC_ENABLE; 1310 1311 pp_ctrl_reg = _pp_ctrl_reg(intel_dp); 1312 1313 I915_WRITE(pp_ctrl_reg, pp); 1314 POSTING_READ(pp_ctrl_reg); 1315 msleep(intel_dp->backlight_off_delay); 1316} 1317 1318static void ironlake_edp_pll_on(struct intel_dp *intel_dp) 1319{ 1320 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 1321 struct drm_crtc *crtc = intel_dig_port->base.base.crtc; 1322 struct drm_device *dev = crtc->dev; 1323 struct drm_i915_private *dev_priv = dev->dev_private; 1324 u32 dpa_ctl; 1325 1326 assert_pipe_disabled(dev_priv, 1327 to_intel_crtc(crtc)->pipe); 1328 1329 DRM_DEBUG_KMS("\n"); 1330 dpa_ctl = I915_READ(DP_A); 1331 WARN(dpa_ctl & DP_PLL_ENABLE, "dp pll on, should be off\n"); 1332 WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n"); 1333 1334 /* We don't adjust intel_dp->DP while tearing down the link, to 1335 * facilitate link retraining (e.g. after hotplug). Hence clear all 1336 * enable bits here to ensure that we don't enable too much. */ 1337 intel_dp->DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE); 1338 intel_dp->DP |= DP_PLL_ENABLE; 1339 I915_WRITE(DP_A, intel_dp->DP); 1340 POSTING_READ(DP_A); 1341 udelay(200); 1342} 1343 1344static void ironlake_edp_pll_off(struct intel_dp *intel_dp) 1345{ 1346 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 1347 struct drm_crtc *crtc = intel_dig_port->base.base.crtc; 1348 struct drm_device *dev = crtc->dev; 1349 struct drm_i915_private *dev_priv = dev->dev_private; 1350 u32 dpa_ctl; 1351 1352 assert_pipe_disabled(dev_priv, 1353 to_intel_crtc(crtc)->pipe); 1354 1355 dpa_ctl = I915_READ(DP_A); 1356 WARN((dpa_ctl & DP_PLL_ENABLE) == 0, 1357 "dp pll off, should be on\n"); 1358 WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n"); 1359 1360 /* We can't rely on the value tracked for the DP register in 1361 * intel_dp->DP because link_down must not change that (otherwise link 1362 * re-training will fail. */ 1363 dpa_ctl &= ~DP_PLL_ENABLE; 1364 I915_WRITE(DP_A, dpa_ctl); 1365 POSTING_READ(DP_A); 1366 udelay(200); 1367} 1368 1369/* If the sink supports it, try to set the power state appropriately */ 1370void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode) 1371{ 1372 int ret, i; 1373 1374 /* Should have a valid DPCD by this point */ 1375 if (intel_dp->dpcd[DP_DPCD_REV] < 0x11) 1376 return; 1377 1378 if (mode != DRM_MODE_DPMS_ON) { 1379 ret = intel_dp_aux_native_write_1(intel_dp, DP_SET_POWER, 1380 DP_SET_POWER_D3); 1381 if (ret != 1) 1382 DRM_DEBUG_DRIVER("failed to write sink power state\n"); 1383 } else { 1384 /* 1385 * When turning on, we need to retry for 1ms to give the sink 1386 * time to wake up. 1387 */ 1388 for (i = 0; i < 3; i++) { 1389 ret = intel_dp_aux_native_write_1(intel_dp, 1390 DP_SET_POWER, 1391 DP_SET_POWER_D0); 1392 if (ret == 1) 1393 break; 1394 msleep(1); 1395 } 1396 } 1397} 1398 1399static bool intel_dp_get_hw_state(struct intel_encoder *encoder, 1400 enum pipe *pipe) 1401{ 1402 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); 1403 enum port port = dp_to_dig_port(intel_dp)->port; 1404 struct drm_device *dev = encoder->base.dev; 1405 struct drm_i915_private *dev_priv = dev->dev_private; 1406 u32 tmp = I915_READ(intel_dp->output_reg); 1407 1408 if (!(tmp & DP_PORT_EN)) 1409 return false; 1410 1411 if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) { 1412 *pipe = PORT_TO_PIPE_CPT(tmp); 1413 } else if (!HAS_PCH_CPT(dev) || port == PORT_A) { 1414 *pipe = PORT_TO_PIPE(tmp); 1415 } else { 1416 u32 trans_sel; 1417 u32 trans_dp; 1418 int i; 1419 1420 switch (intel_dp->output_reg) { 1421 case PCH_DP_B: 1422 trans_sel = TRANS_DP_PORT_SEL_B; 1423 break; 1424 case PCH_DP_C: 1425 trans_sel = TRANS_DP_PORT_SEL_C; 1426 break; 1427 case PCH_DP_D: 1428 trans_sel = TRANS_DP_PORT_SEL_D; 1429 break; 1430 default: 1431 return true; 1432 } 1433 1434 for_each_pipe(i) { 1435 trans_dp = I915_READ(TRANS_DP_CTL(i)); 1436 if ((trans_dp & TRANS_DP_PORT_SEL_MASK) == trans_sel) { 1437 *pipe = i; 1438 return true; 1439 } 1440 } 1441 1442 DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n", 1443 intel_dp->output_reg); 1444 } 1445 1446 return true; 1447} 1448 1449static void intel_dp_get_config(struct intel_encoder *encoder, 1450 struct intel_crtc_config *pipe_config) 1451{ 1452 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); 1453 u32 tmp, flags = 0; 1454 struct drm_device *dev = encoder->base.dev; 1455 struct drm_i915_private *dev_priv = dev->dev_private; 1456 enum port port = dp_to_dig_port(intel_dp)->port; 1457 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); 1458 int dotclock; 1459 1460 if ((port == PORT_A) || !HAS_PCH_CPT(dev)) { 1461 tmp = I915_READ(intel_dp->output_reg); 1462 if (tmp & DP_SYNC_HS_HIGH) 1463 flags |= DRM_MODE_FLAG_PHSYNC; 1464 else 1465 flags |= DRM_MODE_FLAG_NHSYNC; 1466 1467 if (tmp & DP_SYNC_VS_HIGH) 1468 flags |= DRM_MODE_FLAG_PVSYNC; 1469 else 1470 flags |= DRM_MODE_FLAG_NVSYNC; 1471 } else { 1472 tmp = I915_READ(TRANS_DP_CTL(crtc->pipe)); 1473 if (tmp & TRANS_DP_HSYNC_ACTIVE_HIGH) 1474 flags |= DRM_MODE_FLAG_PHSYNC; 1475 else 1476 flags |= DRM_MODE_FLAG_NHSYNC; 1477 1478 if (tmp & TRANS_DP_VSYNC_ACTIVE_HIGH) 1479 flags |= DRM_MODE_FLAG_PVSYNC; 1480 else 1481 flags |= DRM_MODE_FLAG_NVSYNC; 1482 } 1483 1484 pipe_config->adjusted_mode.flags |= flags; 1485 1486 pipe_config->has_dp_encoder = true; 1487 1488 intel_dp_get_m_n(crtc, pipe_config); 1489 1490 if (port == PORT_A) { 1491 if ((I915_READ(DP_A) & DP_PLL_FREQ_MASK) == DP_PLL_FREQ_160MHZ) 1492 pipe_config->port_clock = 162000; 1493 else 1494 pipe_config->port_clock = 270000; 1495 } 1496 1497 dotclock = intel_dotclock_calculate(pipe_config->port_clock, 1498 &pipe_config->dp_m_n); 1499 1500 if (HAS_PCH_SPLIT(dev_priv->dev) && port != PORT_A) 1501 ironlake_check_encoder_dotclock(pipe_config, dotclock); 1502 1503 pipe_config->adjusted_mode.crtc_clock = dotclock; 1504 1505 if (is_edp(intel_dp) && dev_priv->vbt.edp_bpp && 1506 pipe_config->pipe_bpp > dev_priv->vbt.edp_bpp) { 1507 /* 1508 * This is a big fat ugly hack. 1509 * 1510 * Some machines in UEFI boot mode provide us a VBT that has 18 1511 * bpp and 1.62 GHz link bandwidth for eDP, which for reasons 1512 * unknown we fail to light up. Yet the same BIOS boots up with 1513 * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as 1514 * max, not what it tells us to use. 1515 * 1516 * Note: This will still be broken if the eDP panel is not lit 1517 * up by the BIOS, and thus we can't get the mode at module 1518 * load. 1519 */ 1520 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n", 1521 pipe_config->pipe_bpp, dev_priv->vbt.edp_bpp); 1522 dev_priv->vbt.edp_bpp = pipe_config->pipe_bpp; 1523 } 1524} 1525 1526static bool is_edp_psr(struct drm_device *dev) 1527{ 1528 struct drm_i915_private *dev_priv = dev->dev_private; 1529 1530 return dev_priv->psr.sink_support; 1531} 1532 1533static bool intel_edp_is_psr_enabled(struct drm_device *dev) 1534{ 1535 struct drm_i915_private *dev_priv = dev->dev_private; 1536 1537 if (!HAS_PSR(dev)) 1538 return false; 1539 1540 return I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE; 1541} 1542 1543static void intel_edp_psr_write_vsc(struct intel_dp *intel_dp, 1544 struct edp_vsc_psr *vsc_psr) 1545{ 1546 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 1547 struct drm_device *dev = dig_port->base.base.dev; 1548 struct drm_i915_private *dev_priv = dev->dev_private; 1549 struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc); 1550 u32 ctl_reg = HSW_TVIDEO_DIP_CTL(crtc->config.cpu_transcoder); 1551 u32 data_reg = HSW_TVIDEO_DIP_VSC_DATA(crtc->config.cpu_transcoder); 1552 uint32_t *data = (uint32_t *) vsc_psr; 1553 unsigned int i; 1554 1555 /* As per BSPec (Pipe Video Data Island Packet), we need to disable 1556 the video DIP being updated before program video DIP data buffer 1557 registers for DIP being updated. */ 1558 I915_WRITE(ctl_reg, 0); 1559 POSTING_READ(ctl_reg); 1560 1561 for (i = 0; i < VIDEO_DIP_VSC_DATA_SIZE; i += 4) { 1562 if (i < sizeof(struct edp_vsc_psr)) 1563 I915_WRITE(data_reg + i, *data++); 1564 else 1565 I915_WRITE(data_reg + i, 0); 1566 } 1567 1568 I915_WRITE(ctl_reg, VIDEO_DIP_ENABLE_VSC_HSW); 1569 POSTING_READ(ctl_reg); 1570} 1571 1572static void intel_edp_psr_setup(struct intel_dp *intel_dp) 1573{ 1574 struct drm_device *dev = intel_dp_to_dev(intel_dp); 1575 struct drm_i915_private *dev_priv = dev->dev_private; 1576 struct edp_vsc_psr psr_vsc; 1577 1578 if (intel_dp->psr_setup_done) 1579 return; 1580 1581 /* Prepare VSC packet as per EDP 1.3 spec, Table 3.10 */ 1582 memset(&psr_vsc, 0, sizeof(psr_vsc)); 1583 psr_vsc.sdp_header.HB0 = 0; 1584 psr_vsc.sdp_header.HB1 = 0x7; 1585 psr_vsc.sdp_header.HB2 = 0x2; 1586 psr_vsc.sdp_header.HB3 = 0x8; 1587 intel_edp_psr_write_vsc(intel_dp, &psr_vsc); 1588 1589 /* Avoid continuous PSR exit by masking memup and hpd */ 1590 I915_WRITE(EDP_PSR_DEBUG_CTL(dev), EDP_PSR_DEBUG_MASK_MEMUP | 1591 EDP_PSR_DEBUG_MASK_HPD | EDP_PSR_DEBUG_MASK_LPSP); 1592 1593 intel_dp->psr_setup_done = true; 1594} 1595 1596static void intel_edp_psr_enable_sink(struct intel_dp *intel_dp) 1597{ 1598 struct drm_device *dev = intel_dp_to_dev(intel_dp); 1599 struct drm_i915_private *dev_priv = dev->dev_private; 1600 uint32_t aux_clock_divider = get_aux_clock_divider(intel_dp, 0); 1601 int precharge = 0x3; 1602 int msg_size = 5; /* Header(4) + Message(1) */ 1603 1604 /* Enable PSR in sink */ 1605 if (intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT) 1606 intel_dp_aux_native_write_1(intel_dp, DP_PSR_EN_CFG, 1607 DP_PSR_ENABLE & 1608 ~DP_PSR_MAIN_LINK_ACTIVE); 1609 else 1610 intel_dp_aux_native_write_1(intel_dp, DP_PSR_EN_CFG, 1611 DP_PSR_ENABLE | 1612 DP_PSR_MAIN_LINK_ACTIVE); 1613 1614 /* Setup AUX registers */ 1615 I915_WRITE(EDP_PSR_AUX_DATA1(dev), EDP_PSR_DPCD_COMMAND); 1616 I915_WRITE(EDP_PSR_AUX_DATA2(dev), EDP_PSR_DPCD_NORMAL_OPERATION); 1617 I915_WRITE(EDP_PSR_AUX_CTL(dev), 1618 DP_AUX_CH_CTL_TIME_OUT_400us | 1619 (msg_size << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) | 1620 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) | 1621 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT)); 1622} 1623 1624static void intel_edp_psr_enable_source(struct intel_dp *intel_dp) 1625{ 1626 struct drm_device *dev = intel_dp_to_dev(intel_dp); 1627 struct drm_i915_private *dev_priv = dev->dev_private; 1628 uint32_t max_sleep_time = 0x1f; 1629 uint32_t idle_frames = 1; 1630 uint32_t val = 0x0; 1631 const uint32_t link_entry_time = EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES; 1632 1633 if (intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT) { 1634 val |= EDP_PSR_LINK_STANDBY; 1635 val |= EDP_PSR_TP2_TP3_TIME_0us; 1636 val |= EDP_PSR_TP1_TIME_0us; 1637 val |= EDP_PSR_SKIP_AUX_EXIT; 1638 } else 1639 val |= EDP_PSR_LINK_DISABLE; 1640 1641 I915_WRITE(EDP_PSR_CTL(dev), val | 1642 IS_BROADWELL(dev) ? 0 : link_entry_time | 1643 max_sleep_time << EDP_PSR_MAX_SLEEP_TIME_SHIFT | 1644 idle_frames << EDP_PSR_IDLE_FRAME_SHIFT | 1645 EDP_PSR_ENABLE); 1646} 1647 1648static bool intel_edp_psr_match_conditions(struct intel_dp *intel_dp) 1649{ 1650 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 1651 struct drm_device *dev = dig_port->base.base.dev; 1652 struct drm_i915_private *dev_priv = dev->dev_private; 1653 struct drm_crtc *crtc = dig_port->base.base.crtc; 1654 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 1655 struct drm_i915_gem_object *obj = to_intel_framebuffer(crtc->fb)->obj; 1656 struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base; 1657 1658 dev_priv->psr.source_ok = false; 1659 1660 if (!HAS_PSR(dev)) { 1661 DRM_DEBUG_KMS("PSR not supported on this platform\n"); 1662 return false; 1663 } 1664 1665 if ((intel_encoder->type != INTEL_OUTPUT_EDP) || 1666 (dig_port->port != PORT_A)) { 1667 DRM_DEBUG_KMS("HSW ties PSR to DDI A (eDP)\n"); 1668 return false; 1669 } 1670 1671 if (!i915_enable_psr) { 1672 DRM_DEBUG_KMS("PSR disable by flag\n"); 1673 return false; 1674 } 1675 1676 crtc = dig_port->base.base.crtc; 1677 if (crtc == NULL) { 1678 DRM_DEBUG_KMS("crtc not active for PSR\n"); 1679 return false; 1680 } 1681 1682 intel_crtc = to_intel_crtc(crtc); 1683 if (!intel_crtc_active(crtc)) { 1684 DRM_DEBUG_KMS("crtc not active for PSR\n"); 1685 return false; 1686 } 1687 1688 obj = to_intel_framebuffer(crtc->fb)->obj; 1689 if (obj->tiling_mode != I915_TILING_X || 1690 obj->fence_reg == I915_FENCE_REG_NONE) { 1691 DRM_DEBUG_KMS("PSR condition failed: fb not tiled or fenced\n"); 1692 return false; 1693 } 1694 1695 if (I915_READ(SPRCTL(intel_crtc->pipe)) & SPRITE_ENABLE) { 1696 DRM_DEBUG_KMS("PSR condition failed: Sprite is Enabled\n"); 1697 return false; 1698 } 1699 1700 if (I915_READ(HSW_STEREO_3D_CTL(intel_crtc->config.cpu_transcoder)) & 1701 S3D_ENABLE) { 1702 DRM_DEBUG_KMS("PSR condition failed: Stereo 3D is Enabled\n"); 1703 return false; 1704 } 1705 1706 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) { 1707 DRM_DEBUG_KMS("PSR condition failed: Interlaced is Enabled\n"); 1708 return false; 1709 } 1710 1711 dev_priv->psr.source_ok = true; 1712 return true; 1713} 1714 1715static void intel_edp_psr_do_enable(struct intel_dp *intel_dp) 1716{ 1717 struct drm_device *dev = intel_dp_to_dev(intel_dp); 1718 1719 if (!intel_edp_psr_match_conditions(intel_dp) || 1720 intel_edp_is_psr_enabled(dev)) 1721 return; 1722 1723 /* Setup PSR once */ 1724 intel_edp_psr_setup(intel_dp); 1725 1726 /* Enable PSR on the panel */ 1727 intel_edp_psr_enable_sink(intel_dp); 1728 1729 /* Enable PSR on the host */ 1730 intel_edp_psr_enable_source(intel_dp); 1731} 1732 1733void intel_edp_psr_enable(struct intel_dp *intel_dp) 1734{ 1735 struct drm_device *dev = intel_dp_to_dev(intel_dp); 1736 1737 if (intel_edp_psr_match_conditions(intel_dp) && 1738 !intel_edp_is_psr_enabled(dev)) 1739 intel_edp_psr_do_enable(intel_dp); 1740} 1741 1742void intel_edp_psr_disable(struct intel_dp *intel_dp) 1743{ 1744 struct drm_device *dev = intel_dp_to_dev(intel_dp); 1745 struct drm_i915_private *dev_priv = dev->dev_private; 1746 1747 if (!intel_edp_is_psr_enabled(dev)) 1748 return; 1749 1750 I915_WRITE(EDP_PSR_CTL(dev), 1751 I915_READ(EDP_PSR_CTL(dev)) & ~EDP_PSR_ENABLE); 1752 1753 /* Wait till PSR is idle */ 1754 if (_wait_for((I915_READ(EDP_PSR_STATUS_CTL(dev)) & 1755 EDP_PSR_STATUS_STATE_MASK) == 0, 2000, 10)) 1756 DRM_ERROR("Timed out waiting for PSR Idle State\n"); 1757} 1758 1759void intel_edp_psr_update(struct drm_device *dev) 1760{ 1761 struct intel_encoder *encoder; 1762 struct intel_dp *intel_dp = NULL; 1763 1764 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) 1765 if (encoder->type == INTEL_OUTPUT_EDP) { 1766 intel_dp = enc_to_intel_dp(&encoder->base); 1767 1768 if (!is_edp_psr(dev)) 1769 return; 1770 1771 if (!intel_edp_psr_match_conditions(intel_dp)) 1772 intel_edp_psr_disable(intel_dp); 1773 else 1774 if (!intel_edp_is_psr_enabled(dev)) 1775 intel_edp_psr_do_enable(intel_dp); 1776 } 1777} 1778 1779static void intel_disable_dp(struct intel_encoder *encoder) 1780{ 1781 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); 1782 enum port port = dp_to_dig_port(intel_dp)->port; 1783 struct drm_device *dev = encoder->base.dev; 1784 1785 /* Make sure the panel is off before trying to change the mode. But also 1786 * ensure that we have vdd while we switch off the panel. */ 1787 ironlake_edp_backlight_off(intel_dp); 1788 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF); 1789 ironlake_edp_panel_off(intel_dp); 1790 1791 /* cpu edp my only be disable _after_ the cpu pipe/plane is disabled. */ 1792 if (!(port == PORT_A || IS_VALLEYVIEW(dev))) 1793 intel_dp_link_down(intel_dp); 1794} 1795 1796static void intel_post_disable_dp(struct intel_encoder *encoder) 1797{ 1798 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); 1799 enum port port = dp_to_dig_port(intel_dp)->port; 1800 struct drm_device *dev = encoder->base.dev; 1801 1802 if (port == PORT_A || IS_VALLEYVIEW(dev)) { 1803 intel_dp_link_down(intel_dp); 1804 if (!IS_VALLEYVIEW(dev)) 1805 ironlake_edp_pll_off(intel_dp); 1806 } 1807} 1808 1809static void intel_enable_dp(struct intel_encoder *encoder) 1810{ 1811 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); 1812 struct drm_device *dev = encoder->base.dev; 1813 struct drm_i915_private *dev_priv = dev->dev_private; 1814 uint32_t dp_reg = I915_READ(intel_dp->output_reg); 1815 1816 if (WARN_ON(dp_reg & DP_PORT_EN)) 1817 return; 1818 1819 ironlake_edp_panel_vdd_on(intel_dp); 1820 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON); 1821 intel_dp_start_link_train(intel_dp); 1822 ironlake_edp_panel_on(intel_dp); 1823 ironlake_edp_panel_vdd_off(intel_dp, true); 1824 intel_dp_complete_link_train(intel_dp); 1825 intel_dp_stop_link_train(intel_dp); 1826} 1827 1828static void g4x_enable_dp(struct intel_encoder *encoder) 1829{ 1830 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); 1831 1832 intel_enable_dp(encoder); 1833 ironlake_edp_backlight_on(intel_dp); 1834} 1835 1836static void vlv_enable_dp(struct intel_encoder *encoder) 1837{ 1838 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); 1839 1840 ironlake_edp_backlight_on(intel_dp); 1841} 1842 1843static void g4x_pre_enable_dp(struct intel_encoder *encoder) 1844{ 1845 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); 1846 struct intel_digital_port *dport = dp_to_dig_port(intel_dp); 1847 1848 if (dport->port == PORT_A) 1849 ironlake_edp_pll_on(intel_dp); 1850} 1851 1852static void vlv_pre_enable_dp(struct intel_encoder *encoder) 1853{ 1854 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); 1855 struct intel_digital_port *dport = dp_to_dig_port(intel_dp); 1856 struct drm_device *dev = encoder->base.dev; 1857 struct drm_i915_private *dev_priv = dev->dev_private; 1858 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc); 1859 enum dpio_channel port = vlv_dport_to_channel(dport); 1860 int pipe = intel_crtc->pipe; 1861 struct edp_power_seq power_seq; 1862 u32 val; 1863 1864 mutex_lock(&dev_priv->dpio_lock); 1865 1866 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(port)); 1867 val = 0; 1868 if (pipe) 1869 val |= (1<<21); 1870 else 1871 val &= ~(1<<21); 1872 val |= 0x001000c4; 1873 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW8(port), val); 1874 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW14(port), 0x00760018); 1875 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW23(port), 0x00400888); 1876 1877 mutex_unlock(&dev_priv->dpio_lock); 1878 1879 if (is_edp(intel_dp)) { 1880 /* init power sequencer on this pipe and port */ 1881 intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq); 1882 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp, 1883 &power_seq); 1884 } 1885 1886 intel_enable_dp(encoder); 1887 1888 vlv_wait_port_ready(dev_priv, dport); 1889} 1890 1891static void vlv_dp_pre_pll_enable(struct intel_encoder *encoder) 1892{ 1893 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base); 1894 struct drm_device *dev = encoder->base.dev; 1895 struct drm_i915_private *dev_priv = dev->dev_private; 1896 struct intel_crtc *intel_crtc = 1897 to_intel_crtc(encoder->base.crtc); 1898 enum dpio_channel port = vlv_dport_to_channel(dport); 1899 int pipe = intel_crtc->pipe; 1900 1901 /* Program Tx lane resets to default */ 1902 mutex_lock(&dev_priv->dpio_lock); 1903 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port), 1904 DPIO_PCS_TX_LANE2_RESET | 1905 DPIO_PCS_TX_LANE1_RESET); 1906 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port), 1907 DPIO_PCS_CLK_CRI_RXEB_EIOS_EN | 1908 DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN | 1909 (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT) | 1910 DPIO_PCS_CLK_SOFT_RESET); 1911 1912 /* Fix up inter-pair skew failure */ 1913 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW12(port), 0x00750f00); 1914 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW11(port), 0x00001500); 1915 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW14(port), 0x40400000); 1916 mutex_unlock(&dev_priv->dpio_lock); 1917} 1918 1919/* 1920 * Native read with retry for link status and receiver capability reads for 1921 * cases where the sink may still be asleep. 1922 */ 1923static bool 1924intel_dp_aux_native_read_retry(struct intel_dp *intel_dp, uint16_t address, 1925 uint8_t *recv, int recv_bytes) 1926{ 1927 int ret, i; 1928 1929 /* 1930 * Sinks are *supposed* to come up within 1ms from an off state, 1931 * but we're also supposed to retry 3 times per the spec. 1932 */ 1933 for (i = 0; i < 3; i++) { 1934 ret = intel_dp_aux_native_read(intel_dp, address, recv, 1935 recv_bytes); 1936 if (ret == recv_bytes) 1937 return true; 1938 msleep(1); 1939 } 1940 1941 return false; 1942} 1943 1944/* 1945 * Fetch AUX CH registers 0x202 - 0x207 which contain 1946 * link status information 1947 */ 1948static bool 1949intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE]) 1950{ 1951 return intel_dp_aux_native_read_retry(intel_dp, 1952 DP_LANE0_1_STATUS, 1953 link_status, 1954 DP_LINK_STATUS_SIZE); 1955} 1956 1957/* 1958 * These are source-specific values; current Intel hardware supports 1959 * a maximum voltage of 800mV and a maximum pre-emphasis of 6dB 1960 */ 1961 1962static uint8_t 1963intel_dp_voltage_max(struct intel_dp *intel_dp) 1964{ 1965 struct drm_device *dev = intel_dp_to_dev(intel_dp); 1966 enum port port = dp_to_dig_port(intel_dp)->port; 1967 1968 if (IS_VALLEYVIEW(dev) || IS_BROADWELL(dev)) 1969 return DP_TRAIN_VOLTAGE_SWING_1200; 1970 else if (IS_GEN7(dev) && port == PORT_A) 1971 return DP_TRAIN_VOLTAGE_SWING_800; 1972 else if (HAS_PCH_CPT(dev) && port != PORT_A) 1973 return DP_TRAIN_VOLTAGE_SWING_1200; 1974 else 1975 return DP_TRAIN_VOLTAGE_SWING_800; 1976} 1977 1978static uint8_t 1979intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing) 1980{ 1981 struct drm_device *dev = intel_dp_to_dev(intel_dp); 1982 enum port port = dp_to_dig_port(intel_dp)->port; 1983 1984 if (IS_BROADWELL(dev)) { 1985 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) { 1986 case DP_TRAIN_VOLTAGE_SWING_400: 1987 case DP_TRAIN_VOLTAGE_SWING_600: 1988 return DP_TRAIN_PRE_EMPHASIS_6; 1989 case DP_TRAIN_VOLTAGE_SWING_800: 1990 return DP_TRAIN_PRE_EMPHASIS_3_5; 1991 case DP_TRAIN_VOLTAGE_SWING_1200: 1992 default: 1993 return DP_TRAIN_PRE_EMPHASIS_0; 1994 } 1995 } else if (IS_HASWELL(dev)) { 1996 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) { 1997 case DP_TRAIN_VOLTAGE_SWING_400: 1998 return DP_TRAIN_PRE_EMPHASIS_9_5; 1999 case DP_TRAIN_VOLTAGE_SWING_600: 2000 return DP_TRAIN_PRE_EMPHASIS_6; 2001 case DP_TRAIN_VOLTAGE_SWING_800: 2002 return DP_TRAIN_PRE_EMPHASIS_3_5; 2003 case DP_TRAIN_VOLTAGE_SWING_1200: 2004 default: 2005 return DP_TRAIN_PRE_EMPHASIS_0; 2006 } 2007 } else if (IS_VALLEYVIEW(dev)) { 2008 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) { 2009 case DP_TRAIN_VOLTAGE_SWING_400: 2010 return DP_TRAIN_PRE_EMPHASIS_9_5; 2011 case DP_TRAIN_VOLTAGE_SWING_600: 2012 return DP_TRAIN_PRE_EMPHASIS_6; 2013 case DP_TRAIN_VOLTAGE_SWING_800: 2014 return DP_TRAIN_PRE_EMPHASIS_3_5; 2015 case DP_TRAIN_VOLTAGE_SWING_1200: 2016 default: 2017 return DP_TRAIN_PRE_EMPHASIS_0; 2018 } 2019 } else if (IS_GEN7(dev) && port == PORT_A) { 2020 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) { 2021 case DP_TRAIN_VOLTAGE_SWING_400: 2022 return DP_TRAIN_PRE_EMPHASIS_6; 2023 case DP_TRAIN_VOLTAGE_SWING_600: 2024 case DP_TRAIN_VOLTAGE_SWING_800: 2025 return DP_TRAIN_PRE_EMPHASIS_3_5; 2026 default: 2027 return DP_TRAIN_PRE_EMPHASIS_0; 2028 } 2029 } else { 2030 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) { 2031 case DP_TRAIN_VOLTAGE_SWING_400: 2032 return DP_TRAIN_PRE_EMPHASIS_6; 2033 case DP_TRAIN_VOLTAGE_SWING_600: 2034 return DP_TRAIN_PRE_EMPHASIS_6; 2035 case DP_TRAIN_VOLTAGE_SWING_800: 2036 return DP_TRAIN_PRE_EMPHASIS_3_5; 2037 case DP_TRAIN_VOLTAGE_SWING_1200: 2038 default: 2039 return DP_TRAIN_PRE_EMPHASIS_0; 2040 } 2041 } 2042} 2043 2044static uint32_t intel_vlv_signal_levels(struct intel_dp *intel_dp) 2045{ 2046 struct drm_device *dev = intel_dp_to_dev(intel_dp); 2047 struct drm_i915_private *dev_priv = dev->dev_private; 2048 struct intel_digital_port *dport = dp_to_dig_port(intel_dp); 2049 struct intel_crtc *intel_crtc = 2050 to_intel_crtc(dport->base.base.crtc); 2051 unsigned long demph_reg_value, preemph_reg_value, 2052 uniqtranscale_reg_value; 2053 uint8_t train_set = intel_dp->train_set[0]; 2054 enum dpio_channel port = vlv_dport_to_channel(dport); 2055 int pipe = intel_crtc->pipe; 2056 2057 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) { 2058 case DP_TRAIN_PRE_EMPHASIS_0: 2059 preemph_reg_value = 0x0004000; 2060 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { 2061 case DP_TRAIN_VOLTAGE_SWING_400: 2062 demph_reg_value = 0x2B405555; 2063 uniqtranscale_reg_value = 0x552AB83A; 2064 break; 2065 case DP_TRAIN_VOLTAGE_SWING_600: 2066 demph_reg_value = 0x2B404040; 2067 uniqtranscale_reg_value = 0x5548B83A; 2068 break; 2069 case DP_TRAIN_VOLTAGE_SWING_800: 2070 demph_reg_value = 0x2B245555; 2071 uniqtranscale_reg_value = 0x5560B83A; 2072 break; 2073 case DP_TRAIN_VOLTAGE_SWING_1200: 2074 demph_reg_value = 0x2B405555; 2075 uniqtranscale_reg_value = 0x5598DA3A; 2076 break; 2077 default: 2078 return 0; 2079 } 2080 break; 2081 case DP_TRAIN_PRE_EMPHASIS_3_5: 2082 preemph_reg_value = 0x0002000; 2083 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { 2084 case DP_TRAIN_VOLTAGE_SWING_400: 2085 demph_reg_value = 0x2B404040; 2086 uniqtranscale_reg_value = 0x5552B83A; 2087 break; 2088 case DP_TRAIN_VOLTAGE_SWING_600: 2089 demph_reg_value = 0x2B404848; 2090 uniqtranscale_reg_value = 0x5580B83A; 2091 break; 2092 case DP_TRAIN_VOLTAGE_SWING_800: 2093 demph_reg_value = 0x2B404040; 2094 uniqtranscale_reg_value = 0x55ADDA3A; 2095 break; 2096 default: 2097 return 0; 2098 } 2099 break; 2100 case DP_TRAIN_PRE_EMPHASIS_6: 2101 preemph_reg_value = 0x0000000; 2102 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { 2103 case DP_TRAIN_VOLTAGE_SWING_400: 2104 demph_reg_value = 0x2B305555; 2105 uniqtranscale_reg_value = 0x5570B83A; 2106 break; 2107 case DP_TRAIN_VOLTAGE_SWING_600: 2108 demph_reg_value = 0x2B2B4040; 2109 uniqtranscale_reg_value = 0x55ADDA3A; 2110 break; 2111 default: 2112 return 0; 2113 } 2114 break; 2115 case DP_TRAIN_PRE_EMPHASIS_9_5: 2116 preemph_reg_value = 0x0006000; 2117 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { 2118 case DP_TRAIN_VOLTAGE_SWING_400: 2119 demph_reg_value = 0x1B405555; 2120 uniqtranscale_reg_value = 0x55ADDA3A; 2121 break; 2122 default: 2123 return 0; 2124 } 2125 break; 2126 default: 2127 return 0; 2128 } 2129 2130 mutex_lock(&dev_priv->dpio_lock); 2131 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x00000000); 2132 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW4(port), demph_reg_value); 2133 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(port), 2134 uniqtranscale_reg_value); 2135 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(port), 0x0C782040); 2136 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW11(port), 0x00030000); 2137 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), preemph_reg_value); 2138 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x80000000); 2139 mutex_unlock(&dev_priv->dpio_lock); 2140 2141 return 0; 2142} 2143 2144static void 2145intel_get_adjust_train(struct intel_dp *intel_dp, 2146 const uint8_t link_status[DP_LINK_STATUS_SIZE]) 2147{ 2148 uint8_t v = 0; 2149 uint8_t p = 0; 2150 int lane; 2151 uint8_t voltage_max; 2152 uint8_t preemph_max; 2153 2154 for (lane = 0; lane < intel_dp->lane_count; lane++) { 2155 uint8_t this_v = drm_dp_get_adjust_request_voltage(link_status, lane); 2156 uint8_t this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane); 2157 2158 if (this_v > v) 2159 v = this_v; 2160 if (this_p > p) 2161 p = this_p; 2162 } 2163 2164 voltage_max = intel_dp_voltage_max(intel_dp); 2165 if (v >= voltage_max) 2166 v = voltage_max | DP_TRAIN_MAX_SWING_REACHED; 2167 2168 preemph_max = intel_dp_pre_emphasis_max(intel_dp, v); 2169 if (p >= preemph_max) 2170 p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED; 2171 2172 for (lane = 0; lane < 4; lane++) 2173 intel_dp->train_set[lane] = v | p; 2174} 2175 2176static uint32_t 2177intel_gen4_signal_levels(uint8_t train_set) 2178{ 2179 uint32_t signal_levels = 0; 2180 2181 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { 2182 case DP_TRAIN_VOLTAGE_SWING_400: 2183 default: 2184 signal_levels |= DP_VOLTAGE_0_4; 2185 break; 2186 case DP_TRAIN_VOLTAGE_SWING_600: 2187 signal_levels |= DP_VOLTAGE_0_6; 2188 break; 2189 case DP_TRAIN_VOLTAGE_SWING_800: 2190 signal_levels |= DP_VOLTAGE_0_8; 2191 break; 2192 case DP_TRAIN_VOLTAGE_SWING_1200: 2193 signal_levels |= DP_VOLTAGE_1_2; 2194 break; 2195 } 2196 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) { 2197 case DP_TRAIN_PRE_EMPHASIS_0: 2198 default: 2199 signal_levels |= DP_PRE_EMPHASIS_0; 2200 break; 2201 case DP_TRAIN_PRE_EMPHASIS_3_5: 2202 signal_levels |= DP_PRE_EMPHASIS_3_5; 2203 break; 2204 case DP_TRAIN_PRE_EMPHASIS_6: 2205 signal_levels |= DP_PRE_EMPHASIS_6; 2206 break; 2207 case DP_TRAIN_PRE_EMPHASIS_9_5: 2208 signal_levels |= DP_PRE_EMPHASIS_9_5; 2209 break; 2210 } 2211 return signal_levels; 2212} 2213 2214/* Gen6's DP voltage swing and pre-emphasis control */ 2215static uint32_t 2216intel_gen6_edp_signal_levels(uint8_t train_set) 2217{ 2218 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK | 2219 DP_TRAIN_PRE_EMPHASIS_MASK); 2220 switch (signal_levels) { 2221 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0: 2222 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0: 2223 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B; 2224 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5: 2225 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B; 2226 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6: 2227 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6: 2228 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B; 2229 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5: 2230 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5: 2231 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B; 2232 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0: 2233 case DP_TRAIN_VOLTAGE_SWING_1200 | DP_TRAIN_PRE_EMPHASIS_0: 2234 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B; 2235 default: 2236 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:" 2237 "0x%x\n", signal_levels); 2238 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B; 2239 } 2240} 2241 2242/* Gen7's DP voltage swing and pre-emphasis control */ 2243static uint32_t 2244intel_gen7_edp_signal_levels(uint8_t train_set) 2245{ 2246 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK | 2247 DP_TRAIN_PRE_EMPHASIS_MASK); 2248 switch (signal_levels) { 2249 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0: 2250 return EDP_LINK_TRAIN_400MV_0DB_IVB; 2251 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5: 2252 return EDP_LINK_TRAIN_400MV_3_5DB_IVB; 2253 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6: 2254 return EDP_LINK_TRAIN_400MV_6DB_IVB; 2255 2256 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0: 2257 return EDP_LINK_TRAIN_600MV_0DB_IVB; 2258 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5: 2259 return EDP_LINK_TRAIN_600MV_3_5DB_IVB; 2260 2261 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0: 2262 return EDP_LINK_TRAIN_800MV_0DB_IVB; 2263 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5: 2264 return EDP_LINK_TRAIN_800MV_3_5DB_IVB; 2265 2266 default: 2267 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:" 2268 "0x%x\n", signal_levels); 2269 return EDP_LINK_TRAIN_500MV_0DB_IVB; 2270 } 2271} 2272 2273/* Gen7.5's (HSW) DP voltage swing and pre-emphasis control */ 2274static uint32_t 2275intel_hsw_signal_levels(uint8_t train_set) 2276{ 2277 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK | 2278 DP_TRAIN_PRE_EMPHASIS_MASK); 2279 switch (signal_levels) { 2280 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0: 2281 return DDI_BUF_EMP_400MV_0DB_HSW; 2282 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5: 2283 return DDI_BUF_EMP_400MV_3_5DB_HSW; 2284 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6: 2285 return DDI_BUF_EMP_400MV_6DB_HSW; 2286 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_9_5: 2287 return DDI_BUF_EMP_400MV_9_5DB_HSW; 2288 2289 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0: 2290 return DDI_BUF_EMP_600MV_0DB_HSW; 2291 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5: 2292 return DDI_BUF_EMP_600MV_3_5DB_HSW; 2293 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6: 2294 return DDI_BUF_EMP_600MV_6DB_HSW; 2295 2296 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0: 2297 return DDI_BUF_EMP_800MV_0DB_HSW; 2298 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5: 2299 return DDI_BUF_EMP_800MV_3_5DB_HSW; 2300 default: 2301 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:" 2302 "0x%x\n", signal_levels); 2303 return DDI_BUF_EMP_400MV_0DB_HSW; 2304 } 2305} 2306 2307static uint32_t 2308intel_bdw_signal_levels(uint8_t train_set) 2309{ 2310 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK | 2311 DP_TRAIN_PRE_EMPHASIS_MASK); 2312 switch (signal_levels) { 2313 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0: 2314 return DDI_BUF_EMP_400MV_0DB_BDW; /* Sel0 */ 2315 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5: 2316 return DDI_BUF_EMP_400MV_3_5DB_BDW; /* Sel1 */ 2317 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6: 2318 return DDI_BUF_EMP_400MV_6DB_BDW; /* Sel2 */ 2319 2320 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0: 2321 return DDI_BUF_EMP_600MV_0DB_BDW; /* Sel3 */ 2322 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5: 2323 return DDI_BUF_EMP_600MV_3_5DB_BDW; /* Sel4 */ 2324 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6: 2325 return DDI_BUF_EMP_600MV_6DB_BDW; /* Sel5 */ 2326 2327 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0: 2328 return DDI_BUF_EMP_800MV_0DB_BDW; /* Sel6 */ 2329 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5: 2330 return DDI_BUF_EMP_800MV_3_5DB_BDW; /* Sel7 */ 2331 2332 case DP_TRAIN_VOLTAGE_SWING_1200 | DP_TRAIN_PRE_EMPHASIS_0: 2333 return DDI_BUF_EMP_1200MV_0DB_BDW; /* Sel8 */ 2334 2335 default: 2336 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:" 2337 "0x%x\n", signal_levels); 2338 return DDI_BUF_EMP_400MV_0DB_BDW; /* Sel0 */ 2339 } 2340} 2341 2342/* Properly updates "DP" with the correct signal levels. */ 2343static void 2344intel_dp_set_signal_levels(struct intel_dp *intel_dp, uint32_t *DP) 2345{ 2346 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 2347 enum port port = intel_dig_port->port; 2348 struct drm_device *dev = intel_dig_port->base.base.dev; 2349 uint32_t signal_levels, mask; 2350 uint8_t train_set = intel_dp->train_set[0]; 2351 2352 if (IS_BROADWELL(dev)) { 2353 signal_levels = intel_bdw_signal_levels(train_set); 2354 mask = DDI_BUF_EMP_MASK; 2355 } else if (IS_HASWELL(dev)) { 2356 signal_levels = intel_hsw_signal_levels(train_set); 2357 mask = DDI_BUF_EMP_MASK; 2358 } else if (IS_VALLEYVIEW(dev)) { 2359 signal_levels = intel_vlv_signal_levels(intel_dp); 2360 mask = 0; 2361 } else if (IS_GEN7(dev) && port == PORT_A) { 2362 signal_levels = intel_gen7_edp_signal_levels(train_set); 2363 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_IVB; 2364 } else if (IS_GEN6(dev) && port == PORT_A) { 2365 signal_levels = intel_gen6_edp_signal_levels(train_set); 2366 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB; 2367 } else { 2368 signal_levels = intel_gen4_signal_levels(train_set); 2369 mask = DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK; 2370 } 2371 2372 DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels); 2373 2374 *DP = (*DP & ~mask) | signal_levels; 2375} 2376 2377static bool 2378intel_dp_set_link_train(struct intel_dp *intel_dp, 2379 uint32_t *DP, 2380 uint8_t dp_train_pat) 2381{ 2382 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 2383 struct drm_device *dev = intel_dig_port->base.base.dev; 2384 struct drm_i915_private *dev_priv = dev->dev_private; 2385 enum port port = intel_dig_port->port; 2386 uint8_t buf[sizeof(intel_dp->train_set) + 1]; 2387 int ret, len; 2388 2389 if (HAS_DDI(dev)) { 2390 uint32_t temp = I915_READ(DP_TP_CTL(port)); 2391 2392 if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE) 2393 temp |= DP_TP_CTL_SCRAMBLE_DISABLE; 2394 else 2395 temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE; 2396 2397 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK; 2398 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) { 2399 case DP_TRAINING_PATTERN_DISABLE: 2400 temp |= DP_TP_CTL_LINK_TRAIN_NORMAL; 2401 2402 break; 2403 case DP_TRAINING_PATTERN_1: 2404 temp |= DP_TP_CTL_LINK_TRAIN_PAT1; 2405 break; 2406 case DP_TRAINING_PATTERN_2: 2407 temp |= DP_TP_CTL_LINK_TRAIN_PAT2; 2408 break; 2409 case DP_TRAINING_PATTERN_3: 2410 temp |= DP_TP_CTL_LINK_TRAIN_PAT3; 2411 break; 2412 } 2413 I915_WRITE(DP_TP_CTL(port), temp); 2414 2415 } else if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) { 2416 *DP &= ~DP_LINK_TRAIN_MASK_CPT; 2417 2418 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) { 2419 case DP_TRAINING_PATTERN_DISABLE: 2420 *DP |= DP_LINK_TRAIN_OFF_CPT; 2421 break; 2422 case DP_TRAINING_PATTERN_1: 2423 *DP |= DP_LINK_TRAIN_PAT_1_CPT; 2424 break; 2425 case DP_TRAINING_PATTERN_2: 2426 *DP |= DP_LINK_TRAIN_PAT_2_CPT; 2427 break; 2428 case DP_TRAINING_PATTERN_3: 2429 DRM_ERROR("DP training pattern 3 not supported\n"); 2430 *DP |= DP_LINK_TRAIN_PAT_2_CPT; 2431 break; 2432 } 2433 2434 } else { 2435 *DP &= ~DP_LINK_TRAIN_MASK; 2436 2437 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) { 2438 case DP_TRAINING_PATTERN_DISABLE: 2439 *DP |= DP_LINK_TRAIN_OFF; 2440 break; 2441 case DP_TRAINING_PATTERN_1: 2442 *DP |= DP_LINK_TRAIN_PAT_1; 2443 break; 2444 case DP_TRAINING_PATTERN_2: 2445 *DP |= DP_LINK_TRAIN_PAT_2; 2446 break; 2447 case DP_TRAINING_PATTERN_3: 2448 DRM_ERROR("DP training pattern 3 not supported\n"); 2449 *DP |= DP_LINK_TRAIN_PAT_2; 2450 break; 2451 } 2452 } 2453 2454 I915_WRITE(intel_dp->output_reg, *DP); 2455 POSTING_READ(intel_dp->output_reg); 2456 2457 buf[0] = dp_train_pat; 2458 if ((dp_train_pat & DP_TRAINING_PATTERN_MASK) == 2459 DP_TRAINING_PATTERN_DISABLE) { 2460 /* don't write DP_TRAINING_LANEx_SET on disable */ 2461 len = 1; 2462 } else { 2463 /* DP_TRAINING_LANEx_SET follow DP_TRAINING_PATTERN_SET */ 2464 memcpy(buf + 1, intel_dp->train_set, intel_dp->lane_count); 2465 len = intel_dp->lane_count + 1; 2466 } 2467 2468 ret = intel_dp_aux_native_write(intel_dp, DP_TRAINING_PATTERN_SET, 2469 buf, len); 2470 2471 return ret == len; 2472} 2473 2474static bool 2475intel_dp_reset_link_train(struct intel_dp *intel_dp, uint32_t *DP, 2476 uint8_t dp_train_pat) 2477{ 2478 memset(intel_dp->train_set, 0, sizeof(intel_dp->train_set)); 2479 intel_dp_set_signal_levels(intel_dp, DP); 2480 return intel_dp_set_link_train(intel_dp, DP, dp_train_pat); 2481} 2482 2483static bool 2484intel_dp_update_link_train(struct intel_dp *intel_dp, uint32_t *DP, 2485 const uint8_t link_status[DP_LINK_STATUS_SIZE]) 2486{ 2487 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 2488 struct drm_device *dev = intel_dig_port->base.base.dev; 2489 struct drm_i915_private *dev_priv = dev->dev_private; 2490 int ret; 2491 2492 intel_get_adjust_train(intel_dp, link_status); 2493 intel_dp_set_signal_levels(intel_dp, DP); 2494 2495 I915_WRITE(intel_dp->output_reg, *DP); 2496 POSTING_READ(intel_dp->output_reg); 2497 2498 ret = intel_dp_aux_native_write(intel_dp, DP_TRAINING_LANE0_SET, 2499 intel_dp->train_set, 2500 intel_dp->lane_count); 2501 2502 return ret == intel_dp->lane_count; 2503} 2504 2505static void intel_dp_set_idle_link_train(struct intel_dp *intel_dp) 2506{ 2507 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 2508 struct drm_device *dev = intel_dig_port->base.base.dev; 2509 struct drm_i915_private *dev_priv = dev->dev_private; 2510 enum port port = intel_dig_port->port; 2511 uint32_t val; 2512 2513 if (!HAS_DDI(dev)) 2514 return; 2515 2516 val = I915_READ(DP_TP_CTL(port)); 2517 val &= ~DP_TP_CTL_LINK_TRAIN_MASK; 2518 val |= DP_TP_CTL_LINK_TRAIN_IDLE; 2519 I915_WRITE(DP_TP_CTL(port), val); 2520 2521 /* 2522 * On PORT_A we can have only eDP in SST mode. There the only reason 2523 * we need to set idle transmission mode is to work around a HW issue 2524 * where we enable the pipe while not in idle link-training mode. 2525 * In this case there is requirement to wait for a minimum number of 2526 * idle patterns to be sent. 2527 */ 2528 if (port == PORT_A) 2529 return; 2530 2531 if (wait_for((I915_READ(DP_TP_STATUS(port)) & DP_TP_STATUS_IDLE_DONE), 2532 1)) 2533 DRM_ERROR("Timed out waiting for DP idle patterns\n"); 2534} 2535 2536/* Enable corresponding port and start training pattern 1 */ 2537void 2538intel_dp_start_link_train(struct intel_dp *intel_dp) 2539{ 2540 struct drm_encoder *encoder = &dp_to_dig_port(intel_dp)->base.base; 2541 struct drm_device *dev = encoder->dev; 2542 int i; 2543 uint8_t voltage; 2544 int voltage_tries, loop_tries; 2545 uint32_t DP = intel_dp->DP; 2546 uint8_t link_config[2]; 2547 2548 if (HAS_DDI(dev)) 2549 intel_ddi_prepare_link_retrain(encoder); 2550 2551 /* Write the link configuration data */ 2552 link_config[0] = intel_dp->link_bw; 2553 link_config[1] = intel_dp->lane_count; 2554 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd)) 2555 link_config[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN; 2556 intel_dp_aux_native_write(intel_dp, DP_LINK_BW_SET, link_config, 2); 2557 2558 link_config[0] = 0; 2559 link_config[1] = DP_SET_ANSI_8B10B; 2560 intel_dp_aux_native_write(intel_dp, DP_DOWNSPREAD_CTRL, link_config, 2); 2561 2562 DP |= DP_PORT_EN; 2563 2564 /* clock recovery */ 2565 if (!intel_dp_reset_link_train(intel_dp, &DP, 2566 DP_TRAINING_PATTERN_1 | 2567 DP_LINK_SCRAMBLING_DISABLE)) { 2568 DRM_ERROR("failed to enable link training\n"); 2569 return; 2570 } 2571 2572 voltage = 0xff; 2573 voltage_tries = 0; 2574 loop_tries = 0; 2575 for (;;) { 2576 uint8_t link_status[DP_LINK_STATUS_SIZE]; 2577 2578 drm_dp_link_train_clock_recovery_delay(intel_dp->dpcd); 2579 if (!intel_dp_get_link_status(intel_dp, link_status)) { 2580 DRM_ERROR("failed to get link status\n"); 2581 break; 2582 } 2583 2584 if (drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) { 2585 DRM_DEBUG_KMS("clock recovery OK\n"); 2586 break; 2587 } 2588 2589 /* Check to see if we've tried the max voltage */ 2590 for (i = 0; i < intel_dp->lane_count; i++) 2591 if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0) 2592 break; 2593 if (i == intel_dp->lane_count) { 2594 ++loop_tries; 2595 if (loop_tries == 5) { 2596 DRM_ERROR("too many full retries, give up\n"); 2597 break; 2598 } 2599 intel_dp_reset_link_train(intel_dp, &DP, 2600 DP_TRAINING_PATTERN_1 | 2601 DP_LINK_SCRAMBLING_DISABLE); 2602 voltage_tries = 0; 2603 continue; 2604 } 2605 2606 /* Check to see if we've tried the same voltage 5 times */ 2607 if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) { 2608 ++voltage_tries; 2609 if (voltage_tries == 5) { 2610 DRM_ERROR("too many voltage retries, give up\n"); 2611 break; 2612 } 2613 } else 2614 voltage_tries = 0; 2615 voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK; 2616 2617 /* Update training set as requested by target */ 2618 if (!intel_dp_update_link_train(intel_dp, &DP, link_status)) { 2619 DRM_ERROR("failed to update link training\n"); 2620 break; 2621 } 2622 } 2623 2624 intel_dp->DP = DP; 2625} 2626 2627void 2628intel_dp_complete_link_train(struct intel_dp *intel_dp) 2629{ 2630 bool channel_eq = false; 2631 int tries, cr_tries; 2632 uint32_t DP = intel_dp->DP; 2633 2634 /* channel equalization */ 2635 if (!intel_dp_set_link_train(intel_dp, &DP, 2636 DP_TRAINING_PATTERN_2 | 2637 DP_LINK_SCRAMBLING_DISABLE)) { 2638 DRM_ERROR("failed to start channel equalization\n"); 2639 return; 2640 } 2641 2642 tries = 0; 2643 cr_tries = 0; 2644 channel_eq = false; 2645 for (;;) { 2646 uint8_t link_status[DP_LINK_STATUS_SIZE]; 2647 2648 if (cr_tries > 5) { 2649 DRM_ERROR("failed to train DP, aborting\n"); 2650 break; 2651 } 2652 2653 drm_dp_link_train_channel_eq_delay(intel_dp->dpcd); 2654 if (!intel_dp_get_link_status(intel_dp, link_status)) { 2655 DRM_ERROR("failed to get link status\n"); 2656 break; 2657 } 2658 2659 /* Make sure clock is still ok */ 2660 if (!drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) { 2661 intel_dp_start_link_train(intel_dp); 2662 intel_dp_set_link_train(intel_dp, &DP, 2663 DP_TRAINING_PATTERN_2 | 2664 DP_LINK_SCRAMBLING_DISABLE); 2665 cr_tries++; 2666 continue; 2667 } 2668 2669 if (drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) { 2670 channel_eq = true; 2671 break; 2672 } 2673 2674 /* Try 5 times, then try clock recovery if that fails */ 2675 if (tries > 5) { 2676 intel_dp_link_down(intel_dp); 2677 intel_dp_start_link_train(intel_dp); 2678 intel_dp_set_link_train(intel_dp, &DP, 2679 DP_TRAINING_PATTERN_2 | 2680 DP_LINK_SCRAMBLING_DISABLE); 2681 tries = 0; 2682 cr_tries++; 2683 continue; 2684 } 2685 2686 /* Update training set as requested by target */ 2687 if (!intel_dp_update_link_train(intel_dp, &DP, link_status)) { 2688 DRM_ERROR("failed to update link training\n"); 2689 break; 2690 } 2691 ++tries; 2692 } 2693 2694 intel_dp_set_idle_link_train(intel_dp); 2695 2696 intel_dp->DP = DP; 2697 2698 if (channel_eq) 2699 DRM_DEBUG_KMS("Channel EQ done. DP Training successful\n"); 2700 2701} 2702 2703void intel_dp_stop_link_train(struct intel_dp *intel_dp) 2704{ 2705 intel_dp_set_link_train(intel_dp, &intel_dp->DP, 2706 DP_TRAINING_PATTERN_DISABLE); 2707} 2708 2709static void 2710intel_dp_link_down(struct intel_dp *intel_dp) 2711{ 2712 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 2713 enum port port = intel_dig_port->port; 2714 struct drm_device *dev = intel_dig_port->base.base.dev; 2715 struct drm_i915_private *dev_priv = dev->dev_private; 2716 struct intel_crtc *intel_crtc = 2717 to_intel_crtc(intel_dig_port->base.base.crtc); 2718 uint32_t DP = intel_dp->DP; 2719 2720 /* 2721 * DDI code has a strict mode set sequence and we should try to respect 2722 * it, otherwise we might hang the machine in many different ways. So we 2723 * really should be disabling the port only on a complete crtc_disable 2724 * sequence. This function is just called under two conditions on DDI 2725 * code: 2726 * - Link train failed while doing crtc_enable, and on this case we 2727 * really should respect the mode set sequence and wait for a 2728 * crtc_disable. 2729 * - Someone turned the monitor off and intel_dp_check_link_status 2730 * called us. We don't need to disable the whole port on this case, so 2731 * when someone turns the monitor on again, 2732 * intel_ddi_prepare_link_retrain will take care of redoing the link 2733 * train. 2734 */ 2735 if (HAS_DDI(dev)) 2736 return; 2737 2738 if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0)) 2739 return; 2740 2741 DRM_DEBUG_KMS("\n"); 2742 2743 if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) { 2744 DP &= ~DP_LINK_TRAIN_MASK_CPT; 2745 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT); 2746 } else { 2747 DP &= ~DP_LINK_TRAIN_MASK; 2748 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE); 2749 } 2750 POSTING_READ(intel_dp->output_reg); 2751 2752 /* We don't really know why we're doing this */ 2753 intel_wait_for_vblank(dev, intel_crtc->pipe); 2754 2755 if (HAS_PCH_IBX(dev) && 2756 I915_READ(intel_dp->output_reg) & DP_PIPEB_SELECT) { 2757 struct drm_crtc *crtc = intel_dig_port->base.base.crtc; 2758 2759 /* Hardware workaround: leaving our transcoder select 2760 * set to transcoder B while it's off will prevent the 2761 * corresponding HDMI output on transcoder A. 2762 * 2763 * Combine this with another hardware workaround: 2764 * transcoder select bit can only be cleared while the 2765 * port is enabled. 2766 */ 2767 DP &= ~DP_PIPEB_SELECT; 2768 I915_WRITE(intel_dp->output_reg, DP); 2769 2770 /* Changes to enable or select take place the vblank 2771 * after being written. 2772 */ 2773 if (WARN_ON(crtc == NULL)) { 2774 /* We should never try to disable a port without a crtc 2775 * attached. For paranoia keep the code around for a 2776 * bit. */ 2777 POSTING_READ(intel_dp->output_reg); 2778 msleep(50); 2779 } else 2780 intel_wait_for_vblank(dev, intel_crtc->pipe); 2781 } 2782 2783 DP &= ~DP_AUDIO_OUTPUT_ENABLE; 2784 I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN); 2785 POSTING_READ(intel_dp->output_reg); 2786 msleep(intel_dp->panel_power_down_delay); 2787} 2788 2789static bool 2790intel_dp_get_dpcd(struct intel_dp *intel_dp) 2791{ 2792 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 2793 struct drm_device *dev = dig_port->base.base.dev; 2794 struct drm_i915_private *dev_priv = dev->dev_private; 2795 2796 char dpcd_hex_dump[sizeof(intel_dp->dpcd) * 3]; 2797 2798 if (intel_dp_aux_native_read_retry(intel_dp, 0x000, intel_dp->dpcd, 2799 sizeof(intel_dp->dpcd)) == 0) 2800 return false; /* aux transfer failed */ 2801 2802 hex_dump_to_buffer(intel_dp->dpcd, sizeof(intel_dp->dpcd), 2803 32, 1, dpcd_hex_dump, sizeof(dpcd_hex_dump), false); 2804 DRM_DEBUG_KMS("DPCD: %s\n", dpcd_hex_dump); 2805 2806 if (intel_dp->dpcd[DP_DPCD_REV] == 0) 2807 return false; /* DPCD not present */ 2808 2809 /* Check if the panel supports PSR */ 2810 memset(intel_dp->psr_dpcd, 0, sizeof(intel_dp->psr_dpcd)); 2811 if (is_edp(intel_dp)) { 2812 intel_dp_aux_native_read_retry(intel_dp, DP_PSR_SUPPORT, 2813 intel_dp->psr_dpcd, 2814 sizeof(intel_dp->psr_dpcd)); 2815 if (intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED) { 2816 dev_priv->psr.sink_support = true; 2817 DRM_DEBUG_KMS("Detected EDP PSR Panel.\n"); 2818 } 2819 } 2820 2821 if (!(intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] & 2822 DP_DWN_STRM_PORT_PRESENT)) 2823 return true; /* native DP sink */ 2824 2825 if (intel_dp->dpcd[DP_DPCD_REV] == 0x10) 2826 return true; /* no per-port downstream info */ 2827 2828 if (intel_dp_aux_native_read_retry(intel_dp, DP_DOWNSTREAM_PORT_0, 2829 intel_dp->downstream_ports, 2830 DP_MAX_DOWNSTREAM_PORTS) == 0) 2831 return false; /* downstream port status fetch failed */ 2832 2833 return true; 2834} 2835 2836static void 2837intel_dp_probe_oui(struct intel_dp *intel_dp) 2838{ 2839 u8 buf[3]; 2840 2841 if (!(intel_dp->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT)) 2842 return; 2843 2844 ironlake_edp_panel_vdd_on(intel_dp); 2845 2846 if (intel_dp_aux_native_read_retry(intel_dp, DP_SINK_OUI, buf, 3)) 2847 DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n", 2848 buf[0], buf[1], buf[2]); 2849 2850 if (intel_dp_aux_native_read_retry(intel_dp, DP_BRANCH_OUI, buf, 3)) 2851 DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n", 2852 buf[0], buf[1], buf[2]); 2853 2854 ironlake_edp_panel_vdd_off(intel_dp, false); 2855} 2856 2857static bool 2858intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector) 2859{ 2860 int ret; 2861 2862 ret = intel_dp_aux_native_read_retry(intel_dp, 2863 DP_DEVICE_SERVICE_IRQ_VECTOR, 2864 sink_irq_vector, 1); 2865 if (!ret) 2866 return false; 2867 2868 return true; 2869} 2870 2871static void 2872intel_dp_handle_test_request(struct intel_dp *intel_dp) 2873{ 2874 /* NAK by default */ 2875 intel_dp_aux_native_write_1(intel_dp, DP_TEST_RESPONSE, DP_TEST_NAK); 2876} 2877 2878/* 2879 * According to DP spec 2880 * 5.1.2: 2881 * 1. Read DPCD 2882 * 2. Configure link according to Receiver Capabilities 2883 * 3. Use Link Training from 2.5.3.3 and 3.5.1.3 2884 * 4. Check link status on receipt of hot-plug interrupt 2885 */ 2886 2887void 2888intel_dp_check_link_status(struct intel_dp *intel_dp) 2889{ 2890 struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base; 2891 u8 sink_irq_vector; 2892 u8 link_status[DP_LINK_STATUS_SIZE]; 2893 2894 if (!intel_encoder->connectors_active) 2895 return; 2896 2897 if (WARN_ON(!intel_encoder->base.crtc)) 2898 return; 2899 2900 /* Try to read receiver status if the link appears to be up */ 2901 if (!intel_dp_get_link_status(intel_dp, link_status)) { 2902 return; 2903 } 2904 2905 /* Now read the DPCD to see if it's actually running */ 2906 if (!intel_dp_get_dpcd(intel_dp)) { 2907 return; 2908 } 2909 2910 /* Try to read the source of the interrupt */ 2911 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 && 2912 intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) { 2913 /* Clear interrupt source */ 2914 intel_dp_aux_native_write_1(intel_dp, 2915 DP_DEVICE_SERVICE_IRQ_VECTOR, 2916 sink_irq_vector); 2917 2918 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST) 2919 intel_dp_handle_test_request(intel_dp); 2920 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ)) 2921 DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n"); 2922 } 2923 2924 if (!drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) { 2925 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n", 2926 drm_get_encoder_name(&intel_encoder->base)); 2927 intel_dp_start_link_train(intel_dp); 2928 intel_dp_complete_link_train(intel_dp); 2929 intel_dp_stop_link_train(intel_dp); 2930 } 2931} 2932 2933/* XXX this is probably wrong for multiple downstream ports */ 2934static enum drm_connector_status 2935intel_dp_detect_dpcd(struct intel_dp *intel_dp) 2936{ 2937 uint8_t *dpcd = intel_dp->dpcd; 2938 uint8_t type; 2939 2940 if (!intel_dp_get_dpcd(intel_dp)) 2941 return connector_status_disconnected; 2942 2943 /* if there's no downstream port, we're done */ 2944 if (!(dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT)) 2945 return connector_status_connected; 2946 2947 /* If we're HPD-aware, SINK_COUNT changes dynamically */ 2948 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 && 2949 intel_dp->downstream_ports[0] & DP_DS_PORT_HPD) { 2950 uint8_t reg; 2951 if (!intel_dp_aux_native_read_retry(intel_dp, DP_SINK_COUNT, 2952 ®, 1)) 2953 return connector_status_unknown; 2954 return DP_GET_SINK_COUNT(reg) ? connector_status_connected 2955 : connector_status_disconnected; 2956 } 2957 2958 /* If no HPD, poke DDC gently */ 2959 if (drm_probe_ddc(&intel_dp->adapter)) 2960 return connector_status_connected; 2961 2962 /* Well we tried, say unknown for unreliable port types */ 2963 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) { 2964 type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK; 2965 if (type == DP_DS_PORT_TYPE_VGA || 2966 type == DP_DS_PORT_TYPE_NON_EDID) 2967 return connector_status_unknown; 2968 } else { 2969 type = intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] & 2970 DP_DWN_STRM_PORT_TYPE_MASK; 2971 if (type == DP_DWN_STRM_PORT_TYPE_ANALOG || 2972 type == DP_DWN_STRM_PORT_TYPE_OTHER) 2973 return connector_status_unknown; 2974 } 2975 2976 /* Anything else is out of spec, warn and ignore */ 2977 DRM_DEBUG_KMS("Broken DP branch device, ignoring\n"); 2978 return connector_status_disconnected; 2979} 2980 2981static enum drm_connector_status 2982ironlake_dp_detect(struct intel_dp *intel_dp) 2983{ 2984 struct drm_device *dev = intel_dp_to_dev(intel_dp); 2985 struct drm_i915_private *dev_priv = dev->dev_private; 2986 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 2987 enum drm_connector_status status; 2988 2989 /* Can't disconnect eDP, but you can close the lid... */ 2990 if (is_edp(intel_dp)) { 2991 status = intel_panel_detect(dev); 2992 if (status == connector_status_unknown) 2993 status = connector_status_connected; 2994 return status; 2995 } 2996 2997 if (!ibx_digital_port_connected(dev_priv, intel_dig_port)) 2998 return connector_status_disconnected; 2999 3000 return intel_dp_detect_dpcd(intel_dp); 3001} 3002 3003static enum drm_connector_status 3004g4x_dp_detect(struct intel_dp *intel_dp) 3005{ 3006 struct drm_device *dev = intel_dp_to_dev(intel_dp); 3007 struct drm_i915_private *dev_priv = dev->dev_private; 3008 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 3009 uint32_t bit; 3010 3011 /* Can't disconnect eDP, but you can close the lid... */ 3012 if (is_edp(intel_dp)) { 3013 enum drm_connector_status status; 3014 3015 status = intel_panel_detect(dev); 3016 if (status == connector_status_unknown) 3017 status = connector_status_connected; 3018 return status; 3019 } 3020 3021 if (IS_VALLEYVIEW(dev)) { 3022 switch (intel_dig_port->port) { 3023 case PORT_B: 3024 bit = PORTB_HOTPLUG_LIVE_STATUS_VLV; 3025 break; 3026 case PORT_C: 3027 bit = PORTC_HOTPLUG_LIVE_STATUS_VLV; 3028 break; 3029 case PORT_D: 3030 bit = PORTD_HOTPLUG_LIVE_STATUS_VLV; 3031 break; 3032 default: 3033 return connector_status_unknown; 3034 } 3035 } else { 3036 switch (intel_dig_port->port) { 3037 case PORT_B: 3038 bit = PORTB_HOTPLUG_LIVE_STATUS_G4X; 3039 break; 3040 case PORT_C: 3041 bit = PORTC_HOTPLUG_LIVE_STATUS_G4X; 3042 break; 3043 case PORT_D: 3044 bit = PORTD_HOTPLUG_LIVE_STATUS_G4X; 3045 break; 3046 default: 3047 return connector_status_unknown; 3048 } 3049 } 3050 3051 if ((I915_READ(PORT_HOTPLUG_STAT) & bit) == 0) 3052 return connector_status_disconnected; 3053 3054 return intel_dp_detect_dpcd(intel_dp); 3055} 3056 3057static struct edid * 3058intel_dp_get_edid(struct drm_connector *connector, struct i2c_adapter *adapter) 3059{ 3060 struct intel_connector *intel_connector = to_intel_connector(connector); 3061 3062 /* use cached edid if we have one */ 3063 if (intel_connector->edid) { 3064 /* invalid edid */ 3065 if (IS_ERR(intel_connector->edid)) 3066 return NULL; 3067 3068 return drm_edid_duplicate(intel_connector->edid); 3069 } 3070 3071 return drm_get_edid(connector, adapter); 3072} 3073 3074static int 3075intel_dp_get_edid_modes(struct drm_connector *connector, struct i2c_adapter *adapter) 3076{ 3077 struct intel_connector *intel_connector = to_intel_connector(connector); 3078 3079 /* use cached edid if we have one */ 3080 if (intel_connector->edid) { 3081 /* invalid edid */ 3082 if (IS_ERR(intel_connector->edid)) 3083 return 0; 3084 3085 return intel_connector_update_modes(connector, 3086 intel_connector->edid); 3087 } 3088 3089 return intel_ddc_get_modes(connector, adapter); 3090} 3091 3092static enum drm_connector_status 3093intel_dp_detect(struct drm_connector *connector, bool force) 3094{ 3095 struct intel_dp *intel_dp = intel_attached_dp(connector); 3096 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 3097 struct intel_encoder *intel_encoder = &intel_dig_port->base; 3098 struct drm_device *dev = connector->dev; 3099 struct drm_i915_private *dev_priv = dev->dev_private; 3100 enum drm_connector_status status; 3101 struct edid *edid = NULL; 3102 3103 intel_runtime_pm_get(dev_priv); 3104 3105 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", 3106 connector->base.id, drm_get_connector_name(connector)); 3107 3108 intel_dp->has_audio = false; 3109 3110 if (HAS_PCH_SPLIT(dev)) 3111 status = ironlake_dp_detect(intel_dp); 3112 else 3113 status = g4x_dp_detect(intel_dp); 3114 3115 if (status != connector_status_connected) 3116 goto out; 3117 3118 intel_dp_probe_oui(intel_dp); 3119 3120 if (intel_dp->force_audio != HDMI_AUDIO_AUTO) { 3121 intel_dp->has_audio = (intel_dp->force_audio == HDMI_AUDIO_ON); 3122 } else { 3123 edid = intel_dp_get_edid(connector, &intel_dp->adapter); 3124 if (edid) { 3125 intel_dp->has_audio = drm_detect_monitor_audio(edid); 3126 kfree(edid); 3127 } 3128 } 3129 3130 if (intel_encoder->type != INTEL_OUTPUT_EDP) 3131 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT; 3132 status = connector_status_connected; 3133 3134out: 3135 intel_runtime_pm_put(dev_priv); 3136 return status; 3137} 3138 3139static int intel_dp_get_modes(struct drm_connector *connector) 3140{ 3141 struct intel_dp *intel_dp = intel_attached_dp(connector); 3142 struct intel_connector *intel_connector = to_intel_connector(connector); 3143 struct drm_device *dev = connector->dev; 3144 int ret; 3145 3146 /* We should parse the EDID data and find out if it has an audio sink 3147 */ 3148 3149 ret = intel_dp_get_edid_modes(connector, &intel_dp->adapter); 3150 if (ret) 3151 return ret; 3152 3153 /* if eDP has no EDID, fall back to fixed mode */ 3154 if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) { 3155 struct drm_display_mode *mode; 3156 mode = drm_mode_duplicate(dev, 3157 intel_connector->panel.fixed_mode); 3158 if (mode) { 3159 drm_mode_probed_add(connector, mode); 3160 return 1; 3161 } 3162 } 3163 return 0; 3164} 3165 3166static bool 3167intel_dp_detect_audio(struct drm_connector *connector) 3168{ 3169 struct intel_dp *intel_dp = intel_attached_dp(connector); 3170 struct edid *edid; 3171 bool has_audio = false; 3172 3173 edid = intel_dp_get_edid(connector, &intel_dp->adapter); 3174 if (edid) { 3175 has_audio = drm_detect_monitor_audio(edid); 3176 kfree(edid); 3177 } 3178 3179 return has_audio; 3180} 3181 3182static int 3183intel_dp_set_property(struct drm_connector *connector, 3184 struct drm_property *property, 3185 uint64_t val) 3186{ 3187 struct drm_i915_private *dev_priv = connector->dev->dev_private; 3188 struct intel_connector *intel_connector = to_intel_connector(connector); 3189 struct intel_encoder *intel_encoder = intel_attached_encoder(connector); 3190 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base); 3191 int ret; 3192 3193 ret = drm_object_property_set_value(&connector->base, property, val); 3194 if (ret) 3195 return ret; 3196 3197 if (property == dev_priv->force_audio_property) { 3198 int i = val; 3199 bool has_audio; 3200 3201 if (i == intel_dp->force_audio) 3202 return 0; 3203 3204 intel_dp->force_audio = i; 3205 3206 if (i == HDMI_AUDIO_AUTO) 3207 has_audio = intel_dp_detect_audio(connector); 3208 else 3209 has_audio = (i == HDMI_AUDIO_ON); 3210 3211 if (has_audio == intel_dp->has_audio) 3212 return 0; 3213 3214 intel_dp->has_audio = has_audio; 3215 goto done; 3216 } 3217 3218 if (property == dev_priv->broadcast_rgb_property) { 3219 bool old_auto = intel_dp->color_range_auto; 3220 uint32_t old_range = intel_dp->color_range; 3221 3222 switch (val) { 3223 case INTEL_BROADCAST_RGB_AUTO: 3224 intel_dp->color_range_auto = true; 3225 break; 3226 case INTEL_BROADCAST_RGB_FULL: 3227 intel_dp->color_range_auto = false; 3228 intel_dp->color_range = 0; 3229 break; 3230 case INTEL_BROADCAST_RGB_LIMITED: 3231 intel_dp->color_range_auto = false; 3232 intel_dp->color_range = DP_COLOR_RANGE_16_235; 3233 break; 3234 default: 3235 return -EINVAL; 3236 } 3237 3238 if (old_auto == intel_dp->color_range_auto && 3239 old_range == intel_dp->color_range) 3240 return 0; 3241 3242 goto done; 3243 } 3244 3245 if (is_edp(intel_dp) && 3246 property == connector->dev->mode_config.scaling_mode_property) { 3247 if (val == DRM_MODE_SCALE_NONE) { 3248 DRM_DEBUG_KMS("no scaling not supported\n"); 3249 return -EINVAL; 3250 } 3251 3252 if (intel_connector->panel.fitting_mode == val) { 3253 /* the eDP scaling property is not changed */ 3254 return 0; 3255 } 3256 intel_connector->panel.fitting_mode = val; 3257 3258 goto done; 3259 } 3260 3261 return -EINVAL; 3262 3263done: 3264 if (intel_encoder->base.crtc) 3265 intel_crtc_restore_mode(intel_encoder->base.crtc); 3266 3267 return 0; 3268} 3269 3270static void 3271intel_dp_connector_destroy(struct drm_connector *connector) 3272{ 3273 struct intel_connector *intel_connector = to_intel_connector(connector); 3274 3275 if (!IS_ERR_OR_NULL(intel_connector->edid)) 3276 kfree(intel_connector->edid); 3277 3278 /* Can't call is_edp() since the encoder may have been destroyed 3279 * already. */ 3280 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) 3281 intel_panel_fini(&intel_connector->panel); 3282 3283 drm_connector_cleanup(connector); 3284 kfree(connector); 3285} 3286 3287void intel_dp_encoder_destroy(struct drm_encoder *encoder) 3288{ 3289 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); 3290 struct intel_dp *intel_dp = &intel_dig_port->dp; 3291 struct drm_device *dev = intel_dp_to_dev(intel_dp); 3292 3293 i2c_del_adapter(&intel_dp->adapter); 3294 drm_encoder_cleanup(encoder); 3295 if (is_edp(intel_dp)) { 3296 cancel_delayed_work_sync(&intel_dp->panel_vdd_work); 3297 mutex_lock(&dev->mode_config.mutex); 3298 ironlake_panel_vdd_off_sync(intel_dp); 3299 mutex_unlock(&dev->mode_config.mutex); 3300 } 3301 kfree(intel_dig_port); 3302} 3303 3304static const struct drm_connector_funcs intel_dp_connector_funcs = { 3305 .dpms = intel_connector_dpms, 3306 .detect = intel_dp_detect, 3307 .fill_modes = drm_helper_probe_single_connector_modes, 3308 .set_property = intel_dp_set_property, 3309 .destroy = intel_dp_connector_destroy, 3310}; 3311 3312static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = { 3313 .get_modes = intel_dp_get_modes, 3314 .mode_valid = intel_dp_mode_valid, 3315 .best_encoder = intel_best_encoder, 3316}; 3317 3318static const struct drm_encoder_funcs intel_dp_enc_funcs = { 3319 .destroy = intel_dp_encoder_destroy, 3320}; 3321 3322static void 3323intel_dp_hot_plug(struct intel_encoder *intel_encoder) 3324{ 3325 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base); 3326 3327 intel_dp_check_link_status(intel_dp); 3328} 3329 3330/* Return which DP Port should be selected for Transcoder DP control */ 3331int 3332intel_trans_dp_port_sel(struct drm_crtc *crtc) 3333{ 3334 struct drm_device *dev = crtc->dev; 3335 struct intel_encoder *intel_encoder; 3336 struct intel_dp *intel_dp; 3337 3338 for_each_encoder_on_crtc(dev, crtc, intel_encoder) { 3339 intel_dp = enc_to_intel_dp(&intel_encoder->base); 3340 3341 if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT || 3342 intel_encoder->type == INTEL_OUTPUT_EDP) 3343 return intel_dp->output_reg; 3344 } 3345 3346 return -1; 3347} 3348 3349/* check the VBT to see whether the eDP is on DP-D port */ 3350bool intel_dp_is_edp(struct drm_device *dev, enum port port) 3351{ 3352 struct drm_i915_private *dev_priv = dev->dev_private; 3353 union child_device_config *p_child; 3354 int i; 3355 static const short port_mapping[] = { 3356 [PORT_B] = PORT_IDPB, 3357 [PORT_C] = PORT_IDPC, 3358 [PORT_D] = PORT_IDPD, 3359 }; 3360 3361 if (port == PORT_A) 3362 return true; 3363 3364 if (!dev_priv->vbt.child_dev_num) 3365 return false; 3366 3367 for (i = 0; i < dev_priv->vbt.child_dev_num; i++) { 3368 p_child = dev_priv->vbt.child_dev + i; 3369 3370 if (p_child->common.dvo_port == port_mapping[port] && 3371 (p_child->common.device_type & DEVICE_TYPE_eDP_BITS) == 3372 (DEVICE_TYPE_eDP & DEVICE_TYPE_eDP_BITS)) 3373 return true; 3374 } 3375 return false; 3376} 3377 3378static void 3379intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector) 3380{ 3381 struct intel_connector *intel_connector = to_intel_connector(connector); 3382 3383 intel_attach_force_audio_property(connector); 3384 intel_attach_broadcast_rgb_property(connector); 3385 intel_dp->color_range_auto = true; 3386 3387 if (is_edp(intel_dp)) { 3388 drm_mode_create_scaling_mode_property(connector->dev); 3389 drm_object_attach_property( 3390 &connector->base, 3391 connector->dev->mode_config.scaling_mode_property, 3392 DRM_MODE_SCALE_ASPECT); 3393 intel_connector->panel.fitting_mode = DRM_MODE_SCALE_ASPECT; 3394 } 3395} 3396 3397static void 3398intel_dp_init_panel_power_sequencer(struct drm_device *dev, 3399 struct intel_dp *intel_dp, 3400 struct edp_power_seq *out) 3401{ 3402 struct drm_i915_private *dev_priv = dev->dev_private; 3403 struct edp_power_seq cur, vbt, spec, final; 3404 u32 pp_on, pp_off, pp_div, pp; 3405 int pp_ctrl_reg, pp_on_reg, pp_off_reg, pp_div_reg; 3406 3407 if (HAS_PCH_SPLIT(dev)) { 3408 pp_ctrl_reg = PCH_PP_CONTROL; 3409 pp_on_reg = PCH_PP_ON_DELAYS; 3410 pp_off_reg = PCH_PP_OFF_DELAYS; 3411 pp_div_reg = PCH_PP_DIVISOR; 3412 } else { 3413 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp); 3414 3415 pp_ctrl_reg = VLV_PIPE_PP_CONTROL(pipe); 3416 pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe); 3417 pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe); 3418 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe); 3419 } 3420 3421 /* Workaround: Need to write PP_CONTROL with the unlock key as 3422 * the very first thing. */ 3423 pp = ironlake_get_pp_control(intel_dp); 3424 I915_WRITE(pp_ctrl_reg, pp); 3425 3426 pp_on = I915_READ(pp_on_reg); 3427 pp_off = I915_READ(pp_off_reg); 3428 pp_div = I915_READ(pp_div_reg); 3429 3430 /* Pull timing values out of registers */ 3431 cur.t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >> 3432 PANEL_POWER_UP_DELAY_SHIFT; 3433 3434 cur.t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >> 3435 PANEL_LIGHT_ON_DELAY_SHIFT; 3436 3437 cur.t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >> 3438 PANEL_LIGHT_OFF_DELAY_SHIFT; 3439 3440 cur.t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >> 3441 PANEL_POWER_DOWN_DELAY_SHIFT; 3442 3443 cur.t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >> 3444 PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000; 3445 3446 DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n", 3447 cur.t1_t3, cur.t8, cur.t9, cur.t10, cur.t11_t12); 3448 3449 vbt = dev_priv->vbt.edp_pps; 3450 3451 /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of 3452 * our hw here, which are all in 100usec. */ 3453 spec.t1_t3 = 210 * 10; 3454 spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */ 3455 spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */ 3456 spec.t10 = 500 * 10; 3457 /* This one is special and actually in units of 100ms, but zero 3458 * based in the hw (so we need to add 100 ms). But the sw vbt 3459 * table multiplies it with 1000 to make it in units of 100usec, 3460 * too. */ 3461 spec.t11_t12 = (510 + 100) * 10; 3462 3463 DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n", 3464 vbt.t1_t3, vbt.t8, vbt.t9, vbt.t10, vbt.t11_t12); 3465 3466 /* Use the max of the register settings and vbt. If both are 3467 * unset, fall back to the spec limits. */ 3468#define assign_final(field) final.field = (max(cur.field, vbt.field) == 0 ? \ 3469 spec.field : \ 3470 max(cur.field, vbt.field)) 3471 assign_final(t1_t3); 3472 assign_final(t8); 3473 assign_final(t9); 3474 assign_final(t10); 3475 assign_final(t11_t12); 3476#undef assign_final 3477 3478#define get_delay(field) (DIV_ROUND_UP(final.field, 10)) 3479 intel_dp->panel_power_up_delay = get_delay(t1_t3); 3480 intel_dp->backlight_on_delay = get_delay(t8); 3481 intel_dp->backlight_off_delay = get_delay(t9); 3482 intel_dp->panel_power_down_delay = get_delay(t10); 3483 intel_dp->panel_power_cycle_delay = get_delay(t11_t12); 3484#undef get_delay 3485 3486 DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n", 3487 intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay, 3488 intel_dp->panel_power_cycle_delay); 3489 3490 DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n", 3491 intel_dp->backlight_on_delay, intel_dp->backlight_off_delay); 3492 3493 if (out) 3494 *out = final; 3495} 3496 3497static void 3498intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev, 3499 struct intel_dp *intel_dp, 3500 struct edp_power_seq *seq) 3501{ 3502 struct drm_i915_private *dev_priv = dev->dev_private; 3503 u32 pp_on, pp_off, pp_div, port_sel = 0; 3504 int div = HAS_PCH_SPLIT(dev) ? intel_pch_rawclk(dev) : intel_hrawclk(dev); 3505 int pp_on_reg, pp_off_reg, pp_div_reg; 3506 3507 if (HAS_PCH_SPLIT(dev)) { 3508 pp_on_reg = PCH_PP_ON_DELAYS; 3509 pp_off_reg = PCH_PP_OFF_DELAYS; 3510 pp_div_reg = PCH_PP_DIVISOR; 3511 } else { 3512 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp); 3513 3514 pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe); 3515 pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe); 3516 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe); 3517 } 3518 3519 /* And finally store the new values in the power sequencer. */ 3520 pp_on = (seq->t1_t3 << PANEL_POWER_UP_DELAY_SHIFT) | 3521 (seq->t8 << PANEL_LIGHT_ON_DELAY_SHIFT); 3522 pp_off = (seq->t9 << PANEL_LIGHT_OFF_DELAY_SHIFT) | 3523 (seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT); 3524 /* Compute the divisor for the pp clock, simply match the Bspec 3525 * formula. */ 3526 pp_div = ((100 * div)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT; 3527 pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000) 3528 << PANEL_POWER_CYCLE_DELAY_SHIFT); 3529 3530 /* Haswell doesn't have any port selection bits for the panel 3531 * power sequencer any more. */ 3532 if (IS_VALLEYVIEW(dev)) { 3533 if (dp_to_dig_port(intel_dp)->port == PORT_B) 3534 port_sel = PANEL_PORT_SELECT_DPB_VLV; 3535 else 3536 port_sel = PANEL_PORT_SELECT_DPC_VLV; 3537 } else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) { 3538 if (dp_to_dig_port(intel_dp)->port == PORT_A) 3539 port_sel = PANEL_PORT_SELECT_DPA; 3540 else 3541 port_sel = PANEL_PORT_SELECT_DPD; 3542 } 3543 3544 pp_on |= port_sel; 3545 3546 I915_WRITE(pp_on_reg, pp_on); 3547 I915_WRITE(pp_off_reg, pp_off); 3548 I915_WRITE(pp_div_reg, pp_div); 3549 3550 DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n", 3551 I915_READ(pp_on_reg), 3552 I915_READ(pp_off_reg), 3553 I915_READ(pp_div_reg)); 3554} 3555 3556static bool intel_edp_init_connector(struct intel_dp *intel_dp, 3557 struct intel_connector *intel_connector) 3558{ 3559 struct drm_connector *connector = &intel_connector->base; 3560 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 3561 struct drm_device *dev = intel_dig_port->base.base.dev; 3562 struct drm_i915_private *dev_priv = dev->dev_private; 3563 struct drm_display_mode *fixed_mode = NULL; 3564 struct edp_power_seq power_seq = { 0 }; 3565 bool has_dpcd; 3566 struct drm_display_mode *scan; 3567 struct edid *edid; 3568 3569 if (!is_edp(intel_dp)) 3570 return true; 3571 3572 intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq); 3573 3574 /* Cache DPCD and EDID for edp. */ 3575 ironlake_edp_panel_vdd_on(intel_dp); 3576 has_dpcd = intel_dp_get_dpcd(intel_dp); 3577 ironlake_edp_panel_vdd_off(intel_dp, false); 3578 3579 if (has_dpcd) { 3580 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) 3581 dev_priv->no_aux_handshake = 3582 intel_dp->dpcd[DP_MAX_DOWNSPREAD] & 3583 DP_NO_AUX_HANDSHAKE_LINK_TRAINING; 3584 } else { 3585 /* if this fails, presume the device is a ghost */ 3586 DRM_INFO("failed to retrieve link info, disabling eDP\n"); 3587 return false; 3588 } 3589 3590 /* We now know it's not a ghost, init power sequence regs. */ 3591 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp, 3592 &power_seq); 3593 3594 edid = drm_get_edid(connector, &intel_dp->adapter); 3595 if (edid) { 3596 if (drm_add_edid_modes(connector, edid)) { 3597 drm_mode_connector_update_edid_property(connector, 3598 edid); 3599 drm_edid_to_eld(connector, edid); 3600 } else { 3601 kfree(edid); 3602 edid = ERR_PTR(-EINVAL); 3603 } 3604 } else { 3605 edid = ERR_PTR(-ENOENT); 3606 } 3607 intel_connector->edid = edid; 3608 3609 /* prefer fixed mode from EDID if available */ 3610 list_for_each_entry(scan, &connector->probed_modes, head) { 3611 if ((scan->type & DRM_MODE_TYPE_PREFERRED)) { 3612 fixed_mode = drm_mode_duplicate(dev, scan); 3613 break; 3614 } 3615 } 3616 3617 /* fallback to VBT if available for eDP */ 3618 if (!fixed_mode && dev_priv->vbt.lfp_lvds_vbt_mode) { 3619 fixed_mode = drm_mode_duplicate(dev, 3620 dev_priv->vbt.lfp_lvds_vbt_mode); 3621 if (fixed_mode) 3622 fixed_mode->type |= DRM_MODE_TYPE_PREFERRED; 3623 } 3624 3625 intel_panel_init(&intel_connector->panel, fixed_mode); 3626 intel_panel_setup_backlight(connector); 3627 3628 return true; 3629} 3630 3631bool 3632intel_dp_init_connector(struct intel_digital_port *intel_dig_port, 3633 struct intel_connector *intel_connector) 3634{ 3635 struct drm_connector *connector = &intel_connector->base; 3636 struct intel_dp *intel_dp = &intel_dig_port->dp; 3637 struct intel_encoder *intel_encoder = &intel_dig_port->base; 3638 struct drm_device *dev = intel_encoder->base.dev; 3639 struct drm_i915_private *dev_priv = dev->dev_private; 3640 enum port port = intel_dig_port->port; 3641 const char *name = NULL; 3642 int type, error; 3643 3644 /* Preserve the current hw state. */ 3645 intel_dp->DP = I915_READ(intel_dp->output_reg); 3646 intel_dp->attached_connector = intel_connector; 3647 3648 if (intel_dp_is_edp(dev, port)) 3649 type = DRM_MODE_CONNECTOR_eDP; 3650 else 3651 type = DRM_MODE_CONNECTOR_DisplayPort; 3652 3653 /* 3654 * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but 3655 * for DP the encoder type can be set by the caller to 3656 * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it. 3657 */ 3658 if (type == DRM_MODE_CONNECTOR_eDP) 3659 intel_encoder->type = INTEL_OUTPUT_EDP; 3660 3661 DRM_DEBUG_KMS("Adding %s connector on port %c\n", 3662 type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP", 3663 port_name(port)); 3664 3665 drm_connector_init(dev, connector, &intel_dp_connector_funcs, type); 3666 drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs); 3667 3668 connector->interlace_allowed = true; 3669 connector->doublescan_allowed = 0; 3670 3671 INIT_DELAYED_WORK(&intel_dp->panel_vdd_work, 3672 ironlake_panel_vdd_work); 3673 3674 intel_connector_attach_encoder(intel_connector, intel_encoder); 3675 drm_sysfs_connector_add(connector); 3676 3677 if (HAS_DDI(dev)) 3678 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state; 3679 else 3680 intel_connector->get_hw_state = intel_connector_get_hw_state; 3681 3682 intel_dp->aux_ch_ctl_reg = intel_dp->output_reg + 0x10; 3683 if (HAS_DDI(dev)) { 3684 switch (intel_dig_port->port) { 3685 case PORT_A: 3686 intel_dp->aux_ch_ctl_reg = DPA_AUX_CH_CTL; 3687 break; 3688 case PORT_B: 3689 intel_dp->aux_ch_ctl_reg = PCH_DPB_AUX_CH_CTL; 3690 break; 3691 case PORT_C: 3692 intel_dp->aux_ch_ctl_reg = PCH_DPC_AUX_CH_CTL; 3693 break; 3694 case PORT_D: 3695 intel_dp->aux_ch_ctl_reg = PCH_DPD_AUX_CH_CTL; 3696 break; 3697 default: 3698 BUG(); 3699 } 3700 } 3701 3702 /* Set up the DDC bus. */ 3703 switch (port) { 3704 case PORT_A: 3705 intel_encoder->hpd_pin = HPD_PORT_A; 3706 name = "DPDDC-A"; 3707 break; 3708 case PORT_B: 3709 intel_encoder->hpd_pin = HPD_PORT_B; 3710 name = "DPDDC-B"; 3711 break; 3712 case PORT_C: 3713 intel_encoder->hpd_pin = HPD_PORT_C; 3714 name = "DPDDC-C"; 3715 break; 3716 case PORT_D: 3717 intel_encoder->hpd_pin = HPD_PORT_D; 3718 name = "DPDDC-D"; 3719 break; 3720 default: 3721 BUG(); 3722 } 3723 3724 error = intel_dp_i2c_init(intel_dp, intel_connector, name); 3725 WARN(error, "intel_dp_i2c_init failed with error %d for port %c\n", 3726 error, port_name(port)); 3727 3728 intel_dp->psr_setup_done = false; 3729 3730 if (!intel_edp_init_connector(intel_dp, intel_connector)) { 3731 i2c_del_adapter(&intel_dp->adapter); 3732 if (is_edp(intel_dp)) { 3733 cancel_delayed_work_sync(&intel_dp->panel_vdd_work); 3734 mutex_lock(&dev->mode_config.mutex); 3735 ironlake_panel_vdd_off_sync(intel_dp); 3736 mutex_unlock(&dev->mode_config.mutex); 3737 } 3738 drm_sysfs_connector_remove(connector); 3739 drm_connector_cleanup(connector); 3740 return false; 3741 } 3742 3743 intel_dp_add_properties(intel_dp, connector); 3744 3745 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written 3746 * 0xd. Failure to do so will result in spurious interrupts being 3747 * generated on the port when a cable is not attached. 3748 */ 3749 if (IS_G4X(dev) && !IS_GM45(dev)) { 3750 u32 temp = I915_READ(PEG_BAND_GAP_DATA); 3751 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd); 3752 } 3753 3754 return true; 3755} 3756 3757void 3758intel_dp_init(struct drm_device *dev, int output_reg, enum port port) 3759{ 3760 struct intel_digital_port *intel_dig_port; 3761 struct intel_encoder *intel_encoder; 3762 struct drm_encoder *encoder; 3763 struct intel_connector *intel_connector; 3764 3765 intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL); 3766 if (!intel_dig_port) 3767 return; 3768 3769 intel_connector = kzalloc(sizeof(*intel_connector), GFP_KERNEL); 3770 if (!intel_connector) { 3771 kfree(intel_dig_port); 3772 return; 3773 } 3774 3775 intel_encoder = &intel_dig_port->base; 3776 encoder = &intel_encoder->base; 3777 3778 drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs, 3779 DRM_MODE_ENCODER_TMDS); 3780 3781 intel_encoder->compute_config = intel_dp_compute_config; 3782 intel_encoder->mode_set = intel_dp_mode_set; 3783 intel_encoder->disable = intel_disable_dp; 3784 intel_encoder->post_disable = intel_post_disable_dp; 3785 intel_encoder->get_hw_state = intel_dp_get_hw_state; 3786 intel_encoder->get_config = intel_dp_get_config; 3787 if (IS_VALLEYVIEW(dev)) { 3788 intel_encoder->pre_pll_enable = vlv_dp_pre_pll_enable; 3789 intel_encoder->pre_enable = vlv_pre_enable_dp; 3790 intel_encoder->enable = vlv_enable_dp; 3791 } else { 3792 intel_encoder->pre_enable = g4x_pre_enable_dp; 3793 intel_encoder->enable = g4x_enable_dp; 3794 } 3795 3796 intel_dig_port->port = port; 3797 intel_dig_port->dp.output_reg = output_reg; 3798 3799 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT; 3800 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2); 3801 intel_encoder->cloneable = false; 3802 intel_encoder->hot_plug = intel_dp_hot_plug; 3803 3804 if (!intel_dp_init_connector(intel_dig_port, intel_connector)) { 3805 drm_encoder_cleanup(encoder); 3806 kfree(intel_dig_port); 3807 kfree(intel_connector); 3808 } 3809} 3810